DMA_RAM_DAC - won't compile

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won't compile

stm32f30x.h@0:b079fa4ed182, 2016-11-02 (annotated)

Committer:: richardv
Date:: Wed Nov 02 23:50:52 2016 +0000
Revision:: 0:b079fa4ed182

DMA RAM DAC

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User	Revision	Line number	New contents of line
richardv	0:b079fa4ed182	1	/**
richardv	0:b079fa4ed182	2	******************************************************************************
richardv	0:b079fa4ed182	3	* @file stm32f30x.h
richardv	0:b079fa4ed182	4	* @author MCD Application Team
richardv	0:b079fa4ed182	5	* @version V1.1.1
richardv	0:b079fa4ed182	6	* @date 28-March-2014
richardv	0:b079fa4ed182	7	* @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
richardv	0:b079fa4ed182	8	* This file contains all the peripheral registers definitions, bits
richardv	0:b079fa4ed182	9	* definitions and memory mapping for STM32F30x devices.
richardv	0:b079fa4ed182	10	*
richardv	0:b079fa4ed182	11	* The file is the unique include file that the application programmer
richardv	0:b079fa4ed182	12	* is using in the C source code, usually in main.c. This file contains:
richardv	0:b079fa4ed182	13	* - Configuration section that allows to select:
richardv	0:b079fa4ed182	14	* - The device used in the target application
richardv	0:b079fa4ed182	15	* - To use or not the peripherals drivers in application code(i.e.
richardv	0:b079fa4ed182	16	* code will be based on direct access to peripherals registers
richardv	0:b079fa4ed182	17	* rather than drivers API), this option is controlled by
richardv	0:b079fa4ed182	18	* "#define USE_STDPERIPH_DRIVER"
richardv	0:b079fa4ed182	19	* - To change few application-specific parameters such as the HSE
richardv	0:b079fa4ed182	20	* crystal frequency
richardv	0:b079fa4ed182	21	* - Data structures and the address mapping for all peripherals
richardv	0:b079fa4ed182	22	* - Peripheral registers declarations and bits definition
richardv	0:b079fa4ed182	23	* - Macros to access peripheral registers hardware
richardv	0:b079fa4ed182	24	*
richardv	0:b079fa4ed182	25	******************************************************************************
richardv	0:b079fa4ed182	26	* @attention
richardv	0:b079fa4ed182	27	*
richardv	0:b079fa4ed182	28	* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
richardv	0:b079fa4ed182	29	*
richardv	0:b079fa4ed182	30	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
richardv	0:b079fa4ed182	31	* You may not use this file except in compliance with the License.
richardv	0:b079fa4ed182	32	* You may obtain a copy of the License at:
richardv	0:b079fa4ed182	33	*
richardv	0:b079fa4ed182	34	* http://www.st.com/software_license_agreement_liberty_v2
richardv	0:b079fa4ed182	35	*
richardv	0:b079fa4ed182	36	* Unless required by applicable law or agreed to in writing, software
richardv	0:b079fa4ed182	37	* distributed under the License is distributed on an "AS IS" BASIS,
richardv	0:b079fa4ed182	38	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
richardv	0:b079fa4ed182	39	* See the License for the specific language governing permissions and
richardv	0:b079fa4ed182	40	* limitations under the License.
richardv	0:b079fa4ed182	41	*
richardv	0:b079fa4ed182	42	******************************************************************************
richardv	0:b079fa4ed182	43	*/
richardv	0:b079fa4ed182	44
richardv	0:b079fa4ed182	45	/** @addtogroup CMSIS
richardv	0:b079fa4ed182	46	* @{
richardv	0:b079fa4ed182	47	*/
richardv	0:b079fa4ed182	48
richardv	0:b079fa4ed182	49	/** @addtogroup stm32f30x
richardv	0:b079fa4ed182	50	* @{
richardv	0:b079fa4ed182	51	*/
richardv	0:b079fa4ed182	52
richardv	0:b079fa4ed182	53	#ifndef __STM32F30x_H
richardv	0:b079fa4ed182	54	#define __STM32F30x_H
richardv	0:b079fa4ed182	55
richardv	0:b079fa4ed182	56	#ifdef __cplusplus
richardv	0:b079fa4ed182	57	extern "C" {
richardv	0:b079fa4ed182	58	#endif /* __cplusplus */
richardv	0:b079fa4ed182	59
richardv	0:b079fa4ed182	60	/** @addtogroup Library_configuration_section
richardv	0:b079fa4ed182	61	* @{
richardv	0:b079fa4ed182	62	*/
richardv	0:b079fa4ed182	63
richardv	0:b079fa4ed182	64	/* Uncomment the line below according to the target STM32 device used in your
richardv	0:b079fa4ed182	65	application
richardv	0:b079fa4ed182	66	*/
richardv	0:b079fa4ed182	67
richardv	0:b079fa4ed182	68	#if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F303x8) && !defined (STM32F301x8) && !defined (STM32F302x8)
richardv	0:b079fa4ed182	69	/* #define STM32F303xC / /!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */
richardv	0:b079fa4ed182	70	#define STM32F334x8 /!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices /
richardv	0:b079fa4ed182	71	/* #define STM32F302x8 / /!< STM32F302K4, STM32F302K6, STM32F302K8, STM32F302C4, STM32F302C6, STM32F302C8,
richardv	0:b079fa4ed182	72	STM32F302R4, STM32F302R6 and STM32F302R8 Devices */
richardv	0:b079fa4ed182	73	#endif
richardv	0:b079fa4ed182	74
richardv	0:b079fa4ed182	75	/* Tip: To avoid modifying this file each time you need to switch between these
richardv	0:b079fa4ed182	76	devices, you can define the device in your toolchain compiler preprocessor.
richardv	0:b079fa4ed182	77	*/
richardv	0:b079fa4ed182	78
richardv	0:b079fa4ed182	79	/* Old STM32F30X definition, maintained for legacy purpose */
richardv	0:b079fa4ed182	80	#if defined(STM32F30X)
richardv	0:b079fa4ed182	81	#define STM32F303xC
richardv	0:b079fa4ed182	82	#endif /* STM32F30X */
richardv	0:b079fa4ed182	83
richardv	0:b079fa4ed182	84	#if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F302x8)
richardv	0:b079fa4ed182	85	#error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)"
richardv	0:b079fa4ed182	86	#endif
richardv	0:b079fa4ed182	87
richardv	0:b079fa4ed182	88	#if !defined (USE_STDPERIPH_DRIVER)
richardv	0:b079fa4ed182	89	/**
richardv	0:b079fa4ed182	90	* @brief Comment the line below if you will not use the peripherals drivers.
richardv	0:b079fa4ed182	91	In this case, these drivers will not be included and the application code will
richardv	0:b079fa4ed182	92	be based on direct access to peripherals registers
richardv	0:b079fa4ed182	93	*/
richardv	0:b079fa4ed182	94	/* #define USE_STDPERIPH_DRIVER */
richardv	0:b079fa4ed182	95	#endif /* USE_STDPERIPH_DRIVER */
richardv	0:b079fa4ed182	96
richardv	0:b079fa4ed182	97	/**
richardv	0:b079fa4ed182	98	* @brief In the following line adjust the value of External High Speed oscillator (HSE)
richardv	0:b079fa4ed182	99	used in your application
richardv	0:b079fa4ed182	100
richardv	0:b079fa4ed182	101	Tip: To avoid modifying this file each time you need to use different HSE, you
richardv	0:b079fa4ed182	102	can define the HSE value in your toolchain compiler preprocessor.
richardv	0:b079fa4ed182	103	*/
richardv	0:b079fa4ed182	104	#if !defined (HSE_VALUE)
richardv	0:b079fa4ed182	105	#define HSE_VALUE ((uint32_t)8000000) /!< Value of the External oscillator in Hz /
richardv	0:b079fa4ed182	106	#endif /* HSE_VALUE */
richardv	0:b079fa4ed182	107
richardv	0:b079fa4ed182	108	/**
richardv	0:b079fa4ed182	109	* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
richardv	0:b079fa4ed182	110	Timeout value
richardv	0:b079fa4ed182	111	*/
richardv	0:b079fa4ed182	112	#if !defined (HSE_STARTUP_TIMEOUT)
richardv	0:b079fa4ed182	113	#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /!< Time out for HSE start up /
richardv	0:b079fa4ed182	114	#endif /* HSE_STARTUP_TIMEOUT */
richardv	0:b079fa4ed182	115
richardv	0:b079fa4ed182	116	/**
richardv	0:b079fa4ed182	117	* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
richardv	0:b079fa4ed182	118	Timeout value
richardv	0:b079fa4ed182	119	*/
richardv	0:b079fa4ed182	120	#if !defined (HSI_STARTUP_TIMEOUT)
richardv	0:b079fa4ed182	121	#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /!< Time out for HSI start up /
richardv	0:b079fa4ed182	122	#endif /* HSI_STARTUP_TIMEOUT */
richardv	0:b079fa4ed182	123
richardv	0:b079fa4ed182	124	#if !defined (HSI_VALUE)
richardv	0:b079fa4ed182	125	#define HSI_VALUE ((uint32_t)8000000)
richardv	0:b079fa4ed182	126	#endif /* HSI_VALUE / /!< Value of the Internal High Speed oscillator in Hz.
richardv	0:b079fa4ed182	127	The real value may vary depending on the variations
richardv	0:b079fa4ed182	128	in voltage and temperature. */
richardv	0:b079fa4ed182	129	#if !defined (LSI_VALUE)
richardv	0:b079fa4ed182	130	#define LSI_VALUE ((uint32_t)40000)
richardv	0:b079fa4ed182	131	#endif /* LSI_VALUE / /!< Value of the Internal Low Speed oscillator in Hz
richardv	0:b079fa4ed182	132	The real value may vary depending on the variations
richardv	0:b079fa4ed182	133	in voltage and temperature. */
richardv	0:b079fa4ed182	134	#if !defined (LSE_VALUE)
richardv	0:b079fa4ed182	135	#define LSE_VALUE ((uint32_t)32768) /!< Value of the External Low Speed oscillator in Hz /
richardv	0:b079fa4ed182	136	#endif /* LSE_VALUE */
richardv	0:b079fa4ed182	137
richardv	0:b079fa4ed182	138
richardv	0:b079fa4ed182	139	/**
richardv	0:b079fa4ed182	140	* @brief STM32F30x Standard Peripherals Library version number V1.1.0
richardv	0:b079fa4ed182	141	*/
richardv	0:b079fa4ed182	142	#define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /!< [31:24] main version /
richardv	0:b079fa4ed182	143	#define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x01) /!< [23:16] sub1 version /
richardv	0:b079fa4ed182	144	#define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /!< [15:8] sub2 version /
richardv	0:b079fa4ed182	145	#define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /!< [7:0] release candidate /
richardv	0:b079fa4ed182	146	#define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\
richardv	0:b079fa4ed182	147	\|(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\
richardv	0:b079fa4ed182	148	\|(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\
richardv	0:b079fa4ed182	149	\|(__STM32F30X_STDPERIPH_VERSION_RC))
richardv	0:b079fa4ed182	150
richardv	0:b079fa4ed182	151	/**
richardv	0:b079fa4ed182	152	* @}
richardv	0:b079fa4ed182	153	*/
richardv	0:b079fa4ed182	154
richardv	0:b079fa4ed182	155	/** @addtogroup Configuration_section_for_CMSIS
richardv	0:b079fa4ed182	156	* @{
richardv	0:b079fa4ed182	157	*/
richardv	0:b079fa4ed182	158
richardv	0:b079fa4ed182	159	/**
richardv	0:b079fa4ed182	160	* @brief Configuration of the Cortex-M4 Processor and Core Peripherals
richardv	0:b079fa4ed182	161	*/
richardv	0:b079fa4ed182	162	#define __CM4_REV 0x0001 /!< Core revision r0p1 /
richardv	0:b079fa4ed182	163	#define __MPU_PRESENT 1 /!< STM32F30X provide an MPU /
richardv	0:b079fa4ed182	164	#define __NVIC_PRIO_BITS 4 /!< STM32F30X uses 4 Bits for the Priority Levels /
richardv	0:b079fa4ed182	165	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
richardv	0:b079fa4ed182	166	#define __FPU_PRESENT 1 /!< STM32F30X provide an FPU /
richardv	0:b079fa4ed182	167
richardv	0:b079fa4ed182	168
richardv	0:b079fa4ed182	169	/**
richardv	0:b079fa4ed182	170	* @brief STM32F30X Interrupt Number Definition, according to the selected device
richardv	0:b079fa4ed182	171	* in @ref Library_configuration_section
richardv	0:b079fa4ed182	172	*/
richardv	0:b079fa4ed182	173	typedef enum IRQn
richardv	0:b079fa4ed182	174	{
richardv	0:b079fa4ed182	175	/**** Cortex-M4 Processor Exceptions Numbers **************************************************************/
richardv	0:b079fa4ed182	176	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
richardv	0:b079fa4ed182	177	MemoryManagement_IRQn = -12, /!< 4 Cortex-M4 Memory Management Interrupt /
richardv	0:b079fa4ed182	178	BusFault_IRQn = -11, /!< 5 Cortex-M4 Bus Fault Interrupt /
richardv	0:b079fa4ed182	179	UsageFault_IRQn = -10, /!< 6 Cortex-M4 Usage Fault Interrupt /
richardv	0:b079fa4ed182	180	SVCall_IRQn = -5, /!< 11 Cortex-M4 SV Call Interrupt /
richardv	0:b079fa4ed182	181	DebugMonitor_IRQn = -4, /!< 12 Cortex-M4 Debug Monitor Interrupt /
richardv	0:b079fa4ed182	182	PendSV_IRQn = -2, /!< 14 Cortex-M4 Pend SV Interrupt /
richardv	0:b079fa4ed182	183	SysTick_IRQn = -1, /!< 15 Cortex-M4 System Tick Interrupt /
richardv	0:b079fa4ed182	184	/**** STM32 specific Interrupt Numbers ********************************************************************/
richardv	0:b079fa4ed182	185	#ifdef STM32F303xC
richardv	0:b079fa4ed182	186	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
richardv	0:b079fa4ed182	187	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
richardv	0:b079fa4ed182	188	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts /
richardv	0:b079fa4ed182	189	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 /
richardv	0:b079fa4ed182	190	FLASH_IRQn = 4, /!< FLASH global Interrupt /
richardv	0:b079fa4ed182	191	RCC_IRQn = 5, /!< RCC global Interrupt /
richardv	0:b079fa4ed182	192	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
richardv	0:b079fa4ed182	193	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
richardv	0:b079fa4ed182	194	EXTI2_TS_IRQn = 8, /!< EXTI Line2 Interrupt and Touch Sense Interrupt /
richardv	0:b079fa4ed182	195	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
richardv	0:b079fa4ed182	196	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
richardv	0:b079fa4ed182	197	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 Interrupt /
richardv	0:b079fa4ed182	198	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 Interrupt /
richardv	0:b079fa4ed182	199	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 Interrupt /
richardv	0:b079fa4ed182	200	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 Interrupt /
richardv	0:b079fa4ed182	201	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 Interrupt /
richardv	0:b079fa4ed182	202	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 Interrupt /
richardv	0:b079fa4ed182	203	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 Interrupt /
richardv	0:b079fa4ed182	204	ADC1_2_IRQn = 18, /!< ADC1 & ADC2 Interrupts /
richardv	0:b079fa4ed182	205	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
richardv	0:b079fa4ed182	206	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
richardv	0:b079fa4ed182	207	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
richardv	0:b079fa4ed182	208	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
richardv	0:b079fa4ed182	209	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
richardv	0:b079fa4ed182	210	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
richardv	0:b079fa4ed182	211	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
richardv	0:b079fa4ed182	212	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
richardv	0:b079fa4ed182	213	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
richardv	0:b079fa4ed182	214	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
richardv	0:b079fa4ed182	215	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
richardv	0:b079fa4ed182	216	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
richardv	0:b079fa4ed182	217	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
richardv	0:b079fa4ed182	218	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
richardv	0:b079fa4ed182	219	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
richardv	0:b079fa4ed182	220	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
richardv	0:b079fa4ed182	221	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
richardv	0:b079fa4ed182	222	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
richardv	0:b079fa4ed182	223	USART1_IRQn = 37, /!< USART1 global Interrupt /
richardv	0:b079fa4ed182	224	USART2_IRQn = 38, /!< USART2 global Interrupt /
richardv	0:b079fa4ed182	225	USART3_IRQn = 39, /!< USART3 global Interrupt /
richardv	0:b079fa4ed182	226	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
richardv	0:b079fa4ed182	227	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
richardv	0:b079fa4ed182	228	USBWakeUp_IRQn = 42, /!< USB Wakeup Interrupt /
richardv	0:b079fa4ed182	229	TIM8_BRK_IRQn = 43, /!< TIM8 Break Interrupt /
richardv	0:b079fa4ed182	230	TIM8_UP_IRQn = 44, /!< TIM8 Update Interrupt /
richardv	0:b079fa4ed182	231	TIM8_TRG_COM_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt /
richardv	0:b079fa4ed182	232	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
richardv	0:b079fa4ed182	233	ADC3_IRQn = 47, /!< ADC3 global Interrupt /
richardv	0:b079fa4ed182	234	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
richardv	0:b079fa4ed182	235	UART4_IRQn = 52, /!< UART4 global Interrupt /
richardv	0:b079fa4ed182	236	UART5_IRQn = 53, /!< UART5 global Interrupt /
richardv	0:b079fa4ed182	237	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
richardv	0:b079fa4ed182	238	TIM7_IRQn = 55, /!< TIM7 global Interrupt /
richardv	0:b079fa4ed182	239	DMA2_Channel1_IRQn = 56, /!< DMA2 Channel 1 global Interrupt /
richardv	0:b079fa4ed182	240	DMA2_Channel2_IRQn = 57, /!< DMA2 Channel 2 global Interrupt /
richardv	0:b079fa4ed182	241	DMA2_Channel3_IRQn = 58, /!< DMA2 Channel 3 global Interrupt /
richardv	0:b079fa4ed182	242	DMA2_Channel4_IRQn = 59, /!< DMA2 Channel 4 global Interrupt /
richardv	0:b079fa4ed182	243	DMA2_Channel5_IRQn = 60, /!< DMA2 Channel 5 global Interrupt /
richardv	0:b079fa4ed182	244	ADC4_IRQn = 61, /!< ADC4 global Interrupt /
richardv	0:b079fa4ed182	245	COMP1_2_3_IRQn = 64, /!< COMP1, COMP2 and COMP3 global Interrupt /
richardv	0:b079fa4ed182	246	COMP4_5_6_IRQn = 65, /!< COMP5, COMP6 and COMP4 global Interrupt /
richardv	0:b079fa4ed182	247	COMP7_IRQn = 66, /!< COMP7 global Interrupt /
richardv	0:b079fa4ed182	248	USB_HP_IRQn = 74, /!< USB High Priority global Interrupt remap /
richardv	0:b079fa4ed182	249	USB_LP_IRQn = 75, /!< USB Low Priority global Interrupt remap /
richardv	0:b079fa4ed182	250	USBWakeUp_RMP_IRQn = 76, /!< USB Wakeup Interrupt remap /
richardv	0:b079fa4ed182	251	FPU_IRQn = 81 /!< Floating point Interrupt /
richardv	0:b079fa4ed182	252	#endif /* STM32F303xC */
richardv	0:b079fa4ed182	253	#ifdef STM32F334x8
richardv	0:b079fa4ed182	254	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
richardv	0:b079fa4ed182	255	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
richardv	0:b079fa4ed182	256	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts /
richardv	0:b079fa4ed182	257	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 /
richardv	0:b079fa4ed182	258	FLASH_IRQn = 4, /!< FLASH global Interrupt /
richardv	0:b079fa4ed182	259	RCC_IRQn = 5, /!< RCC global Interrupt /
richardv	0:b079fa4ed182	260	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
richardv	0:b079fa4ed182	261	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
richardv	0:b079fa4ed182	262	EXTI2_TS_IRQn = 8, /!< EXTI Line2 Interrupt and Touch Sense Interrupt /
richardv	0:b079fa4ed182	263	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
richardv	0:b079fa4ed182	264	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
richardv	0:b079fa4ed182	265	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 Interrupt /
richardv	0:b079fa4ed182	266	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 Interrupt /
richardv	0:b079fa4ed182	267	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 Interrupt /
richardv	0:b079fa4ed182	268	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 Interrupt /
richardv	0:b079fa4ed182	269	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 Interrupt /
richardv	0:b079fa4ed182	270	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 Interrupt /
richardv	0:b079fa4ed182	271	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 Interrupt /
richardv	0:b079fa4ed182	272	ADC1_2_IRQn = 18, /!< ADC1 & ADC2 Interrupts /
richardv	0:b079fa4ed182	273	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupts /
richardv	0:b079fa4ed182	274	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupts /
richardv	0:b079fa4ed182	275	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
richardv	0:b079fa4ed182	276	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
richardv	0:b079fa4ed182	277	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
richardv	0:b079fa4ed182	278	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
richardv	0:b079fa4ed182	279	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
richardv	0:b079fa4ed182	280	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
richardv	0:b079fa4ed182	281	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
richardv	0:b079fa4ed182	282	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
richardv	0:b079fa4ed182	283	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
richardv	0:b079fa4ed182	284	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
richardv	0:b079fa4ed182	285	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
richardv	0:b079fa4ed182	286	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
richardv	0:b079fa4ed182	287	USART1_IRQn = 37, /!< USART1 global Interrupt /
richardv	0:b079fa4ed182	288	USART2_IRQn = 38, /!< USART2 global Interrupt /
richardv	0:b079fa4ed182	289	USART3_IRQn = 39, /!< USART3 global Interrupt /
richardv	0:b079fa4ed182	290	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
richardv	0:b079fa4ed182	291	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
richardv	0:b079fa4ed182	292	TIM6_DAC1_IRQn = 54, /!< TIM6 global and DAC1 underrun error interrupts /
richardv	0:b079fa4ed182	293	TIM7_DAC2_IRQn = 55, /!< TIM7 global and DAC2 underrun error Interrupt /
richardv	0:b079fa4ed182	294	COMP2_IRQn = 64, /!< COMP2 global Interrupt /
richardv	0:b079fa4ed182	295	COMP4_6_IRQn = 65, /!< COMP6 and COMP4 global Interrupt /
richardv	0:b079fa4ed182	296	HRTIM1_Master_IRQn = 67, /!< HRTIM Master Timer global Interrupts /
richardv	0:b079fa4ed182	297	HRTIM1_TIMA_IRQn = 68, /!< HRTIM Timer A global Interrupt /
richardv	0:b079fa4ed182	298	HRTIM1_TIMB_IRQn = 69, /!< HRTIM Timer B global Interrupt /
richardv	0:b079fa4ed182	299	HRTIM1_TIMC_IRQn = 70, /!< HRTIM Timer C global Interrupt /
richardv	0:b079fa4ed182	300	HRTIM1_TIMD_IRQn = 71, /!< HRTIM Timer D global Interrupt /
richardv	0:b079fa4ed182	301	HRTIM1_TIME_IRQn = 72, /!< HRTIM Timer E global Interrupt /
richardv	0:b079fa4ed182	302	HRTIM1_FLT_IRQn = 73, /!< HRTIM Fault global Interrupt /
richardv	0:b079fa4ed182	303	FPU_IRQn = 81 /!< Floating point Interrupt /
richardv	0:b079fa4ed182	304	#endif /* STM32F334x8 */
richardv	0:b079fa4ed182	305	#ifdef STM32F302x8
richardv	0:b079fa4ed182	306	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
richardv	0:b079fa4ed182	307	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
richardv	0:b079fa4ed182	308	TAMPER_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts /
richardv	0:b079fa4ed182	309	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI lines 20 /
richardv	0:b079fa4ed182	310	FLASH_IRQn = 4, /!< FLASH global Interrupt /
richardv	0:b079fa4ed182	311	RCC_IRQn = 5, /!< RCC global Interrupt /
richardv	0:b079fa4ed182	312	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
richardv	0:b079fa4ed182	313	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
richardv	0:b079fa4ed182	314	EXTI2_TS_IRQn = 8, /!< EXTI Line2 Interrupt and Touch Sense Interrupt /
richardv	0:b079fa4ed182	315	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
richardv	0:b079fa4ed182	316	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
richardv	0:b079fa4ed182	317	DMA1_Channel1_IRQn = 11, /!< DMA1 Channel 1 Interrupt /
richardv	0:b079fa4ed182	318	DMA1_Channel2_IRQn = 12, /!< DMA1 Channel 2 Interrupt /
richardv	0:b079fa4ed182	319	DMA1_Channel3_IRQn = 13, /!< DMA1 Channel 3 Interrupt /
richardv	0:b079fa4ed182	320	DMA1_Channel4_IRQn = 14, /!< DMA1 Channel 4 Interrupt /
richardv	0:b079fa4ed182	321	DMA1_Channel5_IRQn = 15, /!< DMA1 Channel 5 Interrupt /
richardv	0:b079fa4ed182	322	DMA1_Channel6_IRQn = 16, /!< DMA1 Channel 6 Interrupt /
richardv	0:b079fa4ed182	323	DMA1_Channel7_IRQn = 17, /!< DMA1 Channel 7 Interrupt /
richardv	0:b079fa4ed182	324	ADC1_IRQn = 18, /!< ADC1 Interrupts /
richardv	0:b079fa4ed182	325	USB_HP_CAN1_TX_IRQn = 19, /!< USB Device High Priority or CAN1 TX Interrupts /
richardv	0:b079fa4ed182	326	USB_LP_CAN1_RX0_IRQn = 20, /!< USB Device Low Priority or CAN1 RX0 Interrupts /
richardv	0:b079fa4ed182	327	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
richardv	0:b079fa4ed182	328	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
richardv	0:b079fa4ed182	329	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
richardv	0:b079fa4ed182	330	TIM1_BRK_TIM15_IRQn = 24, /!< TIM1 Break and TIM15 Interrupts /
richardv	0:b079fa4ed182	331	TIM1_UP_TIM16_IRQn = 25, /!< TIM1 Update and TIM16 Interrupts /
richardv	0:b079fa4ed182	332	TIM1_TRG_COM_TIM17_IRQn = 26, /!< TIM1 Trigger and Commutation and TIM17 Interrupt /
richardv	0:b079fa4ed182	333	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
richardv	0:b079fa4ed182	334	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
richardv	0:b079fa4ed182	335	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
richardv	0:b079fa4ed182	336	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
richardv	0:b079fa4ed182	337	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
richardv	0:b079fa4ed182	338	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
richardv	0:b079fa4ed182	339	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
richardv	0:b079fa4ed182	340	USART1_IRQn = 37, /!< USART1 global Interrupt /
richardv	0:b079fa4ed182	341	USART2_IRQn = 38, /!< USART2 global Interrupt /
richardv	0:b079fa4ed182	342	USART3_IRQn = 39, /!< USART3 global Interrupt /
richardv	0:b079fa4ed182	343	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
richardv	0:b079fa4ed182	344	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
richardv	0:b079fa4ed182	345	USBWakeUp_IRQn = 42, /!< USB Wakeup Interrupt /
richardv	0:b079fa4ed182	346	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
richardv	0:b079fa4ed182	347	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
richardv	0:b079fa4ed182	348	COMP2_IRQn = 64, /!< COMP2 global Interrupt /
richardv	0:b079fa4ed182	349	COMP4_6_IRQn = 65, /!< COMP5, COMP6 and COMP4 global Interrupt /
richardv	0:b079fa4ed182	350	COMP7_IRQn = 66, /!< COMP7 global Interrupt /
richardv	0:b079fa4ed182	351	I2C3_EV_IRQn = 72, /!< I2C3 Event Interrupt /
richardv	0:b079fa4ed182	352	I2C3_ER_IRQn = 73, /!< I2C3 Error Interrupt /
richardv	0:b079fa4ed182	353	USB_HP_IRQn = 74, /!< USB High Priority global Interrupt remap /
richardv	0:b079fa4ed182	354	USB_LP_IRQn = 75, /!< USB Low Priority global Interrupt remap /
richardv	0:b079fa4ed182	355	USBWakeUp_RMP_IRQn = 76, /!< USB Wakeup Interrupt remap /
richardv	0:b079fa4ed182	356	FPU_IRQn = 81 /!< Floating point Interrupt /
richardv	0:b079fa4ed182	357	#endif /* STM32F302x8 */
richardv	0:b079fa4ed182	358	} IRQn_Type;
richardv	0:b079fa4ed182	359
richardv	0:b079fa4ed182	360	/**
richardv	0:b079fa4ed182	361	* @}
richardv	0:b079fa4ed182	362	*/
richardv	0:b079fa4ed182	363
richardv	0:b079fa4ed182	364	#include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
richardv	0:b079fa4ed182	365	#include "system_stm32f30x.h" /* STM32F30x System Header */
richardv	0:b079fa4ed182	366	#include <stdint.h>
richardv	0:b079fa4ed182	367
richardv	0:b079fa4ed182	368	/** @addtogroup Exported_types
richardv	0:b079fa4ed182	369	* @{
richardv	0:b079fa4ed182	370	*/
richardv	0:b079fa4ed182	371	/!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) /
richardv	0:b079fa4ed182	372	typedef int32_t s32;
richardv	0:b079fa4ed182	373	typedef int16_t s16;
richardv	0:b079fa4ed182	374	typedef int8_t s8;
richardv	0:b079fa4ed182	375
richardv	0:b079fa4ed182	376	typedef const int32_t sc32; /!< Read Only /
richardv	0:b079fa4ed182	377	typedef const int16_t sc16; /!< Read Only /
richardv	0:b079fa4ed182	378	typedef const int8_t sc8; /!< Read Only /
richardv	0:b079fa4ed182	379
richardv	0:b079fa4ed182	380	typedef __IO int32_t vs32;
richardv	0:b079fa4ed182	381	typedef __IO int16_t vs16;
richardv	0:b079fa4ed182	382	typedef __IO int8_t vs8;
richardv	0:b079fa4ed182	383
richardv	0:b079fa4ed182	384	typedef __I int32_t vsc32; /!< Read Only /
richardv	0:b079fa4ed182	385	typedef __I int16_t vsc16; /!< Read Only /
richardv	0:b079fa4ed182	386	typedef __I int8_t vsc8; /!< Read Only /
richardv	0:b079fa4ed182	387
richardv	0:b079fa4ed182	388	typedef uint32_t u32;
richardv	0:b079fa4ed182	389	typedef uint16_t u16;
richardv	0:b079fa4ed182	390	typedef uint8_t u8;
richardv	0:b079fa4ed182	391
richardv	0:b079fa4ed182	392	typedef const uint32_t uc32; /!< Read Only /
richardv	0:b079fa4ed182	393	typedef const uint16_t uc16; /!< Read Only /
richardv	0:b079fa4ed182	394	typedef const uint8_t uc8; /!< Read Only /
richardv	0:b079fa4ed182	395
richardv	0:b079fa4ed182	396	typedef __IO uint32_t vu32;
richardv	0:b079fa4ed182	397	typedef __IO uint16_t vu16;
richardv	0:b079fa4ed182	398	typedef __IO uint8_t vu8;
richardv	0:b079fa4ed182	399
richardv	0:b079fa4ed182	400	typedef __I uint32_t vuc32; /!< Read Only /
richardv	0:b079fa4ed182	401	typedef __I uint16_t vuc16; /!< Read Only /
richardv	0:b079fa4ed182	402	typedef __I uint8_t vuc8; /!< Read Only /
richardv	0:b079fa4ed182	403
richardv	0:b079fa4ed182	404	typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
richardv	0:b079fa4ed182	405
richardv	0:b079fa4ed182	406	typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
richardv	0:b079fa4ed182	407	#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) \|\| ((STATE) == ENABLE))
richardv	0:b079fa4ed182	408
richardv	0:b079fa4ed182	409	typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
richardv	0:b079fa4ed182	410
richardv	0:b079fa4ed182	411	/**
richardv	0:b079fa4ed182	412	* @}
richardv	0:b079fa4ed182	413	*/
richardv	0:b079fa4ed182	414
richardv	0:b079fa4ed182	415	/** @addtogroup Peripheral_registers_structures
richardv	0:b079fa4ed182	416	* @{
richardv	0:b079fa4ed182	417	*/
richardv	0:b079fa4ed182	418
richardv	0:b079fa4ed182	419	/**
richardv	0:b079fa4ed182	420	* @brief Analog to Digital Converter
richardv	0:b079fa4ed182	421	*/
richardv	0:b079fa4ed182	422
richardv	0:b079fa4ed182	423	typedef struct
richardv	0:b079fa4ed182	424	{
richardv	0:b079fa4ed182	425	__IO uint32_t ISR; /!< ADC Interrupt and Status Register, Address offset: 0x00 /
richardv	0:b079fa4ed182	426	__IO uint32_t IER; /!< ADC Interrupt Enable Register, Address offset: 0x04 /
richardv	0:b079fa4ed182	427	__IO uint32_t CR; /!< ADC control register, Address offset: 0x08 /
richardv	0:b079fa4ed182	428	__IO uint32_t CFGR; /!< ADC Configuration register, Address offset: 0x0C /
richardv	0:b079fa4ed182	429	uint32_t RESERVED0; /!< Reserved, 0x010 /
richardv	0:b079fa4ed182	430	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x14 /
richardv	0:b079fa4ed182	431	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x18 /
richardv	0:b079fa4ed182	432	uint32_t RESERVED1; /!< Reserved, 0x01C /
richardv	0:b079fa4ed182	433	__IO uint32_t TR1; /!< ADC watchdog threshold register 1, Address offset: 0x20 /
richardv	0:b079fa4ed182	434	__IO uint32_t TR2; /!< ADC watchdog threshold register 2, Address offset: 0x24 /
richardv	0:b079fa4ed182	435	__IO uint32_t TR3; /!< ADC watchdog threshold register 3, Address offset: 0x28 /
richardv	0:b079fa4ed182	436	uint32_t RESERVED2; /!< Reserved, 0x02C /
richardv	0:b079fa4ed182	437	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x30 /
richardv	0:b079fa4ed182	438	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x34 /
richardv	0:b079fa4ed182	439	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x38 /
richardv	0:b079fa4ed182	440	__IO uint32_t SQR4; /!< ADC regular sequence register 4, Address offset: 0x3C /
richardv	0:b079fa4ed182	441	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x40 /
richardv	0:b079fa4ed182	442	uint32_t RESERVED3; /!< Reserved, 0x044 /
richardv	0:b079fa4ed182	443	uint32_t RESERVED4; /!< Reserved, 0x048 /
richardv	0:b079fa4ed182	444	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x4C /
richardv	0:b079fa4ed182	445	uint32_t RESERVED5[4]; /!< Reserved, 0x050 - 0x05C /
richardv	0:b079fa4ed182	446	__IO uint32_t OFR1; /!< ADC offset register 1, Address offset: 0x60 /
richardv	0:b079fa4ed182	447	__IO uint32_t OFR2; /!< ADC offset register 2, Address offset: 0x64 /
richardv	0:b079fa4ed182	448	__IO uint32_t OFR3; /!< ADC offset register 3, Address offset: 0x68 /
richardv	0:b079fa4ed182	449	__IO uint32_t OFR4; /!< ADC offset register 4, Address offset: 0x6C /
richardv	0:b079fa4ed182	450	uint32_t RESERVED6[4]; /!< Reserved, 0x070 - 0x07C /
richardv	0:b079fa4ed182	451	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x80 /
richardv	0:b079fa4ed182	452	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x84 /
richardv	0:b079fa4ed182	453	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x88 /
richardv	0:b079fa4ed182	454	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x8C /
richardv	0:b079fa4ed182	455	uint32_t RESERVED7[4]; /!< Reserved, 0x090 - 0x09C /
richardv	0:b079fa4ed182	456	__IO uint32_t AWD2CR; /!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 /
richardv	0:b079fa4ed182	457	__IO uint32_t AWD3CR; /!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 /
richardv	0:b079fa4ed182	458	uint32_t RESERVED8; /!< Reserved, 0x0A8 /
richardv	0:b079fa4ed182	459	uint32_t RESERVED9; /!< Reserved, 0x0AC /
richardv	0:b079fa4ed182	460	__IO uint32_t DIFSEL; /!< ADC Differential Mode Selection Register, Address offset: 0xB0 /
richardv	0:b079fa4ed182	461	__IO uint32_t CALFACT; /!< ADC Calibration Factors, Address offset: 0xB4 /
richardv	0:b079fa4ed182	462
richardv	0:b079fa4ed182	463	} ADC_TypeDef;
richardv	0:b079fa4ed182	464
richardv	0:b079fa4ed182	465	typedef struct
richardv	0:b079fa4ed182	466	{
richardv	0:b079fa4ed182	467	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 /
richardv	0:b079fa4ed182	468	uint32_t RESERVED; /!< Reserved, ADC1/3 base address + 0x304 /
richardv	0:b079fa4ed182	469	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1/3 base address + 0x308 /
richardv	0:b079fa4ed182	470	__IO uint32_t CDR; /*!< ADC common regular data register for dual
richardv	0:b079fa4ed182	471	modes, Address offset: ADC1/3 base address + 0x30A */
richardv	0:b079fa4ed182	472	} ADC_Common_TypeDef;
richardv	0:b079fa4ed182	473
richardv	0:b079fa4ed182	474
richardv	0:b079fa4ed182	475	/**
richardv	0:b079fa4ed182	476	* @brief Controller Area Network TxMailBox
richardv	0:b079fa4ed182	477	*/
richardv	0:b079fa4ed182	478	typedef struct
richardv	0:b079fa4ed182	479	{
richardv	0:b079fa4ed182	480	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
richardv	0:b079fa4ed182	481	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
richardv	0:b079fa4ed182	482	__IO uint32_t TDLR; /!< CAN mailbox data low register /
richardv	0:b079fa4ed182	483	__IO uint32_t TDHR; /!< CAN mailbox data high register /
richardv	0:b079fa4ed182	484	} CAN_TxMailBox_TypeDef;
richardv	0:b079fa4ed182	485
richardv	0:b079fa4ed182	486	/**
richardv	0:b079fa4ed182	487	* @brief Controller Area Network FIFOMailBox
richardv	0:b079fa4ed182	488	*/
richardv	0:b079fa4ed182	489	typedef struct
richardv	0:b079fa4ed182	490	{
richardv	0:b079fa4ed182	491	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
richardv	0:b079fa4ed182	492	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
richardv	0:b079fa4ed182	493	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
richardv	0:b079fa4ed182	494	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
richardv	0:b079fa4ed182	495	} CAN_FIFOMailBox_TypeDef;
richardv	0:b079fa4ed182	496
richardv	0:b079fa4ed182	497	/**
richardv	0:b079fa4ed182	498	* @brief Controller Area Network FilterRegister
richardv	0:b079fa4ed182	499	*/
richardv	0:b079fa4ed182	500	typedef struct
richardv	0:b079fa4ed182	501	{
richardv	0:b079fa4ed182	502	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
richardv	0:b079fa4ed182	503	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
richardv	0:b079fa4ed182	504	} CAN_FilterRegister_TypeDef;
richardv	0:b079fa4ed182	505
richardv	0:b079fa4ed182	506	/**
richardv	0:b079fa4ed182	507	* @brief Controller Area Network
richardv	0:b079fa4ed182	508	*/
richardv	0:b079fa4ed182	509	typedef struct
richardv	0:b079fa4ed182	510	{
richardv	0:b079fa4ed182	511	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
richardv	0:b079fa4ed182	512	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
richardv	0:b079fa4ed182	513	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
richardv	0:b079fa4ed182	514	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
richardv	0:b079fa4ed182	515	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
richardv	0:b079fa4ed182	516	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
richardv	0:b079fa4ed182	517	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
richardv	0:b079fa4ed182	518	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
richardv	0:b079fa4ed182	519	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
richardv	0:b079fa4ed182	520	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
richardv	0:b079fa4ed182	521	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
richardv	0:b079fa4ed182	522	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
richardv	0:b079fa4ed182	523	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
richardv	0:b079fa4ed182	524	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
richardv	0:b079fa4ed182	525	uint32_t RESERVED2; /!< Reserved, 0x208 /
richardv	0:b079fa4ed182	526	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
richardv	0:b079fa4ed182	527	uint32_t RESERVED3; /!< Reserved, 0x210 /
richardv	0:b079fa4ed182	528	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
richardv	0:b079fa4ed182	529	uint32_t RESERVED4; /!< Reserved, 0x218 /
richardv	0:b079fa4ed182	530	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
richardv	0:b079fa4ed182	531	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
richardv	0:b079fa4ed182	532	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
richardv	0:b079fa4ed182	533	} CAN_TypeDef;
richardv	0:b079fa4ed182	534
richardv	0:b079fa4ed182	535
richardv	0:b079fa4ed182	536	/**
richardv	0:b079fa4ed182	537	* @brief Analog Comparators
richardv	0:b079fa4ed182	538	*/
richardv	0:b079fa4ed182	539
richardv	0:b079fa4ed182	540	typedef struct
richardv	0:b079fa4ed182	541	{
richardv	0:b079fa4ed182	542	__IO uint32_t CSR; /!< Comparator control Status register, Address offset: 0x00 /
richardv	0:b079fa4ed182	543	} COMP_TypeDef;
richardv	0:b079fa4ed182	544
richardv	0:b079fa4ed182	545	/**
richardv	0:b079fa4ed182	546	* @brief CRC calculation unit
richardv	0:b079fa4ed182	547	*/
richardv	0:b079fa4ed182	548
richardv	0:b079fa4ed182	549	typedef struct
richardv	0:b079fa4ed182	550	{
richardv	0:b079fa4ed182	551	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
richardv	0:b079fa4ed182	552	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
richardv	0:b079fa4ed182	553	uint8_t RESERVED0; /!< Reserved, 0x05 /
richardv	0:b079fa4ed182	554	uint16_t RESERVED1; /!< Reserved, 0x06 /
richardv	0:b079fa4ed182	555	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
richardv	0:b079fa4ed182	556	uint32_t RESERVED2; /!< Reserved, 0x0C /
richardv	0:b079fa4ed182	557	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
richardv	0:b079fa4ed182	558	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
richardv	0:b079fa4ed182	559	} CRC_TypeDef;
richardv	0:b079fa4ed182	560
richardv	0:b079fa4ed182	561	/**
richardv	0:b079fa4ed182	562	* @brief Digital to Analog Converter
richardv	0:b079fa4ed182	563	*/
richardv	0:b079fa4ed182	564
richardv	0:b079fa4ed182	565	typedef struct
richardv	0:b079fa4ed182	566	{
richardv	0:b079fa4ed182	567	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
richardv	0:b079fa4ed182	568	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
richardv	0:b079fa4ed182	569	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
richardv	0:b079fa4ed182	570	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
richardv	0:b079fa4ed182	571	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
richardv	0:b079fa4ed182	572	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
richardv	0:b079fa4ed182	573	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
richardv	0:b079fa4ed182	574	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
richardv	0:b079fa4ed182	575	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
richardv	0:b079fa4ed182	576	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
richardv	0:b079fa4ed182	577	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
richardv	0:b079fa4ed182	578	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
richardv	0:b079fa4ed182	579	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
richardv	0:b079fa4ed182	580	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
richardv	0:b079fa4ed182	581	} DAC_TypeDef;
richardv	0:b079fa4ed182	582
richardv	0:b079fa4ed182	583	/**
richardv	0:b079fa4ed182	584	* @brief Debug MCU
richardv	0:b079fa4ed182	585	*/
richardv	0:b079fa4ed182	586
richardv	0:b079fa4ed182	587	typedef struct
richardv	0:b079fa4ed182	588	{
richardv	0:b079fa4ed182	589	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
richardv	0:b079fa4ed182	590	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
richardv	0:b079fa4ed182	591	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
richardv	0:b079fa4ed182	592	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
richardv	0:b079fa4ed182	593	}DBGMCU_TypeDef;
richardv	0:b079fa4ed182	594
richardv	0:b079fa4ed182	595	/**
richardv	0:b079fa4ed182	596	* @brief DMA Controller
richardv	0:b079fa4ed182	597	*/
richardv	0:b079fa4ed182	598
richardv	0:b079fa4ed182	599	typedef struct
richardv	0:b079fa4ed182	600	{
richardv	0:b079fa4ed182	601	__IO uint32_t CCR; /!< DMA channel x configuration register /
richardv	0:b079fa4ed182	602	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
richardv	0:b079fa4ed182	603	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
richardv	0:b079fa4ed182	604	__IO uint32_t CMAR; /!< DMA channel x memory address register /
richardv	0:b079fa4ed182	605	} DMA_Channel_TypeDef;
richardv	0:b079fa4ed182	606
richardv	0:b079fa4ed182	607	typedef struct
richardv	0:b079fa4ed182	608	{
richardv	0:b079fa4ed182	609	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
richardv	0:b079fa4ed182	610	__IO uint32_t IFCR; /!< DMA interrupt clear flag register, Address offset: 0x04 /
richardv	0:b079fa4ed182	611	} DMA_TypeDef;
richardv	0:b079fa4ed182	612
richardv	0:b079fa4ed182	613	/**
richardv	0:b079fa4ed182	614	* @brief External Interrupt/Event Controller
richardv	0:b079fa4ed182	615	*/
richardv	0:b079fa4ed182	616
richardv	0:b079fa4ed182	617	typedef struct
richardv	0:b079fa4ed182	618	{
richardv	0:b079fa4ed182	619	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
richardv	0:b079fa4ed182	620	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
richardv	0:b079fa4ed182	621	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
richardv	0:b079fa4ed182	622	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
richardv	0:b079fa4ed182	623	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
richardv	0:b079fa4ed182	624	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
richardv	0:b079fa4ed182	625	uint32_t RESERVED1; /!< Reserved, 0x18 /
richardv	0:b079fa4ed182	626	uint32_t RESERVED2; /!< Reserved, 0x1C /
richardv	0:b079fa4ed182	627	__IO uint32_t IMR2; /!< EXTI Interrupt mask register, Address offset: 0x20 /
richardv	0:b079fa4ed182	628	__IO uint32_t EMR2; /!< EXTI Event mask register, Address offset: 0x24 /
richardv	0:b079fa4ed182	629	__IO uint32_t RTSR2; /!< EXTI Rising trigger selection register, Address offset: 0x28 /
richardv	0:b079fa4ed182	630	__IO uint32_t FTSR2; /!< EXTI Falling trigger selection register, Address offset: 0x2C /
richardv	0:b079fa4ed182	631	__IO uint32_t SWIER2; /!< EXTI Software interrupt event register, Address offset: 0x30 /
richardv	0:b079fa4ed182	632	__IO uint32_t PR2; /!< EXTI Pending register, Address offset: 0x34 /
richardv	0:b079fa4ed182	633	}EXTI_TypeDef;
richardv	0:b079fa4ed182	634
richardv	0:b079fa4ed182	635	/**
richardv	0:b079fa4ed182	636	* @brief FLASH Registers
richardv	0:b079fa4ed182	637	*/
richardv	0:b079fa4ed182	638
richardv	0:b079fa4ed182	639	typedef struct
richardv	0:b079fa4ed182	640	{
richardv	0:b079fa4ed182	641	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
richardv	0:b079fa4ed182	642	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
richardv	0:b079fa4ed182	643	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
richardv	0:b079fa4ed182	644	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
richardv	0:b079fa4ed182	645	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
richardv	0:b079fa4ed182	646	__IO uint32_t AR; /!< FLASH address register, Address offset: 0x14 /
richardv	0:b079fa4ed182	647	uint32_t RESERVED; /!< Reserved, 0x18 /
richardv	0:b079fa4ed182	648	__IO uint32_t OBR; /!< FLASH Option byte register, Address offset: 0x1C /
richardv	0:b079fa4ed182	649	__IO uint32_t WRPR; /!< FLASH Write register, Address offset: 0x20 /
richardv	0:b079fa4ed182	650
richardv	0:b079fa4ed182	651	} FLASH_TypeDef;
richardv	0:b079fa4ed182	652
richardv	0:b079fa4ed182	653	/**
richardv	0:b079fa4ed182	654	* @brief Option Bytes Registers
richardv	0:b079fa4ed182	655	*/
richardv	0:b079fa4ed182	656	typedef struct
richardv	0:b079fa4ed182	657	{
richardv	0:b079fa4ed182	658	__IO uint16_t RDP; /!<FLASH option byte Read protection, Address offset: 0x00 /
richardv	0:b079fa4ed182	659	__IO uint16_t USER; /!<FLASH option byte user options, Address offset: 0x02 /
richardv	0:b079fa4ed182	660	uint16_t RESERVED0; /!< Reserved, 0x04 /
richardv	0:b079fa4ed182	661	uint16_t RESERVED1; /!< Reserved, 0x06 /
richardv	0:b079fa4ed182	662	__IO uint16_t WRP0; /!<FLASH option byte write protection 0, Address offset: 0x08 /
richardv	0:b079fa4ed182	663	__IO uint16_t WRP1; /!<FLASH option byte write protection 1, Address offset: 0x0C /
richardv	0:b079fa4ed182	664	__IO uint16_t WRP2; /!<FLASH option byte write protection 2, Address offset: 0x10 /
richardv	0:b079fa4ed182	665	__IO uint16_t WRP3; /!<FLASH option byte write protection 3, Address offset: 0x12 /
richardv	0:b079fa4ed182	666	} OB_TypeDef;
richardv	0:b079fa4ed182	667
richardv	0:b079fa4ed182	668	/**
richardv	0:b079fa4ed182	669	* @brief General Purpose I/O
richardv	0:b079fa4ed182	670	*/
richardv	0:b079fa4ed182	671
richardv	0:b079fa4ed182	672	typedef struct
richardv	0:b079fa4ed182	673	{
richardv	0:b079fa4ed182	674	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
richardv	0:b079fa4ed182	675	__IO uint16_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
richardv	0:b079fa4ed182	676	uint16_t RESERVED0; /!< Reserved, 0x06 /
richardv	0:b079fa4ed182	677	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
richardv	0:b079fa4ed182	678	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
richardv	0:b079fa4ed182	679	__IO uint16_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
richardv	0:b079fa4ed182	680	uint16_t RESERVED1; /!< Reserved, 0x12 /
richardv	0:b079fa4ed182	681	__IO uint16_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
richardv	0:b079fa4ed182	682	uint16_t RESERVED2; /!< Reserved, 0x16 /
richardv	0:b079fa4ed182	683	__IO uint32_t BSRR; /!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 /
richardv	0:b079fa4ed182	684	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
richardv	0:b079fa4ed182	685	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
richardv	0:b079fa4ed182	686	__IO uint16_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
richardv	0:b079fa4ed182	687	uint16_t RESERVED3; /!< Reserved, 0x2A /
richardv	0:b079fa4ed182	688	}GPIO_TypeDef;
richardv	0:b079fa4ed182	689
richardv	0:b079fa4ed182	690	/**
richardv	0:b079fa4ed182	691	* @brief High resolution Timer (HRTIM)
richardv	0:b079fa4ed182	692	*/
richardv	0:b079fa4ed182	693	/* HRTIM master definition */
richardv	0:b079fa4ed182	694	typedef struct
richardv	0:b079fa4ed182	695	{
richardv	0:b079fa4ed182	696	__IO uint32_t MCR; /!< HRTIM Master Timer control register, Address offset: 0x00 /
richardv	0:b079fa4ed182	697	__IO uint32_t MISR; /!< HRTIM Master Timer interrupt status register, Address offset: 0x04 /
richardv	0:b079fa4ed182	698	__IO uint32_t MICR; /!< HRTIM Master Timer interupt clear register, Address offset: 0x08 /
richardv	0:b079fa4ed182	699	__IO uint32_t MDIER; /!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C /
richardv	0:b079fa4ed182	700	__IO uint32_t MCNTR; /!< HRTIM Master Timer counter register, Address offset: 0x10 /
richardv	0:b079fa4ed182	701	__IO uint32_t MPER; /!< HRTIM Master Timer period register, Address offset: 0x14 /
richardv	0:b079fa4ed182	702	__IO uint32_t MREP; /!< HRTIM Master Timer repetition register, Address offset: 0x18 /
richardv	0:b079fa4ed182	703	__IO uint32_t MCMP1R; /!< HRTIM Master Timer compare 1 register, Address offset: 0x1C /
richardv	0:b079fa4ed182	704	uint32_t RESERVED0; /!< Reserved, 0x20 /
richardv	0:b079fa4ed182	705	__IO uint32_t MCMP2R; /!< HRTIM Master Timer compare 2 register, Address offset: 0x24 /
richardv	0:b079fa4ed182	706	__IO uint32_t MCMP3R; /!< HRTIM Master Timer compare 3 register, Address offset: 0x28 /
richardv	0:b079fa4ed182	707	__IO uint32_t MCMP4R; /!< HRTIM Master Timer compare 4 register, Address offset: 0x2C /
richardv	0:b079fa4ed182	708	}HRTIM_Master_TypeDef;
richardv	0:b079fa4ed182	709
richardv	0:b079fa4ed182	710	/* HRTIM slave definition */
richardv	0:b079fa4ed182	711	typedef struct
richardv	0:b079fa4ed182	712	{
richardv	0:b079fa4ed182	713	__IO uint32_t TIMxCR; /!< HRTIM Timerx control register, Address offset: 0x00 /
richardv	0:b079fa4ed182	714	__IO uint32_t TIMxISR; /!< HRTIM Timerx interrupt status register, Address offset: 0x04 /
richardv	0:b079fa4ed182	715	__IO uint32_t TIMxICR; /!< HRTIM Timerx interrupt clear register, Address offset: 0x08 /
richardv	0:b079fa4ed182	716	__IO uint32_t TIMxDIER; /!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C /
richardv	0:b079fa4ed182	717	__IO uint32_t CNTxR; /!< HRTIM Timerx counter register, Address offset: 0x10 /
richardv	0:b079fa4ed182	718	__IO uint32_t PERxR; /!< HRTIM Timerx period register, Address offset: 0x14 /
richardv	0:b079fa4ed182	719	__IO uint32_t REPxR; /!< HRTIM Timerx repetition register, Address offset: 0x18 /
richardv	0:b079fa4ed182	720	__IO uint32_t CMP1xR; /!< HRTIM Timerx compare 1 register, Address offset: 0x1C /
richardv	0:b079fa4ed182	721	__IO uint32_t CMP1CxR; /!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 /
richardv	0:b079fa4ed182	722	__IO uint32_t CMP2xR; /!< HRTIM Timerx compare 2 register, Address offset: 0x24 /
richardv	0:b079fa4ed182	723	__IO uint32_t CMP3xR; /!< HRTIM Timerx compare 3 register, Address offset: 0x28 /
richardv	0:b079fa4ed182	724	__IO uint32_t CMP4xR; /!< HRTIM Timerx compare 4 register, Address offset: 0x2C /
richardv	0:b079fa4ed182	725	__IO uint32_t CPT1xR; /!< HRTIM Timerx capture 1 register, Address offset: 0x30 /
richardv	0:b079fa4ed182	726	__IO uint32_t CPT2xR; /!< HRTIM Timerx capture 2 register, Address offset: 0x34 /
richardv	0:b079fa4ed182	727	__IO uint32_t DTxR; /!< HRTIM Timerx dead time register, Address offset: 0x38 /
richardv	0:b079fa4ed182	728	__IO uint32_t SETx1R; /!< HRTIM Timerx output 1 set register, Address offset: 0x3C /
richardv	0:b079fa4ed182	729	__IO uint32_t RSTx1R; /!< HRTIM Timerx output 1 reset register, Address offset: 0x40 /
richardv	0:b079fa4ed182	730	__IO uint32_t SETx2R; /!< HRTIM Timerx output 2 set register, Address offset: 0x44 /
richardv	0:b079fa4ed182	731	__IO uint32_t RSTx2R; /!< HRTIM Timerx output 2 reset register, Address offset: 0x48 /
richardv	0:b079fa4ed182	732	__IO uint32_t EEFxR1; /!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C /
richardv	0:b079fa4ed182	733	__IO uint32_t EEFxR2; /!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 /
richardv	0:b079fa4ed182	734	__IO uint32_t RSTxR; /!< HRTIM Timerx Reset register, Address offset: 0x54 /
richardv	0:b079fa4ed182	735	__IO uint32_t CHPxR; /!< HRTIM Timerx Chopper register, Address offset: 0x58 /
richardv	0:b079fa4ed182	736	__IO uint32_t CPT1xCR; /!< HRTIM Timerx Capture 1 register, Address offset: 0x5C /
richardv	0:b079fa4ed182	737	__IO uint32_t CPT2xCR; /!< HRTIM Timerx Capture 2 register, Address offset: 0x60 /
richardv	0:b079fa4ed182	738	__IO uint32_t OUTxR; /!< HRTIM Timerx Output register, Address offset: 0x64 /
richardv	0:b079fa4ed182	739	__IO uint32_t FLTxR; /!< HRTIM Timerx Fault register, Address offset: 0x68 /
richardv	0:b079fa4ed182	740	uint32_t RESERVED0[5];/!< Reserved, /
richardv	0:b079fa4ed182	741	}HRTIM_Timerx_TypeDef;
richardv	0:b079fa4ed182	742
richardv	0:b079fa4ed182	743	/* HRTIM common register definition */
richardv	0:b079fa4ed182	744	typedef struct
richardv	0:b079fa4ed182	745	{
richardv	0:b079fa4ed182	746	__IO uint32_t CR1; /!< HRTIM control register1, Address offset: 0x00 /
richardv	0:b079fa4ed182	747	__IO uint32_t CR2; /!< HRTIM control register2, Address offset: 0x04 /
richardv	0:b079fa4ed182	748	__IO uint32_t ISR; /!< HRTIM interrupt status register, Address offset: 0x08 /
richardv	0:b079fa4ed182	749	__IO uint32_t ICR; /!< HRTIM interrupt clear register, Address offset: 0x0C /
richardv	0:b079fa4ed182	750	__IO uint32_t IER; /!< HRTIM interrupt enable register, Address offset: 0x10 /
richardv	0:b079fa4ed182	751	__IO uint32_t OENR; /!< HRTIM Output enable register, Address offset: 0x14 /
richardv	0:b079fa4ed182	752	__IO uint32_t DISR; /!< HRTIM Output disable register, Address offset: 0x18 /
richardv	0:b079fa4ed182	753	__IO uint32_t ODSR; /!< HRTIM Output disable status register, Address offset: 0x1C /
richardv	0:b079fa4ed182	754	__IO uint32_t BMCR; /!< HRTIM Burst mode control register, Address offset: 0x20 /
richardv	0:b079fa4ed182	755	__IO uint32_t BMTRGR; /!< HRTIM Busrt mode trigger register, Address offset: 0x24 /
richardv	0:b079fa4ed182	756	__IO uint32_t BMCMPR; /!< HRTIM Burst mode compare register, Address offset: 0x28 /
richardv	0:b079fa4ed182	757	__IO uint32_t BMPER; /!< HRTIM Burst mode period register, Address offset: 0x2C /
richardv	0:b079fa4ed182	758	__IO uint32_t EECR1; /!< HRTIM Timer external event control register1, Address offset: 0x30 /
richardv	0:b079fa4ed182	759	__IO uint32_t EECR2; /!< HRTIM Timer external event control register2, Address offset: 0x34 /
richardv	0:b079fa4ed182	760	__IO uint32_t EECR3; /!< HRTIM Timer external event control register3, Address offset: 0x38 /
richardv	0:b079fa4ed182	761	__IO uint32_t ADC1R; /!< HRTIM ADC Trigger 1 register, Address offset: 0x3C /
richardv	0:b079fa4ed182	762	__IO uint32_t ADC2R; /!< HRTIM ADC Trigger 2 register, Address offset: 0x40 /
richardv	0:b079fa4ed182	763	__IO uint32_t ADC3R; /!< HRTIM ADC Trigger 3 register, Address offset: 0x44 /
richardv	0:b079fa4ed182	764	__IO uint32_t ADC4R; /!< HRTIM ADC Trigger 4 register, Address offset: 0x48 /
richardv	0:b079fa4ed182	765	__IO uint32_t DLLCR; /!< HRTIM DLL control register, Address offset: 0x4C /
richardv	0:b079fa4ed182	766	__IO uint32_t FLTINxR1; /!< HRTIM Fault input register1, Address offset: 0x50 /
richardv	0:b079fa4ed182	767	__IO uint32_t FLTINxR2; /!< HRTIM Fault input register2, Address offset: 0x54 /
richardv	0:b079fa4ed182	768	__IO uint32_t BDMUPDR; /!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 /
richardv	0:b079fa4ed182	769	__IO uint32_t BDTAUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C /
richardv	0:b079fa4ed182	770	__IO uint32_t BDTBUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 /
richardv	0:b079fa4ed182	771	__IO uint32_t BDTCUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 /
richardv	0:b079fa4ed182	772	__IO uint32_t BDTDUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 /
richardv	0:b079fa4ed182	773	__IO uint32_t BDTEUPR; /!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C /
richardv	0:b079fa4ed182	774	__IO uint32_t BDMADR; /!< HRTIM Burst DMA Master Data register, Address offset: 0x70 /
richardv	0:b079fa4ed182	775	}HRTIM_Common_TypeDef;
richardv	0:b079fa4ed182	776
richardv	0:b079fa4ed182	777	/* HRTIM register definition */
richardv	0:b079fa4ed182	778	typedef struct {
richardv	0:b079fa4ed182	779	HRTIM_Master_TypeDef HRTIM_MASTER;
richardv	0:b079fa4ed182	780	uint32_t RESERVED0[20];
richardv	0:b079fa4ed182	781	HRTIM_Timerx_TypeDef HRTIM_TIMERx[5];
richardv	0:b079fa4ed182	782	uint32_t RESERVED1[32];
richardv	0:b079fa4ed182	783	HRTIM_Common_TypeDef HRTIM_COMMON;
richardv	0:b079fa4ed182	784	}HRTIM_TypeDef;
richardv	0:b079fa4ed182	785
richardv	0:b079fa4ed182	786	/**
richardv	0:b079fa4ed182	787	* @brief Operational Amplifier (OPAMP)
richardv	0:b079fa4ed182	788	*/
richardv	0:b079fa4ed182	789
richardv	0:b079fa4ed182	790	typedef struct
richardv	0:b079fa4ed182	791	{
richardv	0:b079fa4ed182	792	__IO uint32_t CSR; /!< OPAMP control and status register, Address offset: 0x00 /
richardv	0:b079fa4ed182	793	} OPAMP_TypeDef;
richardv	0:b079fa4ed182	794
richardv	0:b079fa4ed182	795
richardv	0:b079fa4ed182	796	/**
richardv	0:b079fa4ed182	797	* @brief System configuration controller
richardv	0:b079fa4ed182	798	*/
richardv	0:b079fa4ed182	799
richardv	0:b079fa4ed182	800	typedef struct
richardv	0:b079fa4ed182	801	{
richardv	0:b079fa4ed182	802	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
richardv	0:b079fa4ed182	803	__IO uint32_t RCR; /!< SYSCFG CCM SRAM protection register, Address offset: 0x04 /
richardv	0:b079fa4ed182	804	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 /
richardv	0:b079fa4ed182	805	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
richardv	0:b079fa4ed182	806	__IO uint32_t RESERVED0; /!< Reserved, 0x1C /
richardv	0:b079fa4ed182	807	__IO uint32_t RESERVED1; /!< Reserved, 0x20 /
richardv	0:b079fa4ed182	808	__IO uint32_t RESERVED2; /!< Reserved, 0x24 /
richardv	0:b079fa4ed182	809	__IO uint32_t RESERVED4; /!< Reserved, 0x28 /
richardv	0:b079fa4ed182	810	__IO uint32_t RESERVED5; /!< Reserved, 0x2C /
richardv	0:b079fa4ed182	811	__IO uint32_t RESERVED6; /!< Reserved, 0x30 /
richardv	0:b079fa4ed182	812	__IO uint32_t RESERVED7; /!< Reserved, 0x34 /
richardv	0:b079fa4ed182	813	__IO uint32_t RESERVED8; /!< Reserved, 0x38 /
richardv	0:b079fa4ed182	814	__IO uint32_t RESERVED9; /!< Reserved, 0x3C /
richardv	0:b079fa4ed182	815	__IO uint32_t RESERVED10; /!< Reserved, 0x40 /
richardv	0:b079fa4ed182	816	__IO uint32_t RESERVED11; /!< Reserved, 0x44 /
richardv	0:b079fa4ed182	817	__IO uint32_t RESERVED12; /!< Reserved, 0x48 /
richardv	0:b079fa4ed182	818	__IO uint32_t RESERVED13; /!< Reserved, 0x4C /
richardv	0:b079fa4ed182	819	__IO uint32_t CFGR3; /!< SYSCFG configuration register 3, Address offset: 0x50 /
richardv	0:b079fa4ed182	820	} SYSCFG_TypeDef;
richardv	0:b079fa4ed182	821
richardv	0:b079fa4ed182	822	/**
richardv	0:b079fa4ed182	823	* @brief Inter-integrated Circuit Interface
richardv	0:b079fa4ed182	824	*/
richardv	0:b079fa4ed182	825
richardv	0:b079fa4ed182	826	typedef struct
richardv	0:b079fa4ed182	827	{
richardv	0:b079fa4ed182	828	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
richardv	0:b079fa4ed182	829	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
richardv	0:b079fa4ed182	830	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
richardv	0:b079fa4ed182	831	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
richardv	0:b079fa4ed182	832	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
richardv	0:b079fa4ed182	833	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
richardv	0:b079fa4ed182	834	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
richardv	0:b079fa4ed182	835	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
richardv	0:b079fa4ed182	836	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
richardv	0:b079fa4ed182	837	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
richardv	0:b079fa4ed182	838	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
richardv	0:b079fa4ed182	839	}I2C_TypeDef;
richardv	0:b079fa4ed182	840
richardv	0:b079fa4ed182	841	/**
richardv	0:b079fa4ed182	842	* @brief Independent WATCHDOG
richardv	0:b079fa4ed182	843	*/
richardv	0:b079fa4ed182	844
richardv	0:b079fa4ed182	845	typedef struct
richardv	0:b079fa4ed182	846	{
richardv	0:b079fa4ed182	847	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
richardv	0:b079fa4ed182	848	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
richardv	0:b079fa4ed182	849	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
richardv	0:b079fa4ed182	850	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
richardv	0:b079fa4ed182	851	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
richardv	0:b079fa4ed182	852	} IWDG_TypeDef;
richardv	0:b079fa4ed182	853
richardv	0:b079fa4ed182	854	/**
richardv	0:b079fa4ed182	855	* @brief Power Control
richardv	0:b079fa4ed182	856	*/
richardv	0:b079fa4ed182	857
richardv	0:b079fa4ed182	858	typedef struct
richardv	0:b079fa4ed182	859	{
richardv	0:b079fa4ed182	860	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
richardv	0:b079fa4ed182	861	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
richardv	0:b079fa4ed182	862	} PWR_TypeDef;
richardv	0:b079fa4ed182	863
richardv	0:b079fa4ed182	864	/**
richardv	0:b079fa4ed182	865	* @brief Reset and Clock Control
richardv	0:b079fa4ed182	866	*/
richardv	0:b079fa4ed182	867	typedef struct
richardv	0:b079fa4ed182	868	{
richardv	0:b079fa4ed182	869	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
richardv	0:b079fa4ed182	870	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
richardv	0:b079fa4ed182	871	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
richardv	0:b079fa4ed182	872	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
richardv	0:b079fa4ed182	873	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
richardv	0:b079fa4ed182	874	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
richardv	0:b079fa4ed182	875	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
richardv	0:b079fa4ed182	876	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
richardv	0:b079fa4ed182	877	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
richardv	0:b079fa4ed182	878	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
richardv	0:b079fa4ed182	879	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
richardv	0:b079fa4ed182	880	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
richardv	0:b079fa4ed182	881	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
richardv	0:b079fa4ed182	882	} RCC_TypeDef;
richardv	0:b079fa4ed182	883
richardv	0:b079fa4ed182	884	/**
richardv	0:b079fa4ed182	885	* @brief Real-Time Clock
richardv	0:b079fa4ed182	886	*/
richardv	0:b079fa4ed182	887
richardv	0:b079fa4ed182	888	typedef struct
richardv	0:b079fa4ed182	889	{
richardv	0:b079fa4ed182	890	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
richardv	0:b079fa4ed182	891	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
richardv	0:b079fa4ed182	892	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
richardv	0:b079fa4ed182	893	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
richardv	0:b079fa4ed182	894	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
richardv	0:b079fa4ed182	895	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
richardv	0:b079fa4ed182	896	uint32_t RESERVED0; /!< Reserved, 0x18 /
richardv	0:b079fa4ed182	897	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
richardv	0:b079fa4ed182	898	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
richardv	0:b079fa4ed182	899	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
richardv	0:b079fa4ed182	900	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
richardv	0:b079fa4ed182	901	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
richardv	0:b079fa4ed182	902	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
richardv	0:b079fa4ed182	903	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
richardv	0:b079fa4ed182	904	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
richardv	0:b079fa4ed182	905	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
richardv	0:b079fa4ed182	906	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
richardv	0:b079fa4ed182	907	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
richardv	0:b079fa4ed182	908	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
richardv	0:b079fa4ed182	909	uint32_t RESERVED7; /!< Reserved, 0x4C /
richardv	0:b079fa4ed182	910	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
richardv	0:b079fa4ed182	911	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
richardv	0:b079fa4ed182	912	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
richardv	0:b079fa4ed182	913	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
richardv	0:b079fa4ed182	914	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
richardv	0:b079fa4ed182	915	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
richardv	0:b079fa4ed182	916	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
richardv	0:b079fa4ed182	917	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
richardv	0:b079fa4ed182	918	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
richardv	0:b079fa4ed182	919	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
richardv	0:b079fa4ed182	920	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
richardv	0:b079fa4ed182	921	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
richardv	0:b079fa4ed182	922	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
richardv	0:b079fa4ed182	923	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
richardv	0:b079fa4ed182	924	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
richardv	0:b079fa4ed182	925	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
richardv	0:b079fa4ed182	926	} RTC_TypeDef;
richardv	0:b079fa4ed182	927
richardv	0:b079fa4ed182	928
richardv	0:b079fa4ed182	929	/**
richardv	0:b079fa4ed182	930	* @brief Serial Peripheral Interface
richardv	0:b079fa4ed182	931	*/
richardv	0:b079fa4ed182	932
richardv	0:b079fa4ed182	933	typedef struct
richardv	0:b079fa4ed182	934	{
richardv	0:b079fa4ed182	935	__IO uint16_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
richardv	0:b079fa4ed182	936	uint16_t RESERVED0; /!< Reserved, 0x02 /
richardv	0:b079fa4ed182	937	__IO uint16_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
richardv	0:b079fa4ed182	938	uint16_t RESERVED1; /!< Reserved, 0x06 /
richardv	0:b079fa4ed182	939	__IO uint16_t SR; /!< SPI Status register, Address offset: 0x08 /
richardv	0:b079fa4ed182	940	uint16_t RESERVED2; /!< Reserved, 0x0A /
richardv	0:b079fa4ed182	941	__IO uint16_t DR; /!< SPI data register, Address offset: 0x0C /
richardv	0:b079fa4ed182	942	uint16_t RESERVED3; /!< Reserved, 0x0E /
richardv	0:b079fa4ed182	943	__IO uint16_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
richardv	0:b079fa4ed182	944	uint16_t RESERVED4; /!< Reserved, 0x12 /
richardv	0:b079fa4ed182	945	__IO uint16_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
richardv	0:b079fa4ed182	946	uint16_t RESERVED5; /!< Reserved, 0x16 /
richardv	0:b079fa4ed182	947	__IO uint16_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
richardv	0:b079fa4ed182	948	uint16_t RESERVED6; /!< Reserved, 0x1A /
richardv	0:b079fa4ed182	949	__IO uint16_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
richardv	0:b079fa4ed182	950	uint16_t RESERVED7; /!< Reserved, 0x1E /
richardv	0:b079fa4ed182	951	__IO uint16_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
richardv	0:b079fa4ed182	952	uint16_t RESERVED8; /!< Reserved, 0x22 /
richardv	0:b079fa4ed182	953	} SPI_TypeDef;
richardv	0:b079fa4ed182	954
richardv	0:b079fa4ed182	955	/**
richardv	0:b079fa4ed182	956	* @brief TIM
richardv	0:b079fa4ed182	957	*/
richardv	0:b079fa4ed182	958	typedef struct
richardv	0:b079fa4ed182	959	{
richardv	0:b079fa4ed182	960	__IO uint16_t CR1; /!< TIM control register 1, Address offset: 0x00 /
richardv	0:b079fa4ed182	961	uint16_t RESERVED0; /!< Reserved, 0x02 /
richardv	0:b079fa4ed182	962	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
richardv	0:b079fa4ed182	963	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
richardv	0:b079fa4ed182	964	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
richardv	0:b079fa4ed182	965	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
richardv	0:b079fa4ed182	966	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
richardv	0:b079fa4ed182	967	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
richardv	0:b079fa4ed182	968	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
richardv	0:b079fa4ed182	969	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
richardv	0:b079fa4ed182	970	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
richardv	0:b079fa4ed182	971	__IO uint16_t PSC; /!< TIM prescaler, Address offset: 0x28 /
richardv	0:b079fa4ed182	972	uint16_t RESERVED9; /!< Reserved, 0x2A /
richardv	0:b079fa4ed182	973	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
richardv	0:b079fa4ed182	974	__IO uint16_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
richardv	0:b079fa4ed182	975	uint16_t RESERVED10; /!< Reserved, 0x32 /
richardv	0:b079fa4ed182	976	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
richardv	0:b079fa4ed182	977	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
richardv	0:b079fa4ed182	978	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
richardv	0:b079fa4ed182	979	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
richardv	0:b079fa4ed182	980	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
richardv	0:b079fa4ed182	981	__IO uint16_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
richardv	0:b079fa4ed182	982	uint16_t RESERVED12; /!< Reserved, 0x4A /
richardv	0:b079fa4ed182	983	__IO uint16_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
richardv	0:b079fa4ed182	984	uint16_t RESERVED13; /!< Reserved, 0x4E /
richardv	0:b079fa4ed182	985	__IO uint16_t OR; /!< TIM option register, Address offset: 0x50 /
richardv	0:b079fa4ed182	986	__IO uint32_t CCMR3; /!< TIM capture/compare mode register 3, Address offset: 0x54 /
richardv	0:b079fa4ed182	987	__IO uint32_t CCR5; /!< TIM capture/compare register5, Address offset: 0x58 /
richardv	0:b079fa4ed182	988	__IO uint32_t CCR6; /!< TIM capture/compare register 4, Address offset: 0x5C /
richardv	0:b079fa4ed182	989	} TIM_TypeDef;
richardv	0:b079fa4ed182	990
richardv	0:b079fa4ed182	991
richardv	0:b079fa4ed182	992	/**
richardv	0:b079fa4ed182	993	* @brief Touch Sensing Controller (TSC)
richardv	0:b079fa4ed182	994	*/
richardv	0:b079fa4ed182	995	typedef struct
richardv	0:b079fa4ed182	996	{
richardv	0:b079fa4ed182	997	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
richardv	0:b079fa4ed182	998	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
richardv	0:b079fa4ed182	999	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
richardv	0:b079fa4ed182	1000	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
richardv	0:b079fa4ed182	1001	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
richardv	0:b079fa4ed182	1002	uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
richardv	0:b079fa4ed182	1003	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
richardv	0:b079fa4ed182	1004	uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
richardv	0:b079fa4ed182	1005	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
richardv	0:b079fa4ed182	1006	uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
richardv	0:b079fa4ed182	1007	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
richardv	0:b079fa4ed182	1008	uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
richardv	0:b079fa4ed182	1009	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
richardv	0:b079fa4ed182	1010	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
richardv	0:b079fa4ed182	1011	} TSC_TypeDef;
richardv	0:b079fa4ed182	1012
richardv	0:b079fa4ed182	1013	/**
richardv	0:b079fa4ed182	1014	* @brief Universal Synchronous Asynchronous Receiver Transmitter
richardv	0:b079fa4ed182	1015	*/
richardv	0:b079fa4ed182	1016
richardv	0:b079fa4ed182	1017	typedef struct
richardv	0:b079fa4ed182	1018	{
richardv	0:b079fa4ed182	1019	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
richardv	0:b079fa4ed182	1020	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
richardv	0:b079fa4ed182	1021	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
richardv	0:b079fa4ed182	1022	__IO uint16_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
richardv	0:b079fa4ed182	1023	uint16_t RESERVED1; /!< Reserved, 0x0E /
richardv	0:b079fa4ed182	1024	__IO uint16_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
richardv	0:b079fa4ed182	1025	uint16_t RESERVED2; /!< Reserved, 0x12 /
richardv	0:b079fa4ed182	1026	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
richardv	0:b079fa4ed182	1027	__IO uint16_t RQR; /!< USART Request register, Address offset: 0x18 /
richardv	0:b079fa4ed182	1028	uint16_t RESERVED3; /!< Reserved, 0x1A /
richardv	0:b079fa4ed182	1029	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
richardv	0:b079fa4ed182	1030	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
richardv	0:b079fa4ed182	1031	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
richardv	0:b079fa4ed182	1032	uint16_t RESERVED4; /!< Reserved, 0x26 /
richardv	0:b079fa4ed182	1033	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
richardv	0:b079fa4ed182	1034	uint16_t RESERVED5; /!< Reserved, 0x2A /
richardv	0:b079fa4ed182	1035	} USART_TypeDef;
richardv	0:b079fa4ed182	1036
richardv	0:b079fa4ed182	1037	/**
richardv	0:b079fa4ed182	1038	* @brief Window WATCHDOG
richardv	0:b079fa4ed182	1039	*/
richardv	0:b079fa4ed182	1040	typedef struct
richardv	0:b079fa4ed182	1041	{
richardv	0:b079fa4ed182	1042	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
richardv	0:b079fa4ed182	1043	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
richardv	0:b079fa4ed182	1044	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
richardv	0:b079fa4ed182	1045	} WWDG_TypeDef;
richardv	0:b079fa4ed182	1046
richardv	0:b079fa4ed182	1047
richardv	0:b079fa4ed182	1048	/** @addtogroup Peripheral_memory_map
richardv	0:b079fa4ed182	1049	* @{
richardv	0:b079fa4ed182	1050	*/
richardv	0:b079fa4ed182	1051
richardv	0:b079fa4ed182	1052	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
richardv	0:b079fa4ed182	1053	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
richardv	0:b079fa4ed182	1054	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
richardv	0:b079fa4ed182	1055
richardv	0:b079fa4ed182	1056	#define SRAM_BB_BASE ((uint32_t)0x22000000) /!< SRAM base address in the bit-band region /
richardv	0:b079fa4ed182	1057	#define PERIPH_BB_BASE ((uint32_t)0x42000000) /!< Peripheral base address in the bit-band region /
richardv	0:b079fa4ed182	1058
richardv	0:b079fa4ed182	1059
richardv	0:b079fa4ed182	1060	/!< Peripheral memory map /
richardv	0:b079fa4ed182	1061	#define APB1PERIPH_BASE PERIPH_BASE
richardv	0:b079fa4ed182	1062	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
richardv	0:b079fa4ed182	1063	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
richardv	0:b079fa4ed182	1064	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
richardv	0:b079fa4ed182	1065	#define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
richardv	0:b079fa4ed182	1066
richardv	0:b079fa4ed182	1067	/!< APB1 peripherals /
richardv	0:b079fa4ed182	1068	#define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
richardv	0:b079fa4ed182	1069	#define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
richardv	0:b079fa4ed182	1070	#define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
richardv	0:b079fa4ed182	1071	#define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
richardv	0:b079fa4ed182	1072	#define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
richardv	0:b079fa4ed182	1073	#define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
richardv	0:b079fa4ed182	1074	#define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
richardv	0:b079fa4ed182	1075	#define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
richardv	0:b079fa4ed182	1076	#define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
richardv	0:b079fa4ed182	1077	#define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
richardv	0:b079fa4ed182	1078	#define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
richardv	0:b079fa4ed182	1079	#define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
richardv	0:b079fa4ed182	1080	#define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
richardv	0:b079fa4ed182	1081	#define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
richardv	0:b079fa4ed182	1082	#define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
richardv	0:b079fa4ed182	1083	#define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
richardv	0:b079fa4ed182	1084	#define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
richardv	0:b079fa4ed182	1085	#define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
richardv	0:b079fa4ed182	1086	#define CAN1_BASE (APB1PERIPH_BASE + 0x00006400)
richardv	0:b079fa4ed182	1087	#define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
richardv	0:b079fa4ed182	1088	#define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
richardv	0:b079fa4ed182	1089	#define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
richardv	0:b079fa4ed182	1090	#define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
richardv	0:b079fa4ed182	1091	#define DAC_BASE DAC1_BASE
richardv	0:b079fa4ed182	1092
richardv	0:b079fa4ed182	1093	/!< APB2 peripherals /
richardv	0:b079fa4ed182	1094	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
richardv	0:b079fa4ed182	1095	#define COMP_BASE (APB2PERIPH_BASE + 0x0000001C)
richardv	0:b079fa4ed182	1096	#define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
richardv	0:b079fa4ed182	1097	#define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
richardv	0:b079fa4ed182	1098	#define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
richardv	0:b079fa4ed182	1099	#define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
richardv	0:b079fa4ed182	1100	#define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
richardv	0:b079fa4ed182	1101	#define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
richardv	0:b079fa4ed182	1102	#define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
richardv	0:b079fa4ed182	1103	#define OPAMP_BASE (APB2PERIPH_BASE + 0x00000038)
richardv	0:b079fa4ed182	1104	#define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
richardv	0:b079fa4ed182	1105	#define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
richardv	0:b079fa4ed182	1106	#define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
richardv	0:b079fa4ed182	1107	#define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
richardv	0:b079fa4ed182	1108	#define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
richardv	0:b079fa4ed182	1109	#define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
richardv	0:b079fa4ed182	1110	#define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
richardv	0:b079fa4ed182	1111	#define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
richardv	0:b079fa4ed182	1112	#define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
richardv	0:b079fa4ed182	1113	#define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
richardv	0:b079fa4ed182	1114	#define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
richardv	0:b079fa4ed182	1115	#define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
richardv	0:b079fa4ed182	1116	#define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400)
richardv	0:b079fa4ed182	1117	#define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
richardv	0:b079fa4ed182	1118	#define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
richardv	0:b079fa4ed182	1119	#define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
richardv	0:b079fa4ed182	1120	#define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
richardv	0:b079fa4ed182	1121	#define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
richardv	0:b079fa4ed182	1122	#define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
richardv	0:b079fa4ed182	1123
richardv	0:b079fa4ed182	1124	/!< AHB1 peripherals /
richardv	0:b079fa4ed182	1125	#define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
richardv	0:b079fa4ed182	1126	#define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
richardv	0:b079fa4ed182	1127	#define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
richardv	0:b079fa4ed182	1128	#define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
richardv	0:b079fa4ed182	1129	#define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
richardv	0:b079fa4ed182	1130	#define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
richardv	0:b079fa4ed182	1131	#define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
richardv	0:b079fa4ed182	1132	#define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
richardv	0:b079fa4ed182	1133	#define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
richardv	0:b079fa4ed182	1134	#define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
richardv	0:b079fa4ed182	1135	#define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
richardv	0:b079fa4ed182	1136	#define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
richardv	0:b079fa4ed182	1137	#define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
richardv	0:b079fa4ed182	1138	#define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
richardv	0:b079fa4ed182	1139	#define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
richardv	0:b079fa4ed182	1140	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /!< Flash registers base address /
richardv	0:b079fa4ed182	1141	#define OB_BASE ((uint32_t)0x1FFFF800) /!< Flash Option Bytes base address /
richardv	0:b079fa4ed182	1142	#define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
richardv	0:b079fa4ed182	1143	#define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
richardv	0:b079fa4ed182	1144
richardv	0:b079fa4ed182	1145	/!< AHB2 peripherals /
richardv	0:b079fa4ed182	1146	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
richardv	0:b079fa4ed182	1147	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
richardv	0:b079fa4ed182	1148	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
richardv	0:b079fa4ed182	1149	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
richardv	0:b079fa4ed182	1150	#define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000)
richardv	0:b079fa4ed182	1151	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
richardv	0:b079fa4ed182	1152
richardv	0:b079fa4ed182	1153	/!< AHB3 peripherals /
richardv	0:b079fa4ed182	1154	#define ADC1_BASE (AHB3PERIPH_BASE + 0x0000)
richardv	0:b079fa4ed182	1155	#define ADC2_BASE (AHB3PERIPH_BASE + 0x0100)
richardv	0:b079fa4ed182	1156	#define ADC1_2_BASE (AHB3PERIPH_BASE + 0x0300)
richardv	0:b079fa4ed182	1157	#define ADC3_BASE (AHB3PERIPH_BASE + 0x0400)
richardv	0:b079fa4ed182	1158	#define ADC4_BASE (AHB3PERIPH_BASE + 0x0500)
richardv	0:b079fa4ed182	1159	#define ADC3_4_BASE (AHB3PERIPH_BASE + 0x0700)
richardv	0:b079fa4ed182	1160
richardv	0:b079fa4ed182	1161	#define DBGMCU_BASE ((uint32_t)0xE0042000) /!< Debug MCU registers base address /
richardv	0:b079fa4ed182	1162	/**
richardv	0:b079fa4ed182	1163	* @}
richardv	0:b079fa4ed182	1164	*/
richardv	0:b079fa4ed182	1165
richardv	0:b079fa4ed182	1166	/** @addtogroup Peripheral_declaration
richardv	0:b079fa4ed182	1167	* @{
richardv	0:b079fa4ed182	1168	*/
richardv	0:b079fa4ed182	1169	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
richardv	0:b079fa4ed182	1170	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
richardv	0:b079fa4ed182	1171	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
richardv	0:b079fa4ed182	1172	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
richardv	0:b079fa4ed182	1173	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
richardv	0:b079fa4ed182	1174	#define RTC ((RTC_TypeDef *) RTC_BASE)
richardv	0:b079fa4ed182	1175	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
richardv	0:b079fa4ed182	1176	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
richardv	0:b079fa4ed182	1177	#define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
richardv	0:b079fa4ed182	1178	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
richardv	0:b079fa4ed182	1179	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
richardv	0:b079fa4ed182	1180	#define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
richardv	0:b079fa4ed182	1181	#define USART2 ((USART_TypeDef *) USART2_BASE)
richardv	0:b079fa4ed182	1182	#define USART3 ((USART_TypeDef *) USART3_BASE)
richardv	0:b079fa4ed182	1183	#define UART4 ((USART_TypeDef *) UART4_BASE)
richardv	0:b079fa4ed182	1184	#define UART5 ((USART_TypeDef *) UART5_BASE)
richardv	0:b079fa4ed182	1185	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
richardv	0:b079fa4ed182	1186	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
richardv	0:b079fa4ed182	1187	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
richardv	0:b079fa4ed182	1188	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
richardv	0:b079fa4ed182	1189	#define PWR ((PWR_TypeDef *) PWR_BASE)
richardv	0:b079fa4ed182	1190	#define DAC1 ((DAC_TypeDef *) DAC1_BASE)
richardv	0:b079fa4ed182	1191	#define DAC2 ((DAC_TypeDef *) DAC2_BASE)
richardv	0:b079fa4ed182	1192	#define DAC DAC1
richardv	0:b079fa4ed182	1193	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
richardv	0:b079fa4ed182	1194	#define COMP ((COMP_TypeDef *) COMP_BASE)
richardv	0:b079fa4ed182	1195	#define COMP1 ((COMP_TypeDef *) COMP1_BASE)
richardv	0:b079fa4ed182	1196	#define COMP2 ((COMP_TypeDef *) COMP2_BASE)
richardv	0:b079fa4ed182	1197	#define COMP3 ((COMP_TypeDef *) COMP3_BASE)
richardv	0:b079fa4ed182	1198	#define COMP4 ((COMP_TypeDef *) COMP4_BASE)
richardv	0:b079fa4ed182	1199	#define COMP5 ((COMP_TypeDef *) COMP5_BASE)
richardv	0:b079fa4ed182	1200	#define COMP6 ((COMP_TypeDef *) COMP6_BASE)
richardv	0:b079fa4ed182	1201	#define COMP7 ((COMP_TypeDef *) COMP7_BASE)
richardv	0:b079fa4ed182	1202	#define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
richardv	0:b079fa4ed182	1203	#define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
richardv	0:b079fa4ed182	1204	#define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
richardv	0:b079fa4ed182	1205	#define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
richardv	0:b079fa4ed182	1206	#define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
richardv	0:b079fa4ed182	1207	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
richardv	0:b079fa4ed182	1208	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
richardv	0:b079fa4ed182	1209	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
richardv	0:b079fa4ed182	1210	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
richardv	0:b079fa4ed182	1211	#define USART1 ((USART_TypeDef *) USART1_BASE)
richardv	0:b079fa4ed182	1212	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
richardv	0:b079fa4ed182	1213	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
richardv	0:b079fa4ed182	1214	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
richardv	0:b079fa4ed182	1215	#define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
richardv	0:b079fa4ed182	1216	#define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
richardv	0:b079fa4ed182	1217	#define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
richardv	0:b079fa4ed182	1218	#define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
richardv	0:b079fa4ed182	1219	#define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
richardv	0:b079fa4ed182	1220	#define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
richardv	0:b079fa4ed182	1221	#define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
richardv	0:b079fa4ed182	1222	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
richardv	0:b079fa4ed182	1223	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
richardv	0:b079fa4ed182	1224	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
richardv	0:b079fa4ed182	1225	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
richardv	0:b079fa4ed182	1226	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
richardv	0:b079fa4ed182	1227	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
richardv	0:b079fa4ed182	1228	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
richardv	0:b079fa4ed182	1229	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
richardv	0:b079fa4ed182	1230	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
richardv	0:b079fa4ed182	1231	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
richardv	0:b079fa4ed182	1232	#define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
richardv	0:b079fa4ed182	1233	#define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
richardv	0:b079fa4ed182	1234	#define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
richardv	0:b079fa4ed182	1235	#define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
richardv	0:b079fa4ed182	1236	#define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
richardv	0:b079fa4ed182	1237	#define RCC ((RCC_TypeDef *) RCC_BASE)
richardv	0:b079fa4ed182	1238	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
richardv	0:b079fa4ed182	1239	#define OB ((OB_TypeDef *) OB_BASE)
richardv	0:b079fa4ed182	1240	#define CRC ((CRC_TypeDef *) CRC_BASE)
richardv	0:b079fa4ed182	1241	#define TSC ((TSC_TypeDef *) TSC_BASE)
richardv	0:b079fa4ed182	1242	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
richardv	0:b079fa4ed182	1243	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
richardv	0:b079fa4ed182	1244	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
richardv	0:b079fa4ed182	1245	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
richardv	0:b079fa4ed182	1246	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
richardv	0:b079fa4ed182	1247	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
richardv	0:b079fa4ed182	1248	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
richardv	0:b079fa4ed182	1249	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
richardv	0:b079fa4ed182	1250	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
richardv	0:b079fa4ed182	1251	#define ADC4 ((ADC_TypeDef *) ADC4_BASE)
richardv	0:b079fa4ed182	1252	#define ADC1_2 ((ADC_Common_TypeDef *) ADC1_2_BASE)
richardv	0:b079fa4ed182	1253	#define ADC3_4 ((ADC_Common_TypeDef *) ADC3_4_BASE)
richardv	0:b079fa4ed182	1254	/**
richardv	0:b079fa4ed182	1255	* @}
richardv	0:b079fa4ed182	1256	*/
richardv	0:b079fa4ed182	1257
richardv	0:b079fa4ed182	1258	/** @addtogroup Exported_constants
richardv	0:b079fa4ed182	1259	* @{
richardv	0:b079fa4ed182	1260	*/
richardv	0:b079fa4ed182	1261
richardv	0:b079fa4ed182	1262	/** @addtogroup Peripheral_Registers_Bits_Definition
richardv	0:b079fa4ed182	1263	* @{
richardv	0:b079fa4ed182	1264	*/
richardv	0:b079fa4ed182	1265
richardv	0:b079fa4ed182	1266	/******************************************************************************/
richardv	0:b079fa4ed182	1267	/* Peripheral Registers_Bits_Definition */
richardv	0:b079fa4ed182	1268	/******************************************************************************/
richardv	0:b079fa4ed182	1269	/******************************************************************************/
richardv	0:b079fa4ed182	1270	/* */
richardv	0:b079fa4ed182	1271	/* High Resolution Timer (HRTIM) */
richardv	0:b079fa4ed182	1272	/* */
richardv	0:b079fa4ed182	1273	/******************************************************************************/
richardv	0:b079fa4ed182	1274	/****************** Master Timer control register *************************/
richardv	0:b079fa4ed182	1275	#define HRTIM_MCR_CK_PSC ((uint32_t)0x00000007) /!< Prescaler mask /
richardv	0:b079fa4ed182	1276	#define HRTIM_MCR_CK_PSC_0 ((uint32_t)0x00000001) /!< Prescaler bit 0 /
richardv	0:b079fa4ed182	1277	#define HRTIM_MCR_CK_PSC_1 ((uint32_t)0x00000002) /!< Prescaler bit 1 /
richardv	0:b079fa4ed182	1278	#define HRTIM_MCR_CK_PSC_2 ((uint32_t)0x00000004) /!< Prescaler bit 2 /
richardv	0:b079fa4ed182	1279
richardv	0:b079fa4ed182	1280	#define HRTIM_MCR_CONT ((uint32_t)0x00000008) /!< Continuous mode /
richardv	0:b079fa4ed182	1281	#define HRTIM_MCR_RETRIG ((uint32_t)0x00000010) /!< Rettrigreable mode /
richardv	0:b079fa4ed182	1282	#define HRTIM_MCR_HALF ((uint32_t)0x00000020) /!< Half mode /
richardv	0:b079fa4ed182	1283
richardv	0:b079fa4ed182	1284	#define HRTIM_MCR_SYNC_IN ((uint32_t)0x00000300) /!< Synchronization input master /
richardv	0:b079fa4ed182	1285	#define HRTIM_MCR_SYNC_IN_0 ((uint32_t)0x00000100) /!< Synchronization input bit 0 /
richardv	0:b079fa4ed182	1286	#define HRTIM_MCR_SYNC_IN_1 ((uint32_t)0x00000200) /!< Synchronization input bit 1 /
richardv	0:b079fa4ed182	1287	#define HRTIM_MCR_SYNCRSTM ((uint32_t)0x00000400) /!< Synchronization reset master /
richardv	0:b079fa4ed182	1288	#define HRTIM_MCR_SYNCSTRTM ((uint32_t)0x00000800) /!< Synchronization start master /
richardv	0:b079fa4ed182	1289	#define HRTIM_MCR_SYNC_OUT ((uint32_t)0x00003000) /!< Synchronization output master /
richardv	0:b079fa4ed182	1290	#define HRTIM_MCR_SYNC_OUT_0 ((uint32_t)0x00001000) /!< Synchronization output bit 0 /
richardv	0:b079fa4ed182	1291	#define HRTIM_MCR_SYNC_OUT_1 ((uint32_t)0x00002000) /!< Synchronization output bit 1 /
richardv	0:b079fa4ed182	1292	#define HRTIM_MCR_SYNC_SRC ((uint32_t)0x0000C000) /!< Synchronization source /
richardv	0:b079fa4ed182	1293	#define HRTIM_MCR_SYNC_SRC_0 ((uint32_t)0x00004000) /!< Synchronization source bit 0 /
richardv	0:b079fa4ed182	1294	#define HRTIM_MCR_SYNC_SRC_1 ((uint32_t)0x00008000) /!< Synchronization source bit 1 /
richardv	0:b079fa4ed182	1295
richardv	0:b079fa4ed182	1296	#define HRTIM_MCR_MCEN ((uint32_t)0x00010000) /!< Master counter enable /
richardv	0:b079fa4ed182	1297	#define HRTIM_MCR_TACEN ((uint32_t)0x00020000) /!< Timer A counter enable /
richardv	0:b079fa4ed182	1298	#define HRTIM_MCR_TBCEN ((uint32_t)0x00040000) /!< Timer B counter enable /
richardv	0:b079fa4ed182	1299	#define HRTIM_MCR_TCCEN ((uint32_t)0x00080000) /!< Timer C counter enable /
richardv	0:b079fa4ed182	1300	#define HRTIM_MCR_TDCEN ((uint32_t)0x00100000) /!< Timer D counter enable /
richardv	0:b079fa4ed182	1301	#define HRTIM_MCR_TECEN ((uint32_t)0x00200000) /!< Timer E counter enable /
richardv	0:b079fa4ed182	1302
richardv	0:b079fa4ed182	1303	#define HRTIM_MCR_DACSYNC ((uint32_t)0x06000000) /!< DAC synchronization mask /
richardv	0:b079fa4ed182	1304	#define HRTIM_MCR_DACSYNC_0 ((uint32_t)0x02000000) /!< DAC synchronization bit 0 /
richardv	0:b079fa4ed182	1305	#define HRTIM_MCR_DACSYNC_1 ((uint32_t)0x04000000) /!< DAC synchronization bit 1 /
richardv	0:b079fa4ed182	1306
richardv	0:b079fa4ed182	1307	#define HRTIM_MCR_PREEN ((uint32_t)0x08000000) /!< Master preload enable /
richardv	0:b079fa4ed182	1308	#define HRTIM_MCR_MREPU ((uint32_t)0x20000000) /!< Master repetition update /
richardv	0:b079fa4ed182	1309
richardv	0:b079fa4ed182	1310	#define HRTIM_MCR_BRSTDMA ((uint32_t)0xC0000000) /!< Burst DMA update /
richardv	0:b079fa4ed182	1311	#define HRTIM_MCR_BRSTDMA_0 ((uint32_t)0x40000000) /!< Burst DMA update bit 0/
richardv	0:b079fa4ed182	1312	#define HRTIM_MCR_BRSTDMA_1 ((uint32_t)0x80000000) /!< Burst DMA update bit 1 /
richardv	0:b079fa4ed182	1313
richardv	0:b079fa4ed182	1314	/****************** Master Timer Interrupt status register ****************/
richardv	0:b079fa4ed182	1315	#define HRTIM_MISR_MCMP1 ((uint32_t)0x00000001) /!< Master compare 1 interrupt flag /
richardv	0:b079fa4ed182	1316	#define HRTIM_MISR_MCMP2 ((uint32_t)0x00000002) /!< Master compare 2 interrupt flag /
richardv	0:b079fa4ed182	1317	#define HRTIM_MISR_MCMP3 ((uint32_t)0x00000004) /!< Master compare 3 interrupt flag /
richardv	0:b079fa4ed182	1318	#define HRTIM_MISR_MCMP4 ((uint32_t)0x00000008) /!< Master compare 4 interrupt flag /
richardv	0:b079fa4ed182	1319	#define HRTIM_MISR_MREP ((uint32_t)0x00000010) /!< Master Repetition interrupt flag /
richardv	0:b079fa4ed182	1320	#define HRTIM_MISR_SYNC ((uint32_t)0x00000020) /!< Synchronization input interrupt flag /
richardv	0:b079fa4ed182	1321	#define HRTIM_MISR_MUPD ((uint32_t)0x00000040) /!< Master update interrupt flag /
richardv	0:b079fa4ed182	1322
richardv	0:b079fa4ed182	1323	/****************** Master Timer Interrupt clear register *****************/
richardv	0:b079fa4ed182	1324	#define HRTIM_MICR_MCMP1 ((uint32_t)0x00000001) /!< Master compare 1 interrupt flag clear /
richardv	0:b079fa4ed182	1325	#define HRTIM_MICR_MCMP2 ((uint32_t)0x00000002) /!< Master compare 2 interrupt flag clear /
richardv	0:b079fa4ed182	1326	#define HRTIM_MICR_MCMP3 ((uint32_t)0x00000004) /!< Master compare 3 interrupt flag clear /
richardv	0:b079fa4ed182	1327	#define HRTIM_MICR_MCMP4 ((uint32_t)0x00000008) /!< Master compare 4 interrupt flag clear /
richardv	0:b079fa4ed182	1328	#define HRTIM_MICR_MREP ((uint32_t)0x00000010) /!< Master Repetition interrupt flag clear /
richardv	0:b079fa4ed182	1329	#define HRTIM_MICR_SYNC ((uint32_t)0x00000020) /!< Synchronization input interrupt flag clear /
richardv	0:b079fa4ed182	1330	#define HRTIM_MICR_MUPD ((uint32_t)0x00000040) /!< Master update interrupt flag clear /
richardv	0:b079fa4ed182	1331
richardv	0:b079fa4ed182	1332	/****************** Master Timer DMA/Interrupt enable register ************/
richardv	0:b079fa4ed182	1333	#define HRTIM_MDIER_MCMP1IE ((uint32_t)0x00000001) /!< Master compare 1 interrupt enable /
richardv	0:b079fa4ed182	1334	#define HRTIM_MDIER_MCMP2IE ((uint32_t)0x00000002) /!< Master compare 2 interrupt enable /
richardv	0:b079fa4ed182	1335	#define HRTIM_MDIER_MCMP3IE ((uint32_t)0x00000004) /!< Master compare 3 interrupt enable /
richardv	0:b079fa4ed182	1336	#define HRTIM_MDIER_MCMP4IE ((uint32_t)0x00000008) /!< Master compare 4 interrupt enable /
richardv	0:b079fa4ed182	1337	#define HRTIM_MDIER_MREPIE ((uint32_t)0x00000010) /!< Master Repetition interrupt enable /
richardv	0:b079fa4ed182	1338	#define HRTIM_MDIER_SYNCIE ((uint32_t)0x00000020) /!< Synchronization input interrupt enable /
richardv	0:b079fa4ed182	1339	#define HRTIM_MDIER_MUPDIE ((uint32_t)0x00000040) /!< Master update interrupt enable /
richardv	0:b079fa4ed182	1340
richardv	0:b079fa4ed182	1341	#define HRTIM_MDIER_MCMP1DE ((uint32_t)0x00010000) /!< Master compare 1 DMA enable /
richardv	0:b079fa4ed182	1342	#define HRTIM_MDIER_MCMP2DE ((uint32_t)0x00020000) /!< Master compare 2 DMA enable /
richardv	0:b079fa4ed182	1343	#define HRTIM_MDIER_MCMP3DE ((uint32_t)0x00040000) /!< Master compare 3 DMA enable /
richardv	0:b079fa4ed182	1344	#define HRTIM_MDIER_MCMP4DE ((uint32_t)0x00080000) /!< Master compare 4 DMA enable /
richardv	0:b079fa4ed182	1345	#define HRTIM_MDIER_MREPDE ((uint32_t)0x00100000) /!< Master Repetition DMA enable /
richardv	0:b079fa4ed182	1346	#define HRTIM_MDIER_SYNCDE ((uint32_t)0x00200000) /!< Synchronization input DMA enable /
richardv	0:b079fa4ed182	1347	#define HRTIM_MDIER_MUPDDE ((uint32_t)0x00400000) /!< Master update DMA enable /
richardv	0:b079fa4ed182	1348
richardv	0:b079fa4ed182	1349	/***************** Bit definition for HRTIM_MCNTR register **************/
richardv	0:b079fa4ed182	1350	#define HRTIM_MCNTR_MCNTR ((uint32_t)0xFFFFFFFF) /!<Counter Value /
richardv	0:b079fa4ed182	1351
richardv	0:b079fa4ed182	1352	/***************** Bit definition for HRTIM_MPER register ***************/
richardv	0:b079fa4ed182	1353	#define HRTIM_MPER_MPER ((uint32_t)0xFFFFFFFF) /!< Period Value /
richardv	0:b079fa4ed182	1354
richardv	0:b079fa4ed182	1355	/***************** Bit definition for HRTIM_MREP register ***************/
richardv	0:b079fa4ed182	1356	#define HRTIM_MREP_MREP ((uint32_t)0xFFFFFFFF) /!<Repetition Value /
richardv	0:b079fa4ed182	1357
richardv	0:b079fa4ed182	1358	/***************** Bit definition for HRTIM_MCMP1R register ***************/
richardv	0:b079fa4ed182	1359	#define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /!<Compare Value /
richardv	0:b079fa4ed182	1360
richardv	0:b079fa4ed182	1361	/***************** Bit definition for HRTIM_MCMP2R register ***************/
richardv	0:b079fa4ed182	1362	#define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /!<Compare Value /
richardv	0:b079fa4ed182	1363
richardv	0:b079fa4ed182	1364	/***************** Bit definition for HRTIM_MCMP3R register ***************/
richardv	0:b079fa4ed182	1365	#define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /!<Compare Value /
richardv	0:b079fa4ed182	1366
richardv	0:b079fa4ed182	1367	/***************** Bit definition for HRTIM_MCMP4R register ***************/
richardv	0:b079fa4ed182	1368	#define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /!<Compare Value /
richardv	0:b079fa4ed182	1369
richardv	0:b079fa4ed182	1370	/****************** Slave control register ********************************/
richardv	0:b079fa4ed182	1371	#define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /!< Slave prescaler mask/
richardv	0:b079fa4ed182	1372	#define HRTIM_TIMCR_CK_PSC_0 ((uint32_t)0x00000001) /!< prescaler bit 0 /
richardv	0:b079fa4ed182	1373	#define HRTIM_TIMCR_CK_PSC_1 ((uint32_t)0x00000002) /!< prescaler bit 1 /
richardv	0:b079fa4ed182	1374	#define HRTIM_TIMCR_CK_PSC_2 ((uint32_t)0x00000004) /!< prescaler bit 2 /
richardv	0:b079fa4ed182	1375
richardv	0:b079fa4ed182	1376	#define HRTIM_TIMCR_CONT ((uint32_t)0x00000008) /!< Slave continuous mode /
richardv	0:b079fa4ed182	1377	#define HRTIM_TIMCR_RETRIG ((uint32_t)0x00000010) /!< Slave Retrigreable mode /
richardv	0:b079fa4ed182	1378	#define HRTIM_TIMCR_HALF ((uint32_t)0x00000020) /!< Slave Half mode /
richardv	0:b079fa4ed182	1379	#define HRTIM_TIMCR_PSHPLL ((uint32_t)0x00000040) /!< Slave push-pull mode /
richardv	0:b079fa4ed182	1380
richardv	0:b079fa4ed182	1381	#define HRTIM_TIMCR_SYNCRST ((uint32_t)0x00000400) /!< Slave synchronization resets /
richardv	0:b079fa4ed182	1382	#define HRTIM_TIMCR_SYNCSTRT ((uint32_t)0x00000800) /!< Slave synchronization starts /
richardv	0:b079fa4ed182	1383
richardv	0:b079fa4ed182	1384	#define HRTIM_TIMCR_DELCMP2 ((uint32_t)0x00003000) /!< Slave delayed comparator 2 mode mask /
richardv	0:b079fa4ed182	1385	#define HRTIM_TIMCR_DELCMP2_0 ((uint32_t)0x00001000) /!< Slave delayed comparator 2 bit 0 /
richardv	0:b079fa4ed182	1386	#define HRTIM_TIMCR_DELCMP2_1 ((uint32_t)0x00002000) /!< Slave delayed comparator 2 bit 1 /
richardv	0:b079fa4ed182	1387	#define HRTIM_TIMCR_DELCMP4 ((uint32_t)0x0000C000) /!< Slave delayed comparator 4 mode mask /
richardv	0:b079fa4ed182	1388	#define HRTIM_TIMCR_DELCMP4_0 ((uint32_t)0x00004000) /!< Slave delayed comparator 4 bit 0 /
richardv	0:b079fa4ed182	1389	#define HRTIM_TIMCR_DELCMP4_1 ((uint32_t)0x00008000) /!< Slave delayed comparator 4 bit 1 /
richardv	0:b079fa4ed182	1390
richardv	0:b079fa4ed182	1391	#define HRTIM_TIMCR_TREPU ((uint32_t)0x00020000) /!< Slave repetition update /
richardv	0:b079fa4ed182	1392	#define HRTIM_TIMCR_TRSTU ((uint32_t)0x00040000) /!< Slave reset update /
richardv	0:b079fa4ed182	1393	#define HRTIM_TIMCR_TAU ((uint32_t)0x00080000) /!< Slave Timer A update reserved for TIM A /
richardv	0:b079fa4ed182	1394	#define HRTIM_TIMCR_TBU ((uint32_t)0x00100000) /!< Slave Timer B update reserved for TIM B /
richardv	0:b079fa4ed182	1395	#define HRTIM_TIMCR_TCU ((uint32_t)0x00200000) /!< Slave Timer C update reserved for TIM C /
richardv	0:b079fa4ed182	1396	#define HRTIM_TIMCR_TDU ((uint32_t)0x00400000) /!< Slave Timer D update reserved for TIM D /
richardv	0:b079fa4ed182	1397	#define HRTIM_TIMCR_TEU ((uint32_t)0x00800000) /!< Slave Timer E update reserved for TIM E /
richardv	0:b079fa4ed182	1398	#define HRTIM_TIMCR_MSTU ((uint32_t)0x01000000) /!< Master Update /
richardv	0:b079fa4ed182	1399
richardv	0:b079fa4ed182	1400	#define HRTIM_TIMCR_DACSYNC ((uint32_t)0x06000000) /!< DAC synchronization mask /
richardv	0:b079fa4ed182	1401	#define HRTIM_TIMCR_DACSYNC_0 ((uint32_t)0x02000000) /!< DAC synchronization bit 0 /
richardv	0:b079fa4ed182	1402	#define HRTIM_TIMCR_DACSYNC_1 ((uint32_t)0x04000000) /!< DAC synchronization bit 1 /
richardv	0:b079fa4ed182	1403	#define HRTIM_TIMCR_PREEN ((uint32_t)0x08000000) /!< Slave preload enable /
richardv	0:b079fa4ed182	1404
richardv	0:b079fa4ed182	1405	#define HRTIM_TIMCR_UPDGAT ((uint32_t)0xF0000000) /!< Slave update gating mask /
richardv	0:b079fa4ed182	1406	#define HRTIM_TIMCR_UPDGAT_0 ((uint32_t)0x10000000) /!< Update gating bit 0 /
richardv	0:b079fa4ed182	1407	#define HRTIM_TIMCR_UPDGAT_1 ((uint32_t)0x20000000) /!< Update gating bit 1 /
richardv	0:b079fa4ed182	1408	#define HRTIM_TIMCR_UPDGAT_2 ((uint32_t)0x40000000) /!< Update gating bit 2 /
richardv	0:b079fa4ed182	1409	#define HRTIM_TIMCR_UPDGAT_3 ((uint32_t)0x80000000) /!< Update gating bit 3 /
richardv	0:b079fa4ed182	1410
richardv	0:b079fa4ed182	1411	/****************** Slave Interrupt status register ************************/
richardv	0:b079fa4ed182	1412	#define HRTIM_TIMISR_CMP1 ((uint32_t)0x00000001) /!< Slave compare 1 interrupt flag /
richardv	0:b079fa4ed182	1413	#define HRTIM_TIMISR_CMP2 ((uint32_t)0x00000002) /!< Slave compare 2 interrupt flag /
richardv	0:b079fa4ed182	1414	#define HRTIM_TIMISR_CMP3 ((uint32_t)0x00000004) /!< Slave compare 3 interrupt flag /
richardv	0:b079fa4ed182	1415	#define HRTIM_TIMISR_CMP4 ((uint32_t)0x00000008) /!< Slave compare 4 interrupt flag /
richardv	0:b079fa4ed182	1416	#define HRTIM_TIMISR_REP ((uint32_t)0x00000010) /!< Slave repetition interrupt flag /
richardv	0:b079fa4ed182	1417	#define HRTIM_TIMISR_UPD ((uint32_t)0x00000040) /!< Slave update interrupt flag /
richardv	0:b079fa4ed182	1418	#define HRTIM_TIMISR_CPT1 ((uint32_t)0x00000080) /!< Slave capture 1 interrupt flag /
richardv	0:b079fa4ed182	1419	#define HRTIM_TIMISR_CPT2 ((uint32_t)0x00000100) /!< Slave capture 2 interrupt flag /
richardv	0:b079fa4ed182	1420	#define HRTIM_TIMISR_SET1 ((uint32_t)0x00000200) /!< Slave output 1 set interrupt flag /
richardv	0:b079fa4ed182	1421	#define HRTIM_TIMISR_RST1 ((uint32_t)0x00000400) /!< Slave output 1 reset interrupt flag /
richardv	0:b079fa4ed182	1422	#define HRTIM_TIMISR_SET2 ((uint32_t)0x00000800) /!< Slave output 2 set interrupt flag /
richardv	0:b079fa4ed182	1423	#define HRTIM_TIMISR_RST2 ((uint32_t)0x00001000) /!< Slave output 2 reset interrupt flag /
richardv	0:b079fa4ed182	1424	#define HRTIM_TIMISR_RST ((uint32_t)0x00002000) /!< Slave reset interrupt flag /
richardv	0:b079fa4ed182	1425	#define HRTIM_TIMISR_DLYPRT ((uint32_t)0x00004000) /!< Slave output 1 delay protection interrupt flag /
richardv	0:b079fa4ed182	1426	#define HRTIM_TIMISR_CPPSTAT ((uint32_t)0x00010000) /!< Slave current push-pull flag /
richardv	0:b079fa4ed182	1427	#define HRTIM_TIMISR_IPPSTAT ((uint32_t)0x00020000) /!< Slave idle push-pull flag /
richardv	0:b079fa4ed182	1428	#define HRTIM_TIMISR_O1STAT ((uint32_t)0x00040000) /!< Slave output 1 state flag /
richardv	0:b079fa4ed182	1429	#define HRTIM_TIMISR_O2STAT ((uint32_t)0x00080000) /!< Slave output 2 state flag /
richardv	0:b079fa4ed182	1430	#define HRTIM_TIMISR_O1CPY ((uint32_t)0x00100000) /!< Slave output 1 copy flag /
richardv	0:b079fa4ed182	1431	#define HRTIM_TIMISR_O2CPY ((uint32_t)0x00200000) /!< Slave output 2 copy flag /
richardv	0:b079fa4ed182	1432
richardv	0:b079fa4ed182	1433	/****************** Slave Interrupt clear register ************************/
richardv	0:b079fa4ed182	1434	#define HRTIM_TIMICR_CMP1C ((uint32_t)0x00000001) /!< Slave compare 1 clear flag /
richardv	0:b079fa4ed182	1435	#define HRTIM_TIMICR_CMP2C ((uint32_t)0x00000002) /!< Slave compare 2 clear flag /
richardv	0:b079fa4ed182	1436	#define HRTIM_TIMICR_CMP3C ((uint32_t)0x00000004) /!< Slave compare 3 clear flag /
richardv	0:b079fa4ed182	1437	#define HRTIM_TIMICR_CMP4C ((uint32_t)0x00000008) /!< Slave compare 4 clear flag /
richardv	0:b079fa4ed182	1438	#define HRTIM_TIMICR_REPC ((uint32_t)0x00000010) /!< Slave repetition clear flag /
richardv	0:b079fa4ed182	1439	#define HRTIM_TIMICR_UPDC ((uint32_t)0x00000040) /!< Slave update clear flag /
richardv	0:b079fa4ed182	1440	#define HRTIM_TIMICR_CPT1C ((uint32_t)0x00000080) /!< Slave capture 1 clear flag /
richardv	0:b079fa4ed182	1441	#define HRTIM_TIMICR_CPT2C ((uint32_t)0x00000100) /!< Slave capture 2 clear flag /
richardv	0:b079fa4ed182	1442	#define HRTIM_TIMICR_SET1C ((uint32_t)0x00000200) /!< Slave output 1 set clear flag /
richardv	0:b079fa4ed182	1443	#define HRTIM_TIMICR_RST1C ((uint32_t)0x00000400) /!< Slave output 1 reset clear flag /
richardv	0:b079fa4ed182	1444	#define HRTIM_TIMICR_SET2C ((uint32_t)0x00000800) /!< Slave output 2 set clear flag /
richardv	0:b079fa4ed182	1445	#define HRTIM_TIMICR_RST2C ((uint32_t)0x00001000) /!< Slave output 2 reset clear flag /
richardv	0:b079fa4ed182	1446	#define HRTIM_TIMICR_RSTC ((uint32_t)0x00002000) /!< Slave reset clear flag /
richardv	0:b079fa4ed182	1447	#define HRTIM_TIMICR_DLYPRT1C ((uint32_t)0x00004000) /!< Slave output 1 delay protection clear flag /
richardv	0:b079fa4ed182	1448	#define HRTIM_TIMICR_DLYPRT2C ((uint32_t)0x00008000) /!< Slave output 2 delay protection clear flag /
richardv	0:b079fa4ed182	1449
richardv	0:b079fa4ed182	1450	/****************** Slave DMA/Interrupt enable register *******************/
richardv	0:b079fa4ed182	1451	#define HRTIM_TIMDIER_CMP1IE ((uint32_t)0x00000001) /!< Slave compare 1 interrupt enable /
richardv	0:b079fa4ed182	1452	#define HRTIM_TIMDIER_CMP2IE ((uint32_t)0x00000002) /!< Slave compare 2 interrupt enable /
richardv	0:b079fa4ed182	1453	#define HRTIM_TIMDIER_CMP3IE ((uint32_t)0x00000004) /!< Slave compare 3 interrupt enable /
richardv	0:b079fa4ed182	1454	#define HRTIM_TIMDIER_CMP4IE ((uint32_t)0x00000008) /!< Slave compare 4 interrupt enable /
richardv	0:b079fa4ed182	1455	#define HRTIM_TIMDIER_REPIE ((uint32_t)0x00000010) /!< Slave repetition interrupt enable /
richardv	0:b079fa4ed182	1456	#define HRTIM_TIMDIER_UPDIE ((uint32_t)0x00000040) /!< Slave update interrupt enable /
richardv	0:b079fa4ed182	1457	#define HRTIM_TIMDIER_CPT1IE ((uint32_t)0x00000080) /!< Slave capture 1 interrupt enable /
richardv	0:b079fa4ed182	1458	#define HRTIM_TIMDIER_CPT2IE ((uint32_t)0x00000100) /!< Slave capture 2 interrupt enable /
richardv	0:b079fa4ed182	1459	#define HRTIM_TIMDIER_SET1IE ((uint32_t)0x00000200) /!< Slave output 1 set interrupt enable /
richardv	0:b079fa4ed182	1460	#define HRTIM_TIMDIER_RST1IE ((uint32_t)0x00000400) /!< Slave output 1 reset interrupt enable /
richardv	0:b079fa4ed182	1461	#define HRTIM_TIMDIER_SET2IE ((uint32_t)0x00000800) /!< Slave output 2 set interrupt enable /
richardv	0:b079fa4ed182	1462	#define HRTIM_TIMDIER_RST2IE ((uint32_t)0x00001000) /!< Slave output 2 reset interrupt enable /
richardv	0:b079fa4ed182	1463	#define HRTIM_TIMDIER_RSTIE ((uint32_t)0x00002000) /!< Slave reset interrupt enable /
richardv	0:b079fa4ed182	1464	#define HRTIM_TIMDIER_DLYPRTIE ((uint32_t)0x00004000) /!< Slave delay protection interrupt enable /
richardv	0:b079fa4ed182	1465
richardv	0:b079fa4ed182	1466	#define HRTIM_TIMDIER_CMP1DE ((uint32_t)0x00010000) /!< Slave compare 1 request enable /
richardv	0:b079fa4ed182	1467	#define HRTIM_TIMDIER_CMP2DE ((uint32_t)0x00020000) /!< Slave compare 2 request enable /
richardv	0:b079fa4ed182	1468	#define HRTIM_TIMDIER_CMP3DE ((uint32_t)0x00040000) /!< Slave compare 3 request enable /
richardv	0:b079fa4ed182	1469	#define HRTIM_TIMDIER_CMP4DE ((uint32_t)0x00080000) /!< Slave compare 4 request enable /
richardv	0:b079fa4ed182	1470	#define HRTIM_TIMDIER_REPDE ((uint32_t)0x00100000) /!< Slave repetition request enable /
richardv	0:b079fa4ed182	1471	#define HRTIM_TIMDIER_UPDDE ((uint32_t)0x00400000) /!< Slave update request enable /
richardv	0:b079fa4ed182	1472	#define HRTIM_TIMDIER_CPT1DE ((uint32_t)0x00800000) /!< Slave capture 1 request enable /
richardv	0:b079fa4ed182	1473	#define HRTIM_TIMDIER_CPT2DE ((uint32_t)0x01000000) /!< Slave capture 2 request enable /
richardv	0:b079fa4ed182	1474	#define HRTIM_TIMDIER_SET1DE ((uint32_t)0x02000000) /!< Slave output 1 set request enable /
richardv	0:b079fa4ed182	1475	#define HRTIM_TIMDIER_RST1DE ((uint32_t)0x04000000) /!< Slave output 1 reset request enable /
richardv	0:b079fa4ed182	1476	#define HRTIM_TIMDIER_SET2DE ((uint32_t)0x08000000) /!< Slave output 2 set request enable /
richardv	0:b079fa4ed182	1477	#define HRTIM_TIMDIER_RST2DE ((uint32_t)0x10000000) /!< Slave output 2 reset request enable /
richardv	0:b079fa4ed182	1478	#define HRTIM_TIMDIER_RSTDE ((uint32_t)0x20000000) /!< Slave reset request enable /
richardv	0:b079fa4ed182	1479	#define HRTIM_TIMDIER_DLYPRTDE ((uint32_t)0x40000000) /!< Slave delay protection request enable /
richardv	0:b079fa4ed182	1480
richardv	0:b079fa4ed182	1481	/**************** Bit definition for HRTIM_CNTR register **************/
richardv	0:b079fa4ed182	1482	#define HRTIM_CNTR_CNTR ((uint32_t)0xFFFFFFFF) /!< Counter Value /
richardv	0:b079fa4ed182	1483
richardv	0:b079fa4ed182	1484	/***************** Bit definition for HRTIM_PER register ***************/
richardv	0:b079fa4ed182	1485	#define HRTIM_PER_PER ((uint32_t)0xFFFFFFFF) /!< Period Value /
richardv	0:b079fa4ed182	1486
richardv	0:b079fa4ed182	1487	/***************** Bit definition for HRTIM_REP register ***************/
richardv	0:b079fa4ed182	1488	#define HRTIM_REP_REP ((uint32_t)0xFFFFFFFF) /!< Repetition Value /
richardv	0:b079fa4ed182	1489
richardv	0:b079fa4ed182	1490	/***************** Bit definition for HRTIM_CMP1R register ***************/
richardv	0:b079fa4ed182	1491	#define HRTIM_CMP1R_CMP1R ((uint32_t)0xFFFFFFFF) /!< Compare Value /
richardv	0:b079fa4ed182	1492
richardv	0:b079fa4ed182	1493	/***************** Bit definition for HRTIM_CMP1CR register ***************/
richardv	0:b079fa4ed182	1494	#define HRTIM_CMP1CR_CMP1CR ((uint32_t)0xFFFFFFFF) /!< Compare Value /
richardv	0:b079fa4ed182	1495
richardv	0:b079fa4ed182	1496	/***************** Bit definition for HRTIM_CMP2R register ***************/
richardv	0:b079fa4ed182	1497	#define HRTIM_CMP2R_CMP2R ((uint32_t)0xFFFFFFFF) /!< Compare Value /
richardv	0:b079fa4ed182	1498
richardv	0:b079fa4ed182	1499	/***************** Bit definition for HRTIM_CMP3R register ***************/
richardv	0:b079fa4ed182	1500	#define HRTIM_CMP3R_CMP3R ((uint32_t)0xFFFFFFFF) /!< Compare Value /
richardv	0:b079fa4ed182	1501
richardv	0:b079fa4ed182	1502	/***************** Bit definition for HRTIM_CMP4R register ***************/
richardv	0:b079fa4ed182	1503	#define HRTIM_CMP4R_CMP4R ((uint32_t)0xFFFFFFFF) /!< Compare Value /
richardv	0:b079fa4ed182	1504
richardv	0:b079fa4ed182	1505	/***************** Bit definition for HRTIM_CPT1R register **************/
richardv	0:b079fa4ed182	1506	#define HRTIM_CPT1R_CPT1R ((uint32_t)0xFFFFFFFF) /!< Capture Value /
richardv	0:b079fa4ed182	1507
richardv	0:b079fa4ed182	1508	/***************** Bit definition for HRTIM_CPT2R register **************/
richardv	0:b079fa4ed182	1509	#define HRTIM_CPT2R_CPT2R ((uint32_t)0xFFFFFFFF) /!< Capture Value /
richardv	0:b079fa4ed182	1510
richardv	0:b079fa4ed182	1511	/****************** Bit definition for Slave Deadtime register ************/
richardv	0:b079fa4ed182	1512	#define HRTIM_DTR_DTR ((uint32_t)0x000001FF) /!< Dead time rising value /
richardv	0:b079fa4ed182	1513	#define HRTIM_DTR_DTR_0 ((uint32_t)0x00000001) /!< Dead time rising bit 0 /
richardv	0:b079fa4ed182	1514	#define HRTIM_DTR_DTR_1 ((uint32_t)0x00000002) /!< Dead time rising bit 1 /
richardv	0:b079fa4ed182	1515	#define HRTIM_DTR_DTR_2 ((uint32_t)0x00000004) /!< Dead time rising bit 2 /
richardv	0:b079fa4ed182	1516	#define HRTIM_DTR_DTR_3 ((uint32_t)0x00000008) /!< Dead time rising bit 3 /
richardv	0:b079fa4ed182	1517	#define HRTIM_DTR_DTR_4 ((uint32_t)0x00000010) /!< Dead time rising bit 4 /
richardv	0:b079fa4ed182	1518	#define HRTIM_DTR_DTR_5 ((uint32_t)0x00000020) /!< Dead time rising bit 5 /
richardv	0:b079fa4ed182	1519	#define HRTIM_DTR_DTR_6 ((uint32_t)0x00000040) /!< Dead time rising bit 6 /
richardv	0:b079fa4ed182	1520	#define HRTIM_DTR_DTR_7 ((uint32_t)0x00000080) /!< Dead time rising bit 7 /
richardv	0:b079fa4ed182	1521	#define HRTIM_DTR_DTR_8 ((uint32_t)0x00000100) /!< Dead time rising bit 8 /
richardv	0:b079fa4ed182	1522	#define HRTIM_DTR_SDTR ((uint32_t)0x00000200) /!< Sign dead time rising value /
richardv	0:b079fa4ed182	1523	#define HRTIM_DTR_DTPRSC ((uint32_t)0x00001C00) /!< Dead time prescaler /
richardv	0:b079fa4ed182	1524	#define HRTIM_DTR_DTPRSC_0 ((uint32_t)0x00000400) /!< Dead time prescaler bit 0 /
richardv	0:b079fa4ed182	1525	#define HRTIM_DTR_DTPRSC_1 ((uint32_t)0x00000800) /!< Dead time prescaler bit 1 /
richardv	0:b079fa4ed182	1526	#define HRTIM_DTR_DTPRSC_2 ((uint32_t)0x00001000) /!< Dead time prescaler bit 2 /
richardv	0:b079fa4ed182	1527	#define HRTIM_DTR_DTRSLK ((uint32_t)0x00004000) /!< Dead time rising sign lock /
richardv	0:b079fa4ed182	1528	#define HRTIM_DTR_DTRLK ((uint32_t)0x00008000) /!< Dead time rising lock /
richardv	0:b079fa4ed182	1529	#define HRTIM_DTR_DTF ((uint32_t)0x01FF0000) /!< Dead time falling value /
richardv	0:b079fa4ed182	1530	#define HRTIM_DTR_DTF_0 ((uint32_t)0x00010000) /!< Dead time falling bit 0 /
richardv	0:b079fa4ed182	1531	#define HRTIM_DTR_DTF_1 ((uint32_t)0x00020000) /!< Dead time falling bit 1 /
richardv	0:b079fa4ed182	1532	#define HRTIM_DTR_DTF_2 ((uint32_t)0x00040000) /!< Dead time falling bit 2 /
richardv	0:b079fa4ed182	1533	#define HRTIM_DTR_DTF_3 ((uint32_t)0x00080000) /!< Dead time falling bit 3 /
richardv	0:b079fa4ed182	1534	#define HRTIM_DTR_DTF_4 ((uint32_t)0x00100000) /!< Dead time falling bit 4 /
richardv	0:b079fa4ed182	1535	#define HRTIM_DTR_DTF_5 ((uint32_t)0x00200000) /!< Dead time falling bit 5 /
richardv	0:b079fa4ed182	1536	#define HRTIM_DTR_DTF_6 ((uint32_t)0x00400000) /!< Dead time falling bit 6 /
richardv	0:b079fa4ed182	1537	#define HRTIM_DTR_DTF_7 ((uint32_t)0x00800000) /!< Dead time falling bit 7 /
richardv	0:b079fa4ed182	1538	#define HRTIM_DTR_DTF_8 ((uint32_t)0x01000000) /!< Dead time falling bit 8 /
richardv	0:b079fa4ed182	1539	#define HRTIM_DTR_SDTF ((uint32_t)0x02000000) /!< Sign dead time falling value /
richardv	0:b079fa4ed182	1540	#define HRTIM_DTR_DTFSLK ((uint32_t)0x40000000) /!< Dead time falling sign lock /
richardv	0:b079fa4ed182	1541	#define HRTIM_DTR_DTFLK ((uint32_t)0x80000000) /!< Dead time falling lock /
richardv	0:b079fa4ed182	1542
richardv	0:b079fa4ed182	1543	/** Bit definition for Slave Output 1 set register ************************/
richardv	0:b079fa4ed182	1544	#define HRTIM_SET1R_SST ((uint32_t)0x00000001) /!< software set trigger /
richardv	0:b079fa4ed182	1545	#define HRTIM_SET1R_RESYNC ((uint32_t)0x00000002) /!< Timer A resynchronization /
richardv	0:b079fa4ed182	1546	#define HRTIM_SET1R_PER ((uint32_t)0x00000004) /!< Timer A period /
richardv	0:b079fa4ed182	1547	#define HRTIM_SET1R_CMP1 ((uint32_t)0x00000008) /!< Timer A compare 1 /
richardv	0:b079fa4ed182	1548	#define HRTIM_SET1R_CMP2 ((uint32_t)0x00000010) /!< Timer A compare 2 /
richardv	0:b079fa4ed182	1549	#define HRTIM_SET1R_CMP3 ((uint32_t)0x00000020) /!< Timer A compare 3 /
richardv	0:b079fa4ed182	1550	#define HRTIM_SET1R_CMP4 ((uint32_t)0x00000040) /!< Timer A compare 4 /
richardv	0:b079fa4ed182	1551
richardv	0:b079fa4ed182	1552	#define HRTIM_SET1R_MSTPER ((uint32_t)0x00000080) /!< Master period /
richardv	0:b079fa4ed182	1553	#define HRTIM_SET1R_MSTCMP1 ((uint32_t)0x00000100) /!< Master compare 1 /
richardv	0:b079fa4ed182	1554	#define HRTIM_SET1R_MSTCMP2 ((uint32_t)0x00000200) /!< Master compare 2 /
richardv	0:b079fa4ed182	1555	#define HRTIM_SET1R_MSTCMP3 ((uint32_t)0x00000400) /!< Master compare 3 /
richardv	0:b079fa4ed182	1556	#define HRTIM_SET1R_MSTCMP4 ((uint32_t)0x00000800) /!< Master compare 4 /
richardv	0:b079fa4ed182	1557
richardv	0:b079fa4ed182	1558	#define HRTIM_SET1R_TIMEVNT1 ((uint32_t)0x00001000) /!< Timer event 1 /
richardv	0:b079fa4ed182	1559	#define HRTIM_SET1R_TIMEVNT2 ((uint32_t)0x00002000) /!< Timer event 2 /
richardv	0:b079fa4ed182	1560	#define HRTIM_SET1R_TIMEVNT3 ((uint32_t)0x00004000) /!< Timer event 3 /
richardv	0:b079fa4ed182	1561	#define HRTIM_SET1R_TIMEVNT4 ((uint32_t)0x00008000) /!< Timer event 4 /
richardv	0:b079fa4ed182	1562	#define HRTIM_SET1R_TIMEVNT5 ((uint32_t)0x00010000) /!< Timer event 5 /
richardv	0:b079fa4ed182	1563	#define HRTIM_SET1R_TIMEVNT6 ((uint32_t)0x00020000) /!< Timer event 6 /
richardv	0:b079fa4ed182	1564	#define HRTIM_SET1R_TIMEVNT7 ((uint32_t)0x00040000) /!< Timer event 7 /
richardv	0:b079fa4ed182	1565	#define HRTIM_SET1R_TIMEVNT8 ((uint32_t)0x00080000) /!< Timer event 8 /
richardv	0:b079fa4ed182	1566	#define HRTIM_SET1R_TIMEVNT9 ((uint32_t)0x00100000) /!< Timer event 9 /
richardv	0:b079fa4ed182	1567
richardv	0:b079fa4ed182	1568	#define HRTIM_SET1R_EXTVNT1 ((uint32_t)0x00200000) /!< External event 1 /
richardv	0:b079fa4ed182	1569	#define HRTIM_SET1R_EXTVNT2 ((uint32_t)0x00400000) /!< External event 2 /
richardv	0:b079fa4ed182	1570	#define HRTIM_SET1R_EXTVNT3 ((uint32_t)0x00800000) /!< External event 3 /
richardv	0:b079fa4ed182	1571	#define HRTIM_SET1R_EXTVNT4 ((uint32_t)0x01000000) /!< External event 4 /
richardv	0:b079fa4ed182	1572	#define HRTIM_SET1R_EXTVNT5 ((uint32_t)0x02000000) /!< External event 5 /
richardv	0:b079fa4ed182	1573	#define HRTIM_SET1R_EXTVNT6 ((uint32_t)0x04000000) /!< External event 6 /
richardv	0:b079fa4ed182	1574	#define HRTIM_SET1R_EXTVNT7 ((uint32_t)0x08000000) /!< External event 7 /
richardv	0:b079fa4ed182	1575	#define HRTIM_SET1R_EXTVNT8 ((uint32_t)0x10000000) /!< External event 8 /
richardv	0:b079fa4ed182	1576	#define HRTIM_SET1R_EXTVNT9 ((uint32_t)0x20000000) /!< External event 9 /
richardv	0:b079fa4ed182	1577	#define HRTIM_SET1R_EXTVNT10 ((uint32_t)0x40000000) /!< External event 10 /
richardv	0:b079fa4ed182	1578
richardv	0:b079fa4ed182	1579	#define HRTIM_SET1R_UPDATE ((uint32_t)0x80000000) /!< Register update (transfer preload to active) /
richardv	0:b079fa4ed182	1580
richardv	0:b079fa4ed182	1581	/** Bit definition for Slave Output 1 reset register **********************/
richardv	0:b079fa4ed182	1582	#define HRTIM_RST1R_SRT ((uint32_t)0x00000001) /!< software reset trigger /
richardv	0:b079fa4ed182	1583	#define HRTIM_RST1R_RESYNC ((uint32_t)0x00000002) /!< Timer A resynchronization /
richardv	0:b079fa4ed182	1584	#define HRTIM_RST1R_PER ((uint32_t)0x00000004) /!< Timer A period /
richardv	0:b079fa4ed182	1585	#define HRTIM_RST1R_CMP1 ((uint32_t)0x00000008) /!< Timer A compare 1 /
richardv	0:b079fa4ed182	1586	#define HRTIM_RST1R_CMP2 ((uint32_t)0x00000010) /!< Timer A compare 2 /
richardv	0:b079fa4ed182	1587	#define HRTIM_RST1R_CMP3 ((uint32_t)0x00000020) /!< Timer A compare 3 /
richardv	0:b079fa4ed182	1588	#define HRTIM_RST1R_CMP4 ((uint32_t)0x00000040) /!< Timer A compare 4 /
richardv	0:b079fa4ed182	1589
richardv	0:b079fa4ed182	1590	#define HRTIM_RST1R_MSTPER ((uint32_t)0x00000080) /!< Master period /
richardv	0:b079fa4ed182	1591	#define HRTIM_RST1R_MSTCMP1 ((uint32_t)0x00000100) /!< Master compare 1 /
richardv	0:b079fa4ed182	1592	#define HRTIM_RST1R_MSTCMP2 ((uint32_t)0x00000200) /!< Master compare 2 /
richardv	0:b079fa4ed182	1593	#define HRTIM_RST1R_MSTCMP3 ((uint32_t)0x00000400) /!< Master compare 3 /
richardv	0:b079fa4ed182	1594	#define HRTIM_RST1R_MSTCMP4 ((uint32_t)0x00000800) /!< Master compare 4 /
richardv	0:b079fa4ed182	1595
richardv	0:b079fa4ed182	1596	#define HRTIM_RST1R_TIMEVNT1 ((uint32_t)0x00001000) /!< Timer event 1 /
richardv	0:b079fa4ed182	1597	#define HRTIM_RST1R_TIMEVNT2 ((uint32_t)0x00002000) /!< Timer event 2 /
richardv	0:b079fa4ed182	1598	#define HRTIM_RST1R_TIMEVNT3 ((uint32_t)0x00004000) /!< Timer event 3 /
richardv	0:b079fa4ed182	1599	#define HRTIM_RST1R_TIMEVNT4 ((uint32_t)0x00008000) /!< Timer event 4 /
richardv	0:b079fa4ed182	1600	#define HRTIM_RST1R_TIMEVNT5 ((uint32_t)0x00010000) /!< Timer event 5 /
richardv	0:b079fa4ed182	1601	#define HRTIM_RST1R_TIMEVNT6 ((uint32_t)0x00020000) /!< Timer event 6 /
richardv	0:b079fa4ed182	1602	#define HRTIM_RST1R_TIMEVNT7 ((uint32_t)0x00040000) /!< Timer event 7 /
richardv	0:b079fa4ed182	1603	#define HRTIM_RST1R_TIMEVNT8 ((uint32_t)0x00080000) /!< Timer event 8 /
richardv	0:b079fa4ed182	1604	#define HRTIM_RST1R_TIMEVNT9 ((uint32_t)0x00100000) /!< Timer event 9 /
richardv	0:b079fa4ed182	1605
richardv	0:b079fa4ed182	1606	#define HRTIM_RST1R_EXTVNT1 ((uint32_t)0x00200000) /!< External event 1 /
richardv	0:b079fa4ed182	1607	#define HRTIM_RST1R_EXTVNT2 ((uint32_t)0x00400000) /!< External event 2 /
richardv	0:b079fa4ed182	1608	#define HRTIM_RST1R_EXTVNT3 ((uint32_t)0x00800000) /!< External event 3 /
richardv	0:b079fa4ed182	1609	#define HRTIM_RST1R_EXTVNT4 ((uint32_t)0x01000000) /!< External event 4 /
richardv	0:b079fa4ed182	1610	#define HRTIM_RST1R_EXTVNT5 ((uint32_t)0x02000000) /!< External event 5 /
richardv	0:b079fa4ed182	1611	#define HRTIM_RST1R_EXTVNT6 ((uint32_t)0x04000000) /!< External event 6 /
richardv	0:b079fa4ed182	1612	#define HRTIM_RST1R_EXTVNT7 ((uint32_t)0x08000000) /!< External event 7 /
richardv	0:b079fa4ed182	1613	#define HRTIM_RST1R_EXTVNT8 ((uint32_t)0x10000000) /!< External event 8 /
richardv	0:b079fa4ed182	1614	#define HRTIM_RST1R_EXTVNT9 ((uint32_t)0x20000000) /!< External event 9 /
richardv	0:b079fa4ed182	1615	#define HRTIM_RST1R_EXTVNT10 ((uint32_t)0x40000000) /!< External event 10 /
richardv	0:b079fa4ed182	1616
richardv	0:b079fa4ed182	1617	#define HRTIM_RST1R_UPDATE ((uint32_t)0x80000000) /!< Register update (transfer preload to active) /
richardv	0:b079fa4ed182	1618
richardv	0:b079fa4ed182	1619
richardv	0:b079fa4ed182	1620	/** Bit definition for Slave Output 2 set register ************************/
richardv	0:b079fa4ed182	1621	#define HRTIM_SET2R_SST ((uint32_t)0x00000001) /!< software set trigger /
richardv	0:b079fa4ed182	1622	#define HRTIM_SET2R_RESYNC ((uint32_t)0x00000002) /!< Timer A resynchronization /
richardv	0:b079fa4ed182	1623	#define HRTIM_SET2R_PER ((uint32_t)0x00000004) /!< Timer A period /
richardv	0:b079fa4ed182	1624	#define HRTIM_SET2R_CMP1 ((uint32_t)0x00000008) /!< Timer A compare 1 /
richardv	0:b079fa4ed182	1625	#define HRTIM_SET2R_CMP2 ((uint32_t)0x00000010) /!< Timer A compare 2 /
richardv	0:b079fa4ed182	1626	#define HRTIM_SET2R_CMP3 ((uint32_t)0x00000020) /!< Timer A compare 3 /
richardv	0:b079fa4ed182	1627	#define HRTIM_SET2R_CMP4 ((uint32_t)0x00000040) /!< Timer A compare 4 /
richardv	0:b079fa4ed182	1628
richardv	0:b079fa4ed182	1629	#define HRTIM_SET2R_MSTPER ((uint32_t)0x00000080) /!< Master period /
richardv	0:b079fa4ed182	1630	#define HRTIM_SET2R_MSTCMP1 ((uint32_t)0x00000100) /!< Master compare 1 /
richardv	0:b079fa4ed182	1631	#define HRTIM_SET2R_MSTCMP2 ((uint32_t)0x00000200) /!< Master compare 2 /
richardv	0:b079fa4ed182	1632	#define HRTIM_SET2R_MSTCMP3 ((uint32_t)0x00000400) /!< Master compare 3 /
richardv	0:b079fa4ed182	1633	#define HRTIM_SET2R_MSTCMP4 ((uint32_t)0x00000800) /!< Master compare 4 /
richardv	0:b079fa4ed182	1634
richardv	0:b079fa4ed182	1635	#define HRTIM_SET2R_TIMEVNT1 ((uint32_t)0x00001000) /!< Timer event 1 /
richardv	0:b079fa4ed182	1636	#define HRTIM_SET2R_TIMEVNT2 ((uint32_t)0x00002000) /!< Timer event 2 /
richardv	0:b079fa4ed182	1637	#define HRTIM_SET2R_TIMEVNT3 ((uint32_t)0x00004000) /!< Timer event 3 /
richardv	0:b079fa4ed182	1638	#define HRTIM_SET2R_TIMEVNT4 ((uint32_t)0x00008000) /!< Timer event 4 /
richardv	0:b079fa4ed182	1639	#define HRTIM_SET2R_TIMEVNT5 ((uint32_t)0x00010000) /!< Timer event 5 /
richardv	0:b079fa4ed182	1640	#define HRTIM_SET2R_TIMEVNT6 ((uint32_t)0x00020000) /!< Timer event 6 /
richardv	0:b079fa4ed182	1641	#define HRTIM_SET2R_TIMEVNT7 ((uint32_t)0x00040000) /!< Timer event 7 /
richardv	0:b079fa4ed182	1642	#define HRTIM_SET2R_TIMEVNT8 ((uint32_t)0x00080000) /!< Timer event 8 /
richardv	0:b079fa4ed182	1643	#define HRTIM_SET2R_TIMEVNT9 ((uint32_t)0x00100000) /!< Timer event 9 /
richardv	0:b079fa4ed182	1644
richardv	0:b079fa4ed182	1645	#define HRTIM_SET2R_EXTVNT1 ((uint32_t)0x00200000) /!< External event 1 /
richardv	0:b079fa4ed182	1646	#define HRTIM_SET2R_EXTVNT2 ((uint32_t)0x00400000) /!< External event 2 /
richardv	0:b079fa4ed182	1647	#define HRTIM_SET2R_EXTVNT3 ((uint32_t)0x00800000) /!< External event 3 /
richardv	0:b079fa4ed182	1648	#define HRTIM_SET2R_EXTVNT4 ((uint32_t)0x01000000) /!< External event 4 /
richardv	0:b079fa4ed182	1649	#define HRTIM_SET2R_EXTVNT5 ((uint32_t)0x02000000) /!< External event 5 /
richardv	0:b079fa4ed182	1650	#define HRTIM_SET2R_EXTVNT6 ((uint32_t)0x04000000) /!< External event 6 /
richardv	0:b079fa4ed182	1651	#define HRTIM_SET2R_EXTVNT7 ((uint32_t)0x08000000) /!< External event 7 /
richardv	0:b079fa4ed182	1652	#define HRTIM_SET2R_EXTVNT8 ((uint32_t)0x10000000) /!< External event 8 /
richardv	0:b079fa4ed182	1653	#define HRTIM_SET2R_EXTVNT9 ((uint32_t)0x20000000) /!< External event 9 /
richardv	0:b079fa4ed182	1654	#define HRTIM_SET2R_EXTVNT10 ((uint32_t)0x40000000) /!< External event 10 /
richardv	0:b079fa4ed182	1655
richardv	0:b079fa4ed182	1656	#define HRTIM_SET2R_UPDATE ((uint32_t)0x80000000) /!< Register update (transfer preload to active) /
richardv	0:b079fa4ed182	1657
richardv	0:b079fa4ed182	1658	/** Bit definition for Slave Output 2 reset register **********************/
richardv	0:b079fa4ed182	1659	#define HRTIM_RST2R_SRT ((uint32_t)0x00000001) /!< software reset trigger /
richardv	0:b079fa4ed182	1660	#define HRTIM_RST2R_RESYNC ((uint32_t)0x00000002) /!< Timer A resynchronization /
richardv	0:b079fa4ed182	1661	#define HRTIM_RST2R_PER ((uint32_t)0x00000004) /!< Timer A period /
richardv	0:b079fa4ed182	1662	#define HRTIM_RST2R_CMP1 ((uint32_t)0x00000008) /!< Timer A compare 1 /
richardv	0:b079fa4ed182	1663	#define HRTIM_RST2R_CMP2 ((uint32_t)0x00000010) /!< Timer A compare 2 /
richardv	0:b079fa4ed182	1664	#define HRTIM_RST2R_CMP3 ((uint32_t)0x00000020) /!< Timer A compare 3 /
richardv	0:b079fa4ed182	1665	#define HRTIM_RST2R_CMP4 ((uint32_t)0x00000040) /!< Timer A compare 4 /
richardv	0:b079fa4ed182	1666
richardv	0:b079fa4ed182	1667	#define HRTIM_RST2R_MSTPER ((uint32_t)0x00000080) /!< Master period /
richardv	0:b079fa4ed182	1668	#define HRTIM_RST2R_MSTCMP1 ((uint32_t)0x00000100) /!< Master compare 1 /
richardv	0:b079fa4ed182	1669	#define HRTIM_RST2R_MSTCMP2 ((uint32_t)0x00000200) /!< Master compare 2 /
richardv	0:b079fa4ed182	1670	#define HRTIM_RST2R_MSTCMP3 ((uint32_t)0x00000400) /!< Master compare 3 /
richardv	0:b079fa4ed182	1671	#define HRTIM_RST2R_MSTCMP4 ((uint32_t)0x00000800) /!< Master compare 4 /
richardv	0:b079fa4ed182	1672
richardv	0:b079fa4ed182	1673	#define HRTIM_RST2R_TIMEVNT1 ((uint32_t)0x00001000) /!< Timer event 1 /
richardv	0:b079fa4ed182	1674	#define HRTIM_RST2R_TIMEVNT2 ((uint32_t)0x00002000) /!< Timer event 2 /
richardv	0:b079fa4ed182	1675	#define HRTIM_RST2R_TIMEVNT3 ((uint32_t)0x00004000) /!< Timer event 3 /
richardv	0:b079fa4ed182	1676	#define HRTIM_RST2R_TIMEVNT4 ((uint32_t)0x00008000) /!< Timer event 4 /
richardv	0:b079fa4ed182	1677	#define HRTIM_RST2R_TIMEVNT5 ((uint32_t)0x00010000) /!< Timer event 5 /
richardv	0:b079fa4ed182	1678	#define HRTIM_RST2R_TIMEVNT6 ((uint32_t)0x00020000) /!< Timer event 6 /
richardv	0:b079fa4ed182	1679	#define HRTIM_RST2R_TIMEVNT7 ((uint32_t)0x00040000) /!< Timer event 7 /
richardv	0:b079fa4ed182	1680	#define HRTIM_RST2R_TIMEVNT8 ((uint32_t)0x00080000) /!< Timer event 8 /
richardv	0:b079fa4ed182	1681	#define HRTIM_RST2R_TIMEVNT9 ((uint32_t)0x00100000) /!< Timer event 9 /
richardv	0:b079fa4ed182	1682
richardv	0:b079fa4ed182	1683	#define HRTIM_RST2R_EXTVNT1 ((uint32_t)0x00200000) /!< External event 1 /
richardv	0:b079fa4ed182	1684	#define HRTIM_RST2R_EXTVNT2 ((uint32_t)0x00400000) /!< External event 2 /
richardv	0:b079fa4ed182	1685	#define HRTIM_RST2R_EXTVNT3 ((uint32_t)0x00800000) /!< External event 3 /
richardv	0:b079fa4ed182	1686	#define HRTIM_RST2R_EXTVNT4 ((uint32_t)0x01000000) /!< External event 4 /
richardv	0:b079fa4ed182	1687	#define HRTIM_RST2R_EXTVNT5 ((uint32_t)0x02000000) /!< External event 5 /
richardv	0:b079fa4ed182	1688	#define HRTIM_RST2R_EXTVNT6 ((uint32_t)0x04000000) /!< External event 6 /
richardv	0:b079fa4ed182	1689	#define HRTIM_RST2R_EXTVNT7 ((uint32_t)0x08000000) /!< External event 7 /
richardv	0:b079fa4ed182	1690	#define HRTIM_RST2R_EXTVNT8 ((uint32_t)0x10000000) /!< External event 8 /
richardv	0:b079fa4ed182	1691	#define HRTIM_RST2R_EXTVNT9 ((uint32_t)0x20000000) /!< External event 9 /
richardv	0:b079fa4ed182	1692	#define HRTIM_RST2R_EXTVNT10 ((uint32_t)0x40000000) /!< External event 10 /
richardv	0:b079fa4ed182	1693
richardv	0:b079fa4ed182	1694	#define HRTIM_RST2R_UPDATE ((uint32_t)0x80000000) /!< Register update (transfer preload to active) /
richardv	0:b079fa4ed182	1695
richardv	0:b079fa4ed182	1696	/** Bit definition for Slave external event filtering register 1 *********/
richardv	0:b079fa4ed182	1697	#define HRTIM_EEFR1_EE1LTCH ((uint32_t)0x00000001) /!< External Event 1 latch /
richardv	0:b079fa4ed182	1698	#define HRTIM_EEFR1_EE1FLTR ((uint32_t)0x0000001E) /!< External Event 1 filter mask /
richardv	0:b079fa4ed182	1699	#define HRTIM_EEFR1_EE1FLTR_0 ((uint32_t)0x00000002) /!< External Event 1 bit 0 /
richardv	0:b079fa4ed182	1700	#define HRTIM_EEFR1_EE1FLTR_1 ((uint32_t)0x00000004) /!< External Event 1 bit 1/
richardv	0:b079fa4ed182	1701	#define HRTIM_EEFR1_EE1FLTR_2 ((uint32_t)0x00000008) /!< External Event 1 bit 2 /
richardv	0:b079fa4ed182	1702	#define HRTIM_EEFR1_EE1FLTR_3 ((uint32_t)0x00000010) /!< External Event 1 bit 3 /
richardv	0:b079fa4ed182	1703
richardv	0:b079fa4ed182	1704	#define HRTIM_EEFR1_EE2LTCH ((uint32_t)0x00000040) /!< External Event 2 latch /
richardv	0:b079fa4ed182	1705	#define HRTIM_EEFR1_EE2FLTR ((uint32_t)0x00000780) /!< External Event 2 filter mask /
richardv	0:b079fa4ed182	1706	#define HRTIM_EEFR1_EE2FLTR_0 ((uint32_t)0x00000080) /!< External Event 2 bit 0 /
richardv	0:b079fa4ed182	1707	#define HRTIM_EEFR1_EE2FLTR_1 ((uint32_t)0x00000100) /!< External Event 2 bit 1/
richardv	0:b079fa4ed182	1708	#define HRTIM_EEFR1_EE2FLTR_2 ((uint32_t)0x00000200) /!< External Event 2 bit 2 /
richardv	0:b079fa4ed182	1709	#define HRTIM_EEFR1_EE2FLTR_3 ((uint32_t)0x00000400) /!< External Event 2 bit 3 /
richardv	0:b079fa4ed182	1710
richardv	0:b079fa4ed182	1711	#define HRTIM_EEFR1_EE3LTCH ((uint32_t)0x00001000) /!< External Event 3 latch /
richardv	0:b079fa4ed182	1712	#define HRTIM_EEFR1_EE3FLTR ((uint32_t)0x0001E000) /!< External Event 3 filter mask /
richardv	0:b079fa4ed182	1713	#define HRTIM_EEFR1_EE3FLTR_0 ((uint32_t)0x00002000) /!< External Event 3 bit 0 /
richardv	0:b079fa4ed182	1714	#define HRTIM_EEFR1_EE3FLTR_1 ((uint32_t)0x00004000) /!< External Event 3 bit 1/
richardv	0:b079fa4ed182	1715	#define HRTIM_EEFR1_EE3FLTR_2 ((uint32_t)0x00008000) /!< External Event 3 bit 2 /
richardv	0:b079fa4ed182	1716	#define HRTIM_EEFR1_EE3FLTR_3 ((uint32_t)0x00010000) /!< External Event 3 bit 3 /
richardv	0:b079fa4ed182	1717
richardv	0:b079fa4ed182	1718	#define HRTIM_EEFR1_EE4LTCH ((uint32_t)0x00040000) /!< External Event 4 latch /
richardv	0:b079fa4ed182	1719	#define HRTIM_EEFR1_EE4FLTR ((uint32_t)0x00780000) /!< External Event 4 filter mask /
richardv	0:b079fa4ed182	1720	#define HRTIM_EEFR1_EE4FLTR_0 ((uint32_t)0x00080000) /!< External Event 4 bit 0 /
richardv	0:b079fa4ed182	1721	#define HRTIM_EEFR1_EE4FLTR_1 ((uint32_t)0x00100000) /!< External Event 4 bit 1/
richardv	0:b079fa4ed182	1722	#define HRTIM_EEFR1_EE4FLTR_2 ((uint32_t)0x00200000) /!< External Event 4 bit 2 /
richardv	0:b079fa4ed182	1723	#define HRTIM_EEFR1_EE4FLTR_3 ((uint32_t)0x00400000) /!< External Event 4 bit 3 /
richardv	0:b079fa4ed182	1724
richardv	0:b079fa4ed182	1725	#define HRTIM_EEFR1_EE5LTCH ((uint32_t)0x01000000) /!< External Event 5 latch /
richardv	0:b079fa4ed182	1726	#define HRTIM_EEFR1_EE5FLTR ((uint32_t)0x1E000000) /!< External Event 5 filter mask /
richardv	0:b079fa4ed182	1727	#define HRTIM_EEFR1_EE5FLTR_0 ((uint32_t)0x02000000) /!< External Event 5 bit 0 /
richardv	0:b079fa4ed182	1728	#define HRTIM_EEFR1_EE5FLTR_1 ((uint32_t)0x04000000) /!< External Event 5 bit 1/
richardv	0:b079fa4ed182	1729	#define HRTIM_EEFR1_EE5FLTR_2 ((uint32_t)0x08000000) /!< External Event 5 bit 2 /
richardv	0:b079fa4ed182	1730	#define HRTIM_EEFR1_EE5FLTR_3 ((uint32_t)0x10000000) /!< External Event 5 bit 3 /
richardv	0:b079fa4ed182	1731
richardv	0:b079fa4ed182	1732	/** Bit definition for Slave external event filtering register 2 *********/
richardv	0:b079fa4ed182	1733	#define HRTIM_EEFR2_EE6LTCH ((uint32_t)0x00000001) /!< External Event 6 latch /
richardv	0:b079fa4ed182	1734	#define HRTIM_EEFR2_EE6FLTR ((uint32_t)0x0000001E) /!< External Event 6 filter mask /
richardv	0:b079fa4ed182	1735	#define HRTIM_EEFR2_EE6FLTR_0 ((uint32_t)0x00000002) /!< External Event 6 bit 0 /
richardv	0:b079fa4ed182	1736	#define HRTIM_EEFR2_EE6FLTR_1 ((uint32_t)0x00000004) /!< External Event 6 bit 1/
richardv	0:b079fa4ed182	1737	#define HRTIM_EEFR2_EE6FLTR_2 ((uint32_t)0x00000008) /!< External Event 6 bit 2 /
richardv	0:b079fa4ed182	1738	#define HRTIM_EEFR2_EE6FLTR_3 ((uint32_t)0x00000010) /!< External Event 6 bit 3 /
richardv	0:b079fa4ed182	1739
richardv	0:b079fa4ed182	1740	#define HRTIM_EEFR2_EE7LTCH ((uint32_t)0x00000040) /!< External Event 7 latch /
richardv	0:b079fa4ed182	1741	#define HRTIM_EEFR2_EE7FLTR ((uint32_t)0x00000780) /!< External Event 7 filter mask /
richardv	0:b079fa4ed182	1742	#define HRTIM_EEFR2_EE7FLTR_0 ((uint32_t)0x00000080) /!< External Event 7 bit 0 /
richardv	0:b079fa4ed182	1743	#define HRTIM_EEFR2_EE7FLTR_1 ((uint32_t)0x00000100) /!< External Event 7 bit 1/
richardv	0:b079fa4ed182	1744	#define HRTIM_EEFR2_EE7FLTR_2 ((uint32_t)0x00000200) /!< External Event 7 bit 2 /
richardv	0:b079fa4ed182	1745	#define HRTIM_EEFR2_EE7FLTR_3 ((uint32_t)0x00000400) /!< External Event 7 bit 3 /
richardv	0:b079fa4ed182	1746
richardv	0:b079fa4ed182	1747	#define HRTIM_EEFR2_EE8LTCH ((uint32_t)0x00001000) /!< External Event 8 latch /
richardv	0:b079fa4ed182	1748	#define HRTIM_EEFR2_EE8FLTR ((uint32_t)0x0001E000) /!< External Event 8 filter mask /
richardv	0:b079fa4ed182	1749	#define HRTIM_EEFR2_EE8FLTR_0 ((uint32_t)0x00002000) /!< External Event 8 bit 0 /
richardv	0:b079fa4ed182	1750	#define HRTIM_EEFR2_EE8FLTR_1 ((uint32_t)0x00004000) /!< External Event 8 bit 1/
richardv	0:b079fa4ed182	1751	#define HRTIM_EEFR2_EE8FLTR_2 ((uint32_t)0x00008000) /!< External Event 8 bit 2 /
richardv	0:b079fa4ed182	1752	#define HRTIM_EEFR2_EE8FLTR_3 ((uint32_t)0x00010000) /!< External Event 8 bit 3 /
richardv	0:b079fa4ed182	1753
richardv	0:b079fa4ed182	1754	#define HRTIM_EEFR2_EE9LTCH ((uint32_t)0x00040000) /!< External Event 9 latch /
richardv	0:b079fa4ed182	1755	#define HRTIM_EEFR2_EE9FLTR ((uint32_t)0x00780000) /!< External Event 9 filter mask /
richardv	0:b079fa4ed182	1756	#define HRTIM_EEFR2_EE9FLTR_0 ((uint32_t)0x00080000) /!< External Event 9 bit 0 /
richardv	0:b079fa4ed182	1757	#define HRTIM_EEFR2_EE9FLTR_1 ((uint32_t)0x00100000) /!< External Event 9 bit 1/
richardv	0:b079fa4ed182	1758	#define HRTIM_EEFR2_EE9FLTR_2 ((uint32_t)0x00200000) /!< External Event 9 bit 2 /
richardv	0:b079fa4ed182	1759	#define HRTIM_EEFR2_EE9FLTR_3 ((uint32_t)0x00400000) /!< External Event 9 bit 3 /
richardv	0:b079fa4ed182	1760
richardv	0:b079fa4ed182	1761	#define HRTIM_EEFR2_EE10LTCH ((uint32_t)0x01000000) /!< External Event 10 latch /
richardv	0:b079fa4ed182	1762	#define HRTIM_EEFR2_EE10FLTR ((uint32_t)0x1E000000) /!< External Event 10 filter mask /
richardv	0:b079fa4ed182	1763	#define HRTIM_EEFR2_EE10FLTR_0 ((uint32_t)0x02000000) /!< External Event 10 bit 0 /
richardv	0:b079fa4ed182	1764	#define HRTIM_EEFR2_EE10FLTR_1 ((uint32_t)0x04000000) /!< External Event 10 bit 1/
richardv	0:b079fa4ed182	1765	#define HRTIM_EEFR2_EE10FLTR_2 ((uint32_t)0x08000000) /!< External Event 10 bit 2 /
richardv	0:b079fa4ed182	1766	#define HRTIM_EEFR2_EE10FLTR_3 ((uint32_t)0x10000000) /!< External Event 10 bit 3 /
richardv	0:b079fa4ed182	1767
richardv	0:b079fa4ed182	1768	/** Bit definition for Slave Timer reset register *************************/
richardv	0:b079fa4ed182	1769	#define HRTIM_RSTR_UPDATE ((uint32_t)0x00000002) /!< Timer update /
richardv	0:b079fa4ed182	1770	#define HRTIM_RSTR_CMP2 ((uint32_t)0x00000004) /!< Timer compare2 /
richardv	0:b079fa4ed182	1771	#define HRTIM_RSTR_CMP4 ((uint32_t)0x00000008) /!< Timer compare4 /
richardv	0:b079fa4ed182	1772
richardv	0:b079fa4ed182	1773	#define HRTIM_RSTR_MSTPER ((uint32_t)0x00000010) /!< Master period /
richardv	0:b079fa4ed182	1774	#define HRTIM_RSTR_MSTCMP1 ((uint32_t)0x00000020) /!< Master compare1 /
richardv	0:b079fa4ed182	1775	#define HRTIM_RSTR_MSTCMP2 ((uint32_t)0x00000040) /!< Master compare2 /
richardv	0:b079fa4ed182	1776	#define HRTIM_RSTR_MSTCMP3 ((uint32_t)0x00000080) /!< Master compare3 /
richardv	0:b079fa4ed182	1777	#define HRTIM_RSTR_MSTCMP4 ((uint32_t)0x00000100) /!< Master compare4 /
richardv	0:b079fa4ed182	1778
richardv	0:b079fa4ed182	1779	#define HRTIM_RSTR_EXTEVNT1 ((uint32_t)0x00000200) /!< External event 1 /
richardv	0:b079fa4ed182	1780	#define HRTIM_RSTR_EXTEVNT2 ((uint32_t)0x00000400) /!< External event 2 /
richardv	0:b079fa4ed182	1781	#define HRTIM_RSTR_EXTEVNT3 ((uint32_t)0x00000800) /!< External event 3 /
richardv	0:b079fa4ed182	1782	#define HRTIM_RSTR_EXTEVNT4 ((uint32_t)0x00001000) /!< External event 4 /
richardv	0:b079fa4ed182	1783	#define HRTIM_RSTR_EXTEVNT5 ((uint32_t)0x00002000) /!< External event 5 /
richardv	0:b079fa4ed182	1784	#define HRTIM_RSTR_EXTEVNT6 ((uint32_t)0x00004000) /!< External event 6 /
richardv	0:b079fa4ed182	1785	#define HRTIM_RSTR_EXTEVNT7 ((uint32_t)0x00008000) /!< External event 7 /
richardv	0:b079fa4ed182	1786	#define HRTIM_RSTR_EXTEVNT8 ((uint32_t)0x00010000) /!< External event 8 /
richardv	0:b079fa4ed182	1787	#define HRTIM_RSTR_EXTEVNT9 ((uint32_t)0x00020000) /!< External event 9 /
richardv	0:b079fa4ed182	1788	#define HRTIM_RSTR_EXTEVNT10 ((uint32_t)0x00040000) /!< External event 10 /
richardv	0:b079fa4ed182	1789
richardv	0:b079fa4ed182	1790	#define HRTIM_RSTR_TIMBCMP1 ((uint32_t)0x00080000) /!< Timer B compare 1 /
richardv	0:b079fa4ed182	1791	#define HRTIM_RSTR_TIMBCMP2 ((uint32_t)0x00100000) /!< Timer B compare 2 /
richardv	0:b079fa4ed182	1792	#define HRTIM_RSTR_TIMBCMP4 ((uint32_t)0x00200000) /!< Timer B compare 4 /
richardv	0:b079fa4ed182	1793
richardv	0:b079fa4ed182	1794	#define HRTIM_RSTR_TIMCCMP1 ((uint32_t)0x00400000) /!< Timer C compare 1 /
richardv	0:b079fa4ed182	1795	#define HRTIM_RSTR_TIMCCMP2 ((uint32_t)0x00800000) /!< Timer C compare 2 /
richardv	0:b079fa4ed182	1796	#define HRTIM_RSTR_TIMCCMP4 ((uint32_t)0x01000000) /!< Timer C compare 4 /
richardv	0:b079fa4ed182	1797
richardv	0:b079fa4ed182	1798	#define HRTIM_RSTR_TIMDCMP1 ((uint32_t)0x02000000) /!< Timer D compare 1 /
richardv	0:b079fa4ed182	1799	#define HRTIM_RSTR_TIMDCMP2 ((uint32_t)0x04000000) /!< Timer D compare 2 /
richardv	0:b079fa4ed182	1800	#define HRTIM_RSTR_TIMDCMP4 ((uint32_t)0x08000000) /!< Timer D compare 4 /
richardv	0:b079fa4ed182	1801
richardv	0:b079fa4ed182	1802	#define HRTIM_RSTR_TIMECMP1 ((uint32_t)0x10000000) /!< Timer E compare 1 /
richardv	0:b079fa4ed182	1803	#define HRTIM_RSTR_TIMECMP2 ((uint32_t)0x20000000) /!< Timer E compare 2 /
richardv	0:b079fa4ed182	1804	#define HRTIM_RSTR_TIMECMP4 ((uint32_t)0x40000000) /!< Timer E compare 4 /
richardv	0:b079fa4ed182	1805
richardv	0:b079fa4ed182	1806	/** Bit definition for Slave Timer Chopper register ***********************/
richardv	0:b079fa4ed182	1807	#define HRTIM_CHPR_CARFRQ ((uint32_t)0x0000000F) /!< Timer carrier frequency value /
richardv	0:b079fa4ed182	1808	#define HRTIM_CHPR_CARFRQ_0 ((uint32_t)0x00000001) /!< Timer carrier frequency value bit 0 /
richardv	0:b079fa4ed182	1809	#define HRTIM_CHPR_CARFRQ_1 ((uint32_t)0x00000002) /!< Timer carrier frequency value bit 1 /
richardv	0:b079fa4ed182	1810	#define HRTIM_CHPR_CARFRQ_2 ((uint32_t)0x00000004) /!< Timer carrier frequency value bit 2 /
richardv	0:b079fa4ed182	1811	#define HRTIM_CHPR_CARFRQ_3 ((uint32_t)0x00000008) /!< Timer carrier frequency value bit 3 /
richardv	0:b079fa4ed182	1812
richardv	0:b079fa4ed182	1813	#define HRTIM_CHPR_CARDTY ((uint32_t)0x00000070) /!< Timer chopper duty cycle value /
richardv	0:b079fa4ed182	1814	#define HRTIM_CHPR_CARDTY_0 ((uint32_t)0x00000010) /!< Timer chopper duty cycle value bit 0 /
richardv	0:b079fa4ed182	1815	#define HRTIM_CHPR_CARDTY_1 ((uint32_t)0x00000020) /!< Timer chopper duty cycle value bit 1 /
richardv	0:b079fa4ed182	1816	#define HRTIM_CHPR_CARDTY_2 ((uint32_t)0x00000040) /!< Timer chopper duty cycle value bit 2 /
richardv	0:b079fa4ed182	1817
richardv	0:b079fa4ed182	1818	#define HRTIM_CHPR_STRPW ((uint32_t)0x00000780) /!< Timer start pulse width value /
richardv	0:b079fa4ed182	1819	#define HRTIM_CHPR_STRPW_0 ((uint32_t)0x00000080) /!< Timer start pulse width value bit 0 /
richardv	0:b079fa4ed182	1820	#define HRTIM_CHPR_STRPW_1 ((uint32_t)0x00000100) /!< Timer start pulse width value bit 1 /
richardv	0:b079fa4ed182	1821	#define HRTIM_CHPR_STRPW_2 ((uint32_t)0x00000200) /!< Timer start pulse width value bit 2 /
richardv	0:b079fa4ed182	1822	#define HRTIM_CHPR_STRPW_3 ((uint32_t)0x00000400) /!< Timer start pulse width value bit 3 /
richardv	0:b079fa4ed182	1823
richardv	0:b079fa4ed182	1824	/** Bit definition for Slave Timer Capture 1 control register *************/
richardv	0:b079fa4ed182	1825	#define HRTIM_CPT1CR_SWCPT ((uint32_t)0x00000001) /!< Software capture /
richardv	0:b079fa4ed182	1826	#define HRTIM_CPT1CR_UPDCPT ((uint32_t)0x00000002) /!< Update capture /
richardv	0:b079fa4ed182	1827	#define HRTIM_CPT1CR_EXEV1CPT ((uint32_t)0x00000004) /!< External event 1 capture /
richardv	0:b079fa4ed182	1828	#define HRTIM_CPT1CR_EXEV2CPT ((uint32_t)0x00000008) /!< External event 2 capture /
richardv	0:b079fa4ed182	1829	#define HRTIM_CPT1CR_EXEV3CPT ((uint32_t)0x00000010) /!< External event 3 capture /
richardv	0:b079fa4ed182	1830	#define HRTIM_CPT1CR_EXEV4CPT ((uint32_t)0x00000020) /!< External event 4 capture /
richardv	0:b079fa4ed182	1831	#define HRTIM_CPT1CR_EXEV5CPT ((uint32_t)0x00000040) /!< External event 5 capture /
richardv	0:b079fa4ed182	1832	#define HRTIM_CPT1CR_EXEV6CPT ((uint32_t)0x00000080) /!< External event 6 capture /
richardv	0:b079fa4ed182	1833	#define HRTIM_CPT1CR_EXEV7CPT ((uint32_t)0x00000100) /!< External event 7 capture /
richardv	0:b079fa4ed182	1834	#define HRTIM_CPT1CR_EXEV8CPT ((uint32_t)0x00000200) /!< External event 8 capture /
richardv	0:b079fa4ed182	1835	#define HRTIM_CPT1CR_EXEV9CPT ((uint32_t)0x00000400) /!< External event 9 capture /
richardv	0:b079fa4ed182	1836	#define HRTIM_CPT1CR_EXEV10CPT ((uint32_t)0x00000800) /!< External event 10 capture /
richardv	0:b079fa4ed182	1837
richardv	0:b079fa4ed182	1838	#define HRTIM_CPT1CR_TA1SET ((uint32_t)0x00001000) /!< Timer A output 1 set /
richardv	0:b079fa4ed182	1839	#define HRTIM_CPT1CR_TA1RST ((uint32_t)0x00002000) /!< Timer A output 1 reset /
richardv	0:b079fa4ed182	1840	#define HRTIM_CPT1CR_TA1CMP1 ((uint32_t)0x00004000) /!< Timer A compare 1 /
richardv	0:b079fa4ed182	1841	#define HRTIM_CPT1CR_TA1CMP2 ((uint32_t)0x00008000) /!< Timer A compare 2 /
richardv	0:b079fa4ed182	1842
richardv	0:b079fa4ed182	1843	#define HRTIM_CPT1CR_TB1SET ((uint32_t)0x00010000) /!< Timer B output 1 set /
richardv	0:b079fa4ed182	1844	#define HRTIM_CPT1CR_TB1RST ((uint32_t)0x00020000) /!< Timer B output 1 reset /
richardv	0:b079fa4ed182	1845	#define HRTIM_CPT1CR_TB1CMP1 ((uint32_t)0x00040000) /!< Timer B compare 1 /
richardv	0:b079fa4ed182	1846	#define HRTIM_CPT1CR_TB1CMP2 ((uint32_t)0x00080000) /!< Timer B compare 2 /
richardv	0:b079fa4ed182	1847
richardv	0:b079fa4ed182	1848	#define HRTIM_CPT1CR_TC1SET ((uint32_t)0x00100000) /!< Timer C output 1 set /
richardv	0:b079fa4ed182	1849	#define HRTIM_CPT1CR_TC1RST ((uint32_t)0x00200000) /!< Timer C output 1 reset /
richardv	0:b079fa4ed182	1850	#define HRTIM_CPT1CR_TC1CMP1 ((uint32_t)0x00400000) /!< Timer C compare 1 /
richardv	0:b079fa4ed182	1851	#define HRTIM_CPT1CR_TC1CMP2 ((uint32_t)0x00800000) /!< Timer C compare 2 /
richardv	0:b079fa4ed182	1852
richardv	0:b079fa4ed182	1853	#define HRTIM_CPT1CR_TD1SET ((uint32_t)0x01000000) /!< Timer D output 1 set /
richardv	0:b079fa4ed182	1854	#define HRTIM_CPT1CR_TD1RST ((uint32_t)0x02000000) /!< Timer D output 1 reset /
richardv	0:b079fa4ed182	1855	#define HRTIM_CPT1CR_TD1CMP1 ((uint32_t)0x04000000) /!< Timer D compare 1 /
richardv	0:b079fa4ed182	1856	#define HRTIM_CPT1CR_TD1CMP2 ((uint32_t)0x08000000) /!< Timer D compare 2 /
richardv	0:b079fa4ed182	1857
richardv	0:b079fa4ed182	1858	#define HRTIM_CPT1CR_TE1SET ((uint32_t)0x10000000) /!< Timer E output 1 set /
richardv	0:b079fa4ed182	1859	#define HRTIM_CPT1CR_TE1RST ((uint32_t)0x20000000) /!< Timer E output 1 reset /
richardv	0:b079fa4ed182	1860	#define HRTIM_CPT1CR_TE1CMP1 ((uint32_t)0x40000000) /!< Timer E compare 1 /
richardv	0:b079fa4ed182	1861	#define HRTIM_CPT1CR_TE1CMP2 ((uint32_t)0x80000000) /!< Timer E compare 2 /
richardv	0:b079fa4ed182	1862
richardv	0:b079fa4ed182	1863	/** Bit definition for Slave Timer Capture 2 control register *************/
richardv	0:b079fa4ed182	1864	#define HRTIM_CPT2CR_SWCPT ((uint32_t)0x00000001) /!< Software capture /
richardv	0:b079fa4ed182	1865	#define HRTIM_CPT2CR_UPDCPT ((uint32_t)0x00000002) /!< Update capture /
richardv	0:b079fa4ed182	1866	#define HRTIM_CPT2CR_EXEV1CPT ((uint32_t)0x00000004) /!< External event 1 capture /
richardv	0:b079fa4ed182	1867	#define HRTIM_CPT2CR_EXEV2CPT ((uint32_t)0x00000008) /!< External event 2 capture /
richardv	0:b079fa4ed182	1868	#define HRTIM_CPT2CR_EXEV3CPT ((uint32_t)0x00000010) /!< External event 3 capture /
richardv	0:b079fa4ed182	1869	#define HRTIM_CPT2CR_EXEV4CPT ((uint32_t)0x00000020) /!< External event 4 capture /
richardv	0:b079fa4ed182	1870	#define HRTIM_CPT2CR_EXEV5CPT ((uint32_t)0x00000040) /!< External event 5 capture /
richardv	0:b079fa4ed182	1871	#define HRTIM_CPT2CR_EXEV6CPT ((uint32_t)0x00000080) /!< External event 6 capture /
richardv	0:b079fa4ed182	1872	#define HRTIM_CPT2CR_EXEV7CPT ((uint32_t)0x00000100) /!< External event 7 capture /
richardv	0:b079fa4ed182	1873	#define HRTIM_CPT2CR_EXEV8CPT ((uint32_t)0x00000200) /!< External event 8 capture /
richardv	0:b079fa4ed182	1874	#define HRTIM_CPT2CR_EXEV9CPT ((uint32_t)0x00000400) /!< External event 9 capture /
richardv	0:b079fa4ed182	1875	#define HRTIM_CPT2CR_EXEV10CPT ((uint32_t)0x00000800) /!< External event 10 capture /
richardv	0:b079fa4ed182	1876
richardv	0:b079fa4ed182	1877	#define HRTIM_CPT2CR_TA1SET ((uint32_t)0x00001000) /!< Timer A output 1 set /
richardv	0:b079fa4ed182	1878	#define HRTIM_CPT2CR_TA1RST ((uint32_t)0x00002000) /!< Timer A output 1 reset /
richardv	0:b079fa4ed182	1879	#define HRTIM_CPT2CR_TA1CMP1 ((uint32_t)0x00004000) /!< Timer A compare 1 /
richardv	0:b079fa4ed182	1880	#define HRTIM_CPT2CR_TA1CMP2 ((uint32_t)0x00008000) /!< Timer A compare 2 /
richardv	0:b079fa4ed182	1881
richardv	0:b079fa4ed182	1882	#define HRTIM_CPT2CR_TB1SET ((uint32_t)0x00010000) /!< Timer B output 1 set /
richardv	0:b079fa4ed182	1883	#define HRTIM_CPT2CR_TB1RST ((uint32_t)0x00020000) /!< Timer B output 1 reset /
richardv	0:b079fa4ed182	1884	#define HRTIM_CPT2CR_TB1CMP1 ((uint32_t)0x00040000) /!< Timer B compare 1 /
richardv	0:b079fa4ed182	1885	#define HRTIM_CPT2CR_TB1CMP2 ((uint32_t)0x00080000) /!< Timer B compare 2 /
richardv	0:b079fa4ed182	1886
richardv	0:b079fa4ed182	1887	#define HRTIM_CPT2CR_TC1SET ((uint32_t)0x00100000) /!< Timer C output 1 set /
richardv	0:b079fa4ed182	1888	#define HRTIM_CPT2CR_TC1RST ((uint32_t)0x00200000) /!< Timer C output 1 reset /
richardv	0:b079fa4ed182	1889	#define HRTIM_CPT2CR_TC1CMP1 ((uint32_t)0x00400000) /!< Timer C compare 1 /
richardv	0:b079fa4ed182	1890	#define HRTIM_CPT2CR_TC1CMP2 ((uint32_t)0x00800000) /!< Timer C compare 2 /
richardv	0:b079fa4ed182	1891
richardv	0:b079fa4ed182	1892	#define HRTIM_CPT2CR_TD1SET ((uint32_t)0x01000000) /!< Timer D output 1 set /
richardv	0:b079fa4ed182	1893	#define HRTIM_CPT2CR_TD1RST ((uint32_t)0x02000000) /!< Timer D output 1 reset /
richardv	0:b079fa4ed182	1894	#define HRTIM_CPT2CR_TD1CMP1 ((uint32_t)0x04000000) /!< Timer D compare 1 /
richardv	0:b079fa4ed182	1895	#define HRTIM_CPT2CR_TD1CMP2 ((uint32_t)0x08000000) /!< Timer D compare 2 /
richardv	0:b079fa4ed182	1896
richardv	0:b079fa4ed182	1897	#define HRTIM_CPT2CR_TE1SET ((uint32_t)0x10000000) /!< Timer E output 1 set /
richardv	0:b079fa4ed182	1898	#define HRTIM_CPT2CR_TE1RST ((uint32_t)0x20000000) /!< Timer E output 1 reset /
richardv	0:b079fa4ed182	1899	#define HRTIM_CPT2CR_TE1CMP1 ((uint32_t)0x40000000) /!< Timer E compare 1 /
richardv	0:b079fa4ed182	1900	#define HRTIM_CPT2CR_TE1CMP2 ((uint32_t)0x80000000) /!< Timer E compare 2 /
richardv	0:b079fa4ed182	1901
richardv	0:b079fa4ed182	1902	/** Bit definition for Slave Timer Output register ************************/
richardv	0:b079fa4ed182	1903	#define HRTIM_OUTR_POL1 ((uint32_t)0x00000002) /!< Slave output 1 polarity /
richardv	0:b079fa4ed182	1904	#define HRTIM_OUTR_IDLM1 ((uint32_t)0x00000004) /!< Slave output 1 idle mode /
richardv	0:b079fa4ed182	1905	#define HRTIM_OUTR_IDLES1 ((uint32_t)0x00000008) /!< Slave output 1 idle state /
richardv	0:b079fa4ed182	1906	#define HRTIM_OUTR_FAULT1 ((uint32_t)0x00000030) /!< Slave output 1 fault state /
richardv	0:b079fa4ed182	1907	#define HRTIM_OUTR_FAULT1_0 ((uint32_t)0x00000010) /!< Slave output 1 fault state bit 0 /
richardv	0:b079fa4ed182	1908	#define HRTIM_OUTR_FAULT1_1 ((uint32_t)0x00000020) /!< Slave output 1 fault state bit 1 /
richardv	0:b079fa4ed182	1909	#define HRTIM_OUTR_CHP1 ((uint32_t)0x00000040) /!< Slave output 1 chopper enable /
richardv	0:b079fa4ed182	1910	#define HRTIM_OUTR_DIDL1 ((uint32_t)0x00000080) /!< Slave output 1 dead time idle /
richardv	0:b079fa4ed182	1911
richardv	0:b079fa4ed182	1912	#define HRTIM_OUTR_DTEN ((uint32_t)0x00000100) /!< Slave output deadtime enable /
richardv	0:b079fa4ed182	1913	#define HRTIM_OUTR_DLYPRTEN ((uint32_t)0x00000200) /!< Slave output delay protection enable /
richardv	0:b079fa4ed182	1914	#define HRTIM_OUTR_DLYPRT ((uint32_t)0x00001C00) /!< Slave output delay protection /
richardv	0:b079fa4ed182	1915	#define HRTIM_OUTR_DLYPRT_0 ((uint32_t)0x00000400) /!< Slave output delay protection bit 0 /
richardv	0:b079fa4ed182	1916	#define HRTIM_OUTR_DLYPRT_1 ((uint32_t)0x00000800) /!< Slave output delay protection bit 1 /
richardv	0:b079fa4ed182	1917	#define HRTIM_OUTR_DLYPRT_2 ((uint32_t)0x00001000) /!< Slave output delay protection bit 2 /
richardv	0:b079fa4ed182	1918
richardv	0:b079fa4ed182	1919	#define HRTIM_OUTR_POL2 ((uint32_t)0x00020000) /!< Slave output 2 polarity /
richardv	0:b079fa4ed182	1920	#define HRTIM_OUTR_IDLM2 ((uint32_t)0x00040000) /!< Slave output 2 idle mode /
richardv	0:b079fa4ed182	1921	#define HRTIM_OUTR_IDLES2 ((uint32_t)0x00080000) /!< Slave output 2 idle state /
richardv	0:b079fa4ed182	1922	#define HRTIM_OUTR_FAULT2 ((uint32_t)0x00300000) /!< Slave output 2 fault state /
richardv	0:b079fa4ed182	1923	#define HRTIM_OUTR_FAULT2_0 ((uint32_t)0x00100000) /!< Slave output 2 fault state bit 0 /
richardv	0:b079fa4ed182	1924	#define HRTIM_OUTR_FAULT2_1 ((uint32_t)0x00200000) /!< Slave output 2 fault state bit 1 /
richardv	0:b079fa4ed182	1925	#define HRTIM_OUTR_CHP2 ((uint32_t)0x00400000) /!< Slave output 2 chopper enable /
richardv	0:b079fa4ed182	1926	#define HRTIM_OUTR_DIDL2 ((uint32_t)0x00800000) /!< Slave output 2 dead time idle /
richardv	0:b079fa4ed182	1927
richardv	0:b079fa4ed182	1928	/** Bit definition for Slave Timer Fault register *************************/
richardv	0:b079fa4ed182	1929	#define HRTIM_FLTR_FLT1EN ((uint32_t)0x00000001) /!< Fault 1 enable /
richardv	0:b079fa4ed182	1930	#define HRTIM_FLTR_FLT2EN ((uint32_t)0x00000002) /!< Fault 2 enable /
richardv	0:b079fa4ed182	1931	#define HRTIM_FLTR_FLT3EN ((uint32_t)0x00000004) /!< Fault 3 enable /
richardv	0:b079fa4ed182	1932	#define HRTIM_FLTR_FLT4EN ((uint32_t)0x00000008) /!< Fault 4 enable /
richardv	0:b079fa4ed182	1933	#define HRTIM_FLTR_FLT5EN ((uint32_t)0x00000010) /!< Fault 5 enable /
richardv	0:b079fa4ed182	1934	#define HRTIM_FLTR_FLTCLK ((uint32_t)0x80000000) /!< Fault sources lock /
richardv	0:b079fa4ed182	1935
richardv	0:b079fa4ed182	1936	/** Bit definition for Common HRTIM Timer control register 1 **************/
richardv	0:b079fa4ed182	1937	#define HRTIM_CR1_MUDIS ((uint32_t)0x00000001) /!< Master update disable/
richardv	0:b079fa4ed182	1938	#define HRTIM_CR1_TAUDIS ((uint32_t)0x00000002) /!< Timer A update disable/
richardv	0:b079fa4ed182	1939	#define HRTIM_CR1_TBUDIS ((uint32_t)0x00000004) /!< Timer B update disable/
richardv	0:b079fa4ed182	1940	#define HRTIM_CR1_TCUDIS ((uint32_t)0x00000008) /!< Timer C update disable/
richardv	0:b079fa4ed182	1941	#define HRTIM_CR1_TDUDIS ((uint32_t)0x00000010) /!< Timer D update disable/
richardv	0:b079fa4ed182	1942	#define HRTIM_CR1_TEUDIS ((uint32_t)0x00000020) /!< Timer E update disable/
richardv	0:b079fa4ed182	1943	#define HRTIM_CR1_ADC1USRC ((uint32_t)0x00070000) /!< ADC Trigger 1 update source /
richardv	0:b079fa4ed182	1944	#define HRTIM_CR1_ADC1USRC_0 ((uint32_t)0x00010000) /!< ADC Trigger 1 update source bit 0 /
richardv	0:b079fa4ed182	1945	#define HRTIM_CR1_ADC1USRC_1 ((uint32_t)0x00020000) /!< ADC Trigger 1 update source bit 1 /
richardv	0:b079fa4ed182	1946	#define HRTIM_CR1_ADC1USRC_2 ((uint32_t)0x00040000) /!< ADC Trigger 1 update source bit 2 /
richardv	0:b079fa4ed182	1947	#define HRTIM_CR1_ADC2USRC ((uint32_t)0x00380000) /!< ADC Trigger 2 update source /
richardv	0:b079fa4ed182	1948	#define HRTIM_CR1_ADC2USRC_0 ((uint32_t)0x00080000) /!< ADC Trigger 2 update source bit 0 /
richardv	0:b079fa4ed182	1949	#define HRTIM_CR1_ADC2USRC_1 ((uint32_t)0x00100000) /!< ADC Trigger 2 update source bit 1 /
richardv	0:b079fa4ed182	1950	#define HRTIM_CR1_ADC2USRC_2 ((uint32_t)0x00200000) /!< ADC Trigger 2 update source bit 2 /
richardv	0:b079fa4ed182	1951	#define HRTIM_CR1_ADC3USRC ((uint32_t)0x01C00000) /!< ADC Trigger 3 update source /
richardv	0:b079fa4ed182	1952	#define HRTIM_CR1_ADC3USRC_0 ((uint32_t)0x00400000) /!< ADC Trigger 3 update source bit 0 /
richardv	0:b079fa4ed182	1953	#define HRTIM_CR1_ADC3USRC_1 ((uint32_t)0x00800000) /!< ADC Trigger 3 update source bit 1 /
richardv	0:b079fa4ed182	1954	#define HRTIM_CR1_ADC3USRC_2 ((uint32_t)0x01000000) /!< ADC Trigger 3 update source bit 2 /
richardv	0:b079fa4ed182	1955	#define HRTIM_CR1_ADC4USRC ((uint32_t)0x0E000000) /!< ADC Trigger 4 update source /
richardv	0:b079fa4ed182	1956	#define HRTIM_CR1_ADC4USRC_0 ((uint32_t)0x02000000) /!< ADC Trigger 4 update source bit 0 /
richardv	0:b079fa4ed182	1957	#define HRTIM_CR1_ADC4USRC_1 ((uint32_t)0x04000000) /!< ADC Trigger 4 update source bit 1 /
richardv	0:b079fa4ed182	1958	#define HRTIM_CR1_ADC4USRC_2 ((uint32_t)0x0800000) /!< ADC Trigger 4 update source bit 2 /
richardv	0:b079fa4ed182	1959
richardv	0:b079fa4ed182	1960	/** Bit definition for Common HRTIM Timer control register 2 **************/
richardv	0:b079fa4ed182	1961	#define HRTIM_CR2_MSWU ((uint32_t)0x00000001) /!< Master software update /
richardv	0:b079fa4ed182	1962	#define HRTIM_CR2_TASWU ((uint32_t)0x00000002) /!< Timer A software update /
richardv	0:b079fa4ed182	1963	#define HRTIM_CR2_TBSWU ((uint32_t)0x00000004) /!< Timer B software update /
richardv	0:b079fa4ed182	1964	#define HRTIM_CR2_TCSWU ((uint32_t)0x00000008) /!< Timer C software update /
richardv	0:b079fa4ed182	1965	#define HRTIM_CR2_TDSWU ((uint32_t)0x00000010) /!< Timer D software update /
richardv	0:b079fa4ed182	1966	#define HRTIM_CR2_TESWU ((uint32_t)0x00000020) /!< Timer E software update /
richardv	0:b079fa4ed182	1967	#define HRTIM_CR2_MRST ((uint32_t)0x00000100) /!< Master count software reset /
richardv	0:b079fa4ed182	1968	#define HRTIM_CR2_TARST ((uint32_t)0x00000200) /!< Timer A count software reset /
richardv	0:b079fa4ed182	1969	#define HRTIM_CR2_TBRST ((uint32_t)0x00000400) /!< Timer B count software reset /
richardv	0:b079fa4ed182	1970	#define HRTIM_CR2_TCRST ((uint32_t)0x00000800) /!< Timer C count software reset /
richardv	0:b079fa4ed182	1971	#define HRTIM_CR2_TDRST ((uint32_t)0x00001000) /!< Timer D count software reset /
richardv	0:b079fa4ed182	1972	#define HRTIM_CR2_TERST ((uint32_t)0x00002000) /!< Timer E count software reset /
richardv	0:b079fa4ed182	1973
richardv	0:b079fa4ed182	1974	/** Bit definition for Common HRTIM Timer interrupt status register *******/
richardv	0:b079fa4ed182	1975	#define HRTIM_ISR_FLT1 ((uint32_t)0x00000001) /!< Fault 1 interrupt flag /
richardv	0:b079fa4ed182	1976	#define HRTIM_ISR_FLT2 ((uint32_t)0x00000002) /!< Fault 2 interrupt flag /
richardv	0:b079fa4ed182	1977	#define HRTIM_ISR_FLT3 ((uint32_t)0x00000004) /!< Fault 3 interrupt flag /
richardv	0:b079fa4ed182	1978	#define HRTIM_ISR_FLT4 ((uint32_t)0x00000008) /!< Fault 4 interrupt flag /
richardv	0:b079fa4ed182	1979	#define HRTIM_ISR_FLT5 ((uint32_t)0x00000010) /!< Fault 5 interrupt flag /
richardv	0:b079fa4ed182	1980	#define HRTIM_ISR_SYSFLT ((uint32_t)0x00000020) /!< System Fault interrupt flag /
richardv	0:b079fa4ed182	1981	#define HRTIM_ISR_DLLRDY ((uint32_t)0x00010000) /!< DLL ready interrupt flag /
richardv	0:b079fa4ed182	1982	#define HRTIM_ISR_BMPER ((uint32_t)0x00020000) /!< Burst mode period interrupt flag /
richardv	0:b079fa4ed182	1983
richardv	0:b079fa4ed182	1984	/** Bit definition for Common HRTIM Timer interrupt clear register ********/
richardv	0:b079fa4ed182	1985	#define HRTIM_ICR_FLT1C ((uint32_t)0x00000001) /!< Fault 1 interrupt flag clear /
richardv	0:b079fa4ed182	1986	#define HRTIM_ICR_FLT2C ((uint32_t)0x00000002) /!< Fault 2 interrupt flag clear /
richardv	0:b079fa4ed182	1987	#define HRTIM_ICR_FLT3C ((uint32_t)0x00000004) /!< Fault 3 interrupt flag clear /
richardv	0:b079fa4ed182	1988	#define HRTIM_ICR_FLT4C ((uint32_t)0x00000008) /!< Fault 4 interrupt flag clear /
richardv	0:b079fa4ed182	1989	#define HRTIM_ICR_FLT5C ((uint32_t)0x00000010) /!< Fault 5 interrupt flag clear /
richardv	0:b079fa4ed182	1990	#define HRTIM_ICR_SYSFLTC ((uint32_t)0x00000020) /!< System Fault interrupt flag clear /
richardv	0:b079fa4ed182	1991	#define HRTIM_ICR_DLLRDYC ((uint32_t)0x00010000) /!< DLL ready interrupt flag clear /
richardv	0:b079fa4ed182	1992	#define HRTIM_ICR_BMPERC ((uint32_t)0x00020000) /!< Burst mode period interrupt flag clear /
richardv	0:b079fa4ed182	1993
richardv	0:b079fa4ed182	1994	/** Bit definition for Common HRTIM Timer interrupt enable register *******/
richardv	0:b079fa4ed182	1995	#define HRTIM_IER_FLT1 ((uint32_t)0x00000001) /!< Fault 1 interrupt enable /
richardv	0:b079fa4ed182	1996	#define HRTIM_IER_FLT2 ((uint32_t)0x00000002) /!< Fault 2 interrupt enable /
richardv	0:b079fa4ed182	1997	#define HRTIM_IER_FLT3 ((uint32_t)0x00000004) /!< Fault 3 interrupt enable /
richardv	0:b079fa4ed182	1998	#define HRTIM_IER_FLT4 ((uint32_t)0x00000008) /!< Fault 4 interrupt enable /
richardv	0:b079fa4ed182	1999	#define HRTIM_IER_FLT5 ((uint32_t)0x00000010) /!< Fault 5 interrupt enable /
richardv	0:b079fa4ed182	2000	#define HRTIM_IER_SYSFLT ((uint32_t)0x00000020) /!< System Fault interrupt enable /
richardv	0:b079fa4ed182	2001	#define HRTIM_IER_DLLRDY ((uint32_t)0x00010000) /!< DLL ready interrupt enable /
richardv	0:b079fa4ed182	2002	#define HRTIM_IER_BMPER ((uint32_t)0x00020000) /!< Burst mode period interrupt enable /
richardv	0:b079fa4ed182	2003
richardv	0:b079fa4ed182	2004	/** Bit definition for Common HRTIM Timer output enable register **********/
richardv	0:b079fa4ed182	2005	#define HRTIM_OENR_TA1OEN ((uint32_t)0x00000001) /!< Timer A Output 1 enable /
richardv	0:b079fa4ed182	2006	#define HRTIM_OENR_TA2OEN ((uint32_t)0x00000002) /!< Timer A Output 2 enable /
richardv	0:b079fa4ed182	2007	#define HRTIM_OENR_TB1OEN ((uint32_t)0x00000004) /!< Timer B Output 1 enable /
richardv	0:b079fa4ed182	2008	#define HRTIM_OENR_TB2OEN ((uint32_t)0x00000008) /!< Timer B Output 2 enable /
richardv	0:b079fa4ed182	2009	#define HRTIM_OENR_TC1OEN ((uint32_t)0x00000010) /!< Timer C Output 1 enable /
richardv	0:b079fa4ed182	2010	#define HRTIM_OENR_TC2OEN ((uint32_t)0x00000020) /!< Timer C Output 2 enable /
richardv	0:b079fa4ed182	2011	#define HRTIM_OENR_TD1OEN ((uint32_t)0x00000040) /!< Timer D Output 1 enable /
richardv	0:b079fa4ed182	2012	#define HRTIM_OENR_TD2OEN ((uint32_t)0x00000080) /!< Timer D Output 2 enable /
richardv	0:b079fa4ed182	2013	#define HRTIM_OENR_TE1OEN ((uint32_t)0x00000100) /!< Timer E Output 1 enable /
richardv	0:b079fa4ed182	2014	#define HRTIM_OENR_TE2OEN ((uint32_t)0x00000200) /!< Timer E Output 2 enable /
richardv	0:b079fa4ed182	2015
richardv	0:b079fa4ed182	2016	/** Bit definition for Common HRTIM Timer output disable register *********/
richardv	0:b079fa4ed182	2017	#define HRTIM_ODISR_TA1ODIS ((uint32_t)0x00000001) /!< Timer A Output 1 disable /
richardv	0:b079fa4ed182	2018	#define HRTIM_ODISR_TA2ODIS ((uint32_t)0x00000002) /!< Timer A Output 2 disable /
richardv	0:b079fa4ed182	2019	#define HRTIM_ODISR_TB1ODIS ((uint32_t)0x00000004) /!< Timer B Output 1 disable /
richardv	0:b079fa4ed182	2020	#define HRTIM_ODISR_TB2ODIS ((uint32_t)0x00000008) /!< Timer B Output 2 disable /
richardv	0:b079fa4ed182	2021	#define HRTIM_ODISR_TC1ODIS ((uint32_t)0x00000010) /!< Timer C Output 1 disable /
richardv	0:b079fa4ed182	2022	#define HRTIM_ODISR_TC2ODIS ((uint32_t)0x00000020) /!< Timer C Output 2 disable /
richardv	0:b079fa4ed182	2023	#define HRTIM_ODISR_TD1ODIS ((uint32_t)0x00000040) /!< Timer D Output 1 disable /
richardv	0:b079fa4ed182	2024	#define HRTIM_ODISR_TD2ODIS ((uint32_t)0x00000080) /!< Timer D Output 2 disable /
richardv	0:b079fa4ed182	2025	#define HRTIM_ODISR_TE1ODIS ((uint32_t)0x00000100) /!< Timer E Output 1 disable /
richardv	0:b079fa4ed182	2026	#define HRTIM_ODISR_TE2ODIS ((uint32_t)0x00000200) /!< Timer E Output 2 disable /
richardv	0:b079fa4ed182	2027
richardv	0:b079fa4ed182	2028	/** Bit definition for Common HRTIM Timer output disable status register ***/
richardv	0:b079fa4ed182	2029	#define HRTIM_ODSR_TA1ODS ((uint32_t)0x00000001) /!< Timer A Output 1 disable status /
richardv	0:b079fa4ed182	2030	#define HRTIM_ODSR_TA2ODS ((uint32_t)0x00000002) /!< Timer A Output 2 disable status /
richardv	0:b079fa4ed182	2031	#define HRTIM_ODSR_TB1ODS ((uint32_t)0x00000004) /!< Timer B Output 1 disable status /
richardv	0:b079fa4ed182	2032	#define HRTIM_ODSR_TB2ODS ((uint32_t)0x00000008) /!< Timer B Output 2 disable status /
richardv	0:b079fa4ed182	2033	#define HRTIM_ODSR_TC1ODS ((uint32_t)0x00000010) /!< Timer C Output 1 disable status /
richardv	0:b079fa4ed182	2034	#define HRTIM_ODSR_TC2ODS ((uint32_t)0x00000020) /!< Timer C Output 2 disable status /
richardv	0:b079fa4ed182	2035	#define HRTIM_ODSR_TD1ODS ((uint32_t)0x00000040) /!< Timer D Output 1 disable status /
richardv	0:b079fa4ed182	2036	#define HRTIM_ODSR_TD2ODS ((uint32_t)0x00000080) /!< Timer D Output 2 disable status /
richardv	0:b079fa4ed182	2037	#define HRTIM_ODSR_TE1ODS ((uint32_t)0x00000100) /!< Timer E Output 1 disable status /
richardv	0:b079fa4ed182	2038	#define HRTIM_ODSR_TE2ODS ((uint32_t)0x00000200) /!< Timer E Output 2 disable status /
richardv	0:b079fa4ed182	2039
richardv	0:b079fa4ed182	2040	/** Bit definition for Common HRTIM Timer Burst mode control register ******/
richardv	0:b079fa4ed182	2041	#define HRTIM_BMCR_BME ((uint32_t)0x00000001) /!< Burst mode enable /
richardv	0:b079fa4ed182	2042	#define HRTIM_BMCR_BMOM ((uint32_t)0x00000002) /!< Burst mode operating mode /
richardv	0:b079fa4ed182	2043	#define HRTIM_BMCR_BMCLK ((uint32_t)0x0000003C) /!< Burst mode clock source /
richardv	0:b079fa4ed182	2044	#define HRTIM_BMCR_BMCLK_0 ((uint32_t)0x00000004) /!< Burst mode clock source bit 0 /
richardv	0:b079fa4ed182	2045	#define HRTIM_BMCR_BMCLK_1 ((uint32_t)0x00000008) /!< Burst mode clock source bit 1 /
richardv	0:b079fa4ed182	2046	#define HRTIM_BMCR_BMCLK_2 ((uint32_t)0x00000010) /!< Burst mode clock source bit 2 /
richardv	0:b079fa4ed182	2047	#define HRTIM_BMCR_BMCLK_3 ((uint32_t)0x00000020) /!< Burst mode clock source bit 3 /
richardv	0:b079fa4ed182	2048	#define HRTIM_BMCR_BMPSC ((uint32_t)0x000003C0) /!< Burst mode prescaler /
richardv	0:b079fa4ed182	2049	#define HRTIM_BMCR_BMPSC_0 ((uint32_t)0x00000040) /!< Burst mode prescaler bit 0 /
richardv	0:b079fa4ed182	2050	#define HRTIM_BMCR_BMPSC_1 ((uint32_t)0x00000080) /!< Burst mode prescaler bit 1 /
richardv	0:b079fa4ed182	2051	#define HRTIM_BMCR_BMPSC_2 ((uint32_t)0x00000100) /!< Burst mode prescaler bit 2 /
richardv	0:b079fa4ed182	2052	#define HRTIM_BMCR_BMPSC_3 ((uint32_t)0x00000200) /!< Burst mode prescaler bit 3 /
richardv	0:b079fa4ed182	2053	#define HRTIM_BMCR_BMPREN ((uint32_t)0x00000400) /!< Burst mode Preload bit /
richardv	0:b079fa4ed182	2054	#define HRTIM_BMCR_MTBM ((uint32_t)0x00010000) /!< Master Timer Burst mode /
richardv	0:b079fa4ed182	2055	#define HRTIM_BMCR_TABM ((uint32_t)0x00020000) /!< Timer A Burst mode /
richardv	0:b079fa4ed182	2056	#define HRTIM_BMCR_TBBM ((uint32_t)0x00040000) /!< Timer B Burst mode /
richardv	0:b079fa4ed182	2057	#define HRTIM_BMCR_TCBM ((uint32_t)0x00080000) /!< Timer C Burst mode /
richardv	0:b079fa4ed182	2058	#define HRTIM_BMCR_TDBM ((uint32_t)0x00100000) /!< Timer D Burst mode /
richardv	0:b079fa4ed182	2059	#define HRTIM_BMCR_TEBM ((uint32_t)0x00200000) /!< Timer E Burst mode /
richardv	0:b079fa4ed182	2060	#define HRTIM_BMCR_BMSTAT ((uint32_t)0x80000000) /!< Burst mode status /
richardv	0:b079fa4ed182	2061
richardv	0:b079fa4ed182	2062	/** Bit definition for Common HRTIM Timer Burst mode Trigger register *****/
richardv	0:b079fa4ed182	2063	#define HRTIM_BMTRGR_SW ((uint32_t)0x00000001) /!< Software start /
richardv	0:b079fa4ed182	2064	#define HRTIM_BMTRGR_MSTRST ((uint32_t)0x00000002) /!< Master reset /
richardv	0:b079fa4ed182	2065	#define HRTIM_BMTRGR_MSTREP ((uint32_t)0x00000004) /!< Master repetition /
richardv	0:b079fa4ed182	2066	#define HRTIM_BMTRGR_MSTCMP1 ((uint32_t)0x00000008) /!< Master compare 1 /
richardv	0:b079fa4ed182	2067	#define HRTIM_BMTRGR_MSTCMP2 ((uint32_t)0x00000010) /!< Master compare 2 /
richardv	0:b079fa4ed182	2068	#define HRTIM_BMTRGR_MSTCMP3 ((uint32_t)0x00000020) /!< Master compare 3 /
richardv	0:b079fa4ed182	2069	#define HRTIM_BMTRGR_MSTCMP4 ((uint32_t)0x00000040) /!< Master compare 4 /
richardv	0:b079fa4ed182	2070	#define HRTIM_BMTRGR_TARST ((uint32_t)0x00000080) /!< Timer A reset /
richardv	0:b079fa4ed182	2071	#define HRTIM_BMTRGR_TAREP ((uint32_t)0x00000100) /!< Timer A repetition /
richardv	0:b079fa4ed182	2072	#define HRTIM_BMTRGR_TACMP1 ((uint32_t)0x00000200) /!< Timer A compare 1 /
richardv	0:b079fa4ed182	2073	#define HRTIM_BMTRGR_TACMP2 ((uint32_t)0x00000400) /!< Timer A compare 2 /
richardv	0:b079fa4ed182	2074	#define HRTIM_BMTRGR_TBRST ((uint32_t)0x00000800) /!< Timer B reset /
richardv	0:b079fa4ed182	2075	#define HRTIM_BMTRGR_TBREP ((uint32_t)0x00001000) /!< Timer B repetition /
richardv	0:b079fa4ed182	2076	#define HRTIM_BMTRGR_TBCMP1 ((uint32_t)0x00002000) /!< Timer B compare 1 /
richardv	0:b079fa4ed182	2077	#define HRTIM_BMTRGR_TBCMP2 ((uint32_t)0x00004000) /!< Timer B compare 2 /
richardv	0:b079fa4ed182	2078	#define HRTIM_BMTRGR_TCRST ((uint32_t)0x00008000) /!< Timer C reset /
richardv	0:b079fa4ed182	2079	#define HRTIM_BMTRGR_TCREP ((uint32_t)0x00010000) /!< Timer C repetition /
richardv	0:b079fa4ed182	2080	#define HRTIM_BMTRGR_TCCMP1 ((uint32_t)0x00020000) /!< Timer C compare 1 /
richardv	0:b079fa4ed182	2081	#define HRTIM_BMTRGR_TCCMP2 ((uint32_t)0x00040000) /!< Timer C compare 2 /
richardv	0:b079fa4ed182	2082	#define HRTIM_BMTRGR_TDRST ((uint32_t)0x00080000) /!< Timer D reset /
richardv	0:b079fa4ed182	2083	#define HRTIM_BMTRGR_TDREP ((uint32_t)0x00100000) /!< Timer D repetition /
richardv	0:b079fa4ed182	2084	#define HRTIM_BMTRGR_TDCMP1 ((uint32_t)0x00200000) /!< Timer D compare 1 /
richardv	0:b079fa4ed182	2085	#define HRTIM_BMTRGR_TDCMP2 ((uint32_t)0x00400000) /!< Timer D compare 2 /
richardv	0:b079fa4ed182	2086	#define HRTIM_BMTRGR_TERST ((uint32_t)0x00800000) /!< Timer E reset /
richardv	0:b079fa4ed182	2087	#define HRTIM_BMTRGR_TEREP ((uint32_t)0x01000000) /!< Timer E repetition /
richardv	0:b079fa4ed182	2088	#define HRTIM_BMTRGR_TECMP1 ((uint32_t)0x02000000) /!< Timer E compare 1 /
richardv	0:b079fa4ed182	2089	#define HRTIM_BMTRGR_TECMP2 ((uint32_t)0x04000000) /!< Timer E compare 2 /
richardv	0:b079fa4ed182	2090	#define HRTIM_BMTRGR_TAEEV7 ((uint32_t)0x08000000) /!< Timer A period following External Event7 /
richardv	0:b079fa4ed182	2091	#define HRTIM_BMTRGR_TDEEV8 ((uint32_t)0x10000000) /!< Timer D period following External Event8 /
richardv	0:b079fa4ed182	2092	#define HRTIM_BMTRGR_EEV7 ((uint32_t)0x20000000) /!< External Event 7 /
richardv	0:b079fa4ed182	2093	#define HRTIM_BMTRGR_EEV8 ((uint32_t)0x40000000) /!< External Event 8 /
richardv	0:b079fa4ed182	2094	#define HRTIM_BMTRGR_OCHPEV ((uint32_t)0x80000000) /!< on-chip Event /
richardv	0:b079fa4ed182	2095
richardv	0:b079fa4ed182	2096	/***************** Bit definition for HRTIM_BMCMPR register *************/
richardv	0:b079fa4ed182	2097	#define HRTIM_BMCMPR_BMCMPR ((uint32_t)0x0000FFFF) /!<!<Burst Compare Value /
richardv	0:b079fa4ed182	2098
richardv	0:b079fa4ed182	2099	/***************** Bit definition for HRTIM_BMPER register **************/
richardv	0:b079fa4ed182	2100	#define HRTIM_BMPER_BMPER ((uint32_t)0x0000FFFF) /!<!<Burst period Value /
richardv	0:b079fa4ed182	2101
richardv	0:b079fa4ed182	2102	/***************** Bit definition for HRTIM_EECR1 register **************/
richardv	0:b079fa4ed182	2103	#define HRTIM_EECR1_EE1SRC ((uint32_t)0x00000003) /!< External event 1 source /
richardv	0:b079fa4ed182	2104	#define HRTIM_EECR1_EE1SRC_0 ((uint32_t)0x00000001) /!< External event 1 source bit 0 /
richardv	0:b079fa4ed182	2105	#define HRTIM_EECR1_EE1SRC_1 ((uint32_t)0x00000002) /!< External event 1 source bit 1 /
richardv	0:b079fa4ed182	2106	#define HRTIM_EECR1_EE1POL ((uint32_t)0x00000004) /!< External event 1 Polarity /
richardv	0:b079fa4ed182	2107	#define HRTIM_EECR1_EE1SNS ((uint32_t)0x00000018) /!< External event 1 sensitivity /
richardv	0:b079fa4ed182	2108	#define HRTIM_EECR1_EE1SNS_0 ((uint32_t)0x00000008) /!< External event 1 sensitivity bit 0 /
richardv	0:b079fa4ed182	2109	#define HRTIM_EECR1_EE1SNS_1 ((uint32_t)0x00000010) /!< External event 1 sensitivity bit 1 /
richardv	0:b079fa4ed182	2110	#define HRTIM_EECR1_EE1FAST ((uint32_t)0x00000020) /!< External event 1 Fast mode /
richardv	0:b079fa4ed182	2111
richardv	0:b079fa4ed182	2112	#define HRTIM_EECR1_EE2SRC ((uint32_t)0x000000C0) /!< External event 2 source /
richardv	0:b079fa4ed182	2113	#define HRTIM_EECR1_EE2SRC_0 ((uint32_t)0x00000040) /!< External event 2 source bit 0 /
richardv	0:b079fa4ed182	2114	#define HRTIM_EECR1_EE2SRC_1 ((uint32_t)0x00000080) /!< External event 2 source bit 1 /
richardv	0:b079fa4ed182	2115	#define HRTIM_EECR1_EE2POL ((uint32_t)0x00000100) /!< External event 2 Polarity /
richardv	0:b079fa4ed182	2116	#define HRTIM_EECR1_EE2SNS ((uint32_t)0x00000600) /!< External event 2 sensitivity /
richardv	0:b079fa4ed182	2117	#define HRTIM_EECR1_EE2SNS_0 ((uint32_t)0x00000200) /!< External event 2 sensitivity bit 0 /
richardv	0:b079fa4ed182	2118	#define HRTIM_EECR1_EE2SNS_1 ((uint32_t)0x00000400) /!< External event 2 sensitivity bit 1 /
richardv	0:b079fa4ed182	2119	#define HRTIM_EECR1_EE2FAST ((uint32_t)0x00000800) /!< External event 2 Fast mode /
richardv	0:b079fa4ed182	2120
richardv	0:b079fa4ed182	2121	#define HRTIM_EECR1_EE3SRC ((uint32_t)0x00003000) /!< External event 3 source /
richardv	0:b079fa4ed182	2122	#define HRTIM_EECR1_EE3SRC_0 ((uint32_t)0x00001000) /!< External event 3 source bit 0 /
richardv	0:b079fa4ed182	2123	#define HRTIM_EECR1_EE3SRC_1 ((uint32_t)0x00002000) /!< External event 3 source bit 1 /
richardv	0:b079fa4ed182	2124	#define HRTIM_EECR1_EE3POL ((uint32_t)0x00004000) /!< External event 3 Polarity /
richardv	0:b079fa4ed182	2125	#define HRTIM_EECR1_EE3SNS ((uint32_t)0x00018000) /!< External event 3 sensitivity /
richardv	0:b079fa4ed182	2126	#define HRTIM_EECR1_EE3SNS_0 ((uint32_t)0x00008000) /!< External event 3 sensitivity bit 0 /
richardv	0:b079fa4ed182	2127	#define HRTIM_EECR1_EE3SNS_1 ((uint32_t)0x00010000) /!< External event 3 sensitivity bit 1 /
richardv	0:b079fa4ed182	2128	#define HRTIM_EECR1_EE3FAST ((uint32_t)0x00020000) /!< External event 3 Fast mode /
richardv	0:b079fa4ed182	2129
richardv	0:b079fa4ed182	2130	#define HRTIM_EECR1_EE4SRC ((uint32_t)0x000C0000) /!< External event 4 source /
richardv	0:b079fa4ed182	2131	#define HRTIM_EECR1_EE4SRC_0 ((uint32_t)0x00040000) /!< External event 4 source bit 0 /
richardv	0:b079fa4ed182	2132	#define HRTIM_EECR1_EE4SRC_1 ((uint32_t)0x00080000) /!< External event 4 source bit 1 /
richardv	0:b079fa4ed182	2133	#define HRTIM_EECR1_EE4POL ((uint32_t)0x00100000) /!< External event 4 Polarity /
richardv	0:b079fa4ed182	2134	#define HRTIM_EECR1_EE4SNS ((uint32_t)0x00600000) /!< External event 4 sensitivity /
richardv	0:b079fa4ed182	2135	#define HRTIM_EECR1_EE4SNS_0 ((uint32_t)0x00200000) /!< External event 4 sensitivity bit 0 /
richardv	0:b079fa4ed182	2136	#define HRTIM_EECR1_EE4SNS_1 ((uint32_t)0x00400000) /!< External event 4 sensitivity bit 1 /
richardv	0:b079fa4ed182	2137	#define HRTIM_EECR1_EE4FAST ((uint32_t)0x00800000) /!< External event 4 Fast mode /
richardv	0:b079fa4ed182	2138
richardv	0:b079fa4ed182	2139	#define HRTIM_EECR1_EE5SRC ((uint32_t)0x03000000) /!< External event 5 source /
richardv	0:b079fa4ed182	2140	#define HRTIM_EECR1_EE5SRC_0 ((uint32_t)0x01000000) /!< External event 5 source bit 0 /
richardv	0:b079fa4ed182	2141	#define HRTIM_EECR1_EE5SRC_1 ((uint32_t)0x02000000) /!< External event 5 source bit 1 /
richardv	0:b079fa4ed182	2142	#define HRTIM_EECR1_EE5POL ((uint32_t)0x04000000) /!< External event 5 Polarity /
richardv	0:b079fa4ed182	2143	#define HRTIM_EECR1_EE5SNS ((uint32_t)0x18000000) /!< External event 5 sensitivity /
richardv	0:b079fa4ed182	2144	#define HRTIM_EECR1_EE5SNS_0 ((uint32_t)0x08000000) /!< External event 5 sensitivity bit 0 /
richardv	0:b079fa4ed182	2145	#define HRTIM_EECR1_EE5SNS_1 ((uint32_t)0x10000000) /!< External event 5 sensitivity bit 1 /
richardv	0:b079fa4ed182	2146	#define HRTIM_EECR1_EE5FAST ((uint32_t)0x20000000) /!< External event 5 Fast mode /
richardv	0:b079fa4ed182	2147
richardv	0:b079fa4ed182	2148	/***************** Bit definition for HRTIM_EECR2 register **************/
richardv	0:b079fa4ed182	2149	#define HRTIM_EECR2_EE6SRC ((uint32_t)0x00000003) /!< External event 6 source /
richardv	0:b079fa4ed182	2150	#define HRTIM_EECR2_EE6SRC_0 ((uint32_t)0x00000001) /!< External event 6 source bit 0 /
richardv	0:b079fa4ed182	2151	#define HRTIM_EECR2_EE6SRC_1 ((uint32_t)0x00000002) /!< External event 6 source bit 1 /
richardv	0:b079fa4ed182	2152	#define HRTIM_EECR2_EE6POL ((uint32_t)0x00000004) /!< External event 6 Polarity /
richardv	0:b079fa4ed182	2153	#define HRTIM_EECR2_EE6SNS ((uint32_t)0x00000018) /!< External event 6 sensitivity /
richardv	0:b079fa4ed182	2154	#define HRTIM_EECR2_EE6SNS_0 ((uint32_t)0x00000008) /!< External event 6 sensitivity bit 0 /
richardv	0:b079fa4ed182	2155	#define HRTIM_EECR2_EE6SNS_1 ((uint32_t)0x00000010) /!< External event 6 sensitivity bit 1 /
richardv	0:b079fa4ed182	2156
richardv	0:b079fa4ed182	2157	#define HRTIM_EECR2_EE7SRC ((uint32_t)0x000000C0) /!< External event 7 source /
richardv	0:b079fa4ed182	2158	#define HRTIM_EECR2_EE7SRC_0 ((uint32_t)0x00000040) /!< External event 7 source bit 0 /
richardv	0:b079fa4ed182	2159	#define HRTIM_EECR2_EE7SRC_1 ((uint32_t)0x00000080) /!< External event 7 source bit 1 /
richardv	0:b079fa4ed182	2160	#define HRTIM_EECR2_EE7POL ((uint32_t)0x00000100) /!< External event 7 Polarity /
richardv	0:b079fa4ed182	2161	#define HRTIM_EECR2_EE7SNS ((uint32_t)0x00000600) /!< External event 7 sensitivity /
richardv	0:b079fa4ed182	2162	#define HRTIM_EECR2_EE7SNS_0 ((uint32_t)0x00000200) /!< External event 7 sensitivity bit 0 /
richardv	0:b079fa4ed182	2163	#define HRTIM_EECR2_EE7SNS_1 ((uint32_t)0x00000400) /!< External event 7 sensitivity bit 1 /
richardv	0:b079fa4ed182	2164
richardv	0:b079fa4ed182	2165	#define HRTIM_EECR2_EE8SRC ((uint32_t)0x00003000) /!< External event 8 source /
richardv	0:b079fa4ed182	2166	#define HRTIM_EECR2_EE8SRC_0 ((uint32_t)0x00001000) /!< External event 8 source bit 0 /
richardv	0:b079fa4ed182	2167	#define HRTIM_EECR2_EE8SRC_1 ((uint32_t)0x00002000) /!< External event 8 source bit 1 /
richardv	0:b079fa4ed182	2168	#define HRTIM_EECR2_EE8POL ((uint32_t)0x00004000) /!< External event 8 Polarity /
richardv	0:b079fa4ed182	2169	#define HRTIM_EECR2_EE8SNS ((uint32_t)0x00018000) /!< External event 8 sensitivity /
richardv	0:b079fa4ed182	2170	#define HRTIM_EECR2_EE8SNS_0 ((uint32_t)0x00008000) /!< External event 8 sensitivity bit 0 /
richardv	0:b079fa4ed182	2171	#define HRTIM_EECR2_EE8SNS_1 ((uint32_t)0x00010000) /!< External event 8 sensitivity bit 1 /
richardv	0:b079fa4ed182	2172
richardv	0:b079fa4ed182	2173	#define HRTIM_EECR2_EE9SRC ((uint32_t)0x000C0000) /!< External event 9 source /
richardv	0:b079fa4ed182	2174	#define HRTIM_EECR2_EE9SRC_0 ((uint32_t)0x00040000) /!< External event 9 source bit 0 /
richardv	0:b079fa4ed182	2175	#define HRTIM_EECR2_EE9SRC_1 ((uint32_t)0x00080000) /!< External event 9 source bit 1 /
richardv	0:b079fa4ed182	2176	#define HRTIM_EECR2_EE9POL ((uint32_t)0x00100000) /!< External event 9 Polarity /
richardv	0:b079fa4ed182	2177	#define HRTIM_EECR2_EE9SNS ((uint32_t)0x00600000) /!< External event 9 sensitivity /
richardv	0:b079fa4ed182	2178	#define HRTIM_EECR2_EE9SNS_0 ((uint32_t)0x00200000) /!< External event 9 sensitivity bit 0 /
richardv	0:b079fa4ed182	2179	#define HRTIM_EECR2_EE9SNS_1 ((uint32_t)0x00400000) /!< External event 9 sensitivity bit 1 /
richardv	0:b079fa4ed182	2180
richardv	0:b079fa4ed182	2181	#define HRTIM_EECR2_EE10SRC ((uint32_t)0x03000000) /!< External event 10 source /
richardv	0:b079fa4ed182	2182	#define HRTIM_EECR2_EE10SRC_0 ((uint32_t)0x01000000) /!< External event 10 source bit 0 /
richardv	0:b079fa4ed182	2183	#define HRTIM_EECR2_EE10SRC_1 ((uint32_t)0x02000000) /!< External event 10 source bit 1 /
richardv	0:b079fa4ed182	2184	#define HRTIM_EECR2_EE10POL ((uint32_t)0x04000000) /!< External event 10 Polarity /
richardv	0:b079fa4ed182	2185	#define HRTIM_EECR2_EE10SNS ((uint32_t)0x18000000) /!< External event 10 sensitivity /
richardv	0:b079fa4ed182	2186	#define HRTIM_EECR2_EE10SNS_0 ((uint32_t)0x08000000) /!< External event 10 sensitivity bit 0 /
richardv	0:b079fa4ed182	2187	#define HRTIM_EECR2_EE10SNS_1 ((uint32_t)0x10000000) /!< External event 10 sensitivity bit 1 /
richardv	0:b079fa4ed182	2188
richardv	0:b079fa4ed182	2189	/***************** Bit definition for HRTIM_EECR3 register **************/
richardv	0:b079fa4ed182	2190	#define HRTIM_EECR3_EE6F ((uint32_t)0x0000000F) /!< External event 6 filter /
richardv	0:b079fa4ed182	2191	#define HRTIM_EECR3_EE6F_0 ((uint32_t)0x00000001) /!< External event 6 filter bit 0 /
richardv	0:b079fa4ed182	2192	#define HRTIM_EECR3_EE6F_1 ((uint32_t)0x00000002) /!< External event 6 filter bit 1 /
richardv	0:b079fa4ed182	2193	#define HRTIM_EECR3_EE6F_2 ((uint32_t)0x00000004) /!< External event 6 filter bit 2 /
richardv	0:b079fa4ed182	2194	#define HRTIM_EECR3_EE6F_3 ((uint32_t)0x00000008) /!< External event 6 filter bit 3 /
richardv	0:b079fa4ed182	2195	#define HRTIM_EECR3_EE7F ((uint32_t)0x000003C0) /!< External event 7 filter /
richardv	0:b079fa4ed182	2196	#define HRTIM_EECR3_EE7F_0 ((uint32_t)0x00000040) /!< External event 7 filter bit 0 /
richardv	0:b079fa4ed182	2197	#define HRTIM_EECR3_EE7F_1 ((uint32_t)0x00000080) /!< External event 7 filter bit 1 /
richardv	0:b079fa4ed182	2198	#define HRTIM_EECR3_EE7F_2 ((uint32_t)0x00000100) /!< External event 7 filter bit 2 /
richardv	0:b079fa4ed182	2199	#define HRTIM_EECR3_EE7F_3 ((uint32_t)0x00000200) /!< External event 7 filter bit 3 /
richardv	0:b079fa4ed182	2200	#define HRTIM_EECR3_EE8F ((uint32_t)0x0000F000) /!< External event 8 filter /
richardv	0:b079fa4ed182	2201	#define HRTIM_EECR3_EE8F_0 ((uint32_t)0x00001000) /!< External event 8 filter bit 0 /
richardv	0:b079fa4ed182	2202	#define HRTIM_EECR3_EE8F_1 ((uint32_t)0x00002000) /!< External event 8 filter bit 1 /
richardv	0:b079fa4ed182	2203	#define HRTIM_EECR3_EE8F_2 ((uint32_t)0x00004000) /!< External event 8 filter bit 2 /
richardv	0:b079fa4ed182	2204	#define HRTIM_EECR3_EE8F_3 ((uint32_t)0x00008000) /!< External event 8 filter bit 3 /
richardv	0:b079fa4ed182	2205	#define HRTIM_EECR3_EE9F ((uint32_t)0x003C0000) /!< External event 9 filter /
richardv	0:b079fa4ed182	2206	#define HRTIM_EECR3_EE9F_0 ((uint32_t)0x00040000) /!< External event 9 filter bit 0 /
richardv	0:b079fa4ed182	2207	#define HRTIM_EECR3_EE9F_1 ((uint32_t)0x00080000) /!< External event 9 filter bit 1 /
richardv	0:b079fa4ed182	2208	#define HRTIM_EECR3_EE9F_2 ((uint32_t)0x00100000) /!< External event 9 filter bit 2 /
richardv	0:b079fa4ed182	2209	#define HRTIM_EECR3_EE9F_3 ((uint32_t)0x00200000) /!< External event 9 filter bit 3 /
richardv	0:b079fa4ed182	2210	#define HRTIM_EECR3_EE10F ((uint32_t)0x0F000000) /!< External event 10 filter /
richardv	0:b079fa4ed182	2211	#define HRTIM_EECR3_EE10F_0 ((uint32_t)0x01000000) /!< External event 10 filter bit 0 /
richardv	0:b079fa4ed182	2212	#define HRTIM_EECR3_EE10F_1 ((uint32_t)0x02000000) /!< External event 10 filter bit 1 /
richardv	0:b079fa4ed182	2213	#define HRTIM_EECR3_EE10F_2 ((uint32_t)0x04000000) /!< External event 10 filter bit 2 /
richardv	0:b079fa4ed182	2214	#define HRTIM_EECR3_EE10F_3 ((uint32_t)0x08000000) /!< External event 10 filter bit 3 /
richardv	0:b079fa4ed182	2215	#define HRTIM_EECR3_EEVSD ((uint32_t)0xC0000000) /!< External event sampling clock division /
richardv	0:b079fa4ed182	2216	#define HRTIM_EECR3_EEVSD_0 ((uint32_t)0x40000000) /!< External event sampling clock division bit 0 /
richardv	0:b079fa4ed182	2217	#define HRTIM_EECR3_EEVSD_1 ((uint32_t)0x80000000) /!< External event sampling clock division bit 1 /
richardv	0:b079fa4ed182	2218
richardv	0:b079fa4ed182	2219	/***************** Bit definition for HRTIM_ADC1R register **************/
richardv	0:b079fa4ed182	2220	#define HRTIM_ADC1R_AD1MC1 ((uint32_t)0x00000001) /!< ADC Trigger 1 on master compare 1 /
richardv	0:b079fa4ed182	2221	#define HRTIM_ADC1R_AD1MC2 ((uint32_t)0x00000002) /!< ADC Trigger 1 on master compare 2 /
richardv	0:b079fa4ed182	2222	#define HRTIM_ADC1R_AD1MC3 ((uint32_t)0x00000004) /!< ADC Trigger 1 on master compare 3 /
richardv	0:b079fa4ed182	2223	#define HRTIM_ADC1R_AD1MC4 ((uint32_t)0x00000008) /!< ADC Trigger 1 on master compare 4 /
richardv	0:b079fa4ed182	2224	#define HRTIM_ADC1R_AD1MPER ((uint32_t)0x00000010) /!< ADC Trigger 1 on master period /
richardv	0:b079fa4ed182	2225	#define HRTIM_ADC1R_AD1EEV1 ((uint32_t)0x00000020) /!< ADC Trigger 1 on external event 1 /
richardv	0:b079fa4ed182	2226	#define HRTIM_ADC1R_AD1EEV2 ((uint32_t)0x00000040) /!< ADC Trigger 1 on external event 2 /
richardv	0:b079fa4ed182	2227	#define HRTIM_ADC1R_AD1EEV3 ((uint32_t)0x00000080) /!< ADC Trigger 1 on external event 3 /
richardv	0:b079fa4ed182	2228	#define HRTIM_ADC1R_AD1EEV4 ((uint32_t)0x00000100) /!< ADC Trigger 1 on external event 4 /
richardv	0:b079fa4ed182	2229	#define HRTIM_ADC1R_AD1EEV5 ((uint32_t)0x00000200) /!< ADC Trigger 1 on external event 5 /
richardv	0:b079fa4ed182	2230	#define HRTIM_ADC1R_AD1TAC2 ((uint32_t)0x00000400) /!< ADC Trigger 1 on Timer A compare 2 /
richardv	0:b079fa4ed182	2231	#define HRTIM_ADC1R_AD1TAC3 ((uint32_t)0x00000800) /!< ADC Trigger 1 on Timer A compare 3 /
richardv	0:b079fa4ed182	2232	#define HRTIM_ADC1R_AD1TAC4 ((uint32_t)0x00001000) /!< ADC Trigger 1 on Timer A compare 4 /
richardv	0:b079fa4ed182	2233	#define HRTIM_ADC1R_AD1TAPER ((uint32_t)0x00002000) /!< ADC Trigger 1 on Timer A period /
richardv	0:b079fa4ed182	2234	#define HRTIM_ADC1R_AD1TARST ((uint32_t)0x00004000) /!< ADC Trigger 1 on Timer A reset /
richardv	0:b079fa4ed182	2235	#define HRTIM_ADC1R_AD1TBC2 ((uint32_t)0x00008000) /!< ADC Trigger 1 on Timer B compare 2 /
richardv	0:b079fa4ed182	2236	#define HRTIM_ADC1R_AD1TBC3 ((uint32_t)0x00010000) /!< ADC Trigger 1 on Timer B compare 3 /
richardv	0:b079fa4ed182	2237	#define HRTIM_ADC1R_AD1TBC4 ((uint32_t)0x00020000) /!< ADC Trigger 1 on Timer B compare 4 /
richardv	0:b079fa4ed182	2238	#define HRTIM_ADC1R_AD1TBPER ((uint32_t)0x00040000) /!< ADC Trigger 1 on Timer B period /
richardv	0:b079fa4ed182	2239	#define HRTIM_ADC1R_AD1TBRST ((uint32_t)0x00080000) /!< ADC Trigger 1 on Timer B reset /
richardv	0:b079fa4ed182	2240	#define HRTIM_ADC1R_AD1TCC2 ((uint32_t)0x00100000) /!< ADC Trigger 1 on Timer C compare 2 /
richardv	0:b079fa4ed182	2241	#define HRTIM_ADC1R_AD1TCC3 ((uint32_t)0x00200000) /!< ADC Trigger 1 on Timer C compare 3 /
richardv	0:b079fa4ed182	2242	#define HRTIM_ADC1R_AD1TCC4 ((uint32_t)0x00400000) /!< ADC Trigger 1 on Timer C compare 4 /
richardv	0:b079fa4ed182	2243	#define HRTIM_ADC1R_AD1TCPER ((uint32_t)0x00800000) /!< ADC Trigger 1 on Timer C period /
richardv	0:b079fa4ed182	2244	#define HRTIM_ADC1R_AD1TDC2 ((uint32_t)0x01000000) /!< ADC Trigger 1 on Timer D compare 2 /
richardv	0:b079fa4ed182	2245	#define HRTIM_ADC1R_AD1TDC3 ((uint32_t)0x02000000) /!< ADC Trigger 1 on Timer D compare 3 /
richardv	0:b079fa4ed182	2246	#define HRTIM_ADC1R_AD1TDC4 ((uint32_t)0x04000000) /!< ADC Trigger 1 on Timer D compare 4 /
richardv	0:b079fa4ed182	2247	#define HRTIM_ADC1R_AD1TDPER ((uint32_t)0x08000000) /!< ADC Trigger 1 on Timer D period /
richardv	0:b079fa4ed182	2248	#define HRTIM_ADC1R_AD1TEC2 ((uint32_t)0x10000000) /!< ADC Trigger 1 on Timer E compare 2 /
richardv	0:b079fa4ed182	2249	#define HRTIM_ADC1R_AD1TEC3 ((uint32_t)0x20000000) /!< ADC Trigger 1 on Timer E compare 3 /
richardv	0:b079fa4ed182	2250	#define HRTIM_ADC1R_AD1TEC4 ((uint32_t)0x40000000) /!< ADC Trigger 1 on Timer E compare 4 /
richardv	0:b079fa4ed182	2251	#define HRTIM_ADC1R_AD1TEPER ((uint32_t)0x80000000) /!< ADC Trigger 1 on Timer E period /
richardv	0:b079fa4ed182	2252
richardv	0:b079fa4ed182	2253	/***************** Bit definition for HRTIM_ADC2R register **************/
richardv	0:b079fa4ed182	2254	#define HRTIM_ADC2R_AD2MC1 ((uint32_t)0x00000001) /!< ADC Trigger 2 on master compare 1 /
richardv	0:b079fa4ed182	2255	#define HRTIM_ADC2R_AD2MC2 ((uint32_t)0x00000002) /!< ADC Trigger 2 on master compare 2 /
richardv	0:b079fa4ed182	2256	#define HRTIM_ADC2R_AD2MC3 ((uint32_t)0x00000004) /!< ADC Trigger 2 on master compare 3 /
richardv	0:b079fa4ed182	2257	#define HRTIM_ADC2R_AD2MC4 ((uint32_t)0x00000008) /!< ADC Trigger 2 on master compare 4 /
richardv	0:b079fa4ed182	2258	#define HRTIM_ADC2R_AD2MPER ((uint32_t)0x00000010) /!< ADC Trigger 2 on master period /
richardv	0:b079fa4ed182	2259	#define HRTIM_ADC2R_AD2EEV6 ((uint32_t)0x00000020) /!< ADC Trigger 2 on external event 6 /
richardv	0:b079fa4ed182	2260	#define HRTIM_ADC2R_AD2EEV7 ((uint32_t)0x00000040) /!< ADC Trigger 2 on external event 7 /
richardv	0:b079fa4ed182	2261	#define HRTIM_ADC2R_AD2EEV8 ((uint32_t)0x00000080) /!< ADC Trigger 2 on external event 8 /
richardv	0:b079fa4ed182	2262	#define HRTIM_ADC2R_AD2EEV9 ((uint32_t)0x00000100) /!< ADC Trigger 2 on external event 9 /
richardv	0:b079fa4ed182	2263	#define HRTIM_ADC2R_AD2EEV10 ((uint32_t)0x00000200) /!< ADC Trigger 2 on external event 10 /
richardv	0:b079fa4ed182	2264	#define HRTIM_ADC2R_AD2TAC2 ((uint32_t)0x00000400) /!< ADC Trigger 2 on Timer A compare 2 /
richardv	0:b079fa4ed182	2265	#define HRTIM_ADC2R_AD2TAC3 ((uint32_t)0x00000800) /!< ADC Trigger 2 on Timer A compare 3 /
richardv	0:b079fa4ed182	2266	#define HRTIM_ADC2R_AD2TAC4 ((uint32_t)0x00001000) /!< ADC Trigger 2 on Timer A compare 4/
richardv	0:b079fa4ed182	2267	#define HRTIM_ADC2R_AD2TAPER ((uint32_t)0x00002000) /!< ADC Trigger 2 on Timer A period /
richardv	0:b079fa4ed182	2268	#define HRTIM_ADC2R_AD2TBC2 ((uint32_t)0x00004000) /!< ADC Trigger 2 on Timer B compare 2 /
richardv	0:b079fa4ed182	2269	#define HRTIM_ADC2R_AD2TBC3 ((uint32_t)0x00008000) /!< ADC Trigger 2 on Timer B compare 3 /
richardv	0:b079fa4ed182	2270	#define HRTIM_ADC2R_AD2TBC4 ((uint32_t)0x00010000) /!< ADC Trigger 2 on Timer B compare 4 /
richardv	0:b079fa4ed182	2271	#define HRTIM_ADC2R_AD2TBPER ((uint32_t)0x00020000) /!< ADC Trigger 2 on Timer B period /
richardv	0:b079fa4ed182	2272	#define HRTIM_ADC2R_AD2TCC2 ((uint32_t)0x00040000) /!< ADC Trigger 2 on Timer C compare 2 /
richardv	0:b079fa4ed182	2273	#define HRTIM_ADC2R_AD2TCC3 ((uint32_t)0x00080000) /!< ADC Trigger 2 on Timer C compare 3 /
richardv	0:b079fa4ed182	2274	#define HRTIM_ADC2R_AD2TCC4 ((uint32_t)0x00100000) /!< ADC Trigger 2 on Timer C compare 4 /
richardv	0:b079fa4ed182	2275	#define HRTIM_ADC2R_AD2TCPER ((uint32_t)0x00200000) /!< ADC Trigger 2 on Timer C period /
richardv	0:b079fa4ed182	2276	#define HRTIM_ADC2R_AD2TCRST ((uint32_t)0x00400000) /!< ADC Trigger 2 on Timer C reset /
richardv	0:b079fa4ed182	2277	#define HRTIM_ADC2R_AD2TDC2 ((uint32_t)0x00800000) /!< ADC Trigger 2 on Timer D compare 2 /
richardv	0:b079fa4ed182	2278	#define HRTIM_ADC2R_AD2TDC3 ((uint32_t)0x01000000) /!< ADC Trigger 2 on Timer D compare 3 /
richardv	0:b079fa4ed182	2279	#define HRTIM_ADC2R_AD2TDC4 ((uint32_t)0x02000000) /!< ADC Trigger 2 on Timer D compare 4/
richardv	0:b079fa4ed182	2280	#define HRTIM_ADC2R_AD2TDPER ((uint32_t)0x04000000) /!< ADC Trigger 2 on Timer D period /
richardv	0:b079fa4ed182	2281	#define HRTIM_ADC2R_AD2TDRST ((uint32_t)0x08000000) /!< ADC Trigger 2 on Timer D reset /
richardv	0:b079fa4ed182	2282	#define HRTIM_ADC2R_AD2TEC2 ((uint32_t)0x10000000) /!< ADC Trigger 2 on Timer E compare 2 /
richardv	0:b079fa4ed182	2283	#define HRTIM_ADC2R_AD2TEC3 ((uint32_t)0x20000000) /!< ADC Trigger 2 on Timer E compare 3 /
richardv	0:b079fa4ed182	2284	#define HRTIM_ADC2R_AD2TEC4 ((uint32_t)0x40000000) /!< ADC Trigger 2 on Timer E compare 4 /
richardv	0:b079fa4ed182	2285	#define HRTIM_ADC2R_AD2TERST ((uint32_t)0x80000000) /!< ADC Trigger 2 on Timer E reset /
richardv	0:b079fa4ed182	2286
richardv	0:b079fa4ed182	2287	/***************** Bit definition for HRTIM_ADC3R register **************/
richardv	0:b079fa4ed182	2288	#define HRTIM_ADC3R_AD3MC1 ((uint32_t)0x00000001) /!< ADC Trigger 3 on master compare 1 /
richardv	0:b079fa4ed182	2289	#define HRTIM_ADC3R_AD3MC2 ((uint32_t)0x00000002) /!< ADC Trigger 3 on master compare 2 /
richardv	0:b079fa4ed182	2290	#define HRTIM_ADC3R_AD3MC3 ((uint32_t)0x00000004) /!< ADC Trigger 3 on master compare 3 /
richardv	0:b079fa4ed182	2291	#define HRTIM_ADC3R_AD3MC4 ((uint32_t)0x00000008) /!< ADC Trigger 3 on master compare 4 /
richardv	0:b079fa4ed182	2292	#define HRTIM_ADC3R_AD3MPER ((uint32_t)0x00000010) /!< ADC Trigger 3 on master period /
richardv	0:b079fa4ed182	2293	#define HRTIM_ADC3R_AD3EEV1 ((uint32_t)0x00000020) /!< ADC Trigger 3 on external event 1 /
richardv	0:b079fa4ed182	2294	#define HRTIM_ADC3R_AD3EEV2 ((uint32_t)0x00000040) /!< ADC Trigger 3 on external event 2 /
richardv	0:b079fa4ed182	2295	#define HRTIM_ADC3R_AD3EEV3 ((uint32_t)0x00000080) /!< ADC Trigger 3 on external event 3 /
richardv	0:b079fa4ed182	2296	#define HRTIM_ADC3R_AD3EEV4 ((uint32_t)0x00000100) /!< ADC Trigger 3 on external event 4 /
richardv	0:b079fa4ed182	2297	#define HRTIM_ADC3R_AD3EEV5 ((uint32_t)0x00000200) /!< ADC Trigger 3 on external event 5 /
richardv	0:b079fa4ed182	2298	#define HRTIM_ADC3R_AD3TAC2 ((uint32_t)0x00000400) /!< ADC Trigger 3 on Timer A compare 2 /
richardv	0:b079fa4ed182	2299	#define HRTIM_ADC3R_AD3TAC3 ((uint32_t)0x00000800) /!< ADC Trigger 3 on Timer A compare 3 /
richardv	0:b079fa4ed182	2300	#define HRTIM_ADC3R_AD3TAC4 ((uint32_t)0x00001000) /!< ADC Trigger 3 on Timer A compare 4 /
richardv	0:b079fa4ed182	2301	#define HRTIM_ADC3R_AD3TAPER ((uint32_t)0x00002000) /!< ADC Trigger 3 on Timer A period /
richardv	0:b079fa4ed182	2302	#define HRTIM_ADC3R_AD3TARST ((uint32_t)0x00004000) /!< ADC Trigger 3 on Timer A reset /
richardv	0:b079fa4ed182	2303	#define HRTIM_ADC3R_AD3TBC2 ((uint32_t)0x00008000) /!< ADC Trigger 3 on Timer B compare 2 /
richardv	0:b079fa4ed182	2304	#define HRTIM_ADC3R_AD3TBC3 ((uint32_t)0x00010000) /!< ADC Trigger 3 on Timer B compare 3 /
richardv	0:b079fa4ed182	2305	#define HRTIM_ADC3R_AD3TBC4 ((uint32_t)0x00020000) /!< ADC Trigger 3 on Timer B compare 4 /
richardv	0:b079fa4ed182	2306	#define HRTIM_ADC3R_AD3TBPER ((uint32_t)0x00040000) /!< ADC Trigger 3 on Timer B period /
richardv	0:b079fa4ed182	2307	#define HRTIM_ADC3R_AD3TBRST ((uint32_t)0x00080000) /!< ADC Trigger 3 on Timer B reset /
richardv	0:b079fa4ed182	2308	#define HRTIM_ADC3R_AD3TCC2 ((uint32_t)0x00100000) /!< ADC Trigger 3 on Timer C compare 2 /
richardv	0:b079fa4ed182	2309	#define HRTIM_ADC3R_AD3TCC3 ((uint32_t)0x00200000) /!< ADC Trigger 3 on Timer C compare 3 /
richardv	0:b079fa4ed182	2310	#define HRTIM_ADC3R_AD3TCC4 ((uint32_t)0x00400000) /!< ADC Trigger 3 on Timer C compare 4 /
richardv	0:b079fa4ed182	2311	#define HRTIM_ADC3R_AD3TCPER ((uint32_t)0x00800000) /!< ADC Trigger 3 on Timer C period /
richardv	0:b079fa4ed182	2312	#define HRTIM_ADC3R_AD3TDC2 ((uint32_t)0x01000000) /!< ADC Trigger 3 on Timer D compare 2 /
richardv	0:b079fa4ed182	2313	#define HRTIM_ADC3R_AD3TDC3 ((uint32_t)0x02000000) /!< ADC Trigger 3 on Timer D compare 3 /
richardv	0:b079fa4ed182	2314	#define HRTIM_ADC3R_AD3TDC4 ((uint32_t)0x04000000) /!< ADC Trigger 3 on Timer D compare 4 /
richardv	0:b079fa4ed182	2315	#define HRTIM_ADC3R_AD3TDPER ((uint32_t)0x08000000) /!< ADC Trigger 3 on Timer D period /
richardv	0:b079fa4ed182	2316	#define HRTIM_ADC3R_AD3TEC2 ((uint32_t)0x10000000) /!< ADC Trigger 3 on Timer E compare 2 /
richardv	0:b079fa4ed182	2317	#define HRTIM_ADC3R_AD3TEC3 ((uint32_t)0x20000000) /!< ADC Trigger 3 on Timer E compare 3 /
richardv	0:b079fa4ed182	2318	#define HRTIM_ADC3R_AD3TEC4 ((uint32_t)0x40000000) /!< ADC Trigger 3 on Timer E compare 4 /
richardv	0:b079fa4ed182	2319	#define HRTIM_ADC3R_AD3TEPER ((uint32_t)0x80000000) /!< ADC Trigger 3 on Timer E period /
richardv	0:b079fa4ed182	2320
richardv	0:b079fa4ed182	2321	/***************** Bit definition for HRTIM_ADC4R register **************/
richardv	0:b079fa4ed182	2322	#define HRTIM_ADC4R_AD4MC1 ((uint32_t)0x00000001) /!< ADC Trigger 4 on master compare 1 /
richardv	0:b079fa4ed182	2323	#define HRTIM_ADC4R_AD4MC2 ((uint32_t)0x00000002) /!< ADC Trigger 4 on master compare 2 /
richardv	0:b079fa4ed182	2324	#define HRTIM_ADC4R_AD4MC3 ((uint32_t)0x00000004) /!< ADC Trigger 4 on master compare 3 /
richardv	0:b079fa4ed182	2325	#define HRTIM_ADC4R_AD4MC4 ((uint32_t)0x00000008) /!< ADC Trigger 4 on master compare 4 /
richardv	0:b079fa4ed182	2326	#define HRTIM_ADC4R_AD4MPER ((uint32_t)0x00000010) /!< ADC Trigger 4 on master period /
richardv	0:b079fa4ed182	2327	#define HRTIM_ADC4R_AD4EEV6 ((uint32_t)0x00000020) /!< ADC Trigger 4 on external event 6 /
richardv	0:b079fa4ed182	2328	#define HRTIM_ADC4R_AD4EEV7 ((uint32_t)0x00000040) /!< ADC Trigger 4 on external event 7 /
richardv	0:b079fa4ed182	2329	#define HRTIM_ADC4R_AD4EEV8 ((uint32_t)0x00000080) /!< ADC Trigger 4 on external event 8 /
richardv	0:b079fa4ed182	2330	#define HRTIM_ADC4R_AD4EEV9 ((uint32_t)0x00000100) /!< ADC Trigger 4 on external event 9 /
richardv	0:b079fa4ed182	2331	#define HRTIM_ADC4R_AD4EEV10 ((uint32_t)0x00000200) /!< ADC Trigger 4 on external event 10 /
richardv	0:b079fa4ed182	2332	#define HRTIM_ADC4R_AD4TAC2 ((uint32_t)0x00000400) /!< ADC Trigger 4 on Timer A compare 2 /
richardv	0:b079fa4ed182	2333	#define HRTIM_ADC4R_AD4TAC3 ((uint32_t)0x00000800) /!< ADC Trigger 4 on Timer A compare 3 /
richardv	0:b079fa4ed182	2334	#define HRTIM_ADC4R_AD4TAC4 ((uint32_t)0x00001000) /!< ADC Trigger 4 on Timer A compare 4/
richardv	0:b079fa4ed182	2335	#define HRTIM_ADC4R_AD4TAPER ((uint32_t)0x00002000) /!< ADC Trigger 4 on Timer A period /
richardv	0:b079fa4ed182	2336	#define HRTIM_ADC4R_AD4TBC2 ((uint32_t)0x00004000) /!< ADC Trigger 4 on Timer B compare 2 /
richardv	0:b079fa4ed182	2337	#define HRTIM_ADC4R_AD4TBC3 ((uint32_t)0x00008000) /!< ADC Trigger 4 on Timer B compare 3 /
richardv	0:b079fa4ed182	2338	#define HRTIM_ADC4R_AD4TBC4 ((uint32_t)0x00010000) /!< ADC Trigger 4 on Timer B compare 4 /
richardv	0:b079fa4ed182	2339	#define HRTIM_ADC4R_AD4TBPER ((uint32_t)0x00020000) /!< ADC Trigger 4 on Timer B period /
richardv	0:b079fa4ed182	2340	#define HRTIM_ADC4R_AD4TCC2 ((uint32_t)0x00040000) /!< ADC Trigger 4 on Timer C compare 2 /
richardv	0:b079fa4ed182	2341	#define HRTIM_ADC4R_AD4TCC3 ((uint32_t)0x00080000) /!< ADC Trigger 4 on Timer C compare 3 /
richardv	0:b079fa4ed182	2342	#define HRTIM_ADC4R_AD4TCC4 ((uint32_t)0x00100000) /!< ADC Trigger 4 on Timer C compare 4 /
richardv	0:b079fa4ed182	2343	#define HRTIM_ADC4R_AD4TCPER ((uint32_t)0x00200000) /!< ADC Trigger 4 on Timer C period /
richardv	0:b079fa4ed182	2344	#define HRTIM_ADC4R_AD4TCRST ((uint32_t)0x00400000) /!< ADC Trigger 4 on Timer C reset /
richardv	0:b079fa4ed182	2345	#define HRTIM_ADC4R_AD4TDC2 ((uint32_t)0x00800000) /!< ADC Trigger 4 on Timer D compare 2 /
richardv	0:b079fa4ed182	2346	#define HRTIM_ADC4R_AD4TDC3 ((uint32_t)0x01000000) /!< ADC Trigger 4 on Timer D compare 3 /
richardv	0:b079fa4ed182	2347	#define HRTIM_ADC4R_AD4TDC4 ((uint32_t)0x02000000) /!< ADC Trigger 4 on Timer D compare 4/
richardv	0:b079fa4ed182	2348	#define HRTIM_ADC4R_AD4TDPER ((uint32_t)0x04000000) /!< ADC Trigger 4 on Timer D period /
richardv	0:b079fa4ed182	2349	#define HRTIM_ADC4R_AD4TDRST ((uint32_t)0x08000000) /!< ADC Trigger 4 on Timer D reset /
richardv	0:b079fa4ed182	2350	#define HRTIM_ADC4R_AD4TEC2 ((uint32_t)0x10000000) /!< ADC Trigger 4 on Timer E compare 2 /
richardv	0:b079fa4ed182	2351	#define HRTIM_ADC4R_AD4TEC3 ((uint32_t)0x20000000) /!< ADC Trigger 4 on Timer E compare 3 /
richardv	0:b079fa4ed182	2352	#define HRTIM_ADC4R_AD4TEC4 ((uint32_t)0x40000000) /!< ADC Trigger 4 on Timer E compare 4 /
richardv	0:b079fa4ed182	2353	#define HRTIM_ADC4R_AD4TERST ((uint32_t)0x80000000) /!< ADC Trigger 4 on Timer E reset /
richardv	0:b079fa4ed182	2354
richardv	0:b079fa4ed182	2355	/***************** Bit definition for HRTIM_DLLCR register **************/
richardv	0:b079fa4ed182	2356	#define HRTIM_DLLCR_CAL ((uint32_t)0x00000001) /!< DLL calibration start /
richardv	0:b079fa4ed182	2357	#define HRTIM_DLLCR_CALEN ((uint32_t)0x00000002) /!< DLL calibration enable /
richardv	0:b079fa4ed182	2358	#define HRTIM_DLLCR_CALRTE ((uint32_t)0x0000000C) /!< DLL calibration rate /
richardv	0:b079fa4ed182	2359	#define HRTIM_DLLCR_CALRTE_0 ((uint32_t)0x00000004) /!< DLL calibration rate bit 0 /
richardv	0:b079fa4ed182	2360	#define HRTIM_DLLCR_CALRTE_1 ((uint32_t)0x00000008) /!< DLL calibration rate bit 1 /
richardv	0:b079fa4ed182	2361
richardv	0:b079fa4ed182	2362	/***************** Bit definition for HRTIM_FLTINR1 register *************/
richardv	0:b079fa4ed182	2363	#define HRTIM_FLTINR1_FLT1E ((uint32_t)0x00000001) /!< Fault 1 enable /
richardv	0:b079fa4ed182	2364	#define HRTIM_FLTINR1_FLT1P ((uint32_t)0x00000002) /!< Fault 1 polarity /
richardv	0:b079fa4ed182	2365	#define HRTIM_FLTINR1_FLT1SRC ((uint32_t)0x00000004) /!< Fault 1 source /
richardv	0:b079fa4ed182	2366	#define HRTIM_FLTINR1_FLT1F ((uint32_t)0x00000078) /!< Fault 1 filter /
richardv	0:b079fa4ed182	2367	#define HRTIM_FLTINR1_FLT1F_0 ((uint32_t)0x00000008) /!< Fault 1 filter bit 0 /
richardv	0:b079fa4ed182	2368	#define HRTIM_FLTINR1_FLT1F_1 ((uint32_t)0x00000010) /!< Fault 1 filter bit 1 /
richardv	0:b079fa4ed182	2369	#define HRTIM_FLTINR1_FLT1F_2 ((uint32_t)0x00000020) /!< Fault 1 filter bit 2 /
richardv	0:b079fa4ed182	2370	#define HRTIM_FLTINR1_FLT1F_3 ((uint32_t)0x00000040) /!< Fault 1 filter bit 3 /
richardv	0:b079fa4ed182	2371	#define HRTIM_FLTINR1_FLT1LCK ((uint32_t)0x00000080) /!< Fault 1 lock /
richardv	0:b079fa4ed182	2372
richardv	0:b079fa4ed182	2373	#define HRTIM_FLTINR1_FLT2E ((uint32_t)0x00000100) /!< Fault 2 enable /
richardv	0:b079fa4ed182	2374	#define HRTIM_FLTINR1_FLT2P ((uint32_t)0x00000200) /!< Fault 2 polarity /
richardv	0:b079fa4ed182	2375	#define HRTIM_FLTINR1_FLT2SRC ((uint32_t)0x00000400) /!< Fault 2 source /
richardv	0:b079fa4ed182	2376	#define HRTIM_FLTINR1_FLT2F ((uint32_t)0x00007800) /!< Fault 2 filter /
richardv	0:b079fa4ed182	2377	#define HRTIM_FLTINR1_FLT2F_0 ((uint32_t)0x00000800) /!< Fault 2 filter bit 0 /
richardv	0:b079fa4ed182	2378	#define HRTIM_FLTINR1_FLT2F_1 ((uint32_t)0x00001000) /!< Fault 2 filter bit 1 /
richardv	0:b079fa4ed182	2379	#define HRTIM_FLTINR1_FLT2F_2 ((uint32_t)0x00002000) /!< Fault 2 filter bit 2 /
richardv	0:b079fa4ed182	2380	#define HRTIM_FLTINR1_FLT2F_3 ((uint32_t)0x00004000) /!< Fault 2 filter bit 3 /
richardv	0:b079fa4ed182	2381	#define HRTIM_FLTINR1_FLT2LCK ((uint32_t)0x00008000) /!< Fault 2 lock /
richardv	0:b079fa4ed182	2382
richardv	0:b079fa4ed182	2383	#define HRTIM_FLTINR1_FLT3E ((uint32_t)0x00010000) /!< Fault 3 enable /
richardv	0:b079fa4ed182	2384	#define HRTIM_FLTINR1_FLT3P ((uint32_t)0x00020000) /!< Fault 3 polarity /
richardv	0:b079fa4ed182	2385	#define HRTIM_FLTINR1_FLT3SRC ((uint32_t)0x00040000) /!< Fault 3 source /
richardv	0:b079fa4ed182	2386	#define HRTIM_FLTINR1_FLT3F ((uint32_t)0x00780000) /!< Fault 3 filter /
richardv	0:b079fa4ed182	2387	#define HRTIM_FLTINR1_FLT3F_0 ((uint32_t)0x00080000) /!< Fault 3 filter bit 0 /
richardv	0:b079fa4ed182	2388	#define HRTIM_FLTINR1_FLT3F_1 ((uint32_t)0x00100000) /!< Fault 3 filter bit 1 /
richardv	0:b079fa4ed182	2389	#define HRTIM_FLTINR1_FLT3F_2 ((uint32_t)0x00200000) /!< Fault 3 filter bit 2 /
richardv	0:b079fa4ed182	2390	#define HRTIM_FLTINR1_FLT3F_3 ((uint32_t)0x00400000) /!< Fault 3 filter bit 3 /
richardv	0:b079fa4ed182	2391	#define HRTIM_FLTINR1_FLT3LCK ((uint32_t)0x00800000) /!< Fault 3 lock /
richardv	0:b079fa4ed182	2392
richardv	0:b079fa4ed182	2393	#define HRTIM_FLTINR1_FLT4E ((uint32_t)0x01000000) /!< Fault 4 enable /
richardv	0:b079fa4ed182	2394	#define HRTIM_FLTINR1_FLT4P ((uint32_t)0x02000000) /!< Fault 4 polarity /
richardv	0:b079fa4ed182	2395	#define HRTIM_FLTINR1_FLT4SRC ((uint32_t)0x04000000) /!< Fault 4 source /
richardv	0:b079fa4ed182	2396	#define HRTIM_FLTINR1_FLT4F ((uint32_t)0x78000000) /!< Fault 4 filter /
richardv	0:b079fa4ed182	2397	#define HRTIM_FLTINR1_FLT4F_0 ((uint32_t)0x08000000) /!< Fault 4 filter bit 0 /
richardv	0:b079fa4ed182	2398	#define HRTIM_FLTINR1_FLT4F_1 ((uint32_t)0x10000000) /!< Fault 4 filter bit 1 /
richardv	0:b079fa4ed182	2399	#define HRTIM_FLTINR1_FLT4F_2 ((uint32_t)0x20000000) /!< Fault 4 filter bit 2 /
richardv	0:b079fa4ed182	2400	#define HRTIM_FLTINR1_FLT4F_3 ((uint32_t)0x40000000) /!< Fault 4 filter bit 3 /
richardv	0:b079fa4ed182	2401	#define HRTIM_FLTINR1_FLT4LCK ((uint32_t)0x80000000) /!< Fault 4 lock /
richardv	0:b079fa4ed182	2402
richardv	0:b079fa4ed182	2403	/***************** Bit definition for HRTIM_FLTINR2 register *************/
richardv	0:b079fa4ed182	2404	#define HRTIM_FLTINR2_FLT5E ((uint32_t)0x00000001) /!< Fault 5 enable /
richardv	0:b079fa4ed182	2405	#define HRTIM_FLTINR2_FLT5P ((uint32_t)0x00000002) /!< Fault 5 polarity /
richardv	0:b079fa4ed182	2406	#define HRTIM_FLTINR2_FLT5SRC ((uint32_t)0x00000004) /!< Fault 5 source /
richardv	0:b079fa4ed182	2407	#define HRTIM_FLTINR2_FLT5F ((uint32_t)0x00000078) /!< Fault 5 filter /
richardv	0:b079fa4ed182	2408	#define HRTIM_FLTINR2_FLT5F_0 ((uint32_t)0x00000008) /!< Fault 5 filter bit 0 /
richardv	0:b079fa4ed182	2409	#define HRTIM_FLTINR2_FLT5F_1 ((uint32_t)0x00000010) /!< Fault 5 filter bit 1 /
richardv	0:b079fa4ed182	2410	#define HRTIM_FLTINR2_FLT5F_2 ((uint32_t)0x00000020) /!< Fault 5 filter bit 2 /
richardv	0:b079fa4ed182	2411	#define HRTIM_FLTINR2_FLT5F_3 ((uint32_t)0x00000040) /!< Fault 5 filter bit 3 /
richardv	0:b079fa4ed182	2412	#define HRTIM_FLTINR2_FLT5LCK ((uint32_t)0x00000080) /!< Fault 5 lock /
richardv	0:b079fa4ed182	2413	#define HRTIM_FLTINR2_FLTSD ((uint32_t)0x03000000) /!< Fault sampling clock division /
richardv	0:b079fa4ed182	2414	#define HRTIM_FLTINR2_FLTSD_0 ((uint32_t)0x01000000) /!< Fault sampling clock division bit 0 /
richardv	0:b079fa4ed182	2415	#define HRTIM_FLTINR2_FLTSD_1 ((uint32_t)0x02000000) /!< Fault sampling clock division bit 1 /
richardv	0:b079fa4ed182	2416
richardv	0:b079fa4ed182	2417	/***************** Bit definition for HRTIM_BDMUPR register *************/
richardv	0:b079fa4ed182	2418	#define HRTIM_BDMUPR_MCR ((uint32_t)0x00000001) /!< MCR register update enable /
richardv	0:b079fa4ed182	2419	#define HRTIM_BDMUPR_MICR ((uint32_t)0x00000002) /!< MICR register update enable /
richardv	0:b079fa4ed182	2420	#define HRTIM_BDMUPR_MDIER ((uint32_t)0x00000004) /!< MDIER register update enable /
richardv	0:b079fa4ed182	2421	#define HRTIM_BDMUPR_MCNT ((uint32_t)0x00000008) /!< MCNT register update enable /
richardv	0:b079fa4ed182	2422	#define HRTIM_BDMUPR_MPER ((uint32_t)0x00000010) /!< MPER register update enable /
richardv	0:b079fa4ed182	2423	#define HRTIM_BDMUPR_MREP ((uint32_t)0x00000020) /!< MREP register update enable /
richardv	0:b079fa4ed182	2424	#define HRTIM_BDMUPR_MCMP1 ((uint32_t)0x00000040) /!< MCMP1 register update enable /
richardv	0:b079fa4ed182	2425	#define HRTIM_BDMUPR_MCMP2 ((uint32_t)0x00000080) /!< MCMP2 register update enable /
richardv	0:b079fa4ed182	2426	#define HRTIM_BDMUPR_MCMP3 ((uint32_t)0x00000100) /!< MCMP3 register update enable /
richardv	0:b079fa4ed182	2427	#define HRTIM_BDMUPR_MCMP4 ((uint32_t)0x00000200) /!< MPCMP4 register update enable /
richardv	0:b079fa4ed182	2428
richardv	0:b079fa4ed182	2429	/***************** Bit definition for HRTIM_BDTUPR register *************/
richardv	0:b079fa4ed182	2430	#define HRTIM_BDTUPR_TIMCR ((uint32_t)0x00000001) /!< TIMCR register update enable /
richardv	0:b079fa4ed182	2431	#define HRTIM_BDTUPR_TIMICR ((uint32_t)0x00000002) /!< TIMICR register update enable /
richardv	0:b079fa4ed182	2432	#define HRTIM_BDTUPR_TIMDIER ((uint32_t)0x00000004) /!< TIMDIER register update enable /
richardv	0:b079fa4ed182	2433	#define HRTIM_BDTUPR_TIMCNT ((uint32_t)0x00000008) /!< TIMCNT register update enable /
richardv	0:b079fa4ed182	2434	#define HRTIM_BDTUPR_TIMPER ((uint32_t)0x00000010) /!< TIMPER register update enable /
richardv	0:b079fa4ed182	2435	#define HRTIM_BDTUPR_TIMREP ((uint32_t)0x00000020) /!< TIMREP register update enable /
richardv	0:b079fa4ed182	2436	#define HRTIM_BDTUPR_TIMCMP1 ((uint32_t)0x00000040) /!< TIMCMP1 register update enable /
richardv	0:b079fa4ed182	2437	#define HRTIM_BDTUPR_TIMCMP2 ((uint32_t)0x00000080) /!< TIMCMP2 register update enable /
richardv	0:b079fa4ed182	2438	#define HRTIM_BDTUPR_TIMCMP3 ((uint32_t)0x00000100) /!< TIMCMP3 register update enable /
richardv	0:b079fa4ed182	2439	#define HRTIM_BDTUPR_TIMCMP4 ((uint32_t)0x00000200) /!< TIMCMP4 register update enable /
richardv	0:b079fa4ed182	2440	#define HRTIM_BDTUPR_TIMDTR ((uint32_t)0x00000400) /!< TIMDTR register update enable /
richardv	0:b079fa4ed182	2441	#define HRTIM_BDTUPR_TIMSET1R ((uint32_t)0x00000800) /!< TIMSET1R register update enable /
richardv	0:b079fa4ed182	2442	#define HRTIM_BDTUPR_TIMRST1R ((uint32_t)0x00001000) /!< TIMRST1R register update enable /
richardv	0:b079fa4ed182	2443	#define HRTIM_BDTUPR_TIMSET2R ((uint32_t)0x00002000) /!< TIMSET2R register update enable /
richardv	0:b079fa4ed182	2444	#define HRTIM_BDTUPR_TIMRST2R ((uint32_t)0x00004000) /!< TIMRST2R register update enable /
richardv	0:b079fa4ed182	2445	#define HRTIM_BDTUPR_TIMEEFR1 ((uint32_t)0x00008000) /!< TIMEEFR1 register update enable /
richardv	0:b079fa4ed182	2446	#define HRTIM_BDTUPR_TIMEEFR2 ((uint32_t)0x00010000) /!< TIMEEFR2 register update enable /
richardv	0:b079fa4ed182	2447	#define HRTIM_BDTUPR_TIMRSTR ((uint32_t)0x00020000) /!< TIMRSTR register update enable /
richardv	0:b079fa4ed182	2448	#define HRTIM_BDTUPR_TIMCHPR ((uint32_t)0x00040000) /!< TIMCHPR register update enable /
richardv	0:b079fa4ed182	2449	#define HRTIM_BDTUPR_TIMOUTR ((uint32_t)0x00080000) /!< TIMOUTR register update enable /
richardv	0:b079fa4ed182	2450	#define HRTIM_BDTUPR_TIMFLTR ((uint32_t)0x00100000) /!< TIMFLTR register update enable /
richardv	0:b079fa4ed182	2451
richardv	0:b079fa4ed182	2452	/***************** Bit definition for HRTIM_BDMADR register *************/
richardv	0:b079fa4ed182	2453	#define HRTIM_BDMADR_BDMADR ((uint32_t)0xFFFFFFFF) /!< Burst DMA Data register /
richardv	0:b079fa4ed182	2454
richardv	0:b079fa4ed182	2455	/******************************************************************************/
richardv	0:b079fa4ed182	2456	/* */
richardv	0:b079fa4ed182	2457	/* Analog to Digital Converter SAR (ADC) */
richardv	0:b079fa4ed182	2458	/* */
richardv	0:b079fa4ed182	2459	/******************************************************************************/
richardv	0:b079fa4ed182	2460	/****************** Bit definition for ADC_ISR register ******************/
richardv	0:b079fa4ed182	2461	#define ADC_ISR_ADRD ((uint32_t)0x00000001) /!< ADC Ready (ADRDY) flag /
richardv	0:b079fa4ed182	2462	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< ADC End of Sampling flag /
richardv	0:b079fa4ed182	2463	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< ADC End of Regular Conversion flag /
richardv	0:b079fa4ed182	2464	#define ADC_ISR_EOS ((uint32_t)0x00000008) /!< ADC End of Regular sequence of Conversions flag /
richardv	0:b079fa4ed182	2465	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< ADC overrun flag /
richardv	0:b079fa4ed182	2466	#define ADC_ISR_JEOC ((uint32_t)0x00000020) /!< ADC End of Injected Conversion flag /
richardv	0:b079fa4ed182	2467	#define ADC_ISR_JEOS ((uint32_t)0x00000040) /!< ADC End of Injected sequence of Conversions flag /
richardv	0:b079fa4ed182	2468	#define ADC_ISR_AWD1 ((uint32_t)0x00000080) /!< ADC Analog watchdog 1 flag /
richardv	0:b079fa4ed182	2469	#define ADC_ISR_AWD2 ((uint32_t)0x00000100) /!< ADC Analog watchdog 2 flag /
richardv	0:b079fa4ed182	2470	#define ADC_ISR_AWD3 ((uint32_t)0x00000200) /!< ADC Analog watchdog 3 flag /
richardv	0:b079fa4ed182	2471	#define ADC_ISR_JQOVF ((uint32_t)0x00000400) /!< ADC Injected Context Queue Overflow flag /
richardv	0:b079fa4ed182	2472
richardv	0:b079fa4ed182	2473	/****************** Bit definition for ADC_IER register ******************/
richardv	0:b079fa4ed182	2474	#define ADC_IER_RDY ((uint32_t)0x00000001) /!< ADC Ready (ADRDY) interrupt source /
richardv	0:b079fa4ed182	2475	#define ADC_IER_EOSMP ((uint32_t)0x00000002) /!< ADC End of Sampling interrupt source /
richardv	0:b079fa4ed182	2476	#define ADC_IER_EOC ((uint32_t)0x00000004) /!< ADC End of Regular Conversion interrupt source /
richardv	0:b079fa4ed182	2477	#define ADC_IER_EOS ((uint32_t)0x00000008) /!< ADC End of Regular sequence of Conversions interrupt source /
richardv	0:b079fa4ed182	2478	#define ADC_IER_OVR ((uint32_t)0x00000010) /!< ADC overrun interrupt source /
richardv	0:b079fa4ed182	2479	#define ADC_IER_JEOC ((uint32_t)0x00000020) /!< ADC End of Injected Conversion interrupt source /
richardv	0:b079fa4ed182	2480	#define ADC_IER_JEOS ((uint32_t)0x00000040) /!< ADC End of Injected sequence of Conversions interrupt source /
richardv	0:b079fa4ed182	2481	#define ADC_IER_AWD1 ((uint32_t)0x00000080) /!< ADC Analog watchdog 1 interrupt source /
richardv	0:b079fa4ed182	2482	#define ADC_IER_AWD2 ((uint32_t)0x00000100) /!< ADC Analog watchdog 2 interrupt source /
richardv	0:b079fa4ed182	2483	#define ADC_IER_AWD3 ((uint32_t)0x00000200) /!< ADC Analog watchdog 3 interrupt source /
richardv	0:b079fa4ed182	2484	#define ADC_IER_JQOVF ((uint32_t)0x00000400) /!< ADC Injected Context Queue Overflow interrupt source /
richardv	0:b079fa4ed182	2485
richardv	0:b079fa4ed182	2486	/****************** Bit definition for ADC_CR register ******************/
richardv	0:b079fa4ed182	2487	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC Enable control /
richardv	0:b079fa4ed182	2488	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC Disable command /
richardv	0:b079fa4ed182	2489	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC Start of Regular conversion /
richardv	0:b079fa4ed182	2490	#define ADC_CR_JADSTART ((uint32_t)0x00000008) /!< ADC Start of injected conversion /
richardv	0:b079fa4ed182	2491	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC Stop of Regular conversion /
richardv	0:b079fa4ed182	2492	#define ADC_CR_JADSTP ((uint32_t)0x00000020) /!< ADC Stop of injected conversion /
richardv	0:b079fa4ed182	2493	#define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /!< ADC Voltage regulator Enable /
richardv	0:b079fa4ed182	2494	#define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /!< ADC ADVREGEN bit 0 /
richardv	0:b079fa4ed182	2495	#define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /!< ADC ADVREGEN bit 1 /
richardv	0:b079fa4ed182	2496	#define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /!< ADC Differential Mode for calibration /
richardv	0:b079fa4ed182	2497	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC Calibration /
richardv	0:b079fa4ed182	2498
richardv	0:b079fa4ed182	2499	/****************** Bit definition for ADC_CFGR register ******************/
richardv	0:b079fa4ed182	2500	#define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /!< ADC DMA Enable /
richardv	0:b079fa4ed182	2501	#define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /!< ADC DMA configuration /
richardv	0:b079fa4ed182	2502
richardv	0:b079fa4ed182	2503	#define ADC_CFGR_RES ((uint32_t)0x00000018) /!< ADC Data resolution /
richardv	0:b079fa4ed182	2504	#define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /!< ADC RES bit 0 /
richardv	0:b079fa4ed182	2505	#define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /!< ADC RES bit 1 /
richardv	0:b079fa4ed182	2506
richardv	0:b079fa4ed182	2507	#define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /!< ADC Data Alignment /
richardv	0:b079fa4ed182	2508
richardv	0:b079fa4ed182	2509	#define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /!< ADC External trigger selection for regular group /
richardv	0:b079fa4ed182	2510	#define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /!< ADC EXTSEL bit 0 /
richardv	0:b079fa4ed182	2511	#define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /!< ADC EXTSEL bit 1 /
richardv	0:b079fa4ed182	2512	#define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /!< ADC EXTSEL bit 2 /
richardv	0:b079fa4ed182	2513	#define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /!< ADC EXTSEL bit 3 /
richardv	0:b079fa4ed182	2514
richardv	0:b079fa4ed182	2515	#define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /!< ADC External trigger enable and polarity selection for regular channels /
richardv	0:b079fa4ed182	2516	#define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /!< ADC EXTEN bit 0 /
richardv	0:b079fa4ed182	2517	#define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /!< ADC EXTEN bit 1 /
richardv	0:b079fa4ed182	2518
richardv	0:b079fa4ed182	2519	#define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /!< ADC overrun mode /
richardv	0:b079fa4ed182	2520	#define ADC_CFGR_CONT ((uint32_t)0x00002000) /!< ADC Single/continuous conversion mode for regular conversion /
richardv	0:b079fa4ed182	2521	#define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /!< ADC Delayed conversion mode /
richardv	0:b079fa4ed182	2522	#define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /!< ADC Discontinuous mode for regular channels /
richardv	0:b079fa4ed182	2523
richardv	0:b079fa4ed182	2524	#define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /!< ADC Discontinuous mode channel count /
richardv	0:b079fa4ed182	2525	#define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /!< ADC DISCNUM bit 0 /
richardv	0:b079fa4ed182	2526	#define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /!< ADC DISCNUM bit 1 /
richardv	0:b079fa4ed182	2527	#define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /!< ADC DISCNUM bit 2 /
richardv	0:b079fa4ed182	2528
richardv	0:b079fa4ed182	2529	#define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /!< ADC Discontinuous mode on injected channels /
richardv	0:b079fa4ed182	2530	#define ADC_CFGR_JQM ((uint32_t)0x00200000) /!< ADC JSQR Queue mode /
richardv	0:b079fa4ed182	2531	#define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /!< Enable the watchdog 1 on a single channel or on all channels /
richardv	0:b079fa4ed182	2532	#define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /!< ADC Analog watchdog 1 enable on regular Channels /
richardv	0:b079fa4ed182	2533	#define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /!< ADC Analog watchdog 1 enable on injected Channels /
richardv	0:b079fa4ed182	2534	#define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /!< ADC Automatic injected group conversion /
richardv	0:b079fa4ed182	2535
richardv	0:b079fa4ed182	2536	#define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /!< ADC Analog watchdog 1 Channel selection /
richardv	0:b079fa4ed182	2537	#define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /!< ADC AWD1CH bit 0 /
richardv	0:b079fa4ed182	2538	#define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /!< ADC AWD1CH bit 1 /
richardv	0:b079fa4ed182	2539	#define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /!< ADC AWD1CH bit 2 /
richardv	0:b079fa4ed182	2540	#define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /!< ADC AWD1CH bit 3 /
richardv	0:b079fa4ed182	2541	#define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /!< ADC AWD1CH bit 4 /
richardv	0:b079fa4ed182	2542
richardv	0:b079fa4ed182	2543	/****************** Bit definition for ADC_SMPR1 register ******************/
richardv	0:b079fa4ed182	2544	#define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /!< ADC Channel 0 Sampling time selection /
richardv	0:b079fa4ed182	2545	#define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /!< ADC SMP0 bit 0 /
richardv	0:b079fa4ed182	2546	#define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /!< ADC SMP0 bit 1 /
richardv	0:b079fa4ed182	2547	#define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /!< ADC SMP0 bit 2 /
richardv	0:b079fa4ed182	2548
richardv	0:b079fa4ed182	2549	#define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /!< ADC Channel 1 Sampling time selection /
richardv	0:b079fa4ed182	2550	#define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /!< ADC SMP1 bit 0 /
richardv	0:b079fa4ed182	2551	#define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /!< ADC SMP1 bit 1 /
richardv	0:b079fa4ed182	2552	#define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /!< ADC SMP1 bit 2 /
richardv	0:b079fa4ed182	2553
richardv	0:b079fa4ed182	2554	#define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /!< ADC Channel 2 Sampling time selection /
richardv	0:b079fa4ed182	2555	#define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /!< ADC SMP2 bit 0 /
richardv	0:b079fa4ed182	2556	#define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /!< ADC SMP2 bit 1 /
richardv	0:b079fa4ed182	2557	#define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /!< ADC SMP2 bit 2 /
richardv	0:b079fa4ed182	2558
richardv	0:b079fa4ed182	2559	#define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /!< ADC Channel 3 Sampling time selection /
richardv	0:b079fa4ed182	2560	#define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /!< ADC SMP3 bit 0 /
richardv	0:b079fa4ed182	2561	#define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /!< ADC SMP3 bit 1 /
richardv	0:b079fa4ed182	2562	#define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /!< ADC SMP3 bit 2 /
richardv	0:b079fa4ed182	2563
richardv	0:b079fa4ed182	2564	#define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /!< ADC Channel 4 Sampling time selection /
richardv	0:b079fa4ed182	2565	#define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /!< ADC SMP4 bit 0 /
richardv	0:b079fa4ed182	2566	#define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /!< ADC SMP4 bit 1 /
richardv	0:b079fa4ed182	2567	#define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /!< ADC SMP4 bit 2 /
richardv	0:b079fa4ed182	2568
richardv	0:b079fa4ed182	2569	#define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /!< ADC Channel 5 Sampling time selection /
richardv	0:b079fa4ed182	2570	#define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /!< ADC SMP5 bit 0 /
richardv	0:b079fa4ed182	2571	#define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /!< ADC SMP5 bit 1 /
richardv	0:b079fa4ed182	2572	#define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /!< ADC SMP5 bit 2 /
richardv	0:b079fa4ed182	2573
richardv	0:b079fa4ed182	2574	#define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /!< ADC Channel 6 Sampling time selection /
richardv	0:b079fa4ed182	2575	#define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /!< ADC SMP6 bit 0 /
richardv	0:b079fa4ed182	2576	#define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /!< ADC SMP6 bit 1 /
richardv	0:b079fa4ed182	2577	#define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /!< ADC SMP6 bit 2 /
richardv	0:b079fa4ed182	2578
richardv	0:b079fa4ed182	2579	#define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /!< ADC Channel 7 Sampling time selection /
richardv	0:b079fa4ed182	2580	#define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /!< ADC SMP7 bit 0 /
richardv	0:b079fa4ed182	2581	#define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /!< ADC SMP7 bit 1 /
richardv	0:b079fa4ed182	2582	#define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /!< ADC SMP7 bit 2 /
richardv	0:b079fa4ed182	2583
richardv	0:b079fa4ed182	2584	#define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /!< ADC Channel 8 Sampling time selection /
richardv	0:b079fa4ed182	2585	#define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /!< ADC SMP8 bit 0 /
richardv	0:b079fa4ed182	2586	#define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /!< ADC SMP8 bit 1 /
richardv	0:b079fa4ed182	2587	#define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /!< ADC SMP8 bit 2 /
richardv	0:b079fa4ed182	2588
richardv	0:b079fa4ed182	2589	#define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /!< ADC Channel 9 Sampling time selection /
richardv	0:b079fa4ed182	2590	#define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /!< ADC SMP9 bit 0 /
richardv	0:b079fa4ed182	2591	#define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /!< ADC SMP9 bit 1 /
richardv	0:b079fa4ed182	2592	#define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /!< ADC SMP9 bit 2 /
richardv	0:b079fa4ed182	2593
richardv	0:b079fa4ed182	2594	/****************** Bit definition for ADC_SMPR2 register ******************/
richardv	0:b079fa4ed182	2595	#define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /!< ADC Channel 10 Sampling time selection /
richardv	0:b079fa4ed182	2596	#define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /!< ADC SMP10 bit 0 /
richardv	0:b079fa4ed182	2597	#define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /!< ADC SMP10 bit 1 /
richardv	0:b079fa4ed182	2598	#define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /!< ADC SMP10 bit 2 /
richardv	0:b079fa4ed182	2599
richardv	0:b079fa4ed182	2600	#define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /!< ADC Channel 11 Sampling time selection /
richardv	0:b079fa4ed182	2601	#define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /!< ADC SMP11 bit 0 /
richardv	0:b079fa4ed182	2602	#define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /!< ADC SMP11 bit 1 /
richardv	0:b079fa4ed182	2603	#define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /!< ADC SMP11 bit 2 /
richardv	0:b079fa4ed182	2604
richardv	0:b079fa4ed182	2605	#define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /!< ADC Channel 12 Sampling time selection /
richardv	0:b079fa4ed182	2606	#define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /!< ADC SMP12 bit 0 /
richardv	0:b079fa4ed182	2607	#define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /!< ADC SMP12 bit 1 /
richardv	0:b079fa4ed182	2608	#define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /!< ADC SMP12 bit 2 /
richardv	0:b079fa4ed182	2609
richardv	0:b079fa4ed182	2610	#define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /!< ADC Channel 13 Sampling time selection /
richardv	0:b079fa4ed182	2611	#define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /!< ADC SMP13 bit 0 /
richardv	0:b079fa4ed182	2612	#define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /!< ADC SMP13 bit 1 /
richardv	0:b079fa4ed182	2613	#define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /!< ADC SMP13 bit 2 /
richardv	0:b079fa4ed182	2614
richardv	0:b079fa4ed182	2615	#define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /!< ADC Channel 14 Sampling time selection /
richardv	0:b079fa4ed182	2616	#define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /!< ADC SMP14 bit 0 /
richardv	0:b079fa4ed182	2617	#define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /!< ADC SMP14 bit 1 /
richardv	0:b079fa4ed182	2618	#define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /!< ADC SMP14 bit 2 /
richardv	0:b079fa4ed182	2619
richardv	0:b079fa4ed182	2620	#define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /!< ADC Channel 15 Sampling time selection /
richardv	0:b079fa4ed182	2621	#define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /!< ADC SMP15 bit 0 /
richardv	0:b079fa4ed182	2622	#define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /!< ADC SMP15 bit 1 /
richardv	0:b079fa4ed182	2623	#define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /!< ADC SMP15 bit 2 /
richardv	0:b079fa4ed182	2624
richardv	0:b079fa4ed182	2625	#define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /!< ADC Channel 16 Sampling time selection /
richardv	0:b079fa4ed182	2626	#define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /!< ADC SMP16 bit 0 /
richardv	0:b079fa4ed182	2627	#define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /!< ADC SMP16 bit 1 /
richardv	0:b079fa4ed182	2628	#define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /!< ADC SMP16 bit 2 /
richardv	0:b079fa4ed182	2629
richardv	0:b079fa4ed182	2630	#define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /!< ADC Channel 17 Sampling time selection /
richardv	0:b079fa4ed182	2631	#define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /!< ADC SMP17 bit 0 /
richardv	0:b079fa4ed182	2632	#define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /!< ADC SMP17 bit 1 /
richardv	0:b079fa4ed182	2633	#define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /!< ADC SMP17 bit 2 /
richardv	0:b079fa4ed182	2634
richardv	0:b079fa4ed182	2635	#define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /!< ADC Channel 18 Sampling time selection /
richardv	0:b079fa4ed182	2636	#define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /!< ADC SMP18 bit 0 /
richardv	0:b079fa4ed182	2637	#define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /!< ADC SMP18 bit 1 /
richardv	0:b079fa4ed182	2638	#define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /!< ADC SMP18 bit 2 /
richardv	0:b079fa4ed182	2639
richardv	0:b079fa4ed182	2640	/****************** Bit definition for ADC_TR1 register ******************/
richardv	0:b079fa4ed182	2641	#define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /!< ADC Analog watchdog 1 lower threshold /
richardv	0:b079fa4ed182	2642	#define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /!< ADC LT1 bit 0 /
richardv	0:b079fa4ed182	2643	#define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /!< ADC LT1 bit 1 /
richardv	0:b079fa4ed182	2644	#define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /!< ADC LT1 bit 2 /
richardv	0:b079fa4ed182	2645	#define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /!< ADC LT1 bit 3 /
richardv	0:b079fa4ed182	2646	#define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /!< ADC LT1 bit 4 /
richardv	0:b079fa4ed182	2647	#define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /!< ADC LT1 bit 5 /
richardv	0:b079fa4ed182	2648	#define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /!< ADC LT1 bit 6 /
richardv	0:b079fa4ed182	2649	#define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /!< ADC LT1 bit 7 /
richardv	0:b079fa4ed182	2650	#define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /!< ADC LT1 bit 8 /
richardv	0:b079fa4ed182	2651	#define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /!< ADC LT1 bit 9 /
richardv	0:b079fa4ed182	2652	#define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /!< ADC LT1 bit 10 /
richardv	0:b079fa4ed182	2653	#define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /!< ADC LT1 bit 11 /
richardv	0:b079fa4ed182	2654
richardv	0:b079fa4ed182	2655	#define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /!< ADC Analog watchdog 1 higher threshold /
richardv	0:b079fa4ed182	2656	#define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /!< ADC HT1 bit 0 /
richardv	0:b079fa4ed182	2657	#define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /!< ADC HT1 bit 1 /
richardv	0:b079fa4ed182	2658	#define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /!< ADC HT1 bit 2 /
richardv	0:b079fa4ed182	2659	#define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /!< ADC HT1 bit 3 /
richardv	0:b079fa4ed182	2660	#define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /!< ADC HT1 bit 4 /
richardv	0:b079fa4ed182	2661	#define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /!< ADC HT1 bit 5 /
richardv	0:b079fa4ed182	2662	#define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /!< ADC HT1 bit 6 /
richardv	0:b079fa4ed182	2663	#define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /!< ADC HT1 bit 7 /
richardv	0:b079fa4ed182	2664	#define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /!< ADC HT1 bit 8 /
richardv	0:b079fa4ed182	2665	#define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /!< ADC HT1 bit 9 /
richardv	0:b079fa4ed182	2666	#define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /!< ADC HT1 bit 10 /
richardv	0:b079fa4ed182	2667	#define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /!< ADC HT1 bit 11 /
richardv	0:b079fa4ed182	2668
richardv	0:b079fa4ed182	2669	/****************** Bit definition for ADC_TR2 register ******************/
richardv	0:b079fa4ed182	2670	#define ADC_TR2_LT2 ((uint32_t)0x000000FF) /!< ADC Analog watchdog 2 lower threshold /
richardv	0:b079fa4ed182	2671	#define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /!< ADC LT2 bit 0 /
richardv	0:b079fa4ed182	2672	#define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /!< ADC LT2 bit 1 /
richardv	0:b079fa4ed182	2673	#define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /!< ADC LT2 bit 2 /
richardv	0:b079fa4ed182	2674	#define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /!< ADC LT2 bit 3 /
richardv	0:b079fa4ed182	2675	#define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /!< ADC LT2 bit 4 /
richardv	0:b079fa4ed182	2676	#define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /!< ADC LT2 bit 5 /
richardv	0:b079fa4ed182	2677	#define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /!< ADC LT2 bit 6 /
richardv	0:b079fa4ed182	2678	#define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /!< ADC LT2 bit 7 /
richardv	0:b079fa4ed182	2679
richardv	0:b079fa4ed182	2680	#define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /!< ADC Analog watchdog 2 higher threshold /
richardv	0:b079fa4ed182	2681	#define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /!< ADC HT2 bit 0 /
richardv	0:b079fa4ed182	2682	#define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /!< ADC HT2 bit 1 /
richardv	0:b079fa4ed182	2683	#define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /!< ADC HT2 bit 2 /
richardv	0:b079fa4ed182	2684	#define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /!< ADC HT2 bit 3 /
richardv	0:b079fa4ed182	2685	#define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /!< ADC HT2 bit 4 /
richardv	0:b079fa4ed182	2686	#define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /!< ADC HT2 bit 5 /
richardv	0:b079fa4ed182	2687	#define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /!< ADC HT2 bit 6 /
richardv	0:b079fa4ed182	2688	#define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /!< ADC HT2 bit 7 /
richardv	0:b079fa4ed182	2689
richardv	0:b079fa4ed182	2690	/****************** Bit definition for ADC_TR3 register ******************/
richardv	0:b079fa4ed182	2691	#define ADC_TR3_LT3 ((uint32_t)0x000000FF) /!< ADC Analog watchdog 3 lower threshold /
richardv	0:b079fa4ed182	2692	#define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /!< ADC LT3 bit 0 /
richardv	0:b079fa4ed182	2693	#define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /!< ADC LT3 bit 1 /
richardv	0:b079fa4ed182	2694	#define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /!< ADC LT3 bit 2 /
richardv	0:b079fa4ed182	2695	#define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /!< ADC LT3 bit 3 /
richardv	0:b079fa4ed182	2696	#define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /!< ADC LT3 bit 4 /
richardv	0:b079fa4ed182	2697	#define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /!< ADC LT3 bit 5 /
richardv	0:b079fa4ed182	2698	#define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /!< ADC LT3 bit 6 /
richardv	0:b079fa4ed182	2699	#define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /!< ADC LT3 bit 7 /
richardv	0:b079fa4ed182	2700
richardv	0:b079fa4ed182	2701	#define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /!< ADC Analog watchdog 3 higher threshold /
richardv	0:b079fa4ed182	2702	#define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /!< ADC HT3 bit 0 /
richardv	0:b079fa4ed182	2703	#define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /!< ADC HT3 bit 1 /
richardv	0:b079fa4ed182	2704	#define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /!< ADC HT3 bit 2 /
richardv	0:b079fa4ed182	2705	#define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /!< ADC HT3 bit 3 /
richardv	0:b079fa4ed182	2706	#define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /!< ADC HT3 bit 4 /
richardv	0:b079fa4ed182	2707	#define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /!< ADC HT3 bit 5 /
richardv	0:b079fa4ed182	2708	#define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /!< ADC HT3 bit 6 /
richardv	0:b079fa4ed182	2709	#define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /!< ADC HT3 bit 7 /
richardv	0:b079fa4ed182	2710
richardv	0:b079fa4ed182	2711	/****************** Bit definition for ADC_SQR1 register ******************/
richardv	0:b079fa4ed182	2712	#define ADC_SQR1_L ((uint32_t)0x0000000F) /!< ADC regular channel sequence length /
richardv	0:b079fa4ed182	2713	#define ADC_SQR1_L_0 ((uint32_t)0x00000001) /!< ADC L bit 0 /
richardv	0:b079fa4ed182	2714	#define ADC_SQR1_L_1 ((uint32_t)0x00000002) /!< ADC L bit 1 /
richardv	0:b079fa4ed182	2715	#define ADC_SQR1_L_2 ((uint32_t)0x00000004) /!< ADC L bit 2 /
richardv	0:b079fa4ed182	2716	#define ADC_SQR1_L_3 ((uint32_t)0x00000008) /!< ADC L bit 3 /
richardv	0:b079fa4ed182	2717
richardv	0:b079fa4ed182	2718	#define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /!< ADC 1st conversion in regular sequence /
richardv	0:b079fa4ed182	2719	#define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /!< ADC SQ1 bit 0 /
richardv	0:b079fa4ed182	2720	#define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /!< ADC SQ1 bit 1 /
richardv	0:b079fa4ed182	2721	#define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /!< ADC SQ1 bit 2 /
richardv	0:b079fa4ed182	2722	#define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /!< ADC SQ1 bit 3 /
richardv	0:b079fa4ed182	2723	#define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /!< ADC SQ1 bit 4 /
richardv	0:b079fa4ed182	2724
richardv	0:b079fa4ed182	2725	#define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /!< ADC 2nd conversion in regular sequence /
richardv	0:b079fa4ed182	2726	#define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /!< ADC SQ2 bit 0 /
richardv	0:b079fa4ed182	2727	#define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /!< ADC SQ2 bit 1 /
richardv	0:b079fa4ed182	2728	#define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /!< ADC SQ2 bit 2 /
richardv	0:b079fa4ed182	2729	#define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /!< ADC SQ2 bit 3 /
richardv	0:b079fa4ed182	2730	#define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /!< ADC SQ2 bit 4 /
richardv	0:b079fa4ed182	2731
richardv	0:b079fa4ed182	2732	#define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /!< ADC 3rd conversion in regular sequence /
richardv	0:b079fa4ed182	2733	#define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /!< ADC SQ3 bit 0 /
richardv	0:b079fa4ed182	2734	#define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /!< ADC SQ3 bit 1 /
richardv	0:b079fa4ed182	2735	#define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /!< ADC SQ3 bit 2 /
richardv	0:b079fa4ed182	2736	#define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /!< ADC SQ3 bit 3 /
richardv	0:b079fa4ed182	2737	#define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /!< ADC SQ3 bit 4 /
richardv	0:b079fa4ed182	2738
richardv	0:b079fa4ed182	2739	#define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /!< ADC 4th conversion in regular sequence /
richardv	0:b079fa4ed182	2740	#define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /!< ADC SQ4 bit 0 /
richardv	0:b079fa4ed182	2741	#define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /!< ADC SQ4 bit 1 /
richardv	0:b079fa4ed182	2742	#define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /!< ADC SQ4 bit 2 /
richardv	0:b079fa4ed182	2743	#define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /!< ADC SQ4 bit 3 /
richardv	0:b079fa4ed182	2744	#define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /!< ADC SQ4 bit 4 /
richardv	0:b079fa4ed182	2745
richardv	0:b079fa4ed182	2746	/****************** Bit definition for ADC_SQR2 register ******************/
richardv	0:b079fa4ed182	2747	#define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /!< ADC 5th conversion in regular sequence /
richardv	0:b079fa4ed182	2748	#define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /!< ADC SQ5 bit 0 /
richardv	0:b079fa4ed182	2749	#define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /!< ADC SQ5 bit 1 /
richardv	0:b079fa4ed182	2750	#define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /!< ADC SQ5 bit 2 /
richardv	0:b079fa4ed182	2751	#define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /!< ADC SQ5 bit 3 /
richardv	0:b079fa4ed182	2752	#define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /!< ADC SQ5 bit 4 /
richardv	0:b079fa4ed182	2753
richardv	0:b079fa4ed182	2754	#define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /!< ADC 6th conversion in regular sequence /
richardv	0:b079fa4ed182	2755	#define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /!< ADC SQ6 bit 0 /
richardv	0:b079fa4ed182	2756	#define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /!< ADC SQ6 bit 1 /
richardv	0:b079fa4ed182	2757	#define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /!< ADC SQ6 bit 2 /
richardv	0:b079fa4ed182	2758	#define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /!< ADC SQ6 bit 3 /
richardv	0:b079fa4ed182	2759	#define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /!< ADC SQ6 bit 4 /
richardv	0:b079fa4ed182	2760
richardv	0:b079fa4ed182	2761	#define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /!< ADC 7th conversion in regular sequence /
richardv	0:b079fa4ed182	2762	#define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /!< ADC SQ7 bit 0 /
richardv	0:b079fa4ed182	2763	#define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /!< ADC SQ7 bit 1 /
richardv	0:b079fa4ed182	2764	#define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /!< ADC SQ7 bit 2 /
richardv	0:b079fa4ed182	2765	#define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /!< ADC SQ7 bit 3 /
richardv	0:b079fa4ed182	2766	#define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /!< ADC SQ7 bit 4 /
richardv	0:b079fa4ed182	2767
richardv	0:b079fa4ed182	2768	#define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /!< ADC 8th conversion in regular sequence /
richardv	0:b079fa4ed182	2769	#define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /!< ADC SQ8 bit 0 /
richardv	0:b079fa4ed182	2770	#define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /!< ADC SQ8 bit 1 /
richardv	0:b079fa4ed182	2771	#define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /!< ADC SQ8 bit 2 /
richardv	0:b079fa4ed182	2772	#define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /!< ADC SQ8 bit 3 /
richardv	0:b079fa4ed182	2773	#define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /!< ADC SQ8 bit 4 /
richardv	0:b079fa4ed182	2774
richardv	0:b079fa4ed182	2775	#define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /!< ADC 9th conversion in regular sequence /
richardv	0:b079fa4ed182	2776	#define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /!< ADC SQ9 bit 0 /
richardv	0:b079fa4ed182	2777	#define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /!< ADC SQ9 bit 1 /
richardv	0:b079fa4ed182	2778	#define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /!< ADC SQ9 bit 2 /
richardv	0:b079fa4ed182	2779	#define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /!< ADC SQ9 bit 3 /
richardv	0:b079fa4ed182	2780	#define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /!< ADC SQ9 bit 4 /
richardv	0:b079fa4ed182	2781
richardv	0:b079fa4ed182	2782	/****************** Bit definition for ADC_SQR3 register ******************/
richardv	0:b079fa4ed182	2783	#define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /!< ADC 10th conversion in regular sequence /
richardv	0:b079fa4ed182	2784	#define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /!< ADC SQ10 bit 0 /
richardv	0:b079fa4ed182	2785	#define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /!< ADC SQ10 bit 1 /
richardv	0:b079fa4ed182	2786	#define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /!< ADC SQ10 bit 2 /
richardv	0:b079fa4ed182	2787	#define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /!< ADC SQ10 bit 3 /
richardv	0:b079fa4ed182	2788	#define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /!< ADC SQ10 bit 4 /
richardv	0:b079fa4ed182	2789
richardv	0:b079fa4ed182	2790	#define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /!< ADC 11th conversion in regular sequence /
richardv	0:b079fa4ed182	2791	#define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /!< ADC SQ11 bit 0 /
richardv	0:b079fa4ed182	2792	#define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /!< ADC SQ11 bit 1 /
richardv	0:b079fa4ed182	2793	#define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /!< ADC SQ11 bit 2 /
richardv	0:b079fa4ed182	2794	#define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /!< ADC SQ11 bit 3 /
richardv	0:b079fa4ed182	2795	#define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /!< ADC SQ11 bit 4 /
richardv	0:b079fa4ed182	2796
richardv	0:b079fa4ed182	2797	#define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /!< ADC 12th conversion in regular sequence /
richardv	0:b079fa4ed182	2798	#define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /!< ADC SQ12 bit 0 /
richardv	0:b079fa4ed182	2799	#define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /!< ADC SQ12 bit 1 /
richardv	0:b079fa4ed182	2800	#define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /!< ADC SQ12 bit 2 /
richardv	0:b079fa4ed182	2801	#define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /!< ADC SQ12 bit 3 /
richardv	0:b079fa4ed182	2802	#define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /!< ADC SQ12 bit 4 /
richardv	0:b079fa4ed182	2803
richardv	0:b079fa4ed182	2804	#define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /!< ADC 13th conversion in regular sequence /
richardv	0:b079fa4ed182	2805	#define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /!< ADC SQ13 bit 0 /
richardv	0:b079fa4ed182	2806	#define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /!< ADC SQ13 bit 1 /
richardv	0:b079fa4ed182	2807	#define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /!< ADC SQ13 bit 2 /
richardv	0:b079fa4ed182	2808	#define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /!< ADC SQ13 bit 3 /
richardv	0:b079fa4ed182	2809	#define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /!< ADC SQ13 bit 4 /
richardv	0:b079fa4ed182	2810
richardv	0:b079fa4ed182	2811	#define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /!< ADC 14th conversion in regular sequence /
richardv	0:b079fa4ed182	2812	#define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /!< ADC SQ14 bit 0 /
richardv	0:b079fa4ed182	2813	#define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /!< ADC SQ14 bit 1 /
richardv	0:b079fa4ed182	2814	#define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /!< ADC SQ14 bit 2 /
richardv	0:b079fa4ed182	2815	#define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /!< ADC SQ14 bit 3 /
richardv	0:b079fa4ed182	2816	#define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /!< ADC SQ14 bit 4 /
richardv	0:b079fa4ed182	2817
richardv	0:b079fa4ed182	2818	/****************** Bit definition for ADC_SQR4 register ******************/
richardv	0:b079fa4ed182	2819	#define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /!< ADC 15th conversion in regular sequence /
richardv	0:b079fa4ed182	2820	#define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /!< ADC SQ15 bit 0 /
richardv	0:b079fa4ed182	2821	#define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /!< ADC SQ15 bit 1 /
richardv	0:b079fa4ed182	2822	#define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /!< ADC SQ15 bit 2 /
richardv	0:b079fa4ed182	2823	#define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /!< ADC SQ15 bit 3 /
richardv	0:b079fa4ed182	2824	#define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /!< ADC SQ105 bit 4 /
richardv	0:b079fa4ed182	2825
richardv	0:b079fa4ed182	2826	#define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /!< ADC 16th conversion in regular sequence /
richardv	0:b079fa4ed182	2827	#define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /!< ADC SQ16 bit 0 /
richardv	0:b079fa4ed182	2828	#define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /!< ADC SQ16 bit 1 /
richardv	0:b079fa4ed182	2829	#define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /!< ADC SQ16 bit 2 /
richardv	0:b079fa4ed182	2830	#define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /!< ADC SQ16 bit 3 /
richardv	0:b079fa4ed182	2831	#define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /!< ADC SQ16 bit 4 /
richardv	0:b079fa4ed182	2832
richardv	0:b079fa4ed182	2833	/* these defines are maintained for legacy purpose */
richardv	0:b079fa4ed182	2834	#define ADC_SQR3_SQ15 ADC_SQR4_SQ15 /!< ADC 15th conversion in regular sequence /
richardv	0:b079fa4ed182	2835	#define ADC_SQR3_SQ15_0 ADC_SQR4_SQ15_0 /!< ADC SQ15 bit 0 /
richardv	0:b079fa4ed182	2836	#define ADC_SQR3_SQ15_1 ADC_SQR4_SQ15_1 /!< ADC SQ15 bit 1 /
richardv	0:b079fa4ed182	2837	#define ADC_SQR3_SQ15_2 ADC_SQR4_SQ15_2 /!< ADC SQ15 bit 2 /
richardv	0:b079fa4ed182	2838	#define ADC_SQR3_SQ15_3 ADC_SQR4_SQ15_3 /!< ADC SQ15 bit 3 /
richardv	0:b079fa4ed182	2839	#define ADC_SQR3_SQ15_4 ADC_SQR4_SQ15_4 /!< ADC SQ105 bit 4 /
richardv	0:b079fa4ed182	2840
richardv	0:b079fa4ed182	2841	#define ADC_SQR3_SQ16 ADC_SQR4_SQ16 /!< ADC 16th conversion in regular sequence /
richardv	0:b079fa4ed182	2842	#define ADC_SQR3_SQ16_0 ADC_SQR4_SQ16_0 /!< ADC SQ16 bit 0 /
richardv	0:b079fa4ed182	2843	#define ADC_SQR3_SQ16_1 ADC_SQR4_SQ16_1 /!< ADC SQ16 bit 1 /
richardv	0:b079fa4ed182	2844	#define ADC_SQR3_SQ16_2 ADC_SQR4_SQ16_2 /!< ADC SQ16 bit 2 /
richardv	0:b079fa4ed182	2845	#define ADC_SQR3_SQ16_3 ADC_SQR4_SQ16_3 /!< ADC SQ16 bit 3 /
richardv	0:b079fa4ed182	2846	#define ADC_SQR3_SQ16_4 ADC_SQR4_SQ16_4 /!< ADC SQ16 bit 4 /
richardv	0:b079fa4ed182	2847	/****************** Bit definition for ADC_DR register ******************/
richardv	0:b079fa4ed182	2848	#define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /!< ADC regular Data converted /
richardv	0:b079fa4ed182	2849	#define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /!< ADC RDATA bit 0 /
richardv	0:b079fa4ed182	2850	#define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /!< ADC RDATA bit 1 /
richardv	0:b079fa4ed182	2851	#define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /!< ADC RDATA bit 2 /
richardv	0:b079fa4ed182	2852	#define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /!< ADC RDATA bit 3 /
richardv	0:b079fa4ed182	2853	#define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /!< ADC RDATA bit 4 /
richardv	0:b079fa4ed182	2854	#define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /!< ADC RDATA bit 5 /
richardv	0:b079fa4ed182	2855	#define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /!< ADC RDATA bit 6 /
richardv	0:b079fa4ed182	2856	#define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /!< ADC RDATA bit 7 /
richardv	0:b079fa4ed182	2857	#define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /!< ADC RDATA bit 8 /
richardv	0:b079fa4ed182	2858	#define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /!< ADC RDATA bit 9 /
richardv	0:b079fa4ed182	2859	#define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /!< ADC RDATA bit 10 /
richardv	0:b079fa4ed182	2860	#define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /!< ADC RDATA bit 11 /
richardv	0:b079fa4ed182	2861	#define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /!< ADC RDATA bit 12 /
richardv	0:b079fa4ed182	2862	#define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /!< ADC RDATA bit 13 /
richardv	0:b079fa4ed182	2863	#define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /!< ADC RDATA bit 14 /
richardv	0:b079fa4ed182	2864	#define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /!< ADC RDATA bit 15 /
richardv	0:b079fa4ed182	2865
richardv	0:b079fa4ed182	2866	/****************** Bit definition for ADC_JSQR register ******************/
richardv	0:b079fa4ed182	2867	#define ADC_JSQR_JL ((uint32_t)0x00000003) /!< ADC injected channel sequence length /
richardv	0:b079fa4ed182	2868	#define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /!< ADC JL bit 0 /
richardv	0:b079fa4ed182	2869	#define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /!< ADC JL bit 1 /
richardv	0:b079fa4ed182	2870
richardv	0:b079fa4ed182	2871	#define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /!< ADC external trigger selection for injected group /
richardv	0:b079fa4ed182	2872	#define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /!< ADC JEXTSEL bit 0 /
richardv	0:b079fa4ed182	2873	#define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /!< ADC JEXTSEL bit 1 /
richardv	0:b079fa4ed182	2874	#define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /!< ADC JEXTSEL bit 2 /
richardv	0:b079fa4ed182	2875	#define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /!< ADC JEXTSEL bit 3 /
richardv	0:b079fa4ed182	2876
richardv	0:b079fa4ed182	2877	#define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /!< ADC external trigger enable and polarity selection for injected channels /
richardv	0:b079fa4ed182	2878	#define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /!< ADC JEXTEN bit 0 /
richardv	0:b079fa4ed182	2879	#define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /!< ADC JEXTEN bit 1 /
richardv	0:b079fa4ed182	2880
richardv	0:b079fa4ed182	2881	#define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /!< ADC 1st conversion in injected sequence /
richardv	0:b079fa4ed182	2882	#define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /!< ADC JSQ1 bit 0 /
richardv	0:b079fa4ed182	2883	#define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /!< ADC JSQ1 bit 1 /
richardv	0:b079fa4ed182	2884	#define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /!< ADC JSQ1 bit 2 /
richardv	0:b079fa4ed182	2885	#define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /!< ADC JSQ1 bit 3 /
richardv	0:b079fa4ed182	2886	#define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /!< ADC JSQ1 bit 4 /
richardv	0:b079fa4ed182	2887
richardv	0:b079fa4ed182	2888	#define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /!< ADC 2nd conversion in injected sequence /
richardv	0:b079fa4ed182	2889	#define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /!< ADC JSQ2 bit 0 /
richardv	0:b079fa4ed182	2890	#define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /!< ADC JSQ2 bit 1 /
richardv	0:b079fa4ed182	2891	#define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /!< ADC JSQ2 bit 2 /
richardv	0:b079fa4ed182	2892	#define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /!< ADC JSQ2 bit 3 /
richardv	0:b079fa4ed182	2893	#define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /!< ADC JSQ2 bit 4 /
richardv	0:b079fa4ed182	2894
richardv	0:b079fa4ed182	2895	#define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /!< ADC 3rd conversion in injected sequence /
richardv	0:b079fa4ed182	2896	#define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /!< ADC JSQ3 bit 0 /
richardv	0:b079fa4ed182	2897	#define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /!< ADC JSQ3 bit 1 /
richardv	0:b079fa4ed182	2898	#define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /!< ADC JSQ3 bit 2 /
richardv	0:b079fa4ed182	2899	#define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /!< ADC JSQ3 bit 3 /
richardv	0:b079fa4ed182	2900	#define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /!< ADC JSQ3 bit 4 /
richardv	0:b079fa4ed182	2901
richardv	0:b079fa4ed182	2902	#define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /!< ADC 4th conversion in injected sequence /
richardv	0:b079fa4ed182	2903	#define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /!< ADC JSQ4 bit 0 /
richardv	0:b079fa4ed182	2904	#define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /!< ADC JSQ4 bit 1 /
richardv	0:b079fa4ed182	2905	#define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /!< ADC JSQ4 bit 2 /
richardv	0:b079fa4ed182	2906	#define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /!< ADC JSQ4 bit 3 /
richardv	0:b079fa4ed182	2907	#define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /!< ADC JSQ4 bit 4 /
richardv	0:b079fa4ed182	2908
richardv	0:b079fa4ed182	2909	/****************** Bit definition for ADC_OFR1 register ******************/
richardv	0:b079fa4ed182	2910	#define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] /
richardv	0:b079fa4ed182	2911	#define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /!< ADC OFFSET1 bit 0 /
richardv	0:b079fa4ed182	2912	#define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /!< ADC OFFSET1 bit 1 /
richardv	0:b079fa4ed182	2913	#define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /!< ADC OFFSET1 bit 2 /
richardv	0:b079fa4ed182	2914	#define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /!< ADC OFFSET1 bit 3 /
richardv	0:b079fa4ed182	2915	#define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /!< ADC OFFSET1 bit 4 /
richardv	0:b079fa4ed182	2916	#define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /!< ADC OFFSET1 bit 5 /
richardv	0:b079fa4ed182	2917	#define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /!< ADC OFFSET1 bit 6 /
richardv	0:b079fa4ed182	2918	#define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /!< ADC OFFSET1 bit 7 /
richardv	0:b079fa4ed182	2919	#define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /!< ADC OFFSET1 bit 8 /
richardv	0:b079fa4ed182	2920	#define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /!< ADC OFFSET1 bit 9 /
richardv	0:b079fa4ed182	2921	#define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /!< ADC OFFSET1 bit 10 /
richardv	0:b079fa4ed182	2922	#define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /!< ADC OFFSET1 bit 11 /
richardv	0:b079fa4ed182	2923
richardv	0:b079fa4ed182	2924	#define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 1 /
richardv	0:b079fa4ed182	2925	#define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET1_CH bit 0 /
richardv	0:b079fa4ed182	2926	#define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET1_CH bit 1 /
richardv	0:b079fa4ed182	2927	#define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET1_CH bit 2 /
richardv	0:b079fa4ed182	2928	#define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET1_CH bit 3 /
richardv	0:b079fa4ed182	2929	#define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET1_CH bit 4 /
richardv	0:b079fa4ed182	2930
richardv	0:b079fa4ed182	2931	#define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /!< ADC offset 1 enable /
richardv	0:b079fa4ed182	2932
richardv	0:b079fa4ed182	2933	/****************** Bit definition for ADC_OFR2 register ******************/
richardv	0:b079fa4ed182	2934	#define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] /
richardv	0:b079fa4ed182	2935	#define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /!< ADC OFFSET2 bit 0 /
richardv	0:b079fa4ed182	2936	#define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /!< ADC OFFSET2 bit 1 /
richardv	0:b079fa4ed182	2937	#define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /!< ADC OFFSET2 bit 2 /
richardv	0:b079fa4ed182	2938	#define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /!< ADC OFFSET2 bit 3 /
richardv	0:b079fa4ed182	2939	#define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /!< ADC OFFSET2 bit 4 /
richardv	0:b079fa4ed182	2940	#define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /!< ADC OFFSET2 bit 5 /
richardv	0:b079fa4ed182	2941	#define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /!< ADC OFFSET2 bit 6 /
richardv	0:b079fa4ed182	2942	#define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /!< ADC OFFSET2 bit 7 /
richardv	0:b079fa4ed182	2943	#define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /!< ADC OFFSET2 bit 8 /
richardv	0:b079fa4ed182	2944	#define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /!< ADC OFFSET2 bit 9 /
richardv	0:b079fa4ed182	2945	#define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /!< ADC OFFSET2 bit 10 /
richardv	0:b079fa4ed182	2946	#define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /!< ADC OFFSET2 bit 11 /
richardv	0:b079fa4ed182	2947
richardv	0:b079fa4ed182	2948	#define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 2 /
richardv	0:b079fa4ed182	2949	#define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET2_CH bit 0 /
richardv	0:b079fa4ed182	2950	#define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET2_CH bit 1 /
richardv	0:b079fa4ed182	2951	#define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET2_CH bit 2 /
richardv	0:b079fa4ed182	2952	#define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET2_CH bit 3 /
richardv	0:b079fa4ed182	2953	#define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET2_CH bit 4 /
richardv	0:b079fa4ed182	2954
richardv	0:b079fa4ed182	2955	#define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /!< ADC offset 2 enable /
richardv	0:b079fa4ed182	2956
richardv	0:b079fa4ed182	2957	/****************** Bit definition for ADC_OFR3 register ******************/
richardv	0:b079fa4ed182	2958	#define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] /
richardv	0:b079fa4ed182	2959	#define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /!< ADC OFFSET3 bit 0 /
richardv	0:b079fa4ed182	2960	#define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /!< ADC OFFSET3 bit 1 /
richardv	0:b079fa4ed182	2961	#define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /!< ADC OFFSET3 bit 2 /
richardv	0:b079fa4ed182	2962	#define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /!< ADC OFFSET3 bit 3 /
richardv	0:b079fa4ed182	2963	#define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /!< ADC OFFSET3 bit 4 /
richardv	0:b079fa4ed182	2964	#define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /!< ADC OFFSET3 bit 5 /
richardv	0:b079fa4ed182	2965	#define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /!< ADC OFFSET3 bit 6 /
richardv	0:b079fa4ed182	2966	#define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /!< ADC OFFSET3 bit 7 /
richardv	0:b079fa4ed182	2967	#define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /!< ADC OFFSET3 bit 8 /
richardv	0:b079fa4ed182	2968	#define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /!< ADC OFFSET3 bit 9 /
richardv	0:b079fa4ed182	2969	#define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /!< ADC OFFSET3 bit 10 /
richardv	0:b079fa4ed182	2970	#define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /!< ADC OFFSET3 bit 11 /
richardv	0:b079fa4ed182	2971
richardv	0:b079fa4ed182	2972	#define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 3 /
richardv	0:b079fa4ed182	2973	#define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET3_CH bit 0 /
richardv	0:b079fa4ed182	2974	#define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET3_CH bit 1 /
richardv	0:b079fa4ed182	2975	#define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET3_CH bit 2 /
richardv	0:b079fa4ed182	2976	#define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET3_CH bit 3 /
richardv	0:b079fa4ed182	2977	#define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET3_CH bit 4 /
richardv	0:b079fa4ed182	2978
richardv	0:b079fa4ed182	2979	#define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /!< ADC offset 3 enable /
richardv	0:b079fa4ed182	2980
richardv	0:b079fa4ed182	2981	/****************** Bit definition for ADC_OFR4 register ******************/
richardv	0:b079fa4ed182	2982	#define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] /
richardv	0:b079fa4ed182	2983	#define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /!< ADC OFFSET4 bit 0 /
richardv	0:b079fa4ed182	2984	#define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /!< ADC OFFSET4 bit 1 /
richardv	0:b079fa4ed182	2985	#define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /!< ADC OFFSET4 bit 2 /
richardv	0:b079fa4ed182	2986	#define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /!< ADC OFFSET4 bit 3 /
richardv	0:b079fa4ed182	2987	#define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /!< ADC OFFSET4 bit 4 /
richardv	0:b079fa4ed182	2988	#define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /!< ADC OFFSET4 bit 5 /
richardv	0:b079fa4ed182	2989	#define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /!< ADC OFFSET4 bit 6 /
richardv	0:b079fa4ed182	2990	#define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /!< ADC OFFSET4 bit 7 /
richardv	0:b079fa4ed182	2991	#define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /!< ADC OFFSET4 bit 8 /
richardv	0:b079fa4ed182	2992	#define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /!< ADC OFFSET4 bit 9 /
richardv	0:b079fa4ed182	2993	#define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /!< ADC OFFSET4 bit 10 /
richardv	0:b079fa4ed182	2994	#define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /!< ADC OFFSET4 bit 11 /
richardv	0:b079fa4ed182	2995
richardv	0:b079fa4ed182	2996	#define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /!< ADC Channel selection for the data offset 4 /
richardv	0:b079fa4ed182	2997	#define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /!< ADC OFFSET4_CH bit 0 /
richardv	0:b079fa4ed182	2998	#define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /!< ADC OFFSET4_CH bit 1 /
richardv	0:b079fa4ed182	2999	#define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /!< ADC OFFSET4_CH bit 2 /
richardv	0:b079fa4ed182	3000	#define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /!< ADC OFFSET4_CH bit 3 /
richardv	0:b079fa4ed182	3001	#define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /!< ADC OFFSET4_CH bit 4 /
richardv	0:b079fa4ed182	3002
richardv	0:b079fa4ed182	3003	#define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /!< ADC offset 4 enable /
richardv	0:b079fa4ed182	3004
richardv	0:b079fa4ed182	3005	/****************** Bit definition for ADC_JDR1 register ******************/
richardv	0:b079fa4ed182	3006	#define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
richardv	0:b079fa4ed182	3007	#define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
richardv	0:b079fa4ed182	3008	#define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
richardv	0:b079fa4ed182	3009	#define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
richardv	0:b079fa4ed182	3010	#define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
richardv	0:b079fa4ed182	3011	#define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
richardv	0:b079fa4ed182	3012	#define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
richardv	0:b079fa4ed182	3013	#define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
richardv	0:b079fa4ed182	3014	#define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
richardv	0:b079fa4ed182	3015	#define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
richardv	0:b079fa4ed182	3016	#define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
richardv	0:b079fa4ed182	3017	#define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
richardv	0:b079fa4ed182	3018	#define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
richardv	0:b079fa4ed182	3019	#define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
richardv	0:b079fa4ed182	3020	#define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
richardv	0:b079fa4ed182	3021	#define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
richardv	0:b079fa4ed182	3022	#define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
richardv	0:b079fa4ed182	3023
richardv	0:b079fa4ed182	3024	/****************** Bit definition for ADC_JDR2 register ******************/
richardv	0:b079fa4ed182	3025	#define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
richardv	0:b079fa4ed182	3026	#define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
richardv	0:b079fa4ed182	3027	#define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
richardv	0:b079fa4ed182	3028	#define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
richardv	0:b079fa4ed182	3029	#define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
richardv	0:b079fa4ed182	3030	#define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
richardv	0:b079fa4ed182	3031	#define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
richardv	0:b079fa4ed182	3032	#define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
richardv	0:b079fa4ed182	3033	#define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
richardv	0:b079fa4ed182	3034	#define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
richardv	0:b079fa4ed182	3035	#define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
richardv	0:b079fa4ed182	3036	#define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
richardv	0:b079fa4ed182	3037	#define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
richardv	0:b079fa4ed182	3038	#define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
richardv	0:b079fa4ed182	3039	#define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
richardv	0:b079fa4ed182	3040	#define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
richardv	0:b079fa4ed182	3041	#define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
richardv	0:b079fa4ed182	3042
richardv	0:b079fa4ed182	3043	/****************** Bit definition for ADC_JDR3 register ******************/
richardv	0:b079fa4ed182	3044	#define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
richardv	0:b079fa4ed182	3045	#define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
richardv	0:b079fa4ed182	3046	#define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
richardv	0:b079fa4ed182	3047	#define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
richardv	0:b079fa4ed182	3048	#define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
richardv	0:b079fa4ed182	3049	#define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
richardv	0:b079fa4ed182	3050	#define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
richardv	0:b079fa4ed182	3051	#define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
richardv	0:b079fa4ed182	3052	#define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
richardv	0:b079fa4ed182	3053	#define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
richardv	0:b079fa4ed182	3054	#define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
richardv	0:b079fa4ed182	3055	#define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
richardv	0:b079fa4ed182	3056	#define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
richardv	0:b079fa4ed182	3057	#define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
richardv	0:b079fa4ed182	3058	#define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
richardv	0:b079fa4ed182	3059	#define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
richardv	0:b079fa4ed182	3060	#define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
richardv	0:b079fa4ed182	3061
richardv	0:b079fa4ed182	3062	/****************** Bit definition for ADC_JDR4 register ******************/
richardv	0:b079fa4ed182	3063	#define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /!< ADC Injected DATA /
richardv	0:b079fa4ed182	3064	#define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /!< ADC JDATA bit 0 /
richardv	0:b079fa4ed182	3065	#define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /!< ADC JDATA bit 1 /
richardv	0:b079fa4ed182	3066	#define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /!< ADC JDATA bit 2 /
richardv	0:b079fa4ed182	3067	#define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /!< ADC JDATA bit 3 /
richardv	0:b079fa4ed182	3068	#define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /!< ADC JDATA bit 4 /
richardv	0:b079fa4ed182	3069	#define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /!< ADC JDATA bit 5 /
richardv	0:b079fa4ed182	3070	#define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /!< ADC JDATA bit 6 /
richardv	0:b079fa4ed182	3071	#define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /!< ADC JDATA bit 7 /
richardv	0:b079fa4ed182	3072	#define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /!< ADC JDATA bit 8 /
richardv	0:b079fa4ed182	3073	#define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /!< ADC JDATA bit 9 /
richardv	0:b079fa4ed182	3074	#define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /!< ADC JDATA bit 10 /
richardv	0:b079fa4ed182	3075	#define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /!< ADC JDATA bit 11 /
richardv	0:b079fa4ed182	3076	#define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /!< ADC JDATA bit 12 /
richardv	0:b079fa4ed182	3077	#define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /!< ADC JDATA bit 13 /
richardv	0:b079fa4ed182	3078	#define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /!< ADC JDATA bit 14 /
richardv	0:b079fa4ed182	3079	#define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /!< ADC JDATA bit 15 /
richardv	0:b079fa4ed182	3080
richardv	0:b079fa4ed182	3081	/****************** Bit definition for ADC_AWD2CR register ******************/
richardv	0:b079fa4ed182	3082	#define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /!< ADC Analog watchdog 2 channel selection /
richardv	0:b079fa4ed182	3083	#define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /!< ADC AWD2CH bit 0 /
richardv	0:b079fa4ed182	3084	#define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /!< ADC AWD2CH bit 1 /
richardv	0:b079fa4ed182	3085	#define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /!< ADC AWD2CH bit 2 /
richardv	0:b079fa4ed182	3086	#define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /!< ADC AWD2CH bit 3 /
richardv	0:b079fa4ed182	3087	#define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /!< ADC AWD2CH bit 4 /
richardv	0:b079fa4ed182	3088	#define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /!< ADC AWD2CH bit 5 /
richardv	0:b079fa4ed182	3089	#define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /!< ADC AWD2CH bit 6 /
richardv	0:b079fa4ed182	3090	#define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /!< ADC AWD2CH bit 7 /
richardv	0:b079fa4ed182	3091	#define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /!< ADC AWD2CH bit 8 /
richardv	0:b079fa4ed182	3092	#define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /!< ADC AWD2CH bit 9 /
richardv	0:b079fa4ed182	3093	#define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /!< ADC AWD2CH bit 10 /
richardv	0:b079fa4ed182	3094	#define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /!< ADC AWD2CH bit 11 /
richardv	0:b079fa4ed182	3095	#define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /!< ADC AWD2CH bit 12 /
richardv	0:b079fa4ed182	3096	#define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /!< ADC AWD2CH bit 13 /
richardv	0:b079fa4ed182	3097	#define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /!< ADC AWD2CH bit 14 /
richardv	0:b079fa4ed182	3098	#define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /!< ADC AWD2CH bit 15 /
richardv	0:b079fa4ed182	3099	#define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /!< ADC AWD2CH bit 16 /
richardv	0:b079fa4ed182	3100	#define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /!< ADC AWD2CH bit 17 /
richardv	0:b079fa4ed182	3101
richardv	0:b079fa4ed182	3102	/****************** Bit definition for ADC_AWD3CR register ******************/
richardv	0:b079fa4ed182	3103	#define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /!< ADC Analog watchdog 2 channel selection /
richardv	0:b079fa4ed182	3104	#define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /!< ADC AWD3CH bit 0 /
richardv	0:b079fa4ed182	3105	#define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /!< ADC AWD3CH bit 1 /
richardv	0:b079fa4ed182	3106	#define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /!< ADC AWD3CH bit 2 /
richardv	0:b079fa4ed182	3107	#define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /!< ADC AWD3CH bit 3 /
richardv	0:b079fa4ed182	3108	#define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /!< ADC AWD3CH bit 4 /
richardv	0:b079fa4ed182	3109	#define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /!< ADC AWD3CH bit 5 /
richardv	0:b079fa4ed182	3110	#define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /!< ADC AWD3CH bit 6 /
richardv	0:b079fa4ed182	3111	#define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /!< ADC AWD3CH bit 7 /
richardv	0:b079fa4ed182	3112	#define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /!< ADC AWD3CH bit 8 /
richardv	0:b079fa4ed182	3113	#define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /!< ADC AWD3CH bit 9 /
richardv	0:b079fa4ed182	3114	#define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /!< ADC AWD3CH bit 10 /
richardv	0:b079fa4ed182	3115	#define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /!< ADC AWD3CH bit 11 /
richardv	0:b079fa4ed182	3116	#define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /!< ADC AWD3CH bit 12 /
richardv	0:b079fa4ed182	3117	#define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /!< ADC AWD3CH bit 13 /
richardv	0:b079fa4ed182	3118	#define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /!< ADC AWD3CH bit 14 /
richardv	0:b079fa4ed182	3119	#define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /!< ADC AWD3CH bit 15 /
richardv	0:b079fa4ed182	3120	#define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /!< ADC AWD3CH bit 16 /
richardv	0:b079fa4ed182	3121	#define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /!< ADC AWD3CH bit 17 /
richardv	0:b079fa4ed182	3122
richardv	0:b079fa4ed182	3123	/****************** Bit definition for ADC_DIFSEL register ******************/
richardv	0:b079fa4ed182	3124	#define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /!< ADC differential modes for channels 1 to 18 /
richardv	0:b079fa4ed182	3125	#define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /!< ADC DIFSEL bit 0 /
richardv	0:b079fa4ed182	3126	#define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /!< ADC DIFSEL bit 1 /
richardv	0:b079fa4ed182	3127	#define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /!< ADC DIFSEL bit 2 /
richardv	0:b079fa4ed182	3128	#define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /!< ADC DIFSEL bit 3 /
richardv	0:b079fa4ed182	3129	#define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /!< ADC DIFSEL bit 4 /
richardv	0:b079fa4ed182	3130	#define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /!< ADC DIFSEL bit 5 /
richardv	0:b079fa4ed182	3131	#define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /!< ADC DIFSEL bit 6 /
richardv	0:b079fa4ed182	3132	#define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /!< ADC DIFSEL bit 7 /
richardv	0:b079fa4ed182	3133	#define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /!< ADC DIFSEL bit 8 /
richardv	0:b079fa4ed182	3134	#define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /!< ADC DIFSEL bit 9 /
richardv	0:b079fa4ed182	3135	#define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /!< ADC DIFSEL bit 10 /
richardv	0:b079fa4ed182	3136	#define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /!< ADC DIFSEL bit 11 /
richardv	0:b079fa4ed182	3137	#define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /!< ADC DIFSEL bit 12 /
richardv	0:b079fa4ed182	3138	#define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /!< ADC DIFSEL bit 13 /
richardv	0:b079fa4ed182	3139	#define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /!< ADC DIFSEL bit 14 /
richardv	0:b079fa4ed182	3140	#define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /!< ADC DIFSEL bit 15 /
richardv	0:b079fa4ed182	3141	#define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /!< ADC DIFSEL bit 16 /
richardv	0:b079fa4ed182	3142	#define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /!< ADC DIFSEL bit 17 /
richardv	0:b079fa4ed182	3143
richardv	0:b079fa4ed182	3144	/****************** Bit definition for ADC_CALFACT register ******************/
richardv	0:b079fa4ed182	3145	#define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /!< ADC calibration factors in single-ended mode /
richardv	0:b079fa4ed182	3146	#define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /!< ADC CALFACT_S bit 0 /
richardv	0:b079fa4ed182	3147	#define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /!< ADC CALFACT_S bit 1 /
richardv	0:b079fa4ed182	3148	#define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /!< ADC CALFACT_S bit 2 /
richardv	0:b079fa4ed182	3149	#define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /!< ADC CALFACT_S bit 3 /
richardv	0:b079fa4ed182	3150	#define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /!< ADC CALFACT_S bit 4 /
richardv	0:b079fa4ed182	3151	#define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /!< ADC CALFACT_S bit 5 /
richardv	0:b079fa4ed182	3152	#define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /!< ADC CALFACT_S bit 6 /
richardv	0:b079fa4ed182	3153	#define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /!< ADC calibration factors in differential mode /
richardv	0:b079fa4ed182	3154	#define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /!< ADC CALFACT_D bit 0 /
richardv	0:b079fa4ed182	3155	#define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /!< ADC CALFACT_D bit 1 /
richardv	0:b079fa4ed182	3156	#define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /!< ADC CALFACT_D bit 2 /
richardv	0:b079fa4ed182	3157	#define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /!< ADC CALFACT_D bit 3 /
richardv	0:b079fa4ed182	3158	#define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /!< ADC CALFACT_D bit 4 /
richardv	0:b079fa4ed182	3159	#define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /!< ADC CALFACT_D bit 5 /
richardv	0:b079fa4ed182	3160	#define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /!< ADC CALFACT_D bit 6 /
richardv	0:b079fa4ed182	3161
richardv	0:b079fa4ed182	3162	/*********************** ADC Common registers ***************************/
richardv	0:b079fa4ed182	3163	/****************** Bit definition for ADC12_CSR register ******************/
richardv	0:b079fa4ed182	3164	#define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /!< Master ADC ready /
richardv	0:b079fa4ed182	3165	#define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /!< End of sampling phase flag of the master ADC /
richardv	0:b079fa4ed182	3166	#define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /!< End of regular conversion of the master ADC /
richardv	0:b079fa4ed182	3167	#define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /!< End of regular sequence flag of the master ADC /
richardv	0:b079fa4ed182	3168	#define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /!< Overrun flag of the master ADC /
richardv	0:b079fa4ed182	3169	#define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /!< End of injected conversion of the master ADC /
richardv	0:b079fa4ed182	3170	#define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /!< End of injected sequence flag of the master ADC /
richardv	0:b079fa4ed182	3171	#define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /!< Analog watchdog 1 flag of the master ADC /
richardv	0:b079fa4ed182	3172	#define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /!< Analog watchdog 2 flag of the master ADC /
richardv	0:b079fa4ed182	3173	#define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /!< Analog watchdog 3 flag of the master ADC /
richardv	0:b079fa4ed182	3174	#define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /!< Injected context queue overflow flag of the master ADC /
richardv	0:b079fa4ed182	3175	#define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /!< Slave ADC ready /
richardv	0:b079fa4ed182	3176	#define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /!< End of sampling phase flag of the slave ADC /
richardv	0:b079fa4ed182	3177	#define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /!< End of regular conversion of the slave ADC /
richardv	0:b079fa4ed182	3178	#define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /!< End of regular sequence flag of the slave ADC /
richardv	0:b079fa4ed182	3179	#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /!< Overrun flag of the slave ADC /
richardv	0:b079fa4ed182	3180	#define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /!< End of injected conversion of the slave ADC /
richardv	0:b079fa4ed182	3181	#define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /!< End of injected sequence flag of the slave ADC /
richardv	0:b079fa4ed182	3182	#define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /!< Analog watchdog 1 flag of the slave ADC /
richardv	0:b079fa4ed182	3183	#define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /!< Analog watchdog 2 flag of the slave ADC /
richardv	0:b079fa4ed182	3184	#define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /!< Analog watchdog 3 flag of the slave ADC /
richardv	0:b079fa4ed182	3185	#define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /!< Injected context queue overflow flag of the slave ADC /
richardv	0:b079fa4ed182	3186
richardv	0:b079fa4ed182	3187	/****************** Bit definition for ADC34_CSR register ******************/
richardv	0:b079fa4ed182	3188	#define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /!< Master ADC ready /
richardv	0:b079fa4ed182	3189	#define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /!< End of sampling phase flag of the master ADC /
richardv	0:b079fa4ed182	3190	#define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /!< End of regular conversion of the master ADC /
richardv	0:b079fa4ed182	3191	#define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /!< End of regular sequence flag of the master ADC /
richardv	0:b079fa4ed182	3192	#define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /!< Overrun flag of the master ADC /
richardv	0:b079fa4ed182	3193	#define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /!< End of injected conversion of the master ADC /
richardv	0:b079fa4ed182	3194	#define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /!< End of injected sequence flag of the master ADC /
richardv	0:b079fa4ed182	3195	#define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /!< Analog watchdog 1 flag of the master ADC /
richardv	0:b079fa4ed182	3196	#define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /!< Analog watchdog 2 flag of the master ADC /
richardv	0:b079fa4ed182	3197	#define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /!< Analog watchdog 3 flag of the master ADC /
richardv	0:b079fa4ed182	3198	#define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /!< Injected context queue overflow flag of the master ADC /
richardv	0:b079fa4ed182	3199	#define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /!< Slave ADC ready /
richardv	0:b079fa4ed182	3200	#define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /!< End of sampling phase flag of the slave ADC /
richardv	0:b079fa4ed182	3201	#define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /!< End of regular conversion of the slave ADC /
richardv	0:b079fa4ed182	3202	#define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /!< End of regular sequence flag of the slave ADC /
richardv	0:b079fa4ed182	3203	#define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /!< Overrun flag of the slave ADC /
richardv	0:b079fa4ed182	3204	#define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /!< End of injected conversion of the slave ADC /
richardv	0:b079fa4ed182	3205	#define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /!< End of injected sequence flag of the slave ADC /
richardv	0:b079fa4ed182	3206	#define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /!< Analog watchdog 1 flag of the slave ADC /
richardv	0:b079fa4ed182	3207	#define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /!< Analog watchdog 2 flag of the slave ADC /
richardv	0:b079fa4ed182	3208	#define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /!< Analog watchdog 3 flag of the slave ADC /
richardv	0:b079fa4ed182	3209	#define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /!< Injected context queue overflow flag of the slave ADC /
richardv	0:b079fa4ed182	3210
richardv	0:b079fa4ed182	3211	/****************** Bit definition for ADC_CCR register ******************/
richardv	0:b079fa4ed182	3212	#define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /!< Multi ADC mode selection /
richardv	0:b079fa4ed182	3213	#define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /!< MULTI bit 0 /
richardv	0:b079fa4ed182	3214	#define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /!< MULTI bit 1 /
richardv	0:b079fa4ed182	3215	#define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /!< MULTI bit 2 /
richardv	0:b079fa4ed182	3216	#define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /!< MULTI bit 3 /
richardv	0:b079fa4ed182	3217	#define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /!< MULTI bit 4 /
richardv	0:b079fa4ed182	3218	#define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /!< Delay between 2 sampling phases /
richardv	0:b079fa4ed182	3219	#define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /!< DELAY bit 0 /
richardv	0:b079fa4ed182	3220	#define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /!< DELAY bit 1 /
richardv	0:b079fa4ed182	3221	#define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /!< DELAY bit 2 /
richardv	0:b079fa4ed182	3222	#define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /!< DELAY bit 3 /
richardv	0:b079fa4ed182	3223	#define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /!< DMA configuration for multi-ADC mode /
richardv	0:b079fa4ed182	3224	#define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /!< DMA mode for multi-ADC mode /
richardv	0:b079fa4ed182	3225	#define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /!< MDMA bit 0 /
richardv	0:b079fa4ed182	3226	#define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /!< MDMA bit 1 /
richardv	0:b079fa4ed182	3227	#define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /!< ADC clock mode /
richardv	0:b079fa4ed182	3228	#define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /!< CKMODE bit 0 /
richardv	0:b079fa4ed182	3229	#define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /!< CKMODE bit 1 /
richardv	0:b079fa4ed182	3230	#define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /!< VREFINT enable /
richardv	0:b079fa4ed182	3231	#define ADC12_CCR_TSEN ((uint32_t)0x00800000) /!< Temperature sensor enable /
richardv	0:b079fa4ed182	3232	#define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /!< VBAT enable /
richardv	0:b079fa4ed182	3233
richardv	0:b079fa4ed182	3234	/****************** Bit definition for ADC_CCR register ******************/
richardv	0:b079fa4ed182	3235	#define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /!< Multi ADC mode selection /
richardv	0:b079fa4ed182	3236	#define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /!< MULTI bit 0 /
richardv	0:b079fa4ed182	3237	#define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /!< MULTI bit 1 /
richardv	0:b079fa4ed182	3238	#define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /!< MULTI bit 2 /
richardv	0:b079fa4ed182	3239	#define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /!< MULTI bit 3 /
richardv	0:b079fa4ed182	3240	#define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /!< MULTI bit 4 /
richardv	0:b079fa4ed182	3241
richardv	0:b079fa4ed182	3242	#define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /!< Delay between 2 sampling phases /
richardv	0:b079fa4ed182	3243	#define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /!< DELAY bit 0 /
richardv	0:b079fa4ed182	3244	#define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /!< DELAY bit 1 /
richardv	0:b079fa4ed182	3245	#define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /!< DELAY bit 2 /
richardv	0:b079fa4ed182	3246	#define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /!< DELAY bit 3 /
richardv	0:b079fa4ed182	3247
richardv	0:b079fa4ed182	3248	#define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /!< DMA configuration for multi-ADC mode /
richardv	0:b079fa4ed182	3249	#define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /!< DMA mode for multi-ADC mode /
richardv	0:b079fa4ed182	3250	#define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /!< MDMA bit 0 /
richardv	0:b079fa4ed182	3251	#define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /!< MDMA bit 1 /
richardv	0:b079fa4ed182	3252
richardv	0:b079fa4ed182	3253	#define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /!< ADC clock mode /
richardv	0:b079fa4ed182	3254	#define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /!< CKMODE bit 0 /
richardv	0:b079fa4ed182	3255	#define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /!< CKMODE bit 1 /
richardv	0:b079fa4ed182	3256
richardv	0:b079fa4ed182	3257	#define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /!< VREFINT enable /
richardv	0:b079fa4ed182	3258
richardv	0:b079fa4ed182	3259	/****************** Bit definition for ADC_CDR register ******************/
richardv	0:b079fa4ed182	3260	#define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /!< Regular Data of the master ADC /
richardv	0:b079fa4ed182	3261	#define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /!< RDATA_MST bit 0 /
richardv	0:b079fa4ed182	3262	#define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /!< RDATA_MST bit 1 /
richardv	0:b079fa4ed182	3263	#define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /!< RDATA_MST bit 2 /
richardv	0:b079fa4ed182	3264	#define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /!< RDATA_MST bit 3 /
richardv	0:b079fa4ed182	3265	#define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /!< RDATA_MST bit 4 /
richardv	0:b079fa4ed182	3266	#define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /!< RDATA_MST bit 5 /
richardv	0:b079fa4ed182	3267	#define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /!< RDATA_MST bit 6 /
richardv	0:b079fa4ed182	3268	#define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /!< RDATA_MST bit 7 /
richardv	0:b079fa4ed182	3269	#define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /!< RDATA_MST bit 8 /
richardv	0:b079fa4ed182	3270	#define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /!< RDATA_MST bit 9 /
richardv	0:b079fa4ed182	3271	#define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /!< RDATA_MST bit 10 /
richardv	0:b079fa4ed182	3272	#define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /!< RDATA_MST bit 11 /
richardv	0:b079fa4ed182	3273	#define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /!< RDATA_MST bit 12 /
richardv	0:b079fa4ed182	3274	#define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /!< RDATA_MST bit 13 /
richardv	0:b079fa4ed182	3275	#define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /!< RDATA_MST bit 14 /
richardv	0:b079fa4ed182	3276	#define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /!< RDATA_MST bit 15 /
richardv	0:b079fa4ed182	3277
richardv	0:b079fa4ed182	3278	#define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /!< Regular Data of the master ADC /
richardv	0:b079fa4ed182	3279	#define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /!< RDATA_SLV bit 0 /
richardv	0:b079fa4ed182	3280	#define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /!< RDATA_SLV bit 1 /
richardv	0:b079fa4ed182	3281	#define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /!< RDATA_SLV bit 2 /
richardv	0:b079fa4ed182	3282	#define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /!< RDATA_SLV bit 3 /
richardv	0:b079fa4ed182	3283	#define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /!< RDATA_SLV bit 4 /
richardv	0:b079fa4ed182	3284	#define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /!< RDATA_SLV bit 5 /
richardv	0:b079fa4ed182	3285	#define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /!< RDATA_SLV bit 6 /
richardv	0:b079fa4ed182	3286	#define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /!< RDATA_SLV bit 7 /
richardv	0:b079fa4ed182	3287	#define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /!< RDATA_SLV bit 8 /
richardv	0:b079fa4ed182	3288	#define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /!< RDATA_SLV bit 9 /
richardv	0:b079fa4ed182	3289	#define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /!< RDATA_SLV bit 10 /
richardv	0:b079fa4ed182	3290	#define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /!< RDATA_SLV bit 11 /
richardv	0:b079fa4ed182	3291	#define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /!< RDATA_SLV bit 12 /
richardv	0:b079fa4ed182	3292	#define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /!< RDATA_SLV bit 13 /
richardv	0:b079fa4ed182	3293	#define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /!< RDATA_SLV bit 14 /
richardv	0:b079fa4ed182	3294	#define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /!< RDATA_SLV bit 15 /
richardv	0:b079fa4ed182	3295
richardv	0:b079fa4ed182	3296	/****************** Bit definition for ADC_CDR register ******************/
richardv	0:b079fa4ed182	3297	#define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /!< Regular Data of the master ADC /
richardv	0:b079fa4ed182	3298	#define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /!< RDATA_MST bit 0 /
richardv	0:b079fa4ed182	3299	#define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /!< RDATA_MST bit 1 /
richardv	0:b079fa4ed182	3300	#define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /!< RDATA_MST bit 2 /
richardv	0:b079fa4ed182	3301	#define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /!< RDATA_MST bit 3 /
richardv	0:b079fa4ed182	3302	#define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /!< RDATA_MST bit 4 /
richardv	0:b079fa4ed182	3303	#define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /!< RDATA_MST bit 5 /
richardv	0:b079fa4ed182	3304	#define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /!< RDATA_MST bit 6 /
richardv	0:b079fa4ed182	3305	#define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /!< RDATA_MST bit 7 /
richardv	0:b079fa4ed182	3306	#define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /!< RDATA_MST bit 8 /
richardv	0:b079fa4ed182	3307	#define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /!< RDATA_MST bit 9 /
richardv	0:b079fa4ed182	3308	#define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /!< RDATA_MST bit 10 /
richardv	0:b079fa4ed182	3309	#define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /!< RDATA_MST bit 11 /
richardv	0:b079fa4ed182	3310	#define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /!< RDATA_MST bit 12 /
richardv	0:b079fa4ed182	3311	#define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /!< RDATA_MST bit 13 /
richardv	0:b079fa4ed182	3312	#define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /!< RDATA_MST bit 14 /
richardv	0:b079fa4ed182	3313	#define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /!< RDATA_MST bit 15 /
richardv	0:b079fa4ed182	3314
richardv	0:b079fa4ed182	3315	#define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /!< Regular Data of the master ADC /
richardv	0:b079fa4ed182	3316	#define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /!< RDATA_SLV bit 0 /
richardv	0:b079fa4ed182	3317	#define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /!< RDATA_SLV bit 1 /
richardv	0:b079fa4ed182	3318	#define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /!< RDATA_SLV bit 2 /
richardv	0:b079fa4ed182	3319	#define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /!< RDATA_SLV bit 3 /
richardv	0:b079fa4ed182	3320	#define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /!< RDATA_SLV bit 4 /
richardv	0:b079fa4ed182	3321	#define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /!< RDATA_SLV bit 5 /
richardv	0:b079fa4ed182	3322	#define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /!< RDATA_SLV bit 6 /
richardv	0:b079fa4ed182	3323	#define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /!< RDATA_SLV bit 7 /
richardv	0:b079fa4ed182	3324	#define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /!< RDATA_SLV bit 8 /
richardv	0:b079fa4ed182	3325	#define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /!< RDATA_SLV bit 9 /
richardv	0:b079fa4ed182	3326	#define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /!< RDATA_SLV bit 10 /
richardv	0:b079fa4ed182	3327	#define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /!< RDATA_SLV bit 11 /
richardv	0:b079fa4ed182	3328	#define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /!< RDATA_SLV bit 12 /
richardv	0:b079fa4ed182	3329	#define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /!< RDATA_SLV bit 13 /
richardv	0:b079fa4ed182	3330	#define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /!< RDATA_SLV bit 14 /
richardv	0:b079fa4ed182	3331	#define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /!< RDATA_SLV bit 15 /
richardv	0:b079fa4ed182	3332
richardv	0:b079fa4ed182	3333	/******************************************************************************/
richardv	0:b079fa4ed182	3334	/* */
richardv	0:b079fa4ed182	3335	/* Analog Comparators (COMP) */
richardv	0:b079fa4ed182	3336	/* */
richardv	0:b079fa4ed182	3337	/******************************************************************************/
richardv	0:b079fa4ed182	3338	/******************** Bit definition for COMP1_CSR register *************/
richardv	0:b079fa4ed182	3339	#define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /!< COMP1 enable /
richardv	0:b079fa4ed182	3340	#define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /!< COMP1 SW1 switch control /
richardv	0:b079fa4ed182	3341	#define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /!< COMP1 power mode /
richardv	0:b079fa4ed182	3342	#define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /!< COMP1 power mode bit 0 /
richardv	0:b079fa4ed182	3343	#define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /!< COMP1 power mode bit 1 /
richardv	0:b079fa4ed182	3344	#define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /!< COMP1 inverting input select /
richardv	0:b079fa4ed182	3345	#define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /!< COMP1 inverting input select bit 0 /
richardv	0:b079fa4ed182	3346	#define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /!< COMP1 inverting input select bit 1 /
richardv	0:b079fa4ed182	3347	#define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /!< COMP1 inverting input select bit 2 /
richardv	0:b079fa4ed182	3348	#define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /!< COMP1 non inverting input select /
richardv	0:b079fa4ed182	3349	#define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /!< COMP1 output select /
richardv	0:b079fa4ed182	3350	#define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /!< COMP1 output select bit 0 /
richardv	0:b079fa4ed182	3351	#define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /!< COMP1 output select bit 1 /
richardv	0:b079fa4ed182	3352	#define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /!< COMP1 output select bit 2 /
richardv	0:b079fa4ed182	3353	#define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /!< COMP1 output select bit 3 /
richardv	0:b079fa4ed182	3354	#define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /!< COMP1 output polarity /
richardv	0:b079fa4ed182	3355	#define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /!< COMP1 hysteresis /
richardv	0:b079fa4ed182	3356	#define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /!< COMP1 hysteresis bit 0 /
richardv	0:b079fa4ed182	3357	#define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /!< COMP1 hysteresis bit 1 /
richardv	0:b079fa4ed182	3358	#define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /!< COMP1 blanking /
richardv	0:b079fa4ed182	3359	#define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /!< COMP1 blanking bit 0 /
richardv	0:b079fa4ed182	3360	#define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /!< COMP1 blanking bit 1 /
richardv	0:b079fa4ed182	3361	#define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /!< COMP1 blanking bit 2 /
richardv	0:b079fa4ed182	3362	#define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /!< COMP1 output level /
richardv	0:b079fa4ed182	3363	#define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /!< COMP1 lock /
richardv	0:b079fa4ed182	3364
richardv	0:b079fa4ed182	3365	/******************** Bit definition for COMP2_CSR register *************/
richardv	0:b079fa4ed182	3366	#define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /!< COMP2 enable /
richardv	0:b079fa4ed182	3367	#define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /!< COMP2 power mode /
richardv	0:b079fa4ed182	3368	#define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /!< COMP2 power mode bit 0 /
richardv	0:b079fa4ed182	3369	#define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /!< COMP2 power mode bit 1 /
richardv	0:b079fa4ed182	3370	#define COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) /!< COMP2 inverting input select /
richardv	0:b079fa4ed182	3371	#define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /!< COMP2 inverting input select bit 0 /
richardv	0:b079fa4ed182	3372	#define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /!< COMP2 inverting input select bit 1 /
richardv	0:b079fa4ed182	3373	#define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /!< COMP2 inverting input select bit 2 /
richardv	0:b079fa4ed182	3374	#define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /!< COMP2 non inverting input select /
richardv	0:b079fa4ed182	3375	#define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /!< COMP2 window mode enable /
richardv	0:b079fa4ed182	3376	#define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /!< COMP2 output select /
richardv	0:b079fa4ed182	3377	#define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /!< COMP2 output select bit 0 /
richardv	0:b079fa4ed182	3378	#define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /!< COMP2 output select bit 1 /
richardv	0:b079fa4ed182	3379	#define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /!< COMP2 output select bit 2 /
richardv	0:b079fa4ed182	3380	#define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /!< COMP2 output select bit 3 /
richardv	0:b079fa4ed182	3381	#define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /!< COMP2 output polarity /
richardv	0:b079fa4ed182	3382	#define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /!< COMP2 hysteresis /
richardv	0:b079fa4ed182	3383	#define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /!< COMP2 hysteresis bit 0 /
richardv	0:b079fa4ed182	3384	#define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /!< COMP2 hysteresis bit 1 /
richardv	0:b079fa4ed182	3385	#define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /!< COMP2 blanking /
richardv	0:b079fa4ed182	3386	#define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /!< COMP2 blanking bit 0 /
richardv	0:b079fa4ed182	3387	#define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /!< COMP2 blanking bit 1 /
richardv	0:b079fa4ed182	3388	#define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /!< COMP2 blanking bit 2 /
richardv	0:b079fa4ed182	3389	#define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /!< COMP2 output level /
richardv	0:b079fa4ed182	3390	#define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /!< COMP2 lock /
richardv	0:b079fa4ed182	3391
richardv	0:b079fa4ed182	3392	/******************** Bit definition for COMP3_CSR register *************/
richardv	0:b079fa4ed182	3393	#define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /!< COMP3 enable /
richardv	0:b079fa4ed182	3394	#define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /!< COMP3 power mode /
richardv	0:b079fa4ed182	3395	#define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /!< COMP3 power mode bit 0 /
richardv	0:b079fa4ed182	3396	#define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /!< COMP3 power mode bit 1 /
richardv	0:b079fa4ed182	3397	#define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /!< COMP3 inverting input select /
richardv	0:b079fa4ed182	3398	#define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /!< COMP3 inverting input select bit 0 /
richardv	0:b079fa4ed182	3399	#define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /!< COMP3 inverting input select bit 1 /
richardv	0:b079fa4ed182	3400	#define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /!< COMP3 inverting input select bit 2 /
richardv	0:b079fa4ed182	3401	#define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /!< COMP3 non inverting input select /
richardv	0:b079fa4ed182	3402	#define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /!< COMP3 output select /
richardv	0:b079fa4ed182	3403	#define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /!< COMP3 output select bit 0 /
richardv	0:b079fa4ed182	3404	#define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /!< COMP3 output select bit 1 /
richardv	0:b079fa4ed182	3405	#define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /!< COMP3 output select bit 2 /
richardv	0:b079fa4ed182	3406	#define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /!< COMP3 output select bit 3 /
richardv	0:b079fa4ed182	3407	#define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /!< COMP3 output polarity /
richardv	0:b079fa4ed182	3408	#define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /!< COMP3 hysteresis /
richardv	0:b079fa4ed182	3409	#define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /!< COMP3 hysteresis bit 0 /
richardv	0:b079fa4ed182	3410	#define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /!< COMP3 hysteresis bit 1 /
richardv	0:b079fa4ed182	3411	#define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /!< COMP3 blanking /
richardv	0:b079fa4ed182	3412	#define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /!< COMP3 blanking bit 0 /
richardv	0:b079fa4ed182	3413	#define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /!< COMP3 blanking bit 1 /
richardv	0:b079fa4ed182	3414	#define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /!< COMP3 blanking bit 2 /
richardv	0:b079fa4ed182	3415	#define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /!< COMP3 output level /
richardv	0:b079fa4ed182	3416	#define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /!< COMP3 lock /
richardv	0:b079fa4ed182	3417
richardv	0:b079fa4ed182	3418	/******************** Bit definition for COMP4_CSR register *************/
richardv	0:b079fa4ed182	3419	#define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /!< COMP4 enable /
richardv	0:b079fa4ed182	3420	#define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /!< COMP4 power mode /
richardv	0:b079fa4ed182	3421	#define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /!< COMP4 power mode bit 0 /
richardv	0:b079fa4ed182	3422	#define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /!< COMP4 power mode bit 1 /
richardv	0:b079fa4ed182	3423	#define COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) /!< COMP4 inverting input select /
richardv	0:b079fa4ed182	3424	#define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /!< COMP4 inverting input select bit 0 /
richardv	0:b079fa4ed182	3425	#define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /!< COMP4 inverting input select bit 1 /
richardv	0:b079fa4ed182	3426	#define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /!< COMP4 inverting input select bit 2 /
richardv	0:b079fa4ed182	3427	#define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /!< COMP4 non inverting input select /
richardv	0:b079fa4ed182	3428	#define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /!< COMP4 window mode enable /
richardv	0:b079fa4ed182	3429	#define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /!< COMP4 output select /
richardv	0:b079fa4ed182	3430	#define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /!< COMP4 output select bit 0 /
richardv	0:b079fa4ed182	3431	#define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /!< COMP4 output select bit 1 /
richardv	0:b079fa4ed182	3432	#define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /!< COMP4 output select bit 2 /
richardv	0:b079fa4ed182	3433	#define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /!< COMP4 output select bit 3 /
richardv	0:b079fa4ed182	3434	#define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /!< COMP4 output polarity /
richardv	0:b079fa4ed182	3435	#define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /!< COMP4 hysteresis /
richardv	0:b079fa4ed182	3436	#define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /!< COMP4 hysteresis bit 0 /
richardv	0:b079fa4ed182	3437	#define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /!< COMP4 hysteresis bit 1 /
richardv	0:b079fa4ed182	3438	#define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /!< COMP4 blanking /
richardv	0:b079fa4ed182	3439	#define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /!< COMP4 blanking bit 0 /
richardv	0:b079fa4ed182	3440	#define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /!< COMP4 blanking bit 1 /
richardv	0:b079fa4ed182	3441	#define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /!< COMP4 blanking bit 2 /
richardv	0:b079fa4ed182	3442	#define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /!< COMP4 output level /
richardv	0:b079fa4ed182	3443	#define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /!< COMP4 lock /
richardv	0:b079fa4ed182	3444
richardv	0:b079fa4ed182	3445	/******************** Bit definition for COMP5_CSR register *************/
richardv	0:b079fa4ed182	3446	#define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /!< COMP5 enable /
richardv	0:b079fa4ed182	3447	#define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /!< COMP5 power mode /
richardv	0:b079fa4ed182	3448	#define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /!< COMP5 power mode bit 0 /
richardv	0:b079fa4ed182	3449	#define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /!< COMP5 power mode bit 1 /
richardv	0:b079fa4ed182	3450	#define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /!< COMP5 inverting input select /
richardv	0:b079fa4ed182	3451	#define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /!< COMP5 inverting input select bit 0 /
richardv	0:b079fa4ed182	3452	#define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /!< COMP5 inverting input select bit 1 /
richardv	0:b079fa4ed182	3453	#define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /!< COMP5 inverting input select bit 2 /
richardv	0:b079fa4ed182	3454	#define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /!< COMP5 non inverting input select /
richardv	0:b079fa4ed182	3455	#define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /!< COMP5 output select /
richardv	0:b079fa4ed182	3456	#define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /!< COMP5 output select bit 0 /
richardv	0:b079fa4ed182	3457	#define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /!< COMP5 output select bit 1 /
richardv	0:b079fa4ed182	3458	#define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /!< COMP5 output select bit 2 /
richardv	0:b079fa4ed182	3459	#define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /!< COMP5 output select bit 3 /
richardv	0:b079fa4ed182	3460	#define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /!< COMP5 output polarity /
richardv	0:b079fa4ed182	3461	#define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /!< COMP5 hysteresis /
richardv	0:b079fa4ed182	3462	#define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /!< COMP5 hysteresis bit 0 /
richardv	0:b079fa4ed182	3463	#define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /!< COMP5 hysteresis bit 1 /
richardv	0:b079fa4ed182	3464	#define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /!< COMP5 blanking /
richardv	0:b079fa4ed182	3465	#define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /!< COMP5 blanking bit 0 /
richardv	0:b079fa4ed182	3466	#define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /!< COMP5 blanking bit 1 /
richardv	0:b079fa4ed182	3467	#define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /!< COMP5 blanking bit 2 /
richardv	0:b079fa4ed182	3468	#define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /!< COMP5 output level /
richardv	0:b079fa4ed182	3469	#define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /!< COMP5 lock /
richardv	0:b079fa4ed182	3470
richardv	0:b079fa4ed182	3471	/******************** Bit definition for COMP6_CSR register *************/
richardv	0:b079fa4ed182	3472	#define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /!< COMP6 enable /
richardv	0:b079fa4ed182	3473	#define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /!< COMP6 power mode /
richardv	0:b079fa4ed182	3474	#define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /!< COMP6 power mode bit 0 /
richardv	0:b079fa4ed182	3475	#define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /!< COMP6 power mode bit 1 /
richardv	0:b079fa4ed182	3476	#define COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) /!< COMP6 inverting input select /
richardv	0:b079fa4ed182	3477	#define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /!< COMP6 inverting input select bit 0 /
richardv	0:b079fa4ed182	3478	#define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /!< COMP6 inverting input select bit 1 /
richardv	0:b079fa4ed182	3479	#define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /!< COMP6 inverting input select bit 2 /
richardv	0:b079fa4ed182	3480	#define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /!< COMP6 non inverting input select /
richardv	0:b079fa4ed182	3481	#define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /!< COMP6 window mode enable /
richardv	0:b079fa4ed182	3482	#define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /!< COMP6 output select /
richardv	0:b079fa4ed182	3483	#define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /!< COMP6 output select bit 0 /
richardv	0:b079fa4ed182	3484	#define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /!< COMP6 output select bit 1 /
richardv	0:b079fa4ed182	3485	#define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /!< COMP6 output select bit 2 /
richardv	0:b079fa4ed182	3486	#define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /!< COMP6 output select bit 3 /
richardv	0:b079fa4ed182	3487	#define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /!< COMP6 output polarity /
richardv	0:b079fa4ed182	3488	#define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /!< COMP6 hysteresis /
richardv	0:b079fa4ed182	3489	#define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /!< COMP6 hysteresis bit 0 /
richardv	0:b079fa4ed182	3490	#define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /!< COMP6 hysteresis bit 1 /
richardv	0:b079fa4ed182	3491	#define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /!< COMP6 blanking /
richardv	0:b079fa4ed182	3492	#define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /!< COMP6 blanking bit 0 /
richardv	0:b079fa4ed182	3493	#define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /!< COMP6 blanking bit 1 /
richardv	0:b079fa4ed182	3494	#define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /!< COMP6 blanking bit 2 /
richardv	0:b079fa4ed182	3495	#define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /!< COMP6 output level /
richardv	0:b079fa4ed182	3496	#define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /!< COMP6 lock /
richardv	0:b079fa4ed182	3497
richardv	0:b079fa4ed182	3498	/******************** Bit definition for COMP7_CSR register *************/
richardv	0:b079fa4ed182	3499	#define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /!< COMP7 enable /
richardv	0:b079fa4ed182	3500	#define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /!< COMP7 power mode /
richardv	0:b079fa4ed182	3501	#define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /!< COMP7 power mode bit 0 /
richardv	0:b079fa4ed182	3502	#define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /!< COMP7 power mode bit 1 /
richardv	0:b079fa4ed182	3503	#define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /!< COMP7 inverting input select /
richardv	0:b079fa4ed182	3504	#define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /!< COMP7 inverting input select bit 0 /
richardv	0:b079fa4ed182	3505	#define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /!< COMP7 inverting input select bit 1 /
richardv	0:b079fa4ed182	3506	#define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /!< COMP7 inverting input select bit 2 /
richardv	0:b079fa4ed182	3507	#define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /!< COMP7 non inverting input select /
richardv	0:b079fa4ed182	3508	#define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /!< COMP7 output select /
richardv	0:b079fa4ed182	3509	#define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /!< COMP7 output select bit 0 /
richardv	0:b079fa4ed182	3510	#define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /!< COMP7 output select bit 1 /
richardv	0:b079fa4ed182	3511	#define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /!< COMP7 output select bit 2 /
richardv	0:b079fa4ed182	3512	#define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /!< COMP7 output select bit 3 /
richardv	0:b079fa4ed182	3513	#define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /!< COMP7 output polarity /
richardv	0:b079fa4ed182	3514	#define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /!< COMP7 hysteresis /
richardv	0:b079fa4ed182	3515	#define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /!< COMP7 hysteresis bit 0 /
richardv	0:b079fa4ed182	3516	#define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /!< COMP7 hysteresis bit 1 /
richardv	0:b079fa4ed182	3517	#define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /!< COMP7 blanking /
richardv	0:b079fa4ed182	3518	#define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /!< COMP7 blanking bit 0 /
richardv	0:b079fa4ed182	3519	#define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /!< COMP7 blanking bit 1 /
richardv	0:b079fa4ed182	3520	#define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /!< COMP7 blanking bit 2 /
richardv	0:b079fa4ed182	3521	#define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /!< COMP7 output level /
richardv	0:b079fa4ed182	3522	#define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /!< COMP7 lock /
richardv	0:b079fa4ed182	3523
richardv	0:b079fa4ed182	3524	/******************** Bit definition for COMP_CSR register **************/
richardv	0:b079fa4ed182	3525	#define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /!< COMPx enable /
richardv	0:b079fa4ed182	3526	#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /!< COMP1 SW1 switch control /
richardv	0:b079fa4ed182	3527	#define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /!< COMPx power mode /
richardv	0:b079fa4ed182	3528	#define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /!< COMPx power mode bit 0 /
richardv	0:b079fa4ed182	3529	#define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /!< COMPx power mode bit 1 /
richardv	0:b079fa4ed182	3530	#define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /!< COMPx inverting input select /
richardv	0:b079fa4ed182	3531	#define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /!< COMPx inverting input select bit 0 /
richardv	0:b079fa4ed182	3532	#define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /!< COMPx inverting input select bit 1 /
richardv	0:b079fa4ed182	3533	#define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /!< COMPx inverting input select bit 2 /
richardv	0:b079fa4ed182	3534	#define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /!< COMPx non inverting input select /
richardv	0:b079fa4ed182	3535	#define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /!< COMPx window mode enable /
richardv	0:b079fa4ed182	3536	#define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /!< COMPx output select /
richardv	0:b079fa4ed182	3537	#define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /!< COMPx output select bit 0 /
richardv	0:b079fa4ed182	3538	#define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /!< COMPx output select bit 1 /
richardv	0:b079fa4ed182	3539	#define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /!< COMPx output select bit 2 /
richardv	0:b079fa4ed182	3540	#define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /!< COMPx output select bit 3 /
richardv	0:b079fa4ed182	3541	#define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /!< COMPx output polarity /
richardv	0:b079fa4ed182	3542	#define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /!< COMPx hysteresis /
richardv	0:b079fa4ed182	3543	#define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /!< COMPx hysteresis bit 0 /
richardv	0:b079fa4ed182	3544	#define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /!< COMPx hysteresis bit 1 /
richardv	0:b079fa4ed182	3545	#define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /!< COMPx blanking /
richardv	0:b079fa4ed182	3546	#define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /!< COMPx blanking bit 0 /
richardv	0:b079fa4ed182	3547	#define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /!< COMPx blanking bit 1 /
richardv	0:b079fa4ed182	3548	#define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /!< COMPx blanking bit 2 /
richardv	0:b079fa4ed182	3549	#define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /!< COMPx inverting input select bit 3 /
richardv	0:b079fa4ed182	3550	#define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /!< COMPx output level /
richardv	0:b079fa4ed182	3551	#define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /!< COMPx lock /
richardv	0:b079fa4ed182	3552
richardv	0:b079fa4ed182	3553	/******************************************************************************/
richardv	0:b079fa4ed182	3554	/* */
richardv	0:b079fa4ed182	3555	/* Operational Amplifier (OPAMP) */
richardv	0:b079fa4ed182	3556	/* */
richardv	0:b079fa4ed182	3557	/******************************************************************************/
richardv	0:b079fa4ed182	3558	/******************* Bit definition for OPAMP1_CSR register *************/
richardv	0:b079fa4ed182	3559	#define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /!< OPAMP1 enable /
richardv	0:b079fa4ed182	3560	#define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
richardv	0:b079fa4ed182	3561	#define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
richardv	0:b079fa4ed182	3562	#define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
richardv	0:b079fa4ed182	3563	#define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
richardv	0:b079fa4ed182	3564	#define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
richardv	0:b079fa4ed182	3565	#define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
richardv	0:b079fa4ed182	3566	#define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
richardv	0:b079fa4ed182	3567	#define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
richardv	0:b079fa4ed182	3568	#define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
richardv	0:b079fa4ed182	3569	#define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
richardv	0:b079fa4ed182	3570	#define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
richardv	0:b079fa4ed182	3571	#define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
richardv	0:b079fa4ed182	3572	#define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
richardv	0:b079fa4ed182	3573	#define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
richardv	0:b079fa4ed182	3574	#define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
richardv	0:b079fa4ed182	3575	#define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
richardv	0:b079fa4ed182	3576	#define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
richardv	0:b079fa4ed182	3577	#define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
richardv	0:b079fa4ed182	3578	#define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
richardv	0:b079fa4ed182	3579	#define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
richardv	0:b079fa4ed182	3580	#define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
richardv	0:b079fa4ed182	3581	#define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
richardv	0:b079fa4ed182	3582	#define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
richardv	0:b079fa4ed182	3583	#define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
richardv	0:b079fa4ed182	3584	#define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
richardv	0:b079fa4ed182	3585	#define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
richardv	0:b079fa4ed182	3586	#define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
richardv	0:b079fa4ed182	3587
richardv	0:b079fa4ed182	3588	/******************* Bit definition for OPAMP2_CSR register *************/
richardv	0:b079fa4ed182	3589	#define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /!< OPAMP2 enable /
richardv	0:b079fa4ed182	3590	#define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
richardv	0:b079fa4ed182	3591	#define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
richardv	0:b079fa4ed182	3592	#define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
richardv	0:b079fa4ed182	3593	#define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
richardv	0:b079fa4ed182	3594	#define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
richardv	0:b079fa4ed182	3595	#define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
richardv	0:b079fa4ed182	3596	#define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
richardv	0:b079fa4ed182	3597	#define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
richardv	0:b079fa4ed182	3598	#define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
richardv	0:b079fa4ed182	3599	#define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
richardv	0:b079fa4ed182	3600	#define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
richardv	0:b079fa4ed182	3601	#define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
richardv	0:b079fa4ed182	3602	#define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
richardv	0:b079fa4ed182	3603	#define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
richardv	0:b079fa4ed182	3604	#define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
richardv	0:b079fa4ed182	3605	#define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
richardv	0:b079fa4ed182	3606	#define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
richardv	0:b079fa4ed182	3607	#define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
richardv	0:b079fa4ed182	3608	#define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
richardv	0:b079fa4ed182	3609	#define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
richardv	0:b079fa4ed182	3610	#define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
richardv	0:b079fa4ed182	3611	#define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
richardv	0:b079fa4ed182	3612	#define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
richardv	0:b079fa4ed182	3613	#define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
richardv	0:b079fa4ed182	3614	#define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
richardv	0:b079fa4ed182	3615	#define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
richardv	0:b079fa4ed182	3616	#define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
richardv	0:b079fa4ed182	3617
richardv	0:b079fa4ed182	3618	/******************* Bit definition for OPAMP3_CSR register *************/
richardv	0:b079fa4ed182	3619	#define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /!< OPAMP3 enable /
richardv	0:b079fa4ed182	3620	#define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
richardv	0:b079fa4ed182	3621	#define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
richardv	0:b079fa4ed182	3622	#define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
richardv	0:b079fa4ed182	3623	#define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
richardv	0:b079fa4ed182	3624	#define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
richardv	0:b079fa4ed182	3625	#define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
richardv	0:b079fa4ed182	3626	#define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
richardv	0:b079fa4ed182	3627	#define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
richardv	0:b079fa4ed182	3628	#define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
richardv	0:b079fa4ed182	3629	#define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
richardv	0:b079fa4ed182	3630	#define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
richardv	0:b079fa4ed182	3631	#define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
richardv	0:b079fa4ed182	3632	#define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
richardv	0:b079fa4ed182	3633	#define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
richardv	0:b079fa4ed182	3634	#define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
richardv	0:b079fa4ed182	3635	#define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
richardv	0:b079fa4ed182	3636	#define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
richardv	0:b079fa4ed182	3637	#define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
richardv	0:b079fa4ed182	3638	#define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
richardv	0:b079fa4ed182	3639	#define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
richardv	0:b079fa4ed182	3640	#define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
richardv	0:b079fa4ed182	3641	#define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
richardv	0:b079fa4ed182	3642	#define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
richardv	0:b079fa4ed182	3643	#define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
richardv	0:b079fa4ed182	3644	#define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
richardv	0:b079fa4ed182	3645	#define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
richardv	0:b079fa4ed182	3646	#define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
richardv	0:b079fa4ed182	3647
richardv	0:b079fa4ed182	3648	/******************* Bit definition for OPAMP4_CSR register *************/
richardv	0:b079fa4ed182	3649	#define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /!< OPAMP4 enable /
richardv	0:b079fa4ed182	3650	#define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
richardv	0:b079fa4ed182	3651	#define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
richardv	0:b079fa4ed182	3652	#define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
richardv	0:b079fa4ed182	3653	#define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
richardv	0:b079fa4ed182	3654	#define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
richardv	0:b079fa4ed182	3655	#define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
richardv	0:b079fa4ed182	3656	#define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
richardv	0:b079fa4ed182	3657	#define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
richardv	0:b079fa4ed182	3658	#define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
richardv	0:b079fa4ed182	3659	#define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
richardv	0:b079fa4ed182	3660	#define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
richardv	0:b079fa4ed182	3661	#define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
richardv	0:b079fa4ed182	3662	#define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
richardv	0:b079fa4ed182	3663	#define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
richardv	0:b079fa4ed182	3664	#define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
richardv	0:b079fa4ed182	3665	#define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
richardv	0:b079fa4ed182	3666	#define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
richardv	0:b079fa4ed182	3667	#define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
richardv	0:b079fa4ed182	3668	#define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
richardv	0:b079fa4ed182	3669	#define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
richardv	0:b079fa4ed182	3670	#define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
richardv	0:b079fa4ed182	3671	#define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
richardv	0:b079fa4ed182	3672	#define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
richardv	0:b079fa4ed182	3673	#define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
richardv	0:b079fa4ed182	3674	#define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
richardv	0:b079fa4ed182	3675	#define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
richardv	0:b079fa4ed182	3676	#define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
richardv	0:b079fa4ed182	3677
richardv	0:b079fa4ed182	3678	/******************* Bit definition for OPAMPx_CSR register *************/
richardv	0:b079fa4ed182	3679	#define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /!< OPAMP enable /
richardv	0:b079fa4ed182	3680	#define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /!< Connect the internal references to the plus input of the OPAMPX /
richardv	0:b079fa4ed182	3681	#define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /!< Non inverting input selection /
richardv	0:b079fa4ed182	3682	#define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /!< Bit 0 /
richardv	0:b079fa4ed182	3683	#define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /!< Bit 1 /
richardv	0:b079fa4ed182	3684	#define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /!< Inverting input selection /
richardv	0:b079fa4ed182	3685	#define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /!< Bit 0 /
richardv	0:b079fa4ed182	3686	#define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /!< Bit 1 /
richardv	0:b079fa4ed182	3687	#define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /!< Timer-Controlled Mux mode enable /
richardv	0:b079fa4ed182	3688	#define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /!< Inverting input secondary selection /
richardv	0:b079fa4ed182	3689	#define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /!< Non inverting input secondary selection /
richardv	0:b079fa4ed182	3690	#define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /!< Bit 0 /
richardv	0:b079fa4ed182	3691	#define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /!< Bit 1 /
richardv	0:b079fa4ed182	3692	#define OPAMP_CSR_CALON ((uint32_t)0x00000800) /!< Calibration mode enable /
richardv	0:b079fa4ed182	3693	#define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /!< Calibration selection /
richardv	0:b079fa4ed182	3694	#define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /!< Bit 0 /
richardv	0:b079fa4ed182	3695	#define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /!< Bit 1 /
richardv	0:b079fa4ed182	3696	#define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /!< Gain in PGA mode /
richardv	0:b079fa4ed182	3697	#define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /!< Bit 0 /
richardv	0:b079fa4ed182	3698	#define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /!< Bit 1 /
richardv	0:b079fa4ed182	3699	#define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /!< Bit 2 /
richardv	0:b079fa4ed182	3700	#define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /!< Bit 3 /
richardv	0:b079fa4ed182	3701	#define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /!< User trimming enable /
richardv	0:b079fa4ed182	3702	#define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /!< Offset trimming value (PMOS) /
richardv	0:b079fa4ed182	3703	#define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /!< Offset trimming value (NMOS) /
richardv	0:b079fa4ed182	3704	#define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /!< It enables the switch to put out the internal reference /
richardv	0:b079fa4ed182	3705	#define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /!< OPAMP output status flag /
richardv	0:b079fa4ed182	3706	#define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /!< OPAMP lock /
richardv	0:b079fa4ed182	3707
richardv	0:b079fa4ed182	3708
richardv	0:b079fa4ed182	3709	/******************************************************************************/
richardv	0:b079fa4ed182	3710	/* */
richardv	0:b079fa4ed182	3711	/* Controller Area Network (CAN ) */
richardv	0:b079fa4ed182	3712	/* */
richardv	0:b079fa4ed182	3713	/******************************************************************************/
richardv	0:b079fa4ed182	3714	/!<CAN control and status registers /
richardv	0:b079fa4ed182	3715	/***************** Bit definition for CAN_MCR register ******************/
richardv	0:b079fa4ed182	3716	#define CAN_MCR_INRQ ((uint16_t)0x0001) /!<Initialization Request /
richardv	0:b079fa4ed182	3717	#define CAN_MCR_SLEEP ((uint16_t)0x0002) /!<Sleep Mode Request /
richardv	0:b079fa4ed182	3718	#define CAN_MCR_TXFP ((uint16_t)0x0004) /!<Transmit FIFO Priority /
richardv	0:b079fa4ed182	3719	#define CAN_MCR_RFLM ((uint16_t)0x0008) /!<Receive FIFO Locked Mode /
richardv	0:b079fa4ed182	3720	#define CAN_MCR_NART ((uint16_t)0x0010) /!<No Automatic Retransmission /
richardv	0:b079fa4ed182	3721	#define CAN_MCR_AWUM ((uint16_t)0x0020) /!<Automatic Wakeup Mode /
richardv	0:b079fa4ed182	3722	#define CAN_MCR_ABOM ((uint16_t)0x0040) /!<Automatic Bus-Off Management /
richardv	0:b079fa4ed182	3723	#define CAN_MCR_TTCM ((uint16_t)0x0080) /!<Time Triggered Communication Mode /
richardv	0:b079fa4ed182	3724	#define CAN_MCR_RESET ((uint16_t)0x8000) /!<bxCAN software master reset /
richardv	0:b079fa4ed182	3725
richardv	0:b079fa4ed182	3726	/***************** Bit definition for CAN_MSR register ******************/
richardv	0:b079fa4ed182	3727	#define CAN_MSR_INAK ((uint16_t)0x0001) /!<Initialization Acknowledge /
richardv	0:b079fa4ed182	3728	#define CAN_MSR_SLAK ((uint16_t)0x0002) /!<Sleep Acknowledge /
richardv	0:b079fa4ed182	3729	#define CAN_MSR_ERRI ((uint16_t)0x0004) /!<Error Interrupt /
richardv	0:b079fa4ed182	3730	#define CAN_MSR_WKUI ((uint16_t)0x0008) /!<Wakeup Interrupt /
richardv	0:b079fa4ed182	3731	#define CAN_MSR_SLAKI ((uint16_t)0x0010) /!<Sleep Acknowledge Interrupt /
richardv	0:b079fa4ed182	3732	#define CAN_MSR_TXM ((uint16_t)0x0100) /!<Transmit Mode /
richardv	0:b079fa4ed182	3733	#define CAN_MSR_RXM ((uint16_t)0x0200) /!<Receive Mode /
richardv	0:b079fa4ed182	3734	#define CAN_MSR_SAMP ((uint16_t)0x0400) /!<Last Sample Point /
richardv	0:b079fa4ed182	3735	#define CAN_MSR_RX ((uint16_t)0x0800) /!<CAN Rx Signal /
richardv	0:b079fa4ed182	3736
richardv	0:b079fa4ed182	3737	/***************** Bit definition for CAN_TSR register ******************/
richardv	0:b079fa4ed182	3738	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
richardv	0:b079fa4ed182	3739	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
richardv	0:b079fa4ed182	3740	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
richardv	0:b079fa4ed182	3741	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
richardv	0:b079fa4ed182	3742	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
richardv	0:b079fa4ed182	3743	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
richardv	0:b079fa4ed182	3744	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
richardv	0:b079fa4ed182	3745	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
richardv	0:b079fa4ed182	3746	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
richardv	0:b079fa4ed182	3747	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
richardv	0:b079fa4ed182	3748	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
richardv	0:b079fa4ed182	3749	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
richardv	0:b079fa4ed182	3750	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
richardv	0:b079fa4ed182	3751	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
richardv	0:b079fa4ed182	3752	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
richardv	0:b079fa4ed182	3753	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
richardv	0:b079fa4ed182	3754
richardv	0:b079fa4ed182	3755	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
richardv	0:b079fa4ed182	3756	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
richardv	0:b079fa4ed182	3757	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
richardv	0:b079fa4ed182	3758	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
richardv	0:b079fa4ed182	3759
richardv	0:b079fa4ed182	3760	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
richardv	0:b079fa4ed182	3761	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
richardv	0:b079fa4ed182	3762	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
richardv	0:b079fa4ed182	3763	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
richardv	0:b079fa4ed182	3764
richardv	0:b079fa4ed182	3765	/***************** Bit definition for CAN_RF0R register *****************/
richardv	0:b079fa4ed182	3766	#define CAN_RF0R_FMP0 ((uint8_t)0x03) /!<FIFO 0 Message Pending /
richardv	0:b079fa4ed182	3767	#define CAN_RF0R_FULL0 ((uint8_t)0x08) /!<FIFO 0 Full /
richardv	0:b079fa4ed182	3768	#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /!<FIFO 0 Overrun /
richardv	0:b079fa4ed182	3769	#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /!<Release FIFO 0 Output Mailbox /
richardv	0:b079fa4ed182	3770
richardv	0:b079fa4ed182	3771	/***************** Bit definition for CAN_RF1R register *****************/
richardv	0:b079fa4ed182	3772	#define CAN_RF1R_FMP1 ((uint8_t)0x03) /!<FIFO 1 Message Pending /
richardv	0:b079fa4ed182	3773	#define CAN_RF1R_FULL1 ((uint8_t)0x08) /!<FIFO 1 Full /
richardv	0:b079fa4ed182	3774	#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /!<FIFO 1 Overrun /
richardv	0:b079fa4ed182	3775	#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /!<Release FIFO 1 Output Mailbox /
richardv	0:b079fa4ed182	3776
richardv	0:b079fa4ed182	3777	/****************** Bit definition for CAN_IER register *****************/
richardv	0:b079fa4ed182	3778	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
richardv	0:b079fa4ed182	3779	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
richardv	0:b079fa4ed182	3780	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
richardv	0:b079fa4ed182	3781	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
richardv	0:b079fa4ed182	3782	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
richardv	0:b079fa4ed182	3783	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
richardv	0:b079fa4ed182	3784	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
richardv	0:b079fa4ed182	3785	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
richardv	0:b079fa4ed182	3786	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
richardv	0:b079fa4ed182	3787	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
richardv	0:b079fa4ed182	3788	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
richardv	0:b079fa4ed182	3789	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
richardv	0:b079fa4ed182	3790	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
richardv	0:b079fa4ed182	3791	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
richardv	0:b079fa4ed182	3792
richardv	0:b079fa4ed182	3793	/****************** Bit definition for CAN_ESR register *****************/
richardv	0:b079fa4ed182	3794	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
richardv	0:b079fa4ed182	3795	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
richardv	0:b079fa4ed182	3796	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
richardv	0:b079fa4ed182	3797
richardv	0:b079fa4ed182	3798	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
richardv	0:b079fa4ed182	3799	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
richardv	0:b079fa4ed182	3800	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
richardv	0:b079fa4ed182	3801	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
richardv	0:b079fa4ed182	3802
richardv	0:b079fa4ed182	3803	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
richardv	0:b079fa4ed182	3804	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
richardv	0:b079fa4ed182	3805
richardv	0:b079fa4ed182	3806	/***************** Bit definition for CAN_BTR register ******************/
richardv	0:b079fa4ed182	3807	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
richardv	0:b079fa4ed182	3808	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
richardv	0:b079fa4ed182	3809	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
richardv	0:b079fa4ed182	3810	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
richardv	0:b079fa4ed182	3811	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
richardv	0:b079fa4ed182	3812	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
richardv	0:b079fa4ed182	3813
richardv	0:b079fa4ed182	3814	/!<Mailbox registers /
richardv	0:b079fa4ed182	3815	/**************** Bit definition for CAN_TI0R register ******************/
richardv	0:b079fa4ed182	3816	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
richardv	0:b079fa4ed182	3817	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
richardv	0:b079fa4ed182	3818	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
richardv	0:b079fa4ed182	3819	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
richardv	0:b079fa4ed182	3820	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
richardv	0:b079fa4ed182	3821
richardv	0:b079fa4ed182	3822	/**************** Bit definition for CAN_TDT0R register *****************/
richardv	0:b079fa4ed182	3823	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
richardv	0:b079fa4ed182	3824	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
richardv	0:b079fa4ed182	3825	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
richardv	0:b079fa4ed182	3826
richardv	0:b079fa4ed182	3827	/**************** Bit definition for CAN_TDL0R register *****************/
richardv	0:b079fa4ed182	3828	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
richardv	0:b079fa4ed182	3829	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
richardv	0:b079fa4ed182	3830	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
richardv	0:b079fa4ed182	3831	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
richardv	0:b079fa4ed182	3832
richardv	0:b079fa4ed182	3833	/**************** Bit definition for CAN_TDH0R register *****************/
richardv	0:b079fa4ed182	3834	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
richardv	0:b079fa4ed182	3835	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
richardv	0:b079fa4ed182	3836	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
richardv	0:b079fa4ed182	3837	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
richardv	0:b079fa4ed182	3838
richardv	0:b079fa4ed182	3839	/***************** Bit definition for CAN_TI1R register *****************/
richardv	0:b079fa4ed182	3840	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
richardv	0:b079fa4ed182	3841	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
richardv	0:b079fa4ed182	3842	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
richardv	0:b079fa4ed182	3843	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
richardv	0:b079fa4ed182	3844	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
richardv	0:b079fa4ed182	3845
richardv	0:b079fa4ed182	3846	/***************** Bit definition for CAN_TDT1R register ****************/
richardv	0:b079fa4ed182	3847	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
richardv	0:b079fa4ed182	3848	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
richardv	0:b079fa4ed182	3849	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
richardv	0:b079fa4ed182	3850
richardv	0:b079fa4ed182	3851	/***************** Bit definition for CAN_TDL1R register ****************/
richardv	0:b079fa4ed182	3852	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
richardv	0:b079fa4ed182	3853	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
richardv	0:b079fa4ed182	3854	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
richardv	0:b079fa4ed182	3855	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
richardv	0:b079fa4ed182	3856
richardv	0:b079fa4ed182	3857	/***************** Bit definition for CAN_TDH1R register ****************/
richardv	0:b079fa4ed182	3858	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
richardv	0:b079fa4ed182	3859	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
richardv	0:b079fa4ed182	3860	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
richardv	0:b079fa4ed182	3861	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
richardv	0:b079fa4ed182	3862
richardv	0:b079fa4ed182	3863	/***************** Bit definition for CAN_TI2R register *****************/
richardv	0:b079fa4ed182	3864	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
richardv	0:b079fa4ed182	3865	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
richardv	0:b079fa4ed182	3866	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
richardv	0:b079fa4ed182	3867	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
richardv	0:b079fa4ed182	3868	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
richardv	0:b079fa4ed182	3869
richardv	0:b079fa4ed182	3870	/***************** Bit definition for CAN_TDT2R register ****************/
richardv	0:b079fa4ed182	3871	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
richardv	0:b079fa4ed182	3872	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
richardv	0:b079fa4ed182	3873	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
richardv	0:b079fa4ed182	3874
richardv	0:b079fa4ed182	3875	/***************** Bit definition for CAN_TDL2R register ****************/
richardv	0:b079fa4ed182	3876	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
richardv	0:b079fa4ed182	3877	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
richardv	0:b079fa4ed182	3878	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
richardv	0:b079fa4ed182	3879	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
richardv	0:b079fa4ed182	3880
richardv	0:b079fa4ed182	3881	/***************** Bit definition for CAN_TDH2R register ****************/
richardv	0:b079fa4ed182	3882	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
richardv	0:b079fa4ed182	3883	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
richardv	0:b079fa4ed182	3884	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
richardv	0:b079fa4ed182	3885	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
richardv	0:b079fa4ed182	3886
richardv	0:b079fa4ed182	3887	/***************** Bit definition for CAN_RI0R register *****************/
richardv	0:b079fa4ed182	3888	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
richardv	0:b079fa4ed182	3889	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
richardv	0:b079fa4ed182	3890	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
richardv	0:b079fa4ed182	3891	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
richardv	0:b079fa4ed182	3892
richardv	0:b079fa4ed182	3893	/***************** Bit definition for CAN_RDT0R register ****************/
richardv	0:b079fa4ed182	3894	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
richardv	0:b079fa4ed182	3895	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
richardv	0:b079fa4ed182	3896	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
richardv	0:b079fa4ed182	3897
richardv	0:b079fa4ed182	3898	/***************** Bit definition for CAN_RDL0R register ****************/
richardv	0:b079fa4ed182	3899	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
richardv	0:b079fa4ed182	3900	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
richardv	0:b079fa4ed182	3901	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
richardv	0:b079fa4ed182	3902	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
richardv	0:b079fa4ed182	3903
richardv	0:b079fa4ed182	3904	/***************** Bit definition for CAN_RDH0R register ****************/
richardv	0:b079fa4ed182	3905	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
richardv	0:b079fa4ed182	3906	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
richardv	0:b079fa4ed182	3907	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
richardv	0:b079fa4ed182	3908	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
richardv	0:b079fa4ed182	3909
richardv	0:b079fa4ed182	3910	/***************** Bit definition for CAN_RI1R register *****************/
richardv	0:b079fa4ed182	3911	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
richardv	0:b079fa4ed182	3912	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
richardv	0:b079fa4ed182	3913	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
richardv	0:b079fa4ed182	3914	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
richardv	0:b079fa4ed182	3915
richardv	0:b079fa4ed182	3916	/***************** Bit definition for CAN_RDT1R register ****************/
richardv	0:b079fa4ed182	3917	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
richardv	0:b079fa4ed182	3918	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
richardv	0:b079fa4ed182	3919	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
richardv	0:b079fa4ed182	3920
richardv	0:b079fa4ed182	3921	/***************** Bit definition for CAN_RDL1R register ****************/
richardv	0:b079fa4ed182	3922	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
richardv	0:b079fa4ed182	3923	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
richardv	0:b079fa4ed182	3924	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
richardv	0:b079fa4ed182	3925	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
richardv	0:b079fa4ed182	3926
richardv	0:b079fa4ed182	3927	/***************** Bit definition for CAN_RDH1R register ****************/
richardv	0:b079fa4ed182	3928	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
richardv	0:b079fa4ed182	3929	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
richardv	0:b079fa4ed182	3930	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
richardv	0:b079fa4ed182	3931	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
richardv	0:b079fa4ed182	3932
richardv	0:b079fa4ed182	3933	/!<CAN filter registers /
richardv	0:b079fa4ed182	3934	/***************** Bit definition for CAN_FMR register ******************/
richardv	0:b079fa4ed182	3935	#define CAN_FMR_FINIT ((uint8_t)0x01) /!<Filter Init Mode /
richardv	0:b079fa4ed182	3936
richardv	0:b079fa4ed182	3937	/***************** Bit definition for CAN_FM1R register *****************/
richardv	0:b079fa4ed182	3938	#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /!<Filter Mode /
richardv	0:b079fa4ed182	3939	#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /!<Filter Init Mode bit 0 /
richardv	0:b079fa4ed182	3940	#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /!<Filter Init Mode bit 1 /
richardv	0:b079fa4ed182	3941	#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /!<Filter Init Mode bit 2 /
richardv	0:b079fa4ed182	3942	#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /!<Filter Init Mode bit 3 /
richardv	0:b079fa4ed182	3943	#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /!<Filter Init Mode bit 4 /
richardv	0:b079fa4ed182	3944	#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /!<Filter Init Mode bit 5 /
richardv	0:b079fa4ed182	3945	#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /!<Filter Init Mode bit 6 /
richardv	0:b079fa4ed182	3946	#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /!<Filter Init Mode bit 7 /
richardv	0:b079fa4ed182	3947	#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /!<Filter Init Mode bit 8 /
richardv	0:b079fa4ed182	3948	#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /!<Filter Init Mode bit 9 /
richardv	0:b079fa4ed182	3949	#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /!<Filter Init Mode bit 10 /
richardv	0:b079fa4ed182	3950	#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /!<Filter Init Mode bit 11 /
richardv	0:b079fa4ed182	3951	#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /!<Filter Init Mode bit 12 /
richardv	0:b079fa4ed182	3952	#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /!<Filter Init Mode bit 13 /
richardv	0:b079fa4ed182	3953
richardv	0:b079fa4ed182	3954	/***************** Bit definition for CAN_FS1R register *****************/
richardv	0:b079fa4ed182	3955	#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /!<Filter Scale Configuration /
richardv	0:b079fa4ed182	3956	#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /!<Filter Scale Configuration bit 0 /
richardv	0:b079fa4ed182	3957	#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /!<Filter Scale Configuration bit 1 /
richardv	0:b079fa4ed182	3958	#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /!<Filter Scale Configuration bit 2 /
richardv	0:b079fa4ed182	3959	#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /!<Filter Scale Configuration bit 3 /
richardv	0:b079fa4ed182	3960	#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /!<Filter Scale Configuration bit 4 /
richardv	0:b079fa4ed182	3961	#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /!<Filter Scale Configuration bit 5 /
richardv	0:b079fa4ed182	3962	#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /!<Filter Scale Configuration bit 6 /
richardv	0:b079fa4ed182	3963	#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /!<Filter Scale Configuration bit 7 /
richardv	0:b079fa4ed182	3964	#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /!<Filter Scale Configuration bit 8 /
richardv	0:b079fa4ed182	3965	#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /!<Filter Scale Configuration bit 9 /
richardv	0:b079fa4ed182	3966	#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /!<Filter Scale Configuration bit 10 /
richardv	0:b079fa4ed182	3967	#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /!<Filter Scale Configuration bit 11 /
richardv	0:b079fa4ed182	3968	#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /!<Filter Scale Configuration bit 12 /
richardv	0:b079fa4ed182	3969	#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /!<Filter Scale Configuration bit 13 /
richardv	0:b079fa4ed182	3970
richardv	0:b079fa4ed182	3971	/**************** Bit definition for CAN_FFA1R register *****************/
richardv	0:b079fa4ed182	3972	#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /!<Filter FIFO Assignment /
richardv	0:b079fa4ed182	3973	#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /!<Filter FIFO Assignment for Filter 0 /
richardv	0:b079fa4ed182	3974	#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /!<Filter FIFO Assignment for Filter 1 /
richardv	0:b079fa4ed182	3975	#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /!<Filter FIFO Assignment for Filter 2 /
richardv	0:b079fa4ed182	3976	#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /!<Filter FIFO Assignment for Filter 3 /
richardv	0:b079fa4ed182	3977	#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /!<Filter FIFO Assignment for Filter 4 /
richardv	0:b079fa4ed182	3978	#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /!<Filter FIFO Assignment for Filter 5 /
richardv	0:b079fa4ed182	3979	#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /!<Filter FIFO Assignment for Filter 6 /
richardv	0:b079fa4ed182	3980	#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /!<Filter FIFO Assignment for Filter 7 /
richardv	0:b079fa4ed182	3981	#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /!<Filter FIFO Assignment for Filter 8 /
richardv	0:b079fa4ed182	3982	#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /!<Filter FIFO Assignment for Filter 9 /
richardv	0:b079fa4ed182	3983	#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /!<Filter FIFO Assignment for Filter 10 /
richardv	0:b079fa4ed182	3984	#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /!<Filter FIFO Assignment for Filter 11 /
richardv	0:b079fa4ed182	3985	#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /!<Filter FIFO Assignment for Filter 12 /
richardv	0:b079fa4ed182	3986	#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /!<Filter FIFO Assignment for Filter 13 /
richardv	0:b079fa4ed182	3987
richardv	0:b079fa4ed182	3988	/***************** Bit definition for CAN_FA1R register *****************/
richardv	0:b079fa4ed182	3989	#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /!<Filter Active /
richardv	0:b079fa4ed182	3990	#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /!<Filter 0 Active /
richardv	0:b079fa4ed182	3991	#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /!<Filter 1 Active /
richardv	0:b079fa4ed182	3992	#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /!<Filter 2 Active /
richardv	0:b079fa4ed182	3993	#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /!<Filter 3 Active /
richardv	0:b079fa4ed182	3994	#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /!<Filter 4 Active /
richardv	0:b079fa4ed182	3995	#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /!<Filter 5 Active /
richardv	0:b079fa4ed182	3996	#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /!<Filter 6 Active /
richardv	0:b079fa4ed182	3997	#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /!<Filter 7 Active /
richardv	0:b079fa4ed182	3998	#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /!<Filter 8 Active /
richardv	0:b079fa4ed182	3999	#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /!<Filter 9 Active /
richardv	0:b079fa4ed182	4000	#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /!<Filter 10 Active /
richardv	0:b079fa4ed182	4001	#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /!<Filter 11 Active /
richardv	0:b079fa4ed182	4002	#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /!<Filter 12 Active /
richardv	0:b079fa4ed182	4003	#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /!<Filter 13 Active /
richardv	0:b079fa4ed182	4004
richardv	0:b079fa4ed182	4005	/***************** Bit definition for CAN_F0R1 register *****************/
richardv	0:b079fa4ed182	4006	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4007	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4008	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4009	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4010	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4011	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4012	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4013	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4014	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4015	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4016	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4017	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4018	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4019	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4020	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4021	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4022	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4023	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4024	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4025	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4026	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4027	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4028	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4029	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4030	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4031	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4032	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4033	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4034	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4035	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4036	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4037	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4038
richardv	0:b079fa4ed182	4039	/***************** Bit definition for CAN_F1R1 register *****************/
richardv	0:b079fa4ed182	4040	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4041	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4042	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4043	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4044	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4045	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4046	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4047	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4048	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4049	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4050	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4051	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4052	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4053	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4054	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4055	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4056	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4057	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4058	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4059	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4060	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4061	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4062	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4063	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4064	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4065	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4066	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4067	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4068	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4069	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4070	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4071	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4072
richardv	0:b079fa4ed182	4073	/***************** Bit definition for CAN_F2R1 register *****************/
richardv	0:b079fa4ed182	4074	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4075	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4076	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4077	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4078	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4079	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4080	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4081	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4082	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4083	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4084	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4085	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4086	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4087	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4088	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4089	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4090	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4091	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4092	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4093	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4094	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4095	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4096	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4097	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4098	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4099	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4100	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4101	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4102	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4103	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4104	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4105	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4106
richardv	0:b079fa4ed182	4107	/***************** Bit definition for CAN_F3R1 register *****************/
richardv	0:b079fa4ed182	4108	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4109	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4110	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4111	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4112	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4113	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4114	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4115	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4116	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4117	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4118	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4119	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4120	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4121	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4122	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4123	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4124	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4125	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4126	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4127	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4128	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4129	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4130	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4131	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4132	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4133	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4134	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4135	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4136	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4137	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4138	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4139	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4140
richardv	0:b079fa4ed182	4141	/***************** Bit definition for CAN_F4R1 register *****************/
richardv	0:b079fa4ed182	4142	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4143	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4144	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4145	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4146	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4147	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4148	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4149	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4150	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4151	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4152	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4153	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4154	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4155	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4156	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4157	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4158	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4159	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4160	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4161	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4162	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4163	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4164	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4165	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4166	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4167	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4168	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4169	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4170	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4171	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4172	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4173	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4174
richardv	0:b079fa4ed182	4175	/***************** Bit definition for CAN_F5R1 register *****************/
richardv	0:b079fa4ed182	4176	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4177	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4178	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4179	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4180	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4181	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4182	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4183	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4184	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4185	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4186	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4187	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4188	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4189	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4190	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4191	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4192	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4193	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4194	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4195	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4196	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4197	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4198	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4199	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4200	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4201	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4202	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4203	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4204	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4205	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4206	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4207	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4208
richardv	0:b079fa4ed182	4209	/***************** Bit definition for CAN_F6R1 register *****************/
richardv	0:b079fa4ed182	4210	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4211	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4212	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4213	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4214	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4215	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4216	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4217	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4218	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4219	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4220	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4221	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4222	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4223	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4224	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4225	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4226	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4227	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4228	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4229	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4230	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4231	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4232	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4233	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4234	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4235	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4236	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4237	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4238	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4239	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4240	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4241	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4242
richardv	0:b079fa4ed182	4243	/***************** Bit definition for CAN_F7R1 register *****************/
richardv	0:b079fa4ed182	4244	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4245	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4246	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4247	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4248	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4249	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4250	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4251	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4252	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4253	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4254	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4255	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4256	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4257	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4258	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4259	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4260	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4261	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4262	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4263	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4264	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4265	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4266	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4267	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4268	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4269	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4270	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4271	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4272	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4273	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4274	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4275	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4276
richardv	0:b079fa4ed182	4277	/***************** Bit definition for CAN_F8R1 register *****************/
richardv	0:b079fa4ed182	4278	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4279	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4280	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4281	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4282	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4283	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4284	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4285	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4286	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4287	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4288	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4289	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4290	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4291	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4292	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4293	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4294	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4295	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4296	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4297	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4298	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4299	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4300	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4301	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4302	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4303	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4304	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4305	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4306	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4307	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4308	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4309	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4310
richardv	0:b079fa4ed182	4311	/***************** Bit definition for CAN_F9R1 register *****************/
richardv	0:b079fa4ed182	4312	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4313	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4314	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4315	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4316	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4317	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4318	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4319	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4320	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4321	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4322	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4323	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4324	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4325	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4326	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4327	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4328	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4329	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4330	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4331	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4332	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4333	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4334	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4335	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4336	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4337	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4338	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4339	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4340	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4341	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4342	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4343	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4344
richardv	0:b079fa4ed182	4345	/***************** Bit definition for CAN_F10R1 register ****************/
richardv	0:b079fa4ed182	4346	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4347	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4348	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4349	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4350	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4351	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4352	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4353	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4354	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4355	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4356	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4357	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4358	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4359	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4360	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4361	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4362	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4363	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4364	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4365	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4366	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4367	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4368	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4369	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4370	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4371	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4372	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4373	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4374	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4375	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4376	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4377	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4378
richardv	0:b079fa4ed182	4379	/***************** Bit definition for CAN_F11R1 register ****************/
richardv	0:b079fa4ed182	4380	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4381	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4382	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4383	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4384	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4385	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4386	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4387	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4388	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4389	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4390	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4391	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4392	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4393	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4394	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4395	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4396	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4397	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4398	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4399	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4400	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4401	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4402	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4403	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4404	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4405	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4406	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4407	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4408	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4409	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4410	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4411	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4412
richardv	0:b079fa4ed182	4413	/***************** Bit definition for CAN_F12R1 register ****************/
richardv	0:b079fa4ed182	4414	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4415	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4416	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4417	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4418	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4419	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4420	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4421	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4422	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4423	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4424	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4425	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4426	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4427	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4428	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4429	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4430	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4431	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4432	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4433	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4434	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4435	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4436	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4437	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4438	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4439	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4440	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4441	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4442	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4443	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4444	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4445	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4446
richardv	0:b079fa4ed182	4447	/***************** Bit definition for CAN_F13R1 register ****************/
richardv	0:b079fa4ed182	4448	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4449	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4450	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4451	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4452	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4453	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4454	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4455	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4456	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4457	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4458	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4459	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4460	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4461	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4462	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4463	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4464	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4465	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4466	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4467	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4468	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4469	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4470	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4471	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4472	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4473	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4474	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4475	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4476	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4477	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4478	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4479	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4480
richardv	0:b079fa4ed182	4481	/***************** Bit definition for CAN_F0R2 register *****************/
richardv	0:b079fa4ed182	4482	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4483	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4484	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4485	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4486	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4487	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4488	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4489	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4490	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4491	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4492	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4493	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4494	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4495	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4496	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4497	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4498	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4499	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4500	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4501	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4502	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4503	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4504	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4505	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4506	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4507	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4508	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4509	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4510	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4511	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4512	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4513	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4514
richardv	0:b079fa4ed182	4515	/***************** Bit definition for CAN_F1R2 register *****************/
richardv	0:b079fa4ed182	4516	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4517	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4518	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4519	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4520	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4521	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4522	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4523	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4524	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4525	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4526	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4527	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4528	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4529	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4530	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4531	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4532	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4533	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4534	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4535	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4536	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4537	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4538	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4539	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4540	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4541	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4542	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4543	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4544	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4545	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4546	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4547	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4548
richardv	0:b079fa4ed182	4549	/***************** Bit definition for CAN_F2R2 register *****************/
richardv	0:b079fa4ed182	4550	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4551	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4552	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4553	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4554	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4555	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4556	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4557	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4558	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4559	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4560	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4561	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4562	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4563	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4564	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4565	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4566	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4567	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4568	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4569	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4570	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4571	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4572	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4573	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4574	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4575	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4576	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4577	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4578	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4579	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4580	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4581	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4582
richardv	0:b079fa4ed182	4583	/***************** Bit definition for CAN_F3R2 register *****************/
richardv	0:b079fa4ed182	4584	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4585	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4586	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4587	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4588	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4589	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4590	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4591	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4592	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4593	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4594	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4595	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4596	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4597	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4598	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4599	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4600	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4601	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4602	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4603	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4604	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4605	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4606	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4607	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4608	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4609	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4610	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4611	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4612	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4613	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4614	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4615	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4616
richardv	0:b079fa4ed182	4617	/***************** Bit definition for CAN_F4R2 register *****************/
richardv	0:b079fa4ed182	4618	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4619	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4620	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4621	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4622	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4623	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4624	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4625	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4626	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4627	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4628	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4629	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4630	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4631	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4632	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4633	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4634	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4635	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4636	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4637	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4638	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4639	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4640	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4641	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4642	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4643	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4644	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4645	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4646	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4647	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4648	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4649	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4650
richardv	0:b079fa4ed182	4651	/***************** Bit definition for CAN_F5R2 register *****************/
richardv	0:b079fa4ed182	4652	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4653	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4654	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4655	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4656	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4657	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4658	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4659	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4660	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4661	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4662	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4663	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4664	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4665	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4666	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4667	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4668	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4669	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4670	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4671	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4672	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4673	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4674	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4675	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4676	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4677	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4678	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4679	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4680	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4681	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4682	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4683	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4684
richardv	0:b079fa4ed182	4685	/***************** Bit definition for CAN_F6R2 register *****************/
richardv	0:b079fa4ed182	4686	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4687	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4688	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4689	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4690	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4691	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4692	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4693	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4694	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4695	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4696	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4697	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4698	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4699	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4700	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4701	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4702	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4703	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4704	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4705	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4706	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4707	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4708	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4709	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4710	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4711	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4712	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4713	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4714	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4715	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4716	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4717	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4718
richardv	0:b079fa4ed182	4719	/***************** Bit definition for CAN_F7R2 register *****************/
richardv	0:b079fa4ed182	4720	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4721	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4722	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4723	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4724	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4725	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4726	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4727	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4728	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4729	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4730	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4731	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4732	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4733	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4734	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4735	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4736	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4737	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4738	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4739	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4740	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4741	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4742	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4743	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4744	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4745	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4746	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4747	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4748	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4749	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4750	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4751	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4752
richardv	0:b079fa4ed182	4753	/***************** Bit definition for CAN_F8R2 register *****************/
richardv	0:b079fa4ed182	4754	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4755	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4756	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4757	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4758	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4759	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4760	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4761	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4762	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4763	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4764	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4765	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4766	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4767	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4768	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4769	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4770	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4771	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4772	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4773	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4774	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4775	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4776	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4777	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4778	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4779	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4780	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4781	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4782	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4783	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4784	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4785	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4786
richardv	0:b079fa4ed182	4787	/***************** Bit definition for CAN_F9R2 register *****************/
richardv	0:b079fa4ed182	4788	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4789	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4790	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4791	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4792	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4793	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4794	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4795	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4796	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4797	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4798	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4799	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4800	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4801	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4802	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4803	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4804	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4805	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4806	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4807	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4808	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4809	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4810	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4811	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4812	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4813	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4814	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4815	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4816	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4817	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4818	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4819	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4820
richardv	0:b079fa4ed182	4821	/***************** Bit definition for CAN_F10R2 register ****************/
richardv	0:b079fa4ed182	4822	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4823	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4824	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4825	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4826	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4827	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4828	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4829	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4830	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4831	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4832	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4833	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4834	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4835	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4836	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4837	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4838	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4839	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4840	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4841	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4842	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4843	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4844	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4845	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4846	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4847	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4848	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4849	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4850	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4851	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4852	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4853	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4854
richardv	0:b079fa4ed182	4855	/***************** Bit definition for CAN_F11R2 register ****************/
richardv	0:b079fa4ed182	4856	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4857	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4858	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4859	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4860	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4861	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4862	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4863	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4864	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4865	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4866	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4867	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4868	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4869	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4870	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4871	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4872	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4873	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4874	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4875	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4876	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4877	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4878	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4879	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4880	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4881	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4882	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4883	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4884	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4885	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4886	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4887	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4888
richardv	0:b079fa4ed182	4889	/***************** Bit definition for CAN_F12R2 register ****************/
richardv	0:b079fa4ed182	4890	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4891	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4892	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4893	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4894	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4895	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4896	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4897	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4898	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4899	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4900	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4901	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4902	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4903	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4904	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4905	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4906	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4907	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4908	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4909	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4910	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4911	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4912	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4913	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4914	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4915	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4916	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4917	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4918	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4919	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4920	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4921	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4922
richardv	0:b079fa4ed182	4923	/***************** Bit definition for CAN_F13R2 register ****************/
richardv	0:b079fa4ed182	4924	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
richardv	0:b079fa4ed182	4925	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
richardv	0:b079fa4ed182	4926	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
richardv	0:b079fa4ed182	4927	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
richardv	0:b079fa4ed182	4928	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
richardv	0:b079fa4ed182	4929	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
richardv	0:b079fa4ed182	4930	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
richardv	0:b079fa4ed182	4931	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
richardv	0:b079fa4ed182	4932	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
richardv	0:b079fa4ed182	4933	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
richardv	0:b079fa4ed182	4934	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
richardv	0:b079fa4ed182	4935	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
richardv	0:b079fa4ed182	4936	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
richardv	0:b079fa4ed182	4937	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
richardv	0:b079fa4ed182	4938	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
richardv	0:b079fa4ed182	4939	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
richardv	0:b079fa4ed182	4940	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
richardv	0:b079fa4ed182	4941	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
richardv	0:b079fa4ed182	4942	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
richardv	0:b079fa4ed182	4943	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
richardv	0:b079fa4ed182	4944	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
richardv	0:b079fa4ed182	4945	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
richardv	0:b079fa4ed182	4946	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
richardv	0:b079fa4ed182	4947	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
richardv	0:b079fa4ed182	4948	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
richardv	0:b079fa4ed182	4949	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
richardv	0:b079fa4ed182	4950	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
richardv	0:b079fa4ed182	4951	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
richardv	0:b079fa4ed182	4952	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
richardv	0:b079fa4ed182	4953	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
richardv	0:b079fa4ed182	4954	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
richardv	0:b079fa4ed182	4955	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
richardv	0:b079fa4ed182	4956
richardv	0:b079fa4ed182	4957	/******************************************************************************/
richardv	0:b079fa4ed182	4958	/* */
richardv	0:b079fa4ed182	4959	/* CRC calculation unit (CRC) */
richardv	0:b079fa4ed182	4960	/* */
richardv	0:b079fa4ed182	4961	/******************************************************************************/
richardv	0:b079fa4ed182	4962	/***************** Bit definition for CRC_DR register *******************/
richardv	0:b079fa4ed182	4963	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
richardv	0:b079fa4ed182	4964
richardv	0:b079fa4ed182	4965	/***************** Bit definition for CRC_IDR register ******************/
richardv	0:b079fa4ed182	4966	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
richardv	0:b079fa4ed182	4967
richardv	0:b079fa4ed182	4968	/****************** Bit definition for CRC_CR register ******************/
richardv	0:b079fa4ed182	4969	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
richardv	0:b079fa4ed182	4970	#define CRC_CR_POLSIZE ((uint32_t)0x00000018) /!< Polynomial size bits /
richardv	0:b079fa4ed182	4971	#define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /!< Polynomial size bit 0 /
richardv	0:b079fa4ed182	4972	#define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /!< Polynomial size bit 1 /
richardv	0:b079fa4ed182	4973	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
richardv	0:b079fa4ed182	4974	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< Bit 0 /
richardv	0:b079fa4ed182	4975	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< Bit 1 /
richardv	0:b079fa4ed182	4976	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
richardv	0:b079fa4ed182	4977
richardv	0:b079fa4ed182	4978	/***************** Bit definition for CRC_INIT register *****************/
richardv	0:b079fa4ed182	4979	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
richardv	0:b079fa4ed182	4980
richardv	0:b079fa4ed182	4981	/***************** Bit definition for CRC_POL register ******************/
richardv	0:b079fa4ed182	4982	#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /!< Coefficients of the polynomial /
richardv	0:b079fa4ed182	4983	/******************************************************************************/
richardv	0:b079fa4ed182	4984	/* */
richardv	0:b079fa4ed182	4985	/* Digital to Analog Converter (DAC) */
richardv	0:b079fa4ed182	4986	/* */
richardv	0:b079fa4ed182	4987	/******************************************************************************/
richardv	0:b079fa4ed182	4988	/****************** Bit definition for DAC_CR register ******************/
richardv	0:b079fa4ed182	4989	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
richardv	0:b079fa4ed182	4990	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
richardv	0:b079fa4ed182	4991	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
richardv	0:b079fa4ed182	4992
richardv	0:b079fa4ed182	4993	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
richardv	0:b079fa4ed182	4994	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
richardv	0:b079fa4ed182	4995	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
richardv	0:b079fa4ed182	4996	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
richardv	0:b079fa4ed182	4997
richardv	0:b079fa4ed182	4998	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) /
richardv	0:b079fa4ed182	4999	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
richardv	0:b079fa4ed182	5000	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
richardv	0:b079fa4ed182	5001
richardv	0:b079fa4ed182	5002	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
richardv	0:b079fa4ed182	5003	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
richardv	0:b079fa4ed182	5004	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
richardv	0:b079fa4ed182	5005	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
richardv	0:b079fa4ed182	5006	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
richardv	0:b079fa4ed182	5007
richardv	0:b079fa4ed182	5008	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
richardv	0:b079fa4ed182	5009	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
richardv	0:b079fa4ed182	5010	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
richardv	0:b079fa4ed182	5011	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
richardv	0:b079fa4ed182	5012
richardv	0:b079fa4ed182	5013	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
richardv	0:b079fa4ed182	5014	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
richardv	0:b079fa4ed182	5015	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
richardv	0:b079fa4ed182	5016	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
richardv	0:b079fa4ed182	5017
richardv	0:b079fa4ed182	5018	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
richardv	0:b079fa4ed182	5019	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
richardv	0:b079fa4ed182	5020	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
richardv	0:b079fa4ed182	5021
richardv	0:b079fa4ed182	5022	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
richardv	0:b079fa4ed182	5023	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
richardv	0:b079fa4ed182	5024	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
richardv	0:b079fa4ed182	5025	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
richardv	0:b079fa4ed182	5026	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
richardv	0:b079fa4ed182	5027
richardv	0:b079fa4ed182	5028	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
richardv	0:b079fa4ed182	5029
richardv	0:b079fa4ed182	5030	/*************** Bit definition for DAC_SWTRIGR register ****************/
richardv	0:b079fa4ed182	5031	#define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /!< DAC channel1 software trigger /
richardv	0:b079fa4ed182	5032	#define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /!< DAC channel2 software trigger /
richardv	0:b079fa4ed182	5033
richardv	0:b079fa4ed182	5034	/*************** Bit definition for DAC_DHR12R1 register ****************/
richardv	0:b079fa4ed182	5035	#define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /!< DAC channel1 12-bit Right aligned data /
richardv	0:b079fa4ed182	5036
richardv	0:b079fa4ed182	5037	/*************** Bit definition for DAC_DHR12L1 register ****************/
richardv	0:b079fa4ed182	5038	#define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /!< DAC channel1 12-bit Left aligned data /
richardv	0:b079fa4ed182	5039
richardv	0:b079fa4ed182	5040	/**************** Bit definition for DAC_DHR8R1 register ****************/
richardv	0:b079fa4ed182	5041	#define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /!< DAC channel1 8-bit Right aligned data /
richardv	0:b079fa4ed182	5042
richardv	0:b079fa4ed182	5043	/*************** Bit definition for DAC_DHR12R2 register ****************/
richardv	0:b079fa4ed182	5044	#define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /!< DAC channel2 12-bit Right aligned data /
richardv	0:b079fa4ed182	5045
richardv	0:b079fa4ed182	5046	/*************** Bit definition for DAC_DHR12L2 register ****************/
richardv	0:b079fa4ed182	5047	#define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /!< DAC channel2 12-bit Left aligned data /
richardv	0:b079fa4ed182	5048
richardv	0:b079fa4ed182	5049	/**************** Bit definition for DAC_DHR8R2 register ****************/
richardv	0:b079fa4ed182	5050	#define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /!< DAC channel2 8-bit Right aligned data /
richardv	0:b079fa4ed182	5051
richardv	0:b079fa4ed182	5052	/*************** Bit definition for DAC_DHR12RD register ****************/
richardv	0:b079fa4ed182	5053	#define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /!< DAC channel1 12-bit Right aligned data /
richardv	0:b079fa4ed182	5054	#define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /!< DAC channel2 12-bit Right aligned data /
richardv	0:b079fa4ed182	5055
richardv	0:b079fa4ed182	5056	/*************** Bit definition for DAC_DHR12LD register ****************/
richardv	0:b079fa4ed182	5057	#define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /!< DAC channel1 12-bit Left aligned data /
richardv	0:b079fa4ed182	5058	#define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /!< DAC channel2 12-bit Left aligned data /
richardv	0:b079fa4ed182	5059
richardv	0:b079fa4ed182	5060	/**************** Bit definition for DAC_DHR8RD register ****************/
richardv	0:b079fa4ed182	5061	#define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /!< DAC channel1 8-bit Right aligned data /
richardv	0:b079fa4ed182	5062	#define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /!< DAC channel2 8-bit Right aligned data /
richardv	0:b079fa4ed182	5063
richardv	0:b079fa4ed182	5064	/***************** Bit definition for DAC_DOR1 register *****************/
richardv	0:b079fa4ed182	5065	#define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /!< DAC channel1 data output /
richardv	0:b079fa4ed182	5066
richardv	0:b079fa4ed182	5067	/***************** Bit definition for DAC_DOR2 register *****************/
richardv	0:b079fa4ed182	5068	#define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /!< DAC channel2 data output /
richardv	0:b079fa4ed182	5069
richardv	0:b079fa4ed182	5070	/****************** Bit definition for DAC_SR register ******************/
richardv	0:b079fa4ed182	5071	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun flag /
richardv	0:b079fa4ed182	5072	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun flag /
richardv	0:b079fa4ed182	5073
richardv	0:b079fa4ed182	5074	/******************************************************************************/
richardv	0:b079fa4ed182	5075	/* */
richardv	0:b079fa4ed182	5076	/* Debug MCU (DBGMCU) */
richardv	0:b079fa4ed182	5077	/* */
richardv	0:b079fa4ed182	5078	/******************************************************************************/
richardv	0:b079fa4ed182	5079	/****************** Bit definition for DBGMCU_IDCODE register ***********/
richardv	0:b079fa4ed182	5080	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
richardv	0:b079fa4ed182	5081	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
richardv	0:b079fa4ed182	5082
richardv	0:b079fa4ed182	5083	/****************** Bit definition for DBGMCU_CR register ***************/
richardv	0:b079fa4ed182	5084	#define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5085	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5086	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5087	#define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5088
richardv	0:b079fa4ed182	5089	#define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
richardv	0:b079fa4ed182	5090	#define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/!<Bit 0 /
richardv	0:b079fa4ed182	5091	#define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/!<Bit 1 /
richardv	0:b079fa4ed182	5092
richardv	0:b079fa4ed182	5093	/****************** Bit definition for DBGMCU_APB1_FZ register **********/
richardv	0:b079fa4ed182	5094	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5095	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5096	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5097	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5098	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5099	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5100	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5101	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5102	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	5103	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	5104	#define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	5105
richardv	0:b079fa4ed182	5106	/****************** Bit definition for DBGMCU_APB2_FZ register **********/
richardv	0:b079fa4ed182	5107	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5108	#define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5109	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5110	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5111	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5112
richardv	0:b079fa4ed182	5113	/******************************************************************************/
richardv	0:b079fa4ed182	5114	/* */
richardv	0:b079fa4ed182	5115	/* DMA Controller (DMA) */
richardv	0:b079fa4ed182	5116	/* */
richardv	0:b079fa4ed182	5117	/******************************************************************************/
richardv	0:b079fa4ed182	5118	/***************** Bit definition for DMA_ISR register ******************/
richardv	0:b079fa4ed182	5119	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
richardv	0:b079fa4ed182	5120	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
richardv	0:b079fa4ed182	5121	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
richardv	0:b079fa4ed182	5122	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
richardv	0:b079fa4ed182	5123	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
richardv	0:b079fa4ed182	5124	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
richardv	0:b079fa4ed182	5125	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
richardv	0:b079fa4ed182	5126	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
richardv	0:b079fa4ed182	5127	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
richardv	0:b079fa4ed182	5128	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
richardv	0:b079fa4ed182	5129	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
richardv	0:b079fa4ed182	5130	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
richardv	0:b079fa4ed182	5131	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
richardv	0:b079fa4ed182	5132	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
richardv	0:b079fa4ed182	5133	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
richardv	0:b079fa4ed182	5134	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
richardv	0:b079fa4ed182	5135	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
richardv	0:b079fa4ed182	5136	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
richardv	0:b079fa4ed182	5137	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
richardv	0:b079fa4ed182	5138	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
richardv	0:b079fa4ed182	5139	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag /
richardv	0:b079fa4ed182	5140	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag /
richardv	0:b079fa4ed182	5141	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag /
richardv	0:b079fa4ed182	5142	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag /
richardv	0:b079fa4ed182	5143	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag /
richardv	0:b079fa4ed182	5144	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag /
richardv	0:b079fa4ed182	5145	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag /
richardv	0:b079fa4ed182	5146	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag /
richardv	0:b079fa4ed182	5147
richardv	0:b079fa4ed182	5148	/***************** Bit definition for DMA_IFCR register *****************/
richardv	0:b079fa4ed182	5149	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
richardv	0:b079fa4ed182	5150	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
richardv	0:b079fa4ed182	5151	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
richardv	0:b079fa4ed182	5152	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
richardv	0:b079fa4ed182	5153	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
richardv	0:b079fa4ed182	5154	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
richardv	0:b079fa4ed182	5155	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
richardv	0:b079fa4ed182	5156	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
richardv	0:b079fa4ed182	5157	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
richardv	0:b079fa4ed182	5158	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
richardv	0:b079fa4ed182	5159	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
richardv	0:b079fa4ed182	5160	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
richardv	0:b079fa4ed182	5161	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
richardv	0:b079fa4ed182	5162	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
richardv	0:b079fa4ed182	5163	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
richardv	0:b079fa4ed182	5164	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
richardv	0:b079fa4ed182	5165	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
richardv	0:b079fa4ed182	5166	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
richardv	0:b079fa4ed182	5167	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
richardv	0:b079fa4ed182	5168	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
richardv	0:b079fa4ed182	5169	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear /
richardv	0:b079fa4ed182	5170	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear /
richardv	0:b079fa4ed182	5171	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear /
richardv	0:b079fa4ed182	5172	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear /
richardv	0:b079fa4ed182	5173	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear /
richardv	0:b079fa4ed182	5174	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear /
richardv	0:b079fa4ed182	5175	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear /
richardv	0:b079fa4ed182	5176	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear /
richardv	0:b079fa4ed182	5177
richardv	0:b079fa4ed182	5178	/***************** Bit definition for DMA_CCR register ******************/
richardv	0:b079fa4ed182	5179	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
richardv	0:b079fa4ed182	5180	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
richardv	0:b079fa4ed182	5181	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
richardv	0:b079fa4ed182	5182	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
richardv	0:b079fa4ed182	5183	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
richardv	0:b079fa4ed182	5184	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
richardv	0:b079fa4ed182	5185	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
richardv	0:b079fa4ed182	5186	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
richardv	0:b079fa4ed182	5187
richardv	0:b079fa4ed182	5188	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
richardv	0:b079fa4ed182	5189	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
richardv	0:b079fa4ed182	5190	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
richardv	0:b079fa4ed182	5191
richardv	0:b079fa4ed182	5192	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
richardv	0:b079fa4ed182	5193	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
richardv	0:b079fa4ed182	5194	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
richardv	0:b079fa4ed182	5195
richardv	0:b079fa4ed182	5196	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
richardv	0:b079fa4ed182	5197	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
richardv	0:b079fa4ed182	5198	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
richardv	0:b079fa4ed182	5199
richardv	0:b079fa4ed182	5200	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
richardv	0:b079fa4ed182	5201
richardv	0:b079fa4ed182	5202	/**************** Bit definition for DMA_CNDTR register *****************/
richardv	0:b079fa4ed182	5203	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
richardv	0:b079fa4ed182	5204
richardv	0:b079fa4ed182	5205	/**************** Bit definition for DMA_CPAR register ******************/
richardv	0:b079fa4ed182	5206	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
richardv	0:b079fa4ed182	5207
richardv	0:b079fa4ed182	5208	/**************** Bit definition for DMA_CMAR register ******************/
richardv	0:b079fa4ed182	5209	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
richardv	0:b079fa4ed182	5210
richardv	0:b079fa4ed182	5211	/******************************************************************************/
richardv	0:b079fa4ed182	5212	/* */
richardv	0:b079fa4ed182	5213	/* External Interrupt/Event Controller (EXTI) */
richardv	0:b079fa4ed182	5214	/* */
richardv	0:b079fa4ed182	5215	/******************************************************************************/
richardv	0:b079fa4ed182	5216	/***************** Bit definition for EXTI_IMR register *****************/
richardv	0:b079fa4ed182	5217	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
richardv	0:b079fa4ed182	5218	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
richardv	0:b079fa4ed182	5219	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
richardv	0:b079fa4ed182	5220	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
richardv	0:b079fa4ed182	5221	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
richardv	0:b079fa4ed182	5222	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
richardv	0:b079fa4ed182	5223	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
richardv	0:b079fa4ed182	5224	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
richardv	0:b079fa4ed182	5225	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
richardv	0:b079fa4ed182	5226	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
richardv	0:b079fa4ed182	5227	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
richardv	0:b079fa4ed182	5228	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
richardv	0:b079fa4ed182	5229	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
richardv	0:b079fa4ed182	5230	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
richardv	0:b079fa4ed182	5231	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
richardv	0:b079fa4ed182	5232	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
richardv	0:b079fa4ed182	5233	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
richardv	0:b079fa4ed182	5234	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
richardv	0:b079fa4ed182	5235	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
richardv	0:b079fa4ed182	5236	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
richardv	0:b079fa4ed182	5237	#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
richardv	0:b079fa4ed182	5238	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
richardv	0:b079fa4ed182	5239	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
richardv	0:b079fa4ed182	5240	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
richardv	0:b079fa4ed182	5241	#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /!< Interrupt Mask on line 24 /
richardv	0:b079fa4ed182	5242	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
richardv	0:b079fa4ed182	5243	#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /!< Interrupt Mask on line 26 /
richardv	0:b079fa4ed182	5244	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
richardv	0:b079fa4ed182	5245	#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /!< Interrupt Mask on line 28 /
richardv	0:b079fa4ed182	5246
richardv	0:b079fa4ed182	5247	/***************** Bit definition for EXTI_EMR register *****************/
richardv	0:b079fa4ed182	5248	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
richardv	0:b079fa4ed182	5249	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
richardv	0:b079fa4ed182	5250	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
richardv	0:b079fa4ed182	5251	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
richardv	0:b079fa4ed182	5252	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
richardv	0:b079fa4ed182	5253	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
richardv	0:b079fa4ed182	5254	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
richardv	0:b079fa4ed182	5255	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
richardv	0:b079fa4ed182	5256	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
richardv	0:b079fa4ed182	5257	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
richardv	0:b079fa4ed182	5258	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
richardv	0:b079fa4ed182	5259	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
richardv	0:b079fa4ed182	5260	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
richardv	0:b079fa4ed182	5261	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
richardv	0:b079fa4ed182	5262	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
richardv	0:b079fa4ed182	5263	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
richardv	0:b079fa4ed182	5264	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
richardv	0:b079fa4ed182	5265	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
richardv	0:b079fa4ed182	5266	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
richardv	0:b079fa4ed182	5267	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
richardv	0:b079fa4ed182	5268	#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
richardv	0:b079fa4ed182	5269	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
richardv	0:b079fa4ed182	5270	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
richardv	0:b079fa4ed182	5271	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
richardv	0:b079fa4ed182	5272	#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /!< Event Mask on line 24 /
richardv	0:b079fa4ed182	5273	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
richardv	0:b079fa4ed182	5274	#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /!< Event Mask on line 26 /
richardv	0:b079fa4ed182	5275	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
richardv	0:b079fa4ed182	5276	#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /!< Event Mask on line 28 /
richardv	0:b079fa4ed182	5277
richardv	0:b079fa4ed182	5278	/**************** Bit definition for EXTI_RTSR register *****************/
richardv	0:b079fa4ed182	5279	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
richardv	0:b079fa4ed182	5280	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
richardv	0:b079fa4ed182	5281	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
richardv	0:b079fa4ed182	5282	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
richardv	0:b079fa4ed182	5283	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
richardv	0:b079fa4ed182	5284	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
richardv	0:b079fa4ed182	5285	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
richardv	0:b079fa4ed182	5286	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
richardv	0:b079fa4ed182	5287	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
richardv	0:b079fa4ed182	5288	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
richardv	0:b079fa4ed182	5289	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
richardv	0:b079fa4ed182	5290	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
richardv	0:b079fa4ed182	5291	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
richardv	0:b079fa4ed182	5292	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
richardv	0:b079fa4ed182	5293	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
richardv	0:b079fa4ed182	5294	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
richardv	0:b079fa4ed182	5295	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
richardv	0:b079fa4ed182	5296	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
richardv	0:b079fa4ed182	5297	#define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /!< Rising trigger event configuration bit of line 18 /
richardv	0:b079fa4ed182	5298	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
richardv	0:b079fa4ed182	5299	#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
richardv	0:b079fa4ed182	5300	#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
richardv	0:b079fa4ed182	5301	#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
richardv	0:b079fa4ed182	5302	#define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /!< Rising trigger event configuration bit of line 23 /
richardv	0:b079fa4ed182	5303	#define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /!< Rising trigger event configuration bit of line 24 /
richardv	0:b079fa4ed182	5304	#define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /!< Rising trigger event configuration bit of line 25 /
richardv	0:b079fa4ed182	5305	#define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /!< Rising trigger event configuration bit of line 26 /
richardv	0:b079fa4ed182	5306	#define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /!< Rising trigger event configuration bit of line 27 /
richardv	0:b079fa4ed182	5307	#define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /!< Rising trigger event configuration bit of line 28 /
richardv	0:b079fa4ed182	5308
richardv	0:b079fa4ed182	5309	/**************** Bit definition for EXTI_FTSR register *****************/
richardv	0:b079fa4ed182	5310	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
richardv	0:b079fa4ed182	5311	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
richardv	0:b079fa4ed182	5312	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
richardv	0:b079fa4ed182	5313	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
richardv	0:b079fa4ed182	5314	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
richardv	0:b079fa4ed182	5315	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
richardv	0:b079fa4ed182	5316	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
richardv	0:b079fa4ed182	5317	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
richardv	0:b079fa4ed182	5318	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
richardv	0:b079fa4ed182	5319	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
richardv	0:b079fa4ed182	5320	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
richardv	0:b079fa4ed182	5321	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
richardv	0:b079fa4ed182	5322	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
richardv	0:b079fa4ed182	5323	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
richardv	0:b079fa4ed182	5324	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
richardv	0:b079fa4ed182	5325	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
richardv	0:b079fa4ed182	5326	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
richardv	0:b079fa4ed182	5327	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
richardv	0:b079fa4ed182	5328	#define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /!< Falling trigger event configuration bit of line 18 /
richardv	0:b079fa4ed182	5329	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
richardv	0:b079fa4ed182	5330	#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
richardv	0:b079fa4ed182	5331	#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
richardv	0:b079fa4ed182	5332	#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
richardv	0:b079fa4ed182	5333	#define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /!< Falling trigger event configuration bit of line 23 /
richardv	0:b079fa4ed182	5334	#define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /!< Falling trigger event configuration bit of line 24 /
richardv	0:b079fa4ed182	5335	#define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /!< Falling trigger event configuration bit of line 25 /
richardv	0:b079fa4ed182	5336	#define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /!< Falling trigger event configuration bit of line 26 /
richardv	0:b079fa4ed182	5337	#define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /!< Falling trigger event configuration bit of line 27 /
richardv	0:b079fa4ed182	5338	#define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /!< Falling trigger event configuration bit of line 28 /
richardv	0:b079fa4ed182	5339
richardv	0:b079fa4ed182	5340	/**************** Bit definition for EXTI_SWIER register ****************/
richardv	0:b079fa4ed182	5341	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
richardv	0:b079fa4ed182	5342	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
richardv	0:b079fa4ed182	5343	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
richardv	0:b079fa4ed182	5344	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
richardv	0:b079fa4ed182	5345	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
richardv	0:b079fa4ed182	5346	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
richardv	0:b079fa4ed182	5347	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
richardv	0:b079fa4ed182	5348	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
richardv	0:b079fa4ed182	5349	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
richardv	0:b079fa4ed182	5350	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
richardv	0:b079fa4ed182	5351	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
richardv	0:b079fa4ed182	5352	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
richardv	0:b079fa4ed182	5353	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
richardv	0:b079fa4ed182	5354	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
richardv	0:b079fa4ed182	5355	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
richardv	0:b079fa4ed182	5356	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
richardv	0:b079fa4ed182	5357	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
richardv	0:b079fa4ed182	5358	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
richardv	0:b079fa4ed182	5359	#define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /!< Software Interrupt on line 18 /
richardv	0:b079fa4ed182	5360	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
richardv	0:b079fa4ed182	5361	#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
richardv	0:b079fa4ed182	5362	#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
richardv	0:b079fa4ed182	5363	#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
richardv	0:b079fa4ed182	5364	#define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /!< Software Interrupt on line 23 /
richardv	0:b079fa4ed182	5365	#define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /!< Software Interrupt on line 24 /
richardv	0:b079fa4ed182	5366	#define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /!< Software Interrupt on line 25 /
richardv	0:b079fa4ed182	5367	#define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /!< Software Interrupt on line 26 /
richardv	0:b079fa4ed182	5368	#define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /!< Software Interrupt on line 27 /
richardv	0:b079fa4ed182	5369	#define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /!< Software Interrupt on line 28 /
richardv	0:b079fa4ed182	5370
richardv	0:b079fa4ed182	5371	/***************** Bit definition for EXTI_PR register ******************/
richardv	0:b079fa4ed182	5372	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit for line 0 /
richardv	0:b079fa4ed182	5373	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit for line 1 /
richardv	0:b079fa4ed182	5374	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit for line 2 /
richardv	0:b079fa4ed182	5375	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit for line 3 /
richardv	0:b079fa4ed182	5376	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit for line 4 /
richardv	0:b079fa4ed182	5377	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit for line 5 /
richardv	0:b079fa4ed182	5378	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit for line 6 /
richardv	0:b079fa4ed182	5379	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit for line 7 /
richardv	0:b079fa4ed182	5380	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit for line 8 /
richardv	0:b079fa4ed182	5381	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit for line 9 /
richardv	0:b079fa4ed182	5382	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit for line 10 /
richardv	0:b079fa4ed182	5383	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit for line 11 /
richardv	0:b079fa4ed182	5384	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit for line 12 /
richardv	0:b079fa4ed182	5385	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit for line 13 /
richardv	0:b079fa4ed182	5386	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit for line 14 /
richardv	0:b079fa4ed182	5387	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit for line 15 /
richardv	0:b079fa4ed182	5388	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit for line 16 /
richardv	0:b079fa4ed182	5389	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit for line 17 /
richardv	0:b079fa4ed182	5390	#define EXTI_PR_PR18 ((uint32_t)0x00040000) /!< Pending bit for line 18 /
richardv	0:b079fa4ed182	5391	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit for line 19 /
richardv	0:b079fa4ed182	5392	#define EXTI_PR_PR20 ((uint32_t)0x00100000) /!< Pending bit for line 20 /
richardv	0:b079fa4ed182	5393	#define EXTI_PR_PR21 ((uint32_t)0x00200000) /!< Pending bit for line 21 /
richardv	0:b079fa4ed182	5394	#define EXTI_PR_PR22 ((uint32_t)0x00400000) /!< Pending bit for line 22 /
richardv	0:b079fa4ed182	5395	#define EXTI_PR_PR23 ((uint32_t)0x00800000) /!< Pending bit for line 23 /
richardv	0:b079fa4ed182	5396	#define EXTI_PR_PR24 ((uint32_t)0x01000000) /!< Pending bit for line 24 /
richardv	0:b079fa4ed182	5397	#define EXTI_PR_PR25 ((uint32_t)0x02000000) /!< Pending bit for line 25 /
richardv	0:b079fa4ed182	5398	#define EXTI_PR_PR26 ((uint32_t)0x04000000) /!< Pending bit for line 26 /
richardv	0:b079fa4ed182	5399	#define EXTI_PR_PR27 ((uint32_t)0x08000000) /!< Pending bit for line 27 /
richardv	0:b079fa4ed182	5400	#define EXTI_PR_PR28 ((uint32_t)0x10000000) /!< Pending bit for line 28 /
richardv	0:b079fa4ed182	5401
richardv	0:b079fa4ed182	5402	/******************************************************************************/
richardv	0:b079fa4ed182	5403	/* */
richardv	0:b079fa4ed182	5404	/* FLASH */
richardv	0:b079fa4ed182	5405	/* */
richardv	0:b079fa4ed182	5406	/******************************************************************************/
richardv	0:b079fa4ed182	5407	/***************** Bit definition for FLASH_ACR register ****************/
richardv	0:b079fa4ed182	5408	#define FLASH_ACR_LATENCY ((uint8_t)0x03) /!< LATENCY[2:0] bits (Latency) /
richardv	0:b079fa4ed182	5409	#define FLASH_ACR_LATENCY_0 ((uint8_t)0x01) /!< Bit 0 /
richardv	0:b079fa4ed182	5410	#define FLASH_ACR_LATENCY_1 ((uint8_t)0x02) /!< Bit 1 /
richardv	0:b079fa4ed182	5411
richardv	0:b079fa4ed182	5412	#define FLASH_ACR_HLFCYA ((uint8_t)0x08) /!< Flash Half Cycle Access Enable /
richardv	0:b079fa4ed182	5413	#define FLASH_ACR_PRFTBE ((uint8_t)0x10) /!< Prefetch Buffer Enable /
richardv	0:b079fa4ed182	5414	#define FLASH_ACR_PRFTBS ((uint8_t)0x20)
richardv	0:b079fa4ed182	5415
richardv	0:b079fa4ed182	5416	/**************** Bit definition for FLASH_KEYR register ****************/
richardv	0:b079fa4ed182	5417	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
richardv	0:b079fa4ed182	5418
richardv	0:b079fa4ed182	5419	#define RDP_KEY ((uint16_t)0x00A5) /!< RDP Key /
richardv	0:b079fa4ed182	5420	#define FLASH_KEY1 ((uint32_t)0x45670123) /!< FPEC Key1 /
richardv	0:b079fa4ed182	5421	#define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /!< FPEC Key2 /
richardv	0:b079fa4ed182	5422
richardv	0:b079fa4ed182	5423	/*************** Bit definition for FLASH_OPTKEYR register **************/
richardv	0:b079fa4ed182	5424	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
richardv	0:b079fa4ed182	5425
richardv	0:b079fa4ed182	5426	#define FLASH_OPTKEY1 FLASH_KEY1 /!< Option Byte Key1 /
richardv	0:b079fa4ed182	5427	#define FLASH_OPTKEY2 FLASH_KEY2 /!< Option Byte Key2 /
richardv	0:b079fa4ed182	5428
richardv	0:b079fa4ed182	5429	/**************** Bit definition for FLASH_SR register *****************/
richardv	0:b079fa4ed182	5430	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
richardv	0:b079fa4ed182	5431	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
richardv	0:b079fa4ed182	5432	#define FLASH_SR_WRPERR ((uint32_t)0x00000010) /!< Write Protection Error /
richardv	0:b079fa4ed182	5433	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
richardv	0:b079fa4ed182	5434
richardv	0:b079fa4ed182	5435	/***************** Bit definition for FLASH_CR register *****************/
richardv	0:b079fa4ed182	5436	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
richardv	0:b079fa4ed182	5437	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
richardv	0:b079fa4ed182	5438	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
richardv	0:b079fa4ed182	5439	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
richardv	0:b079fa4ed182	5440	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
richardv	0:b079fa4ed182	5441	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
richardv	0:b079fa4ed182	5442	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
richardv	0:b079fa4ed182	5443	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
richardv	0:b079fa4ed182	5444	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
richardv	0:b079fa4ed182	5445	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
richardv	0:b079fa4ed182	5446	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< OptionBytes Loader Launch /
richardv	0:b079fa4ed182	5447
richardv	0:b079fa4ed182	5448	/***************** Bit definition for FLASH_AR register *****************/
richardv	0:b079fa4ed182	5449	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
richardv	0:b079fa4ed182	5450
richardv	0:b079fa4ed182	5451	/**************** Bit definition for FLASH_OBR register *****************/
richardv	0:b079fa4ed182	5452	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
richardv	0:b079fa4ed182	5453	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level 1 /
richardv	0:b079fa4ed182	5454	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level 2 /
richardv	0:b079fa4ed182	5455
richardv	0:b079fa4ed182	5456	#define FLASH_OBR_USER ((uint32_t)0x00003700) /!< User Option Bytes /
richardv	0:b079fa4ed182	5457	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
richardv	0:b079fa4ed182	5458	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
richardv	0:b079fa4ed182	5459	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
richardv	0:b079fa4ed182	5460
richardv	0:b079fa4ed182	5461	/**************** Bit definition for FLASH_WRPR register ****************/
richardv	0:b079fa4ed182	5462	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
richardv	0:b079fa4ed182	5463
richardv	0:b079fa4ed182	5464	/----------------------------------------------------------------------------/
richardv	0:b079fa4ed182	5465
richardv	0:b079fa4ed182	5466	/**************** Bit definition for OB_RDP register ********************/
richardv	0:b079fa4ed182	5467	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
richardv	0:b079fa4ed182	5468	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
richardv	0:b079fa4ed182	5469
richardv	0:b079fa4ed182	5470	/**************** Bit definition for OB_USER register *******************/
richardv	0:b079fa4ed182	5471	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
richardv	0:b079fa4ed182	5472	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
richardv	0:b079fa4ed182	5473
richardv	0:b079fa4ed182	5474	/**************** Bit definition for FLASH_WRP0 register ****************/
richardv	0:b079fa4ed182	5475	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
richardv	0:b079fa4ed182	5476	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
richardv	0:b079fa4ed182	5477
richardv	0:b079fa4ed182	5478	/**************** Bit definition for FLASH_WRP1 register ****************/
richardv	0:b079fa4ed182	5479	#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
richardv	0:b079fa4ed182	5480	#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
richardv	0:b079fa4ed182	5481
richardv	0:b079fa4ed182	5482	/**************** Bit definition for FLASH_WRP2 register ****************/
richardv	0:b079fa4ed182	5483	#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
richardv	0:b079fa4ed182	5484	#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
richardv	0:b079fa4ed182	5485
richardv	0:b079fa4ed182	5486	/**************** Bit definition for FLASH_WRP3 register ****************/
richardv	0:b079fa4ed182	5487	#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
richardv	0:b079fa4ed182	5488	#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
richardv	0:b079fa4ed182	5489	/******************************************************************************/
richardv	0:b079fa4ed182	5490	/* */
richardv	0:b079fa4ed182	5491	/* General Purpose I/O (GPIO) */
richardv	0:b079fa4ed182	5492	/* */
richardv	0:b079fa4ed182	5493	/******************************************************************************/
richardv	0:b079fa4ed182	5494	/***************** Bit definition for GPIO_MODER register ***************/
richardv	0:b079fa4ed182	5495	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
richardv	0:b079fa4ed182	5496	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5497	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5498	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
richardv	0:b079fa4ed182	5499	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5500	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5501	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
richardv	0:b079fa4ed182	5502	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5503	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5504	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
richardv	0:b079fa4ed182	5505	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	5506	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	5507	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
richardv	0:b079fa4ed182	5508	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	5509	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	5510	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
richardv	0:b079fa4ed182	5511	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5512	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5513	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
richardv	0:b079fa4ed182	5514	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5515	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	5516	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
richardv	0:b079fa4ed182	5517	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	5518	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	5519	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
richardv	0:b079fa4ed182	5520	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	5521	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	5522	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
richardv	0:b079fa4ed182	5523	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	5524	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	5525	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
richardv	0:b079fa4ed182	5526	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	5527	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	5528	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
richardv	0:b079fa4ed182	5529	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	5530	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
richardv	0:b079fa4ed182	5531	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
richardv	0:b079fa4ed182	5532	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	5533	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	5534	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
richardv	0:b079fa4ed182	5535	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
richardv	0:b079fa4ed182	5536	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
richardv	0:b079fa4ed182	5537	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
richardv	0:b079fa4ed182	5538	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
richardv	0:b079fa4ed182	5539	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
richardv	0:b079fa4ed182	5540	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
richardv	0:b079fa4ed182	5541	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
richardv	0:b079fa4ed182	5542	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
richardv	0:b079fa4ed182	5543
richardv	0:b079fa4ed182	5544
richardv	0:b079fa4ed182	5545	/**************** Bit definition for GPIO_OTYPER register ***************/
richardv	0:b079fa4ed182	5546	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5547	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5548	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5549	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5550	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5551	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5552	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	5553	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	5554	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	5555	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	5556	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5557	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5558	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5559	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	5560	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	5561	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	5562
richardv	0:b079fa4ed182	5563
richardv	0:b079fa4ed182	5564	/************** Bit definition for GPIO_OSPEEDR register ****************/
richardv	0:b079fa4ed182	5565	#define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
richardv	0:b079fa4ed182	5566	#define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5567	#define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5568	#define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
richardv	0:b079fa4ed182	5569	#define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5570	#define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5571	#define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
richardv	0:b079fa4ed182	5572	#define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5573	#define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5574	#define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
richardv	0:b079fa4ed182	5575	#define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	5576	#define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	5577	#define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
richardv	0:b079fa4ed182	5578	#define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	5579	#define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	5580	#define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
richardv	0:b079fa4ed182	5581	#define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5582	#define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5583	#define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
richardv	0:b079fa4ed182	5584	#define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5585	#define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	5586	#define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
richardv	0:b079fa4ed182	5587	#define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	5588	#define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	5589	#define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
richardv	0:b079fa4ed182	5590	#define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	5591	#define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	5592	#define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
richardv	0:b079fa4ed182	5593	#define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	5594	#define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	5595	#define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
richardv	0:b079fa4ed182	5596	#define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	5597	#define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	5598	#define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
richardv	0:b079fa4ed182	5599	#define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	5600	#define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
richardv	0:b079fa4ed182	5601	#define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
richardv	0:b079fa4ed182	5602	#define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	5603	#define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	5604	#define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
richardv	0:b079fa4ed182	5605	#define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
richardv	0:b079fa4ed182	5606	#define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
richardv	0:b079fa4ed182	5607	#define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
richardv	0:b079fa4ed182	5608	#define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
richardv	0:b079fa4ed182	5609	#define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
richardv	0:b079fa4ed182	5610	#define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
richardv	0:b079fa4ed182	5611	#define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
richardv	0:b079fa4ed182	5612	#define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
richardv	0:b079fa4ed182	5613
richardv	0:b079fa4ed182	5614	/***************** Bit definition for GPIO_PUPDR register ****************/
richardv	0:b079fa4ed182	5615	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
richardv	0:b079fa4ed182	5616	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5617	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5618	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
richardv	0:b079fa4ed182	5619	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5620	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5621	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
richardv	0:b079fa4ed182	5622	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5623	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5624	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
richardv	0:b079fa4ed182	5625	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	5626	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	5627	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
richardv	0:b079fa4ed182	5628	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	5629	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	5630	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
richardv	0:b079fa4ed182	5631	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5632	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5633	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
richardv	0:b079fa4ed182	5634	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5635	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	5636	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
richardv	0:b079fa4ed182	5637	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	5638	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	5639	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
richardv	0:b079fa4ed182	5640	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	5641	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	5642	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
richardv	0:b079fa4ed182	5643	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	5644	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	5645	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
richardv	0:b079fa4ed182	5646	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	5647	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	5648	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
richardv	0:b079fa4ed182	5649	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	5650	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
richardv	0:b079fa4ed182	5651	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
richardv	0:b079fa4ed182	5652	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	5653	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	5654	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
richardv	0:b079fa4ed182	5655	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
richardv	0:b079fa4ed182	5656	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
richardv	0:b079fa4ed182	5657	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
richardv	0:b079fa4ed182	5658	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
richardv	0:b079fa4ed182	5659	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
richardv	0:b079fa4ed182	5660	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
richardv	0:b079fa4ed182	5661	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
richardv	0:b079fa4ed182	5662	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
richardv	0:b079fa4ed182	5663
richardv	0:b079fa4ed182	5664	/***************** Bit definition for GPIO_IDR register *****************/
richardv	0:b079fa4ed182	5665	#define GPIO_IDR_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5666	#define GPIO_IDR_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5667	#define GPIO_IDR_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5668	#define GPIO_IDR_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5669	#define GPIO_IDR_4 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5670	#define GPIO_IDR_5 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5671	#define GPIO_IDR_6 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	5672	#define GPIO_IDR_7 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	5673	#define GPIO_IDR_8 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	5674	#define GPIO_IDR_9 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	5675	#define GPIO_IDR_10 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5676	#define GPIO_IDR_11 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5677	#define GPIO_IDR_12 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5678	#define GPIO_IDR_13 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	5679	#define GPIO_IDR_14 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	5680	#define GPIO_IDR_15 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	5681
richardv	0:b079fa4ed182	5682	/**************** Bit definition for GPIO_ODR register ******************/
richardv	0:b079fa4ed182	5683	#define GPIO_ODR_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5684	#define GPIO_ODR_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5685	#define GPIO_ODR_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5686	#define GPIO_ODR_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5687	#define GPIO_ODR_4 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5688	#define GPIO_ODR_5 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5689	#define GPIO_ODR_6 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	5690	#define GPIO_ODR_7 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	5691	#define GPIO_ODR_8 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	5692	#define GPIO_ODR_9 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	5693	#define GPIO_ODR_10 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5694	#define GPIO_ODR_11 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5695	#define GPIO_ODR_12 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5696	#define GPIO_ODR_13 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	5697	#define GPIO_ODR_14 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	5698	#define GPIO_ODR_15 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	5699
richardv	0:b079fa4ed182	5700	/**************** Bit definition for GPIO_BSRR register ******************/
richardv	0:b079fa4ed182	5701	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5702	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5703	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5704	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5705	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5706	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5707	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	5708	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	5709	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	5710	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	5711	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5712	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5713	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5714	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	5715	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	5716	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	5717	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	5718	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	5719	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	5720	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	5721	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	5722	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	5723	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	5724	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
richardv	0:b079fa4ed182	5725	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	5726	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	5727	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
richardv	0:b079fa4ed182	5728	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
richardv	0:b079fa4ed182	5729	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
richardv	0:b079fa4ed182	5730	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
richardv	0:b079fa4ed182	5731	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
richardv	0:b079fa4ed182	5732	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
richardv	0:b079fa4ed182	5733
richardv	0:b079fa4ed182	5734	/**************** Bit definition for GPIO_LCKR register ******************/
richardv	0:b079fa4ed182	5735	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5736	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5737	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5738	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5739	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5740	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5741	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	5742	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	5743	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	5744	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	5745	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5746	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5747	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5748	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	5749	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	5750	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	5751	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	5752
richardv	0:b079fa4ed182	5753	/**************** Bit definition for GPIO_AFRL register ******************/
richardv	0:b079fa4ed182	5754	#define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
richardv	0:b079fa4ed182	5755	#define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
richardv	0:b079fa4ed182	5756	#define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
richardv	0:b079fa4ed182	5757	#define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
richardv	0:b079fa4ed182	5758	#define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
richardv	0:b079fa4ed182	5759	#define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
richardv	0:b079fa4ed182	5760	#define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
richardv	0:b079fa4ed182	5761	#define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
richardv	0:b079fa4ed182	5762
richardv	0:b079fa4ed182	5763	/**************** Bit definition for GPIO_AFRH register ******************/
richardv	0:b079fa4ed182	5764	#define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
richardv	0:b079fa4ed182	5765	#define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
richardv	0:b079fa4ed182	5766	#define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
richardv	0:b079fa4ed182	5767	#define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
richardv	0:b079fa4ed182	5768	#define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
richardv	0:b079fa4ed182	5769	#define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
richardv	0:b079fa4ed182	5770	#define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
richardv	0:b079fa4ed182	5771	#define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
richardv	0:b079fa4ed182	5772
richardv	0:b079fa4ed182	5773	/**************** Bit definition for GPIO_BRR register *******************/
richardv	0:b079fa4ed182	5774	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5775	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5776	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	5777	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	5778	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	5779	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	5780	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	5781	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	5782	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	5783	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	5784	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	5785	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	5786	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	5787	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	5788	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	5789	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	5790
richardv	0:b079fa4ed182	5791	/******************************************************************************/
richardv	0:b079fa4ed182	5792	/* */
richardv	0:b079fa4ed182	5793	/* Inter-integrated Circuit Interface (I2C) */
richardv	0:b079fa4ed182	5794	/* */
richardv	0:b079fa4ed182	5795	/******************************************************************************/
richardv	0:b079fa4ed182	5796	/***************** Bit definition for I2C_CR1 register *****************/
richardv	0:b079fa4ed182	5797	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
richardv	0:b079fa4ed182	5798	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
richardv	0:b079fa4ed182	5799	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
richardv	0:b079fa4ed182	5800	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
richardv	0:b079fa4ed182	5801	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
richardv	0:b079fa4ed182	5802	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
richardv	0:b079fa4ed182	5803	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
richardv	0:b079fa4ed182	5804	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
richardv	0:b079fa4ed182	5805	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
richardv	0:b079fa4ed182	5806	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
richardv	0:b079fa4ed182	5807	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
richardv	0:b079fa4ed182	5808	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
richardv	0:b079fa4ed182	5809	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
richardv	0:b079fa4ed182	5810	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
richardv	0:b079fa4ed182	5811	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
richardv	0:b079fa4ed182	5812	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
richardv	0:b079fa4ed182	5813	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
richardv	0:b079fa4ed182	5814	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
richardv	0:b079fa4ed182	5815	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
richardv	0:b079fa4ed182	5816	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
richardv	0:b079fa4ed182	5817	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
richardv	0:b079fa4ed182	5818
richardv	0:b079fa4ed182	5819	/**************** Bit definition for I2C_CR2 register ******************/
richardv	0:b079fa4ed182	5820	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
richardv	0:b079fa4ed182	5821	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
richardv	0:b079fa4ed182	5822	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
richardv	0:b079fa4ed182	5823	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
richardv	0:b079fa4ed182	5824	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
richardv	0:b079fa4ed182	5825	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
richardv	0:b079fa4ed182	5826	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
richardv	0:b079fa4ed182	5827	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
richardv	0:b079fa4ed182	5828	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
richardv	0:b079fa4ed182	5829	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
richardv	0:b079fa4ed182	5830	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
richardv	0:b079fa4ed182	5831
richardv	0:b079fa4ed182	5832	/***************** Bit definition for I2C_OAR1 register ****************/
richardv	0:b079fa4ed182	5833	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
richardv	0:b079fa4ed182	5834	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
richardv	0:b079fa4ed182	5835	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
richardv	0:b079fa4ed182	5836
richardv	0:b079fa4ed182	5837	/***************** Bit definition for I2C_OAR2 register *****************/
richardv	0:b079fa4ed182	5838	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
richardv	0:b079fa4ed182	5839	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
richardv	0:b079fa4ed182	5840	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
richardv	0:b079fa4ed182	5841
richardv	0:b079fa4ed182	5842	/***************** Bit definition for I2C_TIMINGR register ***************/
richardv	0:b079fa4ed182	5843	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
richardv	0:b079fa4ed182	5844	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
richardv	0:b079fa4ed182	5845	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
richardv	0:b079fa4ed182	5846	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
richardv	0:b079fa4ed182	5847	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
richardv	0:b079fa4ed182	5848
richardv	0:b079fa4ed182	5849	/***************** Bit definition for I2C_TIMEOUTR register ***************/
richardv	0:b079fa4ed182	5850	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
richardv	0:b079fa4ed182	5851	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
richardv	0:b079fa4ed182	5852	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
richardv	0:b079fa4ed182	5853	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
richardv	0:b079fa4ed182	5854	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
richardv	0:b079fa4ed182	5855
richardv	0:b079fa4ed182	5856	/**************** Bit definition for I2C_ISR register *******************/
richardv	0:b079fa4ed182	5857	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
richardv	0:b079fa4ed182	5858	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
richardv	0:b079fa4ed182	5859	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
richardv	0:b079fa4ed182	5860	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
richardv	0:b079fa4ed182	5861	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
richardv	0:b079fa4ed182	5862	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
richardv	0:b079fa4ed182	5863	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
richardv	0:b079fa4ed182	5864	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
richardv	0:b079fa4ed182	5865	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
richardv	0:b079fa4ed182	5866	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
richardv	0:b079fa4ed182	5867	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
richardv	0:b079fa4ed182	5868	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
richardv	0:b079fa4ed182	5869	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
richardv	0:b079fa4ed182	5870	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
richardv	0:b079fa4ed182	5871	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
richardv	0:b079fa4ed182	5872	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
richardv	0:b079fa4ed182	5873	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
richardv	0:b079fa4ed182	5874
richardv	0:b079fa4ed182	5875	/**************** Bit definition for I2C_ICR register *******************/
richardv	0:b079fa4ed182	5876	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
richardv	0:b079fa4ed182	5877	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
richardv	0:b079fa4ed182	5878	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
richardv	0:b079fa4ed182	5879	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
richardv	0:b079fa4ed182	5880	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
richardv	0:b079fa4ed182	5881	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
richardv	0:b079fa4ed182	5882	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
richardv	0:b079fa4ed182	5883	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
richardv	0:b079fa4ed182	5884	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
richardv	0:b079fa4ed182	5885
richardv	0:b079fa4ed182	5886	/**************** Bit definition for I2C_PECR register ******************/
richardv	0:b079fa4ed182	5887	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
richardv	0:b079fa4ed182	5888
richardv	0:b079fa4ed182	5889	/**************** Bit definition for I2C_RXDR register *******************/
richardv	0:b079fa4ed182	5890	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
richardv	0:b079fa4ed182	5891
richardv	0:b079fa4ed182	5892	/**************** Bit definition for I2C_TXDR register *******************/
richardv	0:b079fa4ed182	5893	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
richardv	0:b079fa4ed182	5894
richardv	0:b079fa4ed182	5895
richardv	0:b079fa4ed182	5896	/******************************************************************************/
richardv	0:b079fa4ed182	5897	/* */
richardv	0:b079fa4ed182	5898	/* Independent WATCHDOG (IWDG) */
richardv	0:b079fa4ed182	5899	/* */
richardv	0:b079fa4ed182	5900	/******************************************************************************/
richardv	0:b079fa4ed182	5901	/***************** Bit definition for IWDG_KR register ******************/
richardv	0:b079fa4ed182	5902	#define IWDG_KR_KEY ((uint16_t)0xFFFF) /!< Key value (write only, read 0000h) /
richardv	0:b079fa4ed182	5903
richardv	0:b079fa4ed182	5904	/***************** Bit definition for IWDG_PR register ******************/
richardv	0:b079fa4ed182	5905	#define IWDG_PR_PR ((uint8_t)0x07) /!< PR[2:0] (Prescaler divider) /
richardv	0:b079fa4ed182	5906	#define IWDG_PR_PR_0 ((uint8_t)0x01) /!< Bit 0 /
richardv	0:b079fa4ed182	5907	#define IWDG_PR_PR_1 ((uint8_t)0x02) /!< Bit 1 /
richardv	0:b079fa4ed182	5908	#define IWDG_PR_PR_2 ((uint8_t)0x04) /!< Bit 2 /
richardv	0:b079fa4ed182	5909
richardv	0:b079fa4ed182	5910	/***************** Bit definition for IWDG_RLR register *****************/
richardv	0:b079fa4ed182	5911	#define IWDG_RLR_RL ((uint16_t)0x0FFF) /!< Watchdog counter reload value /
richardv	0:b079fa4ed182	5912
richardv	0:b079fa4ed182	5913	/***************** Bit definition for IWDG_SR register ******************/
richardv	0:b079fa4ed182	5914	#define IWDG_SR_PVU ((uint8_t)0x01) /!< Watchdog prescaler value update /
richardv	0:b079fa4ed182	5915	#define IWDG_SR_RVU ((uint8_t)0x02) /!< Watchdog counter reload value update /
richardv	0:b079fa4ed182	5916	#define IWDG_SR_WVU ((uint8_t)0x04) /!< Watchdog counter window value update /
richardv	0:b079fa4ed182	5917
richardv	0:b079fa4ed182	5918	/***************** Bit definition for IWDG_KR register ******************/
richardv	0:b079fa4ed182	5919	#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /!< Watchdog counter window value /
richardv	0:b079fa4ed182	5920
richardv	0:b079fa4ed182	5921	/******************************************************************************/
richardv	0:b079fa4ed182	5922	/* */
richardv	0:b079fa4ed182	5923	/* Power Control */
richardv	0:b079fa4ed182	5924	/* */
richardv	0:b079fa4ed182	5925	/******************************************************************************/
richardv	0:b079fa4ed182	5926	/****************** Bit definition for PWR_CR register ******************/
richardv	0:b079fa4ed182	5927	#define PWR_CR_LPSDSR ((uint16_t)0x0001) /!< Low-power deepsleep/sleep/low power run /
richardv	0:b079fa4ed182	5928	#define PWR_CR_PDDS ((uint16_t)0x0002) /!< Power Down Deepsleep /
richardv	0:b079fa4ed182	5929	#define PWR_CR_CWUF ((uint16_t)0x0004) /!< Clear Wakeup Flag /
richardv	0:b079fa4ed182	5930	#define PWR_CR_CSBF ((uint16_t)0x0008) /!< Clear Standby Flag /
richardv	0:b079fa4ed182	5931	#define PWR_CR_PVDE ((uint16_t)0x0010) /!< Power Voltage Detector Enable /
richardv	0:b079fa4ed182	5932
richardv	0:b079fa4ed182	5933	#define PWR_CR_PLS ((uint16_t)0x00E0) /!< PLS[2:0] bits (PVD Level Selection) /
richardv	0:b079fa4ed182	5934	#define PWR_CR_PLS_0 ((uint16_t)0x0020) /!< Bit 0 /
richardv	0:b079fa4ed182	5935	#define PWR_CR_PLS_1 ((uint16_t)0x0040) /!< Bit 1 /
richardv	0:b079fa4ed182	5936	#define PWR_CR_PLS_2 ((uint16_t)0x0080) /!< Bit 2 /
richardv	0:b079fa4ed182	5937
richardv	0:b079fa4ed182	5938	/!< PVD level configuration /
richardv	0:b079fa4ed182	5939	#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /!< PVD level 0 /
richardv	0:b079fa4ed182	5940	#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /!< PVD level 1 /
richardv	0:b079fa4ed182	5941	#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /!< PVD level 2 /
richardv	0:b079fa4ed182	5942	#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /!< PVD level 3 /
richardv	0:b079fa4ed182	5943	#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /!< PVD level 4 /
richardv	0:b079fa4ed182	5944	#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /!< PVD level 5 /
richardv	0:b079fa4ed182	5945	#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /!< PVD level 6 /
richardv	0:b079fa4ed182	5946	#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /!< PVD level 7 /
richardv	0:b079fa4ed182	5947
richardv	0:b079fa4ed182	5948	#define PWR_CR_DBP ((uint16_t)0x0100) /!< Disable Backup Domain write protection /
richardv	0:b079fa4ed182	5949
richardv	0:b079fa4ed182	5950	/***************** Bit definition for PWR_CSR register ******************/
richardv	0:b079fa4ed182	5951	#define PWR_CSR_WUF ((uint16_t)0x0001) /!< Wakeup Flag /
richardv	0:b079fa4ed182	5952	#define PWR_CSR_SBF ((uint16_t)0x0002) /!< Standby Flag /
richardv	0:b079fa4ed182	5953	#define PWR_CSR_PVDO ((uint16_t)0x0004) /!< PVD Output /
richardv	0:b079fa4ed182	5954	#define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /!< Internal voltage reference (VREFINT) ready flag /
richardv	0:b079fa4ed182	5955
richardv	0:b079fa4ed182	5956	#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /!< Enable WKUP pin 1 /
richardv	0:b079fa4ed182	5957	#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /!< Enable WKUP pin 2 /
richardv	0:b079fa4ed182	5958	#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /!< Enable WKUP pin 3 /
richardv	0:b079fa4ed182	5959
richardv	0:b079fa4ed182	5960	/******************************************************************************/
richardv	0:b079fa4ed182	5961	/* */
richardv	0:b079fa4ed182	5962	/* Reset and Clock Control */
richardv	0:b079fa4ed182	5963	/* */
richardv	0:b079fa4ed182	5964	/******************************************************************************/
richardv	0:b079fa4ed182	5965	/****************** Bit definition for RCC_CR register ******************/
richardv	0:b079fa4ed182	5966	#define RCC_CR_HSION ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	5967	#define RCC_CR_HSIRDY ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	5968
richardv	0:b079fa4ed182	5969	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
richardv	0:b079fa4ed182	5970	#define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/!<Bit 0 /
richardv	0:b079fa4ed182	5971	#define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/!<Bit 1 /
richardv	0:b079fa4ed182	5972	#define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/!<Bit 2 /
richardv	0:b079fa4ed182	5973	#define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/!<Bit 3 /
richardv	0:b079fa4ed182	5974	#define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/!<Bit 4 /
richardv	0:b079fa4ed182	5975
richardv	0:b079fa4ed182	5976	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
richardv	0:b079fa4ed182	5977	#define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/!<Bit 0 /
richardv	0:b079fa4ed182	5978	#define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/!<Bit 1 /
richardv	0:b079fa4ed182	5979	#define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/!<Bit 2 /
richardv	0:b079fa4ed182	5980	#define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/!<Bit 3 /
richardv	0:b079fa4ed182	5981	#define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/!<Bit 4 /
richardv	0:b079fa4ed182	5982	#define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/!<Bit 5 /
richardv	0:b079fa4ed182	5983	#define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/!<Bit 6 /
richardv	0:b079fa4ed182	5984	#define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/!<Bit 7 /
richardv	0:b079fa4ed182	5985
richardv	0:b079fa4ed182	5986	#define RCC_CR_HSEON ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	5987	#define RCC_CR_HSERDY ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	5988	#define RCC_CR_HSEBYP ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	5989	#define RCC_CR_CSSON ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	5990
richardv	0:b079fa4ed182	5991	#define RCC_CR_PLLON ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	5992	#define RCC_CR_PLLRDY ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	5993
richardv	0:b079fa4ed182	5994	/****************** Bit definition for RCC_CFGR register ****************/
richardv	0:b079fa4ed182	5995	/!< SW configuration /
richardv	0:b079fa4ed182	5996	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
richardv	0:b079fa4ed182	5997	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
richardv	0:b079fa4ed182	5998	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
richardv	0:b079fa4ed182	5999
richardv	0:b079fa4ed182	6000	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
richardv	0:b079fa4ed182	6001	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
richardv	0:b079fa4ed182	6002	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
richardv	0:b079fa4ed182	6003
richardv	0:b079fa4ed182	6004	/!< SWS configuration /
richardv	0:b079fa4ed182	6005	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
richardv	0:b079fa4ed182	6006	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
richardv	0:b079fa4ed182	6007	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
richardv	0:b079fa4ed182	6008
richardv	0:b079fa4ed182	6009	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
richardv	0:b079fa4ed182	6010	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
richardv	0:b079fa4ed182	6011	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
richardv	0:b079fa4ed182	6012
richardv	0:b079fa4ed182	6013	/!< HPRE configuration /
richardv	0:b079fa4ed182	6014	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
richardv	0:b079fa4ed182	6015	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
richardv	0:b079fa4ed182	6016	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
richardv	0:b079fa4ed182	6017	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
richardv	0:b079fa4ed182	6018	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
richardv	0:b079fa4ed182	6019
richardv	0:b079fa4ed182	6020	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
richardv	0:b079fa4ed182	6021	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
richardv	0:b079fa4ed182	6022	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
richardv	0:b079fa4ed182	6023	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
richardv	0:b079fa4ed182	6024	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
richardv	0:b079fa4ed182	6025	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
richardv	0:b079fa4ed182	6026	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
richardv	0:b079fa4ed182	6027	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
richardv	0:b079fa4ed182	6028	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
richardv	0:b079fa4ed182	6029
richardv	0:b079fa4ed182	6030	/!< PPRE1 configuration /
richardv	0:b079fa4ed182	6031	#define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /!< PRE1[2:0] bits (APB1 prescaler) /
richardv	0:b079fa4ed182	6032	#define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /!< Bit 0 /
richardv	0:b079fa4ed182	6033	#define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /!< Bit 1 /
richardv	0:b079fa4ed182	6034	#define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /!< Bit 2 /
richardv	0:b079fa4ed182	6035
richardv	0:b079fa4ed182	6036	#define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
richardv	0:b079fa4ed182	6037	#define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
richardv	0:b079fa4ed182	6038	#define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
richardv	0:b079fa4ed182	6039	#define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
richardv	0:b079fa4ed182	6040	#define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
richardv	0:b079fa4ed182	6041
richardv	0:b079fa4ed182	6042	/!< PPRE2 configuration /
richardv	0:b079fa4ed182	6043	#define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /!< PRE2[2:0] bits (APB2 prescaler) /
richardv	0:b079fa4ed182	6044	#define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /!< Bit 0 /
richardv	0:b079fa4ed182	6045	#define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /!< Bit 1 /
richardv	0:b079fa4ed182	6046	#define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /!< Bit 2 /
richardv	0:b079fa4ed182	6047
richardv	0:b079fa4ed182	6048	#define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
richardv	0:b079fa4ed182	6049	#define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /!< HCLK divided by 2 /
richardv	0:b079fa4ed182	6050	#define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /!< HCLK divided by 4 /
richardv	0:b079fa4ed182	6051	#define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /!< HCLK divided by 8 /
richardv	0:b079fa4ed182	6052	#define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /!< HCLK divided by 16 /
richardv	0:b079fa4ed182	6053
richardv	0:b079fa4ed182	6054	#define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /!< PLL entry clock source /
richardv	0:b079fa4ed182	6055
richardv	0:b079fa4ed182	6056	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
richardv	0:b079fa4ed182	6057
richardv	0:b079fa4ed182	6058	/!< PLLMUL configuration /
richardv	0:b079fa4ed182	6059	#define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
richardv	0:b079fa4ed182	6060	#define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /!< Bit 0 /
richardv	0:b079fa4ed182	6061	#define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /!< Bit 1 /
richardv	0:b079fa4ed182	6062	#define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /!< Bit 2 /
richardv	0:b079fa4ed182	6063	#define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /!< Bit 3 /
richardv	0:b079fa4ed182	6064
richardv	0:b079fa4ed182	6065	#define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
richardv	0:b079fa4ed182	6066	#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /!< PREDIV1 clock selected as PLL entry clock source /
richardv	0:b079fa4ed182	6067
richardv	0:b079fa4ed182	6068	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
richardv	0:b079fa4ed182	6069	#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
richardv	0:b079fa4ed182	6070
richardv	0:b079fa4ed182	6071	#define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
richardv	0:b079fa4ed182	6072	#define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
richardv	0:b079fa4ed182	6073	#define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
richardv	0:b079fa4ed182	6074	#define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
richardv	0:b079fa4ed182	6075	#define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
richardv	0:b079fa4ed182	6076	#define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
richardv	0:b079fa4ed182	6077	#define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
richardv	0:b079fa4ed182	6078	#define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
richardv	0:b079fa4ed182	6079	#define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
richardv	0:b079fa4ed182	6080	#define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
richardv	0:b079fa4ed182	6081	#define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
richardv	0:b079fa4ed182	6082	#define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
richardv	0:b079fa4ed182	6083	#define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
richardv	0:b079fa4ed182	6084	#define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
richardv	0:b079fa4ed182	6085	#define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
richardv	0:b079fa4ed182	6086
richardv	0:b079fa4ed182	6087	/!< USB configuration /
richardv	0:b079fa4ed182	6088	#define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /!< USB prescaler /
richardv	0:b079fa4ed182	6089
richardv	0:b079fa4ed182	6090	/!< I2S configuration /
richardv	0:b079fa4ed182	6091	#define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /!< I2S external clock source selection /
richardv	0:b079fa4ed182	6092
richardv	0:b079fa4ed182	6093	/!< MCO configuration /
richardv	0:b079fa4ed182	6094	#define RCC_CFGR_MCO ((uint32_t)0x07000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
richardv	0:b079fa4ed182	6095	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
richardv	0:b079fa4ed182	6096	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
richardv	0:b079fa4ed182	6097	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
richardv	0:b079fa4ed182	6098
richardv	0:b079fa4ed182	6099	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
richardv	0:b079fa4ed182	6100	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
richardv	0:b079fa4ed182	6101	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
richardv	0:b079fa4ed182	6102	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
richardv	0:b079fa4ed182	6103	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
richardv	0:b079fa4ed182	6104	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
richardv	0:b079fa4ed182	6105	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock divided by 2 selected as MCO source /
richardv	0:b079fa4ed182	6106
richardv	0:b079fa4ed182	6107	#define RCC_CFGR_MCOF ((uint32_t)0x10000000) /!< Microcontroller Clock Output Flag /
richardv	0:b079fa4ed182	6108
richardv	0:b079fa4ed182	6109	#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /!< MCO prescaler /
richardv	0:b079fa4ed182	6110	#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /!< MCO is divided by 1 /
richardv	0:b079fa4ed182	6111	#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /!< MCO is divided by 2 /
richardv	0:b079fa4ed182	6112	#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /!< MCO is divided by 4 /
richardv	0:b079fa4ed182	6113	#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /!< MCO is divided by 8 /
richardv	0:b079fa4ed182	6114	#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /!< MCO is divided by 16 /
richardv	0:b079fa4ed182	6115	#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /!< MCO is divided by 32 /
richardv	0:b079fa4ed182	6116	#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /!< MCO is divided by 64 /
richardv	0:b079fa4ed182	6117	#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /!< MCO is divided by 128 /
richardv	0:b079fa4ed182	6118
richardv	0:b079fa4ed182	6119	#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /!< PLL is not divided to MCO /
richardv	0:b079fa4ed182	6120
richardv	0:b079fa4ed182	6121	/******************* Bit definition for RCC_CIR register ******************/
richardv	0:b079fa4ed182	6122	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
richardv	0:b079fa4ed182	6123	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
richardv	0:b079fa4ed182	6124	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
richardv	0:b079fa4ed182	6125	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
richardv	0:b079fa4ed182	6126	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
richardv	0:b079fa4ed182	6127	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
richardv	0:b079fa4ed182	6128	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
richardv	0:b079fa4ed182	6129	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
richardv	0:b079fa4ed182	6130	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
richardv	0:b079fa4ed182	6131	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
richardv	0:b079fa4ed182	6132	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
richardv	0:b079fa4ed182	6133	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
richardv	0:b079fa4ed182	6134	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
richardv	0:b079fa4ed182	6135	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
richardv	0:b079fa4ed182	6136	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
richardv	0:b079fa4ed182	6137	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
richardv	0:b079fa4ed182	6138	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
richardv	0:b079fa4ed182	6139
richardv	0:b079fa4ed182	6140	/**************** Bit definition for RCC_APB2RSTR register ***************/
richardv	0:b079fa4ed182	6141	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG reset /
richardv	0:b079fa4ed182	6142	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000200) /!< TIM1 reset /
richardv	0:b079fa4ed182	6143	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 reset /
richardv	0:b079fa4ed182	6144	#define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000200) /!< TIM8 reset /
richardv	0:b079fa4ed182	6145	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 reset /
richardv	0:b079fa4ed182	6146	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 reset /
richardv	0:b079fa4ed182	6147	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 reset /
richardv	0:b079fa4ed182	6148	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 reset /
richardv	0:b079fa4ed182	6149	#define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /!< HRTIM1 reset /
richardv	0:b079fa4ed182	6150
richardv	0:b079fa4ed182	6151	/**************** Bit definition for RCC_APB1RSTR register ****************/
richardv	0:b079fa4ed182	6152	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 reset /
richardv	0:b079fa4ed182	6153	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 reset /
richardv	0:b079fa4ed182	6154	#define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /!< Timer 4 reset /
richardv	0:b079fa4ed182	6155	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 reset /
richardv	0:b079fa4ed182	6156	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 reset /
richardv	0:b079fa4ed182	6157	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog reset /
richardv	0:b079fa4ed182	6158	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 reset /
richardv	0:b079fa4ed182	6159	#define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /!< SPI3 reset /
richardv	0:b079fa4ed182	6160	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 reset /
richardv	0:b079fa4ed182	6161	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 reset /
richardv	0:b079fa4ed182	6162	#define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /!< UART 4 reset /
richardv	0:b079fa4ed182	6163	#define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /!< UART 5 reset /
richardv	0:b079fa4ed182	6164	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 reset /
richardv	0:b079fa4ed182	6165	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 reset /
richardv	0:b079fa4ed182	6166	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB reset /
richardv	0:b079fa4ed182	6167	#define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /!< CAN reset /
richardv	0:b079fa4ed182	6168	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR reset /
richardv	0:b079fa4ed182	6169	#define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /!< DAC 1 reset /
richardv	0:b079fa4ed182	6170	#define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /!< I2C 3 reset /
richardv	0:b079fa4ed182	6171	#define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /!< DAC 2 reset /
richardv	0:b079fa4ed182	6172	#define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DAC1RST /!< DAC reset /
richardv	0:b079fa4ed182	6173
richardv	0:b079fa4ed182	6174	/**************** Bit definition for RCC_AHBENR register ****************/
richardv	0:b079fa4ed182	6175	#define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /!< DMA1 clock enable /
richardv	0:b079fa4ed182	6176	#define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /!< DMA2 clock enable /
richardv	0:b079fa4ed182	6177	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
richardv	0:b079fa4ed182	6178	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
richardv	0:b079fa4ed182	6179	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
richardv	0:b079fa4ed182	6180	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
richardv	0:b079fa4ed182	6181	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
richardv	0:b079fa4ed182	6182	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
richardv	0:b079fa4ed182	6183	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
richardv	0:b079fa4ed182	6184	#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /!< GPIOE clock enable /
richardv	0:b079fa4ed182	6185	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
richardv	0:b079fa4ed182	6186	#define RCC_AHBENR_TSEN ((uint32_t)0x01000000) /!< TS clock enable /
richardv	0:b079fa4ed182	6187	#define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /!< ADC1/ ADC2 clock enable /
richardv	0:b079fa4ed182	6188	#define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /!< ADC1/ ADC2 clock enable /
richardv	0:b079fa4ed182	6189
richardv	0:b079fa4ed182	6190	/*************** Bit definition for RCC_APB2ENR register ****************/
richardv	0:b079fa4ed182	6191	#define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /!< SYSCFG clock enable /
richardv	0:b079fa4ed182	6192	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
richardv	0:b079fa4ed182	6193	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
richardv	0:b079fa4ed182	6194	#define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /!< TIM8 clock enable /
richardv	0:b079fa4ed182	6195	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
richardv	0:b079fa4ed182	6196	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 clock enable /
richardv	0:b079fa4ed182	6197	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
richardv	0:b079fa4ed182	6198	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
richardv	0:b079fa4ed182	6199	#define RCC_APB2ENR_HRTIM1 ((uint32_t)0x20000000) /!< HRTIM1 clock enable /
richardv	0:b079fa4ed182	6200
richardv	0:b079fa4ed182	6201	/**************** Bit definition for RCC_APB1ENR register ****************/
richardv	0:b079fa4ed182	6202	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enable /
richardv	0:b079fa4ed182	6203	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
richardv	0:b079fa4ed182	6204	#define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /!< Timer 4 clock enable /
richardv	0:b079fa4ed182	6205	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
richardv	0:b079fa4ed182	6206	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
richardv	0:b079fa4ed182	6207	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
richardv	0:b079fa4ed182	6208	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
richardv	0:b079fa4ed182	6209	#define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /!< SPI3 clock enable /
richardv	0:b079fa4ed182	6210	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART 2 clock enable /
richardv	0:b079fa4ed182	6211	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART 3 clock enable /
richardv	0:b079fa4ed182	6212	#define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /!< UART 4 clock enable /
richardv	0:b079fa4ed182	6213	#define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /!< UART 5 clock enable /
richardv	0:b079fa4ed182	6214	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C 1 clock enable /
richardv	0:b079fa4ed182	6215	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C 2 clock enable /
richardv	0:b079fa4ed182	6216	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
richardv	0:b079fa4ed182	6217	#define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /!< CAN clock enable /
richardv	0:b079fa4ed182	6218	#define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /!< DAC 2 clock enable /
richardv	0:b079fa4ed182	6219	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
richardv	0:b079fa4ed182	6220	#define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /!< DAC clock enable /
richardv	0:b079fa4ed182	6221	#define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /!< I2C 3 clock enable /
richardv	0:b079fa4ed182	6222	#define RCC_APB1ENR_DACEN RCC_APB1ENR_DAC1EN
richardv	0:b079fa4ed182	6223
richardv	0:b079fa4ed182	6224	/****************** Bit definition for RCC_BDCR register ****************/
richardv	0:b079fa4ed182	6225	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
richardv	0:b079fa4ed182	6226	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
richardv	0:b079fa4ed182	6227	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
richardv	0:b079fa4ed182	6228
richardv	0:b079fa4ed182	6229	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
richardv	0:b079fa4ed182	6230	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
richardv	0:b079fa4ed182	6231	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
richardv	0:b079fa4ed182	6232
richardv	0:b079fa4ed182	6233
richardv	0:b079fa4ed182	6234	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
richardv	0:b079fa4ed182	6235	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
richardv	0:b079fa4ed182	6236	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
richardv	0:b079fa4ed182	6237
richardv	0:b079fa4ed182	6238	/!< RTC configuration /
richardv	0:b079fa4ed182	6239	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
richardv	0:b079fa4ed182	6240	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
richardv	0:b079fa4ed182	6241	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
richardv	0:b079fa4ed182	6242	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 32 used as RTC clock /
richardv	0:b079fa4ed182	6243
richardv	0:b079fa4ed182	6244	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
richardv	0:b079fa4ed182	6245	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
richardv	0:b079fa4ed182	6246
richardv	0:b079fa4ed182	6247	/****************** Bit definition for RCC_CSR register *****************/
richardv	0:b079fa4ed182	6248	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
richardv	0:b079fa4ed182	6249	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
richardv	0:b079fa4ed182	6250	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
richardv	0:b079fa4ed182	6251	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
richardv	0:b079fa4ed182	6252	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
richardv	0:b079fa4ed182	6253	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
richardv	0:b079fa4ed182	6254	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
richardv	0:b079fa4ed182	6255	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
richardv	0:b079fa4ed182	6256	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
richardv	0:b079fa4ed182	6257	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
richardv	0:b079fa4ed182	6258
richardv	0:b079fa4ed182	6259	/***************** Bit definition for RCC_AHBRSTR register **************/
richardv	0:b079fa4ed182	6260	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA reset /
richardv	0:b079fa4ed182	6261	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB reset /
richardv	0:b079fa4ed182	6262	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC reset /
richardv	0:b079fa4ed182	6263	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /!< GPIOD reset /
richardv	0:b079fa4ed182	6264	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /!< GPIOF reset /
richardv	0:b079fa4ed182	6265	#define RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) /!< TS reset /
richardv	0:b079fa4ed182	6266	#define RCC_AHBRSTR_ADC12RST ((uint32_t)0x01000000) /!< ADC1 & ADC2 reset /
richardv	0:b079fa4ed182	6267	#define RCC_AHBRSTR_ADC34RST ((uint32_t)0x02000000) /!< ADC3 & ADC4 reset /
richardv	0:b079fa4ed182	6268
richardv	0:b079fa4ed182	6269	/***************** Bit definition for RCC_CFGR2 register ****************/
richardv	0:b079fa4ed182	6270	/!< PREDIV1 configuration /
richardv	0:b079fa4ed182	6271	#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /!< PREDIV1[3:0] bits /
richardv	0:b079fa4ed182	6272	#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /!< Bit 0 /
richardv	0:b079fa4ed182	6273	#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /!< Bit 1 /
richardv	0:b079fa4ed182	6274	#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /!< Bit 2 /
richardv	0:b079fa4ed182	6275	#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /!< Bit 3 /
richardv	0:b079fa4ed182	6276
richardv	0:b079fa4ed182	6277	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
richardv	0:b079fa4ed182	6278	#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /!< PREDIV1 input clock divided by 2 /
richardv	0:b079fa4ed182	6279	#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /!< PREDIV1 input clock divided by 3 /
richardv	0:b079fa4ed182	6280	#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /!< PREDIV1 input clock divided by 4 /
richardv	0:b079fa4ed182	6281	#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /!< PREDIV1 input clock divided by 5 /
richardv	0:b079fa4ed182	6282	#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /!< PREDIV1 input clock divided by 6 /
richardv	0:b079fa4ed182	6283	#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /!< PREDIV1 input clock divided by 7 /
richardv	0:b079fa4ed182	6284	#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /!< PREDIV1 input clock divided by 8 /
richardv	0:b079fa4ed182	6285	#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /!< PREDIV1 input clock divided by 9 /
richardv	0:b079fa4ed182	6286	#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /!< PREDIV1 input clock divided by 10 /
richardv	0:b079fa4ed182	6287	#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /!< PREDIV1 input clock divided by 11 /
richardv	0:b079fa4ed182	6288	#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /!< PREDIV1 input clock divided by 12 /
richardv	0:b079fa4ed182	6289	#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /!< PREDIV1 input clock divided by 13 /
richardv	0:b079fa4ed182	6290	#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /!< PREDIV1 input clock divided by 14 /
richardv	0:b079fa4ed182	6291	#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /!< PREDIV1 input clock divided by 15 /
richardv	0:b079fa4ed182	6292	#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /!< PREDIV1 input clock divided by 16 /
richardv	0:b079fa4ed182	6293
richardv	0:b079fa4ed182	6294	/!< ADCPRE12 configuration /
richardv	0:b079fa4ed182	6295	#define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /!< ADCPRE12[8:4] bits /
richardv	0:b079fa4ed182	6296	#define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /!< Bit 0 /
richardv	0:b079fa4ed182	6297	#define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /!< Bit 1 /
richardv	0:b079fa4ed182	6298	#define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /!< Bit 2 /
richardv	0:b079fa4ed182	6299	#define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /!< Bit 3 /
richardv	0:b079fa4ed182	6300	#define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /!< Bit 4 /
richardv	0:b079fa4ed182	6301
richardv	0:b079fa4ed182	6302	#define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /!< ADC12 clock disabled, ADC12 can use AHB clock /
richardv	0:b079fa4ed182	6303	#define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /!< ADC12 PLL clock divided by 1 /
richardv	0:b079fa4ed182	6304	#define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /!< ADC12 PLL clock divided by 2 /
richardv	0:b079fa4ed182	6305	#define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /!< ADC12 PLL clock divided by 4 /
richardv	0:b079fa4ed182	6306	#define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /!< ADC12 PLL clock divided by 6 /
richardv	0:b079fa4ed182	6307	#define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /!< ADC12 PLL clock divided by 8 /
richardv	0:b079fa4ed182	6308	#define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /!< ADC12 PLL clock divided by 10 /
richardv	0:b079fa4ed182	6309	#define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /!< ADC12 PLL clock divided by 12 /
richardv	0:b079fa4ed182	6310	#define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /!< ADC12 PLL clock divided by 16 /
richardv	0:b079fa4ed182	6311	#define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /!< ADC12 PLL clock divided by 32 /
richardv	0:b079fa4ed182	6312	#define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /!< ADC12 PLL clock divided by 64 /
richardv	0:b079fa4ed182	6313	#define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /!< ADC12 PLL clock divided by 128 /
richardv	0:b079fa4ed182	6314	#define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /!< ADC12 PLL clock divided by 256 /
richardv	0:b079fa4ed182	6315
richardv	0:b079fa4ed182	6316	/!< ADCPRE34 configuration /
richardv	0:b079fa4ed182	6317	#define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /!< ADCPRE34[13:5] bits /
richardv	0:b079fa4ed182	6318	#define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /!< Bit 0 /
richardv	0:b079fa4ed182	6319	#define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /!< Bit 1 /
richardv	0:b079fa4ed182	6320	#define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /!< Bit 2 /
richardv	0:b079fa4ed182	6321	#define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /!< Bit 3 /
richardv	0:b079fa4ed182	6322	#define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /!< Bit 4 /
richardv	0:b079fa4ed182	6323
richardv	0:b079fa4ed182	6324	#define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /!< ADC34 clock disabled, ADC34 can use AHB clock /
richardv	0:b079fa4ed182	6325	#define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /!< ADC34 PLL clock divided by 1 /
richardv	0:b079fa4ed182	6326	#define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /!< ADC34 PLL clock divided by 2 /
richardv	0:b079fa4ed182	6327	#define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /!< ADC34 PLL clock divided by 4 /
richardv	0:b079fa4ed182	6328	#define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /!< ADC34 PLL clock divided by 6 /
richardv	0:b079fa4ed182	6329	#define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /!< ADC34 PLL clock divided by 8 /
richardv	0:b079fa4ed182	6330	#define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /!< ADC34 PLL clock divided by 10 /
richardv	0:b079fa4ed182	6331	#define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /!< ADC34 PLL clock divided by 12 /
richardv	0:b079fa4ed182	6332	#define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /!< ADC34 PLL clock divided by 16 /
richardv	0:b079fa4ed182	6333	#define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /!< ADC34 PLL clock divided by 32 /
richardv	0:b079fa4ed182	6334	#define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /!< ADC34 PLL clock divided by 64 /
richardv	0:b079fa4ed182	6335	#define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /!< ADC34 PLL clock divided by 128 /
richardv	0:b079fa4ed182	6336	#define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /!< ADC34 PLL clock divided by 256 /
richardv	0:b079fa4ed182	6337
richardv	0:b079fa4ed182	6338	/***************** Bit definition for RCC_CFGR3 register ****************/
richardv	0:b079fa4ed182	6339	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
richardv	0:b079fa4ed182	6340	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
richardv	0:b079fa4ed182	6341	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
richardv	0:b079fa4ed182	6342
richardv	0:b079fa4ed182	6343	#define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /!< I2CSW bits /
richardv	0:b079fa4ed182	6344	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
richardv	0:b079fa4ed182	6345	#define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /!< I2C2SW bits /
richardv	0:b079fa4ed182	6346	#define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /!< I2C3SW bits /
richardv	0:b079fa4ed182	6347
richardv	0:b079fa4ed182	6348	#define RCC_CFGR3_TIMSW ((uint32_t)0x00002F00) /!< TIMSW bits /
richardv	0:b079fa4ed182	6349	#define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /!< TIM1SW bits /
richardv	0:b079fa4ed182	6350	#define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /!< TIM8SW bits /
richardv	0:b079fa4ed182	6351	#define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /!< TIM15SW bits /
richardv	0:b079fa4ed182	6352	#define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /!< TIM16SW bits /
richardv	0:b079fa4ed182	6353	#define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /!< TIM17SW bits /
richardv	0:b079fa4ed182	6354
richardv	0:b079fa4ed182	6355	#define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /!< HRTIM1SW bits /
richardv	0:b079fa4ed182	6356
richardv	0:b079fa4ed182	6357	#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /!< USART2SW[1:0] bits /
richardv	0:b079fa4ed182	6358	#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /!< Bit 0 /
richardv	0:b079fa4ed182	6359	#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /!< Bit 1 /
richardv	0:b079fa4ed182	6360
richardv	0:b079fa4ed182	6361	#define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /!< USART3SW[1:0] bits /
richardv	0:b079fa4ed182	6362	#define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /!< Bit 0 /
richardv	0:b079fa4ed182	6363	#define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /!< Bit 1 /
richardv	0:b079fa4ed182	6364
richardv	0:b079fa4ed182	6365	#define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /!< UART4SW[1:0] bits /
richardv	0:b079fa4ed182	6366	#define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /!< Bit 0 /
richardv	0:b079fa4ed182	6367	#define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /!< Bit 1 /
richardv	0:b079fa4ed182	6368
richardv	0:b079fa4ed182	6369	#define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /!< UART5SW[1:0] bits /
richardv	0:b079fa4ed182	6370	#define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /!< Bit 0 /
richardv	0:b079fa4ed182	6371	#define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /!< Bit 1 /
richardv	0:b079fa4ed182	6372
richardv	0:b079fa4ed182	6373	/******************************************************************************/
richardv	0:b079fa4ed182	6374	/* */
richardv	0:b079fa4ed182	6375	/* Real-Time Clock (RTC) */
richardv	0:b079fa4ed182	6376	/* */
richardv	0:b079fa4ed182	6377	/******************************************************************************/
richardv	0:b079fa4ed182	6378	/****************** Bits definition for RTC_TR register *****************/
richardv	0:b079fa4ed182	6379	#define RTC_TR_PM ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	6380	#define RTC_TR_HT ((uint32_t)0x00300000)
richardv	0:b079fa4ed182	6381	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	6382	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	6383	#define RTC_TR_HU ((uint32_t)0x000F0000)
richardv	0:b079fa4ed182	6384	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	6385	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	6386	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	6387	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	6388	#define RTC_TR_MNT ((uint32_t)0x00007000)
richardv	0:b079fa4ed182	6389	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	6390	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6391	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6392	#define RTC_TR_MNU ((uint32_t)0x00000F00)
richardv	0:b079fa4ed182	6393	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6394	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	6395	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	6396	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	6397	#define RTC_TR_ST ((uint32_t)0x00000070)
richardv	0:b079fa4ed182	6398	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6399	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6400	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	6401	#define RTC_TR_SU ((uint32_t)0x0000000F)
richardv	0:b079fa4ed182	6402	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6403	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6404	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6405	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6406
richardv	0:b079fa4ed182	6407	/****************** Bits definition for RTC_DR register *****************/
richardv	0:b079fa4ed182	6408	#define RTC_DR_YT ((uint32_t)0x00F00000)
richardv	0:b079fa4ed182	6409	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	6410	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	6411	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	6412	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
richardv	0:b079fa4ed182	6413	#define RTC_DR_YU ((uint32_t)0x000F0000)
richardv	0:b079fa4ed182	6414	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	6415	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	6416	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	6417	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	6418	#define RTC_DR_WDU ((uint32_t)0x0000E000)
richardv	0:b079fa4ed182	6419	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6420	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6421	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	6422	#define RTC_DR_MT ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	6423	#define RTC_DR_MU ((uint32_t)0x00000F00)
richardv	0:b079fa4ed182	6424	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6425	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	6426	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	6427	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	6428	#define RTC_DR_DT ((uint32_t)0x00000030)
richardv	0:b079fa4ed182	6429	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6430	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6431	#define RTC_DR_DU ((uint32_t)0x0000000F)
richardv	0:b079fa4ed182	6432	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6433	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6434	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6435	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6436
richardv	0:b079fa4ed182	6437	/****************** Bits definition for RTC_CR register *****************/
richardv	0:b079fa4ed182	6438	#define RTC_CR_COE ((uint32_t)0x00800000)
richardv	0:b079fa4ed182	6439	#define RTC_CR_OSEL ((uint32_t)0x00600000)
richardv	0:b079fa4ed182	6440	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	6441	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	6442	#define RTC_CR_POL ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	6443	#define RTC_CR_COSEL ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	6444	#define RTC_CR_BCK ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	6445	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	6446	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	6447	#define RTC_CR_TSIE ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	6448	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6449	#define RTC_CR_ALRBIE ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6450	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	6451	#define RTC_CR_TSE ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	6452	#define RTC_CR_WUTE ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	6453	#define RTC_CR_ALRBE ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	6454	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6455	#define RTC_CR_FMT ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	6456	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6457	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6458	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6459	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
richardv	0:b079fa4ed182	6460	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6461	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6462	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6463
richardv	0:b079fa4ed182	6464	/****************** Bits definition for RTC_ISR register ****************/
richardv	0:b079fa4ed182	6465	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	6466	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	6467	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6468	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6469	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	6470	#define RTC_ISR_TSF ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	6471	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	6472	#define RTC_ISR_ALRBF ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	6473	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6474	#define RTC_ISR_INIT ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	6475	#define RTC_ISR_INITF ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	6476	#define RTC_ISR_RSF ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6477	#define RTC_ISR_INITS ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6478	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6479	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6480	#define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6481	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6482
richardv	0:b079fa4ed182	6483	/****************** Bits definition for RTC_PRER register ***************/
richardv	0:b079fa4ed182	6484	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
richardv	0:b079fa4ed182	6485	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
richardv	0:b079fa4ed182	6486
richardv	0:b079fa4ed182	6487	/****************** Bits definition for RTC_WUTR register ***************/
richardv	0:b079fa4ed182	6488	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
richardv	0:b079fa4ed182	6489
richardv	0:b079fa4ed182	6490	/****************** Bits definition for RTC_ALRMAR register *************/
richardv	0:b079fa4ed182	6491	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
richardv	0:b079fa4ed182	6492	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
richardv	0:b079fa4ed182	6493	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
richardv	0:b079fa4ed182	6494	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
richardv	0:b079fa4ed182	6495	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
richardv	0:b079fa4ed182	6496	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
richardv	0:b079fa4ed182	6497	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	6498	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	6499	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
richardv	0:b079fa4ed182	6500	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
richardv	0:b079fa4ed182	6501	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
richardv	0:b079fa4ed182	6502	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	6503	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
richardv	0:b079fa4ed182	6504	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	6505	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	6506	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
richardv	0:b079fa4ed182	6507	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	6508	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	6509	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	6510	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	6511	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	6512	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
richardv	0:b079fa4ed182	6513	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	6514	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6515	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6516	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
richardv	0:b079fa4ed182	6517	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6518	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	6519	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	6520	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	6521	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	6522	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
richardv	0:b079fa4ed182	6523	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6524	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6525	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	6526	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
richardv	0:b079fa4ed182	6527	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6528	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6529	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6530	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6531
richardv	0:b079fa4ed182	6532	/****************** Bits definition for RTC_ALRMBR register *************/
richardv	0:b079fa4ed182	6533	#define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
richardv	0:b079fa4ed182	6534	#define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
richardv	0:b079fa4ed182	6535	#define RTC_ALRMBR_DT ((uint32_t)0x30000000)
richardv	0:b079fa4ed182	6536	#define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
richardv	0:b079fa4ed182	6537	#define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
richardv	0:b079fa4ed182	6538	#define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
richardv	0:b079fa4ed182	6539	#define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	6540	#define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	6541	#define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
richardv	0:b079fa4ed182	6542	#define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
richardv	0:b079fa4ed182	6543	#define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
richardv	0:b079fa4ed182	6544	#define RTC_ALRMBR_PM ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	6545	#define RTC_ALRMBR_HT ((uint32_t)0x00300000)
richardv	0:b079fa4ed182	6546	#define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	6547	#define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	6548	#define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
richardv	0:b079fa4ed182	6549	#define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	6550	#define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	6551	#define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	6552	#define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	6553	#define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	6554	#define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
richardv	0:b079fa4ed182	6555	#define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	6556	#define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6557	#define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6558	#define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
richardv	0:b079fa4ed182	6559	#define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6560	#define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	6561	#define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	6562	#define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	6563	#define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	6564	#define RTC_ALRMBR_ST ((uint32_t)0x00000070)
richardv	0:b079fa4ed182	6565	#define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6566	#define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6567	#define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	6568	#define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
richardv	0:b079fa4ed182	6569	#define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6570	#define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6571	#define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6572	#define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6573
richardv	0:b079fa4ed182	6574	/****************** Bits definition for RTC_WPR register ****************/
richardv	0:b079fa4ed182	6575	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
richardv	0:b079fa4ed182	6576
richardv	0:b079fa4ed182	6577	/****************** Bits definition for RTC_SSR register ****************/
richardv	0:b079fa4ed182	6578	#define RTC_SSR_SS ((uint32_t)0x0000FFFF)
richardv	0:b079fa4ed182	6579
richardv	0:b079fa4ed182	6580	/****************** Bits definition for RTC_SHIFTR register *************/
richardv	0:b079fa4ed182	6581	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
richardv	0:b079fa4ed182	6582	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
richardv	0:b079fa4ed182	6583
richardv	0:b079fa4ed182	6584	/****************** Bits definition for RTC_TSTR register ***************/
richardv	0:b079fa4ed182	6585	#define RTC_TSTR_PM ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	6586	#define RTC_TSTR_HT ((uint32_t)0x00300000)
richardv	0:b079fa4ed182	6587	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	6588	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	6589	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
richardv	0:b079fa4ed182	6590	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
richardv	0:b079fa4ed182	6591	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
richardv	0:b079fa4ed182	6592	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	6593	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
richardv	0:b079fa4ed182	6594	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
richardv	0:b079fa4ed182	6595	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	6596	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6597	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6598	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
richardv	0:b079fa4ed182	6599	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6600	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	6601	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	6602	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	6603	#define RTC_TSTR_ST ((uint32_t)0x00000070)
richardv	0:b079fa4ed182	6604	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6605	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6606	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	6607	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
richardv	0:b079fa4ed182	6608	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6609	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6610	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6611	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6612
richardv	0:b079fa4ed182	6613	/****************** Bits definition for RTC_TSDR register ***************/
richardv	0:b079fa4ed182	6614	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
richardv	0:b079fa4ed182	6615	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6616	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6617	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	6618	#define RTC_TSDR_MT ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	6619	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
richardv	0:b079fa4ed182	6620	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6621	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	6622	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	6623	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	6624	#define RTC_TSDR_DT ((uint32_t)0x00000030)
richardv	0:b079fa4ed182	6625	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6626	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6627	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
richardv	0:b079fa4ed182	6628	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6629	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6630	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6631	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6632
richardv	0:b079fa4ed182	6633	/****************** Bits definition for RTC_TSSSR register **************/
richardv	0:b079fa4ed182	6634	#define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
richardv	0:b079fa4ed182	6635
richardv	0:b079fa4ed182	6636	/****************** Bits definition for RTC_CAL register ***************/
richardv	0:b079fa4ed182	6637	#define RTC_CALR_CALP ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	6638	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6639	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6640	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
richardv	0:b079fa4ed182	6641	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6642	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6643	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6644	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6645	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6646	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6647	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	6648	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	6649	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6650
richardv	0:b079fa4ed182	6651	/****************** Bits definition for RTC_TAFCR register **************/
richardv	0:b079fa4ed182	6652	#define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
richardv	0:b079fa4ed182	6653	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
richardv	0:b079fa4ed182	6654	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
richardv	0:b079fa4ed182	6655	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	6656	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
richardv	0:b079fa4ed182	6657	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
richardv	0:b079fa4ed182	6658	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
richardv	0:b079fa4ed182	6659	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	6660	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
richardv	0:b079fa4ed182	6661	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
richardv	0:b079fa4ed182	6662	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
richardv	0:b079fa4ed182	6663	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
richardv	0:b079fa4ed182	6664	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
richardv	0:b079fa4ed182	6665	#define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
richardv	0:b079fa4ed182	6666	#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
richardv	0:b079fa4ed182	6667	#define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
richardv	0:b079fa4ed182	6668	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
richardv	0:b079fa4ed182	6669	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
richardv	0:b079fa4ed182	6670	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
richardv	0:b079fa4ed182	6671	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
richardv	0:b079fa4ed182	6672
richardv	0:b079fa4ed182	6673	/****************** Bits definition for RTC_ALRMASSR register ***********/
richardv	0:b079fa4ed182	6674	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
richardv	0:b079fa4ed182	6675	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	6676	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	6677	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
richardv	0:b079fa4ed182	6678	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
richardv	0:b079fa4ed182	6679	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
richardv	0:b079fa4ed182	6680
richardv	0:b079fa4ed182	6681	/****************** Bits definition for RTC_ALRMBSSR register ***********/
richardv	0:b079fa4ed182	6682	#define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
richardv	0:b079fa4ed182	6683	#define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	6684	#define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	6685	#define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
richardv	0:b079fa4ed182	6686	#define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
richardv	0:b079fa4ed182	6687	#define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
richardv	0:b079fa4ed182	6688
richardv	0:b079fa4ed182	6689	/****************** Bits definition for RTC_BKP0R register **************/
richardv	0:b079fa4ed182	6690	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6691
richardv	0:b079fa4ed182	6692	/****************** Bits definition for RTC_BKP1R register **************/
richardv	0:b079fa4ed182	6693	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6694
richardv	0:b079fa4ed182	6695	/****************** Bits definition for RTC_BKP2R register **************/
richardv	0:b079fa4ed182	6696	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6697
richardv	0:b079fa4ed182	6698	/****************** Bits definition for RTC_BKP3R register **************/
richardv	0:b079fa4ed182	6699	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6700
richardv	0:b079fa4ed182	6701	/****************** Bits definition for RTC_BKP4R register **************/
richardv	0:b079fa4ed182	6702	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6703
richardv	0:b079fa4ed182	6704	/****************** Bits definition for RTC_BKP5R register **************/
richardv	0:b079fa4ed182	6705	#define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6706
richardv	0:b079fa4ed182	6707	/****************** Bits definition for RTC_BKP6R register **************/
richardv	0:b079fa4ed182	6708	#define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6709
richardv	0:b079fa4ed182	6710	/****************** Bits definition for RTC_BKP7R register **************/
richardv	0:b079fa4ed182	6711	#define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6712
richardv	0:b079fa4ed182	6713	/****************** Bits definition for RTC_BKP8R register **************/
richardv	0:b079fa4ed182	6714	#define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6715
richardv	0:b079fa4ed182	6716	/****************** Bits definition for RTC_BKP9R register **************/
richardv	0:b079fa4ed182	6717	#define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6718
richardv	0:b079fa4ed182	6719	/****************** Bits definition for RTC_BKP10R register *************/
richardv	0:b079fa4ed182	6720	#define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6721
richardv	0:b079fa4ed182	6722	/****************** Bits definition for RTC_BKP11R register *************/
richardv	0:b079fa4ed182	6723	#define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6724
richardv	0:b079fa4ed182	6725	/****************** Bits definition for RTC_BKP12R register *************/
richardv	0:b079fa4ed182	6726	#define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6727
richardv	0:b079fa4ed182	6728	/****************** Bits definition for RTC_BKP13R register *************/
richardv	0:b079fa4ed182	6729	#define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6730
richardv	0:b079fa4ed182	6731	/****************** Bits definition for RTC_BKP14R register *************/
richardv	0:b079fa4ed182	6732	#define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6733
richardv	0:b079fa4ed182	6734	/****************** Bits definition for RTC_BKP15R register *************/
richardv	0:b079fa4ed182	6735	#define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
richardv	0:b079fa4ed182	6736
richardv	0:b079fa4ed182	6737	/******************************************************************************/
richardv	0:b079fa4ed182	6738	/* */
richardv	0:b079fa4ed182	6739	/* Serial Peripheral Interface (SPI) */
richardv	0:b079fa4ed182	6740	/* */
richardv	0:b079fa4ed182	6741	/******************************************************************************/
richardv	0:b079fa4ed182	6742	/***************** Bit definition for SPI_CR1 register ******************/
richardv	0:b079fa4ed182	6743	#define SPI_CR1_CPHA ((uint16_t)0x0001) /!< Clock Phase /
richardv	0:b079fa4ed182	6744	#define SPI_CR1_CPOL ((uint16_t)0x0002) /!< Clock Polarity /
richardv	0:b079fa4ed182	6745	#define SPI_CR1_MSTR ((uint16_t)0x0004) /!< Master Selection /
richardv	0:b079fa4ed182	6746
richardv	0:b079fa4ed182	6747	#define SPI_CR1_BR ((uint16_t)0x0038) /!< BR[2:0] bits (Baud Rate Control) /
richardv	0:b079fa4ed182	6748	#define SPI_CR1_BR_0 ((uint16_t)0x0008) /!< Bit 0 /
richardv	0:b079fa4ed182	6749	#define SPI_CR1_BR_1 ((uint16_t)0x0010) /!< Bit 1 /
richardv	0:b079fa4ed182	6750	#define SPI_CR1_BR_2 ((uint16_t)0x0020) /!< Bit 2 /
richardv	0:b079fa4ed182	6751
richardv	0:b079fa4ed182	6752	#define SPI_CR1_SPE ((uint16_t)0x0040) /!< SPI Enable /
richardv	0:b079fa4ed182	6753	#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /!< Frame Format /
richardv	0:b079fa4ed182	6754	#define SPI_CR1_SSI ((uint16_t)0x0100) /!< Internal slave select /
richardv	0:b079fa4ed182	6755	#define SPI_CR1_SSM ((uint16_t)0x0200) /!< Software slave management /
richardv	0:b079fa4ed182	6756	#define SPI_CR1_RXONLY ((uint16_t)0x0400) /!< Receive only /
richardv	0:b079fa4ed182	6757	#define SPI_CR1_CRCL ((uint16_t)0x0800) /!< CRC Length /
richardv	0:b079fa4ed182	6758	#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /!< Transmit CRC next /
richardv	0:b079fa4ed182	6759	#define SPI_CR1_CRCEN ((uint16_t)0x2000) /!< Hardware CRC calculation enable /
richardv	0:b079fa4ed182	6760	#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /!< Output enable in bidirectional mode /
richardv	0:b079fa4ed182	6761	#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /!< Bidirectional data mode enable /
richardv	0:b079fa4ed182	6762
richardv	0:b079fa4ed182	6763	/***************** Bit definition for SPI_CR2 register ******************/
richardv	0:b079fa4ed182	6764	#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /!< Rx Buffer DMA Enable /
richardv	0:b079fa4ed182	6765	#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /!< Tx Buffer DMA Enable /
richardv	0:b079fa4ed182	6766	#define SPI_CR2_SSOE ((uint16_t)0x0004) /!< SS Output Enable /
richardv	0:b079fa4ed182	6767	#define SPI_CR2_NSSP ((uint16_t)0x0008) /!< NSS pulse management Enable /
richardv	0:b079fa4ed182	6768	#define SPI_CR2_FRF ((uint16_t)0x0010) /!< Frame Format Enable /
richardv	0:b079fa4ed182	6769	#define SPI_CR2_ERRIE ((uint16_t)0x0020) /!< Error Interrupt Enable /
richardv	0:b079fa4ed182	6770	#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /!< RX buffer Not Empty Interrupt Enable /
richardv	0:b079fa4ed182	6771	#define SPI_CR2_TXEIE ((uint16_t)0x0080) /!< Tx buffer Empty Interrupt Enable /
richardv	0:b079fa4ed182	6772
richardv	0:b079fa4ed182	6773	#define SPI_CR2_DS ((uint16_t)0x0F00) /!< DS[3:0] Data Size /
richardv	0:b079fa4ed182	6774	#define SPI_CR2_DS_0 ((uint16_t)0x0100) /!< Bit 0 /
richardv	0:b079fa4ed182	6775	#define SPI_CR2_DS_1 ((uint16_t)0x0200) /!< Bit 1 /
richardv	0:b079fa4ed182	6776	#define SPI_CR2_DS_2 ((uint16_t)0x0400) /!< Bit 2 /
richardv	0:b079fa4ed182	6777	#define SPI_CR2_DS_3 ((uint16_t)0x0800) /!< Bit 3 /
richardv	0:b079fa4ed182	6778
richardv	0:b079fa4ed182	6779	#define SPI_CR2_FRXTH ((uint16_t)0x1000) /!< FIFO reception Threshold /
richardv	0:b079fa4ed182	6780	#define SPI_CR2_LDMARX ((uint16_t)0x2000) /!< Last DMA transfer for reception /
richardv	0:b079fa4ed182	6781	#define SPI_CR2_LDMATX ((uint16_t)0x4000) /!< Last DMA transfer for transmission /
richardv	0:b079fa4ed182	6782
richardv	0:b079fa4ed182	6783	/****************** Bit definition for SPI_SR register ******************/
richardv	0:b079fa4ed182	6784	#define SPI_SR_RXNE ((uint16_t)0x0001) /!< Receive buffer Not Empty /
richardv	0:b079fa4ed182	6785	#define SPI_SR_TXE ((uint16_t)0x0002) /!< Transmit buffer Empty /
richardv	0:b079fa4ed182	6786	#define SPI_SR_CRCERR ((uint16_t)0x0010) /!< CRC Error flag /
richardv	0:b079fa4ed182	6787	#define SPI_SR_MODF ((uint16_t)0x0020) /!< Mode fault /
richardv	0:b079fa4ed182	6788	#define SPI_SR_OVR ((uint16_t)0x0040) /!< Overrun flag /
richardv	0:b079fa4ed182	6789	#define SPI_SR_BSY ((uint16_t)0x0080) /!< Busy flag /
richardv	0:b079fa4ed182	6790	#define SPI_SR_FRE ((uint16_t)0x0100) /!< TI frame format error /
richardv	0:b079fa4ed182	6791	#define SPI_SR_FRLVL ((uint16_t)0x0600) /!< FIFO Reception Level /
richardv	0:b079fa4ed182	6792	#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /!< Bit 0 /
richardv	0:b079fa4ed182	6793	#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /!< Bit 1 /
richardv	0:b079fa4ed182	6794	#define SPI_SR_FTLVL ((uint16_t)0x1800) /!< FIFO Transmission Level /
richardv	0:b079fa4ed182	6795	#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /!< Bit 0 /
richardv	0:b079fa4ed182	6796	#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /!< Bit 1 /
richardv	0:b079fa4ed182	6797
richardv	0:b079fa4ed182	6798	/****************** Bit definition for SPI_DR register ******************/
richardv	0:b079fa4ed182	6799	#define SPI_DR_DR ((uint16_t)0xFFFF) /!< Data Register /
richardv	0:b079fa4ed182	6800
richardv	0:b079fa4ed182	6801	/***************** Bit definition for SPI_CRCPR register ****************/
richardv	0:b079fa4ed182	6802	#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /!< CRC polynomial register /
richardv	0:b079fa4ed182	6803
richardv	0:b079fa4ed182	6804	/**************** Bit definition for SPI_RXCRCR register ****************/
richardv	0:b079fa4ed182	6805	#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /!< Rx CRC Register /
richardv	0:b079fa4ed182	6806
richardv	0:b079fa4ed182	6807	/**************** Bit definition for SPI_TXCRCR register ****************/
richardv	0:b079fa4ed182	6808	#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /!< Tx CRC Register /
richardv	0:b079fa4ed182	6809
richardv	0:b079fa4ed182	6810	/**************** Bit definition for SPI_I2SCFGR register ***************/
richardv	0:b079fa4ed182	6811	#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /!<Channel length (number of bits per audio channel) /
richardv	0:b079fa4ed182	6812
richardv	0:b079fa4ed182	6813	#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /!<DATLEN[1:0] bits (Data length to be transferred) /
richardv	0:b079fa4ed182	6814	#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /!<Bit 0 /
richardv	0:b079fa4ed182	6815	#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /!<Bit 1 /
richardv	0:b079fa4ed182	6816
richardv	0:b079fa4ed182	6817	#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /!<steady state clock polarity /
richardv	0:b079fa4ed182	6818
richardv	0:b079fa4ed182	6819	#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /!<I2SSTD[1:0] bits (I2S standard selection) /
richardv	0:b079fa4ed182	6820	#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /!<Bit 0 /
richardv	0:b079fa4ed182	6821	#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /!<Bit 1 /
richardv	0:b079fa4ed182	6822
richardv	0:b079fa4ed182	6823	#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /!<PCM frame synchronization /
richardv	0:b079fa4ed182	6824
richardv	0:b079fa4ed182	6825	#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
richardv	0:b079fa4ed182	6826	#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /!<Bit 0 /
richardv	0:b079fa4ed182	6827	#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /!<Bit 1 /
richardv	0:b079fa4ed182	6828
richardv	0:b079fa4ed182	6829	#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /!<I2S Enable /
richardv	0:b079fa4ed182	6830	#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /!<I2S mode selection /
richardv	0:b079fa4ed182	6831
richardv	0:b079fa4ed182	6832	/**************** Bit definition for SPI_I2SPR register *****************/
richardv	0:b079fa4ed182	6833	#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /!<I2S Linear prescaler /
richardv	0:b079fa4ed182	6834	#define SPI_I2SPR_ODD ((uint16_t)0x0100) /!<Odd factor for the prescaler /
richardv	0:b079fa4ed182	6835	#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /!<Master Clock Output Enable /
richardv	0:b079fa4ed182	6836
richardv	0:b079fa4ed182	6837	/******************************************************************************/
richardv	0:b079fa4ed182	6838	/* */
richardv	0:b079fa4ed182	6839	/* System Configuration(SYSCFG) */
richardv	0:b079fa4ed182	6840	/* */
richardv	0:b079fa4ed182	6841	/******************************************************************************/
richardv	0:b079fa4ed182	6842	/*************** Bit definition for SYSCFG_CFGR1 register ***************/
richardv	0:b079fa4ed182	6843	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
richardv	0:b079fa4ed182	6844	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< Bit 0 /
richardv	0:b079fa4ed182	6845	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< Bit 1 /
richardv	0:b079fa4ed182	6846	#define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /!< USB interrupt remap /
richardv	0:b079fa4ed182	6847	#define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /!< Timer 1 ITR3 selection /
richardv	0:b079fa4ed182	6848	#define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /!< DAC1 Trigger1 remap /
richardv	0:b079fa4ed182	6849	#define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /!< ADC2 and ADC4 DMA remap /
richardv	0:b079fa4ed182	6850	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
richardv	0:b079fa4ed182	6851	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
richardv	0:b079fa4ed182	6852	#define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /!< Timer 6 / DAC1 CH1 DMA remap /
richardv	0:b079fa4ed182	6853	#define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /!< Timer 7 / DAC1 CH2 DMA remap /
richardv	0:b079fa4ed182	6854	#define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /!< DAC2 CH1 DMA remap /
richardv	0:b079fa4ed182	6855	#define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
richardv	0:b079fa4ed182	6856	#define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
richardv	0:b079fa4ed182	6857	#define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
richardv	0:b079fa4ed182	6858	#define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
richardv	0:b079fa4ed182	6859	#define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /!< I2C1 Fast mode plus /
richardv	0:b079fa4ed182	6860	#define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /!< I2C2 Fast mode plus /
richardv	0:b079fa4ed182	6861	#define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /!< Encoder Mode /
richardv	0:b079fa4ed182	6862	#define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /!< Encoder Mode 0 /
richardv	0:b079fa4ed182	6863	#define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /!< Encoder Mode 1 /
richardv	0:b079fa4ed182	6864	#define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /!< Floating Point Unit Interrupt Enable /
richardv	0:b079fa4ed182	6865	#define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /!< Floating Point Unit Interrupt Enable 0 /
richardv	0:b079fa4ed182	6866	#define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /!< Floating Point Unit Interrupt Enable 1 /
richardv	0:b079fa4ed182	6867	#define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /!< Floating Point Unit Interrupt Enable 2 /
richardv	0:b079fa4ed182	6868	#define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /!< Floating Point Unit Interrupt Enable 3 /
richardv	0:b079fa4ed182	6869	#define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /!< Floating Point Unit Interrupt Enable 4 /
richardv	0:b079fa4ed182	6870	#define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /!< Floating Point Unit Interrupt Enable 5 /
richardv	0:b079fa4ed182	6871	#define SYSCFG_CFGR1_DAC_TRIG_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP /!< Old define maintained for legacy purpose /
richardv	0:b079fa4ed182	6872	#define SYSCFG_CFGR1_TIM6DAC1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /!< Old define maintained for legacy purpose /
richardv	0:b079fa4ed182	6873	#define SYSCFG_CFGR1_TIM7DAC2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /!< Old define maintained for legacy purpose /
richardv	0:b079fa4ed182	6874	/*************** Bit definition for SYSCFG_RCR register *****************/
richardv	0:b079fa4ed182	6875	#define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /!< ICODE SRAM Write protection page 0 /
richardv	0:b079fa4ed182	6876	#define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /!< ICODE SRAM Write protection page 1 /
richardv	0:b079fa4ed182	6877	#define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /!< ICODE SRAM Write protection page 2 /
richardv	0:b079fa4ed182	6878	#define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /!< ICODE SRAM Write protection page 3 /
richardv	0:b079fa4ed182	6879	#define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /!< ICODE SRAM Write protection page 4 /
richardv	0:b079fa4ed182	6880	#define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /!< ICODE SRAM Write protection page 5 /
richardv	0:b079fa4ed182	6881	#define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /!< ICODE SRAM Write protection page 6 /
richardv	0:b079fa4ed182	6882	#define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /!< ICODE SRAM Write protection page 7 /
richardv	0:b079fa4ed182	6883
richardv	0:b079fa4ed182	6884	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
richardv	0:b079fa4ed182	6885	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
richardv	0:b079fa4ed182	6886	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
richardv	0:b079fa4ed182	6887	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
richardv	0:b079fa4ed182	6888	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
richardv	0:b079fa4ed182	6889
richardv	0:b079fa4ed182	6890	/**
richardv	0:b079fa4ed182	6891	* @brief EXTI0 configuration
richardv	0:b079fa4ed182	6892	*/
richardv	0:b079fa4ed182	6893	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
richardv	0:b079fa4ed182	6894	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
richardv	0:b079fa4ed182	6895	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
richardv	0:b079fa4ed182	6896	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
richardv	0:b079fa4ed182	6897	#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /!< PE[0] pin /
richardv	0:b079fa4ed182	6898	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!< PF[0] pin /
richardv	0:b079fa4ed182	6899
richardv	0:b079fa4ed182	6900	/**
richardv	0:b079fa4ed182	6901	* @brief EXTI1 configuration
richardv	0:b079fa4ed182	6902	*/
richardv	0:b079fa4ed182	6903	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
richardv	0:b079fa4ed182	6904	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
richardv	0:b079fa4ed182	6905	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
richardv	0:b079fa4ed182	6906	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
richardv	0:b079fa4ed182	6907	#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /!< PE[1] pin /
richardv	0:b079fa4ed182	6908	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!< PF[1] pin /
richardv	0:b079fa4ed182	6909
richardv	0:b079fa4ed182	6910	/**
richardv	0:b079fa4ed182	6911	* @brief EXTI2 configuration
richardv	0:b079fa4ed182	6912	*/
richardv	0:b079fa4ed182	6913	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
richardv	0:b079fa4ed182	6914	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
richardv	0:b079fa4ed182	6915	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
richardv	0:b079fa4ed182	6916	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
richardv	0:b079fa4ed182	6917	#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /!< PE[2] pin /
richardv	0:b079fa4ed182	6918	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!< PF[2] pin /
richardv	0:b079fa4ed182	6919
richardv	0:b079fa4ed182	6920	/**
richardv	0:b079fa4ed182	6921	* @brief EXTI3 configuration
richardv	0:b079fa4ed182	6922	*/
richardv	0:b079fa4ed182	6923	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
richardv	0:b079fa4ed182	6924	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
richardv	0:b079fa4ed182	6925	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
richardv	0:b079fa4ed182	6926	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
richardv	0:b079fa4ed182	6927	#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /!< PE[3] pin /
richardv	0:b079fa4ed182	6928
richardv	0:b079fa4ed182	6929	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
richardv	0:b079fa4ed182	6930	#define SYSCFG_EXTIRCR_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
richardv	0:b079fa4ed182	6931	#define SYSCFG_EXTIRCR_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
richardv	0:b079fa4ed182	6932	#define SYSCFG_EXTIRCR_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
richardv	0:b079fa4ed182	6933	#define SYSCFG_EXTIRCR_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
richardv	0:b079fa4ed182	6934
richardv	0:b079fa4ed182	6935	/**
richardv	0:b079fa4ed182	6936	* @brief EXTI4 configuration
richardv	0:b079fa4ed182	6937	*/
richardv	0:b079fa4ed182	6938	#define SYSCFG_EXTIRCR_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
richardv	0:b079fa4ed182	6939	#define SYSCFG_EXTIRCR_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
richardv	0:b079fa4ed182	6940	#define SYSCFG_EXTIRCR_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
richardv	0:b079fa4ed182	6941	#define SYSCFG_EXTIRCR_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
richardv	0:b079fa4ed182	6942	#define SYSCFG_EXTIRCR_EXTI4_PE ((uint16_t)0x0004) /!< PE[4] pin /
richardv	0:b079fa4ed182	6943	#define SYSCFG_EXTIRCR_EXTI4_PF ((uint16_t)0x0005) /!< PF[4] pin /
richardv	0:b079fa4ed182	6944
richardv	0:b079fa4ed182	6945	/**
richardv	0:b079fa4ed182	6946	* @brief EXTI5 configuration
richardv	0:b079fa4ed182	6947	*/
richardv	0:b079fa4ed182	6948	#define SYSCFG_EXTIRCR_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
richardv	0:b079fa4ed182	6949	#define SYSCFG_EXTIRCR_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
richardv	0:b079fa4ed182	6950	#define SYSCFG_EXTIRCR_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
richardv	0:b079fa4ed182	6951	#define SYSCFG_EXTIRCR_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
richardv	0:b079fa4ed182	6952	#define SYSCFG_EXTIRCR_EXTI5_PE ((uint16_t)0x0040) /!< PE[5] pin /
richardv	0:b079fa4ed182	6953	#define SYSCFG_EXTIRCR_EXTI5_PF ((uint16_t)0x0050) /!< PF[5] pin /
richardv	0:b079fa4ed182	6954
richardv	0:b079fa4ed182	6955	/**
richardv	0:b079fa4ed182	6956	* @brief EXTI6 configuration
richardv	0:b079fa4ed182	6957	*/
richardv	0:b079fa4ed182	6958	#define SYSCFG_EXTIRCR_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
richardv	0:b079fa4ed182	6959	#define SYSCFG_EXTIRCR_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
richardv	0:b079fa4ed182	6960	#define SYSCFG_EXTIRCR_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
richardv	0:b079fa4ed182	6961	#define SYSCFG_EXTIRCR_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
richardv	0:b079fa4ed182	6962	#define SYSCFG_EXTIRCR_EXTI6_PE ((uint16_t)0x0400) /!< PE[6] pin /
richardv	0:b079fa4ed182	6963	#define SYSCFG_EXTIRCR_EXTI6_PF ((uint16_t)0x0500) /!< PF[6] pin /
richardv	0:b079fa4ed182	6964
richardv	0:b079fa4ed182	6965	/**
richardv	0:b079fa4ed182	6966	* @brief EXTI7 configuration
richardv	0:b079fa4ed182	6967	*/
richardv	0:b079fa4ed182	6968	#define SYSCFG_EXTIRCR_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
richardv	0:b079fa4ed182	6969	#define SYSCFG_EXTIRCR_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
richardv	0:b079fa4ed182	6970	#define SYSCFG_EXTIRCR_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
richardv	0:b079fa4ed182	6971	#define SYSCFG_EXTIRCR_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
richardv	0:b079fa4ed182	6972	#define SYSCFG_EXTIRCR_EXTI7_PE ((uint16_t)0x4000) /!< PE[7] pin /
richardv	0:b079fa4ed182	6973
richardv	0:b079fa4ed182	6974	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
richardv	0:b079fa4ed182	6975	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
richardv	0:b079fa4ed182	6976	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
richardv	0:b079fa4ed182	6977	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
richardv	0:b079fa4ed182	6978	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
richardv	0:b079fa4ed182	6979
richardv	0:b079fa4ed182	6980	/**
richardv	0:b079fa4ed182	6981	* @brief EXTI8 configuration
richardv	0:b079fa4ed182	6982	*/
richardv	0:b079fa4ed182	6983	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
richardv	0:b079fa4ed182	6984	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
richardv	0:b079fa4ed182	6985	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
richardv	0:b079fa4ed182	6986	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
richardv	0:b079fa4ed182	6987	#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /!< PE[8] pin /
richardv	0:b079fa4ed182	6988
richardv	0:b079fa4ed182	6989	/**
richardv	0:b079fa4ed182	6990	* @brief EXTI9 configuration
richardv	0:b079fa4ed182	6991	*/
richardv	0:b079fa4ed182	6992	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
richardv	0:b079fa4ed182	6993	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
richardv	0:b079fa4ed182	6994	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
richardv	0:b079fa4ed182	6995	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
richardv	0:b079fa4ed182	6996	#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /!< PE[9] pin /
richardv	0:b079fa4ed182	6997	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!< PF[9] pin /
richardv	0:b079fa4ed182	6998
richardv	0:b079fa4ed182	6999	/**
richardv	0:b079fa4ed182	7000	* @brief EXTI10 configuration
richardv	0:b079fa4ed182	7001	*/
richardv	0:b079fa4ed182	7002	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
richardv	0:b079fa4ed182	7003	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
richardv	0:b079fa4ed182	7004	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
richardv	0:b079fa4ed182	7005	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PD[10] pin /
richardv	0:b079fa4ed182	7006	#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /!< PE[10] pin /
richardv	0:b079fa4ed182	7007	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!< PF[10] pin /
richardv	0:b079fa4ed182	7008
richardv	0:b079fa4ed182	7009	/**
richardv	0:b079fa4ed182	7010	* @brief EXTI11 configuration
richardv	0:b079fa4ed182	7011	*/
richardv	0:b079fa4ed182	7012	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
richardv	0:b079fa4ed182	7013	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
richardv	0:b079fa4ed182	7014	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
richardv	0:b079fa4ed182	7015	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
richardv	0:b079fa4ed182	7016	#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /!< PE[11] pin /
richardv	0:b079fa4ed182	7017
richardv	0:b079fa4ed182	7018	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
richardv	0:b079fa4ed182	7019	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
richardv	0:b079fa4ed182	7020	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
richardv	0:b079fa4ed182	7021	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
richardv	0:b079fa4ed182	7022	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
richardv	0:b079fa4ed182	7023
richardv	0:b079fa4ed182	7024	/**
richardv	0:b079fa4ed182	7025	* @brief EXTI12 configuration
richardv	0:b079fa4ed182	7026	*/
richardv	0:b079fa4ed182	7027	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
richardv	0:b079fa4ed182	7028	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
richardv	0:b079fa4ed182	7029	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
richardv	0:b079fa4ed182	7030	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
richardv	0:b079fa4ed182	7031	#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /!< PE[12] pin /
richardv	0:b079fa4ed182	7032
richardv	0:b079fa4ed182	7033	/**
richardv	0:b079fa4ed182	7034	* @brief EXTI13 configuration
richardv	0:b079fa4ed182	7035	*/
richardv	0:b079fa4ed182	7036	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
richardv	0:b079fa4ed182	7037	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
richardv	0:b079fa4ed182	7038	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
richardv	0:b079fa4ed182	7039	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
richardv	0:b079fa4ed182	7040	#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /!< PE[13] pin /
richardv	0:b079fa4ed182	7041
richardv	0:b079fa4ed182	7042	/**
richardv	0:b079fa4ed182	7043	* @brief EXTI14 configuration
richardv	0:b079fa4ed182	7044	*/
richardv	0:b079fa4ed182	7045	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
richardv	0:b079fa4ed182	7046	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
richardv	0:b079fa4ed182	7047	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
richardv	0:b079fa4ed182	7048	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
richardv	0:b079fa4ed182	7049	#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /!< PE[14] pin /
richardv	0:b079fa4ed182	7050
richardv	0:b079fa4ed182	7051	/**
richardv	0:b079fa4ed182	7052	* @brief EXTI15 configuration
richardv	0:b079fa4ed182	7053	*/
richardv	0:b079fa4ed182	7054	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
richardv	0:b079fa4ed182	7055	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
richardv	0:b079fa4ed182	7056	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
richardv	0:b079fa4ed182	7057	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
richardv	0:b079fa4ed182	7058	#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /!< PE[15] pin /
richardv	0:b079fa4ed182	7059
richardv	0:b079fa4ed182	7060	/*************** Bit definition for SYSCFG_CFGR2 register ***************/
richardv	0:b079fa4ed182	7061	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface /
richardv	0:b079fa4ed182	7062	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 /
richardv	0:b079fa4ed182	7063	#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 /
richardv	0:b079fa4ed182	7064	#define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /!< Disables the address parity check on RAM /
richardv	0:b079fa4ed182	7065	#define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /!< SRAM Parity error flag /
richardv	0:b079fa4ed182	7066
richardv	0:b079fa4ed182	7067	/*************** Bit definition for SYSCFG_CFGR3 register ***************/
richardv	0:b079fa4ed182	7068	#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /!< SPI1 RX DMA remap /
richardv	0:b079fa4ed182	7069	#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /!< SPI1 RX DMA remap bit 0 /
richardv	0:b079fa4ed182	7070	#define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /!< SPI1 RX DMA remap bit 1 /
richardv	0:b079fa4ed182	7071	#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /!< SPI1 TX DMA remap /
richardv	0:b079fa4ed182	7072	#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /!< SPI1 TX DMA remap bit 0 /
richardv	0:b079fa4ed182	7073	#define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /!< SPI1 TX DMA remap bit 1 /
richardv	0:b079fa4ed182	7074	#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /!< I2C1 RX DMA remap /
richardv	0:b079fa4ed182	7075	#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /!< I2C1 RX DMA remap bit 0 /
richardv	0:b079fa4ed182	7076	#define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /!< I2C1 RX DMA remap bit 1 /
richardv	0:b079fa4ed182	7077	#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /!< I2C1 RX DMA remap /
richardv	0:b079fa4ed182	7078	#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /!< I2C1 TX DMA remap bit 0 /
richardv	0:b079fa4ed182	7079	#define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /!< I2C1 TX DMA remap bit 1 /
richardv	0:b079fa4ed182	7080	#define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /!< ADC2 DMA remap /
richardv	0:b079fa4ed182	7081	#define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /!< ADC2 DMA remap bit 0 /
richardv	0:b079fa4ed182	7082	#define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /!< ADC2 DMA remap bit 1 /
richardv	0:b079fa4ed182	7083	#define SYSCFG_CFGR3_DAC1_TRG3_RMP ((uint32_t)0x00010000) /!< DAC1 TRG3 remap /
richardv	0:b079fa4ed182	7084	#define SYSCFG_CFGR3_DAC1_TRG5_RMP ((uint32_t)0x00020000) /!< DAC1 TRG5 remap /
richardv	0:b079fa4ed182	7085
richardv	0:b079fa4ed182	7086	/******************************************************************************/
richardv	0:b079fa4ed182	7087	/* */
richardv	0:b079fa4ed182	7088	/* TIM */
richardv	0:b079fa4ed182	7089	/* */
richardv	0:b079fa4ed182	7090	/******************************************************************************/
richardv	0:b079fa4ed182	7091	/***************** Bit definition for TIM_CR1 register ******************/
richardv	0:b079fa4ed182	7092	#define TIM_CR1_CEN ((uint16_t)0x0001) /!<Counter enable /
richardv	0:b079fa4ed182	7093	#define TIM_CR1_UDIS ((uint16_t)0x0002) /!<Update disable /
richardv	0:b079fa4ed182	7094	#define TIM_CR1_URS ((uint16_t)0x0004) /!<Update request source /
richardv	0:b079fa4ed182	7095	#define TIM_CR1_OPM ((uint16_t)0x0008) /!<One pulse mode /
richardv	0:b079fa4ed182	7096	#define TIM_CR1_DIR ((uint16_t)0x0010) /!<Direction /
richardv	0:b079fa4ed182	7097
richardv	0:b079fa4ed182	7098	#define TIM_CR1_CMS ((uint16_t)0x0060) /!<CMS[1:0] bits (Center-aligned mode selection) /
richardv	0:b079fa4ed182	7099	#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /!<Bit 0 /
richardv	0:b079fa4ed182	7100	#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /!<Bit 1 /
richardv	0:b079fa4ed182	7101
richardv	0:b079fa4ed182	7102	#define TIM_CR1_ARPE ((uint16_t)0x0080) /!<Auto-reload preload enable /
richardv	0:b079fa4ed182	7103
richardv	0:b079fa4ed182	7104	#define TIM_CR1_CKD ((uint16_t)0x0300) /!<CKD[1:0] bits (clock division) /
richardv	0:b079fa4ed182	7105	#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /!<Bit 0 /
richardv	0:b079fa4ed182	7106	#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /!<Bit 1 /
richardv	0:b079fa4ed182	7107
richardv	0:b079fa4ed182	7108	#define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /!<Update interrupt flag remap /
richardv	0:b079fa4ed182	7109
richardv	0:b079fa4ed182	7110	/***************** Bit definition for TIM_CR2 register ******************/
richardv	0:b079fa4ed182	7111	#define TIM_CR2_CCPC ((uint32_t)0x00000001) /!<Capture/Compare Preloaded Control /
richardv	0:b079fa4ed182	7112	#define TIM_CR2_CCUS ((uint32_t)0x00000004) /!<Capture/Compare Control Update Selection /
richardv	0:b079fa4ed182	7113	#define TIM_CR2_CCDS ((uint32_t)0x00000008) /!<Capture/Compare DMA Selection /
richardv	0:b079fa4ed182	7114
richardv	0:b079fa4ed182	7115	#define TIM_CR2_MMS ((uint32_t)0x00000070) /!<MMS[2:0] bits (Master Mode Selection) /
richardv	0:b079fa4ed182	7116	#define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /!<Bit 0 /
richardv	0:b079fa4ed182	7117	#define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /!<Bit 1 /
richardv	0:b079fa4ed182	7118	#define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /!<Bit 2 /
richardv	0:b079fa4ed182	7119
richardv	0:b079fa4ed182	7120	#define TIM_CR2_TI1S ((uint32_t)0x00000080) /!<TI1 Selection /
richardv	0:b079fa4ed182	7121	#define TIM_CR2_OIS1 ((uint32_t)0x00000100) /!<Output Idle state 1 (OC1 output) /
richardv	0:b079fa4ed182	7122	#define TIM_CR2_OIS1N ((uint32_t)0x00000200) /!<Output Idle state 1 (OC1N output) /
richardv	0:b079fa4ed182	7123	#define TIM_CR2_OIS2 ((uint32_t)0x00000400) /!<Output Idle state 2 (OC2 output) /
richardv	0:b079fa4ed182	7124	#define TIM_CR2_OIS2N ((uint32_t)0x00000800) /!<Output Idle state 2 (OC2N output) /
richardv	0:b079fa4ed182	7125	#define TIM_CR2_OIS3 ((uint32_t)0x00001000) /!<Output Idle state 3 (OC3 output) /
richardv	0:b079fa4ed182	7126	#define TIM_CR2_OIS3N ((uint32_t)0x00002000) /!<Output Idle state 3 (OC3N output) /
richardv	0:b079fa4ed182	7127	#define TIM_CR2_OIS4 ((uint32_t)0x00004000) /!<Output Idle state 4 (OC4 output) /
richardv	0:b079fa4ed182	7128	#define TIM_CR2_OIS5 ((uint32_t)0x00010000) /!<Output Idle state 4 (OC4 output) /
richardv	0:b079fa4ed182	7129	#define TIM_CR2_OIS6 ((uint32_t)0x00020000) /!<Output Idle state 4 (OC4 output) /
richardv	0:b079fa4ed182	7130
richardv	0:b079fa4ed182	7131	#define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /!<MMS[2:0] bits (Master Mode Selection) /
richardv	0:b079fa4ed182	7132	#define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /!<Bit 0 /
richardv	0:b079fa4ed182	7133	#define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /!<Bit 1 /
richardv	0:b079fa4ed182	7134	#define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /!<Bit 2 /
richardv	0:b079fa4ed182	7135	#define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /!<Bit 2 /
richardv	0:b079fa4ed182	7136
richardv	0:b079fa4ed182	7137	/***************** Bit definition for TIM_SMCR register *****************/
richardv	0:b079fa4ed182	7138	#define TIM_SMCR_SMS ((uint32_t)0x00010007) /!<SMS[2:0] bits (Slave mode selection) /
richardv	0:b079fa4ed182	7139	#define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /!<Bit 0 /
richardv	0:b079fa4ed182	7140	#define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /!<Bit 1 /
richardv	0:b079fa4ed182	7141	#define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /!<Bit 2 /
richardv	0:b079fa4ed182	7142	#define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /!<Bit 3 /
richardv	0:b079fa4ed182	7143
richardv	0:b079fa4ed182	7144	#define TIM_SMCR_OCCS ((uint32_t)0x00000008) /!< OCREF clear selection /
richardv	0:b079fa4ed182	7145
richardv	0:b079fa4ed182	7146	#define TIM_SMCR_TS ((uint32_t)0x00000070) /!<TS[2:0] bits (Trigger selection) /
richardv	0:b079fa4ed182	7147	#define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /!<Bit 0 /
richardv	0:b079fa4ed182	7148	#define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /!<Bit 1 /
richardv	0:b079fa4ed182	7149	#define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /!<Bit 2 /
richardv	0:b079fa4ed182	7150
richardv	0:b079fa4ed182	7151	#define TIM_SMCR_MSM ((uint32_t)0x00000080) /!<Master/slave mode /
richardv	0:b079fa4ed182	7152
richardv	0:b079fa4ed182	7153	#define TIM_SMCR_ETF ((uint32_t)0x00000F00) /!<ETF[3:0] bits (External trigger filter) /
richardv	0:b079fa4ed182	7154	#define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /!<Bit 0 /
richardv	0:b079fa4ed182	7155	#define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /!<Bit 1 /
richardv	0:b079fa4ed182	7156	#define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /!<Bit 2 /
richardv	0:b079fa4ed182	7157	#define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /!<Bit 3 /
richardv	0:b079fa4ed182	7158
richardv	0:b079fa4ed182	7159	#define TIM_SMCR_ETPS ((uint32_t)0x00003000) /!<ETPS[1:0] bits (External trigger prescaler) /
richardv	0:b079fa4ed182	7160	#define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /!<Bit 0 /
richardv	0:b079fa4ed182	7161	#define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /!<Bit 1 /
richardv	0:b079fa4ed182	7162
richardv	0:b079fa4ed182	7163	#define TIM_SMCR_ECE ((uint32_t)0x00004000) /!<External clock enable /
richardv	0:b079fa4ed182	7164	#define TIM_SMCR_ETP ((uint32_t)0x00008000) /!<External trigger polarity /
richardv	0:b079fa4ed182	7165
richardv	0:b079fa4ed182	7166	/***************** Bit definition for TIM_DIER register *****************/
richardv	0:b079fa4ed182	7167	#define TIM_DIER_UIE ((uint16_t)0x0001) /!<Update interrupt enable /
richardv	0:b079fa4ed182	7168	#define TIM_DIER_CC1IE ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt enable /
richardv	0:b079fa4ed182	7169	#define TIM_DIER_CC2IE ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt enable /
richardv	0:b079fa4ed182	7170	#define TIM_DIER_CC3IE ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt enable /
richardv	0:b079fa4ed182	7171	#define TIM_DIER_CC4IE ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt enable /
richardv	0:b079fa4ed182	7172	#define TIM_DIER_COMIE ((uint16_t)0x0020) /!<COM interrupt enable /
richardv	0:b079fa4ed182	7173	#define TIM_DIER_TIE ((uint16_t)0x0040) /!<Trigger interrupt enable /
richardv	0:b079fa4ed182	7174	#define TIM_DIER_BIE ((uint16_t)0x0080) /!<Break interrupt enable /
richardv	0:b079fa4ed182	7175	#define TIM_DIER_UDE ((uint16_t)0x0100) /!<Update DMA request enable /
richardv	0:b079fa4ed182	7176	#define TIM_DIER_CC1DE ((uint16_t)0x0200) /!<Capture/Compare 1 DMA request enable /
richardv	0:b079fa4ed182	7177	#define TIM_DIER_CC2DE ((uint16_t)0x0400) /!<Capture/Compare 2 DMA request enable /
richardv	0:b079fa4ed182	7178	#define TIM_DIER_CC3DE ((uint16_t)0x0800) /!<Capture/Compare 3 DMA request enable /
richardv	0:b079fa4ed182	7179	#define TIM_DIER_CC4DE ((uint16_t)0x1000) /!<Capture/Compare 4 DMA request enable /
richardv	0:b079fa4ed182	7180	#define TIM_DIER_COMDE ((uint16_t)0x2000) /!<COM DMA request enable /
richardv	0:b079fa4ed182	7181	#define TIM_DIER_TDE ((uint16_t)0x4000) /!<Trigger DMA request enable /
richardv	0:b079fa4ed182	7182
richardv	0:b079fa4ed182	7183	/****************** Bit definition for TIM_SR register ******************/
richardv	0:b079fa4ed182	7184	#define TIM_SR_UIF ((uint32_t)0x00000001) /!<Update interrupt Flag /
richardv	0:b079fa4ed182	7185	#define TIM_SR_CC1IF ((uint32_t)0x00000002) /!<Capture/Compare 1 interrupt Flag /
richardv	0:b079fa4ed182	7186	#define TIM_SR_CC2IF ((uint32_t)0x00000004) /!<Capture/Compare 2 interrupt Flag /
richardv	0:b079fa4ed182	7187	#define TIM_SR_CC3IF ((uint32_t)0x00000008) /!<Capture/Compare 3 interrupt Flag /
richardv	0:b079fa4ed182	7188	#define TIM_SR_CC4IF ((uint32_t)0x00000010) /!<Capture/Compare 4 interrupt Flag /
richardv	0:b079fa4ed182	7189	#define TIM_SR_COMIF ((uint32_t)0x00000020) /!<COM interrupt Flag /
richardv	0:b079fa4ed182	7190	#define TIM_SR_TIF ((uint32_t)0x00000040) /!<Trigger interrupt Flag /
richardv	0:b079fa4ed182	7191	#define TIM_SR_BIF ((uint32_t)0x00000080) /!<Break interrupt Flag /
richardv	0:b079fa4ed182	7192	#define TIM_SR_B2IF ((uint32_t)0x00000100) /!<Break2 interrupt Flag /
richardv	0:b079fa4ed182	7193	#define TIM_SR_CC1OF ((uint32_t)0x00000200) /!<Capture/Compare 1 Over capture Flag /
richardv	0:b079fa4ed182	7194	#define TIM_SR_CC2OF ((uint32_t)0x00000400) /!<Capture/Compare 2 Over capture Flag /
richardv	0:b079fa4ed182	7195	#define TIM_SR_CC3OF ((uint32_t)0x00000800) /!<Capture/Compare 3 Over capture Flag /
richardv	0:b079fa4ed182	7196	#define TIM_SR_CC4OF ((uint32_t)0x00001000) /!<Capture/Compare 4 Over capture Flag /
richardv	0:b079fa4ed182	7197	#define TIM_SR_CC5IF ((uint32_t)0x00010000) /!<Capture/Compare 5 interrupt Flag /
richardv	0:b079fa4ed182	7198	#define TIM_SR_CC6IF ((uint32_t)0x00020000) /!<Capture/Compare 6 interrupt Flag /
richardv	0:b079fa4ed182	7199
richardv	0:b079fa4ed182	7200
richardv	0:b079fa4ed182	7201	/***************** Bit definition for TIM_EGR register ******************/
richardv	0:b079fa4ed182	7202	#define TIM_EGR_UG ((uint16_t)0x0001) /!<Update Generation /
richardv	0:b079fa4ed182	7203	#define TIM_EGR_CC1G ((uint16_t)0x0002) /!<Capture/Compare 1 Generation /
richardv	0:b079fa4ed182	7204	#define TIM_EGR_CC2G ((uint16_t)0x0004) /!<Capture/Compare 2 Generation /
richardv	0:b079fa4ed182	7205	#define TIM_EGR_CC3G ((uint16_t)0x0008) /!<Capture/Compare 3 Generation /
richardv	0:b079fa4ed182	7206	#define TIM_EGR_CC4G ((uint16_t)0x0010) /!<Capture/Compare 4 Generation /
richardv	0:b079fa4ed182	7207	#define TIM_EGR_COMG ((uint16_t)0x0020) /!<Capture/Compare Control Update Generation /
richardv	0:b079fa4ed182	7208	#define TIM_EGR_TG ((uint16_t)0x0040) /!<Trigger Generation /
richardv	0:b079fa4ed182	7209	#define TIM_EGR_BG ((uint16_t)0x0080) /!<Break Generation /
richardv	0:b079fa4ed182	7210	#define TIM_EGR_B2G ((uint16_t)0x0100) /!<Break Generation /
richardv	0:b079fa4ed182	7211
richardv	0:b079fa4ed182	7212
richardv	0:b079fa4ed182	7213	/**************** Bit definition for TIM_CCMR1 register *****************/
richardv	0:b079fa4ed182	7214	#define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
richardv	0:b079fa4ed182	7215	#define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /!<Bit 0 /
richardv	0:b079fa4ed182	7216	#define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /!<Bit 1 /
richardv	0:b079fa4ed182	7217
richardv	0:b079fa4ed182	7218	#define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /!<Output Compare 1 Fast enable /
richardv	0:b079fa4ed182	7219	#define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /!<Output Compare 1 Preload enable /
richardv	0:b079fa4ed182	7220
richardv	0:b079fa4ed182	7221	#define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
richardv	0:b079fa4ed182	7222	#define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /!<Bit 0 /
richardv	0:b079fa4ed182	7223	#define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /!<Bit 1 /
richardv	0:b079fa4ed182	7224	#define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /!<Bit 2 /
richardv	0:b079fa4ed182	7225	#define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /!<Bit 3 /
richardv	0:b079fa4ed182	7226
richardv	0:b079fa4ed182	7227	#define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /!<Output Compare 1Clear Enable /
richardv	0:b079fa4ed182	7228
richardv	0:b079fa4ed182	7229	#define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
richardv	0:b079fa4ed182	7230	#define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /!<Bit 0 /
richardv	0:b079fa4ed182	7231	#define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /!<Bit 1 /
richardv	0:b079fa4ed182	7232
richardv	0:b079fa4ed182	7233	#define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /!<Output Compare 2 Fast enable /
richardv	0:b079fa4ed182	7234	#define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /!<Output Compare 2 Preload enable /
richardv	0:b079fa4ed182	7235
richardv	0:b079fa4ed182	7236	#define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
richardv	0:b079fa4ed182	7237	#define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /!<Bit 0 /
richardv	0:b079fa4ed182	7238	#define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /!<Bit 1 /
richardv	0:b079fa4ed182	7239	#define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /!<Bit 2 /
richardv	0:b079fa4ed182	7240	#define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /!<Bit 3 /
richardv	0:b079fa4ed182	7241
richardv	0:b079fa4ed182	7242	#define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /!<Output Compare 2 Clear Enable /
richardv	0:b079fa4ed182	7243
richardv	0:b079fa4ed182	7244	/----------------------------------------------------------------------------/
richardv	0:b079fa4ed182	7245
richardv	0:b079fa4ed182	7246	#define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
richardv	0:b079fa4ed182	7247	#define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /!<Bit 0 /
richardv	0:b079fa4ed182	7248	#define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /!<Bit 1 /
richardv	0:b079fa4ed182	7249
richardv	0:b079fa4ed182	7250	#define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
richardv	0:b079fa4ed182	7251	#define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /!<Bit 0 /
richardv	0:b079fa4ed182	7252	#define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /!<Bit 1 /
richardv	0:b079fa4ed182	7253	#define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /!<Bit 2 /
richardv	0:b079fa4ed182	7254	#define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /!<Bit 3 /
richardv	0:b079fa4ed182	7255
richardv	0:b079fa4ed182	7256	#define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
richardv	0:b079fa4ed182	7257	#define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /!<Bit 0 /
richardv	0:b079fa4ed182	7258	#define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /!<Bit 1 /
richardv	0:b079fa4ed182	7259
richardv	0:b079fa4ed182	7260	#define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
richardv	0:b079fa4ed182	7261	#define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /!<Bit 0 /
richardv	0:b079fa4ed182	7262	#define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /!<Bit 1 /
richardv	0:b079fa4ed182	7263	#define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /!<Bit 2 /
richardv	0:b079fa4ed182	7264	#define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /!<Bit 3 /
richardv	0:b079fa4ed182	7265
richardv	0:b079fa4ed182	7266	/**************** Bit definition for TIM_CCMR2 register *****************/
richardv	0:b079fa4ed182	7267	#define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
richardv	0:b079fa4ed182	7268	#define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /!<Bit 0 /
richardv	0:b079fa4ed182	7269	#define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /!<Bit 1 /
richardv	0:b079fa4ed182	7270
richardv	0:b079fa4ed182	7271	#define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /!<Output Compare 3 Fast enable /
richardv	0:b079fa4ed182	7272	#define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /!<Output Compare 3 Preload enable /
richardv	0:b079fa4ed182	7273
richardv	0:b079fa4ed182	7274	#define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
richardv	0:b079fa4ed182	7275	#define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /!<Bit 0 /
richardv	0:b079fa4ed182	7276	#define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /!<Bit 1 /
richardv	0:b079fa4ed182	7277	#define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /!<Bit 2 /
richardv	0:b079fa4ed182	7278	#define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /!<Bit 3 /
richardv	0:b079fa4ed182	7279
richardv	0:b079fa4ed182	7280	#define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /!<Output Compare 3 Clear Enable /
richardv	0:b079fa4ed182	7281
richardv	0:b079fa4ed182	7282	#define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
richardv	0:b079fa4ed182	7283	#define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /!<Bit 0 /
richardv	0:b079fa4ed182	7284	#define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /!<Bit 1 /
richardv	0:b079fa4ed182	7285
richardv	0:b079fa4ed182	7286	#define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
richardv	0:b079fa4ed182	7287	#define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
richardv	0:b079fa4ed182	7288
richardv	0:b079fa4ed182	7289	#define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
richardv	0:b079fa4ed182	7290	#define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /!<Bit 0 /
richardv	0:b079fa4ed182	7291	#define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /!<Bit 1 /
richardv	0:b079fa4ed182	7292	#define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /!<Bit 2 /
richardv	0:b079fa4ed182	7293	#define TIM_CCMR2_OC4M_3 ((uint32_t)0x00100000) /!<Bit 3 /
richardv	0:b079fa4ed182	7294
richardv	0:b079fa4ed182	7295	#define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
richardv	0:b079fa4ed182	7296
richardv	0:b079fa4ed182	7297	/----------------------------------------------------------------------------/
richardv	0:b079fa4ed182	7298
richardv	0:b079fa4ed182	7299	#define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
richardv	0:b079fa4ed182	7300	#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /!<Bit 0 /
richardv	0:b079fa4ed182	7301	#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /!<Bit 1 /
richardv	0:b079fa4ed182	7302
richardv	0:b079fa4ed182	7303	#define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
richardv	0:b079fa4ed182	7304	#define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /!<Bit 0 /
richardv	0:b079fa4ed182	7305	#define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /!<Bit 1 /
richardv	0:b079fa4ed182	7306	#define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /!<Bit 2 /
richardv	0:b079fa4ed182	7307	#define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /!<Bit 3 /
richardv	0:b079fa4ed182	7308
richardv	0:b079fa4ed182	7309	#define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
richardv	0:b079fa4ed182	7310	#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /!<Bit 0 /
richardv	0:b079fa4ed182	7311	#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /!<Bit 1 /
richardv	0:b079fa4ed182	7312
richardv	0:b079fa4ed182	7313	#define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
richardv	0:b079fa4ed182	7314	#define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /!<Bit 0 /
richardv	0:b079fa4ed182	7315	#define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /!<Bit 1 /
richardv	0:b079fa4ed182	7316	#define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /!<Bit 2 /
richardv	0:b079fa4ed182	7317	#define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /!<Bit 3 /
richardv	0:b079fa4ed182	7318
richardv	0:b079fa4ed182	7319	/***************** Bit definition for TIM_CCER register *****************/
richardv	0:b079fa4ed182	7320	#define TIM_CCER_CC1E ((uint32_t)0x00000001) /!<Capture/Compare 1 output enable /
richardv	0:b079fa4ed182	7321	#define TIM_CCER_CC1P ((uint32_t)0x00000002) /!<Capture/Compare 1 output Polarity /
richardv	0:b079fa4ed182	7322	#define TIM_CCER_CC1NE ((uint32_t)0x00000004) /!<Capture/Compare 1 Complementary output enable /
richardv	0:b079fa4ed182	7323	#define TIM_CCER_CC1NP ((uint32_t)0x00000008) /!<Capture/Compare 1 Complementary output Polarity /
richardv	0:b079fa4ed182	7324	#define TIM_CCER_CC2E ((uint32_t)0x00000010) /!<Capture/Compare 2 output enable /
richardv	0:b079fa4ed182	7325	#define TIM_CCER_CC2P ((uint32_t)0x00000020) /!<Capture/Compare 2 output Polarity /
richardv	0:b079fa4ed182	7326	#define TIM_CCER_CC2NE ((uint32_t)0x00000040) /!<Capture/Compare 2 Complementary output enable /
richardv	0:b079fa4ed182	7327	#define TIM_CCER_CC2NP ((uint32_t)0x00000080) /!<Capture/Compare 2 Complementary output Polarity /
richardv	0:b079fa4ed182	7328	#define TIM_CCER_CC3E ((uint32_t)0x00000100) /!<Capture/Compare 3 output enable /
richardv	0:b079fa4ed182	7329	#define TIM_CCER_CC3P ((uint32_t)0x00000200) /!<Capture/Compare 3 output Polarity /
richardv	0:b079fa4ed182	7330	#define TIM_CCER_CC3NE ((uint32_t)0x00000400) /!<Capture/Compare 3 Complementary output enable /
richardv	0:b079fa4ed182	7331	#define TIM_CCER_CC3NP ((uint32_t)0x00000800) /!<Capture/Compare 3 Complementary output Polarity /
richardv	0:b079fa4ed182	7332	#define TIM_CCER_CC4E ((uint32_t)0x00001000) /!<Capture/Compare 4 output enable /
richardv	0:b079fa4ed182	7333	#define TIM_CCER_CC4P ((uint32_t)0x00002000) /!<Capture/Compare 4 output Polarity /
richardv	0:b079fa4ed182	7334	#define TIM_CCER_CC4NP ((uint32_t)0x00008000) /!<Capture/Compare 4 Complementary output Polarity /
richardv	0:b079fa4ed182	7335	#define TIM_CCER_CC5E ((uint32_t)0x00010000) /!<Capture/Compare 5 output enable /
richardv	0:b079fa4ed182	7336	#define TIM_CCER_CC5P ((uint32_t)0x00020000) /!<Capture/Compare 5 output Polarity /
richardv	0:b079fa4ed182	7337	#define TIM_CCER_CC6E ((uint32_t)0x00100000) /!<Capture/Compare 6 output enable /
richardv	0:b079fa4ed182	7338	#define TIM_CCER_CC6P ((uint32_t)0x00200000) /!<Capture/Compare 6 output Polarity /
richardv	0:b079fa4ed182	7339	/***************** Bit definition for TIM_CNT register ******************/
richardv	0:b079fa4ed182	7340	#define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /!<Counter Value /
richardv	0:b079fa4ed182	7341	#define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /!<Update interrupt flag copy /
richardv	0:b079fa4ed182	7342	/***************** Bit definition for TIM_PSC register ******************/
richardv	0:b079fa4ed182	7343	#define TIM_PSC_PSC ((uint16_t)0xFFFF) /!<Prescaler Value /
richardv	0:b079fa4ed182	7344
richardv	0:b079fa4ed182	7345	/***************** Bit definition for TIM_ARR register ******************/
richardv	0:b079fa4ed182	7346	#define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /!<actual auto-reload Value /
richardv	0:b079fa4ed182	7347
richardv	0:b079fa4ed182	7348	/***************** Bit definition for TIM_RCR register ******************/
richardv	0:b079fa4ed182	7349	#define TIM_RCR_REP ((uint8_t)0xFF) /!<Repetition Counter Value /
richardv	0:b079fa4ed182	7350
richardv	0:b079fa4ed182	7351	/***************** Bit definition for TIM_CCR1 register *****************/
richardv	0:b079fa4ed182	7352	#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /!<Capture/Compare 1 Value /
richardv	0:b079fa4ed182	7353
richardv	0:b079fa4ed182	7354	/***************** Bit definition for TIM_CCR2 register *****************/
richardv	0:b079fa4ed182	7355	#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /!<Capture/Compare 2 Value /
richardv	0:b079fa4ed182	7356
richardv	0:b079fa4ed182	7357	/***************** Bit definition for TIM_CCR3 register *****************/
richardv	0:b079fa4ed182	7358	#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /!<Capture/Compare 3 Value /
richardv	0:b079fa4ed182	7359
richardv	0:b079fa4ed182	7360	/***************** Bit definition for TIM_CCR4 register *****************/
richardv	0:b079fa4ed182	7361	#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /!<Capture/Compare 4 Value /
richardv	0:b079fa4ed182	7362
richardv	0:b079fa4ed182	7363	/***************** Bit definition for TIM_CCR5 register *****************/
richardv	0:b079fa4ed182	7364	#define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /!<Capture/Compare 5 Value /
richardv	0:b079fa4ed182	7365	#define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /!<Group Channel 5 and Channel 1 /
richardv	0:b079fa4ed182	7366	#define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /!<Group Channel 5 and Channel 2 /
richardv	0:b079fa4ed182	7367	#define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /!<Group Channel 5 and Channel 3 /
richardv	0:b079fa4ed182	7368
richardv	0:b079fa4ed182	7369	/***************** Bit definition for TIM_CCR6 register *****************/
richardv	0:b079fa4ed182	7370	#define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /!<Capture/Compare 6 Value /
richardv	0:b079fa4ed182	7371
richardv	0:b079fa4ed182	7372	/***************** Bit definition for TIM_BDTR register *****************/
richardv	0:b079fa4ed182	7373	#define TIM_BDTR_DTG ((uint32_t)0x000000FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
richardv	0:b079fa4ed182	7374	#define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /!<Bit 0 /
richardv	0:b079fa4ed182	7375	#define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /!<Bit 1 /
richardv	0:b079fa4ed182	7376	#define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /!<Bit 2 /
richardv	0:b079fa4ed182	7377	#define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /!<Bit 3 /
richardv	0:b079fa4ed182	7378	#define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /!<Bit 4 /
richardv	0:b079fa4ed182	7379	#define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /!<Bit 5 /
richardv	0:b079fa4ed182	7380	#define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /!<Bit 6 /
richardv	0:b079fa4ed182	7381	#define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /!<Bit 7 /
richardv	0:b079fa4ed182	7382
richardv	0:b079fa4ed182	7383	#define TIM_BDTR_LOCK ((uint32_t)0x00000300) /!<LOCK[1:0] bits (Lock Configuration) /
richardv	0:b079fa4ed182	7384	#define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /!<Bit 0 /
richardv	0:b079fa4ed182	7385	#define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /!<Bit 1 /
richardv	0:b079fa4ed182	7386
richardv	0:b079fa4ed182	7387	#define TIM_BDTR_OSSI ((uint32_t)0x00000400) /!<Off-State Selection for Idle mode /
richardv	0:b079fa4ed182	7388	#define TIM_BDTR_OSSR ((uint32_t)0x00000800) /!<Off-State Selection for Run mode /
richardv	0:b079fa4ed182	7389	#define TIM_BDTR_BKE ((uint32_t)0x00001000) /!<Break enable for Break1 /
richardv	0:b079fa4ed182	7390	#define TIM_BDTR_BKP ((uint32_t)0x00002000) /!<Break Polarity for Break1 /
richardv	0:b079fa4ed182	7391	#define TIM_BDTR_AOE ((uint32_t)0x00004000) /!<Automatic Output enable /
richardv	0:b079fa4ed182	7392	#define TIM_BDTR_MOE ((uint32_t)0x00008000) /!<Main Output enable /
richardv	0:b079fa4ed182	7393
richardv	0:b079fa4ed182	7394	#define TIM_BDTR_BKF ((uint32_t)0x000F0000) /!<Break Filter for Break1 /
richardv	0:b079fa4ed182	7395	#define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /!<Break Filter for Break2 /
richardv	0:b079fa4ed182	7396
richardv	0:b079fa4ed182	7397	#define TIM_BDTR_BK2E ((uint32_t)0x01000000) /!<Break enable for Break2 /
richardv	0:b079fa4ed182	7398	#define TIM_BDTR_BK2P ((uint32_t)0x02000000) /!<Break Polarity for Break2 /
richardv	0:b079fa4ed182	7399
richardv	0:b079fa4ed182	7400	/***************** Bit definition for TIM_DCR register ******************/
richardv	0:b079fa4ed182	7401	#define TIM_DCR_DBA ((uint16_t)0x001F) /!<DBA[4:0] bits (DMA Base Address) /
richardv	0:b079fa4ed182	7402	#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /!<Bit 0 /
richardv	0:b079fa4ed182	7403	#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /!<Bit 1 /
richardv	0:b079fa4ed182	7404	#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /!<Bit 2 /
richardv	0:b079fa4ed182	7405	#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /!<Bit 3 /
richardv	0:b079fa4ed182	7406	#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /!<Bit 4 /
richardv	0:b079fa4ed182	7407
richardv	0:b079fa4ed182	7408	#define TIM_DCR_DBL ((uint16_t)0x1F00) /!<DBL[4:0] bits (DMA Burst Length) /
richardv	0:b079fa4ed182	7409	#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /!<Bit 0 /
richardv	0:b079fa4ed182	7410	#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /!<Bit 1 /
richardv	0:b079fa4ed182	7411	#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /!<Bit 2 /
richardv	0:b079fa4ed182	7412	#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /!<Bit 3 /
richardv	0:b079fa4ed182	7413	#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /!<Bit 4 /
richardv	0:b079fa4ed182	7414
richardv	0:b079fa4ed182	7415	/***************** Bit definition for TIM_DMAR register *****************/
richardv	0:b079fa4ed182	7416	#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /!<DMA register for burst accesses /
richardv	0:b079fa4ed182	7417
richardv	0:b079fa4ed182	7418	/***************** Bit definition for TIM16_OR register *******************/
richardv	0:b079fa4ed182	7419	#define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) /
richardv	0:b079fa4ed182	7420	#define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /!<Bit 0 /
richardv	0:b079fa4ed182	7421	#define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /!<Bit 1 /
richardv	0:b079fa4ed182	7422
richardv	0:b079fa4ed182	7423	/***************** Bit definition for TIM1_OR register *******************/
richardv	0:b079fa4ed182	7424	#define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /!<ETR_RMP[3:0] bits (TIM1 ETR remap) /
richardv	0:b079fa4ed182	7425	#define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /!<Bit 0 /
richardv	0:b079fa4ed182	7426	#define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /!<Bit 1 /
richardv	0:b079fa4ed182	7427	#define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /!<Bit 2 /
richardv	0:b079fa4ed182	7428	#define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /!<Bit 3 /
richardv	0:b079fa4ed182	7429
richardv	0:b079fa4ed182	7430	/***************** Bit definition for TIM8_OR register *******************/
richardv	0:b079fa4ed182	7431	#define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /!<ETR_RMP[3:0] bits (TIM8 ETR remap) /
richardv	0:b079fa4ed182	7432	#define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /!<Bit 0 /
richardv	0:b079fa4ed182	7433	#define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /!<Bit 1 /
richardv	0:b079fa4ed182	7434	#define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /!<Bit 2 /
richardv	0:b079fa4ed182	7435	#define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /!<Bit 3 /
richardv	0:b079fa4ed182	7436
richardv	0:b079fa4ed182	7437	/**************** Bit definition for TIM_CCMR3 register *****************/
richardv	0:b079fa4ed182	7438	#define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /!<Output Compare 5 Fast enable /
richardv	0:b079fa4ed182	7439	#define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /!<Output Compare 5 Preload enable /
richardv	0:b079fa4ed182	7440
richardv	0:b079fa4ed182	7441	#define TIM_CCMR3_OC5M ((uint32_t)0x00000070) /!<OC5M[2:0] bits (Output Compare 5 Mode) /
richardv	0:b079fa4ed182	7442	#define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /!<Bit 0 /
richardv	0:b079fa4ed182	7443	#define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /!<Bit 1 /
richardv	0:b079fa4ed182	7444	#define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /!<Bit 2 /
richardv	0:b079fa4ed182	7445	#define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /!<Bit 3 /
richardv	0:b079fa4ed182	7446
richardv	0:b079fa4ed182	7447	#define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /!<Output Compare 5 Clear Enable /
richardv	0:b079fa4ed182	7448
richardv	0:b079fa4ed182	7449	#define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /!<Output Compare 4 Fast enable /
richardv	0:b079fa4ed182	7450	#define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /!<Output Compare 4 Preload enable /
richardv	0:b079fa4ed182	7451
richardv	0:b079fa4ed182	7452	#define TIM_CCMR3_OC6M ((uint32_t)0x00007000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
richardv	0:b079fa4ed182	7453	#define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /!<Bit 0 /
richardv	0:b079fa4ed182	7454	#define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /!<Bit 1 /
richardv	0:b079fa4ed182	7455	#define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /!<Bit 2 /
richardv	0:b079fa4ed182	7456	#define TIM_CCMR3_OC6M_3 ((uint32_t)0x00100000) /!<Bit 3 /
richardv	0:b079fa4ed182	7457
richardv	0:b079fa4ed182	7458	#define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /!<Output Compare 4 Clear Enable /
richardv	0:b079fa4ed182	7459
richardv	0:b079fa4ed182	7460	/******************************************************************************/
richardv	0:b079fa4ed182	7461	/* */
richardv	0:b079fa4ed182	7462	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
richardv	0:b079fa4ed182	7463	/* */
richardv	0:b079fa4ed182	7464	/******************************************************************************/
richardv	0:b079fa4ed182	7465	/**************** Bit definition for USART_CR1 register *****************/
richardv	0:b079fa4ed182	7466	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
richardv	0:b079fa4ed182	7467	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
richardv	0:b079fa4ed182	7468	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
richardv	0:b079fa4ed182	7469	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
richardv	0:b079fa4ed182	7470	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
richardv	0:b079fa4ed182	7471	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
richardv	0:b079fa4ed182	7472	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
richardv	0:b079fa4ed182	7473	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
richardv	0:b079fa4ed182	7474	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
richardv	0:b079fa4ed182	7475	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
richardv	0:b079fa4ed182	7476	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
richardv	0:b079fa4ed182	7477	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
richardv	0:b079fa4ed182	7478	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
richardv	0:b079fa4ed182	7479	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
richardv	0:b079fa4ed182	7480	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
richardv	0:b079fa4ed182	7481	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
richardv	0:b079fa4ed182	7482	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
richardv	0:b079fa4ed182	7483	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
richardv	0:b079fa4ed182	7484	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
richardv	0:b079fa4ed182	7485	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
richardv	0:b079fa4ed182	7486	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
richardv	0:b079fa4ed182	7487	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
richardv	0:b079fa4ed182	7488	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
richardv	0:b079fa4ed182	7489	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
richardv	0:b079fa4ed182	7490	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
richardv	0:b079fa4ed182	7491	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
richardv	0:b079fa4ed182	7492	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
richardv	0:b079fa4ed182	7493	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
richardv	0:b079fa4ed182	7494	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
richardv	0:b079fa4ed182	7495	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
richardv	0:b079fa4ed182	7496
richardv	0:b079fa4ed182	7497	/**************** Bit definition for USART_CR2 register *****************/
richardv	0:b079fa4ed182	7498	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
richardv	0:b079fa4ed182	7499	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
richardv	0:b079fa4ed182	7500	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
richardv	0:b079fa4ed182	7501	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
richardv	0:b079fa4ed182	7502	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
richardv	0:b079fa4ed182	7503	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
richardv	0:b079fa4ed182	7504	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
richardv	0:b079fa4ed182	7505	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
richardv	0:b079fa4ed182	7506	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
richardv	0:b079fa4ed182	7507	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
richardv	0:b079fa4ed182	7508	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
richardv	0:b079fa4ed182	7509	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
richardv	0:b079fa4ed182	7510	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
richardv	0:b079fa4ed182	7511	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
richardv	0:b079fa4ed182	7512	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
richardv	0:b079fa4ed182	7513	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
richardv	0:b079fa4ed182	7514	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
richardv	0:b079fa4ed182	7515	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
richardv	0:b079fa4ed182	7516	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
richardv	0:b079fa4ed182	7517	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
richardv	0:b079fa4ed182	7518	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
richardv	0:b079fa4ed182	7519	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
richardv	0:b079fa4ed182	7520
richardv	0:b079fa4ed182	7521	/**************** Bit definition for USART_CR3 register *****************/
richardv	0:b079fa4ed182	7522	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
richardv	0:b079fa4ed182	7523	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
richardv	0:b079fa4ed182	7524	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
richardv	0:b079fa4ed182	7525	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
richardv	0:b079fa4ed182	7526	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
richardv	0:b079fa4ed182	7527	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
richardv	0:b079fa4ed182	7528	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
richardv	0:b079fa4ed182	7529	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
richardv	0:b079fa4ed182	7530	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
richardv	0:b079fa4ed182	7531	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
richardv	0:b079fa4ed182	7532	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
richardv	0:b079fa4ed182	7533	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
richardv	0:b079fa4ed182	7534	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
richardv	0:b079fa4ed182	7535	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
richardv	0:b079fa4ed182	7536	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
richardv	0:b079fa4ed182	7537	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
richardv	0:b079fa4ed182	7538	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
richardv	0:b079fa4ed182	7539	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
richardv	0:b079fa4ed182	7540	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
richardv	0:b079fa4ed182	7541	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
richardv	0:b079fa4ed182	7542	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
richardv	0:b079fa4ed182	7543	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
richardv	0:b079fa4ed182	7544	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
richardv	0:b079fa4ed182	7545	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
richardv	0:b079fa4ed182	7546
richardv	0:b079fa4ed182	7547	/**************** Bit definition for USART_BRR register *****************/
richardv	0:b079fa4ed182	7548	#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /!< Fraction of USARTDIV /
richardv	0:b079fa4ed182	7549	#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /!< Mantissa of USARTDIV /
richardv	0:b079fa4ed182	7550
richardv	0:b079fa4ed182	7551	/**************** Bit definition for USART_GTPR register ****************/
richardv	0:b079fa4ed182	7552	#define USART_GTPR_PSC ((uint16_t)0x00FF) /!< PSC[7:0] bits (Prescaler value) /
richardv	0:b079fa4ed182	7553	#define USART_GTPR_GT ((uint16_t)0xFF00) /!< GT[7:0] bits (Guard time value) /
richardv	0:b079fa4ed182	7554
richardv	0:b079fa4ed182	7555
richardv	0:b079fa4ed182	7556	/***************** Bit definition for USART_RTOR register ***************/
richardv	0:b079fa4ed182	7557	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
richardv	0:b079fa4ed182	7558	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
richardv	0:b079fa4ed182	7559
richardv	0:b079fa4ed182	7560	/***************** Bit definition for USART_RQR register ****************/
richardv	0:b079fa4ed182	7561	#define USART_RQR_ABRRQ ((uint16_t)0x0001) /!< Auto-Baud Rate Request /
richardv	0:b079fa4ed182	7562	#define USART_RQR_SBKRQ ((uint16_t)0x0002) /!< Send Break Request /
richardv	0:b079fa4ed182	7563	#define USART_RQR_MMRQ ((uint16_t)0x0004) /!< Mute Mode Request /
richardv	0:b079fa4ed182	7564	#define USART_RQR_RXFRQ ((uint16_t)0x0008) /!< Receive Data flush Request /
richardv	0:b079fa4ed182	7565	#define USART_RQR_TXFRQ ((uint16_t)0x0010) /!< Transmit data flush Request /
richardv	0:b079fa4ed182	7566
richardv	0:b079fa4ed182	7567	/***************** Bit definition for USART_ISR register ****************/
richardv	0:b079fa4ed182	7568	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
richardv	0:b079fa4ed182	7569	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
richardv	0:b079fa4ed182	7570	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
richardv	0:b079fa4ed182	7571	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
richardv	0:b079fa4ed182	7572	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
richardv	0:b079fa4ed182	7573	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
richardv	0:b079fa4ed182	7574	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
richardv	0:b079fa4ed182	7575	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
richardv	0:b079fa4ed182	7576	#define USART_ISR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
richardv	0:b079fa4ed182	7577	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
richardv	0:b079fa4ed182	7578	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
richardv	0:b079fa4ed182	7579	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
richardv	0:b079fa4ed182	7580	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
richardv	0:b079fa4ed182	7581	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
richardv	0:b079fa4ed182	7582	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
richardv	0:b079fa4ed182	7583	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
richardv	0:b079fa4ed182	7584	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
richardv	0:b079fa4ed182	7585	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
richardv	0:b079fa4ed182	7586	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
richardv	0:b079fa4ed182	7587	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
richardv	0:b079fa4ed182	7588	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
richardv	0:b079fa4ed182	7589	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
richardv	0:b079fa4ed182	7590
richardv	0:b079fa4ed182	7591	/***************** Bit definition for USART_ICR register ****************/
richardv	0:b079fa4ed182	7592	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
richardv	0:b079fa4ed182	7593	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
richardv	0:b079fa4ed182	7594	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
richardv	0:b079fa4ed182	7595	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
richardv	0:b079fa4ed182	7596	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
richardv	0:b079fa4ed182	7597	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
richardv	0:b079fa4ed182	7598	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
richardv	0:b079fa4ed182	7599	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
richardv	0:b079fa4ed182	7600	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
richardv	0:b079fa4ed182	7601	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
richardv	0:b079fa4ed182	7602	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
richardv	0:b079fa4ed182	7603	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
richardv	0:b079fa4ed182	7604
richardv	0:b079fa4ed182	7605	/***************** Bit definition for USART_RDR register ****************/
richardv	0:b079fa4ed182	7606	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
richardv	0:b079fa4ed182	7607
richardv	0:b079fa4ed182	7608	/***************** Bit definition for USART_TDR register ****************/
richardv	0:b079fa4ed182	7609	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
richardv	0:b079fa4ed182	7610
richardv	0:b079fa4ed182	7611	/******************************************************************************/
richardv	0:b079fa4ed182	7612	/* */
richardv	0:b079fa4ed182	7613	/* Window WATCHDOG */
richardv	0:b079fa4ed182	7614	/* */
richardv	0:b079fa4ed182	7615	/******************************************************************************/
richardv	0:b079fa4ed182	7616	/***************** Bit definition for WWDG_CR register ******************/
richardv	0:b079fa4ed182	7617	#define WWDG_CR_T ((uint8_t)0x7F) /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
richardv	0:b079fa4ed182	7618	#define WWDG_CR_T0 ((uint8_t)0x01) /!<Bit 0 /
richardv	0:b079fa4ed182	7619	#define WWDG_CR_T1 ((uint8_t)0x02) /!<Bit 1 /
richardv	0:b079fa4ed182	7620	#define WWDG_CR_T2 ((uint8_t)0x04) /!<Bit 2 /
richardv	0:b079fa4ed182	7621	#define WWDG_CR_T3 ((uint8_t)0x08) /!<Bit 3 /
richardv	0:b079fa4ed182	7622	#define WWDG_CR_T4 ((uint8_t)0x10) /!<Bit 4 /
richardv	0:b079fa4ed182	7623	#define WWDG_CR_T5 ((uint8_t)0x20) /!<Bit 5 /
richardv	0:b079fa4ed182	7624	#define WWDG_CR_T6 ((uint8_t)0x40) /!<Bit 6 /
richardv	0:b079fa4ed182	7625
richardv	0:b079fa4ed182	7626	#define WWDG_CR_WDGA ((uint8_t)0x80) /!<Activation bit /
richardv	0:b079fa4ed182	7627
richardv	0:b079fa4ed182	7628	/***************** Bit definition for WWDG_CFR register *****************/
richardv	0:b079fa4ed182	7629	#define WWDG_CFR_W ((uint16_t)0x007F) /!<W[6:0] bits (7-bit window value) /
richardv	0:b079fa4ed182	7630	#define WWDG_CFR_W0 ((uint16_t)0x0001) /!<Bit 0 /
richardv	0:b079fa4ed182	7631	#define WWDG_CFR_W1 ((uint16_t)0x0002) /!<Bit 1 /
richardv	0:b079fa4ed182	7632	#define WWDG_CFR_W2 ((uint16_t)0x0004) /!<Bit 2 /
richardv	0:b079fa4ed182	7633	#define WWDG_CFR_W3 ((uint16_t)0x0008) /!<Bit 3 /
richardv	0:b079fa4ed182	7634	#define WWDG_CFR_W4 ((uint16_t)0x0010) /!<Bit 4 /
richardv	0:b079fa4ed182	7635	#define WWDG_CFR_W5 ((uint16_t)0x0020) /!<Bit 5 /
richardv	0:b079fa4ed182	7636	#define WWDG_CFR_W6 ((uint16_t)0x0040) /!<Bit 6 /
richardv	0:b079fa4ed182	7637
richardv	0:b079fa4ed182	7638	#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /!<WDGTB[1:0] bits (Timer Base) /
richardv	0:b079fa4ed182	7639	#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /!<Bit 0 /
richardv	0:b079fa4ed182	7640	#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /!<Bit 1 /
richardv	0:b079fa4ed182	7641
richardv	0:b079fa4ed182	7642	#define WWDG_CFR_EWI ((uint16_t)0x0200) /!<Early Wakeup Interrupt /
richardv	0:b079fa4ed182	7643
richardv	0:b079fa4ed182	7644	/***************** Bit definition for WWDG_SR register ******************/
richardv	0:b079fa4ed182	7645	#define WWDG_SR_EWIF ((uint8_t)0x01) /!<Early Wakeup Interrupt Flag /
richardv	0:b079fa4ed182	7646
richardv	0:b079fa4ed182	7647	/**
richardv	0:b079fa4ed182	7648	* @}
richardv	0:b079fa4ed182	7649	*/
richardv	0:b079fa4ed182	7650
richardv	0:b079fa4ed182	7651	/**
richardv	0:b079fa4ed182	7652	* @}
richardv	0:b079fa4ed182	7653	*/
richardv	0:b079fa4ed182	7654
richardv	0:b079fa4ed182	7655	#ifdef USE_STDPERIPH_DRIVER
richardv	0:b079fa4ed182	7656	#include "stm32f30x_conf.h"
richardv	0:b079fa4ed182	7657	#endif /!< USE_STDPERIPH_DRIVER /
richardv	0:b079fa4ed182	7658
richardv	0:b079fa4ed182	7659	/** @addtogroup Exported_macro
richardv	0:b079fa4ed182	7660	* @{
richardv	0:b079fa4ed182	7661	*/
richardv	0:b079fa4ed182	7662
richardv	0:b079fa4ed182	7663	#define SET_BIT(REG, BIT) ((REG) \|= (BIT))
richardv	0:b079fa4ed182	7664
richardv	0:b079fa4ed182	7665	#define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
richardv	0:b079fa4ed182	7666
richardv	0:b079fa4ed182	7667	#define READ_BIT(REG, BIT) ((REG) & (BIT))
richardv	0:b079fa4ed182	7668
richardv	0:b079fa4ed182	7669	#define CLEAR_REG(REG) ((REG) = (0x0))
richardv	0:b079fa4ed182	7670
richardv	0:b079fa4ed182	7671	#define WRITE_REG(REG, VAL) ((REG) = (VAL))
richardv	0:b079fa4ed182	7672
richardv	0:b079fa4ed182	7673	#define READ_REG(REG) ((REG))
richardv	0:b079fa4ed182	7674
richardv	0:b079fa4ed182	7675	#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) \| (SETMASK)))
richardv	0:b079fa4ed182	7676
richardv	0:b079fa4ed182	7677	/**
richardv	0:b079fa4ed182	7678	* @}
richardv	0:b079fa4ed182	7679	*/
richardv	0:b079fa4ed182	7680
richardv	0:b079fa4ed182	7681	#ifdef __cplusplus
richardv	0:b079fa4ed182	7682	}
richardv	0:b079fa4ed182	7683	#endif /* __cplusplus */
richardv	0:b079fa4ed182	7684
richardv	0:b079fa4ed182	7685	#endif /* __STM32F30x_H */
richardv	0:b079fa4ed182	7686
richardv	0:b079fa4ed182	7687	/**
richardv	0:b079fa4ed182	7688	* @}
richardv	0:b079fa4ed182	7689	*/
richardv	0:b079fa4ed182	7690
richardv	0:b079fa4ed182	7691	/**
richardv	0:b079fa4ed182	7692	* @}
richardv	0:b079fa4ed182	7693	*/
richardv	0:b079fa4ed182	7694
richardv	0:b079fa4ed182	7695	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	02 Nov 2016
Imports:	8
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

stm32f30x.h@0:b079fa4ed182, 2016-11-02 (annotated)

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