Diff: TARGET_LPC1768/TOOLCHAIN_GCC_CR/LPC1768.ld

Revision:

108:34e6b704fe68

Parent:

76:824293ae5e43

diff -r 4f6c30876dfa -r 34e6b704fe68 TARGET_LPC1768/TOOLCHAIN_GCC_CR/LPC1768.ld
--- a/TARGET_LPC1768/TOOLCHAIN_GCC_CR/LPC1768.ld	Wed Sep 16 15:32:31 2015 +0100
+++ b/TARGET_LPC1768/TOOLCHAIN_GCC_CR/LPC1768.ld	Fri Oct 02 07:35:07 2015 +0200
@@ -8,7 +8,8 @@
   /* Define each memory region */
   MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
   RamLoc32 (rwx) : ORIGIN = 0x100000C8, LENGTH = 0x7F38 /* 32k */
-  RamAHB32 (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x8000 /* 32k */
+  RamAHB_USB (rwx) : ORIGIN = 0x2007c000, LENGTH = 0x4000 /* 16k */
+  RamAHB_Eth (rwx) : ORIGIN = 0x20080000, LENGTH = 0x4000 /* 16k */
 
 }
   /* Define a symbol for the top of each memory region */
@@ -110,11 +111,11 @@
         *(.data.$RAM2*)
         *(.data.$RamAHB32*)
        . = ALIGN(4) ;
-    } > RamAHB32 AT>MFlash512
+    } > RamAHB_USB AT>MFlash512
     
     /* MAIN DATA SECTION */
 
-    .uninit_RESERVED : ALIGN(4)
+    .uninit_RESERVED(NOLOAD) : ALIGN(4)
     {
         KEEP(*(.bss.$RESERVED*))
     } > RamLoc32
@@ -130,15 +131,21 @@
     } > RamLoc32 AT>MFlash512
 
     
-    .bss_RAM2 : ALIGN(4)
+    .bss_RAM2(NOLOAD) : ALIGN(4)
     {
         *(.bss.$RAM2*)
         *(.bss.$RamAHB32*)
+        *(AHBSRAM0)
        . = ALIGN(4) ;
-    } > RamAHB32
+    } > RamAHB_USB
 
+    .bss_RAM3(NOLOAD) : ALIGN(4)
+    {
+        *(AHBSRAM1)
+       . = ALIGN(4) ;
+    } > RamAHB_Eth
     /* MAIN BSS SECTION */
-    .bss : ALIGN(4)
+    .bss(NOLOAD) : ALIGN(4)
     {
         _bss = .;
         *(.bss*)