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TARGET_KL05Z/core_cm0.h@78:ed8466a608b4, 2014-02-18 (annotated)

Committer:
emilmont
Date:
Tue Feb 18 15:02:39 2014 +0000
Revision:
78:ed8466a608b4
Child:
110:165afa46840b
Add KL05Z Target

Fix LPC11XX InterruptIn

Fix NUCLEO boards us_ticker

Fix NUCLEO_L152RE AnalogOut

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 78:ed8466a608b4 1 /**************************************************************************//**
emilmont 78:ed8466a608b4 2 * @file core_cm0.h
emilmont 78:ed8466a608b4 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
emilmont 78:ed8466a608b4 4 * @version V3.20
emilmont 78:ed8466a608b4 5 * @date 25. February 2013
emilmont 78:ed8466a608b4 6 *
emilmont 78:ed8466a608b4 7 * @note
emilmont 78:ed8466a608b4 8 *
emilmont 78:ed8466a608b4 9 ******************************************************************************/
emilmont 78:ed8466a608b4 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
emilmont 78:ed8466a608b4 11
emilmont 78:ed8466a608b4 12 All rights reserved.
emilmont 78:ed8466a608b4 13 Redistribution and use in source and binary forms, with or without
emilmont 78:ed8466a608b4 14 modification, are permitted provided that the following conditions are met:
emilmont 78:ed8466a608b4 15 - Redistributions of source code must retain the above copyright
emilmont 78:ed8466a608b4 16 notice, this list of conditions and the following disclaimer.
emilmont 78:ed8466a608b4 17 - Redistributions in binary form must reproduce the above copyright
emilmont 78:ed8466a608b4 18 notice, this list of conditions and the following disclaimer in the
emilmont 78:ed8466a608b4 19 documentation and/or other materials provided with the distribution.
emilmont 78:ed8466a608b4 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 78:ed8466a608b4 21 to endorse or promote products derived from this software without
emilmont 78:ed8466a608b4 22 specific prior written permission.
emilmont 78:ed8466a608b4 23 *
emilmont 78:ed8466a608b4 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 78:ed8466a608b4 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 78:ed8466a608b4 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 78:ed8466a608b4 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 78:ed8466a608b4 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 78:ed8466a608b4 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 78:ed8466a608b4 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 78:ed8466a608b4 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 78:ed8466a608b4 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 78:ed8466a608b4 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 78:ed8466a608b4 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 78:ed8466a608b4 35 ---------------------------------------------------------------------------*/
emilmont 78:ed8466a608b4 36
emilmont 78:ed8466a608b4 37
emilmont 78:ed8466a608b4 38 #if defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 39 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 78:ed8466a608b4 40 #endif
emilmont 78:ed8466a608b4 41
emilmont 78:ed8466a608b4 42 #ifdef __cplusplus
emilmont 78:ed8466a608b4 43 extern "C" {
emilmont 78:ed8466a608b4 44 #endif
emilmont 78:ed8466a608b4 45
emilmont 78:ed8466a608b4 46 #ifndef __CORE_CM0_H_GENERIC
emilmont 78:ed8466a608b4 47 #define __CORE_CM0_H_GENERIC
emilmont 78:ed8466a608b4 48
emilmont 78:ed8466a608b4 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 78:ed8466a608b4 50 CMSIS violates the following MISRA-C:2004 rules:
emilmont 78:ed8466a608b4 51
emilmont 78:ed8466a608b4 52 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 78:ed8466a608b4 53 Function definitions in header files are used to allow 'inlining'.
emilmont 78:ed8466a608b4 54
emilmont 78:ed8466a608b4 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 78:ed8466a608b4 56 Unions are used for effective representation of core registers.
emilmont 78:ed8466a608b4 57
emilmont 78:ed8466a608b4 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 78:ed8466a608b4 59 Function-like macros are used to allow more efficient code.
emilmont 78:ed8466a608b4 60 */
emilmont 78:ed8466a608b4 61
emilmont 78:ed8466a608b4 62
emilmont 78:ed8466a608b4 63 /*******************************************************************************
emilmont 78:ed8466a608b4 64 * CMSIS definitions
emilmont 78:ed8466a608b4 65 ******************************************************************************/
emilmont 78:ed8466a608b4 66 /** \ingroup Cortex_M0
emilmont 78:ed8466a608b4 67 @{
emilmont 78:ed8466a608b4 68 */
emilmont 78:ed8466a608b4 69
emilmont 78:ed8466a608b4 70 /* CMSIS CM0 definitions */
emilmont 78:ed8466a608b4 71 #define __CM0_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
emilmont 78:ed8466a608b4 72 #define __CM0_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
emilmont 78:ed8466a608b4 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
emilmont 78:ed8466a608b4 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 78:ed8466a608b4 75
emilmont 78:ed8466a608b4 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 78:ed8466a608b4 77
emilmont 78:ed8466a608b4 78
emilmont 78:ed8466a608b4 79 #if defined ( __CC_ARM )
emilmont 78:ed8466a608b4 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 78:ed8466a608b4 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 78:ed8466a608b4 82 #define __STATIC_INLINE static __inline
emilmont 78:ed8466a608b4 83
emilmont 78:ed8466a608b4 84 #elif defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 78:ed8466a608b4 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 78:ed8466a608b4 87 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 88
emilmont 78:ed8466a608b4 89 #elif defined ( __GNUC__ )
emilmont 78:ed8466a608b4 90 #define __ASM __asm /*!< asm keyword for GNU Compiler */
emilmont 78:ed8466a608b4 91 #define __INLINE inline /*!< inline keyword for GNU Compiler */
emilmont 78:ed8466a608b4 92 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 93
emilmont 78:ed8466a608b4 94 #elif defined ( __TASKING__ )
emilmont 78:ed8466a608b4 95 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 78:ed8466a608b4 96 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 78:ed8466a608b4 97 #define __STATIC_INLINE static inline
emilmont 78:ed8466a608b4 98
emilmont 78:ed8466a608b4 99 #endif
emilmont 78:ed8466a608b4 100
emilmont 78:ed8466a608b4 101 /** __FPU_USED indicates whether an FPU is used or not. This core does not support an FPU at all
emilmont 78:ed8466a608b4 102 */
emilmont 78:ed8466a608b4 103 #define __FPU_USED 0
emilmont 78:ed8466a608b4 104
emilmont 78:ed8466a608b4 105 #if defined ( __CC_ARM )
emilmont 78:ed8466a608b4 106 #if defined __TARGET_FPU_VFP
emilmont 78:ed8466a608b4 107 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 108 #endif
emilmont 78:ed8466a608b4 109
emilmont 78:ed8466a608b4 110 #elif defined ( __ICCARM__ )
emilmont 78:ed8466a608b4 111 #if defined __ARMVFP__
emilmont 78:ed8466a608b4 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 113 #endif
emilmont 78:ed8466a608b4 114
emilmont 78:ed8466a608b4 115 #elif defined ( __GNUC__ )
emilmont 78:ed8466a608b4 116 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
emilmont 78:ed8466a608b4 117 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 118 #endif
emilmont 78:ed8466a608b4 119
emilmont 78:ed8466a608b4 120 #elif defined ( __TASKING__ )
emilmont 78:ed8466a608b4 121 #if defined __FPU_VFP__
emilmont 78:ed8466a608b4 122 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 78:ed8466a608b4 123 #endif
emilmont 78:ed8466a608b4 124 #endif
emilmont 78:ed8466a608b4 125
emilmont 78:ed8466a608b4 126 #include <stdint.h> /* standard types definitions */
emilmont 78:ed8466a608b4 127 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 78:ed8466a608b4 128 #include <core_cmFunc.h> /* Core Function Access */
emilmont 78:ed8466a608b4 129
emilmont 78:ed8466a608b4 130 #endif /* __CORE_CM0_H_GENERIC */
emilmont 78:ed8466a608b4 131
emilmont 78:ed8466a608b4 132 #ifndef __CMSIS_GENERIC
emilmont 78:ed8466a608b4 133
emilmont 78:ed8466a608b4 134 #ifndef __CORE_CM0_H_DEPENDANT
emilmont 78:ed8466a608b4 135 #define __CORE_CM0_H_DEPENDANT
emilmont 78:ed8466a608b4 136
emilmont 78:ed8466a608b4 137 /* check device defines and use defaults */
emilmont 78:ed8466a608b4 138 #if defined __CHECK_DEVICE_DEFINES
emilmont 78:ed8466a608b4 139 #ifndef __CM0_REV
emilmont 78:ed8466a608b4 140 #define __CM0_REV 0x0000
emilmont 78:ed8466a608b4 141 #warning "__CM0_REV not defined in device header file; using default!"
emilmont 78:ed8466a608b4 142 #endif
emilmont 78:ed8466a608b4 143
emilmont 78:ed8466a608b4 144 #ifndef __NVIC_PRIO_BITS
emilmont 78:ed8466a608b4 145 #define __NVIC_PRIO_BITS 2
emilmont 78:ed8466a608b4 146 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 78:ed8466a608b4 147 #endif
emilmont 78:ed8466a608b4 148
emilmont 78:ed8466a608b4 149 #ifndef __Vendor_SysTickConfig
emilmont 78:ed8466a608b4 150 #define __Vendor_SysTickConfig 0
emilmont 78:ed8466a608b4 151 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 78:ed8466a608b4 152 #endif
emilmont 78:ed8466a608b4 153 #endif
emilmont 78:ed8466a608b4 154
emilmont 78:ed8466a608b4 155 /* IO definitions (access restrictions to peripheral registers) */
emilmont 78:ed8466a608b4 156 /**
emilmont 78:ed8466a608b4 157 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 78:ed8466a608b4 158
emilmont 78:ed8466a608b4 159 <strong>IO Type Qualifiers</strong> are used
emilmont 78:ed8466a608b4 160 \li to specify the access to peripheral variables.
emilmont 78:ed8466a608b4 161 \li for automatic generation of peripheral register debug information.
emilmont 78:ed8466a608b4 162 */
emilmont 78:ed8466a608b4 163 #ifdef __cplusplus
emilmont 78:ed8466a608b4 164 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 78:ed8466a608b4 165 #else
emilmont 78:ed8466a608b4 166 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 78:ed8466a608b4 167 #endif
emilmont 78:ed8466a608b4 168 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 78:ed8466a608b4 169 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 78:ed8466a608b4 170
emilmont 78:ed8466a608b4 171 /*@} end of group Cortex_M0 */
emilmont 78:ed8466a608b4 172
emilmont 78:ed8466a608b4 173
emilmont 78:ed8466a608b4 174
emilmont 78:ed8466a608b4 175 /*******************************************************************************
emilmont 78:ed8466a608b4 176 * Register Abstraction
emilmont 78:ed8466a608b4 177 Core Register contain:
emilmont 78:ed8466a608b4 178 - Core Register
emilmont 78:ed8466a608b4 179 - Core NVIC Register
emilmont 78:ed8466a608b4 180 - Core SCB Register
emilmont 78:ed8466a608b4 181 - Core SysTick Register
emilmont 78:ed8466a608b4 182 ******************************************************************************/
emilmont 78:ed8466a608b4 183 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 78:ed8466a608b4 184 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 78:ed8466a608b4 185 */
emilmont 78:ed8466a608b4 186
emilmont 78:ed8466a608b4 187 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 188 \defgroup CMSIS_CORE Status and Control Registers
emilmont 78:ed8466a608b4 189 \brief Core Register type definitions.
emilmont 78:ed8466a608b4 190 @{
emilmont 78:ed8466a608b4 191 */
emilmont 78:ed8466a608b4 192
emilmont 78:ed8466a608b4 193 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 78:ed8466a608b4 194 */
emilmont 78:ed8466a608b4 195 typedef union
emilmont 78:ed8466a608b4 196 {
emilmont 78:ed8466a608b4 197 struct
emilmont 78:ed8466a608b4 198 {
emilmont 78:ed8466a608b4 199 #if (__CORTEX_M != 0x04)
emilmont 78:ed8466a608b4 200 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
emilmont 78:ed8466a608b4 201 #else
emilmont 78:ed8466a608b4 202 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
emilmont 78:ed8466a608b4 203 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 78:ed8466a608b4 204 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
emilmont 78:ed8466a608b4 205 #endif
emilmont 78:ed8466a608b4 206 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 78:ed8466a608b4 207 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 78:ed8466a608b4 208 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 78:ed8466a608b4 209 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 78:ed8466a608b4 210 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 78:ed8466a608b4 211 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 212 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 213 } APSR_Type;
emilmont 78:ed8466a608b4 214
emilmont 78:ed8466a608b4 215
emilmont 78:ed8466a608b4 216 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 78:ed8466a608b4 217 */
emilmont 78:ed8466a608b4 218 typedef union
emilmont 78:ed8466a608b4 219 {
emilmont 78:ed8466a608b4 220 struct
emilmont 78:ed8466a608b4 221 {
emilmont 78:ed8466a608b4 222 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 78:ed8466a608b4 223 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 78:ed8466a608b4 224 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 225 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 226 } IPSR_Type;
emilmont 78:ed8466a608b4 227
emilmont 78:ed8466a608b4 228
emilmont 78:ed8466a608b4 229 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 78:ed8466a608b4 230 */
emilmont 78:ed8466a608b4 231 typedef union
emilmont 78:ed8466a608b4 232 {
emilmont 78:ed8466a608b4 233 struct
emilmont 78:ed8466a608b4 234 {
emilmont 78:ed8466a608b4 235 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 78:ed8466a608b4 236 #if (__CORTEX_M != 0x04)
emilmont 78:ed8466a608b4 237 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 78:ed8466a608b4 238 #else
emilmont 78:ed8466a608b4 239 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
emilmont 78:ed8466a608b4 240 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
emilmont 78:ed8466a608b4 241 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
emilmont 78:ed8466a608b4 242 #endif
emilmont 78:ed8466a608b4 243 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
emilmont 78:ed8466a608b4 244 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
emilmont 78:ed8466a608b4 245 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
emilmont 78:ed8466a608b4 246 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 78:ed8466a608b4 247 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 78:ed8466a608b4 248 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 78:ed8466a608b4 249 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 78:ed8466a608b4 250 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 251 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 252 } xPSR_Type;
emilmont 78:ed8466a608b4 253
emilmont 78:ed8466a608b4 254
emilmont 78:ed8466a608b4 255 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 78:ed8466a608b4 256 */
emilmont 78:ed8466a608b4 257 typedef union
emilmont 78:ed8466a608b4 258 {
emilmont 78:ed8466a608b4 259 struct
emilmont 78:ed8466a608b4 260 {
emilmont 78:ed8466a608b4 261 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
emilmont 78:ed8466a608b4 262 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
emilmont 78:ed8466a608b4 263 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
emilmont 78:ed8466a608b4 264 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
emilmont 78:ed8466a608b4 265 } b; /*!< Structure used for bit access */
emilmont 78:ed8466a608b4 266 uint32_t w; /*!< Type used for word access */
emilmont 78:ed8466a608b4 267 } CONTROL_Type;
emilmont 78:ed8466a608b4 268
emilmont 78:ed8466a608b4 269 /*@} end of group CMSIS_CORE */
emilmont 78:ed8466a608b4 270
emilmont 78:ed8466a608b4 271
emilmont 78:ed8466a608b4 272 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 273 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 78:ed8466a608b4 274 \brief Type definitions for the NVIC Registers
emilmont 78:ed8466a608b4 275 @{
emilmont 78:ed8466a608b4 276 */
emilmont 78:ed8466a608b4 277
emilmont 78:ed8466a608b4 278 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 78:ed8466a608b4 279 */
emilmont 78:ed8466a608b4 280 typedef struct
emilmont 78:ed8466a608b4 281 {
emilmont 78:ed8466a608b4 282 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 78:ed8466a608b4 283 uint32_t RESERVED0[31];
emilmont 78:ed8466a608b4 284 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 78:ed8466a608b4 285 uint32_t RSERVED1[31];
emilmont 78:ed8466a608b4 286 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 78:ed8466a608b4 287 uint32_t RESERVED2[31];
emilmont 78:ed8466a608b4 288 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 78:ed8466a608b4 289 uint32_t RESERVED3[31];
emilmont 78:ed8466a608b4 290 uint32_t RESERVED4[64];
emilmont 78:ed8466a608b4 291 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 78:ed8466a608b4 292 } NVIC_Type;
emilmont 78:ed8466a608b4 293
emilmont 78:ed8466a608b4 294 /*@} end of group CMSIS_NVIC */
emilmont 78:ed8466a608b4 295
emilmont 78:ed8466a608b4 296
emilmont 78:ed8466a608b4 297 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 298 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 78:ed8466a608b4 299 \brief Type definitions for the System Control Block Registers
emilmont 78:ed8466a608b4 300 @{
emilmont 78:ed8466a608b4 301 */
emilmont 78:ed8466a608b4 302
emilmont 78:ed8466a608b4 303 /** \brief Structure type to access the System Control Block (SCB).
emilmont 78:ed8466a608b4 304 */
emilmont 78:ed8466a608b4 305 typedef struct
emilmont 78:ed8466a608b4 306 {
emilmont 78:ed8466a608b4 307 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 78:ed8466a608b4 308 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 78:ed8466a608b4 309 uint32_t RESERVED0;
emilmont 78:ed8466a608b4 310 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 78:ed8466a608b4 311 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 78:ed8466a608b4 312 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 78:ed8466a608b4 313 uint32_t RESERVED1;
emilmont 78:ed8466a608b4 314 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 78:ed8466a608b4 315 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 78:ed8466a608b4 316 } SCB_Type;
emilmont 78:ed8466a608b4 317
emilmont 78:ed8466a608b4 318 /* SCB CPUID Register Definitions */
emilmont 78:ed8466a608b4 319 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 78:ed8466a608b4 320 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 78:ed8466a608b4 321
emilmont 78:ed8466a608b4 322 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 78:ed8466a608b4 323 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 78:ed8466a608b4 324
emilmont 78:ed8466a608b4 325 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 78:ed8466a608b4 326 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 78:ed8466a608b4 327
emilmont 78:ed8466a608b4 328 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 78:ed8466a608b4 329 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 78:ed8466a608b4 330
emilmont 78:ed8466a608b4 331 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
emilmont 78:ed8466a608b4 332 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
emilmont 78:ed8466a608b4 333
emilmont 78:ed8466a608b4 334 /* SCB Interrupt Control State Register Definitions */
emilmont 78:ed8466a608b4 335 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 78:ed8466a608b4 336 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 78:ed8466a608b4 337
emilmont 78:ed8466a608b4 338 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 78:ed8466a608b4 339 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 78:ed8466a608b4 340
emilmont 78:ed8466a608b4 341 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 78:ed8466a608b4 342 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 78:ed8466a608b4 343
emilmont 78:ed8466a608b4 344 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 78:ed8466a608b4 345 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 78:ed8466a608b4 346
emilmont 78:ed8466a608b4 347 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 78:ed8466a608b4 348 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 78:ed8466a608b4 349
emilmont 78:ed8466a608b4 350 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 78:ed8466a608b4 351 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 78:ed8466a608b4 352
emilmont 78:ed8466a608b4 353 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 78:ed8466a608b4 354 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 78:ed8466a608b4 355
emilmont 78:ed8466a608b4 356 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 78:ed8466a608b4 357 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 78:ed8466a608b4 358
emilmont 78:ed8466a608b4 359 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
emilmont 78:ed8466a608b4 360 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 78:ed8466a608b4 361
emilmont 78:ed8466a608b4 362 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 78:ed8466a608b4 363 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 78:ed8466a608b4 364 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 78:ed8466a608b4 365
emilmont 78:ed8466a608b4 366 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 78:ed8466a608b4 367 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 78:ed8466a608b4 368
emilmont 78:ed8466a608b4 369 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 78:ed8466a608b4 370 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 78:ed8466a608b4 371
emilmont 78:ed8466a608b4 372 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 78:ed8466a608b4 373 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 78:ed8466a608b4 374
emilmont 78:ed8466a608b4 375 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 78:ed8466a608b4 376 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 78:ed8466a608b4 377
emilmont 78:ed8466a608b4 378 /* SCB System Control Register Definitions */
emilmont 78:ed8466a608b4 379 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 78:ed8466a608b4 380 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 78:ed8466a608b4 381
emilmont 78:ed8466a608b4 382 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 78:ed8466a608b4 383 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 78:ed8466a608b4 384
emilmont 78:ed8466a608b4 385 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 78:ed8466a608b4 386 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 78:ed8466a608b4 387
emilmont 78:ed8466a608b4 388 /* SCB Configuration Control Register Definitions */
emilmont 78:ed8466a608b4 389 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 78:ed8466a608b4 390 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 78:ed8466a608b4 391
emilmont 78:ed8466a608b4 392 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 78:ed8466a608b4 393 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 78:ed8466a608b4 394
emilmont 78:ed8466a608b4 395 /* SCB System Handler Control and State Register Definitions */
emilmont 78:ed8466a608b4 396 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 78:ed8466a608b4 397 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 78:ed8466a608b4 398
emilmont 78:ed8466a608b4 399 /*@} end of group CMSIS_SCB */
emilmont 78:ed8466a608b4 400
emilmont 78:ed8466a608b4 401
emilmont 78:ed8466a608b4 402 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 403 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 78:ed8466a608b4 404 \brief Type definitions for the System Timer Registers.
emilmont 78:ed8466a608b4 405 @{
emilmont 78:ed8466a608b4 406 */
emilmont 78:ed8466a608b4 407
emilmont 78:ed8466a608b4 408 /** \brief Structure type to access the System Timer (SysTick).
emilmont 78:ed8466a608b4 409 */
emilmont 78:ed8466a608b4 410 typedef struct
emilmont 78:ed8466a608b4 411 {
emilmont 78:ed8466a608b4 412 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 78:ed8466a608b4 413 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 78:ed8466a608b4 414 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 78:ed8466a608b4 415 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 78:ed8466a608b4 416 } SysTick_Type;
emilmont 78:ed8466a608b4 417
emilmont 78:ed8466a608b4 418 /* SysTick Control / Status Register Definitions */
emilmont 78:ed8466a608b4 419 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 78:ed8466a608b4 420 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 78:ed8466a608b4 421
emilmont 78:ed8466a608b4 422 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 78:ed8466a608b4 423 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 78:ed8466a608b4 424
emilmont 78:ed8466a608b4 425 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 78:ed8466a608b4 426 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 78:ed8466a608b4 427
emilmont 78:ed8466a608b4 428 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
emilmont 78:ed8466a608b4 429 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
emilmont 78:ed8466a608b4 430
emilmont 78:ed8466a608b4 431 /* SysTick Reload Register Definitions */
emilmont 78:ed8466a608b4 432 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
emilmont 78:ed8466a608b4 433 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
emilmont 78:ed8466a608b4 434
emilmont 78:ed8466a608b4 435 /* SysTick Current Register Definitions */
emilmont 78:ed8466a608b4 436 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
emilmont 78:ed8466a608b4 437 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
emilmont 78:ed8466a608b4 438
emilmont 78:ed8466a608b4 439 /* SysTick Calibration Register Definitions */
emilmont 78:ed8466a608b4 440 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 78:ed8466a608b4 441 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 78:ed8466a608b4 442
emilmont 78:ed8466a608b4 443 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 78:ed8466a608b4 444 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 78:ed8466a608b4 445
emilmont 78:ed8466a608b4 446 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
emilmont 78:ed8466a608b4 447 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
emilmont 78:ed8466a608b4 448
emilmont 78:ed8466a608b4 449 /*@} end of group CMSIS_SysTick */
emilmont 78:ed8466a608b4 450
emilmont 78:ed8466a608b4 451
emilmont 78:ed8466a608b4 452 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 453 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 78:ed8466a608b4 454 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 78:ed8466a608b4 455 are only accessible over DAP and not via processor. Therefore
emilmont 78:ed8466a608b4 456 they are not covered by the Cortex-M0 header file.
emilmont 78:ed8466a608b4 457 @{
emilmont 78:ed8466a608b4 458 */
emilmont 78:ed8466a608b4 459 /*@} end of group CMSIS_CoreDebug */
emilmont 78:ed8466a608b4 460
emilmont 78:ed8466a608b4 461
emilmont 78:ed8466a608b4 462 /** \ingroup CMSIS_core_register
emilmont 78:ed8466a608b4 463 \defgroup CMSIS_core_base Core Definitions
emilmont 78:ed8466a608b4 464 \brief Definitions for base addresses, unions, and structures.
emilmont 78:ed8466a608b4 465 @{
emilmont 78:ed8466a608b4 466 */
emilmont 78:ed8466a608b4 467
emilmont 78:ed8466a608b4 468 /* Memory mapping of Cortex-M0 Hardware */
emilmont 78:ed8466a608b4 469 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 78:ed8466a608b4 470 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 78:ed8466a608b4 471 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 78:ed8466a608b4 472 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 78:ed8466a608b4 473
emilmont 78:ed8466a608b4 474 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 78:ed8466a608b4 475 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 78:ed8466a608b4 476 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 78:ed8466a608b4 477
emilmont 78:ed8466a608b4 478
emilmont 78:ed8466a608b4 479 /*@} */
emilmont 78:ed8466a608b4 480
emilmont 78:ed8466a608b4 481
emilmont 78:ed8466a608b4 482
emilmont 78:ed8466a608b4 483 /*******************************************************************************
emilmont 78:ed8466a608b4 484 * Hardware Abstraction Layer
emilmont 78:ed8466a608b4 485 Core Function Interface contains:
emilmont 78:ed8466a608b4 486 - Core NVIC Functions
emilmont 78:ed8466a608b4 487 - Core SysTick Functions
emilmont 78:ed8466a608b4 488 - Core Register Access Functions
emilmont 78:ed8466a608b4 489 ******************************************************************************/
emilmont 78:ed8466a608b4 490 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 78:ed8466a608b4 491 */
emilmont 78:ed8466a608b4 492
emilmont 78:ed8466a608b4 493
emilmont 78:ed8466a608b4 494
emilmont 78:ed8466a608b4 495 /* ########################## NVIC functions #################################### */
emilmont 78:ed8466a608b4 496 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 497 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 78:ed8466a608b4 498 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 78:ed8466a608b4 499 @{
emilmont 78:ed8466a608b4 500 */
emilmont 78:ed8466a608b4 501
emilmont 78:ed8466a608b4 502 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 78:ed8466a608b4 503 /* The following MACROS handle generation of the register offset and byte masks */
emilmont 78:ed8466a608b4 504 #define _BIT_SHIFT(IRQn) ( (((uint32_t)(IRQn) ) & 0x03) * 8 )
emilmont 78:ed8466a608b4 505 #define _SHP_IDX(IRQn) ( ((((uint32_t)(IRQn) & 0x0F)-8) >> 2) )
emilmont 78:ed8466a608b4 506 #define _IP_IDX(IRQn) ( ((uint32_t)(IRQn) >> 2) )
emilmont 78:ed8466a608b4 507
emilmont 78:ed8466a608b4 508
emilmont 78:ed8466a608b4 509 /** \brief Enable External Interrupt
emilmont 78:ed8466a608b4 510
emilmont 78:ed8466a608b4 511 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 78:ed8466a608b4 512
emilmont 78:ed8466a608b4 513 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 514 */
emilmont 78:ed8466a608b4 515 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 516 {
emilmont 78:ed8466a608b4 517 NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 78:ed8466a608b4 518 }
emilmont 78:ed8466a608b4 519
emilmont 78:ed8466a608b4 520
emilmont 78:ed8466a608b4 521 /** \brief Disable External Interrupt
emilmont 78:ed8466a608b4 522
emilmont 78:ed8466a608b4 523 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 78:ed8466a608b4 524
emilmont 78:ed8466a608b4 525 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 526 */
emilmont 78:ed8466a608b4 527 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 528 {
emilmont 78:ed8466a608b4 529 NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 78:ed8466a608b4 530 }
emilmont 78:ed8466a608b4 531
emilmont 78:ed8466a608b4 532
emilmont 78:ed8466a608b4 533 /** \brief Get Pending Interrupt
emilmont 78:ed8466a608b4 534
emilmont 78:ed8466a608b4 535 The function reads the pending register in the NVIC and returns the pending bit
emilmont 78:ed8466a608b4 536 for the specified interrupt.
emilmont 78:ed8466a608b4 537
emilmont 78:ed8466a608b4 538 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 539
emilmont 78:ed8466a608b4 540 \return 0 Interrupt status is not pending.
emilmont 78:ed8466a608b4 541 \return 1 Interrupt status is pending.
emilmont 78:ed8466a608b4 542 */
emilmont 78:ed8466a608b4 543 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 544 {
emilmont 78:ed8466a608b4 545 return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
emilmont 78:ed8466a608b4 546 }
emilmont 78:ed8466a608b4 547
emilmont 78:ed8466a608b4 548
emilmont 78:ed8466a608b4 549 /** \brief Set Pending Interrupt
emilmont 78:ed8466a608b4 550
emilmont 78:ed8466a608b4 551 The function sets the pending bit of an external interrupt.
emilmont 78:ed8466a608b4 552
emilmont 78:ed8466a608b4 553 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 554 */
emilmont 78:ed8466a608b4 555 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 556 {
emilmont 78:ed8466a608b4 557 NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
emilmont 78:ed8466a608b4 558 }
emilmont 78:ed8466a608b4 559
emilmont 78:ed8466a608b4 560
emilmont 78:ed8466a608b4 561 /** \brief Clear Pending Interrupt
emilmont 78:ed8466a608b4 562
emilmont 78:ed8466a608b4 563 The function clears the pending bit of an external interrupt.
emilmont 78:ed8466a608b4 564
emilmont 78:ed8466a608b4 565 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 78:ed8466a608b4 566 */
emilmont 78:ed8466a608b4 567 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 568 {
emilmont 78:ed8466a608b4 569 NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
emilmont 78:ed8466a608b4 570 }
emilmont 78:ed8466a608b4 571
emilmont 78:ed8466a608b4 572
emilmont 78:ed8466a608b4 573 /** \brief Set Interrupt Priority
emilmont 78:ed8466a608b4 574
emilmont 78:ed8466a608b4 575 The function sets the priority of an interrupt.
emilmont 78:ed8466a608b4 576
emilmont 78:ed8466a608b4 577 \note The priority cannot be set for every core interrupt.
emilmont 78:ed8466a608b4 578
emilmont 78:ed8466a608b4 579 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 580 \param [in] priority Priority to set.
emilmont 78:ed8466a608b4 581 */
emilmont 78:ed8466a608b4 582 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 78:ed8466a608b4 583 {
emilmont 78:ed8466a608b4 584 if(IRQn < 0) {
emilmont 78:ed8466a608b4 585 SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 78:ed8466a608b4 586 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 78:ed8466a608b4 587 else {
emilmont 78:ed8466a608b4 588 NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
emilmont 78:ed8466a608b4 589 (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
emilmont 78:ed8466a608b4 590 }
emilmont 78:ed8466a608b4 591
emilmont 78:ed8466a608b4 592
emilmont 78:ed8466a608b4 593 /** \brief Get Interrupt Priority
emilmont 78:ed8466a608b4 594
emilmont 78:ed8466a608b4 595 The function reads the priority of an interrupt. The interrupt
emilmont 78:ed8466a608b4 596 number can be positive to specify an external (device specific)
emilmont 78:ed8466a608b4 597 interrupt, or negative to specify an internal (core) interrupt.
emilmont 78:ed8466a608b4 598
emilmont 78:ed8466a608b4 599
emilmont 78:ed8466a608b4 600 \param [in] IRQn Interrupt number.
emilmont 78:ed8466a608b4 601 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 78:ed8466a608b4 602 priority bits of the microcontroller.
emilmont 78:ed8466a608b4 603 */
emilmont 78:ed8466a608b4 604 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 78:ed8466a608b4 605 {
emilmont 78:ed8466a608b4 606
emilmont 78:ed8466a608b4 607 if(IRQn < 0) {
emilmont 78:ed8466a608b4 608 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M0 system interrupts */
emilmont 78:ed8466a608b4 609 else {
emilmont 78:ed8466a608b4 610 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & 0xFF) >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
emilmont 78:ed8466a608b4 611 }
emilmont 78:ed8466a608b4 612
emilmont 78:ed8466a608b4 613
emilmont 78:ed8466a608b4 614 /** \brief System Reset
emilmont 78:ed8466a608b4 615
emilmont 78:ed8466a608b4 616 The function initiates a system reset request to reset the MCU.
emilmont 78:ed8466a608b4 617 */
emilmont 78:ed8466a608b4 618 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 78:ed8466a608b4 619 {
emilmont 78:ed8466a608b4 620 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 78:ed8466a608b4 621 buffered write are completed before reset */
emilmont 78:ed8466a608b4 622 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
emilmont 78:ed8466a608b4 623 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 78:ed8466a608b4 624 __DSB(); /* Ensure completion of memory access */
emilmont 78:ed8466a608b4 625 while(1); /* wait until reset */
emilmont 78:ed8466a608b4 626 }
emilmont 78:ed8466a608b4 627
emilmont 78:ed8466a608b4 628 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 78:ed8466a608b4 629
emilmont 78:ed8466a608b4 630
emilmont 78:ed8466a608b4 631
emilmont 78:ed8466a608b4 632 /* ################################## SysTick function ############################################ */
emilmont 78:ed8466a608b4 633 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 634 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 78:ed8466a608b4 635 \brief Functions that configure the System.
emilmont 78:ed8466a608b4 636 @{
emilmont 78:ed8466a608b4 637 */
emilmont 78:ed8466a608b4 638
emilmont 78:ed8466a608b4 639 #if (__Vendor_SysTickConfig == 0)
emilmont 78:ed8466a608b4 640
emilmont 78:ed8466a608b4 641 /** \brief System Tick Configuration
emilmont 78:ed8466a608b4 642
emilmont 78:ed8466a608b4 643 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 78:ed8466a608b4 644 Counter is in free running mode to generate periodic interrupts.
emilmont 78:ed8466a608b4 645
emilmont 78:ed8466a608b4 646 \param [in] ticks Number of ticks between two interrupts.
emilmont 78:ed8466a608b4 647
emilmont 78:ed8466a608b4 648 \return 0 Function succeeded.
emilmont 78:ed8466a608b4 649 \return 1 Function failed.
emilmont 78:ed8466a608b4 650
emilmont 78:ed8466a608b4 651 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 78:ed8466a608b4 652 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 78:ed8466a608b4 653 must contain a vendor-specific implementation of this function.
emilmont 78:ed8466a608b4 654
emilmont 78:ed8466a608b4 655 */
emilmont 78:ed8466a608b4 656 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 78:ed8466a608b4 657 {
emilmont 78:ed8466a608b4 658 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
emilmont 78:ed8466a608b4 659
emilmont 78:ed8466a608b4 660 SysTick->LOAD = ticks - 1; /* set reload register */
emilmont 78:ed8466a608b4 661 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
emilmont 78:ed8466a608b4 662 SysTick->VAL = 0; /* Load the SysTick Counter Value */
emilmont 78:ed8466a608b4 663 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 78:ed8466a608b4 664 SysTick_CTRL_TICKINT_Msk |
emilmont 78:ed8466a608b4 665 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
emilmont 78:ed8466a608b4 666 return (0); /* Function successful */
emilmont 78:ed8466a608b4 667 }
emilmont 78:ed8466a608b4 668
emilmont 78:ed8466a608b4 669 #endif
emilmont 78:ed8466a608b4 670
emilmont 78:ed8466a608b4 671 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 78:ed8466a608b4 672
emilmont 78:ed8466a608b4 673
emilmont 78:ed8466a608b4 674
emilmont 78:ed8466a608b4 675
emilmont 78:ed8466a608b4 676 #endif /* __CORE_CM0_H_DEPENDANT */
emilmont 78:ed8466a608b4 677
emilmont 78:ed8466a608b4 678 #endif /* __CMSIS_GENERIC */
emilmont 78:ed8466a608b4 679
emilmont 78:ed8466a608b4 680 #ifdef __cplusplus
emilmont 78:ed8466a608b4 681 }
emilmont 78:ed8466a608b4 682 #endif