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TARGET_KL25Z/MKL25Z4.h@64:e3affc9e7238, 2013-08-05 (annotated)

Committer:: bogdanm
Date:: Mon Aug 05 12:28:09 2013 +0300
Revision:: 64:e3affc9e7238
Parent:: KL25Z/MKL25Z4.h@60:3d0ef94e36ec
Child:: 65:5798e58a58b1

New build system structure, new target (LPC1347), bug fixes (I2C read/write errors, LPC11U24 memory map and others)

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	60:3d0ef94e36ec	1	/*
emilmont	60:3d0ef94e36ec	2	** ###################################################################
emilmont	60:3d0ef94e36ec	3	** Processor: MKL25Z128VLK4
emilmont	60:3d0ef94e36ec	4	** Compilers: ARM Compiler
emilmont	60:3d0ef94e36ec	5	** Freescale C/C++ for Embedded ARM
emilmont	60:3d0ef94e36ec	6	** GNU C Compiler
emilmont	60:3d0ef94e36ec	7	** IAR ANSI C/C++ Compiler for ARM
emilmont	60:3d0ef94e36ec	8	**
emilmont	60:3d0ef94e36ec	9	** Reference manual: KL25RM, Rev.1, Jun 2012
emilmont	60:3d0ef94e36ec	10	** Version: rev. 1.1, 2012-06-21
emilmont	60:3d0ef94e36ec	11	**
emilmont	60:3d0ef94e36ec	12	** Abstract:
emilmont	60:3d0ef94e36ec	13	** CMSIS Peripheral Access Layer for MKL25Z4
emilmont	60:3d0ef94e36ec	14	**
emilmont	60:3d0ef94e36ec	15	** Copyright: 1997 - 2012 Freescale Semiconductor, Inc. All Rights Reserved.
emilmont	60:3d0ef94e36ec	16	**
emilmont	60:3d0ef94e36ec	17	** http: www.freescale.com
emilmont	60:3d0ef94e36ec	18	** mail: support@freescale.com
emilmont	60:3d0ef94e36ec	19	**
emilmont	60:3d0ef94e36ec	20	** Revisions:
emilmont	60:3d0ef94e36ec	21	** - rev. 1.0 (2012-06-13)
emilmont	60:3d0ef94e36ec	22	** Initial version.
emilmont	60:3d0ef94e36ec	23	** - rev. 1.1 (2012-06-21)
emilmont	60:3d0ef94e36ec	24	** Update according to reference manual rev. 1.
emilmont	60:3d0ef94e36ec	25	**
emilmont	60:3d0ef94e36ec	26	** ###################################################################
emilmont	60:3d0ef94e36ec	27	*/
emilmont	60:3d0ef94e36ec	28
emilmont	60:3d0ef94e36ec	29	/**
emilmont	60:3d0ef94e36ec	30	* @file MKL25Z4.h
emilmont	60:3d0ef94e36ec	31	* @version 1.1
emilmont	60:3d0ef94e36ec	32	* @date 2012-06-21
emilmont	60:3d0ef94e36ec	33	* @brief CMSIS Peripheral Access Layer for MKL25Z4
emilmont	60:3d0ef94e36ec	34	*
emilmont	60:3d0ef94e36ec	35	* CMSIS Peripheral Access Layer for MKL25Z4
emilmont	60:3d0ef94e36ec	36	*/
emilmont	60:3d0ef94e36ec	37
emilmont	60:3d0ef94e36ec	38	#if !defined(MKL25Z4_H_)
emilmont	60:3d0ef94e36ec	39	#define MKL25Z4_H_ /*< Symbol preventing repeated inclusion /
emilmont	60:3d0ef94e36ec	40
emilmont	60:3d0ef94e36ec	41	/** Memory map major version (memory maps with equal major version number are
emilmont	60:3d0ef94e36ec	42	* compatible) */
emilmont	60:3d0ef94e36ec	43	#define MCU_MEM_MAP_VERSION 0x0100u
emilmont	60:3d0ef94e36ec	44	/** Memory map minor version */
emilmont	60:3d0ef94e36ec	45	#define MCU_MEM_MAP_VERSION_MINOR 0x0001u
emilmont	60:3d0ef94e36ec	46
emilmont	60:3d0ef94e36ec	47
emilmont	60:3d0ef94e36ec	48	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	49	-- Interrupt vector numbers
emilmont	60:3d0ef94e36ec	50	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	51
emilmont	60:3d0ef94e36ec	52	/**
emilmont	60:3d0ef94e36ec	53	* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
emilmont	60:3d0ef94e36ec	54	* @{
emilmont	60:3d0ef94e36ec	55	*/
emilmont	60:3d0ef94e36ec	56
emilmont	60:3d0ef94e36ec	57	/** Interrupt Number Definitions */
emilmont	60:3d0ef94e36ec	58	typedef enum IRQn {
emilmont	60:3d0ef94e36ec	59	/* Core interrupts */
emilmont	60:3d0ef94e36ec	60	NonMaskableInt_IRQn = -14, /*< Non Maskable Interrupt /
emilmont	60:3d0ef94e36ec	61	HardFault_IRQn = -13, /*< Cortex-M0 SV Hard Fault Interrupt /
emilmont	60:3d0ef94e36ec	62	SVCall_IRQn = -5, /*< Cortex-M0 SV Call Interrupt /
emilmont	60:3d0ef94e36ec	63	PendSV_IRQn = -2, /*< Cortex-M0 Pend SV Interrupt /
emilmont	60:3d0ef94e36ec	64	SysTick_IRQn = -1, /*< Cortex-M0 System Tick Interrupt /
emilmont	60:3d0ef94e36ec	65
emilmont	60:3d0ef94e36ec	66	/* Device specific interrupts */
emilmont	60:3d0ef94e36ec	67	DMA0_IRQn = 0, /*< DMA channel 0 transfer complete interrupt /
emilmont	60:3d0ef94e36ec	68	DMA1_IRQn = 1, /*< DMA channel 1 transfer complete interrupt /
emilmont	60:3d0ef94e36ec	69	DMA2_IRQn = 2, /*< DMA channel 2 transfer complete interrupt /
emilmont	60:3d0ef94e36ec	70	DMA3_IRQn = 3, /*< DMA channel 3 transfer complete interrupt /
emilmont	60:3d0ef94e36ec	71	Reserved20_IRQn = 4, /*< Reserved interrupt 20 /
emilmont	60:3d0ef94e36ec	72	FTFA_IRQn = 5, /*< FTFA interrupt /
emilmont	60:3d0ef94e36ec	73	LVD_LVW_IRQn = 6, /*< Low Voltage Detect, Low Voltage Warning /
emilmont	60:3d0ef94e36ec	74	LLW_IRQn = 7, /*< Low Leakage Wakeup /
emilmont	60:3d0ef94e36ec	75	I2C0_IRQn = 8, /*< I2C0 interrupt /
emilmont	60:3d0ef94e36ec	76	I2C1_IRQn = 9, /*< I2C0 interrupt 25 /
emilmont	60:3d0ef94e36ec	77	SPI0_IRQn = 10, /*< SPI0 interrupt /
emilmont	60:3d0ef94e36ec	78	SPI1_IRQn = 11, /*< SPI1 interrupt /
emilmont	60:3d0ef94e36ec	79	UART0_IRQn = 12, /*< UART0 status/error interrupt /
emilmont	60:3d0ef94e36ec	80	UART1_IRQn = 13, /*< UART1 status/error interrupt /
emilmont	60:3d0ef94e36ec	81	UART2_IRQn = 14, /*< UART2 status/error interrupt /
emilmont	60:3d0ef94e36ec	82	ADC0_IRQn = 15, /*< ADC0 interrupt /
emilmont	60:3d0ef94e36ec	83	CMP0_IRQn = 16, /*< CMP0 interrupt /
emilmont	60:3d0ef94e36ec	84	TPM0_IRQn = 17, /*< TPM0 fault, overflow and channels interrupt /
emilmont	60:3d0ef94e36ec	85	TPM1_IRQn = 18, /*< TPM1 fault, overflow and channels interrupt /
emilmont	60:3d0ef94e36ec	86	TPM2_IRQn = 19, /*< TPM2 fault, overflow and channels interrupt /
emilmont	60:3d0ef94e36ec	87	RTC_IRQn = 20, /*< RTC interrupt /
emilmont	60:3d0ef94e36ec	88	RTC_Seconds_IRQn = 21, /*< RTC seconds interrupt /
emilmont	60:3d0ef94e36ec	89	PIT_IRQn = 22, /*< PIT timer interrupt /
emilmont	60:3d0ef94e36ec	90	Reserved39_IRQn = 23, /*< Reserved interrupt 39 /
emilmont	60:3d0ef94e36ec	91	USB0_IRQn = 24, /*< USB0 interrupt /
emilmont	60:3d0ef94e36ec	92	DAC0_IRQn = 25, /*< DAC interrupt /
emilmont	60:3d0ef94e36ec	93	TSI0_IRQn = 26, /*< TSI0 interrupt /
emilmont	60:3d0ef94e36ec	94	MCG_IRQn = 27, /*< MCG interrupt /
emilmont	60:3d0ef94e36ec	95	LPTimer_IRQn = 28, /*< LPTimer interrupt /
emilmont	60:3d0ef94e36ec	96	Reserved45_IRQn = 29, /*< Reserved interrupt 45 /
emilmont	60:3d0ef94e36ec	97	PORTA_IRQn = 30, /*< Port A interrupt /
emilmont	60:3d0ef94e36ec	98	PORTD_IRQn = 31 /*< Port D interrupt /
emilmont	60:3d0ef94e36ec	99	} IRQn_Type;
emilmont	60:3d0ef94e36ec	100
emilmont	60:3d0ef94e36ec	101	/**
emilmont	60:3d0ef94e36ec	102	* @}
emilmont	60:3d0ef94e36ec	103	/ / end of group Interrupt_vector_numbers */
emilmont	60:3d0ef94e36ec	104
emilmont	60:3d0ef94e36ec	105
emilmont	60:3d0ef94e36ec	106	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	107	-- Cortex M0 Core Configuration
emilmont	60:3d0ef94e36ec	108	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	109
emilmont	60:3d0ef94e36ec	110	/**
emilmont	60:3d0ef94e36ec	111	* @addtogroup Cortex_Core_Configuration Cortex M0 Core Configuration
emilmont	60:3d0ef94e36ec	112	* @{
emilmont	60:3d0ef94e36ec	113	*/
emilmont	60:3d0ef94e36ec	114
emilmont	60:3d0ef94e36ec	115	#define __CM0PLUS_REV 0x0000 /*< Core revision r0p0 /
emilmont	60:3d0ef94e36ec	116	#define __MPU_PRESENT 0 /*< Defines if an MPU is present or not /
emilmont	60:3d0ef94e36ec	117	#define __VTOR_PRESENT 1 /*< Defines if an MPU is present or not /
emilmont	60:3d0ef94e36ec	118	#define __NVIC_PRIO_BITS 2 /*< Number of priority bits implemented in the NVIC /
emilmont	60:3d0ef94e36ec	119	#define __Vendor_SysTickConfig 0 /*< Vendor specific implementation of SysTickConfig is defined /
emilmont	60:3d0ef94e36ec	120
emilmont	60:3d0ef94e36ec	121	#include "core_cm0plus.h" /* Core Peripheral Access Layer */
emilmont	60:3d0ef94e36ec	122	#include "system_MKL25Z4.h" /* Device specific configuration file */
emilmont	60:3d0ef94e36ec	123
emilmont	60:3d0ef94e36ec	124	/**
emilmont	60:3d0ef94e36ec	125	* @}
emilmont	60:3d0ef94e36ec	126	/ / end of group Cortex_Core_Configuration */
emilmont	60:3d0ef94e36ec	127
emilmont	60:3d0ef94e36ec	128
emilmont	60:3d0ef94e36ec	129	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	130	-- Device Peripheral Access Layer
emilmont	60:3d0ef94e36ec	131	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	132
emilmont	60:3d0ef94e36ec	133	/**
emilmont	60:3d0ef94e36ec	134	* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
emilmont	60:3d0ef94e36ec	135	* @{
emilmont	60:3d0ef94e36ec	136	*/
emilmont	60:3d0ef94e36ec	137
emilmont	60:3d0ef94e36ec	138
emilmont	60:3d0ef94e36ec	139	/*
emilmont	60:3d0ef94e36ec	140	** Start of section using anonymous unions
emilmont	60:3d0ef94e36ec	141	*/
emilmont	60:3d0ef94e36ec	142
emilmont	60:3d0ef94e36ec	143	#if defined(__ARMCC_VERSION)
emilmont	60:3d0ef94e36ec	144	#pragma push
emilmont	60:3d0ef94e36ec	145	#pragma anon_unions
emilmont	60:3d0ef94e36ec	146	#elif defined(__CWCC__)
emilmont	60:3d0ef94e36ec	147	#pragma push
emilmont	60:3d0ef94e36ec	148	#pragma cpp_extensions on
emilmont	60:3d0ef94e36ec	149	#elif defined(__GNUC__)
emilmont	60:3d0ef94e36ec	150	/* anonymous unions are enabled by default */
emilmont	60:3d0ef94e36ec	151	#elif defined(__IAR_SYSTEMS_ICC__)
emilmont	60:3d0ef94e36ec	152	#pragma language=extended
emilmont	60:3d0ef94e36ec	153	#else
emilmont	60:3d0ef94e36ec	154	#error Not supported compiler type
emilmont	60:3d0ef94e36ec	155	#endif
emilmont	60:3d0ef94e36ec	156
emilmont	60:3d0ef94e36ec	157	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	158	-- ADC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	159	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	160
emilmont	60:3d0ef94e36ec	161	/**
emilmont	60:3d0ef94e36ec	162	* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	163	* @{
emilmont	60:3d0ef94e36ec	164	*/
emilmont	60:3d0ef94e36ec	165
emilmont	60:3d0ef94e36ec	166	/** ADC - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	167	typedef struct {
emilmont	60:3d0ef94e36ec	168	__IO uint32_t SC1[2]; /*< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 /
emilmont	60:3d0ef94e36ec	169	__IO uint32_t CFG1; /*< ADC Configuration Register 1, offset: 0x8 /
emilmont	60:3d0ef94e36ec	170	__IO uint32_t CFG2; /*< ADC Configuration Register 2, offset: 0xC /
emilmont	60:3d0ef94e36ec	171	__I uint32_t R[2]; /*< ADC Data Result Register, array offset: 0x10, array step: 0x4 /
emilmont	60:3d0ef94e36ec	172	__IO uint32_t CV1; /*< Compare Value Registers, offset: 0x18 /
emilmont	60:3d0ef94e36ec	173	__IO uint32_t CV2; /*< Compare Value Registers, offset: 0x1C /
emilmont	60:3d0ef94e36ec	174	__IO uint32_t SC2; /*< Status and Control Register 2, offset: 0x20 /
emilmont	60:3d0ef94e36ec	175	__IO uint32_t SC3; /*< Status and Control Register 3, offset: 0x24 /
emilmont	60:3d0ef94e36ec	176	__IO uint32_t OFS; /*< ADC Offset Correction Register, offset: 0x28 /
emilmont	60:3d0ef94e36ec	177	__IO uint32_t PG; /*< ADC Plus-Side Gain Register, offset: 0x2C /
emilmont	60:3d0ef94e36ec	178	__IO uint32_t MG; /*< ADC Minus-Side Gain Register, offset: 0x30 /
emilmont	60:3d0ef94e36ec	179	__IO uint32_t CLPD; /*< ADC Plus-Side General Calibration Value Register, offset: 0x34 /
emilmont	60:3d0ef94e36ec	180	__IO uint32_t CLPS; /*< ADC Plus-Side General Calibration Value Register, offset: 0x38 /
emilmont	60:3d0ef94e36ec	181	__IO uint32_t CLP4; /*< ADC Plus-Side General Calibration Value Register, offset: 0x3C /
emilmont	60:3d0ef94e36ec	182	__IO uint32_t CLP3; /*< ADC Plus-Side General Calibration Value Register, offset: 0x40 /
emilmont	60:3d0ef94e36ec	183	__IO uint32_t CLP2; /*< ADC Plus-Side General Calibration Value Register, offset: 0x44 /
emilmont	60:3d0ef94e36ec	184	__IO uint32_t CLP1; /*< ADC Plus-Side General Calibration Value Register, offset: 0x48 /
emilmont	60:3d0ef94e36ec	185	__IO uint32_t CLP0; /*< ADC Plus-Side General Calibration Value Register, offset: 0x4C /
emilmont	60:3d0ef94e36ec	186	uint8_t RESERVED_0[4];
emilmont	60:3d0ef94e36ec	187	__IO uint32_t CLMD; /*< ADC Minus-Side General Calibration Value Register, offset: 0x54 /
emilmont	60:3d0ef94e36ec	188	__IO uint32_t CLMS; /*< ADC Minus-Side General Calibration Value Register, offset: 0x58 /
emilmont	60:3d0ef94e36ec	189	__IO uint32_t CLM4; /*< ADC Minus-Side General Calibration Value Register, offset: 0x5C /
emilmont	60:3d0ef94e36ec	190	__IO uint32_t CLM3; /*< ADC Minus-Side General Calibration Value Register, offset: 0x60 /
emilmont	60:3d0ef94e36ec	191	__IO uint32_t CLM2; /*< ADC Minus-Side General Calibration Value Register, offset: 0x64 /
emilmont	60:3d0ef94e36ec	192	__IO uint32_t CLM1; /*< ADC Minus-Side General Calibration Value Register, offset: 0x68 /
emilmont	60:3d0ef94e36ec	193	__IO uint32_t CLM0; /*< ADC Minus-Side General Calibration Value Register, offset: 0x6C /
emilmont	60:3d0ef94e36ec	194	} ADC_Type;
emilmont	60:3d0ef94e36ec	195
emilmont	60:3d0ef94e36ec	196	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	197	-- ADC Register Masks
emilmont	60:3d0ef94e36ec	198	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	199
emilmont	60:3d0ef94e36ec	200	/**
emilmont	60:3d0ef94e36ec	201	* @addtogroup ADC_Register_Masks ADC Register Masks
emilmont	60:3d0ef94e36ec	202	* @{
emilmont	60:3d0ef94e36ec	203	*/
emilmont	60:3d0ef94e36ec	204
emilmont	60:3d0ef94e36ec	205	/* SC1 Bit Fields */
emilmont	60:3d0ef94e36ec	206	#define ADC_SC1_ADCH_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	207	#define ADC_SC1_ADCH_SHIFT 0
emilmont	60:3d0ef94e36ec	208	#define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC1_ADCH_SHIFT))&ADC_SC1_ADCH_MASK)
emilmont	60:3d0ef94e36ec	209	#define ADC_SC1_DIFF_MASK 0x20u
emilmont	60:3d0ef94e36ec	210	#define ADC_SC1_DIFF_SHIFT 5
emilmont	60:3d0ef94e36ec	211	#define ADC_SC1_AIEN_MASK 0x40u
emilmont	60:3d0ef94e36ec	212	#define ADC_SC1_AIEN_SHIFT 6
emilmont	60:3d0ef94e36ec	213	#define ADC_SC1_COCO_MASK 0x80u
emilmont	60:3d0ef94e36ec	214	#define ADC_SC1_COCO_SHIFT 7
emilmont	60:3d0ef94e36ec	215	/* CFG1 Bit Fields */
emilmont	60:3d0ef94e36ec	216	#define ADC_CFG1_ADICLK_MASK 0x3u
emilmont	60:3d0ef94e36ec	217	#define ADC_CFG1_ADICLK_SHIFT 0
emilmont	60:3d0ef94e36ec	218	#define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADICLK_SHIFT))&ADC_CFG1_ADICLK_MASK)
emilmont	60:3d0ef94e36ec	219	#define ADC_CFG1_MODE_MASK 0xCu
emilmont	60:3d0ef94e36ec	220	#define ADC_CFG1_MODE_SHIFT 2
emilmont	60:3d0ef94e36ec	221	#define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_MODE_SHIFT))&ADC_CFG1_MODE_MASK)
emilmont	60:3d0ef94e36ec	222	#define ADC_CFG1_ADLSMP_MASK 0x10u
emilmont	60:3d0ef94e36ec	223	#define ADC_CFG1_ADLSMP_SHIFT 4
emilmont	60:3d0ef94e36ec	224	#define ADC_CFG1_ADIV_MASK 0x60u
emilmont	60:3d0ef94e36ec	225	#define ADC_CFG1_ADIV_SHIFT 5
emilmont	60:3d0ef94e36ec	226	#define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG1_ADIV_SHIFT))&ADC_CFG1_ADIV_MASK)
emilmont	60:3d0ef94e36ec	227	#define ADC_CFG1_ADLPC_MASK 0x80u
emilmont	60:3d0ef94e36ec	228	#define ADC_CFG1_ADLPC_SHIFT 7
emilmont	60:3d0ef94e36ec	229	/* CFG2 Bit Fields */
emilmont	60:3d0ef94e36ec	230	#define ADC_CFG2_ADLSTS_MASK 0x3u
emilmont	60:3d0ef94e36ec	231	#define ADC_CFG2_ADLSTS_SHIFT 0
emilmont	60:3d0ef94e36ec	232	#define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CFG2_ADLSTS_SHIFT))&ADC_CFG2_ADLSTS_MASK)
emilmont	60:3d0ef94e36ec	233	#define ADC_CFG2_ADHSC_MASK 0x4u
emilmont	60:3d0ef94e36ec	234	#define ADC_CFG2_ADHSC_SHIFT 2
emilmont	60:3d0ef94e36ec	235	#define ADC_CFG2_ADACKEN_MASK 0x8u
emilmont	60:3d0ef94e36ec	236	#define ADC_CFG2_ADACKEN_SHIFT 3
emilmont	60:3d0ef94e36ec	237	#define ADC_CFG2_MUXSEL_MASK 0x10u
emilmont	60:3d0ef94e36ec	238	#define ADC_CFG2_MUXSEL_SHIFT 4
emilmont	60:3d0ef94e36ec	239	/* R Bit Fields */
emilmont	60:3d0ef94e36ec	240	#define ADC_R_D_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	241	#define ADC_R_D_SHIFT 0
emilmont	60:3d0ef94e36ec	242	#define ADC_R_D(x) (((uint32_t)(((uint32_t)(x))<<ADC_R_D_SHIFT))&ADC_R_D_MASK)
emilmont	60:3d0ef94e36ec	243	/* CV1 Bit Fields */
emilmont	60:3d0ef94e36ec	244	#define ADC_CV1_CV_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	245	#define ADC_CV1_CV_SHIFT 0
emilmont	60:3d0ef94e36ec	246	#define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV1_CV_SHIFT))&ADC_CV1_CV_MASK)
emilmont	60:3d0ef94e36ec	247	/* CV2 Bit Fields */
emilmont	60:3d0ef94e36ec	248	#define ADC_CV2_CV_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	249	#define ADC_CV2_CV_SHIFT 0
emilmont	60:3d0ef94e36ec	250	#define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x))<<ADC_CV2_CV_SHIFT))&ADC_CV2_CV_MASK)
emilmont	60:3d0ef94e36ec	251	/* SC2 Bit Fields */
emilmont	60:3d0ef94e36ec	252	#define ADC_SC2_REFSEL_MASK 0x3u
emilmont	60:3d0ef94e36ec	253	#define ADC_SC2_REFSEL_SHIFT 0
emilmont	60:3d0ef94e36ec	254	#define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC2_REFSEL_SHIFT))&ADC_SC2_REFSEL_MASK)
emilmont	60:3d0ef94e36ec	255	#define ADC_SC2_DMAEN_MASK 0x4u
emilmont	60:3d0ef94e36ec	256	#define ADC_SC2_DMAEN_SHIFT 2
emilmont	60:3d0ef94e36ec	257	#define ADC_SC2_ACREN_MASK 0x8u
emilmont	60:3d0ef94e36ec	258	#define ADC_SC2_ACREN_SHIFT 3
emilmont	60:3d0ef94e36ec	259	#define ADC_SC2_ACFGT_MASK 0x10u
emilmont	60:3d0ef94e36ec	260	#define ADC_SC2_ACFGT_SHIFT 4
emilmont	60:3d0ef94e36ec	261	#define ADC_SC2_ACFE_MASK 0x20u
emilmont	60:3d0ef94e36ec	262	#define ADC_SC2_ACFE_SHIFT 5
emilmont	60:3d0ef94e36ec	263	#define ADC_SC2_ADTRG_MASK 0x40u
emilmont	60:3d0ef94e36ec	264	#define ADC_SC2_ADTRG_SHIFT 6
emilmont	60:3d0ef94e36ec	265	#define ADC_SC2_ADACT_MASK 0x80u
emilmont	60:3d0ef94e36ec	266	#define ADC_SC2_ADACT_SHIFT 7
emilmont	60:3d0ef94e36ec	267	/* SC3 Bit Fields */
emilmont	60:3d0ef94e36ec	268	#define ADC_SC3_AVGS_MASK 0x3u
emilmont	60:3d0ef94e36ec	269	#define ADC_SC3_AVGS_SHIFT 0
emilmont	60:3d0ef94e36ec	270	#define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x))<<ADC_SC3_AVGS_SHIFT))&ADC_SC3_AVGS_MASK)
emilmont	60:3d0ef94e36ec	271	#define ADC_SC3_AVGE_MASK 0x4u
emilmont	60:3d0ef94e36ec	272	#define ADC_SC3_AVGE_SHIFT 2
emilmont	60:3d0ef94e36ec	273	#define ADC_SC3_ADCO_MASK 0x8u
emilmont	60:3d0ef94e36ec	274	#define ADC_SC3_ADCO_SHIFT 3
emilmont	60:3d0ef94e36ec	275	#define ADC_SC3_CALF_MASK 0x40u
emilmont	60:3d0ef94e36ec	276	#define ADC_SC3_CALF_SHIFT 6
emilmont	60:3d0ef94e36ec	277	#define ADC_SC3_CAL_MASK 0x80u
emilmont	60:3d0ef94e36ec	278	#define ADC_SC3_CAL_SHIFT 7
emilmont	60:3d0ef94e36ec	279	/* OFS Bit Fields */
emilmont	60:3d0ef94e36ec	280	#define ADC_OFS_OFS_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	281	#define ADC_OFS_OFS_SHIFT 0
emilmont	60:3d0ef94e36ec	282	#define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x))<<ADC_OFS_OFS_SHIFT))&ADC_OFS_OFS_MASK)
emilmont	60:3d0ef94e36ec	283	/* PG Bit Fields */
emilmont	60:3d0ef94e36ec	284	#define ADC_PG_PG_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	285	#define ADC_PG_PG_SHIFT 0
emilmont	60:3d0ef94e36ec	286	#define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x))<<ADC_PG_PG_SHIFT))&ADC_PG_PG_MASK)
emilmont	60:3d0ef94e36ec	287	/* MG Bit Fields */
emilmont	60:3d0ef94e36ec	288	#define ADC_MG_MG_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	289	#define ADC_MG_MG_SHIFT 0
emilmont	60:3d0ef94e36ec	290	#define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x))<<ADC_MG_MG_SHIFT))&ADC_MG_MG_MASK)
emilmont	60:3d0ef94e36ec	291	/* CLPD Bit Fields */
emilmont	60:3d0ef94e36ec	292	#define ADC_CLPD_CLPD_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	293	#define ADC_CLPD_CLPD_SHIFT 0
emilmont	60:3d0ef94e36ec	294	#define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPD_CLPD_SHIFT))&ADC_CLPD_CLPD_MASK)
emilmont	60:3d0ef94e36ec	295	/* CLPS Bit Fields */
emilmont	60:3d0ef94e36ec	296	#define ADC_CLPS_CLPS_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	297	#define ADC_CLPS_CLPS_SHIFT 0
emilmont	60:3d0ef94e36ec	298	#define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLPS_CLPS_SHIFT))&ADC_CLPS_CLPS_MASK)
emilmont	60:3d0ef94e36ec	299	/* CLP4 Bit Fields */
emilmont	60:3d0ef94e36ec	300	#define ADC_CLP4_CLP4_MASK 0x3FFu
emilmont	60:3d0ef94e36ec	301	#define ADC_CLP4_CLP4_SHIFT 0
emilmont	60:3d0ef94e36ec	302	#define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP4_CLP4_SHIFT))&ADC_CLP4_CLP4_MASK)
emilmont	60:3d0ef94e36ec	303	/* CLP3 Bit Fields */
emilmont	60:3d0ef94e36ec	304	#define ADC_CLP3_CLP3_MASK 0x1FFu
emilmont	60:3d0ef94e36ec	305	#define ADC_CLP3_CLP3_SHIFT 0
emilmont	60:3d0ef94e36ec	306	#define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP3_CLP3_SHIFT))&ADC_CLP3_CLP3_MASK)
emilmont	60:3d0ef94e36ec	307	/* CLP2 Bit Fields */
emilmont	60:3d0ef94e36ec	308	#define ADC_CLP2_CLP2_MASK 0xFFu
emilmont	60:3d0ef94e36ec	309	#define ADC_CLP2_CLP2_SHIFT 0
emilmont	60:3d0ef94e36ec	310	#define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP2_CLP2_SHIFT))&ADC_CLP2_CLP2_MASK)
emilmont	60:3d0ef94e36ec	311	/* CLP1 Bit Fields */
emilmont	60:3d0ef94e36ec	312	#define ADC_CLP1_CLP1_MASK 0x7Fu
emilmont	60:3d0ef94e36ec	313	#define ADC_CLP1_CLP1_SHIFT 0
emilmont	60:3d0ef94e36ec	314	#define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP1_CLP1_SHIFT))&ADC_CLP1_CLP1_MASK)
emilmont	60:3d0ef94e36ec	315	/* CLP0 Bit Fields */
emilmont	60:3d0ef94e36ec	316	#define ADC_CLP0_CLP0_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	317	#define ADC_CLP0_CLP0_SHIFT 0
emilmont	60:3d0ef94e36ec	318	#define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLP0_CLP0_SHIFT))&ADC_CLP0_CLP0_MASK)
emilmont	60:3d0ef94e36ec	319	/* CLMD Bit Fields */
emilmont	60:3d0ef94e36ec	320	#define ADC_CLMD_CLMD_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	321	#define ADC_CLMD_CLMD_SHIFT 0
emilmont	60:3d0ef94e36ec	322	#define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMD_CLMD_SHIFT))&ADC_CLMD_CLMD_MASK)
emilmont	60:3d0ef94e36ec	323	/* CLMS Bit Fields */
emilmont	60:3d0ef94e36ec	324	#define ADC_CLMS_CLMS_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	325	#define ADC_CLMS_CLMS_SHIFT 0
emilmont	60:3d0ef94e36ec	326	#define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLMS_CLMS_SHIFT))&ADC_CLMS_CLMS_MASK)
emilmont	60:3d0ef94e36ec	327	/* CLM4 Bit Fields */
emilmont	60:3d0ef94e36ec	328	#define ADC_CLM4_CLM4_MASK 0x3FFu
emilmont	60:3d0ef94e36ec	329	#define ADC_CLM4_CLM4_SHIFT 0
emilmont	60:3d0ef94e36ec	330	#define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM4_CLM4_SHIFT))&ADC_CLM4_CLM4_MASK)
emilmont	60:3d0ef94e36ec	331	/* CLM3 Bit Fields */
emilmont	60:3d0ef94e36ec	332	#define ADC_CLM3_CLM3_MASK 0x1FFu
emilmont	60:3d0ef94e36ec	333	#define ADC_CLM3_CLM3_SHIFT 0
emilmont	60:3d0ef94e36ec	334	#define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM3_CLM3_SHIFT))&ADC_CLM3_CLM3_MASK)
emilmont	60:3d0ef94e36ec	335	/* CLM2 Bit Fields */
emilmont	60:3d0ef94e36ec	336	#define ADC_CLM2_CLM2_MASK 0xFFu
emilmont	60:3d0ef94e36ec	337	#define ADC_CLM2_CLM2_SHIFT 0
emilmont	60:3d0ef94e36ec	338	#define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM2_CLM2_SHIFT))&ADC_CLM2_CLM2_MASK)
emilmont	60:3d0ef94e36ec	339	/* CLM1 Bit Fields */
emilmont	60:3d0ef94e36ec	340	#define ADC_CLM1_CLM1_MASK 0x7Fu
emilmont	60:3d0ef94e36ec	341	#define ADC_CLM1_CLM1_SHIFT 0
emilmont	60:3d0ef94e36ec	342	#define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM1_CLM1_SHIFT))&ADC_CLM1_CLM1_MASK)
emilmont	60:3d0ef94e36ec	343	/* CLM0 Bit Fields */
emilmont	60:3d0ef94e36ec	344	#define ADC_CLM0_CLM0_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	345	#define ADC_CLM0_CLM0_SHIFT 0
emilmont	60:3d0ef94e36ec	346	#define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x))<<ADC_CLM0_CLM0_SHIFT))&ADC_CLM0_CLM0_MASK)
emilmont	60:3d0ef94e36ec	347
emilmont	60:3d0ef94e36ec	348	/**
emilmont	60:3d0ef94e36ec	349	* @}
emilmont	60:3d0ef94e36ec	350	/ / end of group ADC_Register_Masks */
emilmont	60:3d0ef94e36ec	351
emilmont	60:3d0ef94e36ec	352
emilmont	60:3d0ef94e36ec	353	/* ADC - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	354	/** Peripheral ADC0 base address */
emilmont	60:3d0ef94e36ec	355	#define ADC0_BASE (0x4003B000u)
emilmont	60:3d0ef94e36ec	356	/** Peripheral ADC0 base pointer */
emilmont	60:3d0ef94e36ec	357	#define ADC0 ((ADC_Type *)ADC0_BASE)
emilmont	60:3d0ef94e36ec	358	/** Array initializer of ADC peripheral base pointers */
emilmont	60:3d0ef94e36ec	359	#define ADC_BASES { ADC0 }
emilmont	60:3d0ef94e36ec	360
emilmont	60:3d0ef94e36ec	361	/**
emilmont	60:3d0ef94e36ec	362	* @}
emilmont	60:3d0ef94e36ec	363	/ / end of group ADC_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	364
emilmont	60:3d0ef94e36ec	365
emilmont	60:3d0ef94e36ec	366	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	367	-- CMP Peripheral Access Layer
emilmont	60:3d0ef94e36ec	368	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	369
emilmont	60:3d0ef94e36ec	370	/**
emilmont	60:3d0ef94e36ec	371	* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
emilmont	60:3d0ef94e36ec	372	* @{
emilmont	60:3d0ef94e36ec	373	*/
emilmont	60:3d0ef94e36ec	374
emilmont	60:3d0ef94e36ec	375	/** CMP - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	376	typedef struct {
emilmont	60:3d0ef94e36ec	377	__IO uint8_t CR0; /*< CMP Control Register 0, offset: 0x0 /
emilmont	60:3d0ef94e36ec	378	__IO uint8_t CR1; /*< CMP Control Register 1, offset: 0x1 /
emilmont	60:3d0ef94e36ec	379	__IO uint8_t FPR; /*< CMP Filter Period Register, offset: 0x2 /
emilmont	60:3d0ef94e36ec	380	__IO uint8_t SCR; /*< CMP Status and Control Register, offset: 0x3 /
emilmont	60:3d0ef94e36ec	381	__IO uint8_t DACCR; /*< DAC Control Register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	382	__IO uint8_t MUXCR; /*< MUX Control Register, offset: 0x5 /
emilmont	60:3d0ef94e36ec	383	} CMP_Type;
emilmont	60:3d0ef94e36ec	384
emilmont	60:3d0ef94e36ec	385	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	386	-- CMP Register Masks
emilmont	60:3d0ef94e36ec	387	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	388
emilmont	60:3d0ef94e36ec	389	/**
emilmont	60:3d0ef94e36ec	390	* @addtogroup CMP_Register_Masks CMP Register Masks
emilmont	60:3d0ef94e36ec	391	* @{
emilmont	60:3d0ef94e36ec	392	*/
emilmont	60:3d0ef94e36ec	393
emilmont	60:3d0ef94e36ec	394	/* CR0 Bit Fields */
emilmont	60:3d0ef94e36ec	395	#define CMP_CR0_HYSTCTR_MASK 0x3u
emilmont	60:3d0ef94e36ec	396	#define CMP_CR0_HYSTCTR_SHIFT 0
emilmont	60:3d0ef94e36ec	397	#define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_HYSTCTR_SHIFT))&CMP_CR0_HYSTCTR_MASK)
emilmont	60:3d0ef94e36ec	398	#define CMP_CR0_FILTER_CNT_MASK 0x70u
emilmont	60:3d0ef94e36ec	399	#define CMP_CR0_FILTER_CNT_SHIFT 4
emilmont	60:3d0ef94e36ec	400	#define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x))<<CMP_CR0_FILTER_CNT_SHIFT))&CMP_CR0_FILTER_CNT_MASK)
emilmont	60:3d0ef94e36ec	401	/* CR1 Bit Fields */
emilmont	60:3d0ef94e36ec	402	#define CMP_CR1_EN_MASK 0x1u
emilmont	60:3d0ef94e36ec	403	#define CMP_CR1_EN_SHIFT 0
emilmont	60:3d0ef94e36ec	404	#define CMP_CR1_OPE_MASK 0x2u
emilmont	60:3d0ef94e36ec	405	#define CMP_CR1_OPE_SHIFT 1
emilmont	60:3d0ef94e36ec	406	#define CMP_CR1_COS_MASK 0x4u
emilmont	60:3d0ef94e36ec	407	#define CMP_CR1_COS_SHIFT 2
emilmont	60:3d0ef94e36ec	408	#define CMP_CR1_INV_MASK 0x8u
emilmont	60:3d0ef94e36ec	409	#define CMP_CR1_INV_SHIFT 3
emilmont	60:3d0ef94e36ec	410	#define CMP_CR1_PMODE_MASK 0x10u
emilmont	60:3d0ef94e36ec	411	#define CMP_CR1_PMODE_SHIFT 4
emilmont	60:3d0ef94e36ec	412	#define CMP_CR1_TRIGM_MASK 0x20u
emilmont	60:3d0ef94e36ec	413	#define CMP_CR1_TRIGM_SHIFT 5
emilmont	60:3d0ef94e36ec	414	#define CMP_CR1_WE_MASK 0x40u
emilmont	60:3d0ef94e36ec	415	#define CMP_CR1_WE_SHIFT 6
emilmont	60:3d0ef94e36ec	416	#define CMP_CR1_SE_MASK 0x80u
emilmont	60:3d0ef94e36ec	417	#define CMP_CR1_SE_SHIFT 7
emilmont	60:3d0ef94e36ec	418	/* FPR Bit Fields */
emilmont	60:3d0ef94e36ec	419	#define CMP_FPR_FILT_PER_MASK 0xFFu
emilmont	60:3d0ef94e36ec	420	#define CMP_FPR_FILT_PER_SHIFT 0
emilmont	60:3d0ef94e36ec	421	#define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x))<<CMP_FPR_FILT_PER_SHIFT))&CMP_FPR_FILT_PER_MASK)
emilmont	60:3d0ef94e36ec	422	/* SCR Bit Fields */
emilmont	60:3d0ef94e36ec	423	#define CMP_SCR_COUT_MASK 0x1u
emilmont	60:3d0ef94e36ec	424	#define CMP_SCR_COUT_SHIFT 0
emilmont	60:3d0ef94e36ec	425	#define CMP_SCR_CFF_MASK 0x2u
emilmont	60:3d0ef94e36ec	426	#define CMP_SCR_CFF_SHIFT 1
emilmont	60:3d0ef94e36ec	427	#define CMP_SCR_CFR_MASK 0x4u
emilmont	60:3d0ef94e36ec	428	#define CMP_SCR_CFR_SHIFT 2
emilmont	60:3d0ef94e36ec	429	#define CMP_SCR_IEF_MASK 0x8u
emilmont	60:3d0ef94e36ec	430	#define CMP_SCR_IEF_SHIFT 3
emilmont	60:3d0ef94e36ec	431	#define CMP_SCR_IER_MASK 0x10u
emilmont	60:3d0ef94e36ec	432	#define CMP_SCR_IER_SHIFT 4
emilmont	60:3d0ef94e36ec	433	#define CMP_SCR_DMAEN_MASK 0x40u
emilmont	60:3d0ef94e36ec	434	#define CMP_SCR_DMAEN_SHIFT 6
emilmont	60:3d0ef94e36ec	435	/* DACCR Bit Fields */
emilmont	60:3d0ef94e36ec	436	#define CMP_DACCR_VOSEL_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	437	#define CMP_DACCR_VOSEL_SHIFT 0
emilmont	60:3d0ef94e36ec	438	#define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_DACCR_VOSEL_SHIFT))&CMP_DACCR_VOSEL_MASK)
emilmont	60:3d0ef94e36ec	439	#define CMP_DACCR_VRSEL_MASK 0x40u
emilmont	60:3d0ef94e36ec	440	#define CMP_DACCR_VRSEL_SHIFT 6
emilmont	60:3d0ef94e36ec	441	#define CMP_DACCR_DACEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	442	#define CMP_DACCR_DACEN_SHIFT 7
emilmont	60:3d0ef94e36ec	443	/* MUXCR Bit Fields */
emilmont	60:3d0ef94e36ec	444	#define CMP_MUXCR_MSEL_MASK 0x7u
emilmont	60:3d0ef94e36ec	445	#define CMP_MUXCR_MSEL_SHIFT 0
emilmont	60:3d0ef94e36ec	446	#define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_MSEL_SHIFT))&CMP_MUXCR_MSEL_MASK)
emilmont	60:3d0ef94e36ec	447	#define CMP_MUXCR_PSEL_MASK 0x38u
emilmont	60:3d0ef94e36ec	448	#define CMP_MUXCR_PSEL_SHIFT 3
emilmont	60:3d0ef94e36ec	449	#define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x))<<CMP_MUXCR_PSEL_SHIFT))&CMP_MUXCR_PSEL_MASK)
emilmont	60:3d0ef94e36ec	450	#define CMP_MUXCR_PSTM_MASK 0x40u
emilmont	60:3d0ef94e36ec	451	#define CMP_MUXCR_PSTM_SHIFT 6
emilmont	60:3d0ef94e36ec	452
emilmont	60:3d0ef94e36ec	453	/**
emilmont	60:3d0ef94e36ec	454	* @}
emilmont	60:3d0ef94e36ec	455	/ / end of group CMP_Register_Masks */
emilmont	60:3d0ef94e36ec	456
emilmont	60:3d0ef94e36ec	457
emilmont	60:3d0ef94e36ec	458	/* CMP - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	459	/** Peripheral CMP0 base address */
emilmont	60:3d0ef94e36ec	460	#define CMP0_BASE (0x40073000u)
emilmont	60:3d0ef94e36ec	461	/** Peripheral CMP0 base pointer */
emilmont	60:3d0ef94e36ec	462	#define CMP0 ((CMP_Type *)CMP0_BASE)
emilmont	60:3d0ef94e36ec	463	/** Array initializer of CMP peripheral base pointers */
emilmont	60:3d0ef94e36ec	464	#define CMP_BASES { CMP0 }
emilmont	60:3d0ef94e36ec	465
emilmont	60:3d0ef94e36ec	466	/**
emilmont	60:3d0ef94e36ec	467	* @}
emilmont	60:3d0ef94e36ec	468	/ / end of group CMP_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	469
emilmont	60:3d0ef94e36ec	470
emilmont	60:3d0ef94e36ec	471	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	472	-- DAC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	473	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	474
emilmont	60:3d0ef94e36ec	475	/**
emilmont	60:3d0ef94e36ec	476	* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	477	* @{
emilmont	60:3d0ef94e36ec	478	*/
emilmont	60:3d0ef94e36ec	479
emilmont	60:3d0ef94e36ec	480	/** DAC - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	481	typedef struct {
emilmont	60:3d0ef94e36ec	482	struct { /* offset: 0x0, array step: 0x2 */
emilmont	60:3d0ef94e36ec	483	__IO uint8_t DATL; /*< DAC Data Low Register, array offset: 0x0, array step: 0x2 /
emilmont	60:3d0ef94e36ec	484	__IO uint8_t DATH; /*< DAC Data High Register, array offset: 0x1, array step: 0x2 /
emilmont	60:3d0ef94e36ec	485	} DAT[2];
emilmont	60:3d0ef94e36ec	486	uint8_t RESERVED_0[28];
emilmont	60:3d0ef94e36ec	487	__IO uint8_t SR; /*< DAC Status Register, offset: 0x20 /
emilmont	60:3d0ef94e36ec	488	__IO uint8_t C0; /*< DAC Control Register, offset: 0x21 /
emilmont	60:3d0ef94e36ec	489	__IO uint8_t C1; /*< DAC Control Register 1, offset: 0x22 /
emilmont	60:3d0ef94e36ec	490	__IO uint8_t C2; /*< DAC Control Register 2, offset: 0x23 /
emilmont	60:3d0ef94e36ec	491	} DAC_Type;
emilmont	60:3d0ef94e36ec	492
emilmont	60:3d0ef94e36ec	493	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	494	-- DAC Register Masks
emilmont	60:3d0ef94e36ec	495	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	496
emilmont	60:3d0ef94e36ec	497	/**
emilmont	60:3d0ef94e36ec	498	* @addtogroup DAC_Register_Masks DAC Register Masks
emilmont	60:3d0ef94e36ec	499	* @{
emilmont	60:3d0ef94e36ec	500	*/
emilmont	60:3d0ef94e36ec	501
emilmont	60:3d0ef94e36ec	502	/* DATL Bit Fields */
emilmont	60:3d0ef94e36ec	503	#define DAC_DATL_DATA0_MASK 0xFFu
emilmont	60:3d0ef94e36ec	504	#define DAC_DATL_DATA0_SHIFT 0
emilmont	60:3d0ef94e36ec	505	#define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATL_DATA0_SHIFT))&DAC_DATL_DATA0_MASK)
emilmont	60:3d0ef94e36ec	506	/* DATH Bit Fields */
emilmont	60:3d0ef94e36ec	507	#define DAC_DATH_DATA1_MASK 0xFu
emilmont	60:3d0ef94e36ec	508	#define DAC_DATH_DATA1_SHIFT 0
emilmont	60:3d0ef94e36ec	509	#define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x))<<DAC_DATH_DATA1_SHIFT))&DAC_DATH_DATA1_MASK)
emilmont	60:3d0ef94e36ec	510	/* SR Bit Fields */
emilmont	60:3d0ef94e36ec	511	#define DAC_SR_DACBFRPBF_MASK 0x1u
emilmont	60:3d0ef94e36ec	512	#define DAC_SR_DACBFRPBF_SHIFT 0
emilmont	60:3d0ef94e36ec	513	#define DAC_SR_DACBFRPTF_MASK 0x2u
emilmont	60:3d0ef94e36ec	514	#define DAC_SR_DACBFRPTF_SHIFT 1
emilmont	60:3d0ef94e36ec	515	/* C0 Bit Fields */
emilmont	60:3d0ef94e36ec	516	#define DAC_C0_DACBBIEN_MASK 0x1u
emilmont	60:3d0ef94e36ec	517	#define DAC_C0_DACBBIEN_SHIFT 0
emilmont	60:3d0ef94e36ec	518	#define DAC_C0_DACBTIEN_MASK 0x2u
emilmont	60:3d0ef94e36ec	519	#define DAC_C0_DACBTIEN_SHIFT 1
emilmont	60:3d0ef94e36ec	520	#define DAC_C0_LPEN_MASK 0x8u
emilmont	60:3d0ef94e36ec	521	#define DAC_C0_LPEN_SHIFT 3
emilmont	60:3d0ef94e36ec	522	#define DAC_C0_DACSWTRG_MASK 0x10u
emilmont	60:3d0ef94e36ec	523	#define DAC_C0_DACSWTRG_SHIFT 4
emilmont	60:3d0ef94e36ec	524	#define DAC_C0_DACTRGSEL_MASK 0x20u
emilmont	60:3d0ef94e36ec	525	#define DAC_C0_DACTRGSEL_SHIFT 5
emilmont	60:3d0ef94e36ec	526	#define DAC_C0_DACRFS_MASK 0x40u
emilmont	60:3d0ef94e36ec	527	#define DAC_C0_DACRFS_SHIFT 6
emilmont	60:3d0ef94e36ec	528	#define DAC_C0_DACEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	529	#define DAC_C0_DACEN_SHIFT 7
emilmont	60:3d0ef94e36ec	530	/* C1 Bit Fields */
emilmont	60:3d0ef94e36ec	531	#define DAC_C1_DACBFEN_MASK 0x1u
emilmont	60:3d0ef94e36ec	532	#define DAC_C1_DACBFEN_SHIFT 0
emilmont	60:3d0ef94e36ec	533	#define DAC_C1_DACBFMD_MASK 0x4u
emilmont	60:3d0ef94e36ec	534	#define DAC_C1_DACBFMD_SHIFT 2
emilmont	60:3d0ef94e36ec	535	#define DAC_C1_DMAEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	536	#define DAC_C1_DMAEN_SHIFT 7
emilmont	60:3d0ef94e36ec	537	/* C2 Bit Fields */
emilmont	60:3d0ef94e36ec	538	#define DAC_C2_DACBFUP_MASK 0x1u
emilmont	60:3d0ef94e36ec	539	#define DAC_C2_DACBFUP_SHIFT 0
emilmont	60:3d0ef94e36ec	540	#define DAC_C2_DACBFRP_MASK 0x10u
emilmont	60:3d0ef94e36ec	541	#define DAC_C2_DACBFRP_SHIFT 4
emilmont	60:3d0ef94e36ec	542
emilmont	60:3d0ef94e36ec	543	/**
emilmont	60:3d0ef94e36ec	544	* @}
emilmont	60:3d0ef94e36ec	545	/ / end of group DAC_Register_Masks */
emilmont	60:3d0ef94e36ec	546
emilmont	60:3d0ef94e36ec	547
emilmont	60:3d0ef94e36ec	548	/* DAC - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	549	/** Peripheral DAC0 base address */
emilmont	60:3d0ef94e36ec	550	#define DAC0_BASE (0x4003F000u)
emilmont	60:3d0ef94e36ec	551	/** Peripheral DAC0 base pointer */
emilmont	60:3d0ef94e36ec	552	#define DAC0 ((DAC_Type *)DAC0_BASE)
emilmont	60:3d0ef94e36ec	553	/** Array initializer of DAC peripheral base pointers */
emilmont	60:3d0ef94e36ec	554	#define DAC_BASES { DAC0 }
emilmont	60:3d0ef94e36ec	555
emilmont	60:3d0ef94e36ec	556	/**
emilmont	60:3d0ef94e36ec	557	* @}
emilmont	60:3d0ef94e36ec	558	/ / end of group DAC_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	559
emilmont	60:3d0ef94e36ec	560
emilmont	60:3d0ef94e36ec	561	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	562	-- DMA Peripheral Access Layer
emilmont	60:3d0ef94e36ec	563	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	564
emilmont	60:3d0ef94e36ec	565	/**
emilmont	60:3d0ef94e36ec	566	* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
emilmont	60:3d0ef94e36ec	567	* @{
emilmont	60:3d0ef94e36ec	568	*/
emilmont	60:3d0ef94e36ec	569
emilmont	60:3d0ef94e36ec	570	/** DMA - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	571	typedef struct {
emilmont	60:3d0ef94e36ec	572	union { /* offset: 0x0 */
emilmont	60:3d0ef94e36ec	573	__IO uint8_t REQC_ARR[4]; /*< DMA_REQC0 register...DMA_REQC3 register., array offset: 0x0, array step: 0x1 /
emilmont	60:3d0ef94e36ec	574	};
emilmont	60:3d0ef94e36ec	575	uint8_t RESERVED_0[252];
emilmont	60:3d0ef94e36ec	576	struct { /* offset: 0x100, array step: 0x10 */
emilmont	60:3d0ef94e36ec	577	__IO uint32_t SAR; /*< Source Address Register, array offset: 0x100, array step: 0x10 /
emilmont	60:3d0ef94e36ec	578	__IO uint32_t DAR; /*< Destination Address Register, array offset: 0x104, array step: 0x10 /
emilmont	60:3d0ef94e36ec	579	union { /* offset: 0x108, array step: 0x10 */
emilmont	60:3d0ef94e36ec	580	__IO uint32_t DSR_BCR; /*< DMA Status Register / Byte Count Register, array offset: 0x108, array step: 0x10 /
emilmont	60:3d0ef94e36ec	581	struct { /* offset: 0x108, array step: 0x10 */
emilmont	60:3d0ef94e36ec	582	uint8_t RESERVED_0[3];
emilmont	60:3d0ef94e36ec	583	__IO uint8_t DSR; /*< DMA_DSR0 register...DMA_DSR3 register., array offset: 0x10B, array step: 0x10 /
emilmont	60:3d0ef94e36ec	584	} DMA_DSR_ACCESS8BIT;
emilmont	60:3d0ef94e36ec	585	};
emilmont	60:3d0ef94e36ec	586	__IO uint32_t DCR; /*< DMA Control Register, array offset: 0x10C, array step: 0x10 /
emilmont	60:3d0ef94e36ec	587	} DMA[4];
emilmont	60:3d0ef94e36ec	588	} DMA_Type;
emilmont	60:3d0ef94e36ec	589
emilmont	60:3d0ef94e36ec	590	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	591	-- DMA Register Masks
emilmont	60:3d0ef94e36ec	592	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	593
emilmont	60:3d0ef94e36ec	594	/**
emilmont	60:3d0ef94e36ec	595	* @addtogroup DMA_Register_Masks DMA Register Masks
emilmont	60:3d0ef94e36ec	596	* @{
emilmont	60:3d0ef94e36ec	597	*/
emilmont	60:3d0ef94e36ec	598
emilmont	60:3d0ef94e36ec	599	/* REQC_ARR Bit Fields */
emilmont	60:3d0ef94e36ec	600	#define DMA_REQC_ARR_DMAC_MASK 0xFu
emilmont	60:3d0ef94e36ec	601	#define DMA_REQC_ARR_DMAC_SHIFT 0
emilmont	60:3d0ef94e36ec	602	#define DMA_REQC_ARR_DMAC(x) (((uint8_t)(((uint8_t)(x))<<DMA_REQC_ARR_DMAC_SHIFT))&DMA_REQC_ARR_DMAC_MASK)
emilmont	60:3d0ef94e36ec	603	#define DMA_REQC_ARR_CFSM_MASK 0x80u
emilmont	60:3d0ef94e36ec	604	#define DMA_REQC_ARR_CFSM_SHIFT 7
emilmont	60:3d0ef94e36ec	605	/* SAR Bit Fields */
emilmont	60:3d0ef94e36ec	606	#define DMA_SAR_SAR_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	607	#define DMA_SAR_SAR_SHIFT 0
emilmont	60:3d0ef94e36ec	608	#define DMA_SAR_SAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_SAR_SAR_SHIFT))&DMA_SAR_SAR_MASK)
emilmont	60:3d0ef94e36ec	609	/* DAR Bit Fields */
emilmont	60:3d0ef94e36ec	610	#define DMA_DAR_DAR_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	611	#define DMA_DAR_DAR_SHIFT 0
emilmont	60:3d0ef94e36ec	612	#define DMA_DAR_DAR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DAR_DAR_SHIFT))&DMA_DAR_DAR_MASK)
emilmont	60:3d0ef94e36ec	613	/* DSR_BCR Bit Fields */
emilmont	60:3d0ef94e36ec	614	#define DMA_DSR_BCR_BCR_MASK 0xFFFFFFu
emilmont	60:3d0ef94e36ec	615	#define DMA_DSR_BCR_BCR_SHIFT 0
emilmont	60:3d0ef94e36ec	616	#define DMA_DSR_BCR_BCR(x) (((uint32_t)(((uint32_t)(x))<<DMA_DSR_BCR_BCR_SHIFT))&DMA_DSR_BCR_BCR_MASK)
emilmont	60:3d0ef94e36ec	617	#define DMA_DSR_BCR_DONE_MASK 0x1000000u
emilmont	60:3d0ef94e36ec	618	#define DMA_DSR_BCR_DONE_SHIFT 24
emilmont	60:3d0ef94e36ec	619	#define DMA_DSR_BCR_BSY_MASK 0x2000000u
emilmont	60:3d0ef94e36ec	620	#define DMA_DSR_BCR_BSY_SHIFT 25
emilmont	60:3d0ef94e36ec	621	#define DMA_DSR_BCR_REQ_MASK 0x4000000u
emilmont	60:3d0ef94e36ec	622	#define DMA_DSR_BCR_REQ_SHIFT 26
emilmont	60:3d0ef94e36ec	623	#define DMA_DSR_BCR_BED_MASK 0x10000000u
emilmont	60:3d0ef94e36ec	624	#define DMA_DSR_BCR_BED_SHIFT 28
emilmont	60:3d0ef94e36ec	625	#define DMA_DSR_BCR_BES_MASK 0x20000000u
emilmont	60:3d0ef94e36ec	626	#define DMA_DSR_BCR_BES_SHIFT 29
emilmont	60:3d0ef94e36ec	627	#define DMA_DSR_BCR_CE_MASK 0x40000000u
emilmont	60:3d0ef94e36ec	628	#define DMA_DSR_BCR_CE_SHIFT 30
emilmont	60:3d0ef94e36ec	629	/* DCR Bit Fields */
emilmont	60:3d0ef94e36ec	630	#define DMA_DCR_LCH2_MASK 0x3u
emilmont	60:3d0ef94e36ec	631	#define DMA_DCR_LCH2_SHIFT 0
emilmont	60:3d0ef94e36ec	632	#define DMA_DCR_LCH2(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH2_SHIFT))&DMA_DCR_LCH2_MASK)
emilmont	60:3d0ef94e36ec	633	#define DMA_DCR_LCH1_MASK 0xCu
emilmont	60:3d0ef94e36ec	634	#define DMA_DCR_LCH1_SHIFT 2
emilmont	60:3d0ef94e36ec	635	#define DMA_DCR_LCH1(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LCH1_SHIFT))&DMA_DCR_LCH1_MASK)
emilmont	60:3d0ef94e36ec	636	#define DMA_DCR_LINKCC_MASK 0x30u
emilmont	60:3d0ef94e36ec	637	#define DMA_DCR_LINKCC_SHIFT 4
emilmont	60:3d0ef94e36ec	638	#define DMA_DCR_LINKCC(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_LINKCC_SHIFT))&DMA_DCR_LINKCC_MASK)
emilmont	60:3d0ef94e36ec	639	#define DMA_DCR_D_REQ_MASK 0x80u
emilmont	60:3d0ef94e36ec	640	#define DMA_DCR_D_REQ_SHIFT 7
emilmont	60:3d0ef94e36ec	641	#define DMA_DCR_DMOD_MASK 0xF00u
emilmont	60:3d0ef94e36ec	642	#define DMA_DCR_DMOD_SHIFT 8
emilmont	60:3d0ef94e36ec	643	#define DMA_DCR_DMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DMOD_SHIFT))&DMA_DCR_DMOD_MASK)
emilmont	60:3d0ef94e36ec	644	#define DMA_DCR_SMOD_MASK 0xF000u
emilmont	60:3d0ef94e36ec	645	#define DMA_DCR_SMOD_SHIFT 12
emilmont	60:3d0ef94e36ec	646	#define DMA_DCR_SMOD(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SMOD_SHIFT))&DMA_DCR_SMOD_MASK)
emilmont	60:3d0ef94e36ec	647	#define DMA_DCR_START_MASK 0x10000u
emilmont	60:3d0ef94e36ec	648	#define DMA_DCR_START_SHIFT 16
emilmont	60:3d0ef94e36ec	649	#define DMA_DCR_DSIZE_MASK 0x60000u
emilmont	60:3d0ef94e36ec	650	#define DMA_DCR_DSIZE_SHIFT 17
emilmont	60:3d0ef94e36ec	651	#define DMA_DCR_DSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_DSIZE_SHIFT))&DMA_DCR_DSIZE_MASK)
emilmont	60:3d0ef94e36ec	652	#define DMA_DCR_DINC_MASK 0x80000u
emilmont	60:3d0ef94e36ec	653	#define DMA_DCR_DINC_SHIFT 19
emilmont	60:3d0ef94e36ec	654	#define DMA_DCR_SSIZE_MASK 0x300000u
emilmont	60:3d0ef94e36ec	655	#define DMA_DCR_SSIZE_SHIFT 20
emilmont	60:3d0ef94e36ec	656	#define DMA_DCR_SSIZE(x) (((uint32_t)(((uint32_t)(x))<<DMA_DCR_SSIZE_SHIFT))&DMA_DCR_SSIZE_MASK)
emilmont	60:3d0ef94e36ec	657	#define DMA_DCR_SINC_MASK 0x400000u
emilmont	60:3d0ef94e36ec	658	#define DMA_DCR_SINC_SHIFT 22
emilmont	60:3d0ef94e36ec	659	#define DMA_DCR_EADREQ_MASK 0x800000u
emilmont	60:3d0ef94e36ec	660	#define DMA_DCR_EADREQ_SHIFT 23
emilmont	60:3d0ef94e36ec	661	#define DMA_DCR_AA_MASK 0x10000000u
emilmont	60:3d0ef94e36ec	662	#define DMA_DCR_AA_SHIFT 28
emilmont	60:3d0ef94e36ec	663	#define DMA_DCR_CS_MASK 0x20000000u
emilmont	60:3d0ef94e36ec	664	#define DMA_DCR_CS_SHIFT 29
emilmont	60:3d0ef94e36ec	665	#define DMA_DCR_ERQ_MASK 0x40000000u
emilmont	60:3d0ef94e36ec	666	#define DMA_DCR_ERQ_SHIFT 30
emilmont	60:3d0ef94e36ec	667	#define DMA_DCR_EINT_MASK 0x80000000u
emilmont	60:3d0ef94e36ec	668	#define DMA_DCR_EINT_SHIFT 31
emilmont	60:3d0ef94e36ec	669
emilmont	60:3d0ef94e36ec	670	/**
emilmont	60:3d0ef94e36ec	671	* @}
emilmont	60:3d0ef94e36ec	672	/ / end of group DMA_Register_Masks */
emilmont	60:3d0ef94e36ec	673
emilmont	60:3d0ef94e36ec	674
emilmont	60:3d0ef94e36ec	675	/* DMA - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	676	/** Peripheral DMA base address */
emilmont	60:3d0ef94e36ec	677	#define DMA_BASE (0x40008000u)
emilmont	60:3d0ef94e36ec	678	/** Peripheral DMA base pointer */
emilmont	60:3d0ef94e36ec	679	#define DMA0 ((DMA_Type *)DMA_BASE)
emilmont	60:3d0ef94e36ec	680	/** Array initializer of DMA peripheral base pointers */
emilmont	60:3d0ef94e36ec	681	#define DMA_BASES { DMA0 }
emilmont	60:3d0ef94e36ec	682
emilmont	60:3d0ef94e36ec	683	/**
emilmont	60:3d0ef94e36ec	684	* @}
emilmont	60:3d0ef94e36ec	685	/ / end of group DMA_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	686
emilmont	60:3d0ef94e36ec	687
emilmont	60:3d0ef94e36ec	688	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	689	-- DMAMUX Peripheral Access Layer
emilmont	60:3d0ef94e36ec	690	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	691
emilmont	60:3d0ef94e36ec	692	/**
emilmont	60:3d0ef94e36ec	693	* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
emilmont	60:3d0ef94e36ec	694	* @{
emilmont	60:3d0ef94e36ec	695	*/
emilmont	60:3d0ef94e36ec	696
emilmont	60:3d0ef94e36ec	697	/** DMAMUX - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	698	typedef struct {
emilmont	60:3d0ef94e36ec	699	__IO uint8_t CHCFG[4]; /*< Channel Configuration register, array offset: 0x0, array step: 0x1 /
emilmont	60:3d0ef94e36ec	700	} DMAMUX_Type;
emilmont	60:3d0ef94e36ec	701
emilmont	60:3d0ef94e36ec	702	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	703	-- DMAMUX Register Masks
emilmont	60:3d0ef94e36ec	704	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	705
emilmont	60:3d0ef94e36ec	706	/**
emilmont	60:3d0ef94e36ec	707	* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
emilmont	60:3d0ef94e36ec	708	* @{
emilmont	60:3d0ef94e36ec	709	*/
emilmont	60:3d0ef94e36ec	710
emilmont	60:3d0ef94e36ec	711	/* CHCFG Bit Fields */
emilmont	60:3d0ef94e36ec	712	#define DMAMUX_CHCFG_SOURCE_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	713	#define DMAMUX_CHCFG_SOURCE_SHIFT 0
emilmont	60:3d0ef94e36ec	714	#define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x))<<DMAMUX_CHCFG_SOURCE_SHIFT))&DMAMUX_CHCFG_SOURCE_MASK)
emilmont	60:3d0ef94e36ec	715	#define DMAMUX_CHCFG_TRIG_MASK 0x40u
emilmont	60:3d0ef94e36ec	716	#define DMAMUX_CHCFG_TRIG_SHIFT 6
emilmont	60:3d0ef94e36ec	717	#define DMAMUX_CHCFG_ENBL_MASK 0x80u
emilmont	60:3d0ef94e36ec	718	#define DMAMUX_CHCFG_ENBL_SHIFT 7
emilmont	60:3d0ef94e36ec	719
emilmont	60:3d0ef94e36ec	720	/**
emilmont	60:3d0ef94e36ec	721	* @}
emilmont	60:3d0ef94e36ec	722	/ / end of group DMAMUX_Register_Masks */
emilmont	60:3d0ef94e36ec	723
emilmont	60:3d0ef94e36ec	724
emilmont	60:3d0ef94e36ec	725	/* DMAMUX - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	726	/** Peripheral DMAMUX0 base address */
emilmont	60:3d0ef94e36ec	727	#define DMAMUX0_BASE (0x40021000u)
emilmont	60:3d0ef94e36ec	728	/** Peripheral DMAMUX0 base pointer */
emilmont	60:3d0ef94e36ec	729	#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
emilmont	60:3d0ef94e36ec	730	/** Array initializer of DMAMUX peripheral base pointers */
emilmont	60:3d0ef94e36ec	731	#define DMAMUX_BASES { DMAMUX0 }
emilmont	60:3d0ef94e36ec	732
emilmont	60:3d0ef94e36ec	733	/**
emilmont	60:3d0ef94e36ec	734	* @}
emilmont	60:3d0ef94e36ec	735	/ / end of group DMAMUX_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	736
emilmont	60:3d0ef94e36ec	737
emilmont	60:3d0ef94e36ec	738	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	739	-- FGPIO Peripheral Access Layer
emilmont	60:3d0ef94e36ec	740	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	741
emilmont	60:3d0ef94e36ec	742	/**
emilmont	60:3d0ef94e36ec	743	* @addtogroup FGPIO_Peripheral_Access_Layer FGPIO Peripheral Access Layer
emilmont	60:3d0ef94e36ec	744	* @{
emilmont	60:3d0ef94e36ec	745	*/
emilmont	60:3d0ef94e36ec	746
emilmont	60:3d0ef94e36ec	747	/** FGPIO - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	748	typedef struct {
emilmont	60:3d0ef94e36ec	749	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	750	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	751	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	752	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
emilmont	60:3d0ef94e36ec	753	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
emilmont	60:3d0ef94e36ec	754	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
emilmont	60:3d0ef94e36ec	755	} FGPIO_Type;
emilmont	60:3d0ef94e36ec	756
emilmont	60:3d0ef94e36ec	757	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	758	-- FGPIO Register Masks
emilmont	60:3d0ef94e36ec	759	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	760
emilmont	60:3d0ef94e36ec	761	/**
emilmont	60:3d0ef94e36ec	762	* @addtogroup FGPIO_Register_Masks FGPIO Register Masks
emilmont	60:3d0ef94e36ec	763	* @{
emilmont	60:3d0ef94e36ec	764	*/
emilmont	60:3d0ef94e36ec	765
emilmont	60:3d0ef94e36ec	766	/* PDOR Bit Fields */
emilmont	60:3d0ef94e36ec	767	#define FGPIO_PDOR_PDO_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	768	#define FGPIO_PDOR_PDO_SHIFT 0
emilmont	60:3d0ef94e36ec	769	#define FGPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDOR_PDO_SHIFT))&FGPIO_PDOR_PDO_MASK)
emilmont	60:3d0ef94e36ec	770	/* PSOR Bit Fields */
emilmont	60:3d0ef94e36ec	771	#define FGPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	772	#define FGPIO_PSOR_PTSO_SHIFT 0
emilmont	60:3d0ef94e36ec	773	#define FGPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PSOR_PTSO_SHIFT))&FGPIO_PSOR_PTSO_MASK)
emilmont	60:3d0ef94e36ec	774	/* PCOR Bit Fields */
emilmont	60:3d0ef94e36ec	775	#define FGPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	776	#define FGPIO_PCOR_PTCO_SHIFT 0
emilmont	60:3d0ef94e36ec	777	#define FGPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PCOR_PTCO_SHIFT))&FGPIO_PCOR_PTCO_MASK)
emilmont	60:3d0ef94e36ec	778	/* PTOR Bit Fields */
emilmont	60:3d0ef94e36ec	779	#define FGPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	780	#define FGPIO_PTOR_PTTO_SHIFT 0
emilmont	60:3d0ef94e36ec	781	#define FGPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PTOR_PTTO_SHIFT))&FGPIO_PTOR_PTTO_MASK)
emilmont	60:3d0ef94e36ec	782	/* PDIR Bit Fields */
emilmont	60:3d0ef94e36ec	783	#define FGPIO_PDIR_PDI_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	784	#define FGPIO_PDIR_PDI_SHIFT 0
emilmont	60:3d0ef94e36ec	785	#define FGPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDIR_PDI_SHIFT))&FGPIO_PDIR_PDI_MASK)
emilmont	60:3d0ef94e36ec	786	/* PDDR Bit Fields */
emilmont	60:3d0ef94e36ec	787	#define FGPIO_PDDR_PDD_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	788	#define FGPIO_PDDR_PDD_SHIFT 0
emilmont	60:3d0ef94e36ec	789	#define FGPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<FGPIO_PDDR_PDD_SHIFT))&FGPIO_PDDR_PDD_MASK)
emilmont	60:3d0ef94e36ec	790
emilmont	60:3d0ef94e36ec	791	/**
emilmont	60:3d0ef94e36ec	792	* @}
emilmont	60:3d0ef94e36ec	793	/ / end of group FGPIO_Register_Masks */
emilmont	60:3d0ef94e36ec	794
emilmont	60:3d0ef94e36ec	795
emilmont	60:3d0ef94e36ec	796	/* FGPIO - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	797	/** Peripheral FPTA base address */
emilmont	60:3d0ef94e36ec	798	#define FPTA_BASE (0xF80FF000u)
emilmont	60:3d0ef94e36ec	799	/** Peripheral FPTA base pointer */
emilmont	60:3d0ef94e36ec	800	#define FPTA ((FGPIO_Type *)FPTA_BASE)
emilmont	60:3d0ef94e36ec	801	/** Peripheral FPTB base address */
emilmont	60:3d0ef94e36ec	802	#define FPTB_BASE (0xF80FF040u)
emilmont	60:3d0ef94e36ec	803	/** Peripheral FPTB base pointer */
emilmont	60:3d0ef94e36ec	804	#define FPTB ((FGPIO_Type *)FPTB_BASE)
emilmont	60:3d0ef94e36ec	805	/** Peripheral FPTC base address */
emilmont	60:3d0ef94e36ec	806	#define FPTC_BASE (0xF80FF080u)
emilmont	60:3d0ef94e36ec	807	/** Peripheral FPTC base pointer */
emilmont	60:3d0ef94e36ec	808	#define FPTC ((FGPIO_Type *)FPTC_BASE)
emilmont	60:3d0ef94e36ec	809	/** Peripheral FPTD base address */
emilmont	60:3d0ef94e36ec	810	#define FPTD_BASE (0xF80FF0C0u)
emilmont	60:3d0ef94e36ec	811	/** Peripheral FPTD base pointer */
emilmont	60:3d0ef94e36ec	812	#define FPTD ((FGPIO_Type *)FPTD_BASE)
emilmont	60:3d0ef94e36ec	813	/** Peripheral FPTE base address */
emilmont	60:3d0ef94e36ec	814	#define FPTE_BASE (0xF80FF100u)
emilmont	60:3d0ef94e36ec	815	/** Peripheral FPTE base pointer */
emilmont	60:3d0ef94e36ec	816	#define FPTE ((FGPIO_Type *)FPTE_BASE)
emilmont	60:3d0ef94e36ec	817	/** Array initializer of FGPIO peripheral base pointers */
emilmont	60:3d0ef94e36ec	818	#define FGPIO_BASES { FPTA, FPTB, FPTC, FPTD, FPTE }
emilmont	60:3d0ef94e36ec	819
emilmont	60:3d0ef94e36ec	820	/**
emilmont	60:3d0ef94e36ec	821	* @}
emilmont	60:3d0ef94e36ec	822	/ / end of group FGPIO_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	823
emilmont	60:3d0ef94e36ec	824
emilmont	60:3d0ef94e36ec	825	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	826	-- FTFA Peripheral Access Layer
emilmont	60:3d0ef94e36ec	827	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	828
emilmont	60:3d0ef94e36ec	829	/**
emilmont	60:3d0ef94e36ec	830	* @addtogroup FTFA_Peripheral_Access_Layer FTFA Peripheral Access Layer
emilmont	60:3d0ef94e36ec	831	* @{
emilmont	60:3d0ef94e36ec	832	*/
emilmont	60:3d0ef94e36ec	833
emilmont	60:3d0ef94e36ec	834	/** FTFA - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	835	typedef struct {
emilmont	60:3d0ef94e36ec	836	__IO uint8_t FSTAT; /*< Flash Status Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	837	__IO uint8_t FCNFG; /*< Flash Configuration Register, offset: 0x1 /
emilmont	60:3d0ef94e36ec	838	__I uint8_t FSEC; /*< Flash Security Register, offset: 0x2 /
emilmont	60:3d0ef94e36ec	839	__I uint8_t FOPT; /*< Flash Option Register, offset: 0x3 /
emilmont	60:3d0ef94e36ec	840	__IO uint8_t FCCOB3; /*< Flash Common Command Object Registers, offset: 0x4 /
emilmont	60:3d0ef94e36ec	841	__IO uint8_t FCCOB2; /*< Flash Common Command Object Registers, offset: 0x5 /
emilmont	60:3d0ef94e36ec	842	__IO uint8_t FCCOB1; /*< Flash Common Command Object Registers, offset: 0x6 /
emilmont	60:3d0ef94e36ec	843	__IO uint8_t FCCOB0; /*< Flash Common Command Object Registers, offset: 0x7 /
emilmont	60:3d0ef94e36ec	844	__IO uint8_t FCCOB7; /*< Flash Common Command Object Registers, offset: 0x8 /
emilmont	60:3d0ef94e36ec	845	__IO uint8_t FCCOB6; /*< Flash Common Command Object Registers, offset: 0x9 /
emilmont	60:3d0ef94e36ec	846	__IO uint8_t FCCOB5; /*< Flash Common Command Object Registers, offset: 0xA /
emilmont	60:3d0ef94e36ec	847	__IO uint8_t FCCOB4; /*< Flash Common Command Object Registers, offset: 0xB /
emilmont	60:3d0ef94e36ec	848	__IO uint8_t FCCOBB; /*< Flash Common Command Object Registers, offset: 0xC /
emilmont	60:3d0ef94e36ec	849	__IO uint8_t FCCOBA; /*< Flash Common Command Object Registers, offset: 0xD /
emilmont	60:3d0ef94e36ec	850	__IO uint8_t FCCOB9; /*< Flash Common Command Object Registers, offset: 0xE /
emilmont	60:3d0ef94e36ec	851	__IO uint8_t FCCOB8; /*< Flash Common Command Object Registers, offset: 0xF /
emilmont	60:3d0ef94e36ec	852	__IO uint8_t FPROT3; /*< Program Flash Protection Registers, offset: 0x10 /
emilmont	60:3d0ef94e36ec	853	__IO uint8_t FPROT2; /*< Program Flash Protection Registers, offset: 0x11 /
emilmont	60:3d0ef94e36ec	854	__IO uint8_t FPROT1; /*< Program Flash Protection Registers, offset: 0x12 /
emilmont	60:3d0ef94e36ec	855	__IO uint8_t FPROT0; /*< Program Flash Protection Registers, offset: 0x13 /
emilmont	60:3d0ef94e36ec	856	} FTFA_Type;
emilmont	60:3d0ef94e36ec	857
emilmont	60:3d0ef94e36ec	858	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	859	-- FTFA Register Masks
emilmont	60:3d0ef94e36ec	860	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	861
emilmont	60:3d0ef94e36ec	862	/**
emilmont	60:3d0ef94e36ec	863	* @addtogroup FTFA_Register_Masks FTFA Register Masks
emilmont	60:3d0ef94e36ec	864	* @{
emilmont	60:3d0ef94e36ec	865	*/
emilmont	60:3d0ef94e36ec	866
emilmont	60:3d0ef94e36ec	867	/* FSTAT Bit Fields */
emilmont	60:3d0ef94e36ec	868	#define FTFA_FSTAT_MGSTAT0_MASK 0x1u
emilmont	60:3d0ef94e36ec	869	#define FTFA_FSTAT_MGSTAT0_SHIFT 0
emilmont	60:3d0ef94e36ec	870	#define FTFA_FSTAT_FPVIOL_MASK 0x10u
emilmont	60:3d0ef94e36ec	871	#define FTFA_FSTAT_FPVIOL_SHIFT 4
emilmont	60:3d0ef94e36ec	872	#define FTFA_FSTAT_ACCERR_MASK 0x20u
emilmont	60:3d0ef94e36ec	873	#define FTFA_FSTAT_ACCERR_SHIFT 5
emilmont	60:3d0ef94e36ec	874	#define FTFA_FSTAT_RDCOLERR_MASK 0x40u
emilmont	60:3d0ef94e36ec	875	#define FTFA_FSTAT_RDCOLERR_SHIFT 6
emilmont	60:3d0ef94e36ec	876	#define FTFA_FSTAT_CCIF_MASK 0x80u
emilmont	60:3d0ef94e36ec	877	#define FTFA_FSTAT_CCIF_SHIFT 7
emilmont	60:3d0ef94e36ec	878	/* FCNFG Bit Fields */
emilmont	60:3d0ef94e36ec	879	#define FTFA_FCNFG_ERSSUSP_MASK 0x10u
emilmont	60:3d0ef94e36ec	880	#define FTFA_FCNFG_ERSSUSP_SHIFT 4
emilmont	60:3d0ef94e36ec	881	#define FTFA_FCNFG_ERSAREQ_MASK 0x20u
emilmont	60:3d0ef94e36ec	882	#define FTFA_FCNFG_ERSAREQ_SHIFT 5
emilmont	60:3d0ef94e36ec	883	#define FTFA_FCNFG_RDCOLLIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	884	#define FTFA_FCNFG_RDCOLLIE_SHIFT 6
emilmont	60:3d0ef94e36ec	885	#define FTFA_FCNFG_CCIE_MASK 0x80u
emilmont	60:3d0ef94e36ec	886	#define FTFA_FCNFG_CCIE_SHIFT 7
emilmont	60:3d0ef94e36ec	887	/* FSEC Bit Fields */
emilmont	60:3d0ef94e36ec	888	#define FTFA_FSEC_SEC_MASK 0x3u
emilmont	60:3d0ef94e36ec	889	#define FTFA_FSEC_SEC_SHIFT 0
emilmont	60:3d0ef94e36ec	890	#define FTFA_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_SEC_SHIFT))&FTFA_FSEC_SEC_MASK)
emilmont	60:3d0ef94e36ec	891	#define FTFA_FSEC_FSLACC_MASK 0xCu
emilmont	60:3d0ef94e36ec	892	#define FTFA_FSEC_FSLACC_SHIFT 2
emilmont	60:3d0ef94e36ec	893	#define FTFA_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_FSLACC_SHIFT))&FTFA_FSEC_FSLACC_MASK)
emilmont	60:3d0ef94e36ec	894	#define FTFA_FSEC_MEEN_MASK 0x30u
emilmont	60:3d0ef94e36ec	895	#define FTFA_FSEC_MEEN_SHIFT 4
emilmont	60:3d0ef94e36ec	896	#define FTFA_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_MEEN_SHIFT))&FTFA_FSEC_MEEN_MASK)
emilmont	60:3d0ef94e36ec	897	#define FTFA_FSEC_KEYEN_MASK 0xC0u
emilmont	60:3d0ef94e36ec	898	#define FTFA_FSEC_KEYEN_SHIFT 6
emilmont	60:3d0ef94e36ec	899	#define FTFA_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FSEC_KEYEN_SHIFT))&FTFA_FSEC_KEYEN_MASK)
emilmont	60:3d0ef94e36ec	900	/* FOPT Bit Fields */
emilmont	60:3d0ef94e36ec	901	#define FTFA_FOPT_OPT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	902	#define FTFA_FOPT_OPT_SHIFT 0
emilmont	60:3d0ef94e36ec	903	#define FTFA_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FOPT_OPT_SHIFT))&FTFA_FOPT_OPT_MASK)
emilmont	60:3d0ef94e36ec	904	/* FCCOB3 Bit Fields */
emilmont	60:3d0ef94e36ec	905	#define FTFA_FCCOB3_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	906	#define FTFA_FCCOB3_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	907	#define FTFA_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB3_CCOBn_SHIFT))&FTFA_FCCOB3_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	908	/* FCCOB2 Bit Fields */
emilmont	60:3d0ef94e36ec	909	#define FTFA_FCCOB2_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	910	#define FTFA_FCCOB2_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	911	#define FTFA_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB2_CCOBn_SHIFT))&FTFA_FCCOB2_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	912	/* FCCOB1 Bit Fields */
emilmont	60:3d0ef94e36ec	913	#define FTFA_FCCOB1_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	914	#define FTFA_FCCOB1_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	915	#define FTFA_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB1_CCOBn_SHIFT))&FTFA_FCCOB1_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	916	/* FCCOB0 Bit Fields */
emilmont	60:3d0ef94e36ec	917	#define FTFA_FCCOB0_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	918	#define FTFA_FCCOB0_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	919	#define FTFA_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB0_CCOBn_SHIFT))&FTFA_FCCOB0_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	920	/* FCCOB7 Bit Fields */
emilmont	60:3d0ef94e36ec	921	#define FTFA_FCCOB7_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	922	#define FTFA_FCCOB7_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	923	#define FTFA_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB7_CCOBn_SHIFT))&FTFA_FCCOB7_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	924	/* FCCOB6 Bit Fields */
emilmont	60:3d0ef94e36ec	925	#define FTFA_FCCOB6_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	926	#define FTFA_FCCOB6_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	927	#define FTFA_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB6_CCOBn_SHIFT))&FTFA_FCCOB6_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	928	/* FCCOB5 Bit Fields */
emilmont	60:3d0ef94e36ec	929	#define FTFA_FCCOB5_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	930	#define FTFA_FCCOB5_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	931	#define FTFA_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB5_CCOBn_SHIFT))&FTFA_FCCOB5_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	932	/* FCCOB4 Bit Fields */
emilmont	60:3d0ef94e36ec	933	#define FTFA_FCCOB4_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	934	#define FTFA_FCCOB4_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	935	#define FTFA_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB4_CCOBn_SHIFT))&FTFA_FCCOB4_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	936	/* FCCOBB Bit Fields */
emilmont	60:3d0ef94e36ec	937	#define FTFA_FCCOBB_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	938	#define FTFA_FCCOBB_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	939	#define FTFA_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBB_CCOBn_SHIFT))&FTFA_FCCOBB_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	940	/* FCCOBA Bit Fields */
emilmont	60:3d0ef94e36ec	941	#define FTFA_FCCOBA_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	942	#define FTFA_FCCOBA_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	943	#define FTFA_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOBA_CCOBn_SHIFT))&FTFA_FCCOBA_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	944	/* FCCOB9 Bit Fields */
emilmont	60:3d0ef94e36ec	945	#define FTFA_FCCOB9_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	946	#define FTFA_FCCOB9_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	947	#define FTFA_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB9_CCOBn_SHIFT))&FTFA_FCCOB9_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	948	/* FCCOB8 Bit Fields */
emilmont	60:3d0ef94e36ec	949	#define FTFA_FCCOB8_CCOBn_MASK 0xFFu
emilmont	60:3d0ef94e36ec	950	#define FTFA_FCCOB8_CCOBn_SHIFT 0
emilmont	60:3d0ef94e36ec	951	#define FTFA_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FCCOB8_CCOBn_SHIFT))&FTFA_FCCOB8_CCOBn_MASK)
emilmont	60:3d0ef94e36ec	952	/* FPROT3 Bit Fields */
emilmont	60:3d0ef94e36ec	953	#define FTFA_FPROT3_PROT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	954	#define FTFA_FPROT3_PROT_SHIFT 0
emilmont	60:3d0ef94e36ec	955	#define FTFA_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT3_PROT_SHIFT))&FTFA_FPROT3_PROT_MASK)
emilmont	60:3d0ef94e36ec	956	/* FPROT2 Bit Fields */
emilmont	60:3d0ef94e36ec	957	#define FTFA_FPROT2_PROT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	958	#define FTFA_FPROT2_PROT_SHIFT 0
emilmont	60:3d0ef94e36ec	959	#define FTFA_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT2_PROT_SHIFT))&FTFA_FPROT2_PROT_MASK)
emilmont	60:3d0ef94e36ec	960	/* FPROT1 Bit Fields */
emilmont	60:3d0ef94e36ec	961	#define FTFA_FPROT1_PROT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	962	#define FTFA_FPROT1_PROT_SHIFT 0
emilmont	60:3d0ef94e36ec	963	#define FTFA_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT1_PROT_SHIFT))&FTFA_FPROT1_PROT_MASK)
emilmont	60:3d0ef94e36ec	964	/* FPROT0 Bit Fields */
emilmont	60:3d0ef94e36ec	965	#define FTFA_FPROT0_PROT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	966	#define FTFA_FPROT0_PROT_SHIFT 0
emilmont	60:3d0ef94e36ec	967	#define FTFA_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<FTFA_FPROT0_PROT_SHIFT))&FTFA_FPROT0_PROT_MASK)
emilmont	60:3d0ef94e36ec	968
emilmont	60:3d0ef94e36ec	969	/**
emilmont	60:3d0ef94e36ec	970	* @}
emilmont	60:3d0ef94e36ec	971	/ / end of group FTFA_Register_Masks */
emilmont	60:3d0ef94e36ec	972
emilmont	60:3d0ef94e36ec	973
emilmont	60:3d0ef94e36ec	974	/* FTFA - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	975	/** Peripheral FTFA base address */
emilmont	60:3d0ef94e36ec	976	#define FTFA_BASE (0x40020000u)
emilmont	60:3d0ef94e36ec	977	/** Peripheral FTFA base pointer */
emilmont	60:3d0ef94e36ec	978	#define FTFA ((FTFA_Type *)FTFA_BASE)
emilmont	60:3d0ef94e36ec	979	/** Array initializer of FTFA peripheral base pointers */
emilmont	60:3d0ef94e36ec	980	#define FTFA_BASES { FTFA }
emilmont	60:3d0ef94e36ec	981
emilmont	60:3d0ef94e36ec	982	/**
emilmont	60:3d0ef94e36ec	983	* @}
emilmont	60:3d0ef94e36ec	984	/ / end of group FTFA_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	985
emilmont	60:3d0ef94e36ec	986
emilmont	60:3d0ef94e36ec	987	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	988	-- GPIO Peripheral Access Layer
emilmont	60:3d0ef94e36ec	989	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	990
emilmont	60:3d0ef94e36ec	991	/**
emilmont	60:3d0ef94e36ec	992	* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
emilmont	60:3d0ef94e36ec	993	* @{
emilmont	60:3d0ef94e36ec	994	*/
emilmont	60:3d0ef94e36ec	995
emilmont	60:3d0ef94e36ec	996	/** GPIO - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	997	typedef struct {
emilmont	60:3d0ef94e36ec	998	__IO uint32_t PDOR; /*< Port Data Output Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	999	__O uint32_t PSOR; /*< Port Set Output Register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	1000	__O uint32_t PCOR; /*< Port Clear Output Register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	1001	__O uint32_t PTOR; /*< Port Toggle Output Register, offset: 0xC /
emilmont	60:3d0ef94e36ec	1002	__I uint32_t PDIR; /*< Port Data Input Register, offset: 0x10 /
emilmont	60:3d0ef94e36ec	1003	__IO uint32_t PDDR; /*< Port Data Direction Register, offset: 0x14 /
emilmont	60:3d0ef94e36ec	1004	} GPIO_Type;
emilmont	60:3d0ef94e36ec	1005
emilmont	60:3d0ef94e36ec	1006	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1007	-- GPIO Register Masks
emilmont	60:3d0ef94e36ec	1008	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1009
emilmont	60:3d0ef94e36ec	1010	/**
emilmont	60:3d0ef94e36ec	1011	* @addtogroup GPIO_Register_Masks GPIO Register Masks
emilmont	60:3d0ef94e36ec	1012	* @{
emilmont	60:3d0ef94e36ec	1013	*/
emilmont	60:3d0ef94e36ec	1014
emilmont	60:3d0ef94e36ec	1015	/* PDOR Bit Fields */
emilmont	60:3d0ef94e36ec	1016	#define GPIO_PDOR_PDO_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1017	#define GPIO_PDOR_PDO_SHIFT 0
emilmont	60:3d0ef94e36ec	1018	#define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDOR_PDO_SHIFT))&GPIO_PDOR_PDO_MASK)
emilmont	60:3d0ef94e36ec	1019	/* PSOR Bit Fields */
emilmont	60:3d0ef94e36ec	1020	#define GPIO_PSOR_PTSO_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1021	#define GPIO_PSOR_PTSO_SHIFT 0
emilmont	60:3d0ef94e36ec	1022	#define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PSOR_PTSO_SHIFT))&GPIO_PSOR_PTSO_MASK)
emilmont	60:3d0ef94e36ec	1023	/* PCOR Bit Fields */
emilmont	60:3d0ef94e36ec	1024	#define GPIO_PCOR_PTCO_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1025	#define GPIO_PCOR_PTCO_SHIFT 0
emilmont	60:3d0ef94e36ec	1026	#define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PCOR_PTCO_SHIFT))&GPIO_PCOR_PTCO_MASK)
emilmont	60:3d0ef94e36ec	1027	/* PTOR Bit Fields */
emilmont	60:3d0ef94e36ec	1028	#define GPIO_PTOR_PTTO_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1029	#define GPIO_PTOR_PTTO_SHIFT 0
emilmont	60:3d0ef94e36ec	1030	#define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PTOR_PTTO_SHIFT))&GPIO_PTOR_PTTO_MASK)
emilmont	60:3d0ef94e36ec	1031	/* PDIR Bit Fields */
emilmont	60:3d0ef94e36ec	1032	#define GPIO_PDIR_PDI_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1033	#define GPIO_PDIR_PDI_SHIFT 0
emilmont	60:3d0ef94e36ec	1034	#define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDIR_PDI_SHIFT))&GPIO_PDIR_PDI_MASK)
emilmont	60:3d0ef94e36ec	1035	/* PDDR Bit Fields */
emilmont	60:3d0ef94e36ec	1036	#define GPIO_PDDR_PDD_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1037	#define GPIO_PDDR_PDD_SHIFT 0
emilmont	60:3d0ef94e36ec	1038	#define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x))<<GPIO_PDDR_PDD_SHIFT))&GPIO_PDDR_PDD_MASK)
emilmont	60:3d0ef94e36ec	1039
emilmont	60:3d0ef94e36ec	1040	/**
emilmont	60:3d0ef94e36ec	1041	* @}
emilmont	60:3d0ef94e36ec	1042	/ / end of group GPIO_Register_Masks */
emilmont	60:3d0ef94e36ec	1043
emilmont	60:3d0ef94e36ec	1044
emilmont	60:3d0ef94e36ec	1045	/* GPIO - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	1046	/** Peripheral PTA base address */
emilmont	60:3d0ef94e36ec	1047	#define PTA_BASE (0x400FF000u)
emilmont	60:3d0ef94e36ec	1048	/** Peripheral PTA base pointer */
emilmont	60:3d0ef94e36ec	1049	#define PTA ((GPIO_Type *)PTA_BASE)
emilmont	60:3d0ef94e36ec	1050	/** Peripheral PTB base address */
emilmont	60:3d0ef94e36ec	1051	#define PTB_BASE (0x400FF040u)
emilmont	60:3d0ef94e36ec	1052	/** Peripheral PTB base pointer */
emilmont	60:3d0ef94e36ec	1053	#define PTB ((GPIO_Type *)PTB_BASE)
emilmont	60:3d0ef94e36ec	1054	/** Peripheral PTC base address */
emilmont	60:3d0ef94e36ec	1055	#define PTC_BASE (0x400FF080u)
emilmont	60:3d0ef94e36ec	1056	/** Peripheral PTC base pointer */
emilmont	60:3d0ef94e36ec	1057	#define PTC ((GPIO_Type *)PTC_BASE)
emilmont	60:3d0ef94e36ec	1058	/** Peripheral PTD base address */
emilmont	60:3d0ef94e36ec	1059	#define PTD_BASE (0x400FF0C0u)
emilmont	60:3d0ef94e36ec	1060	/** Peripheral PTD base pointer */
emilmont	60:3d0ef94e36ec	1061	#define PTD ((GPIO_Type *)PTD_BASE)
emilmont	60:3d0ef94e36ec	1062	/** Peripheral PTE base address */
emilmont	60:3d0ef94e36ec	1063	#define PTE_BASE (0x400FF100u)
emilmont	60:3d0ef94e36ec	1064	/** Peripheral PTE base pointer */
emilmont	60:3d0ef94e36ec	1065	#define PTE ((GPIO_Type *)PTE_BASE)
emilmont	60:3d0ef94e36ec	1066	/** Array initializer of GPIO peripheral base pointers */
emilmont	60:3d0ef94e36ec	1067	#define GPIO_BASES { PTA, PTB, PTC, PTD, PTE }
emilmont	60:3d0ef94e36ec	1068
emilmont	60:3d0ef94e36ec	1069	/**
emilmont	60:3d0ef94e36ec	1070	* @}
emilmont	60:3d0ef94e36ec	1071	/ / end of group GPIO_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	1072
emilmont	60:3d0ef94e36ec	1073
emilmont	60:3d0ef94e36ec	1074	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1075	-- I2C Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1076	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1077
emilmont	60:3d0ef94e36ec	1078	/**
emilmont	60:3d0ef94e36ec	1079	* @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1080	* @{
emilmont	60:3d0ef94e36ec	1081	*/
emilmont	60:3d0ef94e36ec	1082
emilmont	60:3d0ef94e36ec	1083	/** I2C - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	1084	typedef struct {
emilmont	60:3d0ef94e36ec	1085	__IO uint8_t A1; /*< I2C Address Register 1, offset: 0x0 /
emilmont	60:3d0ef94e36ec	1086	__IO uint8_t F; /*< I2C Frequency Divider register, offset: 0x1 /
emilmont	60:3d0ef94e36ec	1087	__IO uint8_t C1; /*< I2C Control Register 1, offset: 0x2 /
emilmont	60:3d0ef94e36ec	1088	__IO uint8_t S; /*< I2C Status register, offset: 0x3 /
emilmont	60:3d0ef94e36ec	1089	__IO uint8_t D; /*< I2C Data I/O register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	1090	__IO uint8_t C2; /*< I2C Control Register 2, offset: 0x5 /
emilmont	60:3d0ef94e36ec	1091	__IO uint8_t FLT; /*< I2C Programmable Input Glitch Filter register, offset: 0x6 /
emilmont	60:3d0ef94e36ec	1092	__IO uint8_t RA; /*< I2C Range Address register, offset: 0x7 /
emilmont	60:3d0ef94e36ec	1093	__IO uint8_t SMB; /*< I2C SMBus Control and Status register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	1094	__IO uint8_t A2; /*< I2C Address Register 2, offset: 0x9 /
emilmont	60:3d0ef94e36ec	1095	__IO uint8_t SLTH; /*< I2C SCL Low Timeout Register High, offset: 0xA /
emilmont	60:3d0ef94e36ec	1096	__IO uint8_t SLTL; /*< I2C SCL Low Timeout Register Low, offset: 0xB /
emilmont	60:3d0ef94e36ec	1097	} I2C_Type;
emilmont	60:3d0ef94e36ec	1098
emilmont	60:3d0ef94e36ec	1099	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1100	-- I2C Register Masks
emilmont	60:3d0ef94e36ec	1101	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1102
emilmont	60:3d0ef94e36ec	1103	/**
emilmont	60:3d0ef94e36ec	1104	* @addtogroup I2C_Register_Masks I2C Register Masks
emilmont	60:3d0ef94e36ec	1105	* @{
emilmont	60:3d0ef94e36ec	1106	*/
emilmont	60:3d0ef94e36ec	1107
emilmont	60:3d0ef94e36ec	1108	/* A1 Bit Fields */
emilmont	60:3d0ef94e36ec	1109	#define I2C_A1_AD_MASK 0xFEu
emilmont	60:3d0ef94e36ec	1110	#define I2C_A1_AD_SHIFT 1
emilmont	60:3d0ef94e36ec	1111	#define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A1_AD_SHIFT))&I2C_A1_AD_MASK)
emilmont	60:3d0ef94e36ec	1112	/* F Bit Fields */
emilmont	60:3d0ef94e36ec	1113	#define I2C_F_ICR_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	1114	#define I2C_F_ICR_SHIFT 0
emilmont	60:3d0ef94e36ec	1115	#define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_ICR_SHIFT))&I2C_F_ICR_MASK)
emilmont	60:3d0ef94e36ec	1116	#define I2C_F_MULT_MASK 0xC0u
emilmont	60:3d0ef94e36ec	1117	#define I2C_F_MULT_SHIFT 6
emilmont	60:3d0ef94e36ec	1118	#define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x))<<I2C_F_MULT_SHIFT))&I2C_F_MULT_MASK)
emilmont	60:3d0ef94e36ec	1119	/* C1 Bit Fields */
emilmont	60:3d0ef94e36ec	1120	#define I2C_C1_DMAEN_MASK 0x1u
emilmont	60:3d0ef94e36ec	1121	#define I2C_C1_DMAEN_SHIFT 0
emilmont	60:3d0ef94e36ec	1122	#define I2C_C1_WUEN_MASK 0x2u
emilmont	60:3d0ef94e36ec	1123	#define I2C_C1_WUEN_SHIFT 1
emilmont	60:3d0ef94e36ec	1124	#define I2C_C1_RSTA_MASK 0x4u
emilmont	60:3d0ef94e36ec	1125	#define I2C_C1_RSTA_SHIFT 2
emilmont	60:3d0ef94e36ec	1126	#define I2C_C1_TXAK_MASK 0x8u
emilmont	60:3d0ef94e36ec	1127	#define I2C_C1_TXAK_SHIFT 3
emilmont	60:3d0ef94e36ec	1128	#define I2C_C1_TX_MASK 0x10u
emilmont	60:3d0ef94e36ec	1129	#define I2C_C1_TX_SHIFT 4
emilmont	60:3d0ef94e36ec	1130	#define I2C_C1_MST_MASK 0x20u
emilmont	60:3d0ef94e36ec	1131	#define I2C_C1_MST_SHIFT 5
emilmont	60:3d0ef94e36ec	1132	#define I2C_C1_IICIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	1133	#define I2C_C1_IICIE_SHIFT 6
emilmont	60:3d0ef94e36ec	1134	#define I2C_C1_IICEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	1135	#define I2C_C1_IICEN_SHIFT 7
emilmont	60:3d0ef94e36ec	1136	/* S Bit Fields */
emilmont	60:3d0ef94e36ec	1137	#define I2C_S_RXAK_MASK 0x1u
emilmont	60:3d0ef94e36ec	1138	#define I2C_S_RXAK_SHIFT 0
emilmont	60:3d0ef94e36ec	1139	#define I2C_S_IICIF_MASK 0x2u
emilmont	60:3d0ef94e36ec	1140	#define I2C_S_IICIF_SHIFT 1
emilmont	60:3d0ef94e36ec	1141	#define I2C_S_SRW_MASK 0x4u
emilmont	60:3d0ef94e36ec	1142	#define I2C_S_SRW_SHIFT 2
emilmont	60:3d0ef94e36ec	1143	#define I2C_S_RAM_MASK 0x8u
emilmont	60:3d0ef94e36ec	1144	#define I2C_S_RAM_SHIFT 3
emilmont	60:3d0ef94e36ec	1145	#define I2C_S_ARBL_MASK 0x10u
emilmont	60:3d0ef94e36ec	1146	#define I2C_S_ARBL_SHIFT 4
emilmont	60:3d0ef94e36ec	1147	#define I2C_S_BUSY_MASK 0x20u
emilmont	60:3d0ef94e36ec	1148	#define I2C_S_BUSY_SHIFT 5
emilmont	60:3d0ef94e36ec	1149	#define I2C_S_IAAS_MASK 0x40u
emilmont	60:3d0ef94e36ec	1150	#define I2C_S_IAAS_SHIFT 6
emilmont	60:3d0ef94e36ec	1151	#define I2C_S_TCF_MASK 0x80u
emilmont	60:3d0ef94e36ec	1152	#define I2C_S_TCF_SHIFT 7
emilmont	60:3d0ef94e36ec	1153	/* D Bit Fields */
emilmont	60:3d0ef94e36ec	1154	#define I2C_D_DATA_MASK 0xFFu
emilmont	60:3d0ef94e36ec	1155	#define I2C_D_DATA_SHIFT 0
emilmont	60:3d0ef94e36ec	1156	#define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x))<<I2C_D_DATA_SHIFT))&I2C_D_DATA_MASK)
emilmont	60:3d0ef94e36ec	1157	/* C2 Bit Fields */
emilmont	60:3d0ef94e36ec	1158	#define I2C_C2_AD_MASK 0x7u
emilmont	60:3d0ef94e36ec	1159	#define I2C_C2_AD_SHIFT 0
emilmont	60:3d0ef94e36ec	1160	#define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x))<<I2C_C2_AD_SHIFT))&I2C_C2_AD_MASK)
emilmont	60:3d0ef94e36ec	1161	#define I2C_C2_RMEN_MASK 0x8u
emilmont	60:3d0ef94e36ec	1162	#define I2C_C2_RMEN_SHIFT 3
emilmont	60:3d0ef94e36ec	1163	#define I2C_C2_SBRC_MASK 0x10u
emilmont	60:3d0ef94e36ec	1164	#define I2C_C2_SBRC_SHIFT 4
emilmont	60:3d0ef94e36ec	1165	#define I2C_C2_HDRS_MASK 0x20u
emilmont	60:3d0ef94e36ec	1166	#define I2C_C2_HDRS_SHIFT 5
emilmont	60:3d0ef94e36ec	1167	#define I2C_C2_ADEXT_MASK 0x40u
emilmont	60:3d0ef94e36ec	1168	#define I2C_C2_ADEXT_SHIFT 6
emilmont	60:3d0ef94e36ec	1169	#define I2C_C2_GCAEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	1170	#define I2C_C2_GCAEN_SHIFT 7
emilmont	60:3d0ef94e36ec	1171	/* FLT Bit Fields */
emilmont	60:3d0ef94e36ec	1172	#define I2C_FLT_FLT_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	1173	#define I2C_FLT_FLT_SHIFT 0
emilmont	60:3d0ef94e36ec	1174	#define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_FLT_FLT_SHIFT))&I2C_FLT_FLT_MASK)
emilmont	60:3d0ef94e36ec	1175	#define I2C_FLT_STOPIE_MASK 0x20u
emilmont	60:3d0ef94e36ec	1176	#define I2C_FLT_STOPIE_SHIFT 5
emilmont	60:3d0ef94e36ec	1177	#define I2C_FLT_STOPF_MASK 0x40u
emilmont	60:3d0ef94e36ec	1178	#define I2C_FLT_STOPF_SHIFT 6
emilmont	60:3d0ef94e36ec	1179	#define I2C_FLT_SHEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	1180	#define I2C_FLT_SHEN_SHIFT 7
emilmont	60:3d0ef94e36ec	1181	/* RA Bit Fields */
emilmont	60:3d0ef94e36ec	1182	#define I2C_RA_RAD_MASK 0xFEu
emilmont	60:3d0ef94e36ec	1183	#define I2C_RA_RAD_SHIFT 1
emilmont	60:3d0ef94e36ec	1184	#define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_RA_RAD_SHIFT))&I2C_RA_RAD_MASK)
emilmont	60:3d0ef94e36ec	1185	/* SMB Bit Fields */
emilmont	60:3d0ef94e36ec	1186	#define I2C_SMB_SHTF2IE_MASK 0x1u
emilmont	60:3d0ef94e36ec	1187	#define I2C_SMB_SHTF2IE_SHIFT 0
emilmont	60:3d0ef94e36ec	1188	#define I2C_SMB_SHTF2_MASK 0x2u
emilmont	60:3d0ef94e36ec	1189	#define I2C_SMB_SHTF2_SHIFT 1
emilmont	60:3d0ef94e36ec	1190	#define I2C_SMB_SHTF1_MASK 0x4u
emilmont	60:3d0ef94e36ec	1191	#define I2C_SMB_SHTF1_SHIFT 2
emilmont	60:3d0ef94e36ec	1192	#define I2C_SMB_SLTF_MASK 0x8u
emilmont	60:3d0ef94e36ec	1193	#define I2C_SMB_SLTF_SHIFT 3
emilmont	60:3d0ef94e36ec	1194	#define I2C_SMB_TCKSEL_MASK 0x10u
emilmont	60:3d0ef94e36ec	1195	#define I2C_SMB_TCKSEL_SHIFT 4
emilmont	60:3d0ef94e36ec	1196	#define I2C_SMB_SIICAEN_MASK 0x20u
emilmont	60:3d0ef94e36ec	1197	#define I2C_SMB_SIICAEN_SHIFT 5
emilmont	60:3d0ef94e36ec	1198	#define I2C_SMB_ALERTEN_MASK 0x40u
emilmont	60:3d0ef94e36ec	1199	#define I2C_SMB_ALERTEN_SHIFT 6
emilmont	60:3d0ef94e36ec	1200	#define I2C_SMB_FACK_MASK 0x80u
emilmont	60:3d0ef94e36ec	1201	#define I2C_SMB_FACK_SHIFT 7
emilmont	60:3d0ef94e36ec	1202	/* A2 Bit Fields */
emilmont	60:3d0ef94e36ec	1203	#define I2C_A2_SAD_MASK 0xFEu
emilmont	60:3d0ef94e36ec	1204	#define I2C_A2_SAD_SHIFT 1
emilmont	60:3d0ef94e36ec	1205	#define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x))<<I2C_A2_SAD_SHIFT))&I2C_A2_SAD_MASK)
emilmont	60:3d0ef94e36ec	1206	/* SLTH Bit Fields */
emilmont	60:3d0ef94e36ec	1207	#define I2C_SLTH_SSLT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	1208	#define I2C_SLTH_SSLT_SHIFT 0
emilmont	60:3d0ef94e36ec	1209	#define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTH_SSLT_SHIFT))&I2C_SLTH_SSLT_MASK)
emilmont	60:3d0ef94e36ec	1210	/* SLTL Bit Fields */
emilmont	60:3d0ef94e36ec	1211	#define I2C_SLTL_SSLT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	1212	#define I2C_SLTL_SSLT_SHIFT 0
emilmont	60:3d0ef94e36ec	1213	#define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x))<<I2C_SLTL_SSLT_SHIFT))&I2C_SLTL_SSLT_MASK)
emilmont	60:3d0ef94e36ec	1214
emilmont	60:3d0ef94e36ec	1215	/**
emilmont	60:3d0ef94e36ec	1216	* @}
emilmont	60:3d0ef94e36ec	1217	/ / end of group I2C_Register_Masks */
emilmont	60:3d0ef94e36ec	1218
emilmont	60:3d0ef94e36ec	1219
emilmont	60:3d0ef94e36ec	1220	/* I2C - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	1221	/** Peripheral I2C0 base address */
emilmont	60:3d0ef94e36ec	1222	#define I2C0_BASE (0x40066000u)
emilmont	60:3d0ef94e36ec	1223	/** Peripheral I2C0 base pointer */
emilmont	60:3d0ef94e36ec	1224	#define I2C0 ((I2C_Type *)I2C0_BASE)
emilmont	60:3d0ef94e36ec	1225	/** Peripheral I2C1 base address */
emilmont	60:3d0ef94e36ec	1226	#define I2C1_BASE (0x40067000u)
emilmont	60:3d0ef94e36ec	1227	/** Peripheral I2C1 base pointer */
emilmont	60:3d0ef94e36ec	1228	#define I2C1 ((I2C_Type *)I2C1_BASE)
emilmont	60:3d0ef94e36ec	1229	/** Array initializer of I2C peripheral base pointers */
emilmont	60:3d0ef94e36ec	1230	#define I2C_BASES { I2C0, I2C1 }
emilmont	60:3d0ef94e36ec	1231
emilmont	60:3d0ef94e36ec	1232	/**
emilmont	60:3d0ef94e36ec	1233	* @}
emilmont	60:3d0ef94e36ec	1234	/ / end of group I2C_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	1235
emilmont	60:3d0ef94e36ec	1236
emilmont	60:3d0ef94e36ec	1237	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1238	-- LLWU Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1239	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1240
emilmont	60:3d0ef94e36ec	1241	/**
emilmont	60:3d0ef94e36ec	1242	* @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1243	* @{
emilmont	60:3d0ef94e36ec	1244	*/
emilmont	60:3d0ef94e36ec	1245
emilmont	60:3d0ef94e36ec	1246	/** LLWU - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	1247	typedef struct {
emilmont	60:3d0ef94e36ec	1248	__IO uint8_t PE1; /*< LLWU Pin Enable 1 register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	1249	__IO uint8_t PE2; /*< LLWU Pin Enable 2 register, offset: 0x1 /
emilmont	60:3d0ef94e36ec	1250	__IO uint8_t PE3; /*< LLWU Pin Enable 3 register, offset: 0x2 /
emilmont	60:3d0ef94e36ec	1251	__IO uint8_t PE4; /*< LLWU Pin Enable 4 register, offset: 0x3 /
emilmont	60:3d0ef94e36ec	1252	__IO uint8_t ME; /*< LLWU Module Enable register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	1253	__IO uint8_t F1; /*< LLWU Flag 1 register, offset: 0x5 /
emilmont	60:3d0ef94e36ec	1254	__IO uint8_t F2; /*< LLWU Flag 2 register, offset: 0x6 /
emilmont	60:3d0ef94e36ec	1255	__I uint8_t F3; /*< LLWU Flag 3 register, offset: 0x7 /
emilmont	60:3d0ef94e36ec	1256	__IO uint8_t FILT1; /*< LLWU Pin Filter 1 register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	1257	__IO uint8_t FILT2; /*< LLWU Pin Filter 2 register, offset: 0x9 /
emilmont	60:3d0ef94e36ec	1258	} LLWU_Type;
emilmont	60:3d0ef94e36ec	1259
emilmont	60:3d0ef94e36ec	1260	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1261	-- LLWU Register Masks
emilmont	60:3d0ef94e36ec	1262	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1263
emilmont	60:3d0ef94e36ec	1264	/**
emilmont	60:3d0ef94e36ec	1265	* @addtogroup LLWU_Register_Masks LLWU Register Masks
emilmont	60:3d0ef94e36ec	1266	* @{
emilmont	60:3d0ef94e36ec	1267	*/
emilmont	60:3d0ef94e36ec	1268
emilmont	60:3d0ef94e36ec	1269	/* PE1 Bit Fields */
emilmont	60:3d0ef94e36ec	1270	#define LLWU_PE1_WUPE0_MASK 0x3u
emilmont	60:3d0ef94e36ec	1271	#define LLWU_PE1_WUPE0_SHIFT 0
emilmont	60:3d0ef94e36ec	1272	#define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE0_SHIFT))&LLWU_PE1_WUPE0_MASK)
emilmont	60:3d0ef94e36ec	1273	#define LLWU_PE1_WUPE1_MASK 0xCu
emilmont	60:3d0ef94e36ec	1274	#define LLWU_PE1_WUPE1_SHIFT 2
emilmont	60:3d0ef94e36ec	1275	#define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE1_SHIFT))&LLWU_PE1_WUPE1_MASK)
emilmont	60:3d0ef94e36ec	1276	#define LLWU_PE1_WUPE2_MASK 0x30u
emilmont	60:3d0ef94e36ec	1277	#define LLWU_PE1_WUPE2_SHIFT 4
emilmont	60:3d0ef94e36ec	1278	#define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE2_SHIFT))&LLWU_PE1_WUPE2_MASK)
emilmont	60:3d0ef94e36ec	1279	#define LLWU_PE1_WUPE3_MASK 0xC0u
emilmont	60:3d0ef94e36ec	1280	#define LLWU_PE1_WUPE3_SHIFT 6
emilmont	60:3d0ef94e36ec	1281	#define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE1_WUPE3_SHIFT))&LLWU_PE1_WUPE3_MASK)
emilmont	60:3d0ef94e36ec	1282	/* PE2 Bit Fields */
emilmont	60:3d0ef94e36ec	1283	#define LLWU_PE2_WUPE4_MASK 0x3u
emilmont	60:3d0ef94e36ec	1284	#define LLWU_PE2_WUPE4_SHIFT 0
emilmont	60:3d0ef94e36ec	1285	#define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE4_SHIFT))&LLWU_PE2_WUPE4_MASK)
emilmont	60:3d0ef94e36ec	1286	#define LLWU_PE2_WUPE5_MASK 0xCu
emilmont	60:3d0ef94e36ec	1287	#define LLWU_PE2_WUPE5_SHIFT 2
emilmont	60:3d0ef94e36ec	1288	#define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE5_SHIFT))&LLWU_PE2_WUPE5_MASK)
emilmont	60:3d0ef94e36ec	1289	#define LLWU_PE2_WUPE6_MASK 0x30u
emilmont	60:3d0ef94e36ec	1290	#define LLWU_PE2_WUPE6_SHIFT 4
emilmont	60:3d0ef94e36ec	1291	#define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE6_SHIFT))&LLWU_PE2_WUPE6_MASK)
emilmont	60:3d0ef94e36ec	1292	#define LLWU_PE2_WUPE7_MASK 0xC0u
emilmont	60:3d0ef94e36ec	1293	#define LLWU_PE2_WUPE7_SHIFT 6
emilmont	60:3d0ef94e36ec	1294	#define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE2_WUPE7_SHIFT))&LLWU_PE2_WUPE7_MASK)
emilmont	60:3d0ef94e36ec	1295	/* PE3 Bit Fields */
emilmont	60:3d0ef94e36ec	1296	#define LLWU_PE3_WUPE8_MASK 0x3u
emilmont	60:3d0ef94e36ec	1297	#define LLWU_PE3_WUPE8_SHIFT 0
emilmont	60:3d0ef94e36ec	1298	#define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE8_SHIFT))&LLWU_PE3_WUPE8_MASK)
emilmont	60:3d0ef94e36ec	1299	#define LLWU_PE3_WUPE9_MASK 0xCu
emilmont	60:3d0ef94e36ec	1300	#define LLWU_PE3_WUPE9_SHIFT 2
emilmont	60:3d0ef94e36ec	1301	#define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE9_SHIFT))&LLWU_PE3_WUPE9_MASK)
emilmont	60:3d0ef94e36ec	1302	#define LLWU_PE3_WUPE10_MASK 0x30u
emilmont	60:3d0ef94e36ec	1303	#define LLWU_PE3_WUPE10_SHIFT 4
emilmont	60:3d0ef94e36ec	1304	#define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE10_SHIFT))&LLWU_PE3_WUPE10_MASK)
emilmont	60:3d0ef94e36ec	1305	#define LLWU_PE3_WUPE11_MASK 0xC0u
emilmont	60:3d0ef94e36ec	1306	#define LLWU_PE3_WUPE11_SHIFT 6
emilmont	60:3d0ef94e36ec	1307	#define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE3_WUPE11_SHIFT))&LLWU_PE3_WUPE11_MASK)
emilmont	60:3d0ef94e36ec	1308	/* PE4 Bit Fields */
emilmont	60:3d0ef94e36ec	1309	#define LLWU_PE4_WUPE12_MASK 0x3u
emilmont	60:3d0ef94e36ec	1310	#define LLWU_PE4_WUPE12_SHIFT 0
emilmont	60:3d0ef94e36ec	1311	#define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE12_SHIFT))&LLWU_PE4_WUPE12_MASK)
emilmont	60:3d0ef94e36ec	1312	#define LLWU_PE4_WUPE13_MASK 0xCu
emilmont	60:3d0ef94e36ec	1313	#define LLWU_PE4_WUPE13_SHIFT 2
emilmont	60:3d0ef94e36ec	1314	#define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE13_SHIFT))&LLWU_PE4_WUPE13_MASK)
emilmont	60:3d0ef94e36ec	1315	#define LLWU_PE4_WUPE14_MASK 0x30u
emilmont	60:3d0ef94e36ec	1316	#define LLWU_PE4_WUPE14_SHIFT 4
emilmont	60:3d0ef94e36ec	1317	#define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE14_SHIFT))&LLWU_PE4_WUPE14_MASK)
emilmont	60:3d0ef94e36ec	1318	#define LLWU_PE4_WUPE15_MASK 0xC0u
emilmont	60:3d0ef94e36ec	1319	#define LLWU_PE4_WUPE15_SHIFT 6
emilmont	60:3d0ef94e36ec	1320	#define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x))<<LLWU_PE4_WUPE15_SHIFT))&LLWU_PE4_WUPE15_MASK)
emilmont	60:3d0ef94e36ec	1321	/* ME Bit Fields */
emilmont	60:3d0ef94e36ec	1322	#define LLWU_ME_WUME0_MASK 0x1u
emilmont	60:3d0ef94e36ec	1323	#define LLWU_ME_WUME0_SHIFT 0
emilmont	60:3d0ef94e36ec	1324	#define LLWU_ME_WUME1_MASK 0x2u
emilmont	60:3d0ef94e36ec	1325	#define LLWU_ME_WUME1_SHIFT 1
emilmont	60:3d0ef94e36ec	1326	#define LLWU_ME_WUME2_MASK 0x4u
emilmont	60:3d0ef94e36ec	1327	#define LLWU_ME_WUME2_SHIFT 2
emilmont	60:3d0ef94e36ec	1328	#define LLWU_ME_WUME3_MASK 0x8u
emilmont	60:3d0ef94e36ec	1329	#define LLWU_ME_WUME3_SHIFT 3
emilmont	60:3d0ef94e36ec	1330	#define LLWU_ME_WUME4_MASK 0x10u
emilmont	60:3d0ef94e36ec	1331	#define LLWU_ME_WUME4_SHIFT 4
emilmont	60:3d0ef94e36ec	1332	#define LLWU_ME_WUME5_MASK 0x20u
emilmont	60:3d0ef94e36ec	1333	#define LLWU_ME_WUME5_SHIFT 5
emilmont	60:3d0ef94e36ec	1334	#define LLWU_ME_WUME6_MASK 0x40u
emilmont	60:3d0ef94e36ec	1335	#define LLWU_ME_WUME6_SHIFT 6
emilmont	60:3d0ef94e36ec	1336	#define LLWU_ME_WUME7_MASK 0x80u
emilmont	60:3d0ef94e36ec	1337	#define LLWU_ME_WUME7_SHIFT 7
emilmont	60:3d0ef94e36ec	1338	/* F1 Bit Fields */
emilmont	60:3d0ef94e36ec	1339	#define LLWU_F1_WUF0_MASK 0x1u
emilmont	60:3d0ef94e36ec	1340	#define LLWU_F1_WUF0_SHIFT 0
emilmont	60:3d0ef94e36ec	1341	#define LLWU_F1_WUF1_MASK 0x2u
emilmont	60:3d0ef94e36ec	1342	#define LLWU_F1_WUF1_SHIFT 1
emilmont	60:3d0ef94e36ec	1343	#define LLWU_F1_WUF2_MASK 0x4u
emilmont	60:3d0ef94e36ec	1344	#define LLWU_F1_WUF2_SHIFT 2
emilmont	60:3d0ef94e36ec	1345	#define LLWU_F1_WUF3_MASK 0x8u
emilmont	60:3d0ef94e36ec	1346	#define LLWU_F1_WUF3_SHIFT 3
emilmont	60:3d0ef94e36ec	1347	#define LLWU_F1_WUF4_MASK 0x10u
emilmont	60:3d0ef94e36ec	1348	#define LLWU_F1_WUF4_SHIFT 4
emilmont	60:3d0ef94e36ec	1349	#define LLWU_F1_WUF5_MASK 0x20u
emilmont	60:3d0ef94e36ec	1350	#define LLWU_F1_WUF5_SHIFT 5
emilmont	60:3d0ef94e36ec	1351	#define LLWU_F1_WUF6_MASK 0x40u
emilmont	60:3d0ef94e36ec	1352	#define LLWU_F1_WUF6_SHIFT 6
emilmont	60:3d0ef94e36ec	1353	#define LLWU_F1_WUF7_MASK 0x80u
emilmont	60:3d0ef94e36ec	1354	#define LLWU_F1_WUF7_SHIFT 7
emilmont	60:3d0ef94e36ec	1355	/* F2 Bit Fields */
emilmont	60:3d0ef94e36ec	1356	#define LLWU_F2_WUF8_MASK 0x1u
emilmont	60:3d0ef94e36ec	1357	#define LLWU_F2_WUF8_SHIFT 0
emilmont	60:3d0ef94e36ec	1358	#define LLWU_F2_WUF9_MASK 0x2u
emilmont	60:3d0ef94e36ec	1359	#define LLWU_F2_WUF9_SHIFT 1
emilmont	60:3d0ef94e36ec	1360	#define LLWU_F2_WUF10_MASK 0x4u
emilmont	60:3d0ef94e36ec	1361	#define LLWU_F2_WUF10_SHIFT 2
emilmont	60:3d0ef94e36ec	1362	#define LLWU_F2_WUF11_MASK 0x8u
emilmont	60:3d0ef94e36ec	1363	#define LLWU_F2_WUF11_SHIFT 3
emilmont	60:3d0ef94e36ec	1364	#define LLWU_F2_WUF12_MASK 0x10u
emilmont	60:3d0ef94e36ec	1365	#define LLWU_F2_WUF12_SHIFT 4
emilmont	60:3d0ef94e36ec	1366	#define LLWU_F2_WUF13_MASK 0x20u
emilmont	60:3d0ef94e36ec	1367	#define LLWU_F2_WUF13_SHIFT 5
emilmont	60:3d0ef94e36ec	1368	#define LLWU_F2_WUF14_MASK 0x40u
emilmont	60:3d0ef94e36ec	1369	#define LLWU_F2_WUF14_SHIFT 6
emilmont	60:3d0ef94e36ec	1370	#define LLWU_F2_WUF15_MASK 0x80u
emilmont	60:3d0ef94e36ec	1371	#define LLWU_F2_WUF15_SHIFT 7
emilmont	60:3d0ef94e36ec	1372	/* F3 Bit Fields */
emilmont	60:3d0ef94e36ec	1373	#define LLWU_F3_MWUF0_MASK 0x1u
emilmont	60:3d0ef94e36ec	1374	#define LLWU_F3_MWUF0_SHIFT 0
emilmont	60:3d0ef94e36ec	1375	#define LLWU_F3_MWUF1_MASK 0x2u
emilmont	60:3d0ef94e36ec	1376	#define LLWU_F3_MWUF1_SHIFT 1
emilmont	60:3d0ef94e36ec	1377	#define LLWU_F3_MWUF2_MASK 0x4u
emilmont	60:3d0ef94e36ec	1378	#define LLWU_F3_MWUF2_SHIFT 2
emilmont	60:3d0ef94e36ec	1379	#define LLWU_F3_MWUF3_MASK 0x8u
emilmont	60:3d0ef94e36ec	1380	#define LLWU_F3_MWUF3_SHIFT 3
emilmont	60:3d0ef94e36ec	1381	#define LLWU_F3_MWUF4_MASK 0x10u
emilmont	60:3d0ef94e36ec	1382	#define LLWU_F3_MWUF4_SHIFT 4
emilmont	60:3d0ef94e36ec	1383	#define LLWU_F3_MWUF5_MASK 0x20u
emilmont	60:3d0ef94e36ec	1384	#define LLWU_F3_MWUF5_SHIFT 5
emilmont	60:3d0ef94e36ec	1385	#define LLWU_F3_MWUF6_MASK 0x40u
emilmont	60:3d0ef94e36ec	1386	#define LLWU_F3_MWUF6_SHIFT 6
emilmont	60:3d0ef94e36ec	1387	#define LLWU_F3_MWUF7_MASK 0x80u
emilmont	60:3d0ef94e36ec	1388	#define LLWU_F3_MWUF7_SHIFT 7
emilmont	60:3d0ef94e36ec	1389	/* FILT1 Bit Fields */
emilmont	60:3d0ef94e36ec	1390	#define LLWU_FILT1_FILTSEL_MASK 0xFu
emilmont	60:3d0ef94e36ec	1391	#define LLWU_FILT1_FILTSEL_SHIFT 0
emilmont	60:3d0ef94e36ec	1392	#define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTSEL_SHIFT))&LLWU_FILT1_FILTSEL_MASK)
emilmont	60:3d0ef94e36ec	1393	#define LLWU_FILT1_FILTE_MASK 0x60u
emilmont	60:3d0ef94e36ec	1394	#define LLWU_FILT1_FILTE_SHIFT 5
emilmont	60:3d0ef94e36ec	1395	#define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT1_FILTE_SHIFT))&LLWU_FILT1_FILTE_MASK)
emilmont	60:3d0ef94e36ec	1396	#define LLWU_FILT1_FILTF_MASK 0x80u
emilmont	60:3d0ef94e36ec	1397	#define LLWU_FILT1_FILTF_SHIFT 7
emilmont	60:3d0ef94e36ec	1398	/* FILT2 Bit Fields */
emilmont	60:3d0ef94e36ec	1399	#define LLWU_FILT2_FILTSEL_MASK 0xFu
emilmont	60:3d0ef94e36ec	1400	#define LLWU_FILT2_FILTSEL_SHIFT 0
emilmont	60:3d0ef94e36ec	1401	#define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTSEL_SHIFT))&LLWU_FILT2_FILTSEL_MASK)
emilmont	60:3d0ef94e36ec	1402	#define LLWU_FILT2_FILTE_MASK 0x60u
emilmont	60:3d0ef94e36ec	1403	#define LLWU_FILT2_FILTE_SHIFT 5
emilmont	60:3d0ef94e36ec	1404	#define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x))<<LLWU_FILT2_FILTE_SHIFT))&LLWU_FILT2_FILTE_MASK)
emilmont	60:3d0ef94e36ec	1405	#define LLWU_FILT2_FILTF_MASK 0x80u
emilmont	60:3d0ef94e36ec	1406	#define LLWU_FILT2_FILTF_SHIFT 7
emilmont	60:3d0ef94e36ec	1407
emilmont	60:3d0ef94e36ec	1408	/**
emilmont	60:3d0ef94e36ec	1409	* @}
emilmont	60:3d0ef94e36ec	1410	/ / end of group LLWU_Register_Masks */
emilmont	60:3d0ef94e36ec	1411
emilmont	60:3d0ef94e36ec	1412
emilmont	60:3d0ef94e36ec	1413	/* LLWU - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	1414	/** Peripheral LLWU base address */
emilmont	60:3d0ef94e36ec	1415	#define LLWU_BASE (0x4007C000u)
emilmont	60:3d0ef94e36ec	1416	/** Peripheral LLWU base pointer */
emilmont	60:3d0ef94e36ec	1417	#define LLWU ((LLWU_Type *)LLWU_BASE)
emilmont	60:3d0ef94e36ec	1418	/** Array initializer of LLWU peripheral base pointers */
emilmont	60:3d0ef94e36ec	1419	#define LLWU_BASES { LLWU }
emilmont	60:3d0ef94e36ec	1420
emilmont	60:3d0ef94e36ec	1421	/**
emilmont	60:3d0ef94e36ec	1422	* @}
emilmont	60:3d0ef94e36ec	1423	/ / end of group LLWU_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	1424
emilmont	60:3d0ef94e36ec	1425
emilmont	60:3d0ef94e36ec	1426	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1427	-- LPTMR Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1428	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1429
emilmont	60:3d0ef94e36ec	1430	/**
emilmont	60:3d0ef94e36ec	1431	* @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1432	* @{
emilmont	60:3d0ef94e36ec	1433	*/
emilmont	60:3d0ef94e36ec	1434
emilmont	60:3d0ef94e36ec	1435	/** LPTMR - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	1436	typedef struct {
emilmont	60:3d0ef94e36ec	1437	__IO uint32_t CSR; /*< Low Power Timer Control Status Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	1438	__IO uint32_t PSR; /*< Low Power Timer Prescale Register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	1439	__IO uint32_t CMR; /*< Low Power Timer Compare Register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	1440	__I uint32_t CNR; /*< Low Power Timer Counter Register, offset: 0xC /
emilmont	60:3d0ef94e36ec	1441	} LPTMR_Type;
emilmont	60:3d0ef94e36ec	1442
emilmont	60:3d0ef94e36ec	1443	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1444	-- LPTMR Register Masks
emilmont	60:3d0ef94e36ec	1445	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1446
emilmont	60:3d0ef94e36ec	1447	/**
emilmont	60:3d0ef94e36ec	1448	* @addtogroup LPTMR_Register_Masks LPTMR Register Masks
emilmont	60:3d0ef94e36ec	1449	* @{
emilmont	60:3d0ef94e36ec	1450	*/
emilmont	60:3d0ef94e36ec	1451
emilmont	60:3d0ef94e36ec	1452	/* CSR Bit Fields */
emilmont	60:3d0ef94e36ec	1453	#define LPTMR_CSR_TEN_MASK 0x1u
emilmont	60:3d0ef94e36ec	1454	#define LPTMR_CSR_TEN_SHIFT 0
emilmont	60:3d0ef94e36ec	1455	#define LPTMR_CSR_TMS_MASK 0x2u
emilmont	60:3d0ef94e36ec	1456	#define LPTMR_CSR_TMS_SHIFT 1
emilmont	60:3d0ef94e36ec	1457	#define LPTMR_CSR_TFC_MASK 0x4u
emilmont	60:3d0ef94e36ec	1458	#define LPTMR_CSR_TFC_SHIFT 2
emilmont	60:3d0ef94e36ec	1459	#define LPTMR_CSR_TPP_MASK 0x8u
emilmont	60:3d0ef94e36ec	1460	#define LPTMR_CSR_TPP_SHIFT 3
emilmont	60:3d0ef94e36ec	1461	#define LPTMR_CSR_TPS_MASK 0x30u
emilmont	60:3d0ef94e36ec	1462	#define LPTMR_CSR_TPS_SHIFT 4
emilmont	60:3d0ef94e36ec	1463	#define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CSR_TPS_SHIFT))&LPTMR_CSR_TPS_MASK)
emilmont	60:3d0ef94e36ec	1464	#define LPTMR_CSR_TIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	1465	#define LPTMR_CSR_TIE_SHIFT 6
emilmont	60:3d0ef94e36ec	1466	#define LPTMR_CSR_TCF_MASK 0x80u
emilmont	60:3d0ef94e36ec	1467	#define LPTMR_CSR_TCF_SHIFT 7
emilmont	60:3d0ef94e36ec	1468	/* PSR Bit Fields */
emilmont	60:3d0ef94e36ec	1469	#define LPTMR_PSR_PCS_MASK 0x3u
emilmont	60:3d0ef94e36ec	1470	#define LPTMR_PSR_PCS_SHIFT 0
emilmont	60:3d0ef94e36ec	1471	#define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PCS_SHIFT))&LPTMR_PSR_PCS_MASK)
emilmont	60:3d0ef94e36ec	1472	#define LPTMR_PSR_PBYP_MASK 0x4u
emilmont	60:3d0ef94e36ec	1473	#define LPTMR_PSR_PBYP_SHIFT 2
emilmont	60:3d0ef94e36ec	1474	#define LPTMR_PSR_PRESCALE_MASK 0x78u
emilmont	60:3d0ef94e36ec	1475	#define LPTMR_PSR_PRESCALE_SHIFT 3
emilmont	60:3d0ef94e36ec	1476	#define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_PSR_PRESCALE_SHIFT))&LPTMR_PSR_PRESCALE_MASK)
emilmont	60:3d0ef94e36ec	1477	/* CMR Bit Fields */
emilmont	60:3d0ef94e36ec	1478	#define LPTMR_CMR_COMPARE_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	1479	#define LPTMR_CMR_COMPARE_SHIFT 0
emilmont	60:3d0ef94e36ec	1480	#define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CMR_COMPARE_SHIFT))&LPTMR_CMR_COMPARE_MASK)
emilmont	60:3d0ef94e36ec	1481	/* CNR Bit Fields */
emilmont	60:3d0ef94e36ec	1482	#define LPTMR_CNR_COUNTER_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	1483	#define LPTMR_CNR_COUNTER_SHIFT 0
emilmont	60:3d0ef94e36ec	1484	#define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x))<<LPTMR_CNR_COUNTER_SHIFT))&LPTMR_CNR_COUNTER_MASK)
emilmont	60:3d0ef94e36ec	1485
emilmont	60:3d0ef94e36ec	1486	/**
emilmont	60:3d0ef94e36ec	1487	* @}
emilmont	60:3d0ef94e36ec	1488	/ / end of group LPTMR_Register_Masks */
emilmont	60:3d0ef94e36ec	1489
emilmont	60:3d0ef94e36ec	1490
emilmont	60:3d0ef94e36ec	1491	/* LPTMR - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	1492	/** Peripheral LPTMR0 base address */
emilmont	60:3d0ef94e36ec	1493	#define LPTMR0_BASE (0x40040000u)
emilmont	60:3d0ef94e36ec	1494	/** Peripheral LPTMR0 base pointer */
emilmont	60:3d0ef94e36ec	1495	#define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
emilmont	60:3d0ef94e36ec	1496	/** Array initializer of LPTMR peripheral base pointers */
emilmont	60:3d0ef94e36ec	1497	#define LPTMR_BASES { LPTMR0 }
emilmont	60:3d0ef94e36ec	1498
emilmont	60:3d0ef94e36ec	1499	/**
emilmont	60:3d0ef94e36ec	1500	* @}
emilmont	60:3d0ef94e36ec	1501	/ / end of group LPTMR_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	1502
emilmont	60:3d0ef94e36ec	1503
emilmont	60:3d0ef94e36ec	1504	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1505	-- MCG Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1506	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1507
emilmont	60:3d0ef94e36ec	1508	/**
emilmont	60:3d0ef94e36ec	1509	* @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1510	* @{
emilmont	60:3d0ef94e36ec	1511	*/
emilmont	60:3d0ef94e36ec	1512
emilmont	60:3d0ef94e36ec	1513	/** MCG - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	1514	typedef struct {
emilmont	60:3d0ef94e36ec	1515	__IO uint8_t C1; /*< MCG Control 1 Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	1516	__IO uint8_t C2; /*< MCG Control 2 Register, offset: 0x1 /
emilmont	60:3d0ef94e36ec	1517	__IO uint8_t C3; /*< MCG Control 3 Register, offset: 0x2 /
emilmont	60:3d0ef94e36ec	1518	__IO uint8_t C4; /*< MCG Control 4 Register, offset: 0x3 /
emilmont	60:3d0ef94e36ec	1519	__IO uint8_t C5; /*< MCG Control 5 Register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	1520	__IO uint8_t C6; /*< MCG Control 6 Register, offset: 0x5 /
emilmont	60:3d0ef94e36ec	1521	__I uint8_t S; /*< MCG Status Register, offset: 0x6 /
emilmont	60:3d0ef94e36ec	1522	uint8_t RESERVED_0[1];
emilmont	60:3d0ef94e36ec	1523	__IO uint8_t SC; /*< MCG Status and Control Register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	1524	uint8_t RESERVED_1[1];
emilmont	60:3d0ef94e36ec	1525	__IO uint8_t ATCVH; /*< MCG Auto Trim Compare Value High Register, offset: 0xA /
emilmont	60:3d0ef94e36ec	1526	__IO uint8_t ATCVL; /*< MCG Auto Trim Compare Value Low Register, offset: 0xB /
emilmont	60:3d0ef94e36ec	1527	__I uint8_t C7; /*< MCG Control 7 Register, offset: 0xC /
emilmont	60:3d0ef94e36ec	1528	__IO uint8_t C8; /*< MCG Control 8 Register, offset: 0xD /
emilmont	60:3d0ef94e36ec	1529	__I uint8_t C9; /*< MCG Control 9 Register, offset: 0xE /
emilmont	60:3d0ef94e36ec	1530	__I uint8_t C10; /*< MCG Control 10 Register, offset: 0xF /
emilmont	60:3d0ef94e36ec	1531	} MCG_Type;
emilmont	60:3d0ef94e36ec	1532
emilmont	60:3d0ef94e36ec	1533	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1534	-- MCG Register Masks
emilmont	60:3d0ef94e36ec	1535	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1536
emilmont	60:3d0ef94e36ec	1537	/**
emilmont	60:3d0ef94e36ec	1538	* @addtogroup MCG_Register_Masks MCG Register Masks
emilmont	60:3d0ef94e36ec	1539	* @{
emilmont	60:3d0ef94e36ec	1540	*/
emilmont	60:3d0ef94e36ec	1541
emilmont	60:3d0ef94e36ec	1542	/* C1 Bit Fields */
emilmont	60:3d0ef94e36ec	1543	#define MCG_C1_IREFSTEN_MASK 0x1u
emilmont	60:3d0ef94e36ec	1544	#define MCG_C1_IREFSTEN_SHIFT 0
emilmont	60:3d0ef94e36ec	1545	#define MCG_C1_IRCLKEN_MASK 0x2u
emilmont	60:3d0ef94e36ec	1546	#define MCG_C1_IRCLKEN_SHIFT 1
emilmont	60:3d0ef94e36ec	1547	#define MCG_C1_IREFS_MASK 0x4u
emilmont	60:3d0ef94e36ec	1548	#define MCG_C1_IREFS_SHIFT 2
emilmont	60:3d0ef94e36ec	1549	#define MCG_C1_FRDIV_MASK 0x38u
emilmont	60:3d0ef94e36ec	1550	#define MCG_C1_FRDIV_SHIFT 3
emilmont	60:3d0ef94e36ec	1551	#define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_FRDIV_SHIFT))&MCG_C1_FRDIV_MASK)
emilmont	60:3d0ef94e36ec	1552	#define MCG_C1_CLKS_MASK 0xC0u
emilmont	60:3d0ef94e36ec	1553	#define MCG_C1_CLKS_SHIFT 6
emilmont	60:3d0ef94e36ec	1554	#define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C1_CLKS_SHIFT))&MCG_C1_CLKS_MASK)
emilmont	60:3d0ef94e36ec	1555	/* C2 Bit Fields */
emilmont	60:3d0ef94e36ec	1556	#define MCG_C2_IRCS_MASK 0x1u
emilmont	60:3d0ef94e36ec	1557	#define MCG_C2_IRCS_SHIFT 0
emilmont	60:3d0ef94e36ec	1558	#define MCG_C2_LP_MASK 0x2u
emilmont	60:3d0ef94e36ec	1559	#define MCG_C2_LP_SHIFT 1
emilmont	60:3d0ef94e36ec	1560	#define MCG_C2_EREFS0_MASK 0x4u
emilmont	60:3d0ef94e36ec	1561	#define MCG_C2_EREFS0_SHIFT 2
emilmont	60:3d0ef94e36ec	1562	#define MCG_C2_HGO0_MASK 0x8u
emilmont	60:3d0ef94e36ec	1563	#define MCG_C2_HGO0_SHIFT 3
emilmont	60:3d0ef94e36ec	1564	#define MCG_C2_RANGE0_MASK 0x30u
emilmont	60:3d0ef94e36ec	1565	#define MCG_C2_RANGE0_SHIFT 4
emilmont	60:3d0ef94e36ec	1566	#define MCG_C2_RANGE0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C2_RANGE0_SHIFT))&MCG_C2_RANGE0_MASK)
emilmont	60:3d0ef94e36ec	1567	#define MCG_C2_LOCRE0_MASK 0x80u
emilmont	60:3d0ef94e36ec	1568	#define MCG_C2_LOCRE0_SHIFT 7
emilmont	60:3d0ef94e36ec	1569	/* C3 Bit Fields */
emilmont	60:3d0ef94e36ec	1570	#define MCG_C3_SCTRIM_MASK 0xFFu
emilmont	60:3d0ef94e36ec	1571	#define MCG_C3_SCTRIM_SHIFT 0
emilmont	60:3d0ef94e36ec	1572	#define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C3_SCTRIM_SHIFT))&MCG_C3_SCTRIM_MASK)
emilmont	60:3d0ef94e36ec	1573	/* C4 Bit Fields */
emilmont	60:3d0ef94e36ec	1574	#define MCG_C4_SCFTRIM_MASK 0x1u
emilmont	60:3d0ef94e36ec	1575	#define MCG_C4_SCFTRIM_SHIFT 0
emilmont	60:3d0ef94e36ec	1576	#define MCG_C4_FCTRIM_MASK 0x1Eu
emilmont	60:3d0ef94e36ec	1577	#define MCG_C4_FCTRIM_SHIFT 1
emilmont	60:3d0ef94e36ec	1578	#define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_FCTRIM_SHIFT))&MCG_C4_FCTRIM_MASK)
emilmont	60:3d0ef94e36ec	1579	#define MCG_C4_DRST_DRS_MASK 0x60u
emilmont	60:3d0ef94e36ec	1580	#define MCG_C4_DRST_DRS_SHIFT 5
emilmont	60:3d0ef94e36ec	1581	#define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x))<<MCG_C4_DRST_DRS_SHIFT))&MCG_C4_DRST_DRS_MASK)
emilmont	60:3d0ef94e36ec	1582	#define MCG_C4_DMX32_MASK 0x80u
emilmont	60:3d0ef94e36ec	1583	#define MCG_C4_DMX32_SHIFT 7
emilmont	60:3d0ef94e36ec	1584	/* C5 Bit Fields */
emilmont	60:3d0ef94e36ec	1585	#define MCG_C5_PRDIV0_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	1586	#define MCG_C5_PRDIV0_SHIFT 0
emilmont	60:3d0ef94e36ec	1587	#define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C5_PRDIV0_SHIFT))&MCG_C5_PRDIV0_MASK)
emilmont	60:3d0ef94e36ec	1588	#define MCG_C5_PLLSTEN0_MASK 0x20u
emilmont	60:3d0ef94e36ec	1589	#define MCG_C5_PLLSTEN0_SHIFT 5
emilmont	60:3d0ef94e36ec	1590	#define MCG_C5_PLLCLKEN0_MASK 0x40u
emilmont	60:3d0ef94e36ec	1591	#define MCG_C5_PLLCLKEN0_SHIFT 6
emilmont	60:3d0ef94e36ec	1592	/* C6 Bit Fields */
emilmont	60:3d0ef94e36ec	1593	#define MCG_C6_VDIV0_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	1594	#define MCG_C6_VDIV0_SHIFT 0
emilmont	60:3d0ef94e36ec	1595	#define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x))<<MCG_C6_VDIV0_SHIFT))&MCG_C6_VDIV0_MASK)
emilmont	60:3d0ef94e36ec	1596	#define MCG_C6_CME0_MASK 0x20u
emilmont	60:3d0ef94e36ec	1597	#define MCG_C6_CME0_SHIFT 5
emilmont	60:3d0ef94e36ec	1598	#define MCG_C6_PLLS_MASK 0x40u
emilmont	60:3d0ef94e36ec	1599	#define MCG_C6_PLLS_SHIFT 6
emilmont	60:3d0ef94e36ec	1600	#define MCG_C6_LOLIE0_MASK 0x80u
emilmont	60:3d0ef94e36ec	1601	#define MCG_C6_LOLIE0_SHIFT 7
emilmont	60:3d0ef94e36ec	1602	/* S Bit Fields */
emilmont	60:3d0ef94e36ec	1603	#define MCG_S_IRCST_MASK 0x1u
emilmont	60:3d0ef94e36ec	1604	#define MCG_S_IRCST_SHIFT 0
emilmont	60:3d0ef94e36ec	1605	#define MCG_S_OSCINIT0_MASK 0x2u
emilmont	60:3d0ef94e36ec	1606	#define MCG_S_OSCINIT0_SHIFT 1
emilmont	60:3d0ef94e36ec	1607	#define MCG_S_CLKST_MASK 0xCu
emilmont	60:3d0ef94e36ec	1608	#define MCG_S_CLKST_SHIFT 2
emilmont	60:3d0ef94e36ec	1609	#define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x))<<MCG_S_CLKST_SHIFT))&MCG_S_CLKST_MASK)
emilmont	60:3d0ef94e36ec	1610	#define MCG_S_IREFST_MASK 0x10u
emilmont	60:3d0ef94e36ec	1611	#define MCG_S_IREFST_SHIFT 4
emilmont	60:3d0ef94e36ec	1612	#define MCG_S_PLLST_MASK 0x20u
emilmont	60:3d0ef94e36ec	1613	#define MCG_S_PLLST_SHIFT 5
emilmont	60:3d0ef94e36ec	1614	#define MCG_S_LOCK0_MASK 0x40u
emilmont	60:3d0ef94e36ec	1615	#define MCG_S_LOCK0_SHIFT 6
emilmont	60:3d0ef94e36ec	1616	#define MCG_S_LOLS_MASK 0x80u
emilmont	60:3d0ef94e36ec	1617	#define MCG_S_LOLS_SHIFT 7
emilmont	60:3d0ef94e36ec	1618	/* SC Bit Fields */
emilmont	60:3d0ef94e36ec	1619	#define MCG_SC_LOCS0_MASK 0x1u
emilmont	60:3d0ef94e36ec	1620	#define MCG_SC_LOCS0_SHIFT 0
emilmont	60:3d0ef94e36ec	1621	#define MCG_SC_FCRDIV_MASK 0xEu
emilmont	60:3d0ef94e36ec	1622	#define MCG_SC_FCRDIV_SHIFT 1
emilmont	60:3d0ef94e36ec	1623	#define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x))<<MCG_SC_FCRDIV_SHIFT))&MCG_SC_FCRDIV_MASK)
emilmont	60:3d0ef94e36ec	1624	#define MCG_SC_FLTPRSRV_MASK 0x10u
emilmont	60:3d0ef94e36ec	1625	#define MCG_SC_FLTPRSRV_SHIFT 4
emilmont	60:3d0ef94e36ec	1626	#define MCG_SC_ATMF_MASK 0x20u
emilmont	60:3d0ef94e36ec	1627	#define MCG_SC_ATMF_SHIFT 5
emilmont	60:3d0ef94e36ec	1628	#define MCG_SC_ATMS_MASK 0x40u
emilmont	60:3d0ef94e36ec	1629	#define MCG_SC_ATMS_SHIFT 6
emilmont	60:3d0ef94e36ec	1630	#define MCG_SC_ATME_MASK 0x80u
emilmont	60:3d0ef94e36ec	1631	#define MCG_SC_ATME_SHIFT 7
emilmont	60:3d0ef94e36ec	1632	/* ATCVH Bit Fields */
emilmont	60:3d0ef94e36ec	1633	#define MCG_ATCVH_ATCVH_MASK 0xFFu
emilmont	60:3d0ef94e36ec	1634	#define MCG_ATCVH_ATCVH_SHIFT 0
emilmont	60:3d0ef94e36ec	1635	#define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVH_ATCVH_SHIFT))&MCG_ATCVH_ATCVH_MASK)
emilmont	60:3d0ef94e36ec	1636	/* ATCVL Bit Fields */
emilmont	60:3d0ef94e36ec	1637	#define MCG_ATCVL_ATCVL_MASK 0xFFu
emilmont	60:3d0ef94e36ec	1638	#define MCG_ATCVL_ATCVL_SHIFT 0
emilmont	60:3d0ef94e36ec	1639	#define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x))<<MCG_ATCVL_ATCVL_SHIFT))&MCG_ATCVL_ATCVL_MASK)
emilmont	60:3d0ef94e36ec	1640	/* C8 Bit Fields */
emilmont	60:3d0ef94e36ec	1641	#define MCG_C8_LOLRE_MASK 0x40u
emilmont	60:3d0ef94e36ec	1642	#define MCG_C8_LOLRE_SHIFT 6
emilmont	60:3d0ef94e36ec	1643
emilmont	60:3d0ef94e36ec	1644	/**
emilmont	60:3d0ef94e36ec	1645	* @}
emilmont	60:3d0ef94e36ec	1646	/ / end of group MCG_Register_Masks */
emilmont	60:3d0ef94e36ec	1647
emilmont	60:3d0ef94e36ec	1648
emilmont	60:3d0ef94e36ec	1649	/* MCG - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	1650	/** Peripheral MCG base address */
emilmont	60:3d0ef94e36ec	1651	#define MCG_BASE (0x40064000u)
emilmont	60:3d0ef94e36ec	1652	/** Peripheral MCG base pointer */
emilmont	60:3d0ef94e36ec	1653	#define MCG ((MCG_Type *)MCG_BASE)
emilmont	60:3d0ef94e36ec	1654	/** Array initializer of MCG peripheral base pointers */
emilmont	60:3d0ef94e36ec	1655	#define MCG_BASES { MCG }
emilmont	60:3d0ef94e36ec	1656
emilmont	60:3d0ef94e36ec	1657	/**
emilmont	60:3d0ef94e36ec	1658	* @}
emilmont	60:3d0ef94e36ec	1659	/ / end of group MCG_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	1660
emilmont	60:3d0ef94e36ec	1661
emilmont	60:3d0ef94e36ec	1662	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1663	-- MCM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1664	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1665
emilmont	60:3d0ef94e36ec	1666	/**
emilmont	60:3d0ef94e36ec	1667	* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1668	* @{
emilmont	60:3d0ef94e36ec	1669	*/
emilmont	60:3d0ef94e36ec	1670
emilmont	60:3d0ef94e36ec	1671	/** MCM - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	1672	typedef struct {
emilmont	60:3d0ef94e36ec	1673	uint8_t RESERVED_0[8];
emilmont	60:3d0ef94e36ec	1674	__I uint16_t PLASC; /*< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 /
emilmont	60:3d0ef94e36ec	1675	__I uint16_t PLAMC; /*< Crossbar Switch (AXBS) Master Configuration, offset: 0xA /
emilmont	60:3d0ef94e36ec	1676	__IO uint32_t PLACR; /*< Platform Control Register, offset: 0xC /
emilmont	60:3d0ef94e36ec	1677	uint8_t RESERVED_1[48];
emilmont	60:3d0ef94e36ec	1678	__IO uint32_t CPO; /*< Compute Operation Control Register, offset: 0x40 /
emilmont	60:3d0ef94e36ec	1679	} MCM_Type;
emilmont	60:3d0ef94e36ec	1680
emilmont	60:3d0ef94e36ec	1681	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1682	-- MCM Register Masks
emilmont	60:3d0ef94e36ec	1683	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1684
emilmont	60:3d0ef94e36ec	1685	/**
emilmont	60:3d0ef94e36ec	1686	* @addtogroup MCM_Register_Masks MCM Register Masks
emilmont	60:3d0ef94e36ec	1687	* @{
emilmont	60:3d0ef94e36ec	1688	*/
emilmont	60:3d0ef94e36ec	1689
emilmont	60:3d0ef94e36ec	1690	/* PLASC Bit Fields */
emilmont	60:3d0ef94e36ec	1691	#define MCM_PLASC_ASC_MASK 0xFFu
emilmont	60:3d0ef94e36ec	1692	#define MCM_PLASC_ASC_SHIFT 0
emilmont	60:3d0ef94e36ec	1693	#define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLASC_ASC_SHIFT))&MCM_PLASC_ASC_MASK)
emilmont	60:3d0ef94e36ec	1694	/* PLAMC Bit Fields */
emilmont	60:3d0ef94e36ec	1695	#define MCM_PLAMC_AMC_MASK 0xFFu
emilmont	60:3d0ef94e36ec	1696	#define MCM_PLAMC_AMC_SHIFT 0
emilmont	60:3d0ef94e36ec	1697	#define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x))<<MCM_PLAMC_AMC_SHIFT))&MCM_PLAMC_AMC_MASK)
emilmont	60:3d0ef94e36ec	1698	/* PLACR Bit Fields */
emilmont	60:3d0ef94e36ec	1699	#define MCM_PLACR_ARB_MASK 0x200u
emilmont	60:3d0ef94e36ec	1700	#define MCM_PLACR_ARB_SHIFT 9
emilmont	60:3d0ef94e36ec	1701	#define MCM_PLACR_CFCC_MASK 0x400u
emilmont	60:3d0ef94e36ec	1702	#define MCM_PLACR_CFCC_SHIFT 10
emilmont	60:3d0ef94e36ec	1703	#define MCM_PLACR_DFCDA_MASK 0x800u
emilmont	60:3d0ef94e36ec	1704	#define MCM_PLACR_DFCDA_SHIFT 11
emilmont	60:3d0ef94e36ec	1705	#define MCM_PLACR_DFCIC_MASK 0x1000u
emilmont	60:3d0ef94e36ec	1706	#define MCM_PLACR_DFCIC_SHIFT 12
emilmont	60:3d0ef94e36ec	1707	#define MCM_PLACR_DFCC_MASK 0x2000u
emilmont	60:3d0ef94e36ec	1708	#define MCM_PLACR_DFCC_SHIFT 13
emilmont	60:3d0ef94e36ec	1709	#define MCM_PLACR_EFDS_MASK 0x4000u
emilmont	60:3d0ef94e36ec	1710	#define MCM_PLACR_EFDS_SHIFT 14
emilmont	60:3d0ef94e36ec	1711	#define MCM_PLACR_DFCS_MASK 0x8000u
emilmont	60:3d0ef94e36ec	1712	#define MCM_PLACR_DFCS_SHIFT 15
emilmont	60:3d0ef94e36ec	1713	#define MCM_PLACR_ESFC_MASK 0x10000u
emilmont	60:3d0ef94e36ec	1714	#define MCM_PLACR_ESFC_SHIFT 16
emilmont	60:3d0ef94e36ec	1715	/* CPO Bit Fields */
emilmont	60:3d0ef94e36ec	1716	#define MCM_CPO_CPOREQ_MASK 0x1u
emilmont	60:3d0ef94e36ec	1717	#define MCM_CPO_CPOREQ_SHIFT 0
emilmont	60:3d0ef94e36ec	1718	#define MCM_CPO_CPOACK_MASK 0x2u
emilmont	60:3d0ef94e36ec	1719	#define MCM_CPO_CPOACK_SHIFT 1
emilmont	60:3d0ef94e36ec	1720	#define MCM_CPO_CPOWOI_MASK 0x4u
emilmont	60:3d0ef94e36ec	1721	#define MCM_CPO_CPOWOI_SHIFT 2
emilmont	60:3d0ef94e36ec	1722
emilmont	60:3d0ef94e36ec	1723	/**
emilmont	60:3d0ef94e36ec	1724	* @}
emilmont	60:3d0ef94e36ec	1725	/ / end of group MCM_Register_Masks */
emilmont	60:3d0ef94e36ec	1726
emilmont	60:3d0ef94e36ec	1727
emilmont	60:3d0ef94e36ec	1728	/* MCM - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	1729	/** Peripheral MCM base address */
emilmont	60:3d0ef94e36ec	1730	#define MCM_BASE (0xF0003000u)
emilmont	60:3d0ef94e36ec	1731	/** Peripheral MCM base pointer */
emilmont	60:3d0ef94e36ec	1732	#define MCM ((MCM_Type *)MCM_BASE)
emilmont	60:3d0ef94e36ec	1733	/** Array initializer of MCM peripheral base pointers */
emilmont	60:3d0ef94e36ec	1734	#define MCM_BASES { MCM }
emilmont	60:3d0ef94e36ec	1735
emilmont	60:3d0ef94e36ec	1736	/**
emilmont	60:3d0ef94e36ec	1737	* @}
emilmont	60:3d0ef94e36ec	1738	/ / end of group MCM_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	1739
emilmont	60:3d0ef94e36ec	1740
emilmont	60:3d0ef94e36ec	1741	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1742	-- MTB Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1743	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1744
emilmont	60:3d0ef94e36ec	1745	/**
emilmont	60:3d0ef94e36ec	1746	* @addtogroup MTB_Peripheral_Access_Layer MTB Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1747	* @{
emilmont	60:3d0ef94e36ec	1748	*/
emilmont	60:3d0ef94e36ec	1749
emilmont	60:3d0ef94e36ec	1750	/** MTB - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	1751	typedef struct {
emilmont	60:3d0ef94e36ec	1752	__IO uint32_t POSITION; /*< MTB Position Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	1753	__IO uint32_t MASTER; /*< MTB Master Register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	1754	__IO uint32_t FLOW; /*< MTB Flow Register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	1755	__I uint32_t BASE; /*< MTB Base Register, offset: 0xC /
emilmont	60:3d0ef94e36ec	1756	uint8_t RESERVED_0[3824];
emilmont	60:3d0ef94e36ec	1757	__I uint32_t MODECTRL; /*< Integration Mode Control Register, offset: 0xF00 /
emilmont	60:3d0ef94e36ec	1758	uint8_t RESERVED_1[156];
emilmont	60:3d0ef94e36ec	1759	__I uint32_t TAGSET; /*< Claim TAG Set Register, offset: 0xFA0 /
emilmont	60:3d0ef94e36ec	1760	__I uint32_t TAGCLEAR; /*< Claim TAG Clear Register, offset: 0xFA4 /
emilmont	60:3d0ef94e36ec	1761	uint8_t RESERVED_2[8];
emilmont	60:3d0ef94e36ec	1762	__I uint32_t LOCKACCESS; /*< Lock Access Register, offset: 0xFB0 /
emilmont	60:3d0ef94e36ec	1763	__I uint32_t LOCKSTAT; /*< Lock Status Register, offset: 0xFB4 /
emilmont	60:3d0ef94e36ec	1764	__I uint32_t AUTHSTAT; /*< Authentication Status Register, offset: 0xFB8 /
emilmont	60:3d0ef94e36ec	1765	__I uint32_t DEVICEARCH; /*< Device Architecture Register, offset: 0xFBC /
emilmont	60:3d0ef94e36ec	1766	uint8_t RESERVED_3[8];
emilmont	60:3d0ef94e36ec	1767	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
emilmont	60:3d0ef94e36ec	1768	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
emilmont	60:3d0ef94e36ec	1769	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
emilmont	60:3d0ef94e36ec	1770	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
emilmont	60:3d0ef94e36ec	1771	} MTB_Type;
emilmont	60:3d0ef94e36ec	1772
emilmont	60:3d0ef94e36ec	1773	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1774	-- MTB Register Masks
emilmont	60:3d0ef94e36ec	1775	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1776
emilmont	60:3d0ef94e36ec	1777	/**
emilmont	60:3d0ef94e36ec	1778	* @addtogroup MTB_Register_Masks MTB Register Masks
emilmont	60:3d0ef94e36ec	1779	* @{
emilmont	60:3d0ef94e36ec	1780	*/
emilmont	60:3d0ef94e36ec	1781
emilmont	60:3d0ef94e36ec	1782	/* POSITION Bit Fields */
emilmont	60:3d0ef94e36ec	1783	#define MTB_POSITION_WRAP_MASK 0x4u
emilmont	60:3d0ef94e36ec	1784	#define MTB_POSITION_WRAP_SHIFT 2
emilmont	60:3d0ef94e36ec	1785	#define MTB_POSITION_POINTER_MASK 0xFFFFFFF8u
emilmont	60:3d0ef94e36ec	1786	#define MTB_POSITION_POINTER_SHIFT 3
emilmont	60:3d0ef94e36ec	1787	#define MTB_POSITION_POINTER(x) (((uint32_t)(((uint32_t)(x))<<MTB_POSITION_POINTER_SHIFT))&MTB_POSITION_POINTER_MASK)
emilmont	60:3d0ef94e36ec	1788	/* MASTER Bit Fields */
emilmont	60:3d0ef94e36ec	1789	#define MTB_MASTER_MASK_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	1790	#define MTB_MASTER_MASK_SHIFT 0
emilmont	60:3d0ef94e36ec	1791	#define MTB_MASTER_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTB_MASTER_MASK_SHIFT))&MTB_MASTER_MASK_MASK)
emilmont	60:3d0ef94e36ec	1792	#define MTB_MASTER_TSTARTEN_MASK 0x20u
emilmont	60:3d0ef94e36ec	1793	#define MTB_MASTER_TSTARTEN_SHIFT 5
emilmont	60:3d0ef94e36ec	1794	#define MTB_MASTER_TSTOPEN_MASK 0x40u
emilmont	60:3d0ef94e36ec	1795	#define MTB_MASTER_TSTOPEN_SHIFT 6
emilmont	60:3d0ef94e36ec	1796	#define MTB_MASTER_SFRWPRIV_MASK 0x80u
emilmont	60:3d0ef94e36ec	1797	#define MTB_MASTER_SFRWPRIV_SHIFT 7
emilmont	60:3d0ef94e36ec	1798	#define MTB_MASTER_RAMPRIV_MASK 0x100u
emilmont	60:3d0ef94e36ec	1799	#define MTB_MASTER_RAMPRIV_SHIFT 8
emilmont	60:3d0ef94e36ec	1800	#define MTB_MASTER_HALTREQ_MASK 0x200u
emilmont	60:3d0ef94e36ec	1801	#define MTB_MASTER_HALTREQ_SHIFT 9
emilmont	60:3d0ef94e36ec	1802	#define MTB_MASTER_EN_MASK 0x80000000u
emilmont	60:3d0ef94e36ec	1803	#define MTB_MASTER_EN_SHIFT 31
emilmont	60:3d0ef94e36ec	1804	/* FLOW Bit Fields */
emilmont	60:3d0ef94e36ec	1805	#define MTB_FLOW_AUTOSTOP_MASK 0x1u
emilmont	60:3d0ef94e36ec	1806	#define MTB_FLOW_AUTOSTOP_SHIFT 0
emilmont	60:3d0ef94e36ec	1807	#define MTB_FLOW_AUTOHALT_MASK 0x2u
emilmont	60:3d0ef94e36ec	1808	#define MTB_FLOW_AUTOHALT_SHIFT 1
emilmont	60:3d0ef94e36ec	1809	#define MTB_FLOW_WATERMARK_MASK 0xFFFFFFF8u
emilmont	60:3d0ef94e36ec	1810	#define MTB_FLOW_WATERMARK_SHIFT 3
emilmont	60:3d0ef94e36ec	1811	#define MTB_FLOW_WATERMARK(x) (((uint32_t)(((uint32_t)(x))<<MTB_FLOW_WATERMARK_SHIFT))&MTB_FLOW_WATERMARK_MASK)
emilmont	60:3d0ef94e36ec	1812	/* BASE Bit Fields */
emilmont	60:3d0ef94e36ec	1813	#define MTB_BASE_BASEADDR_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1814	#define MTB_BASE_BASEADDR_SHIFT 0
emilmont	60:3d0ef94e36ec	1815	#define MTB_BASE_BASEADDR(x) (((uint32_t)(((uint32_t)(x))<<MTB_BASE_BASEADDR_SHIFT))&MTB_BASE_BASEADDR_MASK)
emilmont	60:3d0ef94e36ec	1816	/* MODECTRL Bit Fields */
emilmont	60:3d0ef94e36ec	1817	#define MTB_MODECTRL_MODECTRL_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1818	#define MTB_MODECTRL_MODECTRL_SHIFT 0
emilmont	60:3d0ef94e36ec	1819	#define MTB_MODECTRL_MODECTRL(x) (((uint32_t)(((uint32_t)(x))<<MTB_MODECTRL_MODECTRL_SHIFT))&MTB_MODECTRL_MODECTRL_MASK)
emilmont	60:3d0ef94e36ec	1820	/* TAGSET Bit Fields */
emilmont	60:3d0ef94e36ec	1821	#define MTB_TAGSET_TAGSET_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1822	#define MTB_TAGSET_TAGSET_SHIFT 0
emilmont	60:3d0ef94e36ec	1823	#define MTB_TAGSET_TAGSET(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGSET_TAGSET_SHIFT))&MTB_TAGSET_TAGSET_MASK)
emilmont	60:3d0ef94e36ec	1824	/* TAGCLEAR Bit Fields */
emilmont	60:3d0ef94e36ec	1825	#define MTB_TAGCLEAR_TAGCLEAR_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1826	#define MTB_TAGCLEAR_TAGCLEAR_SHIFT 0
emilmont	60:3d0ef94e36ec	1827	#define MTB_TAGCLEAR_TAGCLEAR(x) (((uint32_t)(((uint32_t)(x))<<MTB_TAGCLEAR_TAGCLEAR_SHIFT))&MTB_TAGCLEAR_TAGCLEAR_MASK)
emilmont	60:3d0ef94e36ec	1828	/* LOCKACCESS Bit Fields */
emilmont	60:3d0ef94e36ec	1829	#define MTB_LOCKACCESS_LOCKACCESS_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1830	#define MTB_LOCKACCESS_LOCKACCESS_SHIFT 0
emilmont	60:3d0ef94e36ec	1831	#define MTB_LOCKACCESS_LOCKACCESS(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKACCESS_LOCKACCESS_SHIFT))&MTB_LOCKACCESS_LOCKACCESS_MASK)
emilmont	60:3d0ef94e36ec	1832	/* LOCKSTAT Bit Fields */
emilmont	60:3d0ef94e36ec	1833	#define MTB_LOCKSTAT_LOCKSTAT_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1834	#define MTB_LOCKSTAT_LOCKSTAT_SHIFT 0
emilmont	60:3d0ef94e36ec	1835	#define MTB_LOCKSTAT_LOCKSTAT(x) (((uint32_t)(((uint32_t)(x))<<MTB_LOCKSTAT_LOCKSTAT_SHIFT))&MTB_LOCKSTAT_LOCKSTAT_MASK)
emilmont	60:3d0ef94e36ec	1836	/* AUTHSTAT Bit Fields */
emilmont	60:3d0ef94e36ec	1837	#define MTB_AUTHSTAT_BIT0_MASK 0x1u
emilmont	60:3d0ef94e36ec	1838	#define MTB_AUTHSTAT_BIT0_SHIFT 0
emilmont	60:3d0ef94e36ec	1839	#define MTB_AUTHSTAT_BIT1_MASK 0x2u
emilmont	60:3d0ef94e36ec	1840	#define MTB_AUTHSTAT_BIT1_SHIFT 1
emilmont	60:3d0ef94e36ec	1841	#define MTB_AUTHSTAT_BIT2_MASK 0x4u
emilmont	60:3d0ef94e36ec	1842	#define MTB_AUTHSTAT_BIT2_SHIFT 2
emilmont	60:3d0ef94e36ec	1843	#define MTB_AUTHSTAT_BIT3_MASK 0x8u
emilmont	60:3d0ef94e36ec	1844	#define MTB_AUTHSTAT_BIT3_SHIFT 3
emilmont	60:3d0ef94e36ec	1845	/* DEVICEARCH Bit Fields */
emilmont	60:3d0ef94e36ec	1846	#define MTB_DEVICEARCH_DEVICEARCH_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1847	#define MTB_DEVICEARCH_DEVICEARCH_SHIFT 0
emilmont	60:3d0ef94e36ec	1848	#define MTB_DEVICEARCH_DEVICEARCH(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICEARCH_DEVICEARCH_SHIFT))&MTB_DEVICEARCH_DEVICEARCH_MASK)
emilmont	60:3d0ef94e36ec	1849	/* DEVICECFG Bit Fields */
emilmont	60:3d0ef94e36ec	1850	#define MTB_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1851	#define MTB_DEVICECFG_DEVICECFG_SHIFT 0
emilmont	60:3d0ef94e36ec	1852	#define MTB_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICECFG_DEVICECFG_SHIFT))&MTB_DEVICECFG_DEVICECFG_MASK)
emilmont	60:3d0ef94e36ec	1853	/* DEVICETYPID Bit Fields */
emilmont	60:3d0ef94e36ec	1854	#define MTB_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1855	#define MTB_DEVICETYPID_DEVICETYPID_SHIFT 0
emilmont	60:3d0ef94e36ec	1856	#define MTB_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_DEVICETYPID_DEVICETYPID_SHIFT))&MTB_DEVICETYPID_DEVICETYPID_MASK)
emilmont	60:3d0ef94e36ec	1857	/* PERIPHID Bit Fields */
emilmont	60:3d0ef94e36ec	1858	#define MTB_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1859	#define MTB_PERIPHID_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	1860	#define MTB_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTB_PERIPHID_PERIPHID_SHIFT))&MTB_PERIPHID_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	1861	/* COMPID Bit Fields */
emilmont	60:3d0ef94e36ec	1862	#define MTB_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1863	#define MTB_COMPID_COMPID_SHIFT 0
emilmont	60:3d0ef94e36ec	1864	#define MTB_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTB_COMPID_COMPID_SHIFT))&MTB_COMPID_COMPID_MASK)
emilmont	60:3d0ef94e36ec	1865
emilmont	60:3d0ef94e36ec	1866	/**
emilmont	60:3d0ef94e36ec	1867	* @}
emilmont	60:3d0ef94e36ec	1868	/ / end of group MTB_Register_Masks */
emilmont	60:3d0ef94e36ec	1869
emilmont	60:3d0ef94e36ec	1870
emilmont	60:3d0ef94e36ec	1871	/* MTB - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	1872	/** Peripheral MTB base address */
emilmont	60:3d0ef94e36ec	1873	#define MTB_BASE (0xF0000000u)
emilmont	60:3d0ef94e36ec	1874	/** Peripheral MTB base pointer */
emilmont	60:3d0ef94e36ec	1875	#define MTB ((MTB_Type *)MTB_BASE)
emilmont	60:3d0ef94e36ec	1876	/** Array initializer of MTB peripheral base pointers */
emilmont	60:3d0ef94e36ec	1877	#define MTB_BASES { MTB }
emilmont	60:3d0ef94e36ec	1878
emilmont	60:3d0ef94e36ec	1879	/**
emilmont	60:3d0ef94e36ec	1880	* @}
emilmont	60:3d0ef94e36ec	1881	/ / end of group MTB_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	1882
emilmont	60:3d0ef94e36ec	1883
emilmont	60:3d0ef94e36ec	1884	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1885	-- MTBDWT Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1886	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1887
emilmont	60:3d0ef94e36ec	1888	/**
emilmont	60:3d0ef94e36ec	1889	* @addtogroup MTBDWT_Peripheral_Access_Layer MTBDWT Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1890	* @{
emilmont	60:3d0ef94e36ec	1891	*/
emilmont	60:3d0ef94e36ec	1892
emilmont	60:3d0ef94e36ec	1893	/** MTBDWT - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	1894	typedef struct {
emilmont	60:3d0ef94e36ec	1895	__I uint32_t CTRL; /*< MTB DWT Control Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	1896	uint8_t RESERVED_0[28];
emilmont	60:3d0ef94e36ec	1897	struct { /* offset: 0x20, array step: 0x10 */
emilmont	60:3d0ef94e36ec	1898	__IO uint32_t COMP; /*< MTB_DWT Comparator Register, array offset: 0x20, array step: 0x10 /
emilmont	60:3d0ef94e36ec	1899	__IO uint32_t MASK; /*< MTB_DWT Comparator Mask Register, array offset: 0x24, array step: 0x10 /
emilmont	60:3d0ef94e36ec	1900	__IO uint32_t FCT; /*< MTB_DWT Comparator Function Register 0..MTB_DWT Comparator Function Register 1, array offset: 0x28, array step: 0x10 /
emilmont	60:3d0ef94e36ec	1901	uint8_t RESERVED_0[4];
emilmont	60:3d0ef94e36ec	1902	} COMPARATOR[2];
emilmont	60:3d0ef94e36ec	1903	uint8_t RESERVED_1[448];
emilmont	60:3d0ef94e36ec	1904	__IO uint32_t TBCTRL; /*< MTB_DWT Trace Buffer Control Register, offset: 0x200 /
emilmont	60:3d0ef94e36ec	1905	uint8_t RESERVED_2[3524];
emilmont	60:3d0ef94e36ec	1906	__I uint32_t DEVICECFG; /*< Device Configuration Register, offset: 0xFC8 /
emilmont	60:3d0ef94e36ec	1907	__I uint32_t DEVICETYPID; /*< Device Type Identifier Register, offset: 0xFCC /
emilmont	60:3d0ef94e36ec	1908	__I uint32_t PERIPHID[8]; /*< Peripheral ID Register, array offset: 0xFD0, array step: 0x4 /
emilmont	60:3d0ef94e36ec	1909	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
emilmont	60:3d0ef94e36ec	1910	} MTBDWT_Type;
emilmont	60:3d0ef94e36ec	1911
emilmont	60:3d0ef94e36ec	1912	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1913	-- MTBDWT Register Masks
emilmont	60:3d0ef94e36ec	1914	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1915
emilmont	60:3d0ef94e36ec	1916	/**
emilmont	60:3d0ef94e36ec	1917	* @addtogroup MTBDWT_Register_Masks MTBDWT Register Masks
emilmont	60:3d0ef94e36ec	1918	* @{
emilmont	60:3d0ef94e36ec	1919	*/
emilmont	60:3d0ef94e36ec	1920
emilmont	60:3d0ef94e36ec	1921	/* CTRL Bit Fields */
emilmont	60:3d0ef94e36ec	1922	#define MTBDWT_CTRL_DWTCFGCTRL_MASK 0xFFFFFFFu
emilmont	60:3d0ef94e36ec	1923	#define MTBDWT_CTRL_DWTCFGCTRL_SHIFT 0
emilmont	60:3d0ef94e36ec	1924	#define MTBDWT_CTRL_DWTCFGCTRL(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_DWTCFGCTRL_SHIFT))&MTBDWT_CTRL_DWTCFGCTRL_MASK)
emilmont	60:3d0ef94e36ec	1925	#define MTBDWT_CTRL_NUMCMP_MASK 0xF0000000u
emilmont	60:3d0ef94e36ec	1926	#define MTBDWT_CTRL_NUMCMP_SHIFT 28
emilmont	60:3d0ef94e36ec	1927	#define MTBDWT_CTRL_NUMCMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_CTRL_NUMCMP_SHIFT))&MTBDWT_CTRL_NUMCMP_MASK)
emilmont	60:3d0ef94e36ec	1928	/* COMP Bit Fields */
emilmont	60:3d0ef94e36ec	1929	#define MTBDWT_COMP_COMP_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1930	#define MTBDWT_COMP_COMP_SHIFT 0
emilmont	60:3d0ef94e36ec	1931	#define MTBDWT_COMP_COMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMP_COMP_SHIFT))&MTBDWT_COMP_COMP_MASK)
emilmont	60:3d0ef94e36ec	1932	/* MASK Bit Fields */
emilmont	60:3d0ef94e36ec	1933	#define MTBDWT_MASK_MASK_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	1934	#define MTBDWT_MASK_MASK_SHIFT 0
emilmont	60:3d0ef94e36ec	1935	#define MTBDWT_MASK_MASK(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_MASK_MASK_SHIFT))&MTBDWT_MASK_MASK_MASK)
emilmont	60:3d0ef94e36ec	1936	/* FCT Bit Fields */
emilmont	60:3d0ef94e36ec	1937	#define MTBDWT_FCT_FUNCTION_MASK 0xFu
emilmont	60:3d0ef94e36ec	1938	#define MTBDWT_FCT_FUNCTION_SHIFT 0
emilmont	60:3d0ef94e36ec	1939	#define MTBDWT_FCT_FUNCTION(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_FUNCTION_SHIFT))&MTBDWT_FCT_FUNCTION_MASK)
emilmont	60:3d0ef94e36ec	1940	#define MTBDWT_FCT_DATAVMATCH_MASK 0x100u
emilmont	60:3d0ef94e36ec	1941	#define MTBDWT_FCT_DATAVMATCH_SHIFT 8
emilmont	60:3d0ef94e36ec	1942	#define MTBDWT_FCT_DATAVSIZE_MASK 0xC00u
emilmont	60:3d0ef94e36ec	1943	#define MTBDWT_FCT_DATAVSIZE_SHIFT 10
emilmont	60:3d0ef94e36ec	1944	#define MTBDWT_FCT_DATAVSIZE(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVSIZE_SHIFT))&MTBDWT_FCT_DATAVSIZE_MASK)
emilmont	60:3d0ef94e36ec	1945	#define MTBDWT_FCT_DATAVADDR0_MASK 0xF000u
emilmont	60:3d0ef94e36ec	1946	#define MTBDWT_FCT_DATAVADDR0_SHIFT 12
emilmont	60:3d0ef94e36ec	1947	#define MTBDWT_FCT_DATAVADDR0(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_FCT_DATAVADDR0_SHIFT))&MTBDWT_FCT_DATAVADDR0_MASK)
emilmont	60:3d0ef94e36ec	1948	#define MTBDWT_FCT_MATCHED_MASK 0x1000000u
emilmont	60:3d0ef94e36ec	1949	#define MTBDWT_FCT_MATCHED_SHIFT 24
emilmont	60:3d0ef94e36ec	1950	/* TBCTRL Bit Fields */
emilmont	60:3d0ef94e36ec	1951	#define MTBDWT_TBCTRL_ACOMP0_MASK 0x1u
emilmont	60:3d0ef94e36ec	1952	#define MTBDWT_TBCTRL_ACOMP0_SHIFT 0
emilmont	60:3d0ef94e36ec	1953	#define MTBDWT_TBCTRL_ACOMP1_MASK 0x2u
emilmont	60:3d0ef94e36ec	1954	#define MTBDWT_TBCTRL_ACOMP1_SHIFT 1
emilmont	60:3d0ef94e36ec	1955	#define MTBDWT_TBCTRL_NUMCOMP_MASK 0xF0000000u
emilmont	60:3d0ef94e36ec	1956	#define MTBDWT_TBCTRL_NUMCOMP_SHIFT 28
emilmont	60:3d0ef94e36ec	1957	#define MTBDWT_TBCTRL_NUMCOMP(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_TBCTRL_NUMCOMP_SHIFT))&MTBDWT_TBCTRL_NUMCOMP_MASK)
emilmont	60:3d0ef94e36ec	1958	/* DEVICECFG Bit Fields */
emilmont	60:3d0ef94e36ec	1959	#define MTBDWT_DEVICECFG_DEVICECFG_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1960	#define MTBDWT_DEVICECFG_DEVICECFG_SHIFT 0
emilmont	60:3d0ef94e36ec	1961	#define MTBDWT_DEVICECFG_DEVICECFG(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICECFG_DEVICECFG_SHIFT))&MTBDWT_DEVICECFG_DEVICECFG_MASK)
emilmont	60:3d0ef94e36ec	1962	/* DEVICETYPID Bit Fields */
emilmont	60:3d0ef94e36ec	1963	#define MTBDWT_DEVICETYPID_DEVICETYPID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1964	#define MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT 0
emilmont	60:3d0ef94e36ec	1965	#define MTBDWT_DEVICETYPID_DEVICETYPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_DEVICETYPID_DEVICETYPID_SHIFT))&MTBDWT_DEVICETYPID_DEVICETYPID_MASK)
emilmont	60:3d0ef94e36ec	1966	/* PERIPHID Bit Fields */
emilmont	60:3d0ef94e36ec	1967	#define MTBDWT_PERIPHID_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1968	#define MTBDWT_PERIPHID_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	1969	#define MTBDWT_PERIPHID_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_PERIPHID_PERIPHID_SHIFT))&MTBDWT_PERIPHID_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	1970	/* COMPID Bit Fields */
emilmont	60:3d0ef94e36ec	1971	#define MTBDWT_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	1972	#define MTBDWT_COMPID_COMPID_SHIFT 0
emilmont	60:3d0ef94e36ec	1973	#define MTBDWT_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<MTBDWT_COMPID_COMPID_SHIFT))&MTBDWT_COMPID_COMPID_MASK)
emilmont	60:3d0ef94e36ec	1974
emilmont	60:3d0ef94e36ec	1975	/**
emilmont	60:3d0ef94e36ec	1976	* @}
emilmont	60:3d0ef94e36ec	1977	/ / end of group MTBDWT_Register_Masks */
emilmont	60:3d0ef94e36ec	1978
emilmont	60:3d0ef94e36ec	1979
emilmont	60:3d0ef94e36ec	1980	/* MTBDWT - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	1981	/** Peripheral MTBDWT base address */
emilmont	60:3d0ef94e36ec	1982	#define MTBDWT_BASE (0xF0001000u)
emilmont	60:3d0ef94e36ec	1983	/** Peripheral MTBDWT base pointer */
emilmont	60:3d0ef94e36ec	1984	#define MTBDWT ((MTBDWT_Type *)MTBDWT_BASE)
emilmont	60:3d0ef94e36ec	1985	/** Array initializer of MTBDWT peripheral base pointers */
emilmont	60:3d0ef94e36ec	1986	#define MTBDWT_BASES { MTBDWT }
emilmont	60:3d0ef94e36ec	1987
emilmont	60:3d0ef94e36ec	1988	/**
emilmont	60:3d0ef94e36ec	1989	* @}
emilmont	60:3d0ef94e36ec	1990	/ / end of group MTBDWT_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	1991
emilmont	60:3d0ef94e36ec	1992
emilmont	60:3d0ef94e36ec	1993	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	1994	-- NV Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1995	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	1996
emilmont	60:3d0ef94e36ec	1997	/**
emilmont	60:3d0ef94e36ec	1998	* @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
emilmont	60:3d0ef94e36ec	1999	* @{
emilmont	60:3d0ef94e36ec	2000	*/
emilmont	60:3d0ef94e36ec	2001
emilmont	60:3d0ef94e36ec	2002	/** NV - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	2003	typedef struct {
emilmont	60:3d0ef94e36ec	2004	__I uint8_t BACKKEY3; /*< Backdoor Comparison Key 3., offset: 0x0 /
emilmont	60:3d0ef94e36ec	2005	__I uint8_t BACKKEY2; /*< Backdoor Comparison Key 2., offset: 0x1 /
emilmont	60:3d0ef94e36ec	2006	__I uint8_t BACKKEY1; /*< Backdoor Comparison Key 1., offset: 0x2 /
emilmont	60:3d0ef94e36ec	2007	__I uint8_t BACKKEY0; /*< Backdoor Comparison Key 0., offset: 0x3 /
emilmont	60:3d0ef94e36ec	2008	__I uint8_t BACKKEY7; /*< Backdoor Comparison Key 7., offset: 0x4 /
emilmont	60:3d0ef94e36ec	2009	__I uint8_t BACKKEY6; /*< Backdoor Comparison Key 6., offset: 0x5 /
emilmont	60:3d0ef94e36ec	2010	__I uint8_t BACKKEY5; /*< Backdoor Comparison Key 5., offset: 0x6 /
emilmont	60:3d0ef94e36ec	2011	__I uint8_t BACKKEY4; /*< Backdoor Comparison Key 4., offset: 0x7 /
emilmont	60:3d0ef94e36ec	2012	__I uint8_t FPROT3; /*< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	2013	__I uint8_t FPROT2; /*< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 /
emilmont	60:3d0ef94e36ec	2014	__I uint8_t FPROT1; /*< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA /
emilmont	60:3d0ef94e36ec	2015	__I uint8_t FPROT0; /*< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB /
emilmont	60:3d0ef94e36ec	2016	__I uint8_t FSEC; /*< Non-volatile Flash Security Register, offset: 0xC /
emilmont	60:3d0ef94e36ec	2017	__I uint8_t FOPT; /*< Non-volatile Flash Option Register, offset: 0xD /
emilmont	60:3d0ef94e36ec	2018	} NV_Type;
emilmont	60:3d0ef94e36ec	2019
emilmont	60:3d0ef94e36ec	2020	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2021	-- NV Register Masks
emilmont	60:3d0ef94e36ec	2022	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2023
emilmont	60:3d0ef94e36ec	2024	/**
emilmont	60:3d0ef94e36ec	2025	* @addtogroup NV_Register_Masks NV Register Masks
emilmont	60:3d0ef94e36ec	2026	* @{
emilmont	60:3d0ef94e36ec	2027	*/
emilmont	60:3d0ef94e36ec	2028
emilmont	60:3d0ef94e36ec	2029	/* BACKKEY3 Bit Fields */
emilmont	60:3d0ef94e36ec	2030	#define NV_BACKKEY3_KEY_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2031	#define NV_BACKKEY3_KEY_SHIFT 0
emilmont	60:3d0ef94e36ec	2032	#define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY3_KEY_SHIFT))&NV_BACKKEY3_KEY_MASK)
emilmont	60:3d0ef94e36ec	2033	/* BACKKEY2 Bit Fields */
emilmont	60:3d0ef94e36ec	2034	#define NV_BACKKEY2_KEY_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2035	#define NV_BACKKEY2_KEY_SHIFT 0
emilmont	60:3d0ef94e36ec	2036	#define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY2_KEY_SHIFT))&NV_BACKKEY2_KEY_MASK)
emilmont	60:3d0ef94e36ec	2037	/* BACKKEY1 Bit Fields */
emilmont	60:3d0ef94e36ec	2038	#define NV_BACKKEY1_KEY_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2039	#define NV_BACKKEY1_KEY_SHIFT 0
emilmont	60:3d0ef94e36ec	2040	#define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY1_KEY_SHIFT))&NV_BACKKEY1_KEY_MASK)
emilmont	60:3d0ef94e36ec	2041	/* BACKKEY0 Bit Fields */
emilmont	60:3d0ef94e36ec	2042	#define NV_BACKKEY0_KEY_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2043	#define NV_BACKKEY0_KEY_SHIFT 0
emilmont	60:3d0ef94e36ec	2044	#define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY0_KEY_SHIFT))&NV_BACKKEY0_KEY_MASK)
emilmont	60:3d0ef94e36ec	2045	/* BACKKEY7 Bit Fields */
emilmont	60:3d0ef94e36ec	2046	#define NV_BACKKEY7_KEY_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2047	#define NV_BACKKEY7_KEY_SHIFT 0
emilmont	60:3d0ef94e36ec	2048	#define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY7_KEY_SHIFT))&NV_BACKKEY7_KEY_MASK)
emilmont	60:3d0ef94e36ec	2049	/* BACKKEY6 Bit Fields */
emilmont	60:3d0ef94e36ec	2050	#define NV_BACKKEY6_KEY_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2051	#define NV_BACKKEY6_KEY_SHIFT 0
emilmont	60:3d0ef94e36ec	2052	#define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY6_KEY_SHIFT))&NV_BACKKEY6_KEY_MASK)
emilmont	60:3d0ef94e36ec	2053	/* BACKKEY5 Bit Fields */
emilmont	60:3d0ef94e36ec	2054	#define NV_BACKKEY5_KEY_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2055	#define NV_BACKKEY5_KEY_SHIFT 0
emilmont	60:3d0ef94e36ec	2056	#define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY5_KEY_SHIFT))&NV_BACKKEY5_KEY_MASK)
emilmont	60:3d0ef94e36ec	2057	/* BACKKEY4 Bit Fields */
emilmont	60:3d0ef94e36ec	2058	#define NV_BACKKEY4_KEY_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2059	#define NV_BACKKEY4_KEY_SHIFT 0
emilmont	60:3d0ef94e36ec	2060	#define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x))<<NV_BACKKEY4_KEY_SHIFT))&NV_BACKKEY4_KEY_MASK)
emilmont	60:3d0ef94e36ec	2061	/* FPROT3 Bit Fields */
emilmont	60:3d0ef94e36ec	2062	#define NV_FPROT3_PROT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2063	#define NV_FPROT3_PROT_SHIFT 0
emilmont	60:3d0ef94e36ec	2064	#define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT3_PROT_SHIFT))&NV_FPROT3_PROT_MASK)
emilmont	60:3d0ef94e36ec	2065	/* FPROT2 Bit Fields */
emilmont	60:3d0ef94e36ec	2066	#define NV_FPROT2_PROT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2067	#define NV_FPROT2_PROT_SHIFT 0
emilmont	60:3d0ef94e36ec	2068	#define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT2_PROT_SHIFT))&NV_FPROT2_PROT_MASK)
emilmont	60:3d0ef94e36ec	2069	/* FPROT1 Bit Fields */
emilmont	60:3d0ef94e36ec	2070	#define NV_FPROT1_PROT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2071	#define NV_FPROT1_PROT_SHIFT 0
emilmont	60:3d0ef94e36ec	2072	#define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT1_PROT_SHIFT))&NV_FPROT1_PROT_MASK)
emilmont	60:3d0ef94e36ec	2073	/* FPROT0 Bit Fields */
emilmont	60:3d0ef94e36ec	2074	#define NV_FPROT0_PROT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2075	#define NV_FPROT0_PROT_SHIFT 0
emilmont	60:3d0ef94e36ec	2076	#define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x))<<NV_FPROT0_PROT_SHIFT))&NV_FPROT0_PROT_MASK)
emilmont	60:3d0ef94e36ec	2077	/* FSEC Bit Fields */
emilmont	60:3d0ef94e36ec	2078	#define NV_FSEC_SEC_MASK 0x3u
emilmont	60:3d0ef94e36ec	2079	#define NV_FSEC_SEC_SHIFT 0
emilmont	60:3d0ef94e36ec	2080	#define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_SEC_SHIFT))&NV_FSEC_SEC_MASK)
emilmont	60:3d0ef94e36ec	2081	#define NV_FSEC_FSLACC_MASK 0xCu
emilmont	60:3d0ef94e36ec	2082	#define NV_FSEC_FSLACC_SHIFT 2
emilmont	60:3d0ef94e36ec	2083	#define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_FSLACC_SHIFT))&NV_FSEC_FSLACC_MASK)
emilmont	60:3d0ef94e36ec	2084	#define NV_FSEC_MEEN_MASK 0x30u
emilmont	60:3d0ef94e36ec	2085	#define NV_FSEC_MEEN_SHIFT 4
emilmont	60:3d0ef94e36ec	2086	#define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_MEEN_SHIFT))&NV_FSEC_MEEN_MASK)
emilmont	60:3d0ef94e36ec	2087	#define NV_FSEC_KEYEN_MASK 0xC0u
emilmont	60:3d0ef94e36ec	2088	#define NV_FSEC_KEYEN_SHIFT 6
emilmont	60:3d0ef94e36ec	2089	#define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x))<<NV_FSEC_KEYEN_SHIFT))&NV_FSEC_KEYEN_MASK)
emilmont	60:3d0ef94e36ec	2090	/* FOPT Bit Fields */
emilmont	60:3d0ef94e36ec	2091	#define NV_FOPT_LPBOOT0_MASK 0x1u
emilmont	60:3d0ef94e36ec	2092	#define NV_FOPT_LPBOOT0_SHIFT 0
emilmont	60:3d0ef94e36ec	2093	#define NV_FOPT_NMI_DIS_MASK 0x4u
emilmont	60:3d0ef94e36ec	2094	#define NV_FOPT_NMI_DIS_SHIFT 2
emilmont	60:3d0ef94e36ec	2095	#define NV_FOPT_RESET_PIN_CFG_MASK 0x8u
emilmont	60:3d0ef94e36ec	2096	#define NV_FOPT_RESET_PIN_CFG_SHIFT 3
emilmont	60:3d0ef94e36ec	2097	#define NV_FOPT_LPBOOT1_MASK 0x10u
emilmont	60:3d0ef94e36ec	2098	#define NV_FOPT_LPBOOT1_SHIFT 4
emilmont	60:3d0ef94e36ec	2099	#define NV_FOPT_FAST_INIT_MASK 0x20u
emilmont	60:3d0ef94e36ec	2100	#define NV_FOPT_FAST_INIT_SHIFT 5
emilmont	60:3d0ef94e36ec	2101
emilmont	60:3d0ef94e36ec	2102	/**
emilmont	60:3d0ef94e36ec	2103	* @}
emilmont	60:3d0ef94e36ec	2104	/ / end of group NV_Register_Masks */
emilmont	60:3d0ef94e36ec	2105
emilmont	60:3d0ef94e36ec	2106
emilmont	60:3d0ef94e36ec	2107	/* NV - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	2108	/** Peripheral FTFA_FlashConfig base address */
emilmont	60:3d0ef94e36ec	2109	#define FTFA_FlashConfig_BASE (0x400u)
emilmont	60:3d0ef94e36ec	2110	/** Peripheral FTFA_FlashConfig base pointer */
emilmont	60:3d0ef94e36ec	2111	#define FTFA_FlashConfig ((NV_Type *)FTFA_FlashConfig_BASE)
emilmont	60:3d0ef94e36ec	2112	/** Array initializer of NV peripheral base pointers */
emilmont	60:3d0ef94e36ec	2113	#define NV_BASES { FTFA_FlashConfig }
emilmont	60:3d0ef94e36ec	2114
emilmont	60:3d0ef94e36ec	2115	/**
emilmont	60:3d0ef94e36ec	2116	* @}
emilmont	60:3d0ef94e36ec	2117	/ / end of group NV_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	2118
emilmont	60:3d0ef94e36ec	2119
emilmont	60:3d0ef94e36ec	2120	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2121	-- OSC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2122	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2123
emilmont	60:3d0ef94e36ec	2124	/**
emilmont	60:3d0ef94e36ec	2125	* @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2126	* @{
emilmont	60:3d0ef94e36ec	2127	*/
emilmont	60:3d0ef94e36ec	2128
emilmont	60:3d0ef94e36ec	2129	/** OSC - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	2130	typedef struct {
emilmont	60:3d0ef94e36ec	2131	__IO uint8_t CR; /*< OSC Control Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	2132	} OSC_Type;
emilmont	60:3d0ef94e36ec	2133
emilmont	60:3d0ef94e36ec	2134	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2135	-- OSC Register Masks
emilmont	60:3d0ef94e36ec	2136	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2137
emilmont	60:3d0ef94e36ec	2138	/**
emilmont	60:3d0ef94e36ec	2139	* @addtogroup OSC_Register_Masks OSC Register Masks
emilmont	60:3d0ef94e36ec	2140	* @{
emilmont	60:3d0ef94e36ec	2141	*/
emilmont	60:3d0ef94e36ec	2142
emilmont	60:3d0ef94e36ec	2143	/* CR Bit Fields */
emilmont	60:3d0ef94e36ec	2144	#define OSC_CR_SC16P_MASK 0x1u
emilmont	60:3d0ef94e36ec	2145	#define OSC_CR_SC16P_SHIFT 0
emilmont	60:3d0ef94e36ec	2146	#define OSC_CR_SC8P_MASK 0x2u
emilmont	60:3d0ef94e36ec	2147	#define OSC_CR_SC8P_SHIFT 1
emilmont	60:3d0ef94e36ec	2148	#define OSC_CR_SC4P_MASK 0x4u
emilmont	60:3d0ef94e36ec	2149	#define OSC_CR_SC4P_SHIFT 2
emilmont	60:3d0ef94e36ec	2150	#define OSC_CR_SC2P_MASK 0x8u
emilmont	60:3d0ef94e36ec	2151	#define OSC_CR_SC2P_SHIFT 3
emilmont	60:3d0ef94e36ec	2152	#define OSC_CR_EREFSTEN_MASK 0x20u
emilmont	60:3d0ef94e36ec	2153	#define OSC_CR_EREFSTEN_SHIFT 5
emilmont	60:3d0ef94e36ec	2154	#define OSC_CR_ERCLKEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	2155	#define OSC_CR_ERCLKEN_SHIFT 7
emilmont	60:3d0ef94e36ec	2156
emilmont	60:3d0ef94e36ec	2157	/**
emilmont	60:3d0ef94e36ec	2158	* @}
emilmont	60:3d0ef94e36ec	2159	/ / end of group OSC_Register_Masks */
emilmont	60:3d0ef94e36ec	2160
emilmont	60:3d0ef94e36ec	2161
emilmont	60:3d0ef94e36ec	2162	/* OSC - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	2163	/** Peripheral OSC0 base address */
emilmont	60:3d0ef94e36ec	2164	#define OSC0_BASE (0x40065000u)
emilmont	60:3d0ef94e36ec	2165	/** Peripheral OSC0 base pointer */
emilmont	60:3d0ef94e36ec	2166	#define OSC0 ((OSC_Type *)OSC0_BASE)
emilmont	60:3d0ef94e36ec	2167	/** Array initializer of OSC peripheral base pointers */
emilmont	60:3d0ef94e36ec	2168	#define OSC_BASES { OSC0 }
emilmont	60:3d0ef94e36ec	2169
emilmont	60:3d0ef94e36ec	2170	/**
emilmont	60:3d0ef94e36ec	2171	* @}
emilmont	60:3d0ef94e36ec	2172	/ / end of group OSC_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	2173
emilmont	60:3d0ef94e36ec	2174
emilmont	60:3d0ef94e36ec	2175	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2176	-- PIT Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2177	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2178
emilmont	60:3d0ef94e36ec	2179	/**
emilmont	60:3d0ef94e36ec	2180	* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2181	* @{
emilmont	60:3d0ef94e36ec	2182	*/
emilmont	60:3d0ef94e36ec	2183
emilmont	60:3d0ef94e36ec	2184	/** PIT - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	2185	typedef struct {
emilmont	60:3d0ef94e36ec	2186	__IO uint32_t MCR; /*< PIT Module Control Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	2187	uint8_t RESERVED_0[220];
emilmont	60:3d0ef94e36ec	2188	__I uint32_t LTMR64H; /*< PIT Upper Lifetime Timer Register, offset: 0xE0 /
emilmont	60:3d0ef94e36ec	2189	__I uint32_t LTMR64L; /*< PIT Lower Lifetime Timer Register, offset: 0xE4 /
emilmont	60:3d0ef94e36ec	2190	uint8_t RESERVED_1[24];
emilmont	60:3d0ef94e36ec	2191	struct { /* offset: 0x100, array step: 0x10 */
emilmont	60:3d0ef94e36ec	2192	__IO uint32_t LDVAL; /*< Timer Load Value Register, array offset: 0x100, array step: 0x10 /
emilmont	60:3d0ef94e36ec	2193	__I uint32_t CVAL; /*< Current Timer Value Register, array offset: 0x104, array step: 0x10 /
emilmont	60:3d0ef94e36ec	2194	__IO uint32_t TCTRL; /*< Timer Control Register, array offset: 0x108, array step: 0x10 /
emilmont	60:3d0ef94e36ec	2195	__IO uint32_t TFLG; /*< Timer Flag Register, array offset: 0x10C, array step: 0x10 /
emilmont	60:3d0ef94e36ec	2196	} CHANNEL[2];
emilmont	60:3d0ef94e36ec	2197	} PIT_Type;
emilmont	60:3d0ef94e36ec	2198
emilmont	60:3d0ef94e36ec	2199	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2200	-- PIT Register Masks
emilmont	60:3d0ef94e36ec	2201	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2202
emilmont	60:3d0ef94e36ec	2203	/**
emilmont	60:3d0ef94e36ec	2204	* @addtogroup PIT_Register_Masks PIT Register Masks
emilmont	60:3d0ef94e36ec	2205	* @{
emilmont	60:3d0ef94e36ec	2206	*/
emilmont	60:3d0ef94e36ec	2207
emilmont	60:3d0ef94e36ec	2208	/* MCR Bit Fields */
emilmont	60:3d0ef94e36ec	2209	#define PIT_MCR_FRZ_MASK 0x1u
emilmont	60:3d0ef94e36ec	2210	#define PIT_MCR_FRZ_SHIFT 0
emilmont	60:3d0ef94e36ec	2211	#define PIT_MCR_MDIS_MASK 0x2u
emilmont	60:3d0ef94e36ec	2212	#define PIT_MCR_MDIS_SHIFT 1
emilmont	60:3d0ef94e36ec	2213	/* LTMR64H Bit Fields */
emilmont	60:3d0ef94e36ec	2214	#define PIT_LTMR64H_LTH_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2215	#define PIT_LTMR64H_LTH_SHIFT 0
emilmont	60:3d0ef94e36ec	2216	#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64H_LTH_SHIFT))&PIT_LTMR64H_LTH_MASK)
emilmont	60:3d0ef94e36ec	2217	/* LTMR64L Bit Fields */
emilmont	60:3d0ef94e36ec	2218	#define PIT_LTMR64L_LTL_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2219	#define PIT_LTMR64L_LTL_SHIFT 0
emilmont	60:3d0ef94e36ec	2220	#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x))<<PIT_LTMR64L_LTL_SHIFT))&PIT_LTMR64L_LTL_MASK)
emilmont	60:3d0ef94e36ec	2221	/* LDVAL Bit Fields */
emilmont	60:3d0ef94e36ec	2222	#define PIT_LDVAL_TSV_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2223	#define PIT_LDVAL_TSV_SHIFT 0
emilmont	60:3d0ef94e36ec	2224	#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x))<<PIT_LDVAL_TSV_SHIFT))&PIT_LDVAL_TSV_MASK)
emilmont	60:3d0ef94e36ec	2225	/* CVAL Bit Fields */
emilmont	60:3d0ef94e36ec	2226	#define PIT_CVAL_TVL_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2227	#define PIT_CVAL_TVL_SHIFT 0
emilmont	60:3d0ef94e36ec	2228	#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x))<<PIT_CVAL_TVL_SHIFT))&PIT_CVAL_TVL_MASK)
emilmont	60:3d0ef94e36ec	2229	/* TCTRL Bit Fields */
emilmont	60:3d0ef94e36ec	2230	#define PIT_TCTRL_TEN_MASK 0x1u
emilmont	60:3d0ef94e36ec	2231	#define PIT_TCTRL_TEN_SHIFT 0
emilmont	60:3d0ef94e36ec	2232	#define PIT_TCTRL_TIE_MASK 0x2u
emilmont	60:3d0ef94e36ec	2233	#define PIT_TCTRL_TIE_SHIFT 1
emilmont	60:3d0ef94e36ec	2234	#define PIT_TCTRL_CHN_MASK 0x4u
emilmont	60:3d0ef94e36ec	2235	#define PIT_TCTRL_CHN_SHIFT 2
emilmont	60:3d0ef94e36ec	2236	/* TFLG Bit Fields */
emilmont	60:3d0ef94e36ec	2237	#define PIT_TFLG_TIF_MASK 0x1u
emilmont	60:3d0ef94e36ec	2238	#define PIT_TFLG_TIF_SHIFT 0
emilmont	60:3d0ef94e36ec	2239
emilmont	60:3d0ef94e36ec	2240	/**
emilmont	60:3d0ef94e36ec	2241	* @}
emilmont	60:3d0ef94e36ec	2242	/ / end of group PIT_Register_Masks */
emilmont	60:3d0ef94e36ec	2243
emilmont	60:3d0ef94e36ec	2244
emilmont	60:3d0ef94e36ec	2245	/* PIT - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	2246	/** Peripheral PIT base address */
emilmont	60:3d0ef94e36ec	2247	#define PIT_BASE (0x40037000u)
emilmont	60:3d0ef94e36ec	2248	/** Peripheral PIT base pointer */
emilmont	60:3d0ef94e36ec	2249	#define PIT ((PIT_Type *)PIT_BASE)
emilmont	60:3d0ef94e36ec	2250	/** Array initializer of PIT peripheral base pointers */
emilmont	60:3d0ef94e36ec	2251	#define PIT_BASES { PIT }
emilmont	60:3d0ef94e36ec	2252
emilmont	60:3d0ef94e36ec	2253	/**
emilmont	60:3d0ef94e36ec	2254	* @}
emilmont	60:3d0ef94e36ec	2255	/ / end of group PIT_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	2256
emilmont	60:3d0ef94e36ec	2257
emilmont	60:3d0ef94e36ec	2258	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2259	-- PMC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2260	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2261
emilmont	60:3d0ef94e36ec	2262	/**
emilmont	60:3d0ef94e36ec	2263	* @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2264	* @{
emilmont	60:3d0ef94e36ec	2265	*/
emilmont	60:3d0ef94e36ec	2266
emilmont	60:3d0ef94e36ec	2267	/** PMC - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	2268	typedef struct {
emilmont	60:3d0ef94e36ec	2269	__IO uint8_t LVDSC1; /*< Low Voltage Detect Status And Control 1 register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	2270	__IO uint8_t LVDSC2; /*< Low Voltage Detect Status And Control 2 register, offset: 0x1 /
emilmont	60:3d0ef94e36ec	2271	__IO uint8_t REGSC; /*< Regulator Status And Control register, offset: 0x2 /
emilmont	60:3d0ef94e36ec	2272	} PMC_Type;
emilmont	60:3d0ef94e36ec	2273
emilmont	60:3d0ef94e36ec	2274	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2275	-- PMC Register Masks
emilmont	60:3d0ef94e36ec	2276	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2277
emilmont	60:3d0ef94e36ec	2278	/**
emilmont	60:3d0ef94e36ec	2279	* @addtogroup PMC_Register_Masks PMC Register Masks
emilmont	60:3d0ef94e36ec	2280	* @{
emilmont	60:3d0ef94e36ec	2281	*/
emilmont	60:3d0ef94e36ec	2282
emilmont	60:3d0ef94e36ec	2283	/* LVDSC1 Bit Fields */
emilmont	60:3d0ef94e36ec	2284	#define PMC_LVDSC1_LVDV_MASK 0x3u
emilmont	60:3d0ef94e36ec	2285	#define PMC_LVDSC1_LVDV_SHIFT 0
emilmont	60:3d0ef94e36ec	2286	#define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC1_LVDV_SHIFT))&PMC_LVDSC1_LVDV_MASK)
emilmont	60:3d0ef94e36ec	2287	#define PMC_LVDSC1_LVDRE_MASK 0x10u
emilmont	60:3d0ef94e36ec	2288	#define PMC_LVDSC1_LVDRE_SHIFT 4
emilmont	60:3d0ef94e36ec	2289	#define PMC_LVDSC1_LVDIE_MASK 0x20u
emilmont	60:3d0ef94e36ec	2290	#define PMC_LVDSC1_LVDIE_SHIFT 5
emilmont	60:3d0ef94e36ec	2291	#define PMC_LVDSC1_LVDACK_MASK 0x40u
emilmont	60:3d0ef94e36ec	2292	#define PMC_LVDSC1_LVDACK_SHIFT 6
emilmont	60:3d0ef94e36ec	2293	#define PMC_LVDSC1_LVDF_MASK 0x80u
emilmont	60:3d0ef94e36ec	2294	#define PMC_LVDSC1_LVDF_SHIFT 7
emilmont	60:3d0ef94e36ec	2295	/* LVDSC2 Bit Fields */
emilmont	60:3d0ef94e36ec	2296	#define PMC_LVDSC2_LVWV_MASK 0x3u
emilmont	60:3d0ef94e36ec	2297	#define PMC_LVDSC2_LVWV_SHIFT 0
emilmont	60:3d0ef94e36ec	2298	#define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x))<<PMC_LVDSC2_LVWV_SHIFT))&PMC_LVDSC2_LVWV_MASK)
emilmont	60:3d0ef94e36ec	2299	#define PMC_LVDSC2_LVWIE_MASK 0x20u
emilmont	60:3d0ef94e36ec	2300	#define PMC_LVDSC2_LVWIE_SHIFT 5
emilmont	60:3d0ef94e36ec	2301	#define PMC_LVDSC2_LVWACK_MASK 0x40u
emilmont	60:3d0ef94e36ec	2302	#define PMC_LVDSC2_LVWACK_SHIFT 6
emilmont	60:3d0ef94e36ec	2303	#define PMC_LVDSC2_LVWF_MASK 0x80u
emilmont	60:3d0ef94e36ec	2304	#define PMC_LVDSC2_LVWF_SHIFT 7
emilmont	60:3d0ef94e36ec	2305	/* REGSC Bit Fields */
emilmont	60:3d0ef94e36ec	2306	#define PMC_REGSC_BGBE_MASK 0x1u
emilmont	60:3d0ef94e36ec	2307	#define PMC_REGSC_BGBE_SHIFT 0
emilmont	60:3d0ef94e36ec	2308	#define PMC_REGSC_REGONS_MASK 0x4u
emilmont	60:3d0ef94e36ec	2309	#define PMC_REGSC_REGONS_SHIFT 2
emilmont	60:3d0ef94e36ec	2310	#define PMC_REGSC_ACKISO_MASK 0x8u
emilmont	60:3d0ef94e36ec	2311	#define PMC_REGSC_ACKISO_SHIFT 3
emilmont	60:3d0ef94e36ec	2312	#define PMC_REGSC_BGEN_MASK 0x10u
emilmont	60:3d0ef94e36ec	2313	#define PMC_REGSC_BGEN_SHIFT 4
emilmont	60:3d0ef94e36ec	2314
emilmont	60:3d0ef94e36ec	2315	/**
emilmont	60:3d0ef94e36ec	2316	* @}
emilmont	60:3d0ef94e36ec	2317	/ / end of group PMC_Register_Masks */
emilmont	60:3d0ef94e36ec	2318
emilmont	60:3d0ef94e36ec	2319
emilmont	60:3d0ef94e36ec	2320	/* PMC - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	2321	/** Peripheral PMC base address */
emilmont	60:3d0ef94e36ec	2322	#define PMC_BASE (0x4007D000u)
emilmont	60:3d0ef94e36ec	2323	/** Peripheral PMC base pointer */
emilmont	60:3d0ef94e36ec	2324	#define PMC ((PMC_Type *)PMC_BASE)
emilmont	60:3d0ef94e36ec	2325	/** Array initializer of PMC peripheral base pointers */
emilmont	60:3d0ef94e36ec	2326	#define PMC_BASES { PMC }
emilmont	60:3d0ef94e36ec	2327
emilmont	60:3d0ef94e36ec	2328	/**
emilmont	60:3d0ef94e36ec	2329	* @}
emilmont	60:3d0ef94e36ec	2330	/ / end of group PMC_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	2331
emilmont	60:3d0ef94e36ec	2332
emilmont	60:3d0ef94e36ec	2333	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2334	-- PORT Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2335	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2336
emilmont	60:3d0ef94e36ec	2337	/**
emilmont	60:3d0ef94e36ec	2338	* @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2339	* @{
emilmont	60:3d0ef94e36ec	2340	*/
emilmont	60:3d0ef94e36ec	2341
emilmont	60:3d0ef94e36ec	2342	/** PORT - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	2343	typedef struct {
emilmont	60:3d0ef94e36ec	2344	__IO uint32_t PCR[32]; /*< Pin Control Register n, array offset: 0x0, array step: 0x4 /
emilmont	60:3d0ef94e36ec	2345	__O uint32_t GPCLR; /*< Global Pin Control Low Register, offset: 0x80 /
emilmont	60:3d0ef94e36ec	2346	__O uint32_t GPCHR; /*< Global Pin Control High Register, offset: 0x84 /
emilmont	60:3d0ef94e36ec	2347	uint8_t RESERVED_0[24];
emilmont	60:3d0ef94e36ec	2348	__IO uint32_t ISFR; /*< Interrupt Status Flag Register, offset: 0xA0 /
emilmont	60:3d0ef94e36ec	2349	} PORT_Type;
emilmont	60:3d0ef94e36ec	2350
emilmont	60:3d0ef94e36ec	2351	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2352	-- PORT Register Masks
emilmont	60:3d0ef94e36ec	2353	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2354
emilmont	60:3d0ef94e36ec	2355	/**
emilmont	60:3d0ef94e36ec	2356	* @addtogroup PORT_Register_Masks PORT Register Masks
emilmont	60:3d0ef94e36ec	2357	* @{
emilmont	60:3d0ef94e36ec	2358	*/
emilmont	60:3d0ef94e36ec	2359
emilmont	60:3d0ef94e36ec	2360	/* PCR Bit Fields */
emilmont	60:3d0ef94e36ec	2361	#define PORT_PCR_PS_MASK 0x1u
emilmont	60:3d0ef94e36ec	2362	#define PORT_PCR_PS_SHIFT 0
emilmont	60:3d0ef94e36ec	2363	#define PORT_PCR_PE_MASK 0x2u
emilmont	60:3d0ef94e36ec	2364	#define PORT_PCR_PE_SHIFT 1
emilmont	60:3d0ef94e36ec	2365	#define PORT_PCR_SRE_MASK 0x4u
emilmont	60:3d0ef94e36ec	2366	#define PORT_PCR_SRE_SHIFT 2
emilmont	60:3d0ef94e36ec	2367	#define PORT_PCR_PFE_MASK 0x10u
emilmont	60:3d0ef94e36ec	2368	#define PORT_PCR_PFE_SHIFT 4
emilmont	60:3d0ef94e36ec	2369	#define PORT_PCR_DSE_MASK 0x40u
emilmont	60:3d0ef94e36ec	2370	#define PORT_PCR_DSE_SHIFT 6
emilmont	60:3d0ef94e36ec	2371	#define PORT_PCR_MUX_MASK 0x700u
emilmont	60:3d0ef94e36ec	2372	#define PORT_PCR_MUX_SHIFT 8
emilmont	60:3d0ef94e36ec	2373	#define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_MUX_SHIFT))&PORT_PCR_MUX_MASK)
emilmont	60:3d0ef94e36ec	2374	#define PORT_PCR_IRQC_MASK 0xF0000u
emilmont	60:3d0ef94e36ec	2375	#define PORT_PCR_IRQC_SHIFT 16
emilmont	60:3d0ef94e36ec	2376	#define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x))<<PORT_PCR_IRQC_SHIFT))&PORT_PCR_IRQC_MASK)
emilmont	60:3d0ef94e36ec	2377	#define PORT_PCR_ISF_MASK 0x1000000u
emilmont	60:3d0ef94e36ec	2378	#define PORT_PCR_ISF_SHIFT 24
emilmont	60:3d0ef94e36ec	2379	/* GPCLR Bit Fields */
emilmont	60:3d0ef94e36ec	2380	#define PORT_GPCLR_GPWD_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	2381	#define PORT_GPCLR_GPWD_SHIFT 0
emilmont	60:3d0ef94e36ec	2382	#define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWD_SHIFT))&PORT_GPCLR_GPWD_MASK)
emilmont	60:3d0ef94e36ec	2383	#define PORT_GPCLR_GPWE_MASK 0xFFFF0000u
emilmont	60:3d0ef94e36ec	2384	#define PORT_GPCLR_GPWE_SHIFT 16
emilmont	60:3d0ef94e36ec	2385	#define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCLR_GPWE_SHIFT))&PORT_GPCLR_GPWE_MASK)
emilmont	60:3d0ef94e36ec	2386	/* GPCHR Bit Fields */
emilmont	60:3d0ef94e36ec	2387	#define PORT_GPCHR_GPWD_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	2388	#define PORT_GPCHR_GPWD_SHIFT 0
emilmont	60:3d0ef94e36ec	2389	#define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWD_SHIFT))&PORT_GPCHR_GPWD_MASK)
emilmont	60:3d0ef94e36ec	2390	#define PORT_GPCHR_GPWE_MASK 0xFFFF0000u
emilmont	60:3d0ef94e36ec	2391	#define PORT_GPCHR_GPWE_SHIFT 16
emilmont	60:3d0ef94e36ec	2392	#define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x))<<PORT_GPCHR_GPWE_SHIFT))&PORT_GPCHR_GPWE_MASK)
emilmont	60:3d0ef94e36ec	2393	/* ISFR Bit Fields */
emilmont	60:3d0ef94e36ec	2394	#define PORT_ISFR_ISF_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2395	#define PORT_ISFR_ISF_SHIFT 0
emilmont	60:3d0ef94e36ec	2396	#define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x))<<PORT_ISFR_ISF_SHIFT))&PORT_ISFR_ISF_MASK)
emilmont	60:3d0ef94e36ec	2397
emilmont	60:3d0ef94e36ec	2398	/**
emilmont	60:3d0ef94e36ec	2399	* @}
emilmont	60:3d0ef94e36ec	2400	/ / end of group PORT_Register_Masks */
emilmont	60:3d0ef94e36ec	2401
emilmont	60:3d0ef94e36ec	2402
emilmont	60:3d0ef94e36ec	2403	/* PORT - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	2404	/** Peripheral PORTA base address */
emilmont	60:3d0ef94e36ec	2405	#define PORTA_BASE (0x40049000u)
emilmont	60:3d0ef94e36ec	2406	/** Peripheral PORTA base pointer */
emilmont	60:3d0ef94e36ec	2407	#define PORTA ((PORT_Type *)PORTA_BASE)
emilmont	60:3d0ef94e36ec	2408	/** Peripheral PORTB base address */
emilmont	60:3d0ef94e36ec	2409	#define PORTB_BASE (0x4004A000u)
emilmont	60:3d0ef94e36ec	2410	/** Peripheral PORTB base pointer */
emilmont	60:3d0ef94e36ec	2411	#define PORTB ((PORT_Type *)PORTB_BASE)
emilmont	60:3d0ef94e36ec	2412	/** Peripheral PORTC base address */
emilmont	60:3d0ef94e36ec	2413	#define PORTC_BASE (0x4004B000u)
emilmont	60:3d0ef94e36ec	2414	/** Peripheral PORTC base pointer */
emilmont	60:3d0ef94e36ec	2415	#define PORTC ((PORT_Type *)PORTC_BASE)
emilmont	60:3d0ef94e36ec	2416	/** Peripheral PORTD base address */
emilmont	60:3d0ef94e36ec	2417	#define PORTD_BASE (0x4004C000u)
emilmont	60:3d0ef94e36ec	2418	/** Peripheral PORTD base pointer */
emilmont	60:3d0ef94e36ec	2419	#define PORTD ((PORT_Type *)PORTD_BASE)
emilmont	60:3d0ef94e36ec	2420	/** Peripheral PORTE base address */
emilmont	60:3d0ef94e36ec	2421	#define PORTE_BASE (0x4004D000u)
emilmont	60:3d0ef94e36ec	2422	/** Peripheral PORTE base pointer */
emilmont	60:3d0ef94e36ec	2423	#define PORTE ((PORT_Type *)PORTE_BASE)
emilmont	60:3d0ef94e36ec	2424	/** Array initializer of PORT peripheral base pointers */
emilmont	60:3d0ef94e36ec	2425	#define PORT_BASES { PORTA, PORTB, PORTC, PORTD, PORTE }
emilmont	60:3d0ef94e36ec	2426
emilmont	60:3d0ef94e36ec	2427	/**
emilmont	60:3d0ef94e36ec	2428	* @}
emilmont	60:3d0ef94e36ec	2429	/ / end of group PORT_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	2430
emilmont	60:3d0ef94e36ec	2431
emilmont	60:3d0ef94e36ec	2432	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2433	-- RCM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2434	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2435
emilmont	60:3d0ef94e36ec	2436	/**
emilmont	60:3d0ef94e36ec	2437	* @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2438	* @{
emilmont	60:3d0ef94e36ec	2439	*/
emilmont	60:3d0ef94e36ec	2440
emilmont	60:3d0ef94e36ec	2441	/** RCM - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	2442	typedef struct {
emilmont	60:3d0ef94e36ec	2443	__I uint8_t SRS0; /*< System Reset Status Register 0, offset: 0x0 /
emilmont	60:3d0ef94e36ec	2444	__I uint8_t SRS1; /*< System Reset Status Register 1, offset: 0x1 /
emilmont	60:3d0ef94e36ec	2445	uint8_t RESERVED_0[2];
emilmont	60:3d0ef94e36ec	2446	__IO uint8_t RPFC; /*< Reset Pin Filter Control register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	2447	__IO uint8_t RPFW; /*< Reset Pin Filter Width register, offset: 0x5 /
emilmont	60:3d0ef94e36ec	2448	} RCM_Type;
emilmont	60:3d0ef94e36ec	2449
emilmont	60:3d0ef94e36ec	2450	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2451	-- RCM Register Masks
emilmont	60:3d0ef94e36ec	2452	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2453
emilmont	60:3d0ef94e36ec	2454	/**
emilmont	60:3d0ef94e36ec	2455	* @addtogroup RCM_Register_Masks RCM Register Masks
emilmont	60:3d0ef94e36ec	2456	* @{
emilmont	60:3d0ef94e36ec	2457	*/
emilmont	60:3d0ef94e36ec	2458
emilmont	60:3d0ef94e36ec	2459	/* SRS0 Bit Fields */
emilmont	60:3d0ef94e36ec	2460	#define RCM_SRS0_WAKEUP_MASK 0x1u
emilmont	60:3d0ef94e36ec	2461	#define RCM_SRS0_WAKEUP_SHIFT 0
emilmont	60:3d0ef94e36ec	2462	#define RCM_SRS0_LVD_MASK 0x2u
emilmont	60:3d0ef94e36ec	2463	#define RCM_SRS0_LVD_SHIFT 1
emilmont	60:3d0ef94e36ec	2464	#define RCM_SRS0_LOC_MASK 0x4u
emilmont	60:3d0ef94e36ec	2465	#define RCM_SRS0_LOC_SHIFT 2
emilmont	60:3d0ef94e36ec	2466	#define RCM_SRS0_LOL_MASK 0x8u
emilmont	60:3d0ef94e36ec	2467	#define RCM_SRS0_LOL_SHIFT 3
emilmont	60:3d0ef94e36ec	2468	#define RCM_SRS0_WDOG_MASK 0x20u
emilmont	60:3d0ef94e36ec	2469	#define RCM_SRS0_WDOG_SHIFT 5
emilmont	60:3d0ef94e36ec	2470	#define RCM_SRS0_PIN_MASK 0x40u
emilmont	60:3d0ef94e36ec	2471	#define RCM_SRS0_PIN_SHIFT 6
emilmont	60:3d0ef94e36ec	2472	#define RCM_SRS0_POR_MASK 0x80u
emilmont	60:3d0ef94e36ec	2473	#define RCM_SRS0_POR_SHIFT 7
emilmont	60:3d0ef94e36ec	2474	/* SRS1 Bit Fields */
emilmont	60:3d0ef94e36ec	2475	#define RCM_SRS1_LOCKUP_MASK 0x2u
emilmont	60:3d0ef94e36ec	2476	#define RCM_SRS1_LOCKUP_SHIFT 1
emilmont	60:3d0ef94e36ec	2477	#define RCM_SRS1_SW_MASK 0x4u
emilmont	60:3d0ef94e36ec	2478	#define RCM_SRS1_SW_SHIFT 2
emilmont	60:3d0ef94e36ec	2479	#define RCM_SRS1_MDM_AP_MASK 0x8u
emilmont	60:3d0ef94e36ec	2480	#define RCM_SRS1_MDM_AP_SHIFT 3
emilmont	60:3d0ef94e36ec	2481	#define RCM_SRS1_SACKERR_MASK 0x20u
emilmont	60:3d0ef94e36ec	2482	#define RCM_SRS1_SACKERR_SHIFT 5
emilmont	60:3d0ef94e36ec	2483	/* RPFC Bit Fields */
emilmont	60:3d0ef94e36ec	2484	#define RCM_RPFC_RSTFLTSRW_MASK 0x3u
emilmont	60:3d0ef94e36ec	2485	#define RCM_RPFC_RSTFLTSRW_SHIFT 0
emilmont	60:3d0ef94e36ec	2486	#define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFC_RSTFLTSRW_SHIFT))&RCM_RPFC_RSTFLTSRW_MASK)
emilmont	60:3d0ef94e36ec	2487	#define RCM_RPFC_RSTFLTSS_MASK 0x4u
emilmont	60:3d0ef94e36ec	2488	#define RCM_RPFC_RSTFLTSS_SHIFT 2
emilmont	60:3d0ef94e36ec	2489	/* RPFW Bit Fields */
emilmont	60:3d0ef94e36ec	2490	#define RCM_RPFW_RSTFLTSEL_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	2491	#define RCM_RPFW_RSTFLTSEL_SHIFT 0
emilmont	60:3d0ef94e36ec	2492	#define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x))<<RCM_RPFW_RSTFLTSEL_SHIFT))&RCM_RPFW_RSTFLTSEL_MASK)
emilmont	60:3d0ef94e36ec	2493
emilmont	60:3d0ef94e36ec	2494	/**
emilmont	60:3d0ef94e36ec	2495	* @}
emilmont	60:3d0ef94e36ec	2496	/ / end of group RCM_Register_Masks */
emilmont	60:3d0ef94e36ec	2497
emilmont	60:3d0ef94e36ec	2498
emilmont	60:3d0ef94e36ec	2499	/* RCM - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	2500	/** Peripheral RCM base address */
emilmont	60:3d0ef94e36ec	2501	#define RCM_BASE (0x4007F000u)
emilmont	60:3d0ef94e36ec	2502	/** Peripheral RCM base pointer */
emilmont	60:3d0ef94e36ec	2503	#define RCM ((RCM_Type *)RCM_BASE)
emilmont	60:3d0ef94e36ec	2504	/** Array initializer of RCM peripheral base pointers */
emilmont	60:3d0ef94e36ec	2505	#define RCM_BASES { RCM }
emilmont	60:3d0ef94e36ec	2506
emilmont	60:3d0ef94e36ec	2507	/**
emilmont	60:3d0ef94e36ec	2508	* @}
emilmont	60:3d0ef94e36ec	2509	/ / end of group RCM_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	2510
emilmont	60:3d0ef94e36ec	2511
emilmont	60:3d0ef94e36ec	2512	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2513	-- ROM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2514	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2515
emilmont	60:3d0ef94e36ec	2516	/**
emilmont	60:3d0ef94e36ec	2517	* @addtogroup ROM_Peripheral_Access_Layer ROM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2518	* @{
emilmont	60:3d0ef94e36ec	2519	*/
emilmont	60:3d0ef94e36ec	2520
emilmont	60:3d0ef94e36ec	2521	/** ROM - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	2522	typedef struct {
emilmont	60:3d0ef94e36ec	2523	__I uint32_t ENTRY[3]; /*< Entry, array offset: 0x0, array step: 0x4 /
emilmont	60:3d0ef94e36ec	2524	__I uint32_t TABLEMARK; /*< End of Table Marker Register, offset: 0xC /
emilmont	60:3d0ef94e36ec	2525	uint8_t RESERVED_0[4028];
emilmont	60:3d0ef94e36ec	2526	__I uint32_t SYSACCESS; /*< System Access Register, offset: 0xFCC /
emilmont	60:3d0ef94e36ec	2527	__I uint32_t PERIPHID4; /*< Peripheral ID Register, offset: 0xFD0 /
emilmont	60:3d0ef94e36ec	2528	__I uint32_t PERIPHID5; /*< Peripheral ID Register, offset: 0xFD4 /
emilmont	60:3d0ef94e36ec	2529	__I uint32_t PERIPHID6; /*< Peripheral ID Register, offset: 0xFD8 /
emilmont	60:3d0ef94e36ec	2530	__I uint32_t PERIPHID7; /*< Peripheral ID Register, offset: 0xFDC /
emilmont	60:3d0ef94e36ec	2531	__I uint32_t PERIPHID0; /*< Peripheral ID Register, offset: 0xFE0 /
emilmont	60:3d0ef94e36ec	2532	__I uint32_t PERIPHID1; /*< Peripheral ID Register, offset: 0xFE4 /
emilmont	60:3d0ef94e36ec	2533	__I uint32_t PERIPHID2; /*< Peripheral ID Register, offset: 0xFE8 /
emilmont	60:3d0ef94e36ec	2534	__I uint32_t PERIPHID3; /*< Peripheral ID Register, offset: 0xFEC /
emilmont	60:3d0ef94e36ec	2535	__I uint32_t COMPID[4]; /*< Component ID Register, array offset: 0xFF0, array step: 0x4 /
emilmont	60:3d0ef94e36ec	2536	} ROM_Type;
emilmont	60:3d0ef94e36ec	2537
emilmont	60:3d0ef94e36ec	2538	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2539	-- ROM Register Masks
emilmont	60:3d0ef94e36ec	2540	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2541
emilmont	60:3d0ef94e36ec	2542	/**
emilmont	60:3d0ef94e36ec	2543	* @addtogroup ROM_Register_Masks ROM Register Masks
emilmont	60:3d0ef94e36ec	2544	* @{
emilmont	60:3d0ef94e36ec	2545	*/
emilmont	60:3d0ef94e36ec	2546
emilmont	60:3d0ef94e36ec	2547	/* ENTRY Bit Fields */
emilmont	60:3d0ef94e36ec	2548	#define ROM_ENTRY_ENTRY_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2549	#define ROM_ENTRY_ENTRY_SHIFT 0
emilmont	60:3d0ef94e36ec	2550	#define ROM_ENTRY_ENTRY(x) (((uint32_t)(((uint32_t)(x))<<ROM_ENTRY_ENTRY_SHIFT))&ROM_ENTRY_ENTRY_MASK)
emilmont	60:3d0ef94e36ec	2551	/* TABLEMARK Bit Fields */
emilmont	60:3d0ef94e36ec	2552	#define ROM_TABLEMARK_MARK_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2553	#define ROM_TABLEMARK_MARK_SHIFT 0
emilmont	60:3d0ef94e36ec	2554	#define ROM_TABLEMARK_MARK(x) (((uint32_t)(((uint32_t)(x))<<ROM_TABLEMARK_MARK_SHIFT))&ROM_TABLEMARK_MARK_MASK)
emilmont	60:3d0ef94e36ec	2555	/* SYSACCESS Bit Fields */
emilmont	60:3d0ef94e36ec	2556	#define ROM_SYSACCESS_SYSACCESS_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2557	#define ROM_SYSACCESS_SYSACCESS_SHIFT 0
emilmont	60:3d0ef94e36ec	2558	#define ROM_SYSACCESS_SYSACCESS(x) (((uint32_t)(((uint32_t)(x))<<ROM_SYSACCESS_SYSACCESS_SHIFT))&ROM_SYSACCESS_SYSACCESS_MASK)
emilmont	60:3d0ef94e36ec	2559	/* PERIPHID4 Bit Fields */
emilmont	60:3d0ef94e36ec	2560	#define ROM_PERIPHID4_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2561	#define ROM_PERIPHID4_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	2562	#define ROM_PERIPHID4_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID4_PERIPHID_SHIFT))&ROM_PERIPHID4_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	2563	/* PERIPHID5 Bit Fields */
emilmont	60:3d0ef94e36ec	2564	#define ROM_PERIPHID5_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2565	#define ROM_PERIPHID5_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	2566	#define ROM_PERIPHID5_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID5_PERIPHID_SHIFT))&ROM_PERIPHID5_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	2567	/* PERIPHID6 Bit Fields */
emilmont	60:3d0ef94e36ec	2568	#define ROM_PERIPHID6_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2569	#define ROM_PERIPHID6_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	2570	#define ROM_PERIPHID6_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID6_PERIPHID_SHIFT))&ROM_PERIPHID6_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	2571	/* PERIPHID7 Bit Fields */
emilmont	60:3d0ef94e36ec	2572	#define ROM_PERIPHID7_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2573	#define ROM_PERIPHID7_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	2574	#define ROM_PERIPHID7_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID7_PERIPHID_SHIFT))&ROM_PERIPHID7_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	2575	/* PERIPHID0 Bit Fields */
emilmont	60:3d0ef94e36ec	2576	#define ROM_PERIPHID0_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2577	#define ROM_PERIPHID0_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	2578	#define ROM_PERIPHID0_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID0_PERIPHID_SHIFT))&ROM_PERIPHID0_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	2579	/* PERIPHID1 Bit Fields */
emilmont	60:3d0ef94e36ec	2580	#define ROM_PERIPHID1_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2581	#define ROM_PERIPHID1_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	2582	#define ROM_PERIPHID1_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID1_PERIPHID_SHIFT))&ROM_PERIPHID1_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	2583	/* PERIPHID2 Bit Fields */
emilmont	60:3d0ef94e36ec	2584	#define ROM_PERIPHID2_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2585	#define ROM_PERIPHID2_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	2586	#define ROM_PERIPHID2_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID2_PERIPHID_SHIFT))&ROM_PERIPHID2_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	2587	/* PERIPHID3 Bit Fields */
emilmont	60:3d0ef94e36ec	2588	#define ROM_PERIPHID3_PERIPHID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2589	#define ROM_PERIPHID3_PERIPHID_SHIFT 0
emilmont	60:3d0ef94e36ec	2590	#define ROM_PERIPHID3_PERIPHID(x) (((uint32_t)(((uint32_t)(x))<<ROM_PERIPHID3_PERIPHID_SHIFT))&ROM_PERIPHID3_PERIPHID_MASK)
emilmont	60:3d0ef94e36ec	2591	/* COMPID Bit Fields */
emilmont	60:3d0ef94e36ec	2592	#define ROM_COMPID_COMPID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2593	#define ROM_COMPID_COMPID_SHIFT 0
emilmont	60:3d0ef94e36ec	2594	#define ROM_COMPID_COMPID(x) (((uint32_t)(((uint32_t)(x))<<ROM_COMPID_COMPID_SHIFT))&ROM_COMPID_COMPID_MASK)
emilmont	60:3d0ef94e36ec	2595
emilmont	60:3d0ef94e36ec	2596	/**
emilmont	60:3d0ef94e36ec	2597	* @}
emilmont	60:3d0ef94e36ec	2598	/ / end of group ROM_Register_Masks */
emilmont	60:3d0ef94e36ec	2599
emilmont	60:3d0ef94e36ec	2600
emilmont	60:3d0ef94e36ec	2601	/* ROM - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	2602	/** Peripheral ROM base address */
emilmont	60:3d0ef94e36ec	2603	#define ROM_BASE (0xF0002000u)
emilmont	60:3d0ef94e36ec	2604	/** Peripheral ROM base pointer */
emilmont	60:3d0ef94e36ec	2605	#define ROM ((ROM_Type *)ROM_BASE)
emilmont	60:3d0ef94e36ec	2606	/** Array initializer of ROM peripheral base pointers */
emilmont	60:3d0ef94e36ec	2607	#define ROM_BASES { ROM }
emilmont	60:3d0ef94e36ec	2608
emilmont	60:3d0ef94e36ec	2609	/**
emilmont	60:3d0ef94e36ec	2610	* @}
emilmont	60:3d0ef94e36ec	2611	/ / end of group ROM_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	2612
emilmont	60:3d0ef94e36ec	2613
emilmont	60:3d0ef94e36ec	2614	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2615	-- RTC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2616	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2617
emilmont	60:3d0ef94e36ec	2618	/**
emilmont	60:3d0ef94e36ec	2619	* @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2620	* @{
emilmont	60:3d0ef94e36ec	2621	*/
emilmont	60:3d0ef94e36ec	2622
emilmont	60:3d0ef94e36ec	2623	/** RTC - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	2624	typedef struct {
emilmont	60:3d0ef94e36ec	2625	__IO uint32_t TSR; /*< RTC Time Seconds Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	2626	__IO uint32_t TPR; /*< RTC Time Prescaler Register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	2627	__IO uint32_t TAR; /*< RTC Time Alarm Register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	2628	__IO uint32_t TCR; /*< RTC Time Compensation Register, offset: 0xC /
emilmont	60:3d0ef94e36ec	2629	__IO uint32_t CR; /*< RTC Control Register, offset: 0x10 /
emilmont	60:3d0ef94e36ec	2630	__IO uint32_t SR; /*< RTC Status Register, offset: 0x14 /
emilmont	60:3d0ef94e36ec	2631	__IO uint32_t LR; /*< RTC Lock Register, offset: 0x18 /
emilmont	60:3d0ef94e36ec	2632	__IO uint32_t IER; /*< RTC Interrupt Enable Register, offset: 0x1C /
emilmont	60:3d0ef94e36ec	2633	} RTC_Type;
emilmont	60:3d0ef94e36ec	2634
emilmont	60:3d0ef94e36ec	2635	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2636	-- RTC Register Masks
emilmont	60:3d0ef94e36ec	2637	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2638
emilmont	60:3d0ef94e36ec	2639	/**
emilmont	60:3d0ef94e36ec	2640	* @addtogroup RTC_Register_Masks RTC Register Masks
emilmont	60:3d0ef94e36ec	2641	* @{
emilmont	60:3d0ef94e36ec	2642	*/
emilmont	60:3d0ef94e36ec	2643
emilmont	60:3d0ef94e36ec	2644	/* TSR Bit Fields */
emilmont	60:3d0ef94e36ec	2645	#define RTC_TSR_TSR_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2646	#define RTC_TSR_TSR_SHIFT 0
emilmont	60:3d0ef94e36ec	2647	#define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TSR_TSR_SHIFT))&RTC_TSR_TSR_MASK)
emilmont	60:3d0ef94e36ec	2648	/* TPR Bit Fields */
emilmont	60:3d0ef94e36ec	2649	#define RTC_TPR_TPR_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	2650	#define RTC_TPR_TPR_SHIFT 0
emilmont	60:3d0ef94e36ec	2651	#define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TPR_TPR_SHIFT))&RTC_TPR_TPR_MASK)
emilmont	60:3d0ef94e36ec	2652	/* TAR Bit Fields */
emilmont	60:3d0ef94e36ec	2653	#define RTC_TAR_TAR_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2654	#define RTC_TAR_TAR_SHIFT 0
emilmont	60:3d0ef94e36ec	2655	#define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TAR_TAR_SHIFT))&RTC_TAR_TAR_MASK)
emilmont	60:3d0ef94e36ec	2656	/* TCR Bit Fields */
emilmont	60:3d0ef94e36ec	2657	#define RTC_TCR_TCR_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2658	#define RTC_TCR_TCR_SHIFT 0
emilmont	60:3d0ef94e36ec	2659	#define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCR_SHIFT))&RTC_TCR_TCR_MASK)
emilmont	60:3d0ef94e36ec	2660	#define RTC_TCR_CIR_MASK 0xFF00u
emilmont	60:3d0ef94e36ec	2661	#define RTC_TCR_CIR_SHIFT 8
emilmont	60:3d0ef94e36ec	2662	#define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIR_SHIFT))&RTC_TCR_CIR_MASK)
emilmont	60:3d0ef94e36ec	2663	#define RTC_TCR_TCV_MASK 0xFF0000u
emilmont	60:3d0ef94e36ec	2664	#define RTC_TCR_TCV_SHIFT 16
emilmont	60:3d0ef94e36ec	2665	#define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_TCV_SHIFT))&RTC_TCR_TCV_MASK)
emilmont	60:3d0ef94e36ec	2666	#define RTC_TCR_CIC_MASK 0xFF000000u
emilmont	60:3d0ef94e36ec	2667	#define RTC_TCR_CIC_SHIFT 24
emilmont	60:3d0ef94e36ec	2668	#define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x))<<RTC_TCR_CIC_SHIFT))&RTC_TCR_CIC_MASK)
emilmont	60:3d0ef94e36ec	2669	/* CR Bit Fields */
emilmont	60:3d0ef94e36ec	2670	#define RTC_CR_SWR_MASK 0x1u
emilmont	60:3d0ef94e36ec	2671	#define RTC_CR_SWR_SHIFT 0
emilmont	60:3d0ef94e36ec	2672	#define RTC_CR_WPE_MASK 0x2u
emilmont	60:3d0ef94e36ec	2673	#define RTC_CR_WPE_SHIFT 1
emilmont	60:3d0ef94e36ec	2674	#define RTC_CR_SUP_MASK 0x4u
emilmont	60:3d0ef94e36ec	2675	#define RTC_CR_SUP_SHIFT 2
emilmont	60:3d0ef94e36ec	2676	#define RTC_CR_UM_MASK 0x8u
emilmont	60:3d0ef94e36ec	2677	#define RTC_CR_UM_SHIFT 3
emilmont	60:3d0ef94e36ec	2678	#define RTC_CR_OSCE_MASK 0x100u
emilmont	60:3d0ef94e36ec	2679	#define RTC_CR_OSCE_SHIFT 8
emilmont	60:3d0ef94e36ec	2680	#define RTC_CR_CLKO_MASK 0x200u
emilmont	60:3d0ef94e36ec	2681	#define RTC_CR_CLKO_SHIFT 9
emilmont	60:3d0ef94e36ec	2682	#define RTC_CR_SC16P_MASK 0x400u
emilmont	60:3d0ef94e36ec	2683	#define RTC_CR_SC16P_SHIFT 10
emilmont	60:3d0ef94e36ec	2684	#define RTC_CR_SC8P_MASK 0x800u
emilmont	60:3d0ef94e36ec	2685	#define RTC_CR_SC8P_SHIFT 11
emilmont	60:3d0ef94e36ec	2686	#define RTC_CR_SC4P_MASK 0x1000u
emilmont	60:3d0ef94e36ec	2687	#define RTC_CR_SC4P_SHIFT 12
emilmont	60:3d0ef94e36ec	2688	#define RTC_CR_SC2P_MASK 0x2000u
emilmont	60:3d0ef94e36ec	2689	#define RTC_CR_SC2P_SHIFT 13
emilmont	60:3d0ef94e36ec	2690	/* SR Bit Fields */
emilmont	60:3d0ef94e36ec	2691	#define RTC_SR_TIF_MASK 0x1u
emilmont	60:3d0ef94e36ec	2692	#define RTC_SR_TIF_SHIFT 0
emilmont	60:3d0ef94e36ec	2693	#define RTC_SR_TOF_MASK 0x2u
emilmont	60:3d0ef94e36ec	2694	#define RTC_SR_TOF_SHIFT 1
emilmont	60:3d0ef94e36ec	2695	#define RTC_SR_TAF_MASK 0x4u
emilmont	60:3d0ef94e36ec	2696	#define RTC_SR_TAF_SHIFT 2
emilmont	60:3d0ef94e36ec	2697	#define RTC_SR_TCE_MASK 0x10u
emilmont	60:3d0ef94e36ec	2698	#define RTC_SR_TCE_SHIFT 4
emilmont	60:3d0ef94e36ec	2699	/* LR Bit Fields */
emilmont	60:3d0ef94e36ec	2700	#define RTC_LR_TCL_MASK 0x8u
emilmont	60:3d0ef94e36ec	2701	#define RTC_LR_TCL_SHIFT 3
emilmont	60:3d0ef94e36ec	2702	#define RTC_LR_CRL_MASK 0x10u
emilmont	60:3d0ef94e36ec	2703	#define RTC_LR_CRL_SHIFT 4
emilmont	60:3d0ef94e36ec	2704	#define RTC_LR_SRL_MASK 0x20u
emilmont	60:3d0ef94e36ec	2705	#define RTC_LR_SRL_SHIFT 5
emilmont	60:3d0ef94e36ec	2706	#define RTC_LR_LRL_MASK 0x40u
emilmont	60:3d0ef94e36ec	2707	#define RTC_LR_LRL_SHIFT 6
emilmont	60:3d0ef94e36ec	2708	/* IER Bit Fields */
emilmont	60:3d0ef94e36ec	2709	#define RTC_IER_TIIE_MASK 0x1u
emilmont	60:3d0ef94e36ec	2710	#define RTC_IER_TIIE_SHIFT 0
emilmont	60:3d0ef94e36ec	2711	#define RTC_IER_TOIE_MASK 0x2u
emilmont	60:3d0ef94e36ec	2712	#define RTC_IER_TOIE_SHIFT 1
emilmont	60:3d0ef94e36ec	2713	#define RTC_IER_TAIE_MASK 0x4u
emilmont	60:3d0ef94e36ec	2714	#define RTC_IER_TAIE_SHIFT 2
emilmont	60:3d0ef94e36ec	2715	#define RTC_IER_TSIE_MASK 0x10u
emilmont	60:3d0ef94e36ec	2716	#define RTC_IER_TSIE_SHIFT 4
emilmont	60:3d0ef94e36ec	2717	#define RTC_IER_WPON_MASK 0x80u
emilmont	60:3d0ef94e36ec	2718	#define RTC_IER_WPON_SHIFT 7
emilmont	60:3d0ef94e36ec	2719
emilmont	60:3d0ef94e36ec	2720	/**
emilmont	60:3d0ef94e36ec	2721	* @}
emilmont	60:3d0ef94e36ec	2722	/ / end of group RTC_Register_Masks */
emilmont	60:3d0ef94e36ec	2723
emilmont	60:3d0ef94e36ec	2724
emilmont	60:3d0ef94e36ec	2725	/* RTC - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	2726	/** Peripheral RTC base address */
emilmont	60:3d0ef94e36ec	2727	#define RTC_BASE (0x4003D000u)
emilmont	60:3d0ef94e36ec	2728	/** Peripheral RTC base pointer */
emilmont	60:3d0ef94e36ec	2729	#define RTC ((RTC_Type *)RTC_BASE)
emilmont	60:3d0ef94e36ec	2730	/** Array initializer of RTC peripheral base pointers */
emilmont	60:3d0ef94e36ec	2731	#define RTC_BASES { RTC }
emilmont	60:3d0ef94e36ec	2732
emilmont	60:3d0ef94e36ec	2733	/**
emilmont	60:3d0ef94e36ec	2734	* @}
emilmont	60:3d0ef94e36ec	2735	/ / end of group RTC_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	2736
emilmont	60:3d0ef94e36ec	2737
emilmont	60:3d0ef94e36ec	2738	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2739	-- SIM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2740	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2741
emilmont	60:3d0ef94e36ec	2742	/**
emilmont	60:3d0ef94e36ec	2743	* @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2744	* @{
emilmont	60:3d0ef94e36ec	2745	*/
emilmont	60:3d0ef94e36ec	2746
emilmont	60:3d0ef94e36ec	2747	/** SIM - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	2748	typedef struct {
emilmont	60:3d0ef94e36ec	2749	__IO uint32_t SOPT1; /*< System Options Register 1, offset: 0x0 /
emilmont	60:3d0ef94e36ec	2750	__IO uint32_t SOPT1CFG; /*< SOPT1 Configuration Register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	2751	uint8_t RESERVED_0[4092];
emilmont	60:3d0ef94e36ec	2752	__IO uint32_t SOPT2; /*< System Options Register 2, offset: 0x1004 /
emilmont	60:3d0ef94e36ec	2753	uint8_t RESERVED_1[4];
emilmont	60:3d0ef94e36ec	2754	__IO uint32_t SOPT4; /*< System Options Register 4, offset: 0x100C /
emilmont	60:3d0ef94e36ec	2755	__IO uint32_t SOPT5; /*< System Options Register 5, offset: 0x1010 /
emilmont	60:3d0ef94e36ec	2756	uint8_t RESERVED_2[4];
emilmont	60:3d0ef94e36ec	2757	__IO uint32_t SOPT7; /*< System Options Register 7, offset: 0x1018 /
emilmont	60:3d0ef94e36ec	2758	uint8_t RESERVED_3[8];
emilmont	60:3d0ef94e36ec	2759	__I uint32_t SDID; /*< System Device Identification Register, offset: 0x1024 /
emilmont	60:3d0ef94e36ec	2760	uint8_t RESERVED_4[12];
emilmont	60:3d0ef94e36ec	2761	__IO uint32_t SCGC4; /*< System Clock Gating Control Register 4, offset: 0x1034 /
emilmont	60:3d0ef94e36ec	2762	__IO uint32_t SCGC5; /*< System Clock Gating Control Register 5, offset: 0x1038 /
emilmont	60:3d0ef94e36ec	2763	__IO uint32_t SCGC6; /*< System Clock Gating Control Register 6, offset: 0x103C /
emilmont	60:3d0ef94e36ec	2764	__IO uint32_t SCGC7; /*< System Clock Gating Control Register 7, offset: 0x1040 /
emilmont	60:3d0ef94e36ec	2765	__IO uint32_t CLKDIV1; /*< System Clock Divider Register 1, offset: 0x1044 /
emilmont	60:3d0ef94e36ec	2766	uint8_t RESERVED_5[4];
emilmont	60:3d0ef94e36ec	2767	__IO uint32_t FCFG1; /*< Flash Configuration Register 1, offset: 0x104C /
emilmont	60:3d0ef94e36ec	2768	__I uint32_t FCFG2; /*< Flash Configuration Register 2, offset: 0x1050 /
emilmont	60:3d0ef94e36ec	2769	uint8_t RESERVED_6[4];
emilmont	60:3d0ef94e36ec	2770	__I uint32_t UIDMH; /*< Unique Identification Register Mid-High, offset: 0x1058 /
emilmont	60:3d0ef94e36ec	2771	__I uint32_t UIDML; /*< Unique Identification Register Mid Low, offset: 0x105C /
emilmont	60:3d0ef94e36ec	2772	__I uint32_t UIDL; /*< Unique Identification Register Low, offset: 0x1060 /
emilmont	60:3d0ef94e36ec	2773	uint8_t RESERVED_7[156];
emilmont	60:3d0ef94e36ec	2774	__IO uint32_t COPC; /*< COP Control Register, offset: 0x1100 /
emilmont	60:3d0ef94e36ec	2775	__O uint32_t SRVCOP; /*< Service COP Register, offset: 0x1104 /
emilmont	60:3d0ef94e36ec	2776	} SIM_Type;
emilmont	60:3d0ef94e36ec	2777
emilmont	60:3d0ef94e36ec	2778	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2779	-- SIM Register Masks
emilmont	60:3d0ef94e36ec	2780	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2781
emilmont	60:3d0ef94e36ec	2782	/**
emilmont	60:3d0ef94e36ec	2783	* @addtogroup SIM_Register_Masks SIM Register Masks
emilmont	60:3d0ef94e36ec	2784	* @{
emilmont	60:3d0ef94e36ec	2785	*/
emilmont	60:3d0ef94e36ec	2786
emilmont	60:3d0ef94e36ec	2787	/* SOPT1 Bit Fields */
emilmont	60:3d0ef94e36ec	2788	#define SIM_SOPT1_OSC32KSEL_MASK 0xC0000u
emilmont	60:3d0ef94e36ec	2789	#define SIM_SOPT1_OSC32KSEL_SHIFT 18
emilmont	60:3d0ef94e36ec	2790	#define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT1_OSC32KSEL_SHIFT))&SIM_SOPT1_OSC32KSEL_MASK)
emilmont	60:3d0ef94e36ec	2791	#define SIM_SOPT1_USBVSTBY_MASK 0x20000000u
emilmont	60:3d0ef94e36ec	2792	#define SIM_SOPT1_USBVSTBY_SHIFT 29
emilmont	60:3d0ef94e36ec	2793	#define SIM_SOPT1_USBSSTBY_MASK 0x40000000u
emilmont	60:3d0ef94e36ec	2794	#define SIM_SOPT1_USBSSTBY_SHIFT 30
emilmont	60:3d0ef94e36ec	2795	#define SIM_SOPT1_USBREGEN_MASK 0x80000000u
emilmont	60:3d0ef94e36ec	2796	#define SIM_SOPT1_USBREGEN_SHIFT 31
emilmont	60:3d0ef94e36ec	2797	/* SOPT1CFG Bit Fields */
emilmont	60:3d0ef94e36ec	2798	#define SIM_SOPT1CFG_URWE_MASK 0x1000000u
emilmont	60:3d0ef94e36ec	2799	#define SIM_SOPT1CFG_URWE_SHIFT 24
emilmont	60:3d0ef94e36ec	2800	#define SIM_SOPT1CFG_UVSWE_MASK 0x2000000u
emilmont	60:3d0ef94e36ec	2801	#define SIM_SOPT1CFG_UVSWE_SHIFT 25
emilmont	60:3d0ef94e36ec	2802	#define SIM_SOPT1CFG_USSWE_MASK 0x4000000u
emilmont	60:3d0ef94e36ec	2803	#define SIM_SOPT1CFG_USSWE_SHIFT 26
emilmont	60:3d0ef94e36ec	2804	/* SOPT2 Bit Fields */
emilmont	60:3d0ef94e36ec	2805	#define SIM_SOPT2_RTCCLKOUTSEL_MASK 0x10u
emilmont	60:3d0ef94e36ec	2806	#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT 4
emilmont	60:3d0ef94e36ec	2807	#define SIM_SOPT2_CLKOUTSEL_MASK 0xE0u
emilmont	60:3d0ef94e36ec	2808	#define SIM_SOPT2_CLKOUTSEL_SHIFT 5
emilmont	60:3d0ef94e36ec	2809	#define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_CLKOUTSEL_SHIFT))&SIM_SOPT2_CLKOUTSEL_MASK)
emilmont	60:3d0ef94e36ec	2810	#define SIM_SOPT2_PLLFLLSEL_MASK 0x10000u
emilmont	60:3d0ef94e36ec	2811	#define SIM_SOPT2_PLLFLLSEL_SHIFT 16
emilmont	60:3d0ef94e36ec	2812	#define SIM_SOPT2_USBSRC_MASK 0x40000u
emilmont	60:3d0ef94e36ec	2813	#define SIM_SOPT2_USBSRC_SHIFT 18
emilmont	60:3d0ef94e36ec	2814	#define SIM_SOPT2_TPMSRC_MASK 0x3000000u
emilmont	60:3d0ef94e36ec	2815	#define SIM_SOPT2_TPMSRC_SHIFT 24
emilmont	60:3d0ef94e36ec	2816	#define SIM_SOPT2_TPMSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_TPMSRC_SHIFT))&SIM_SOPT2_TPMSRC_MASK)
emilmont	60:3d0ef94e36ec	2817	#define SIM_SOPT2_UART0SRC_MASK 0xC000000u
emilmont	60:3d0ef94e36ec	2818	#define SIM_SOPT2_UART0SRC_SHIFT 26
emilmont	60:3d0ef94e36ec	2819	#define SIM_SOPT2_UART0SRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT2_UART0SRC_SHIFT))&SIM_SOPT2_UART0SRC_MASK)
emilmont	60:3d0ef94e36ec	2820	/* SOPT4 Bit Fields */
emilmont	60:3d0ef94e36ec	2821	#define SIM_SOPT4_TPM1CH0SRC_MASK 0x40000u
emilmont	60:3d0ef94e36ec	2822	#define SIM_SOPT4_TPM1CH0SRC_SHIFT 18
emilmont	60:3d0ef94e36ec	2823	#define SIM_SOPT4_TPM2CH0SRC_MASK 0x100000u
emilmont	60:3d0ef94e36ec	2824	#define SIM_SOPT4_TPM2CH0SRC_SHIFT 20
emilmont	60:3d0ef94e36ec	2825	#define SIM_SOPT4_TPM0CLKSEL_MASK 0x1000000u
emilmont	60:3d0ef94e36ec	2826	#define SIM_SOPT4_TPM0CLKSEL_SHIFT 24
emilmont	60:3d0ef94e36ec	2827	#define SIM_SOPT4_TPM1CLKSEL_MASK 0x2000000u
emilmont	60:3d0ef94e36ec	2828	#define SIM_SOPT4_TPM1CLKSEL_SHIFT 25
emilmont	60:3d0ef94e36ec	2829	#define SIM_SOPT4_TPM2CLKSEL_MASK 0x4000000u
emilmont	60:3d0ef94e36ec	2830	#define SIM_SOPT4_TPM2CLKSEL_SHIFT 26
emilmont	60:3d0ef94e36ec	2831	/* SOPT5 Bit Fields */
emilmont	60:3d0ef94e36ec	2832	#define SIM_SOPT5_UART0TXSRC_MASK 0x3u
emilmont	60:3d0ef94e36ec	2833	#define SIM_SOPT5_UART0TXSRC_SHIFT 0
emilmont	60:3d0ef94e36ec	2834	#define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART0TXSRC_SHIFT))&SIM_SOPT5_UART0TXSRC_MASK)
emilmont	60:3d0ef94e36ec	2835	#define SIM_SOPT5_UART0RXSRC_MASK 0x4u
emilmont	60:3d0ef94e36ec	2836	#define SIM_SOPT5_UART0RXSRC_SHIFT 2
emilmont	60:3d0ef94e36ec	2837	#define SIM_SOPT5_UART1TXSRC_MASK 0x30u
emilmont	60:3d0ef94e36ec	2838	#define SIM_SOPT5_UART1TXSRC_SHIFT 4
emilmont	60:3d0ef94e36ec	2839	#define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT5_UART1TXSRC_SHIFT))&SIM_SOPT5_UART1TXSRC_MASK)
emilmont	60:3d0ef94e36ec	2840	#define SIM_SOPT5_UART1RXSRC_MASK 0x40u
emilmont	60:3d0ef94e36ec	2841	#define SIM_SOPT5_UART1RXSRC_SHIFT 6
emilmont	60:3d0ef94e36ec	2842	#define SIM_SOPT5_UART0ODE_MASK 0x10000u
emilmont	60:3d0ef94e36ec	2843	#define SIM_SOPT5_UART0ODE_SHIFT 16
emilmont	60:3d0ef94e36ec	2844	#define SIM_SOPT5_UART1ODE_MASK 0x20000u
emilmont	60:3d0ef94e36ec	2845	#define SIM_SOPT5_UART1ODE_SHIFT 17
emilmont	60:3d0ef94e36ec	2846	#define SIM_SOPT5_UART2ODE_MASK 0x40000u
emilmont	60:3d0ef94e36ec	2847	#define SIM_SOPT5_UART2ODE_SHIFT 18
emilmont	60:3d0ef94e36ec	2848	/* SOPT7 Bit Fields */
emilmont	60:3d0ef94e36ec	2849	#define SIM_SOPT7_ADC0TRGSEL_MASK 0xFu
emilmont	60:3d0ef94e36ec	2850	#define SIM_SOPT7_ADC0TRGSEL_SHIFT 0
emilmont	60:3d0ef94e36ec	2851	#define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<SIM_SOPT7_ADC0TRGSEL_SHIFT))&SIM_SOPT7_ADC0TRGSEL_MASK)
emilmont	60:3d0ef94e36ec	2852	#define SIM_SOPT7_ADC0PRETRGSEL_MASK 0x10u
emilmont	60:3d0ef94e36ec	2853	#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT 4
emilmont	60:3d0ef94e36ec	2854	#define SIM_SOPT7_ADC0ALTTRGEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	2855	#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT 7
emilmont	60:3d0ef94e36ec	2856	/* SDID Bit Fields */
emilmont	60:3d0ef94e36ec	2857	#define SIM_SDID_PINID_MASK 0xFu
emilmont	60:3d0ef94e36ec	2858	#define SIM_SDID_PINID_SHIFT 0
emilmont	60:3d0ef94e36ec	2859	#define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_PINID_SHIFT))&SIM_SDID_PINID_MASK)
emilmont	60:3d0ef94e36ec	2860	#define SIM_SDID_DIEID_MASK 0xF80u
emilmont	60:3d0ef94e36ec	2861	#define SIM_SDID_DIEID_SHIFT 7
emilmont	60:3d0ef94e36ec	2862	#define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_DIEID_SHIFT))&SIM_SDID_DIEID_MASK)
emilmont	60:3d0ef94e36ec	2863	#define SIM_SDID_REVID_MASK 0xF000u
emilmont	60:3d0ef94e36ec	2864	#define SIM_SDID_REVID_SHIFT 12
emilmont	60:3d0ef94e36ec	2865	#define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_REVID_SHIFT))&SIM_SDID_REVID_MASK)
emilmont	60:3d0ef94e36ec	2866	#define SIM_SDID_SRAMSIZE_MASK 0xF0000u
emilmont	60:3d0ef94e36ec	2867	#define SIM_SDID_SRAMSIZE_SHIFT 16
emilmont	60:3d0ef94e36ec	2868	#define SIM_SDID_SRAMSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SRAMSIZE_SHIFT))&SIM_SDID_SRAMSIZE_MASK)
emilmont	60:3d0ef94e36ec	2869	#define SIM_SDID_SERIESID_MASK 0xF00000u
emilmont	60:3d0ef94e36ec	2870	#define SIM_SDID_SERIESID_SHIFT 20
emilmont	60:3d0ef94e36ec	2871	#define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SERIESID_SHIFT))&SIM_SDID_SERIESID_MASK)
emilmont	60:3d0ef94e36ec	2872	#define SIM_SDID_SUBFAMID_MASK 0xF000000u
emilmont	60:3d0ef94e36ec	2873	#define SIM_SDID_SUBFAMID_SHIFT 24
emilmont	60:3d0ef94e36ec	2874	#define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_SUBFAMID_SHIFT))&SIM_SDID_SUBFAMID_MASK)
emilmont	60:3d0ef94e36ec	2875	#define SIM_SDID_FAMID_MASK 0xF0000000u
emilmont	60:3d0ef94e36ec	2876	#define SIM_SDID_FAMID_SHIFT 28
emilmont	60:3d0ef94e36ec	2877	#define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x))<<SIM_SDID_FAMID_SHIFT))&SIM_SDID_FAMID_MASK)
emilmont	60:3d0ef94e36ec	2878	/* SCGC4 Bit Fields */
emilmont	60:3d0ef94e36ec	2879	#define SIM_SCGC4_I2C0_MASK 0x40u
emilmont	60:3d0ef94e36ec	2880	#define SIM_SCGC4_I2C0_SHIFT 6
emilmont	60:3d0ef94e36ec	2881	#define SIM_SCGC4_I2C1_MASK 0x80u
emilmont	60:3d0ef94e36ec	2882	#define SIM_SCGC4_I2C1_SHIFT 7
emilmont	60:3d0ef94e36ec	2883	#define SIM_SCGC4_UART0_MASK 0x400u
emilmont	60:3d0ef94e36ec	2884	#define SIM_SCGC4_UART0_SHIFT 10
emilmont	60:3d0ef94e36ec	2885	#define SIM_SCGC4_UART1_MASK 0x800u
emilmont	60:3d0ef94e36ec	2886	#define SIM_SCGC4_UART1_SHIFT 11
emilmont	60:3d0ef94e36ec	2887	#define SIM_SCGC4_UART2_MASK 0x1000u
emilmont	60:3d0ef94e36ec	2888	#define SIM_SCGC4_UART2_SHIFT 12
emilmont	60:3d0ef94e36ec	2889	#define SIM_SCGC4_USBOTG_MASK 0x40000u
emilmont	60:3d0ef94e36ec	2890	#define SIM_SCGC4_USBOTG_SHIFT 18
emilmont	60:3d0ef94e36ec	2891	#define SIM_SCGC4_CMP_MASK 0x80000u
emilmont	60:3d0ef94e36ec	2892	#define SIM_SCGC4_CMP_SHIFT 19
emilmont	60:3d0ef94e36ec	2893	#define SIM_SCGC4_SPI0_MASK 0x400000u
emilmont	60:3d0ef94e36ec	2894	#define SIM_SCGC4_SPI0_SHIFT 22
emilmont	60:3d0ef94e36ec	2895	#define SIM_SCGC4_SPI1_MASK 0x800000u
emilmont	60:3d0ef94e36ec	2896	#define SIM_SCGC4_SPI1_SHIFT 23
emilmont	60:3d0ef94e36ec	2897	/* SCGC5 Bit Fields */
emilmont	60:3d0ef94e36ec	2898	#define SIM_SCGC5_LPTMR_MASK 0x1u
emilmont	60:3d0ef94e36ec	2899	#define SIM_SCGC5_LPTMR_SHIFT 0
emilmont	60:3d0ef94e36ec	2900	#define SIM_SCGC5_TSI_MASK 0x20u
emilmont	60:3d0ef94e36ec	2901	#define SIM_SCGC5_TSI_SHIFT 5
emilmont	60:3d0ef94e36ec	2902	#define SIM_SCGC5_PORTA_MASK 0x200u
emilmont	60:3d0ef94e36ec	2903	#define SIM_SCGC5_PORTA_SHIFT 9
emilmont	60:3d0ef94e36ec	2904	#define SIM_SCGC5_PORTB_MASK 0x400u
emilmont	60:3d0ef94e36ec	2905	#define SIM_SCGC5_PORTB_SHIFT 10
emilmont	60:3d0ef94e36ec	2906	#define SIM_SCGC5_PORTC_MASK 0x800u
emilmont	60:3d0ef94e36ec	2907	#define SIM_SCGC5_PORTC_SHIFT 11
emilmont	60:3d0ef94e36ec	2908	#define SIM_SCGC5_PORTD_MASK 0x1000u
emilmont	60:3d0ef94e36ec	2909	#define SIM_SCGC5_PORTD_SHIFT 12
emilmont	60:3d0ef94e36ec	2910	#define SIM_SCGC5_PORTE_MASK 0x2000u
emilmont	60:3d0ef94e36ec	2911	#define SIM_SCGC5_PORTE_SHIFT 13
emilmont	60:3d0ef94e36ec	2912	/* SCGC6 Bit Fields */
emilmont	60:3d0ef94e36ec	2913	#define SIM_SCGC6_FTF_MASK 0x1u
emilmont	60:3d0ef94e36ec	2914	#define SIM_SCGC6_FTF_SHIFT 0
emilmont	60:3d0ef94e36ec	2915	#define SIM_SCGC6_DMAMUX_MASK 0x2u
emilmont	60:3d0ef94e36ec	2916	#define SIM_SCGC6_DMAMUX_SHIFT 1
emilmont	60:3d0ef94e36ec	2917	#define SIM_SCGC6_PIT_MASK 0x800000u
emilmont	60:3d0ef94e36ec	2918	#define SIM_SCGC6_PIT_SHIFT 23
emilmont	60:3d0ef94e36ec	2919	#define SIM_SCGC6_TPM0_MASK 0x1000000u
emilmont	60:3d0ef94e36ec	2920	#define SIM_SCGC6_TPM0_SHIFT 24
emilmont	60:3d0ef94e36ec	2921	#define SIM_SCGC6_TPM1_MASK 0x2000000u
emilmont	60:3d0ef94e36ec	2922	#define SIM_SCGC6_TPM1_SHIFT 25
emilmont	60:3d0ef94e36ec	2923	#define SIM_SCGC6_TPM2_MASK 0x4000000u
emilmont	60:3d0ef94e36ec	2924	#define SIM_SCGC6_TPM2_SHIFT 26
emilmont	60:3d0ef94e36ec	2925	#define SIM_SCGC6_ADC0_MASK 0x8000000u
emilmont	60:3d0ef94e36ec	2926	#define SIM_SCGC6_ADC0_SHIFT 27
emilmont	60:3d0ef94e36ec	2927	#define SIM_SCGC6_RTC_MASK 0x20000000u
emilmont	60:3d0ef94e36ec	2928	#define SIM_SCGC6_RTC_SHIFT 29
emilmont	60:3d0ef94e36ec	2929	#define SIM_SCGC6_DAC0_MASK 0x80000000u
emilmont	60:3d0ef94e36ec	2930	#define SIM_SCGC6_DAC0_SHIFT 31
emilmont	60:3d0ef94e36ec	2931	/* SCGC7 Bit Fields */
emilmont	60:3d0ef94e36ec	2932	#define SIM_SCGC7_DMA_MASK 0x100u
emilmont	60:3d0ef94e36ec	2933	#define SIM_SCGC7_DMA_SHIFT 8
emilmont	60:3d0ef94e36ec	2934	/* CLKDIV1 Bit Fields */
emilmont	60:3d0ef94e36ec	2935	#define SIM_CLKDIV1_OUTDIV4_MASK 0x70000u
emilmont	60:3d0ef94e36ec	2936	#define SIM_CLKDIV1_OUTDIV4_SHIFT 16
emilmont	60:3d0ef94e36ec	2937	#define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV4_SHIFT))&SIM_CLKDIV1_OUTDIV4_MASK)
emilmont	60:3d0ef94e36ec	2938	#define SIM_CLKDIV1_OUTDIV1_MASK 0xF0000000u
emilmont	60:3d0ef94e36ec	2939	#define SIM_CLKDIV1_OUTDIV1_SHIFT 28
emilmont	60:3d0ef94e36ec	2940	#define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x))<<SIM_CLKDIV1_OUTDIV1_SHIFT))&SIM_CLKDIV1_OUTDIV1_MASK)
emilmont	60:3d0ef94e36ec	2941	/* FCFG1 Bit Fields */
emilmont	60:3d0ef94e36ec	2942	#define SIM_FCFG1_FLASHDIS_MASK 0x1u
emilmont	60:3d0ef94e36ec	2943	#define SIM_FCFG1_FLASHDIS_SHIFT 0
emilmont	60:3d0ef94e36ec	2944	#define SIM_FCFG1_FLASHDOZE_MASK 0x2u
emilmont	60:3d0ef94e36ec	2945	#define SIM_FCFG1_FLASHDOZE_SHIFT 1
emilmont	60:3d0ef94e36ec	2946	#define SIM_FCFG1_PFSIZE_MASK 0xF000000u
emilmont	60:3d0ef94e36ec	2947	#define SIM_FCFG1_PFSIZE_SHIFT 24
emilmont	60:3d0ef94e36ec	2948	#define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG1_PFSIZE_SHIFT))&SIM_FCFG1_PFSIZE_MASK)
emilmont	60:3d0ef94e36ec	2949	/* FCFG2 Bit Fields */
emilmont	60:3d0ef94e36ec	2950	#define SIM_FCFG2_MAXADDR_MASK 0x7F000000u
emilmont	60:3d0ef94e36ec	2951	#define SIM_FCFG2_MAXADDR_SHIFT 24
emilmont	60:3d0ef94e36ec	2952	#define SIM_FCFG2_MAXADDR(x) (((uint32_t)(((uint32_t)(x))<<SIM_FCFG2_MAXADDR_SHIFT))&SIM_FCFG2_MAXADDR_MASK)
emilmont	60:3d0ef94e36ec	2953	/* UIDMH Bit Fields */
emilmont	60:3d0ef94e36ec	2954	#define SIM_UIDMH_UID_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	2955	#define SIM_UIDMH_UID_SHIFT 0
emilmont	60:3d0ef94e36ec	2956	#define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDMH_UID_SHIFT))&SIM_UIDMH_UID_MASK)
emilmont	60:3d0ef94e36ec	2957	/* UIDML Bit Fields */
emilmont	60:3d0ef94e36ec	2958	#define SIM_UIDML_UID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2959	#define SIM_UIDML_UID_SHIFT 0
emilmont	60:3d0ef94e36ec	2960	#define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDML_UID_SHIFT))&SIM_UIDML_UID_MASK)
emilmont	60:3d0ef94e36ec	2961	/* UIDL Bit Fields */
emilmont	60:3d0ef94e36ec	2962	#define SIM_UIDL_UID_MASK 0xFFFFFFFFu
emilmont	60:3d0ef94e36ec	2963	#define SIM_UIDL_UID_SHIFT 0
emilmont	60:3d0ef94e36ec	2964	#define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x))<<SIM_UIDL_UID_SHIFT))&SIM_UIDL_UID_MASK)
emilmont	60:3d0ef94e36ec	2965	/* COPC Bit Fields */
emilmont	60:3d0ef94e36ec	2966	#define SIM_COPC_COPW_MASK 0x1u
emilmont	60:3d0ef94e36ec	2967	#define SIM_COPC_COPW_SHIFT 0
emilmont	60:3d0ef94e36ec	2968	#define SIM_COPC_COPCLKS_MASK 0x2u
emilmont	60:3d0ef94e36ec	2969	#define SIM_COPC_COPCLKS_SHIFT 1
emilmont	60:3d0ef94e36ec	2970	#define SIM_COPC_COPT_MASK 0xCu
emilmont	60:3d0ef94e36ec	2971	#define SIM_COPC_COPT_SHIFT 2
emilmont	60:3d0ef94e36ec	2972	#define SIM_COPC_COPT(x) (((uint32_t)(((uint32_t)(x))<<SIM_COPC_COPT_SHIFT))&SIM_COPC_COPT_MASK)
emilmont	60:3d0ef94e36ec	2973	/* SRVCOP Bit Fields */
emilmont	60:3d0ef94e36ec	2974	#define SIM_SRVCOP_SRVCOP_MASK 0xFFu
emilmont	60:3d0ef94e36ec	2975	#define SIM_SRVCOP_SRVCOP_SHIFT 0
emilmont	60:3d0ef94e36ec	2976	#define SIM_SRVCOP_SRVCOP(x) (((uint32_t)(((uint32_t)(x))<<SIM_SRVCOP_SRVCOP_SHIFT))&SIM_SRVCOP_SRVCOP_MASK)
emilmont	60:3d0ef94e36ec	2977
emilmont	60:3d0ef94e36ec	2978	/**
emilmont	60:3d0ef94e36ec	2979	* @}
emilmont	60:3d0ef94e36ec	2980	/ / end of group SIM_Register_Masks */
emilmont	60:3d0ef94e36ec	2981
emilmont	60:3d0ef94e36ec	2982
emilmont	60:3d0ef94e36ec	2983	/* SIM - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	2984	/** Peripheral SIM base address */
emilmont	60:3d0ef94e36ec	2985	#define SIM_BASE (0x40047000u)
emilmont	60:3d0ef94e36ec	2986	/** Peripheral SIM base pointer */
emilmont	60:3d0ef94e36ec	2987	#define SIM ((SIM_Type *)SIM_BASE)
emilmont	60:3d0ef94e36ec	2988	/** Array initializer of SIM peripheral base pointers */
emilmont	60:3d0ef94e36ec	2989	#define SIM_BASES { SIM }
emilmont	60:3d0ef94e36ec	2990
emilmont	60:3d0ef94e36ec	2991	/**
emilmont	60:3d0ef94e36ec	2992	* @}
emilmont	60:3d0ef94e36ec	2993	/ / end of group SIM_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	2994
emilmont	60:3d0ef94e36ec	2995
emilmont	60:3d0ef94e36ec	2996	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	2997	-- SMC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	2998	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	2999
emilmont	60:3d0ef94e36ec	3000	/**
emilmont	60:3d0ef94e36ec	3001	* @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3002	* @{
emilmont	60:3d0ef94e36ec	3003	*/
emilmont	60:3d0ef94e36ec	3004
emilmont	60:3d0ef94e36ec	3005	/** SMC - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	3006	typedef struct {
emilmont	60:3d0ef94e36ec	3007	__IO uint8_t PMPROT; /*< Power Mode Protection register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	3008	__IO uint8_t PMCTRL; /*< Power Mode Control register, offset: 0x1 /
emilmont	60:3d0ef94e36ec	3009	__IO uint8_t STOPCTRL; /*< Stop Control Register, offset: 0x2 /
emilmont	60:3d0ef94e36ec	3010	__I uint8_t PMSTAT; /*< Power Mode Status register, offset: 0x3 /
emilmont	60:3d0ef94e36ec	3011	} SMC_Type;
emilmont	60:3d0ef94e36ec	3012
emilmont	60:3d0ef94e36ec	3013	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3014	-- SMC Register Masks
emilmont	60:3d0ef94e36ec	3015	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3016
emilmont	60:3d0ef94e36ec	3017	/**
emilmont	60:3d0ef94e36ec	3018	* @addtogroup SMC_Register_Masks SMC Register Masks
emilmont	60:3d0ef94e36ec	3019	* @{
emilmont	60:3d0ef94e36ec	3020	*/
emilmont	60:3d0ef94e36ec	3021
emilmont	60:3d0ef94e36ec	3022	/* PMPROT Bit Fields */
emilmont	60:3d0ef94e36ec	3023	#define SMC_PMPROT_AVLLS_MASK 0x2u
emilmont	60:3d0ef94e36ec	3024	#define SMC_PMPROT_AVLLS_SHIFT 1
emilmont	60:3d0ef94e36ec	3025	#define SMC_PMPROT_ALLS_MASK 0x8u
emilmont	60:3d0ef94e36ec	3026	#define SMC_PMPROT_ALLS_SHIFT 3
emilmont	60:3d0ef94e36ec	3027	#define SMC_PMPROT_AVLP_MASK 0x20u
emilmont	60:3d0ef94e36ec	3028	#define SMC_PMPROT_AVLP_SHIFT 5
emilmont	60:3d0ef94e36ec	3029	/* PMCTRL Bit Fields */
emilmont	60:3d0ef94e36ec	3030	#define SMC_PMCTRL_STOPM_MASK 0x7u
emilmont	60:3d0ef94e36ec	3031	#define SMC_PMCTRL_STOPM_SHIFT 0
emilmont	60:3d0ef94e36ec	3032	#define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_STOPM_SHIFT))&SMC_PMCTRL_STOPM_MASK)
emilmont	60:3d0ef94e36ec	3033	#define SMC_PMCTRL_STOPA_MASK 0x8u
emilmont	60:3d0ef94e36ec	3034	#define SMC_PMCTRL_STOPA_SHIFT 3
emilmont	60:3d0ef94e36ec	3035	#define SMC_PMCTRL_RUNM_MASK 0x60u
emilmont	60:3d0ef94e36ec	3036	#define SMC_PMCTRL_RUNM_SHIFT 5
emilmont	60:3d0ef94e36ec	3037	#define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMCTRL_RUNM_SHIFT))&SMC_PMCTRL_RUNM_MASK)
emilmont	60:3d0ef94e36ec	3038	/* STOPCTRL Bit Fields */
emilmont	60:3d0ef94e36ec	3039	#define SMC_STOPCTRL_VLLSM_MASK 0x7u
emilmont	60:3d0ef94e36ec	3040	#define SMC_STOPCTRL_VLLSM_SHIFT 0
emilmont	60:3d0ef94e36ec	3041	#define SMC_STOPCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_VLLSM_SHIFT))&SMC_STOPCTRL_VLLSM_MASK)
emilmont	60:3d0ef94e36ec	3042	#define SMC_STOPCTRL_PORPO_MASK 0x20u
emilmont	60:3d0ef94e36ec	3043	#define SMC_STOPCTRL_PORPO_SHIFT 5
emilmont	60:3d0ef94e36ec	3044	#define SMC_STOPCTRL_PSTOPO_MASK 0xC0u
emilmont	60:3d0ef94e36ec	3045	#define SMC_STOPCTRL_PSTOPO_SHIFT 6
emilmont	60:3d0ef94e36ec	3046	#define SMC_STOPCTRL_PSTOPO(x) (((uint8_t)(((uint8_t)(x))<<SMC_STOPCTRL_PSTOPO_SHIFT))&SMC_STOPCTRL_PSTOPO_MASK)
emilmont	60:3d0ef94e36ec	3047	/* PMSTAT Bit Fields */
emilmont	60:3d0ef94e36ec	3048	#define SMC_PMSTAT_PMSTAT_MASK 0x7Fu
emilmont	60:3d0ef94e36ec	3049	#define SMC_PMSTAT_PMSTAT_SHIFT 0
emilmont	60:3d0ef94e36ec	3050	#define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x))<<SMC_PMSTAT_PMSTAT_SHIFT))&SMC_PMSTAT_PMSTAT_MASK)
emilmont	60:3d0ef94e36ec	3051
emilmont	60:3d0ef94e36ec	3052	/**
emilmont	60:3d0ef94e36ec	3053	* @}
emilmont	60:3d0ef94e36ec	3054	/ / end of group SMC_Register_Masks */
emilmont	60:3d0ef94e36ec	3055
emilmont	60:3d0ef94e36ec	3056
emilmont	60:3d0ef94e36ec	3057	/* SMC - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	3058	/** Peripheral SMC base address */
emilmont	60:3d0ef94e36ec	3059	#define SMC_BASE (0x4007E000u)
emilmont	60:3d0ef94e36ec	3060	/** Peripheral SMC base pointer */
emilmont	60:3d0ef94e36ec	3061	#define SMC ((SMC_Type *)SMC_BASE)
emilmont	60:3d0ef94e36ec	3062	/** Array initializer of SMC peripheral base pointers */
emilmont	60:3d0ef94e36ec	3063	#define SMC_BASES { SMC }
emilmont	60:3d0ef94e36ec	3064
emilmont	60:3d0ef94e36ec	3065	/**
emilmont	60:3d0ef94e36ec	3066	* @}
emilmont	60:3d0ef94e36ec	3067	/ / end of group SMC_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	3068
emilmont	60:3d0ef94e36ec	3069
emilmont	60:3d0ef94e36ec	3070	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3071	-- SPI Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3072	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3073
emilmont	60:3d0ef94e36ec	3074	/**
emilmont	60:3d0ef94e36ec	3075	* @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3076	* @{
emilmont	60:3d0ef94e36ec	3077	*/
emilmont	60:3d0ef94e36ec	3078
emilmont	60:3d0ef94e36ec	3079	/** SPI - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	3080	typedef struct {
emilmont	60:3d0ef94e36ec	3081	__IO uint8_t C1; /*< SPI control register 1, offset: 0x0 /
emilmont	60:3d0ef94e36ec	3082	__IO uint8_t C2; /*< SPI control register 2, offset: 0x1 /
emilmont	60:3d0ef94e36ec	3083	__IO uint8_t BR; /*< SPI baud rate register, offset: 0x2 /
emilmont	60:3d0ef94e36ec	3084	__I uint8_t S; /*< SPI status register, offset: 0x3 /
emilmont	60:3d0ef94e36ec	3085	uint8_t RESERVED_0[1];
emilmont	60:3d0ef94e36ec	3086	__IO uint8_t D; /*< SPI data register, offset: 0x5 /
emilmont	60:3d0ef94e36ec	3087	uint8_t RESERVED_1[1];
emilmont	60:3d0ef94e36ec	3088	__IO uint8_t M; /*< SPI match register, offset: 0x7 /
emilmont	60:3d0ef94e36ec	3089	} SPI_Type;
emilmont	60:3d0ef94e36ec	3090
emilmont	60:3d0ef94e36ec	3091	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3092	-- SPI Register Masks
emilmont	60:3d0ef94e36ec	3093	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3094
emilmont	60:3d0ef94e36ec	3095	/**
emilmont	60:3d0ef94e36ec	3096	* @addtogroup SPI_Register_Masks SPI Register Masks
emilmont	60:3d0ef94e36ec	3097	* @{
emilmont	60:3d0ef94e36ec	3098	*/
emilmont	60:3d0ef94e36ec	3099
emilmont	60:3d0ef94e36ec	3100	/* C1 Bit Fields */
emilmont	60:3d0ef94e36ec	3101	#define SPI_C1_LSBFE_MASK 0x1u
emilmont	60:3d0ef94e36ec	3102	#define SPI_C1_LSBFE_SHIFT 0
emilmont	60:3d0ef94e36ec	3103	#define SPI_C1_SSOE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3104	#define SPI_C1_SSOE_SHIFT 1
emilmont	60:3d0ef94e36ec	3105	#define SPI_C1_CPHA_MASK 0x4u
emilmont	60:3d0ef94e36ec	3106	#define SPI_C1_CPHA_SHIFT 2
emilmont	60:3d0ef94e36ec	3107	#define SPI_C1_CPOL_MASK 0x8u
emilmont	60:3d0ef94e36ec	3108	#define SPI_C1_CPOL_SHIFT 3
emilmont	60:3d0ef94e36ec	3109	#define SPI_C1_MSTR_MASK 0x10u
emilmont	60:3d0ef94e36ec	3110	#define SPI_C1_MSTR_SHIFT 4
emilmont	60:3d0ef94e36ec	3111	#define SPI_C1_SPTIE_MASK 0x20u
emilmont	60:3d0ef94e36ec	3112	#define SPI_C1_SPTIE_SHIFT 5
emilmont	60:3d0ef94e36ec	3113	#define SPI_C1_SPE_MASK 0x40u
emilmont	60:3d0ef94e36ec	3114	#define SPI_C1_SPE_SHIFT 6
emilmont	60:3d0ef94e36ec	3115	#define SPI_C1_SPIE_MASK 0x80u
emilmont	60:3d0ef94e36ec	3116	#define SPI_C1_SPIE_SHIFT 7
emilmont	60:3d0ef94e36ec	3117	/* C2 Bit Fields */
emilmont	60:3d0ef94e36ec	3118	#define SPI_C2_SPC0_MASK 0x1u
emilmont	60:3d0ef94e36ec	3119	#define SPI_C2_SPC0_SHIFT 0
emilmont	60:3d0ef94e36ec	3120	#define SPI_C2_SPISWAI_MASK 0x2u
emilmont	60:3d0ef94e36ec	3121	#define SPI_C2_SPISWAI_SHIFT 1
emilmont	60:3d0ef94e36ec	3122	#define SPI_C2_RXDMAE_MASK 0x4u
emilmont	60:3d0ef94e36ec	3123	#define SPI_C2_RXDMAE_SHIFT 2
emilmont	60:3d0ef94e36ec	3124	#define SPI_C2_BIDIROE_MASK 0x8u
emilmont	60:3d0ef94e36ec	3125	#define SPI_C2_BIDIROE_SHIFT 3
emilmont	60:3d0ef94e36ec	3126	#define SPI_C2_MODFEN_MASK 0x10u
emilmont	60:3d0ef94e36ec	3127	#define SPI_C2_MODFEN_SHIFT 4
emilmont	60:3d0ef94e36ec	3128	#define SPI_C2_TXDMAE_MASK 0x20u
emilmont	60:3d0ef94e36ec	3129	#define SPI_C2_TXDMAE_SHIFT 5
emilmont	60:3d0ef94e36ec	3130	#define SPI_C2_SPLPIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	3131	#define SPI_C2_SPLPIE_SHIFT 6
emilmont	60:3d0ef94e36ec	3132	#define SPI_C2_SPMIE_MASK 0x80u
emilmont	60:3d0ef94e36ec	3133	#define SPI_C2_SPMIE_SHIFT 7
emilmont	60:3d0ef94e36ec	3134	/* BR Bit Fields */
emilmont	60:3d0ef94e36ec	3135	#define SPI_BR_SPR_MASK 0xFu
emilmont	60:3d0ef94e36ec	3136	#define SPI_BR_SPR_SHIFT 0
emilmont	60:3d0ef94e36ec	3137	#define SPI_BR_SPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPR_SHIFT))&SPI_BR_SPR_MASK)
emilmont	60:3d0ef94e36ec	3138	#define SPI_BR_SPPR_MASK 0x70u
emilmont	60:3d0ef94e36ec	3139	#define SPI_BR_SPPR_SHIFT 4
emilmont	60:3d0ef94e36ec	3140	#define SPI_BR_SPPR(x) (((uint8_t)(((uint8_t)(x))<<SPI_BR_SPPR_SHIFT))&SPI_BR_SPPR_MASK)
emilmont	60:3d0ef94e36ec	3141	/* S Bit Fields */
emilmont	60:3d0ef94e36ec	3142	#define SPI_S_MODF_MASK 0x10u
emilmont	60:3d0ef94e36ec	3143	#define SPI_S_MODF_SHIFT 4
emilmont	60:3d0ef94e36ec	3144	#define SPI_S_SPTEF_MASK 0x20u
emilmont	60:3d0ef94e36ec	3145	#define SPI_S_SPTEF_SHIFT 5
emilmont	60:3d0ef94e36ec	3146	#define SPI_S_SPMF_MASK 0x40u
emilmont	60:3d0ef94e36ec	3147	#define SPI_S_SPMF_SHIFT 6
emilmont	60:3d0ef94e36ec	3148	#define SPI_S_SPRF_MASK 0x80u
emilmont	60:3d0ef94e36ec	3149	#define SPI_S_SPRF_SHIFT 7
emilmont	60:3d0ef94e36ec	3150	/* D Bit Fields */
emilmont	60:3d0ef94e36ec	3151	#define SPI_D_Bits_MASK 0xFFu
emilmont	60:3d0ef94e36ec	3152	#define SPI_D_Bits_SHIFT 0
emilmont	60:3d0ef94e36ec	3153	#define SPI_D_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_D_Bits_SHIFT))&SPI_D_Bits_MASK)
emilmont	60:3d0ef94e36ec	3154	/* M Bit Fields */
emilmont	60:3d0ef94e36ec	3155	#define SPI_M_Bits_MASK 0xFFu
emilmont	60:3d0ef94e36ec	3156	#define SPI_M_Bits_SHIFT 0
emilmont	60:3d0ef94e36ec	3157	#define SPI_M_Bits(x) (((uint8_t)(((uint8_t)(x))<<SPI_M_Bits_SHIFT))&SPI_M_Bits_MASK)
emilmont	60:3d0ef94e36ec	3158
emilmont	60:3d0ef94e36ec	3159	/**
emilmont	60:3d0ef94e36ec	3160	* @}
emilmont	60:3d0ef94e36ec	3161	/ / end of group SPI_Register_Masks */
emilmont	60:3d0ef94e36ec	3162
emilmont	60:3d0ef94e36ec	3163
emilmont	60:3d0ef94e36ec	3164	/* SPI - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	3165	/** Peripheral SPI0 base address */
emilmont	60:3d0ef94e36ec	3166	#define SPI0_BASE (0x40076000u)
emilmont	60:3d0ef94e36ec	3167	/** Peripheral SPI0 base pointer */
emilmont	60:3d0ef94e36ec	3168	#define SPI0 ((SPI_Type *)SPI0_BASE)
emilmont	60:3d0ef94e36ec	3169	/** Peripheral SPI1 base address */
emilmont	60:3d0ef94e36ec	3170	#define SPI1_BASE (0x40077000u)
emilmont	60:3d0ef94e36ec	3171	/** Peripheral SPI1 base pointer */
emilmont	60:3d0ef94e36ec	3172	#define SPI1 ((SPI_Type *)SPI1_BASE)
emilmont	60:3d0ef94e36ec	3173	/** Array initializer of SPI peripheral base pointers */
emilmont	60:3d0ef94e36ec	3174	#define SPI_BASES { SPI0, SPI1 }
emilmont	60:3d0ef94e36ec	3175
emilmont	60:3d0ef94e36ec	3176	/**
emilmont	60:3d0ef94e36ec	3177	* @}
emilmont	60:3d0ef94e36ec	3178	/ / end of group SPI_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	3179
emilmont	60:3d0ef94e36ec	3180
emilmont	60:3d0ef94e36ec	3181	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3182	-- TPM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3183	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3184
emilmont	60:3d0ef94e36ec	3185	/**
emilmont	60:3d0ef94e36ec	3186	* @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3187	* @{
emilmont	60:3d0ef94e36ec	3188	*/
emilmont	60:3d0ef94e36ec	3189
emilmont	60:3d0ef94e36ec	3190	/** TPM - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	3191	typedef struct {
emilmont	60:3d0ef94e36ec	3192	__IO uint32_t SC; /*< Status and Control, offset: 0x0 /
emilmont	60:3d0ef94e36ec	3193	__IO uint32_t CNT; /*< Counter, offset: 0x4 /
emilmont	60:3d0ef94e36ec	3194	__IO uint32_t MOD; /*< Modulo, offset: 0x8 /
emilmont	60:3d0ef94e36ec	3195	struct { /* offset: 0xC, array step: 0x8 */
emilmont	60:3d0ef94e36ec	3196	__IO uint32_t CnSC; /*< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 /
emilmont	60:3d0ef94e36ec	3197	__IO uint32_t CnV; /*< Channel (n) Value, array offset: 0x10, array step: 0x8 /
emilmont	60:3d0ef94e36ec	3198	} CONTROLS[6];
emilmont	60:3d0ef94e36ec	3199	uint8_t RESERVED_0[20];
emilmont	60:3d0ef94e36ec	3200	__IO uint32_t STATUS; /*< Capture and Compare Status, offset: 0x50 /
emilmont	60:3d0ef94e36ec	3201	uint8_t RESERVED_1[48];
emilmont	60:3d0ef94e36ec	3202	__IO uint32_t CONF; /*< Configuration, offset: 0x84 /
emilmont	60:3d0ef94e36ec	3203	} TPM_Type;
emilmont	60:3d0ef94e36ec	3204
emilmont	60:3d0ef94e36ec	3205	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3206	-- TPM Register Masks
emilmont	60:3d0ef94e36ec	3207	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3208
emilmont	60:3d0ef94e36ec	3209	/**
emilmont	60:3d0ef94e36ec	3210	* @addtogroup TPM_Register_Masks TPM Register Masks
emilmont	60:3d0ef94e36ec	3211	* @{
emilmont	60:3d0ef94e36ec	3212	*/
emilmont	60:3d0ef94e36ec	3213
emilmont	60:3d0ef94e36ec	3214	/* SC Bit Fields */
emilmont	60:3d0ef94e36ec	3215	#define TPM_SC_PS_MASK 0x7u
emilmont	60:3d0ef94e36ec	3216	#define TPM_SC_PS_SHIFT 0
emilmont	60:3d0ef94e36ec	3217	#define TPM_SC_PS(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_PS_SHIFT))&TPM_SC_PS_MASK)
emilmont	60:3d0ef94e36ec	3218	#define TPM_SC_CMOD_MASK 0x18u
emilmont	60:3d0ef94e36ec	3219	#define TPM_SC_CMOD_SHIFT 3
emilmont	60:3d0ef94e36ec	3220	#define TPM_SC_CMOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_SC_CMOD_SHIFT))&TPM_SC_CMOD_MASK)
emilmont	60:3d0ef94e36ec	3221	#define TPM_SC_CPWMS_MASK 0x20u
emilmont	60:3d0ef94e36ec	3222	#define TPM_SC_CPWMS_SHIFT 5
emilmont	60:3d0ef94e36ec	3223	#define TPM_SC_TOIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	3224	#define TPM_SC_TOIE_SHIFT 6
emilmont	60:3d0ef94e36ec	3225	#define TPM_SC_TOF_MASK 0x80u
emilmont	60:3d0ef94e36ec	3226	#define TPM_SC_TOF_SHIFT 7
emilmont	60:3d0ef94e36ec	3227	#define TPM_SC_DMA_MASK 0x100u
emilmont	60:3d0ef94e36ec	3228	#define TPM_SC_DMA_SHIFT 8
emilmont	60:3d0ef94e36ec	3229	/* CNT Bit Fields */
emilmont	60:3d0ef94e36ec	3230	#define TPM_CNT_COUNT_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	3231	#define TPM_CNT_COUNT_SHIFT 0
emilmont	60:3d0ef94e36ec	3232	#define TPM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x))<<TPM_CNT_COUNT_SHIFT))&TPM_CNT_COUNT_MASK)
emilmont	60:3d0ef94e36ec	3233	/* MOD Bit Fields */
emilmont	60:3d0ef94e36ec	3234	#define TPM_MOD_MOD_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	3235	#define TPM_MOD_MOD_SHIFT 0
emilmont	60:3d0ef94e36ec	3236	#define TPM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x))<<TPM_MOD_MOD_SHIFT))&TPM_MOD_MOD_MASK)
emilmont	60:3d0ef94e36ec	3237	/* CnSC Bit Fields */
emilmont	60:3d0ef94e36ec	3238	#define TPM_CnSC_DMA_MASK 0x1u
emilmont	60:3d0ef94e36ec	3239	#define TPM_CnSC_DMA_SHIFT 0
emilmont	60:3d0ef94e36ec	3240	#define TPM_CnSC_ELSA_MASK 0x4u
emilmont	60:3d0ef94e36ec	3241	#define TPM_CnSC_ELSA_SHIFT 2
emilmont	60:3d0ef94e36ec	3242	#define TPM_CnSC_ELSB_MASK 0x8u
emilmont	60:3d0ef94e36ec	3243	#define TPM_CnSC_ELSB_SHIFT 3
emilmont	60:3d0ef94e36ec	3244	#define TPM_CnSC_MSA_MASK 0x10u
emilmont	60:3d0ef94e36ec	3245	#define TPM_CnSC_MSA_SHIFT 4
emilmont	60:3d0ef94e36ec	3246	#define TPM_CnSC_MSB_MASK 0x20u
emilmont	60:3d0ef94e36ec	3247	#define TPM_CnSC_MSB_SHIFT 5
emilmont	60:3d0ef94e36ec	3248	#define TPM_CnSC_CHIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	3249	#define TPM_CnSC_CHIE_SHIFT 6
emilmont	60:3d0ef94e36ec	3250	#define TPM_CnSC_CHF_MASK 0x80u
emilmont	60:3d0ef94e36ec	3251	#define TPM_CnSC_CHF_SHIFT 7
emilmont	60:3d0ef94e36ec	3252	/* CnV Bit Fields */
emilmont	60:3d0ef94e36ec	3253	#define TPM_CnV_VAL_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	3254	#define TPM_CnV_VAL_SHIFT 0
emilmont	60:3d0ef94e36ec	3255	#define TPM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CnV_VAL_SHIFT))&TPM_CnV_VAL_MASK)
emilmont	60:3d0ef94e36ec	3256	/* STATUS Bit Fields */
emilmont	60:3d0ef94e36ec	3257	#define TPM_STATUS_CH0F_MASK 0x1u
emilmont	60:3d0ef94e36ec	3258	#define TPM_STATUS_CH0F_SHIFT 0
emilmont	60:3d0ef94e36ec	3259	#define TPM_STATUS_CH1F_MASK 0x2u
emilmont	60:3d0ef94e36ec	3260	#define TPM_STATUS_CH1F_SHIFT 1
emilmont	60:3d0ef94e36ec	3261	#define TPM_STATUS_CH2F_MASK 0x4u
emilmont	60:3d0ef94e36ec	3262	#define TPM_STATUS_CH2F_SHIFT 2
emilmont	60:3d0ef94e36ec	3263	#define TPM_STATUS_CH3F_MASK 0x8u
emilmont	60:3d0ef94e36ec	3264	#define TPM_STATUS_CH3F_SHIFT 3
emilmont	60:3d0ef94e36ec	3265	#define TPM_STATUS_CH4F_MASK 0x10u
emilmont	60:3d0ef94e36ec	3266	#define TPM_STATUS_CH4F_SHIFT 4
emilmont	60:3d0ef94e36ec	3267	#define TPM_STATUS_CH5F_MASK 0x20u
emilmont	60:3d0ef94e36ec	3268	#define TPM_STATUS_CH5F_SHIFT 5
emilmont	60:3d0ef94e36ec	3269	#define TPM_STATUS_TOF_MASK 0x100u
emilmont	60:3d0ef94e36ec	3270	#define TPM_STATUS_TOF_SHIFT 8
emilmont	60:3d0ef94e36ec	3271	/* CONF Bit Fields */
emilmont	60:3d0ef94e36ec	3272	#define TPM_CONF_DOZEEN_MASK 0x20u
emilmont	60:3d0ef94e36ec	3273	#define TPM_CONF_DOZEEN_SHIFT 5
emilmont	60:3d0ef94e36ec	3274	#define TPM_CONF_DBGMODE_MASK 0xC0u
emilmont	60:3d0ef94e36ec	3275	#define TPM_CONF_DBGMODE_SHIFT 6
emilmont	60:3d0ef94e36ec	3276	#define TPM_CONF_DBGMODE(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_DBGMODE_SHIFT))&TPM_CONF_DBGMODE_MASK)
emilmont	60:3d0ef94e36ec	3277	#define TPM_CONF_GTBEEN_MASK 0x200u
emilmont	60:3d0ef94e36ec	3278	#define TPM_CONF_GTBEEN_SHIFT 9
emilmont	60:3d0ef94e36ec	3279	#define TPM_CONF_CSOT_MASK 0x10000u
emilmont	60:3d0ef94e36ec	3280	#define TPM_CONF_CSOT_SHIFT 16
emilmont	60:3d0ef94e36ec	3281	#define TPM_CONF_CSOO_MASK 0x20000u
emilmont	60:3d0ef94e36ec	3282	#define TPM_CONF_CSOO_SHIFT 17
emilmont	60:3d0ef94e36ec	3283	#define TPM_CONF_CROT_MASK 0x40000u
emilmont	60:3d0ef94e36ec	3284	#define TPM_CONF_CROT_SHIFT 18
emilmont	60:3d0ef94e36ec	3285	#define TPM_CONF_TRGSEL_MASK 0xF000000u
emilmont	60:3d0ef94e36ec	3286	#define TPM_CONF_TRGSEL_SHIFT 24
emilmont	60:3d0ef94e36ec	3287	#define TPM_CONF_TRGSEL(x) (((uint32_t)(((uint32_t)(x))<<TPM_CONF_TRGSEL_SHIFT))&TPM_CONF_TRGSEL_MASK)
emilmont	60:3d0ef94e36ec	3288
emilmont	60:3d0ef94e36ec	3289	/**
emilmont	60:3d0ef94e36ec	3290	* @}
emilmont	60:3d0ef94e36ec	3291	/ / end of group TPM_Register_Masks */
emilmont	60:3d0ef94e36ec	3292
emilmont	60:3d0ef94e36ec	3293
emilmont	60:3d0ef94e36ec	3294	/* TPM - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	3295	/** Peripheral TPM0 base address */
emilmont	60:3d0ef94e36ec	3296	#define TPM0_BASE (0x40038000u)
emilmont	60:3d0ef94e36ec	3297	/** Peripheral TPM0 base pointer */
emilmont	60:3d0ef94e36ec	3298	#define TPM0 ((TPM_Type *)TPM0_BASE)
emilmont	60:3d0ef94e36ec	3299	/** Peripheral TPM1 base address */
emilmont	60:3d0ef94e36ec	3300	#define TPM1_BASE (0x40039000u)
emilmont	60:3d0ef94e36ec	3301	/** Peripheral TPM1 base pointer */
emilmont	60:3d0ef94e36ec	3302	#define TPM1 ((TPM_Type *)TPM1_BASE)
emilmont	60:3d0ef94e36ec	3303	/** Peripheral TPM2 base address */
emilmont	60:3d0ef94e36ec	3304	#define TPM2_BASE (0x4003A000u)
emilmont	60:3d0ef94e36ec	3305	/** Peripheral TPM2 base pointer */
emilmont	60:3d0ef94e36ec	3306	#define TPM2 ((TPM_Type *)TPM2_BASE)
emilmont	60:3d0ef94e36ec	3307	/** Array initializer of TPM peripheral base pointers */
emilmont	60:3d0ef94e36ec	3308	#define TPM_BASES { TPM0, TPM1, TPM2 }
emilmont	60:3d0ef94e36ec	3309
emilmont	60:3d0ef94e36ec	3310	/**
emilmont	60:3d0ef94e36ec	3311	* @}
emilmont	60:3d0ef94e36ec	3312	/ / end of group TPM_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	3313
emilmont	60:3d0ef94e36ec	3314
emilmont	60:3d0ef94e36ec	3315	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3316	-- TSI Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3317	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3318
emilmont	60:3d0ef94e36ec	3319	/**
emilmont	60:3d0ef94e36ec	3320	* @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3321	* @{
emilmont	60:3d0ef94e36ec	3322	*/
emilmont	60:3d0ef94e36ec	3323
emilmont	60:3d0ef94e36ec	3324	/** TSI - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	3325	typedef struct {
emilmont	60:3d0ef94e36ec	3326	__IO uint32_t GENCS; /*< TSI General Control and Status Register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	3327	__IO uint32_t DATA; /*< TSI DATA Register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	3328	__IO uint32_t TSHD; /*< TSI Threshold Register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	3329	} TSI_Type;
emilmont	60:3d0ef94e36ec	3330
emilmont	60:3d0ef94e36ec	3331	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3332	-- TSI Register Masks
emilmont	60:3d0ef94e36ec	3333	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3334
emilmont	60:3d0ef94e36ec	3335	/**
emilmont	60:3d0ef94e36ec	3336	* @addtogroup TSI_Register_Masks TSI Register Masks
emilmont	60:3d0ef94e36ec	3337	* @{
emilmont	60:3d0ef94e36ec	3338	*/
emilmont	60:3d0ef94e36ec	3339
emilmont	60:3d0ef94e36ec	3340	/* GENCS Bit Fields */
emilmont	60:3d0ef94e36ec	3341	#define TSI_GENCS_CURSW_MASK 0x2u
emilmont	60:3d0ef94e36ec	3342	#define TSI_GENCS_CURSW_SHIFT 1
emilmont	60:3d0ef94e36ec	3343	#define TSI_GENCS_EOSF_MASK 0x4u
emilmont	60:3d0ef94e36ec	3344	#define TSI_GENCS_EOSF_SHIFT 2
emilmont	60:3d0ef94e36ec	3345	#define TSI_GENCS_SCNIP_MASK 0x8u
emilmont	60:3d0ef94e36ec	3346	#define TSI_GENCS_SCNIP_SHIFT 3
emilmont	60:3d0ef94e36ec	3347	#define TSI_GENCS_STM_MASK 0x10u
emilmont	60:3d0ef94e36ec	3348	#define TSI_GENCS_STM_SHIFT 4
emilmont	60:3d0ef94e36ec	3349	#define TSI_GENCS_STPE_MASK 0x20u
emilmont	60:3d0ef94e36ec	3350	#define TSI_GENCS_STPE_SHIFT 5
emilmont	60:3d0ef94e36ec	3351	#define TSI_GENCS_TSIIEN_MASK 0x40u
emilmont	60:3d0ef94e36ec	3352	#define TSI_GENCS_TSIIEN_SHIFT 6
emilmont	60:3d0ef94e36ec	3353	#define TSI_GENCS_TSIEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	3354	#define TSI_GENCS_TSIEN_SHIFT 7
emilmont	60:3d0ef94e36ec	3355	#define TSI_GENCS_NSCN_MASK 0x1F00u
emilmont	60:3d0ef94e36ec	3356	#define TSI_GENCS_NSCN_SHIFT 8
emilmont	60:3d0ef94e36ec	3357	#define TSI_GENCS_NSCN(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_NSCN_SHIFT))&TSI_GENCS_NSCN_MASK)
emilmont	60:3d0ef94e36ec	3358	#define TSI_GENCS_PS_MASK 0xE000u
emilmont	60:3d0ef94e36ec	3359	#define TSI_GENCS_PS_SHIFT 13
emilmont	60:3d0ef94e36ec	3360	#define TSI_GENCS_PS(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_PS_SHIFT))&TSI_GENCS_PS_MASK)
emilmont	60:3d0ef94e36ec	3361	#define TSI_GENCS_EXTCHRG_MASK 0x70000u
emilmont	60:3d0ef94e36ec	3362	#define TSI_GENCS_EXTCHRG_SHIFT 16
emilmont	60:3d0ef94e36ec	3363	#define TSI_GENCS_EXTCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_EXTCHRG_SHIFT))&TSI_GENCS_EXTCHRG_MASK)
emilmont	60:3d0ef94e36ec	3364	#define TSI_GENCS_DVOLT_MASK 0x180000u
emilmont	60:3d0ef94e36ec	3365	#define TSI_GENCS_DVOLT_SHIFT 19
emilmont	60:3d0ef94e36ec	3366	#define TSI_GENCS_DVOLT(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_DVOLT_SHIFT))&TSI_GENCS_DVOLT_MASK)
emilmont	60:3d0ef94e36ec	3367	#define TSI_GENCS_REFCHRG_MASK 0xE00000u
emilmont	60:3d0ef94e36ec	3368	#define TSI_GENCS_REFCHRG_SHIFT 21
emilmont	60:3d0ef94e36ec	3369	#define TSI_GENCS_REFCHRG(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_REFCHRG_SHIFT))&TSI_GENCS_REFCHRG_MASK)
emilmont	60:3d0ef94e36ec	3370	#define TSI_GENCS_MODE_MASK 0xF000000u
emilmont	60:3d0ef94e36ec	3371	#define TSI_GENCS_MODE_SHIFT 24
emilmont	60:3d0ef94e36ec	3372	#define TSI_GENCS_MODE(x) (((uint32_t)(((uint32_t)(x))<<TSI_GENCS_MODE_SHIFT))&TSI_GENCS_MODE_MASK)
emilmont	60:3d0ef94e36ec	3373	#define TSI_GENCS_ESOR_MASK 0x10000000u
emilmont	60:3d0ef94e36ec	3374	#define TSI_GENCS_ESOR_SHIFT 28
emilmont	60:3d0ef94e36ec	3375	#define TSI_GENCS_OUTRGF_MASK 0x80000000u
emilmont	60:3d0ef94e36ec	3376	#define TSI_GENCS_OUTRGF_SHIFT 31
emilmont	60:3d0ef94e36ec	3377	/* DATA Bit Fields */
emilmont	60:3d0ef94e36ec	3378	#define TSI_DATA_TSICNT_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	3379	#define TSI_DATA_TSICNT_SHIFT 0
emilmont	60:3d0ef94e36ec	3380	#define TSI_DATA_TSICNT(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICNT_SHIFT))&TSI_DATA_TSICNT_MASK)
emilmont	60:3d0ef94e36ec	3381	#define TSI_DATA_SWTS_MASK 0x400000u
emilmont	60:3d0ef94e36ec	3382	#define TSI_DATA_SWTS_SHIFT 22
emilmont	60:3d0ef94e36ec	3383	#define TSI_DATA_DMAEN_MASK 0x800000u
emilmont	60:3d0ef94e36ec	3384	#define TSI_DATA_DMAEN_SHIFT 23
emilmont	60:3d0ef94e36ec	3385	#define TSI_DATA_TSICH_MASK 0xF0000000u
emilmont	60:3d0ef94e36ec	3386	#define TSI_DATA_TSICH_SHIFT 28
emilmont	60:3d0ef94e36ec	3387	#define TSI_DATA_TSICH(x) (((uint32_t)(((uint32_t)(x))<<TSI_DATA_TSICH_SHIFT))&TSI_DATA_TSICH_MASK)
emilmont	60:3d0ef94e36ec	3388	/* TSHD Bit Fields */
emilmont	60:3d0ef94e36ec	3389	#define TSI_TSHD_THRESL_MASK 0xFFFFu
emilmont	60:3d0ef94e36ec	3390	#define TSI_TSHD_THRESL_SHIFT 0
emilmont	60:3d0ef94e36ec	3391	#define TSI_TSHD_THRESL(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESL_SHIFT))&TSI_TSHD_THRESL_MASK)
emilmont	60:3d0ef94e36ec	3392	#define TSI_TSHD_THRESH_MASK 0xFFFF0000u
emilmont	60:3d0ef94e36ec	3393	#define TSI_TSHD_THRESH_SHIFT 16
emilmont	60:3d0ef94e36ec	3394	#define TSI_TSHD_THRESH(x) (((uint32_t)(((uint32_t)(x))<<TSI_TSHD_THRESH_SHIFT))&TSI_TSHD_THRESH_MASK)
emilmont	60:3d0ef94e36ec	3395
emilmont	60:3d0ef94e36ec	3396	/**
emilmont	60:3d0ef94e36ec	3397	* @}
emilmont	60:3d0ef94e36ec	3398	/ / end of group TSI_Register_Masks */
emilmont	60:3d0ef94e36ec	3399
emilmont	60:3d0ef94e36ec	3400
emilmont	60:3d0ef94e36ec	3401	/* TSI - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	3402	/** Peripheral TSI0 base address */
emilmont	60:3d0ef94e36ec	3403	#define TSI0_BASE (0x40045000u)
emilmont	60:3d0ef94e36ec	3404	/** Peripheral TSI0 base pointer */
emilmont	60:3d0ef94e36ec	3405	#define TSI0 ((TSI_Type *)TSI0_BASE)
emilmont	60:3d0ef94e36ec	3406	/** Array initializer of TSI peripheral base pointers */
emilmont	60:3d0ef94e36ec	3407	#define TSI_BASES { TSI0 }
emilmont	60:3d0ef94e36ec	3408
emilmont	60:3d0ef94e36ec	3409	/**
emilmont	60:3d0ef94e36ec	3410	* @}
emilmont	60:3d0ef94e36ec	3411	/ / end of group TSI_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	3412
emilmont	60:3d0ef94e36ec	3413
emilmont	60:3d0ef94e36ec	3414	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3415	-- UART Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3416	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3417
emilmont	60:3d0ef94e36ec	3418	/**
emilmont	60:3d0ef94e36ec	3419	* @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3420	* @{
emilmont	60:3d0ef94e36ec	3421	*/
emilmont	60:3d0ef94e36ec	3422
emilmont	60:3d0ef94e36ec	3423	/** UART - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	3424	typedef struct {
emilmont	60:3d0ef94e36ec	3425	__IO uint8_t BDH; /*< UART Baud Rate Register: High, offset: 0x0 /
emilmont	60:3d0ef94e36ec	3426	__IO uint8_t BDL; /*< UART Baud Rate Register: Low, offset: 0x1 /
emilmont	60:3d0ef94e36ec	3427	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
emilmont	60:3d0ef94e36ec	3428	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
emilmont	60:3d0ef94e36ec	3429	__I uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
emilmont	60:3d0ef94e36ec	3430	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
emilmont	60:3d0ef94e36ec	3431	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
emilmont	60:3d0ef94e36ec	3432	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
emilmont	60:3d0ef94e36ec	3433	__IO uint8_t C4; /*< UART Control Register 4, offset: 0x8 /
emilmont	60:3d0ef94e36ec	3434	} UART_Type;
emilmont	60:3d0ef94e36ec	3435
emilmont	60:3d0ef94e36ec	3436	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3437	-- UART Register Masks
emilmont	60:3d0ef94e36ec	3438	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3439
emilmont	60:3d0ef94e36ec	3440	/**
emilmont	60:3d0ef94e36ec	3441	* @addtogroup UART_Register_Masks UART Register Masks
emilmont	60:3d0ef94e36ec	3442	* @{
emilmont	60:3d0ef94e36ec	3443	*/
emilmont	60:3d0ef94e36ec	3444
emilmont	60:3d0ef94e36ec	3445	/* BDH Bit Fields */
emilmont	60:3d0ef94e36ec	3446	#define UART_BDH_SBR_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	3447	#define UART_BDH_SBR_SHIFT 0
emilmont	60:3d0ef94e36ec	3448	#define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDH_SBR_SHIFT))&UART_BDH_SBR_MASK)
emilmont	60:3d0ef94e36ec	3449	#define UART_BDH_SBNS_MASK 0x20u
emilmont	60:3d0ef94e36ec	3450	#define UART_BDH_SBNS_SHIFT 5
emilmont	60:3d0ef94e36ec	3451	#define UART_BDH_RXEDGIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	3452	#define UART_BDH_RXEDGIE_SHIFT 6
emilmont	60:3d0ef94e36ec	3453	#define UART_BDH_LBKDIE_MASK 0x80u
emilmont	60:3d0ef94e36ec	3454	#define UART_BDH_LBKDIE_SHIFT 7
emilmont	60:3d0ef94e36ec	3455	/* BDL Bit Fields */
emilmont	60:3d0ef94e36ec	3456	#define UART_BDL_SBR_MASK 0xFFu
emilmont	60:3d0ef94e36ec	3457	#define UART_BDL_SBR_SHIFT 0
emilmont	60:3d0ef94e36ec	3458	#define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UART_BDL_SBR_SHIFT))&UART_BDL_SBR_MASK)
emilmont	60:3d0ef94e36ec	3459	/* C1 Bit Fields */
emilmont	60:3d0ef94e36ec	3460	#define UART_C1_PT_MASK 0x1u
emilmont	60:3d0ef94e36ec	3461	#define UART_C1_PT_SHIFT 0
emilmont	60:3d0ef94e36ec	3462	#define UART_C1_PE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3463	#define UART_C1_PE_SHIFT 1
emilmont	60:3d0ef94e36ec	3464	#define UART_C1_ILT_MASK 0x4u
emilmont	60:3d0ef94e36ec	3465	#define UART_C1_ILT_SHIFT 2
emilmont	60:3d0ef94e36ec	3466	#define UART_C1_WAKE_MASK 0x8u
emilmont	60:3d0ef94e36ec	3467	#define UART_C1_WAKE_SHIFT 3
emilmont	60:3d0ef94e36ec	3468	#define UART_C1_M_MASK 0x10u
emilmont	60:3d0ef94e36ec	3469	#define UART_C1_M_SHIFT 4
emilmont	60:3d0ef94e36ec	3470	#define UART_C1_RSRC_MASK 0x20u
emilmont	60:3d0ef94e36ec	3471	#define UART_C1_RSRC_SHIFT 5
emilmont	60:3d0ef94e36ec	3472	#define UART_C1_UARTSWAI_MASK 0x40u
emilmont	60:3d0ef94e36ec	3473	#define UART_C1_UARTSWAI_SHIFT 6
emilmont	60:3d0ef94e36ec	3474	#define UART_C1_LOOPS_MASK 0x80u
emilmont	60:3d0ef94e36ec	3475	#define UART_C1_LOOPS_SHIFT 7
emilmont	60:3d0ef94e36ec	3476	/* C2 Bit Fields */
emilmont	60:3d0ef94e36ec	3477	#define UART_C2_SBK_MASK 0x1u
emilmont	60:3d0ef94e36ec	3478	#define UART_C2_SBK_SHIFT 0
emilmont	60:3d0ef94e36ec	3479	#define UART_C2_RWU_MASK 0x2u
emilmont	60:3d0ef94e36ec	3480	#define UART_C2_RWU_SHIFT 1
emilmont	60:3d0ef94e36ec	3481	#define UART_C2_RE_MASK 0x4u
emilmont	60:3d0ef94e36ec	3482	#define UART_C2_RE_SHIFT 2
emilmont	60:3d0ef94e36ec	3483	#define UART_C2_TE_MASK 0x8u
emilmont	60:3d0ef94e36ec	3484	#define UART_C2_TE_SHIFT 3
emilmont	60:3d0ef94e36ec	3485	#define UART_C2_ILIE_MASK 0x10u
emilmont	60:3d0ef94e36ec	3486	#define UART_C2_ILIE_SHIFT 4
emilmont	60:3d0ef94e36ec	3487	#define UART_C2_RIE_MASK 0x20u
emilmont	60:3d0ef94e36ec	3488	#define UART_C2_RIE_SHIFT 5
emilmont	60:3d0ef94e36ec	3489	#define UART_C2_TCIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	3490	#define UART_C2_TCIE_SHIFT 6
emilmont	60:3d0ef94e36ec	3491	#define UART_C2_TIE_MASK 0x80u
emilmont	60:3d0ef94e36ec	3492	#define UART_C2_TIE_SHIFT 7
emilmont	60:3d0ef94e36ec	3493	/* S1 Bit Fields */
emilmont	60:3d0ef94e36ec	3494	#define UART_S1_PF_MASK 0x1u
emilmont	60:3d0ef94e36ec	3495	#define UART_S1_PF_SHIFT 0
emilmont	60:3d0ef94e36ec	3496	#define UART_S1_FE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3497	#define UART_S1_FE_SHIFT 1
emilmont	60:3d0ef94e36ec	3498	#define UART_S1_NF_MASK 0x4u
emilmont	60:3d0ef94e36ec	3499	#define UART_S1_NF_SHIFT 2
emilmont	60:3d0ef94e36ec	3500	#define UART_S1_OR_MASK 0x8u
emilmont	60:3d0ef94e36ec	3501	#define UART_S1_OR_SHIFT 3
emilmont	60:3d0ef94e36ec	3502	#define UART_S1_IDLE_MASK 0x10u
emilmont	60:3d0ef94e36ec	3503	#define UART_S1_IDLE_SHIFT 4
emilmont	60:3d0ef94e36ec	3504	#define UART_S1_RDRF_MASK 0x20u
emilmont	60:3d0ef94e36ec	3505	#define UART_S1_RDRF_SHIFT 5
emilmont	60:3d0ef94e36ec	3506	#define UART_S1_TC_MASK 0x40u
emilmont	60:3d0ef94e36ec	3507	#define UART_S1_TC_SHIFT 6
emilmont	60:3d0ef94e36ec	3508	#define UART_S1_TDRE_MASK 0x80u
emilmont	60:3d0ef94e36ec	3509	#define UART_S1_TDRE_SHIFT 7
emilmont	60:3d0ef94e36ec	3510	/* S2 Bit Fields */
emilmont	60:3d0ef94e36ec	3511	#define UART_S2_RAF_MASK 0x1u
emilmont	60:3d0ef94e36ec	3512	#define UART_S2_RAF_SHIFT 0
emilmont	60:3d0ef94e36ec	3513	#define UART_S2_LBKDE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3514	#define UART_S2_LBKDE_SHIFT 1
emilmont	60:3d0ef94e36ec	3515	#define UART_S2_BRK13_MASK 0x4u
emilmont	60:3d0ef94e36ec	3516	#define UART_S2_BRK13_SHIFT 2
emilmont	60:3d0ef94e36ec	3517	#define UART_S2_RWUID_MASK 0x8u
emilmont	60:3d0ef94e36ec	3518	#define UART_S2_RWUID_SHIFT 3
emilmont	60:3d0ef94e36ec	3519	#define UART_S2_RXINV_MASK 0x10u
emilmont	60:3d0ef94e36ec	3520	#define UART_S2_RXINV_SHIFT 4
emilmont	60:3d0ef94e36ec	3521	#define UART_S2_RXEDGIF_MASK 0x40u
emilmont	60:3d0ef94e36ec	3522	#define UART_S2_RXEDGIF_SHIFT 6
emilmont	60:3d0ef94e36ec	3523	#define UART_S2_LBKDIF_MASK 0x80u
emilmont	60:3d0ef94e36ec	3524	#define UART_S2_LBKDIF_SHIFT 7
emilmont	60:3d0ef94e36ec	3525	/* C3 Bit Fields */
emilmont	60:3d0ef94e36ec	3526	#define UART_C3_PEIE_MASK 0x1u
emilmont	60:3d0ef94e36ec	3527	#define UART_C3_PEIE_SHIFT 0
emilmont	60:3d0ef94e36ec	3528	#define UART_C3_FEIE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3529	#define UART_C3_FEIE_SHIFT 1
emilmont	60:3d0ef94e36ec	3530	#define UART_C3_NEIE_MASK 0x4u
emilmont	60:3d0ef94e36ec	3531	#define UART_C3_NEIE_SHIFT 2
emilmont	60:3d0ef94e36ec	3532	#define UART_C3_ORIE_MASK 0x8u
emilmont	60:3d0ef94e36ec	3533	#define UART_C3_ORIE_SHIFT 3
emilmont	60:3d0ef94e36ec	3534	#define UART_C3_TXINV_MASK 0x10u
emilmont	60:3d0ef94e36ec	3535	#define UART_C3_TXINV_SHIFT 4
emilmont	60:3d0ef94e36ec	3536	#define UART_C3_TXDIR_MASK 0x20u
emilmont	60:3d0ef94e36ec	3537	#define UART_C3_TXDIR_SHIFT 5
emilmont	60:3d0ef94e36ec	3538	#define UART_C3_T8_MASK 0x40u
emilmont	60:3d0ef94e36ec	3539	#define UART_C3_T8_SHIFT 6
emilmont	60:3d0ef94e36ec	3540	#define UART_C3_R8_MASK 0x80u
emilmont	60:3d0ef94e36ec	3541	#define UART_C3_R8_SHIFT 7
emilmont	60:3d0ef94e36ec	3542	/* D Bit Fields */
emilmont	60:3d0ef94e36ec	3543	#define UART_D_R0T0_MASK 0x1u
emilmont	60:3d0ef94e36ec	3544	#define UART_D_R0T0_SHIFT 0
emilmont	60:3d0ef94e36ec	3545	#define UART_D_R1T1_MASK 0x2u
emilmont	60:3d0ef94e36ec	3546	#define UART_D_R1T1_SHIFT 1
emilmont	60:3d0ef94e36ec	3547	#define UART_D_R2T2_MASK 0x4u
emilmont	60:3d0ef94e36ec	3548	#define UART_D_R2T2_SHIFT 2
emilmont	60:3d0ef94e36ec	3549	#define UART_D_R3T3_MASK 0x8u
emilmont	60:3d0ef94e36ec	3550	#define UART_D_R3T3_SHIFT 3
emilmont	60:3d0ef94e36ec	3551	#define UART_D_R4T4_MASK 0x10u
emilmont	60:3d0ef94e36ec	3552	#define UART_D_R4T4_SHIFT 4
emilmont	60:3d0ef94e36ec	3553	#define UART_D_R5T5_MASK 0x20u
emilmont	60:3d0ef94e36ec	3554	#define UART_D_R5T5_SHIFT 5
emilmont	60:3d0ef94e36ec	3555	#define UART_D_R6T6_MASK 0x40u
emilmont	60:3d0ef94e36ec	3556	#define UART_D_R6T6_SHIFT 6
emilmont	60:3d0ef94e36ec	3557	#define UART_D_R7T7_MASK 0x80u
emilmont	60:3d0ef94e36ec	3558	#define UART_D_R7T7_SHIFT 7
emilmont	60:3d0ef94e36ec	3559	/* C4 Bit Fields */
emilmont	60:3d0ef94e36ec	3560	#define UART_C4_LBKDDMAS_MASK 0x8u
emilmont	60:3d0ef94e36ec	3561	#define UART_C4_LBKDDMAS_SHIFT 3
emilmont	60:3d0ef94e36ec	3562	#define UART_C4_ILDMAS_MASK 0x10u
emilmont	60:3d0ef94e36ec	3563	#define UART_C4_ILDMAS_SHIFT 4
emilmont	60:3d0ef94e36ec	3564	#define UART_C4_RDMAS_MASK 0x20u
emilmont	60:3d0ef94e36ec	3565	#define UART_C4_RDMAS_SHIFT 5
emilmont	60:3d0ef94e36ec	3566	#define UART_C4_TCDMAS_MASK 0x40u
emilmont	60:3d0ef94e36ec	3567	#define UART_C4_TCDMAS_SHIFT 6
emilmont	60:3d0ef94e36ec	3568	#define UART_C4_TDMAS_MASK 0x80u
emilmont	60:3d0ef94e36ec	3569	#define UART_C4_TDMAS_SHIFT 7
emilmont	60:3d0ef94e36ec	3570
emilmont	60:3d0ef94e36ec	3571	/**
emilmont	60:3d0ef94e36ec	3572	* @}
emilmont	60:3d0ef94e36ec	3573	/ / end of group UART_Register_Masks */
emilmont	60:3d0ef94e36ec	3574
emilmont	60:3d0ef94e36ec	3575
emilmont	60:3d0ef94e36ec	3576	/* UART - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	3577	/** Peripheral UART1 base address */
emilmont	60:3d0ef94e36ec	3578	#define UART1_BASE (0x4006B000u)
emilmont	60:3d0ef94e36ec	3579	/** Peripheral UART1 base pointer */
emilmont	60:3d0ef94e36ec	3580	#define UART1 ((UART_Type *)UART1_BASE)
emilmont	60:3d0ef94e36ec	3581	/** Peripheral UART2 base address */
emilmont	60:3d0ef94e36ec	3582	#define UART2_BASE (0x4006C000u)
emilmont	60:3d0ef94e36ec	3583	/** Peripheral UART2 base pointer */
emilmont	60:3d0ef94e36ec	3584	#define UART2 ((UART_Type *)UART2_BASE)
emilmont	60:3d0ef94e36ec	3585	/** Array initializer of UART peripheral base pointers */
emilmont	60:3d0ef94e36ec	3586	#define UART_BASES { UART1, UART2 }
emilmont	60:3d0ef94e36ec	3587
emilmont	60:3d0ef94e36ec	3588	/**
emilmont	60:3d0ef94e36ec	3589	* @}
emilmont	60:3d0ef94e36ec	3590	/ / end of group UART_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	3591
emilmont	60:3d0ef94e36ec	3592
emilmont	60:3d0ef94e36ec	3593	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3594	-- UARTLP Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3595	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3596
emilmont	60:3d0ef94e36ec	3597	/**
emilmont	60:3d0ef94e36ec	3598	* @addtogroup UARTLP_Peripheral_Access_Layer UARTLP Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3599	* @{
emilmont	60:3d0ef94e36ec	3600	*/
emilmont	60:3d0ef94e36ec	3601
emilmont	60:3d0ef94e36ec	3602	/** UARTLP - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	3603	typedef struct {
emilmont	60:3d0ef94e36ec	3604	__IO uint8_t BDH; /*< UART Baud Rate Register High, offset: 0x0 /
emilmont	60:3d0ef94e36ec	3605	__IO uint8_t BDL; /*< UART Baud Rate Register Low, offset: 0x1 /
emilmont	60:3d0ef94e36ec	3606	__IO uint8_t C1; /*< UART Control Register 1, offset: 0x2 /
emilmont	60:3d0ef94e36ec	3607	__IO uint8_t C2; /*< UART Control Register 2, offset: 0x3 /
emilmont	60:3d0ef94e36ec	3608	__IO uint8_t S1; /*< UART Status Register 1, offset: 0x4 /
emilmont	60:3d0ef94e36ec	3609	__IO uint8_t S2; /*< UART Status Register 2, offset: 0x5 /
emilmont	60:3d0ef94e36ec	3610	__IO uint8_t C3; /*< UART Control Register 3, offset: 0x6 /
emilmont	60:3d0ef94e36ec	3611	__IO uint8_t D; /*< UART Data Register, offset: 0x7 /
emilmont	60:3d0ef94e36ec	3612	__IO uint8_t MA1; /*< UART Match Address Registers 1, offset: 0x8 /
emilmont	60:3d0ef94e36ec	3613	__IO uint8_t MA2; /*< UART Match Address Registers 2, offset: 0x9 /
emilmont	60:3d0ef94e36ec	3614	__IO uint8_t C4; /*< UART Control Register 4, offset: 0xA /
emilmont	60:3d0ef94e36ec	3615	__IO uint8_t C5; /*< UART Control Register 5, offset: 0xB /
emilmont	60:3d0ef94e36ec	3616	} UARTLP_Type;
emilmont	60:3d0ef94e36ec	3617
emilmont	60:3d0ef94e36ec	3618	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3619	-- UARTLP Register Masks
emilmont	60:3d0ef94e36ec	3620	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3621
emilmont	60:3d0ef94e36ec	3622	/**
emilmont	60:3d0ef94e36ec	3623	* @addtogroup UARTLP_Register_Masks UARTLP Register Masks
emilmont	60:3d0ef94e36ec	3624	* @{
emilmont	60:3d0ef94e36ec	3625	*/
emilmont	60:3d0ef94e36ec	3626
emilmont	60:3d0ef94e36ec	3627	/* BDH Bit Fields */
emilmont	60:3d0ef94e36ec	3628	#define UARTLP_BDH_SBR_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	3629	#define UARTLP_BDH_SBR_SHIFT 0
emilmont	60:3d0ef94e36ec	3630	#define UARTLP_BDH_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDH_SBR_SHIFT))&UARTLP_BDH_SBR_MASK)
emilmont	60:3d0ef94e36ec	3631	#define UARTLP_BDH_SBNS_MASK 0x20u
emilmont	60:3d0ef94e36ec	3632	#define UARTLP_BDH_SBNS_SHIFT 5
emilmont	60:3d0ef94e36ec	3633	#define UARTLP_BDH_RXEDGIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	3634	#define UARTLP_BDH_RXEDGIE_SHIFT 6
emilmont	60:3d0ef94e36ec	3635	#define UARTLP_BDH_LBKDIE_MASK 0x80u
emilmont	60:3d0ef94e36ec	3636	#define UARTLP_BDH_LBKDIE_SHIFT 7
emilmont	60:3d0ef94e36ec	3637	/* BDL Bit Fields */
emilmont	60:3d0ef94e36ec	3638	#define UARTLP_BDL_SBR_MASK 0xFFu
emilmont	60:3d0ef94e36ec	3639	#define UARTLP_BDL_SBR_SHIFT 0
emilmont	60:3d0ef94e36ec	3640	#define UARTLP_BDL_SBR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_BDL_SBR_SHIFT))&UARTLP_BDL_SBR_MASK)
emilmont	60:3d0ef94e36ec	3641	/* C1 Bit Fields */
emilmont	60:3d0ef94e36ec	3642	#define UARTLP_C1_PT_MASK 0x1u
emilmont	60:3d0ef94e36ec	3643	#define UARTLP_C1_PT_SHIFT 0
emilmont	60:3d0ef94e36ec	3644	#define UARTLP_C1_PE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3645	#define UARTLP_C1_PE_SHIFT 1
emilmont	60:3d0ef94e36ec	3646	#define UARTLP_C1_ILT_MASK 0x4u
emilmont	60:3d0ef94e36ec	3647	#define UARTLP_C1_ILT_SHIFT 2
emilmont	60:3d0ef94e36ec	3648	#define UARTLP_C1_WAKE_MASK 0x8u
emilmont	60:3d0ef94e36ec	3649	#define UARTLP_C1_WAKE_SHIFT 3
emilmont	60:3d0ef94e36ec	3650	#define UARTLP_C1_M_MASK 0x10u
emilmont	60:3d0ef94e36ec	3651	#define UARTLP_C1_M_SHIFT 4
emilmont	60:3d0ef94e36ec	3652	#define UARTLP_C1_RSRC_MASK 0x20u
emilmont	60:3d0ef94e36ec	3653	#define UARTLP_C1_RSRC_SHIFT 5
emilmont	60:3d0ef94e36ec	3654	#define UARTLP_C1_DOZEEN_MASK 0x40u
emilmont	60:3d0ef94e36ec	3655	#define UARTLP_C1_DOZEEN_SHIFT 6
emilmont	60:3d0ef94e36ec	3656	#define UARTLP_C1_LOOPS_MASK 0x80u
emilmont	60:3d0ef94e36ec	3657	#define UARTLP_C1_LOOPS_SHIFT 7
emilmont	60:3d0ef94e36ec	3658	/* C2 Bit Fields */
emilmont	60:3d0ef94e36ec	3659	#define UARTLP_C2_SBK_MASK 0x1u
emilmont	60:3d0ef94e36ec	3660	#define UARTLP_C2_SBK_SHIFT 0
emilmont	60:3d0ef94e36ec	3661	#define UARTLP_C2_RWU_MASK 0x2u
emilmont	60:3d0ef94e36ec	3662	#define UARTLP_C2_RWU_SHIFT 1
emilmont	60:3d0ef94e36ec	3663	#define UARTLP_C2_RE_MASK 0x4u
emilmont	60:3d0ef94e36ec	3664	#define UARTLP_C2_RE_SHIFT 2
emilmont	60:3d0ef94e36ec	3665	#define UARTLP_C2_TE_MASK 0x8u
emilmont	60:3d0ef94e36ec	3666	#define UARTLP_C2_TE_SHIFT 3
emilmont	60:3d0ef94e36ec	3667	#define UARTLP_C2_ILIE_MASK 0x10u
emilmont	60:3d0ef94e36ec	3668	#define UARTLP_C2_ILIE_SHIFT 4
emilmont	60:3d0ef94e36ec	3669	#define UARTLP_C2_RIE_MASK 0x20u
emilmont	60:3d0ef94e36ec	3670	#define UARTLP_C2_RIE_SHIFT 5
emilmont	60:3d0ef94e36ec	3671	#define UARTLP_C2_TCIE_MASK 0x40u
emilmont	60:3d0ef94e36ec	3672	#define UARTLP_C2_TCIE_SHIFT 6
emilmont	60:3d0ef94e36ec	3673	#define UARTLP_C2_TIE_MASK 0x80u
emilmont	60:3d0ef94e36ec	3674	#define UARTLP_C2_TIE_SHIFT 7
emilmont	60:3d0ef94e36ec	3675	/* S1 Bit Fields */
emilmont	60:3d0ef94e36ec	3676	#define UARTLP_S1_PF_MASK 0x1u
emilmont	60:3d0ef94e36ec	3677	#define UARTLP_S1_PF_SHIFT 0
emilmont	60:3d0ef94e36ec	3678	#define UARTLP_S1_FE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3679	#define UARTLP_S1_FE_SHIFT 1
emilmont	60:3d0ef94e36ec	3680	#define UARTLP_S1_NF_MASK 0x4u
emilmont	60:3d0ef94e36ec	3681	#define UARTLP_S1_NF_SHIFT 2
emilmont	60:3d0ef94e36ec	3682	#define UARTLP_S1_OR_MASK 0x8u
emilmont	60:3d0ef94e36ec	3683	#define UARTLP_S1_OR_SHIFT 3
emilmont	60:3d0ef94e36ec	3684	#define UARTLP_S1_IDLE_MASK 0x10u
emilmont	60:3d0ef94e36ec	3685	#define UARTLP_S1_IDLE_SHIFT 4
emilmont	60:3d0ef94e36ec	3686	#define UARTLP_S1_RDRF_MASK 0x20u
emilmont	60:3d0ef94e36ec	3687	#define UARTLP_S1_RDRF_SHIFT 5
emilmont	60:3d0ef94e36ec	3688	#define UARTLP_S1_TC_MASK 0x40u
emilmont	60:3d0ef94e36ec	3689	#define UARTLP_S1_TC_SHIFT 6
emilmont	60:3d0ef94e36ec	3690	#define UARTLP_S1_TDRE_MASK 0x80u
emilmont	60:3d0ef94e36ec	3691	#define UARTLP_S1_TDRE_SHIFT 7
emilmont	60:3d0ef94e36ec	3692	/* S2 Bit Fields */
emilmont	60:3d0ef94e36ec	3693	#define UARTLP_S2_RAF_MASK 0x1u
emilmont	60:3d0ef94e36ec	3694	#define UARTLP_S2_RAF_SHIFT 0
emilmont	60:3d0ef94e36ec	3695	#define UARTLP_S2_LBKDE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3696	#define UARTLP_S2_LBKDE_SHIFT 1
emilmont	60:3d0ef94e36ec	3697	#define UARTLP_S2_BRK13_MASK 0x4u
emilmont	60:3d0ef94e36ec	3698	#define UARTLP_S2_BRK13_SHIFT 2
emilmont	60:3d0ef94e36ec	3699	#define UARTLP_S2_RWUID_MASK 0x8u
emilmont	60:3d0ef94e36ec	3700	#define UARTLP_S2_RWUID_SHIFT 3
emilmont	60:3d0ef94e36ec	3701	#define UARTLP_S2_RXINV_MASK 0x10u
emilmont	60:3d0ef94e36ec	3702	#define UARTLP_S2_RXINV_SHIFT 4
emilmont	60:3d0ef94e36ec	3703	#define UARTLP_S2_MSBF_MASK 0x20u
emilmont	60:3d0ef94e36ec	3704	#define UARTLP_S2_MSBF_SHIFT 5
emilmont	60:3d0ef94e36ec	3705	#define UARTLP_S2_RXEDGIF_MASK 0x40u
emilmont	60:3d0ef94e36ec	3706	#define UARTLP_S2_RXEDGIF_SHIFT 6
emilmont	60:3d0ef94e36ec	3707	#define UARTLP_S2_LBKDIF_MASK 0x80u
emilmont	60:3d0ef94e36ec	3708	#define UARTLP_S2_LBKDIF_SHIFT 7
emilmont	60:3d0ef94e36ec	3709	/* C3 Bit Fields */
emilmont	60:3d0ef94e36ec	3710	#define UARTLP_C3_PEIE_MASK 0x1u
emilmont	60:3d0ef94e36ec	3711	#define UARTLP_C3_PEIE_SHIFT 0
emilmont	60:3d0ef94e36ec	3712	#define UARTLP_C3_FEIE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3713	#define UARTLP_C3_FEIE_SHIFT 1
emilmont	60:3d0ef94e36ec	3714	#define UARTLP_C3_NEIE_MASK 0x4u
emilmont	60:3d0ef94e36ec	3715	#define UARTLP_C3_NEIE_SHIFT 2
emilmont	60:3d0ef94e36ec	3716	#define UARTLP_C3_ORIE_MASK 0x8u
emilmont	60:3d0ef94e36ec	3717	#define UARTLP_C3_ORIE_SHIFT 3
emilmont	60:3d0ef94e36ec	3718	#define UARTLP_C3_TXINV_MASK 0x10u
emilmont	60:3d0ef94e36ec	3719	#define UARTLP_C3_TXINV_SHIFT 4
emilmont	60:3d0ef94e36ec	3720	#define UARTLP_C3_TXDIR_MASK 0x20u
emilmont	60:3d0ef94e36ec	3721	#define UARTLP_C3_TXDIR_SHIFT 5
emilmont	60:3d0ef94e36ec	3722	#define UARTLP_C3_R9T8_MASK 0x40u
emilmont	60:3d0ef94e36ec	3723	#define UARTLP_C3_R9T8_SHIFT 6
emilmont	60:3d0ef94e36ec	3724	#define UARTLP_C3_R8T9_MASK 0x80u
emilmont	60:3d0ef94e36ec	3725	#define UARTLP_C3_R8T9_SHIFT 7
emilmont	60:3d0ef94e36ec	3726	/* D Bit Fields */
emilmont	60:3d0ef94e36ec	3727	#define UARTLP_D_R0T0_MASK 0x1u
emilmont	60:3d0ef94e36ec	3728	#define UARTLP_D_R0T0_SHIFT 0
emilmont	60:3d0ef94e36ec	3729	#define UARTLP_D_R1T1_MASK 0x2u
emilmont	60:3d0ef94e36ec	3730	#define UARTLP_D_R1T1_SHIFT 1
emilmont	60:3d0ef94e36ec	3731	#define UARTLP_D_R2T2_MASK 0x4u
emilmont	60:3d0ef94e36ec	3732	#define UARTLP_D_R2T2_SHIFT 2
emilmont	60:3d0ef94e36ec	3733	#define UARTLP_D_R3T3_MASK 0x8u
emilmont	60:3d0ef94e36ec	3734	#define UARTLP_D_R3T3_SHIFT 3
emilmont	60:3d0ef94e36ec	3735	#define UARTLP_D_R4T4_MASK 0x10u
emilmont	60:3d0ef94e36ec	3736	#define UARTLP_D_R4T4_SHIFT 4
emilmont	60:3d0ef94e36ec	3737	#define UARTLP_D_R5T5_MASK 0x20u
emilmont	60:3d0ef94e36ec	3738	#define UARTLP_D_R5T5_SHIFT 5
emilmont	60:3d0ef94e36ec	3739	#define UARTLP_D_R6T6_MASK 0x40u
emilmont	60:3d0ef94e36ec	3740	#define UARTLP_D_R6T6_SHIFT 6
emilmont	60:3d0ef94e36ec	3741	#define UARTLP_D_R7T7_MASK 0x80u
emilmont	60:3d0ef94e36ec	3742	#define UARTLP_D_R7T7_SHIFT 7
emilmont	60:3d0ef94e36ec	3743	/* MA1 Bit Fields */
emilmont	60:3d0ef94e36ec	3744	#define UARTLP_MA1_MA_MASK 0xFFu
emilmont	60:3d0ef94e36ec	3745	#define UARTLP_MA1_MA_SHIFT 0
emilmont	60:3d0ef94e36ec	3746	#define UARTLP_MA1_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA1_MA_SHIFT))&UARTLP_MA1_MA_MASK)
emilmont	60:3d0ef94e36ec	3747	/* MA2 Bit Fields */
emilmont	60:3d0ef94e36ec	3748	#define UARTLP_MA2_MA_MASK 0xFFu
emilmont	60:3d0ef94e36ec	3749	#define UARTLP_MA2_MA_SHIFT 0
emilmont	60:3d0ef94e36ec	3750	#define UARTLP_MA2_MA(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_MA2_MA_SHIFT))&UARTLP_MA2_MA_MASK)
emilmont	60:3d0ef94e36ec	3751	/* C4 Bit Fields */
emilmont	60:3d0ef94e36ec	3752	#define UARTLP_C4_OSR_MASK 0x1Fu
emilmont	60:3d0ef94e36ec	3753	#define UARTLP_C4_OSR_SHIFT 0
emilmont	60:3d0ef94e36ec	3754	#define UARTLP_C4_OSR(x) (((uint8_t)(((uint8_t)(x))<<UARTLP_C4_OSR_SHIFT))&UARTLP_C4_OSR_MASK)
emilmont	60:3d0ef94e36ec	3755	#define UARTLP_C4_M10_MASK 0x20u
emilmont	60:3d0ef94e36ec	3756	#define UARTLP_C4_M10_SHIFT 5
emilmont	60:3d0ef94e36ec	3757	#define UARTLP_C4_MAEN2_MASK 0x40u
emilmont	60:3d0ef94e36ec	3758	#define UARTLP_C4_MAEN2_SHIFT 6
emilmont	60:3d0ef94e36ec	3759	#define UARTLP_C4_MAEN1_MASK 0x80u
emilmont	60:3d0ef94e36ec	3760	#define UARTLP_C4_MAEN1_SHIFT 7
emilmont	60:3d0ef94e36ec	3761	/* C5 Bit Fields */
emilmont	60:3d0ef94e36ec	3762	#define UARTLP_C5_RESYNCDIS_MASK 0x1u
emilmont	60:3d0ef94e36ec	3763	#define UARTLP_C5_RESYNCDIS_SHIFT 0
emilmont	60:3d0ef94e36ec	3764	#define UARTLP_C5_BOTHEDGE_MASK 0x2u
emilmont	60:3d0ef94e36ec	3765	#define UARTLP_C5_BOTHEDGE_SHIFT 1
emilmont	60:3d0ef94e36ec	3766	#define UARTLP_C5_RDMAE_MASK 0x20u
emilmont	60:3d0ef94e36ec	3767	#define UARTLP_C5_RDMAE_SHIFT 5
emilmont	60:3d0ef94e36ec	3768	#define UARTLP_C5_TDMAE_MASK 0x80u
emilmont	60:3d0ef94e36ec	3769	#define UARTLP_C5_TDMAE_SHIFT 7
emilmont	60:3d0ef94e36ec	3770
emilmont	60:3d0ef94e36ec	3771	/**
emilmont	60:3d0ef94e36ec	3772	* @}
emilmont	60:3d0ef94e36ec	3773	/ / end of group UARTLP_Register_Masks */
emilmont	60:3d0ef94e36ec	3774
emilmont	60:3d0ef94e36ec	3775
emilmont	60:3d0ef94e36ec	3776	/* UARTLP - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	3777	/** Peripheral UART0 base address */
emilmont	60:3d0ef94e36ec	3778	#define UART0_BASE (0x4006A000u)
emilmont	60:3d0ef94e36ec	3779	/** Peripheral UART0 base pointer */
emilmont	60:3d0ef94e36ec	3780	#define UART0 ((UARTLP_Type *)UART0_BASE)
emilmont	60:3d0ef94e36ec	3781	/** Array initializer of UARTLP peripheral base pointers */
emilmont	60:3d0ef94e36ec	3782	#define UARTLP_BASES { UART0 }
emilmont	60:3d0ef94e36ec	3783
emilmont	60:3d0ef94e36ec	3784	/**
emilmont	60:3d0ef94e36ec	3785	* @}
emilmont	60:3d0ef94e36ec	3786	/ / end of group UARTLP_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	3787
emilmont	60:3d0ef94e36ec	3788
emilmont	60:3d0ef94e36ec	3789	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3790	-- USB Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3791	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3792
emilmont	60:3d0ef94e36ec	3793	/**
emilmont	60:3d0ef94e36ec	3794	* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
emilmont	60:3d0ef94e36ec	3795	* @{
emilmont	60:3d0ef94e36ec	3796	*/
emilmont	60:3d0ef94e36ec	3797
emilmont	60:3d0ef94e36ec	3798	/** USB - Register Layout Typedef */
emilmont	60:3d0ef94e36ec	3799	typedef struct {
emilmont	60:3d0ef94e36ec	3800	__I uint8_t PERID; /*< Peripheral ID register, offset: 0x0 /
emilmont	60:3d0ef94e36ec	3801	uint8_t RESERVED_0[3];
emilmont	60:3d0ef94e36ec	3802	__I uint8_t IDCOMP; /*< Peripheral ID Complement register, offset: 0x4 /
emilmont	60:3d0ef94e36ec	3803	uint8_t RESERVED_1[3];
emilmont	60:3d0ef94e36ec	3804	__I uint8_t REV; /*< Peripheral Revision register, offset: 0x8 /
emilmont	60:3d0ef94e36ec	3805	uint8_t RESERVED_2[3];
emilmont	60:3d0ef94e36ec	3806	__I uint8_t ADDINFO; /*< Peripheral Additional Info register, offset: 0xC /
emilmont	60:3d0ef94e36ec	3807	uint8_t RESERVED_3[3];
emilmont	60:3d0ef94e36ec	3808	__IO uint8_t OTGISTAT; /*< OTG Interrupt Status register, offset: 0x10 /
emilmont	60:3d0ef94e36ec	3809	uint8_t RESERVED_4[3];
emilmont	60:3d0ef94e36ec	3810	__IO uint8_t OTGICR; /*< OTG Interrupt Control Register, offset: 0x14 /
emilmont	60:3d0ef94e36ec	3811	uint8_t RESERVED_5[3];
emilmont	60:3d0ef94e36ec	3812	__IO uint8_t OTGSTAT; /*< OTG Status register, offset: 0x18 /
emilmont	60:3d0ef94e36ec	3813	uint8_t RESERVED_6[3];
emilmont	60:3d0ef94e36ec	3814	__IO uint8_t OTGCTL; /*< OTG Control register, offset: 0x1C /
emilmont	60:3d0ef94e36ec	3815	uint8_t RESERVED_7[99];
emilmont	60:3d0ef94e36ec	3816	__IO uint8_t ISTAT; /*< Interrupt Status register, offset: 0x80 /
emilmont	60:3d0ef94e36ec	3817	uint8_t RESERVED_8[3];
emilmont	60:3d0ef94e36ec	3818	__IO uint8_t INTEN; /*< Interrupt Enable register, offset: 0x84 /
emilmont	60:3d0ef94e36ec	3819	uint8_t RESERVED_9[3];
emilmont	60:3d0ef94e36ec	3820	__IO uint8_t ERRSTAT; /*< Error Interrupt Status register, offset: 0x88 /
emilmont	60:3d0ef94e36ec	3821	uint8_t RESERVED_10[3];
emilmont	60:3d0ef94e36ec	3822	__IO uint8_t ERREN; /*< Error Interrupt Enable register, offset: 0x8C /
emilmont	60:3d0ef94e36ec	3823	uint8_t RESERVED_11[3];
emilmont	60:3d0ef94e36ec	3824	__I uint8_t STAT; /*< Status register, offset: 0x90 /
emilmont	60:3d0ef94e36ec	3825	uint8_t RESERVED_12[3];
emilmont	60:3d0ef94e36ec	3826	__IO uint8_t CTL; /*< Control register, offset: 0x94 /
emilmont	60:3d0ef94e36ec	3827	uint8_t RESERVED_13[3];
emilmont	60:3d0ef94e36ec	3828	__IO uint8_t ADDR; /*< Address register, offset: 0x98 /
emilmont	60:3d0ef94e36ec	3829	uint8_t RESERVED_14[3];
emilmont	60:3d0ef94e36ec	3830	__IO uint8_t BDTPAGE1; /*< BDT Page Register 1, offset: 0x9C /
emilmont	60:3d0ef94e36ec	3831	uint8_t RESERVED_15[3];
emilmont	60:3d0ef94e36ec	3832	__IO uint8_t FRMNUML; /*< Frame Number Register Low, offset: 0xA0 /
emilmont	60:3d0ef94e36ec	3833	uint8_t RESERVED_16[3];
emilmont	60:3d0ef94e36ec	3834	__IO uint8_t FRMNUMH; /*< Frame Number Register High, offset: 0xA4 /
emilmont	60:3d0ef94e36ec	3835	uint8_t RESERVED_17[3];
emilmont	60:3d0ef94e36ec	3836	__IO uint8_t TOKEN; /*< Token register, offset: 0xA8 /
emilmont	60:3d0ef94e36ec	3837	uint8_t RESERVED_18[3];
emilmont	60:3d0ef94e36ec	3838	__IO uint8_t SOFTHLD; /*< SOF Threshold Register, offset: 0xAC /
emilmont	60:3d0ef94e36ec	3839	uint8_t RESERVED_19[3];
emilmont	60:3d0ef94e36ec	3840	__IO uint8_t BDTPAGE2; /*< BDT Page Register 2, offset: 0xB0 /
emilmont	60:3d0ef94e36ec	3841	uint8_t RESERVED_20[3];
emilmont	60:3d0ef94e36ec	3842	__IO uint8_t BDTPAGE3; /*< BDT Page Register 3, offset: 0xB4 /
emilmont	60:3d0ef94e36ec	3843	uint8_t RESERVED_21[11];
emilmont	60:3d0ef94e36ec	3844	struct { /* offset: 0xC0, array step: 0x4 */
emilmont	60:3d0ef94e36ec	3845	__IO uint8_t ENDPT; /*< Endpoint Control register, array offset: 0xC0, array step: 0x4 /
emilmont	60:3d0ef94e36ec	3846	uint8_t RESERVED_0[3];
emilmont	60:3d0ef94e36ec	3847	} ENDPOINT[16];
emilmont	60:3d0ef94e36ec	3848	__IO uint8_t USBCTRL; /*< USB Control register, offset: 0x100 /
emilmont	60:3d0ef94e36ec	3849	uint8_t RESERVED_22[3];
emilmont	60:3d0ef94e36ec	3850	__I uint8_t OBSERVE; /*< USB OTG Observe register, offset: 0x104 /
emilmont	60:3d0ef94e36ec	3851	uint8_t RESERVED_23[3];
emilmont	60:3d0ef94e36ec	3852	__IO uint8_t CONTROL; /*< USB OTG Control register, offset: 0x108 /
emilmont	60:3d0ef94e36ec	3853	uint8_t RESERVED_24[3];
emilmont	60:3d0ef94e36ec	3854	__IO uint8_t USBTRC0; /*< USB Transceiver Control Register 0, offset: 0x10C /
emilmont	60:3d0ef94e36ec	3855	} USB_Type;
emilmont	60:3d0ef94e36ec	3856
emilmont	60:3d0ef94e36ec	3857	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	3858	-- USB Register Masks
emilmont	60:3d0ef94e36ec	3859	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	3860
emilmont	60:3d0ef94e36ec	3861	/**
emilmont	60:3d0ef94e36ec	3862	* @addtogroup USB_Register_Masks USB Register Masks
emilmont	60:3d0ef94e36ec	3863	* @{
emilmont	60:3d0ef94e36ec	3864	*/
emilmont	60:3d0ef94e36ec	3865
emilmont	60:3d0ef94e36ec	3866	/* PERID Bit Fields */
emilmont	60:3d0ef94e36ec	3867	#define USB_PERID_ID_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	3868	#define USB_PERID_ID_SHIFT 0
emilmont	60:3d0ef94e36ec	3869	#define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x))<<USB_PERID_ID_SHIFT))&USB_PERID_ID_MASK)
emilmont	60:3d0ef94e36ec	3870	/* IDCOMP Bit Fields */
emilmont	60:3d0ef94e36ec	3871	#define USB_IDCOMP_NID_MASK 0x3Fu
emilmont	60:3d0ef94e36ec	3872	#define USB_IDCOMP_NID_SHIFT 0
emilmont	60:3d0ef94e36ec	3873	#define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x))<<USB_IDCOMP_NID_SHIFT))&USB_IDCOMP_NID_MASK)
emilmont	60:3d0ef94e36ec	3874	/* REV Bit Fields */
emilmont	60:3d0ef94e36ec	3875	#define USB_REV_REV_MASK 0xFFu
emilmont	60:3d0ef94e36ec	3876	#define USB_REV_REV_SHIFT 0
emilmont	60:3d0ef94e36ec	3877	#define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x))<<USB_REV_REV_SHIFT))&USB_REV_REV_MASK)
emilmont	60:3d0ef94e36ec	3878	/* ADDINFO Bit Fields */
emilmont	60:3d0ef94e36ec	3879	#define USB_ADDINFO_IEHOST_MASK 0x1u
emilmont	60:3d0ef94e36ec	3880	#define USB_ADDINFO_IEHOST_SHIFT 0
emilmont	60:3d0ef94e36ec	3881	#define USB_ADDINFO_IRQNUM_MASK 0xF8u
emilmont	60:3d0ef94e36ec	3882	#define USB_ADDINFO_IRQNUM_SHIFT 3
emilmont	60:3d0ef94e36ec	3883	#define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDINFO_IRQNUM_SHIFT))&USB_ADDINFO_IRQNUM_MASK)
emilmont	60:3d0ef94e36ec	3884	/* OTGISTAT Bit Fields */
emilmont	60:3d0ef94e36ec	3885	#define USB_OTGISTAT_AVBUSCHG_MASK 0x1u
emilmont	60:3d0ef94e36ec	3886	#define USB_OTGISTAT_AVBUSCHG_SHIFT 0
emilmont	60:3d0ef94e36ec	3887	#define USB_OTGISTAT_B_SESS_CHG_MASK 0x4u
emilmont	60:3d0ef94e36ec	3888	#define USB_OTGISTAT_B_SESS_CHG_SHIFT 2
emilmont	60:3d0ef94e36ec	3889	#define USB_OTGISTAT_SESSVLDCHG_MASK 0x8u
emilmont	60:3d0ef94e36ec	3890	#define USB_OTGISTAT_SESSVLDCHG_SHIFT 3
emilmont	60:3d0ef94e36ec	3891	#define USB_OTGISTAT_LINE_STATE_CHG_MASK 0x20u
emilmont	60:3d0ef94e36ec	3892	#define USB_OTGISTAT_LINE_STATE_CHG_SHIFT 5
emilmont	60:3d0ef94e36ec	3893	#define USB_OTGISTAT_ONEMSEC_MASK 0x40u
emilmont	60:3d0ef94e36ec	3894	#define USB_OTGISTAT_ONEMSEC_SHIFT 6
emilmont	60:3d0ef94e36ec	3895	#define USB_OTGISTAT_IDCHG_MASK 0x80u
emilmont	60:3d0ef94e36ec	3896	#define USB_OTGISTAT_IDCHG_SHIFT 7
emilmont	60:3d0ef94e36ec	3897	/* OTGICR Bit Fields */
emilmont	60:3d0ef94e36ec	3898	#define USB_OTGICR_AVBUSEN_MASK 0x1u
emilmont	60:3d0ef94e36ec	3899	#define USB_OTGICR_AVBUSEN_SHIFT 0
emilmont	60:3d0ef94e36ec	3900	#define USB_OTGICR_BSESSEN_MASK 0x4u
emilmont	60:3d0ef94e36ec	3901	#define USB_OTGICR_BSESSEN_SHIFT 2
emilmont	60:3d0ef94e36ec	3902	#define USB_OTGICR_SESSVLDEN_MASK 0x8u
emilmont	60:3d0ef94e36ec	3903	#define USB_OTGICR_SESSVLDEN_SHIFT 3
emilmont	60:3d0ef94e36ec	3904	#define USB_OTGICR_LINESTATEEN_MASK 0x20u
emilmont	60:3d0ef94e36ec	3905	#define USB_OTGICR_LINESTATEEN_SHIFT 5
emilmont	60:3d0ef94e36ec	3906	#define USB_OTGICR_ONEMSECEN_MASK 0x40u
emilmont	60:3d0ef94e36ec	3907	#define USB_OTGICR_ONEMSECEN_SHIFT 6
emilmont	60:3d0ef94e36ec	3908	#define USB_OTGICR_IDEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	3909	#define USB_OTGICR_IDEN_SHIFT 7
emilmont	60:3d0ef94e36ec	3910	/* OTGSTAT Bit Fields */
emilmont	60:3d0ef94e36ec	3911	#define USB_OTGSTAT_AVBUSVLD_MASK 0x1u
emilmont	60:3d0ef94e36ec	3912	#define USB_OTGSTAT_AVBUSVLD_SHIFT 0
emilmont	60:3d0ef94e36ec	3913	#define USB_OTGSTAT_BSESSEND_MASK 0x4u
emilmont	60:3d0ef94e36ec	3914	#define USB_OTGSTAT_BSESSEND_SHIFT 2
emilmont	60:3d0ef94e36ec	3915	#define USB_OTGSTAT_SESS_VLD_MASK 0x8u
emilmont	60:3d0ef94e36ec	3916	#define USB_OTGSTAT_SESS_VLD_SHIFT 3
emilmont	60:3d0ef94e36ec	3917	#define USB_OTGSTAT_LINESTATESTABLE_MASK 0x20u
emilmont	60:3d0ef94e36ec	3918	#define USB_OTGSTAT_LINESTATESTABLE_SHIFT 5
emilmont	60:3d0ef94e36ec	3919	#define USB_OTGSTAT_ONEMSECEN_MASK 0x40u
emilmont	60:3d0ef94e36ec	3920	#define USB_OTGSTAT_ONEMSECEN_SHIFT 6
emilmont	60:3d0ef94e36ec	3921	#define USB_OTGSTAT_ID_MASK 0x80u
emilmont	60:3d0ef94e36ec	3922	#define USB_OTGSTAT_ID_SHIFT 7
emilmont	60:3d0ef94e36ec	3923	/* OTGCTL Bit Fields */
emilmont	60:3d0ef94e36ec	3924	#define USB_OTGCTL_OTGEN_MASK 0x4u
emilmont	60:3d0ef94e36ec	3925	#define USB_OTGCTL_OTGEN_SHIFT 2
emilmont	60:3d0ef94e36ec	3926	#define USB_OTGCTL_DMLOW_MASK 0x10u
emilmont	60:3d0ef94e36ec	3927	#define USB_OTGCTL_DMLOW_SHIFT 4
emilmont	60:3d0ef94e36ec	3928	#define USB_OTGCTL_DPLOW_MASK 0x20u
emilmont	60:3d0ef94e36ec	3929	#define USB_OTGCTL_DPLOW_SHIFT 5
emilmont	60:3d0ef94e36ec	3930	#define USB_OTGCTL_DPHIGH_MASK 0x80u
emilmont	60:3d0ef94e36ec	3931	#define USB_OTGCTL_DPHIGH_SHIFT 7
emilmont	60:3d0ef94e36ec	3932	/* ISTAT Bit Fields */
emilmont	60:3d0ef94e36ec	3933	#define USB_ISTAT_USBRST_MASK 0x1u
emilmont	60:3d0ef94e36ec	3934	#define USB_ISTAT_USBRST_SHIFT 0
emilmont	60:3d0ef94e36ec	3935	#define USB_ISTAT_ERROR_MASK 0x2u
emilmont	60:3d0ef94e36ec	3936	#define USB_ISTAT_ERROR_SHIFT 1
emilmont	60:3d0ef94e36ec	3937	#define USB_ISTAT_SOFTOK_MASK 0x4u
emilmont	60:3d0ef94e36ec	3938	#define USB_ISTAT_SOFTOK_SHIFT 2
emilmont	60:3d0ef94e36ec	3939	#define USB_ISTAT_TOKDNE_MASK 0x8u
emilmont	60:3d0ef94e36ec	3940	#define USB_ISTAT_TOKDNE_SHIFT 3
emilmont	60:3d0ef94e36ec	3941	#define USB_ISTAT_SLEEP_MASK 0x10u
emilmont	60:3d0ef94e36ec	3942	#define USB_ISTAT_SLEEP_SHIFT 4
emilmont	60:3d0ef94e36ec	3943	#define USB_ISTAT_RESUME_MASK 0x20u
emilmont	60:3d0ef94e36ec	3944	#define USB_ISTAT_RESUME_SHIFT 5
emilmont	60:3d0ef94e36ec	3945	#define USB_ISTAT_ATTACH_MASK 0x40u
emilmont	60:3d0ef94e36ec	3946	#define USB_ISTAT_ATTACH_SHIFT 6
emilmont	60:3d0ef94e36ec	3947	#define USB_ISTAT_STALL_MASK 0x80u
emilmont	60:3d0ef94e36ec	3948	#define USB_ISTAT_STALL_SHIFT 7
emilmont	60:3d0ef94e36ec	3949	/* INTEN Bit Fields */
emilmont	60:3d0ef94e36ec	3950	#define USB_INTEN_USBRSTEN_MASK 0x1u
emilmont	60:3d0ef94e36ec	3951	#define USB_INTEN_USBRSTEN_SHIFT 0
emilmont	60:3d0ef94e36ec	3952	#define USB_INTEN_ERROREN_MASK 0x2u
emilmont	60:3d0ef94e36ec	3953	#define USB_INTEN_ERROREN_SHIFT 1
emilmont	60:3d0ef94e36ec	3954	#define USB_INTEN_SOFTOKEN_MASK 0x4u
emilmont	60:3d0ef94e36ec	3955	#define USB_INTEN_SOFTOKEN_SHIFT 2
emilmont	60:3d0ef94e36ec	3956	#define USB_INTEN_TOKDNEEN_MASK 0x8u
emilmont	60:3d0ef94e36ec	3957	#define USB_INTEN_TOKDNEEN_SHIFT 3
emilmont	60:3d0ef94e36ec	3958	#define USB_INTEN_SLEEPEN_MASK 0x10u
emilmont	60:3d0ef94e36ec	3959	#define USB_INTEN_SLEEPEN_SHIFT 4
emilmont	60:3d0ef94e36ec	3960	#define USB_INTEN_RESUMEEN_MASK 0x20u
emilmont	60:3d0ef94e36ec	3961	#define USB_INTEN_RESUMEEN_SHIFT 5
emilmont	60:3d0ef94e36ec	3962	#define USB_INTEN_ATTACHEN_MASK 0x40u
emilmont	60:3d0ef94e36ec	3963	#define USB_INTEN_ATTACHEN_SHIFT 6
emilmont	60:3d0ef94e36ec	3964	#define USB_INTEN_STALLEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	3965	#define USB_INTEN_STALLEN_SHIFT 7
emilmont	60:3d0ef94e36ec	3966	/* ERRSTAT Bit Fields */
emilmont	60:3d0ef94e36ec	3967	#define USB_ERRSTAT_PIDERR_MASK 0x1u
emilmont	60:3d0ef94e36ec	3968	#define USB_ERRSTAT_PIDERR_SHIFT 0
emilmont	60:3d0ef94e36ec	3969	#define USB_ERRSTAT_CRC5EOF_MASK 0x2u
emilmont	60:3d0ef94e36ec	3970	#define USB_ERRSTAT_CRC5EOF_SHIFT 1
emilmont	60:3d0ef94e36ec	3971	#define USB_ERRSTAT_CRC16_MASK 0x4u
emilmont	60:3d0ef94e36ec	3972	#define USB_ERRSTAT_CRC16_SHIFT 2
emilmont	60:3d0ef94e36ec	3973	#define USB_ERRSTAT_DFN8_MASK 0x8u
emilmont	60:3d0ef94e36ec	3974	#define USB_ERRSTAT_DFN8_SHIFT 3
emilmont	60:3d0ef94e36ec	3975	#define USB_ERRSTAT_BTOERR_MASK 0x10u
emilmont	60:3d0ef94e36ec	3976	#define USB_ERRSTAT_BTOERR_SHIFT 4
emilmont	60:3d0ef94e36ec	3977	#define USB_ERRSTAT_DMAERR_MASK 0x20u
emilmont	60:3d0ef94e36ec	3978	#define USB_ERRSTAT_DMAERR_SHIFT 5
emilmont	60:3d0ef94e36ec	3979	#define USB_ERRSTAT_BTSERR_MASK 0x80u
emilmont	60:3d0ef94e36ec	3980	#define USB_ERRSTAT_BTSERR_SHIFT 7
emilmont	60:3d0ef94e36ec	3981	/* ERREN Bit Fields */
emilmont	60:3d0ef94e36ec	3982	#define USB_ERREN_PIDERREN_MASK 0x1u
emilmont	60:3d0ef94e36ec	3983	#define USB_ERREN_PIDERREN_SHIFT 0
emilmont	60:3d0ef94e36ec	3984	#define USB_ERREN_CRC5EOFEN_MASK 0x2u
emilmont	60:3d0ef94e36ec	3985	#define USB_ERREN_CRC5EOFEN_SHIFT 1
emilmont	60:3d0ef94e36ec	3986	#define USB_ERREN_CRC16EN_MASK 0x4u
emilmont	60:3d0ef94e36ec	3987	#define USB_ERREN_CRC16EN_SHIFT 2
emilmont	60:3d0ef94e36ec	3988	#define USB_ERREN_DFN8EN_MASK 0x8u
emilmont	60:3d0ef94e36ec	3989	#define USB_ERREN_DFN8EN_SHIFT 3
emilmont	60:3d0ef94e36ec	3990	#define USB_ERREN_BTOERREN_MASK 0x10u
emilmont	60:3d0ef94e36ec	3991	#define USB_ERREN_BTOERREN_SHIFT 4
emilmont	60:3d0ef94e36ec	3992	#define USB_ERREN_DMAERREN_MASK 0x20u
emilmont	60:3d0ef94e36ec	3993	#define USB_ERREN_DMAERREN_SHIFT 5
emilmont	60:3d0ef94e36ec	3994	#define USB_ERREN_BTSERREN_MASK 0x80u
emilmont	60:3d0ef94e36ec	3995	#define USB_ERREN_BTSERREN_SHIFT 7
emilmont	60:3d0ef94e36ec	3996	/* STAT Bit Fields */
emilmont	60:3d0ef94e36ec	3997	#define USB_STAT_ODD_MASK 0x4u
emilmont	60:3d0ef94e36ec	3998	#define USB_STAT_ODD_SHIFT 2
emilmont	60:3d0ef94e36ec	3999	#define USB_STAT_TX_MASK 0x8u
emilmont	60:3d0ef94e36ec	4000	#define USB_STAT_TX_SHIFT 3
emilmont	60:3d0ef94e36ec	4001	#define USB_STAT_ENDP_MASK 0xF0u
emilmont	60:3d0ef94e36ec	4002	#define USB_STAT_ENDP_SHIFT 4
emilmont	60:3d0ef94e36ec	4003	#define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x))<<USB_STAT_ENDP_SHIFT))&USB_STAT_ENDP_MASK)
emilmont	60:3d0ef94e36ec	4004	/* CTL Bit Fields */
emilmont	60:3d0ef94e36ec	4005	#define USB_CTL_USBENSOFEN_MASK 0x1u
emilmont	60:3d0ef94e36ec	4006	#define USB_CTL_USBENSOFEN_SHIFT 0
emilmont	60:3d0ef94e36ec	4007	#define USB_CTL_ODDRST_MASK 0x2u
emilmont	60:3d0ef94e36ec	4008	#define USB_CTL_ODDRST_SHIFT 1
emilmont	60:3d0ef94e36ec	4009	#define USB_CTL_RESUME_MASK 0x4u
emilmont	60:3d0ef94e36ec	4010	#define USB_CTL_RESUME_SHIFT 2
emilmont	60:3d0ef94e36ec	4011	#define USB_CTL_HOSTMODEEN_MASK 0x8u
emilmont	60:3d0ef94e36ec	4012	#define USB_CTL_HOSTMODEEN_SHIFT 3
emilmont	60:3d0ef94e36ec	4013	#define USB_CTL_RESET_MASK 0x10u
emilmont	60:3d0ef94e36ec	4014	#define USB_CTL_RESET_SHIFT 4
emilmont	60:3d0ef94e36ec	4015	#define USB_CTL_TXSUSPENDTOKENBUSY_MASK 0x20u
emilmont	60:3d0ef94e36ec	4016	#define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT 5
emilmont	60:3d0ef94e36ec	4017	#define USB_CTL_SE0_MASK 0x40u
emilmont	60:3d0ef94e36ec	4018	#define USB_CTL_SE0_SHIFT 6
emilmont	60:3d0ef94e36ec	4019	#define USB_CTL_JSTATE_MASK 0x80u
emilmont	60:3d0ef94e36ec	4020	#define USB_CTL_JSTATE_SHIFT 7
emilmont	60:3d0ef94e36ec	4021	/* ADDR Bit Fields */
emilmont	60:3d0ef94e36ec	4022	#define USB_ADDR_ADDR_MASK 0x7Fu
emilmont	60:3d0ef94e36ec	4023	#define USB_ADDR_ADDR_SHIFT 0
emilmont	60:3d0ef94e36ec	4024	#define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x))<<USB_ADDR_ADDR_SHIFT))&USB_ADDR_ADDR_MASK)
emilmont	60:3d0ef94e36ec	4025	#define USB_ADDR_LSEN_MASK 0x80u
emilmont	60:3d0ef94e36ec	4026	#define USB_ADDR_LSEN_SHIFT 7
emilmont	60:3d0ef94e36ec	4027	/* BDTPAGE1 Bit Fields */
emilmont	60:3d0ef94e36ec	4028	#define USB_BDTPAGE1_BDTBA_MASK 0xFEu
emilmont	60:3d0ef94e36ec	4029	#define USB_BDTPAGE1_BDTBA_SHIFT 1
emilmont	60:3d0ef94e36ec	4030	#define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE1_BDTBA_SHIFT))&USB_BDTPAGE1_BDTBA_MASK)
emilmont	60:3d0ef94e36ec	4031	/* FRMNUML Bit Fields */
emilmont	60:3d0ef94e36ec	4032	#define USB_FRMNUML_FRM_MASK 0xFFu
emilmont	60:3d0ef94e36ec	4033	#define USB_FRMNUML_FRM_SHIFT 0
emilmont	60:3d0ef94e36ec	4034	#define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUML_FRM_SHIFT))&USB_FRMNUML_FRM_MASK)
emilmont	60:3d0ef94e36ec	4035	/* FRMNUMH Bit Fields */
emilmont	60:3d0ef94e36ec	4036	#define USB_FRMNUMH_FRM_MASK 0x7u
emilmont	60:3d0ef94e36ec	4037	#define USB_FRMNUMH_FRM_SHIFT 0
emilmont	60:3d0ef94e36ec	4038	#define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x))<<USB_FRMNUMH_FRM_SHIFT))&USB_FRMNUMH_FRM_MASK)
emilmont	60:3d0ef94e36ec	4039	/* TOKEN Bit Fields */
emilmont	60:3d0ef94e36ec	4040	#define USB_TOKEN_TOKENENDPT_MASK 0xFu
emilmont	60:3d0ef94e36ec	4041	#define USB_TOKEN_TOKENENDPT_SHIFT 0
emilmont	60:3d0ef94e36ec	4042	#define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENENDPT_SHIFT))&USB_TOKEN_TOKENENDPT_MASK)
emilmont	60:3d0ef94e36ec	4043	#define USB_TOKEN_TOKENPID_MASK 0xF0u
emilmont	60:3d0ef94e36ec	4044	#define USB_TOKEN_TOKENPID_SHIFT 4
emilmont	60:3d0ef94e36ec	4045	#define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x))<<USB_TOKEN_TOKENPID_SHIFT))&USB_TOKEN_TOKENPID_MASK)
emilmont	60:3d0ef94e36ec	4046	/* SOFTHLD Bit Fields */
emilmont	60:3d0ef94e36ec	4047	#define USB_SOFTHLD_CNT_MASK 0xFFu
emilmont	60:3d0ef94e36ec	4048	#define USB_SOFTHLD_CNT_SHIFT 0
emilmont	60:3d0ef94e36ec	4049	#define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x))<<USB_SOFTHLD_CNT_SHIFT))&USB_SOFTHLD_CNT_MASK)
emilmont	60:3d0ef94e36ec	4050	/* BDTPAGE2 Bit Fields */
emilmont	60:3d0ef94e36ec	4051	#define USB_BDTPAGE2_BDTBA_MASK 0xFFu
emilmont	60:3d0ef94e36ec	4052	#define USB_BDTPAGE2_BDTBA_SHIFT 0
emilmont	60:3d0ef94e36ec	4053	#define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE2_BDTBA_SHIFT))&USB_BDTPAGE2_BDTBA_MASK)
emilmont	60:3d0ef94e36ec	4054	/* BDTPAGE3 Bit Fields */
emilmont	60:3d0ef94e36ec	4055	#define USB_BDTPAGE3_BDTBA_MASK 0xFFu
emilmont	60:3d0ef94e36ec	4056	#define USB_BDTPAGE3_BDTBA_SHIFT 0
emilmont	60:3d0ef94e36ec	4057	#define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x))<<USB_BDTPAGE3_BDTBA_SHIFT))&USB_BDTPAGE3_BDTBA_MASK)
emilmont	60:3d0ef94e36ec	4058	/* ENDPT Bit Fields */
emilmont	60:3d0ef94e36ec	4059	#define USB_ENDPT_EPHSHK_MASK 0x1u
emilmont	60:3d0ef94e36ec	4060	#define USB_ENDPT_EPHSHK_SHIFT 0
emilmont	60:3d0ef94e36ec	4061	#define USB_ENDPT_EPSTALL_MASK 0x2u
emilmont	60:3d0ef94e36ec	4062	#define USB_ENDPT_EPSTALL_SHIFT 1
emilmont	60:3d0ef94e36ec	4063	#define USB_ENDPT_EPTXEN_MASK 0x4u
emilmont	60:3d0ef94e36ec	4064	#define USB_ENDPT_EPTXEN_SHIFT 2
emilmont	60:3d0ef94e36ec	4065	#define USB_ENDPT_EPRXEN_MASK 0x8u
emilmont	60:3d0ef94e36ec	4066	#define USB_ENDPT_EPRXEN_SHIFT 3
emilmont	60:3d0ef94e36ec	4067	#define USB_ENDPT_EPCTLDIS_MASK 0x10u
emilmont	60:3d0ef94e36ec	4068	#define USB_ENDPT_EPCTLDIS_SHIFT 4
emilmont	60:3d0ef94e36ec	4069	#define USB_ENDPT_RETRYDIS_MASK 0x40u
emilmont	60:3d0ef94e36ec	4070	#define USB_ENDPT_RETRYDIS_SHIFT 6
emilmont	60:3d0ef94e36ec	4071	#define USB_ENDPT_HOSTWOHUB_MASK 0x80u
emilmont	60:3d0ef94e36ec	4072	#define USB_ENDPT_HOSTWOHUB_SHIFT 7
emilmont	60:3d0ef94e36ec	4073	/* USBCTRL Bit Fields */
emilmont	60:3d0ef94e36ec	4074	#define USB_USBCTRL_PDE_MASK 0x40u
emilmont	60:3d0ef94e36ec	4075	#define USB_USBCTRL_PDE_SHIFT 6
emilmont	60:3d0ef94e36ec	4076	#define USB_USBCTRL_SUSP_MASK 0x80u
emilmont	60:3d0ef94e36ec	4077	#define USB_USBCTRL_SUSP_SHIFT 7
emilmont	60:3d0ef94e36ec	4078	/* OBSERVE Bit Fields */
emilmont	60:3d0ef94e36ec	4079	#define USB_OBSERVE_DMPD_MASK 0x10u
emilmont	60:3d0ef94e36ec	4080	#define USB_OBSERVE_DMPD_SHIFT 4
emilmont	60:3d0ef94e36ec	4081	#define USB_OBSERVE_DPPD_MASK 0x40u
emilmont	60:3d0ef94e36ec	4082	#define USB_OBSERVE_DPPD_SHIFT 6
emilmont	60:3d0ef94e36ec	4083	#define USB_OBSERVE_DPPU_MASK 0x80u
emilmont	60:3d0ef94e36ec	4084	#define USB_OBSERVE_DPPU_SHIFT 7
emilmont	60:3d0ef94e36ec	4085	/* CONTROL Bit Fields */
emilmont	60:3d0ef94e36ec	4086	#define USB_CONTROL_DPPULLUPNONOTG_MASK 0x10u
emilmont	60:3d0ef94e36ec	4087	#define USB_CONTROL_DPPULLUPNONOTG_SHIFT 4
emilmont	60:3d0ef94e36ec	4088	/* USBTRC0 Bit Fields */
emilmont	60:3d0ef94e36ec	4089	#define USB_USBTRC0_USB_RESUME_INT_MASK 0x1u
emilmont	60:3d0ef94e36ec	4090	#define USB_USBTRC0_USB_RESUME_INT_SHIFT 0
emilmont	60:3d0ef94e36ec	4091	#define USB_USBTRC0_SYNC_DET_MASK 0x2u
emilmont	60:3d0ef94e36ec	4092	#define USB_USBTRC0_SYNC_DET_SHIFT 1
emilmont	60:3d0ef94e36ec	4093	#define USB_USBTRC0_USBRESMEN_MASK 0x20u
emilmont	60:3d0ef94e36ec	4094	#define USB_USBTRC0_USBRESMEN_SHIFT 5
emilmont	60:3d0ef94e36ec	4095	#define USB_USBTRC0_USBRESET_MASK 0x80u
emilmont	60:3d0ef94e36ec	4096	#define USB_USBTRC0_USBRESET_SHIFT 7
emilmont	60:3d0ef94e36ec	4097
emilmont	60:3d0ef94e36ec	4098	/**
emilmont	60:3d0ef94e36ec	4099	* @}
emilmont	60:3d0ef94e36ec	4100	/ / end of group USB_Register_Masks */
emilmont	60:3d0ef94e36ec	4101
emilmont	60:3d0ef94e36ec	4102
emilmont	60:3d0ef94e36ec	4103	/* USB - Peripheral instance base addresses */
emilmont	60:3d0ef94e36ec	4104	/** Peripheral USB0 base address */
emilmont	60:3d0ef94e36ec	4105	#define USB0_BASE (0x40072000u)
emilmont	60:3d0ef94e36ec	4106	/** Peripheral USB0 base pointer */
emilmont	60:3d0ef94e36ec	4107	#define USB0 ((USB_Type *)USB0_BASE)
emilmont	60:3d0ef94e36ec	4108	/** Array initializer of USB peripheral base pointers */
emilmont	60:3d0ef94e36ec	4109	#define USB_BASES { USB0 }
emilmont	60:3d0ef94e36ec	4110
emilmont	60:3d0ef94e36ec	4111	/**
emilmont	60:3d0ef94e36ec	4112	* @}
emilmont	60:3d0ef94e36ec	4113	/ / end of group USB_Peripheral_Access_Layer */
emilmont	60:3d0ef94e36ec	4114
emilmont	60:3d0ef94e36ec	4115
emilmont	60:3d0ef94e36ec	4116	/*
emilmont	60:3d0ef94e36ec	4117	** End of section using anonymous unions
emilmont	60:3d0ef94e36ec	4118	*/
emilmont	60:3d0ef94e36ec	4119
emilmont	60:3d0ef94e36ec	4120	#if defined(__ARMCC_VERSION)
emilmont	60:3d0ef94e36ec	4121	#pragma pop
emilmont	60:3d0ef94e36ec	4122	#elif defined(__CWCC__)
emilmont	60:3d0ef94e36ec	4123	#pragma pop
emilmont	60:3d0ef94e36ec	4124	#elif defined(__GNUC__)
emilmont	60:3d0ef94e36ec	4125	/* leave anonymous unions enabled */
emilmont	60:3d0ef94e36ec	4126	#elif defined(__IAR_SYSTEMS_ICC__)
emilmont	60:3d0ef94e36ec	4127	#pragma language=default
emilmont	60:3d0ef94e36ec	4128	#else
emilmont	60:3d0ef94e36ec	4129	#error Not supported compiler type
emilmont	60:3d0ef94e36ec	4130	#endif
emilmont	60:3d0ef94e36ec	4131
emilmont	60:3d0ef94e36ec	4132	/**
emilmont	60:3d0ef94e36ec	4133	* @}
emilmont	60:3d0ef94e36ec	4134	/ / end of group Peripheral_access_layer */
emilmont	60:3d0ef94e36ec	4135
emilmont	60:3d0ef94e36ec	4136
emilmont	60:3d0ef94e36ec	4137	/* ----------------------------------------------------------------------------
emilmont	60:3d0ef94e36ec	4138	-- Backward Compatibility
emilmont	60:3d0ef94e36ec	4139	---------------------------------------------------------------------------- */
emilmont	60:3d0ef94e36ec	4140
emilmont	60:3d0ef94e36ec	4141	/**
emilmont	60:3d0ef94e36ec	4142	* @addtogroup Backward_Compatibility_Symbols Backward Compatibility
emilmont	60:3d0ef94e36ec	4143	* @{
emilmont	60:3d0ef94e36ec	4144	*/
emilmont	60:3d0ef94e36ec	4145
emilmont	60:3d0ef94e36ec	4146	/* No backward compatibility issues. */
emilmont	60:3d0ef94e36ec	4147
emilmont	60:3d0ef94e36ec	4148	/**
emilmont	60:3d0ef94e36ec	4149	* @}
emilmont	60:3d0ef94e36ec	4150	/ / end of group Backward_Compatibility_Symbols */
emilmont	60:3d0ef94e36ec	4151
emilmont	60:3d0ef94e36ec	4152
emilmont	60:3d0ef94e36ec	4153	#endif /* #if !defined(MKL25Z4_H_) */
emilmont	60:3d0ef94e36ec	4154
emilmont	60:3d0ef94e36ec	4155	/* MKL25Z4.h, eof. */

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Type:	Library
Created:	05 Apr 2016
Imports:	0
Forks:	0
Commits:	119
Dependents:	0
Dependencies:	0
Followers:	1

TARGET_KL25Z/MKL25Z4.h@64:e3affc9e7238, 2013-08-05 (annotated)

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