Ricardo Benitez / mbed

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Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32f4xx_hal_nor.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Parent:
85:024bf7f99721
Child:
99:dbbf35b96557
Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_nor.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V1.1.0
Kojto 90:cb3d968589d8 6 * @date 19-June-2014
emilmont 77:869cf507173a 7 * @brief Header file of NOR HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_NOR_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_NOR_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 48 #include "stm32f4xx_ll_fsmc.h"
emilmont 77:869cf507173a 49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 52 #include "stm32f4xx_ll_fmc.h"
emilmont 77:869cf507173a 53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 56 * @{
emilmont 77:869cf507173a 57 */
emilmont 77:869cf507173a 58
emilmont 77:869cf507173a 59 /** @addtogroup NOR
emilmont 77:869cf507173a 60 * @{
emilmont 77:869cf507173a 61 */
emilmont 77:869cf507173a 62
emilmont 77:869cf507173a 63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
emilmont 77:869cf507173a 64
bogdanm 85:024bf7f99721 65 /* Exported typedef ----------------------------------------------------------*/
emilmont 77:869cf507173a 66 /**
emilmont 77:869cf507173a 67 * @brief HAL SRAM State structures definition
emilmont 77:869cf507173a 68 */
emilmont 77:869cf507173a 69 typedef enum
emilmont 77:869cf507173a 70 {
emilmont 77:869cf507173a 71 HAL_NOR_STATE_RESET = 0x00, /*!< NOR not yet initialized or disabled */
emilmont 77:869cf507173a 72 HAL_NOR_STATE_READY = 0x01, /*!< NOR initialized and ready for use */
emilmont 77:869cf507173a 73 HAL_NOR_STATE_BUSY = 0x02, /*!< NOR internal processing is ongoing */
bogdanm 85:024bf7f99721 74 HAL_NOR_STATE_ERROR = 0x03, /*!< NOR error state */
bogdanm 85:024bf7f99721 75 HAL_NOR_STATE_PROTECTED = 0x04 /*!< NOR NORSRAM device write protected */
bogdanm 85:024bf7f99721 76 }HAL_NOR_StateTypeDef;
emilmont 77:869cf507173a 77
emilmont 77:869cf507173a 78 /**
emilmont 77:869cf507173a 79 * @brief FMC NOR Status typedef
emilmont 77:869cf507173a 80 */
emilmont 77:869cf507173a 81 typedef enum
emilmont 77:869cf507173a 82 {
emilmont 77:869cf507173a 83 NOR_SUCCESS = 0,
emilmont 77:869cf507173a 84 NOR_ONGOING,
emilmont 77:869cf507173a 85 NOR_ERROR,
emilmont 77:869cf507173a 86 NOR_TIMEOUT
bogdanm 85:024bf7f99721 87 }NOR_StatusTypedef;
emilmont 77:869cf507173a 88
emilmont 77:869cf507173a 89 /**
emilmont 77:869cf507173a 90 * @brief FMC NOR ID typedef
emilmont 77:869cf507173a 91 */
emilmont 77:869cf507173a 92 typedef struct
emilmont 77:869cf507173a 93 {
emilmont 77:869cf507173a 94 uint16_t Manufacturer_Code; /*!< Defines the device's manufacturer code used to identify the memory */
bogdanm 85:024bf7f99721 95
bogdanm 85:024bf7f99721 96 uint16_t Device_Code1;
bogdanm 85:024bf7f99721 97
bogdanm 85:024bf7f99721 98 uint16_t Device_Code2;
bogdanm 85:024bf7f99721 99
bogdanm 85:024bf7f99721 100 uint16_t Device_Code3; /*!< Defines the devices' codes used to identify the memory.
emilmont 77:869cf507173a 101 These codes can be accessed by performing read operations with specific
emilmont 77:869cf507173a 102 control signals and addresses set.They can also be accessed by issuing
bogdanm 85:024bf7f99721 103 an Auto Select command */
emilmont 77:869cf507173a 104 }NOR_IDTypeDef;
emilmont 77:869cf507173a 105
emilmont 77:869cf507173a 106 /**
emilmont 77:869cf507173a 107 * @brief FMC NOR CFI typedef
emilmont 77:869cf507173a 108 */
emilmont 77:869cf507173a 109 typedef struct
emilmont 77:869cf507173a 110 {
emilmont 77:869cf507173a 111 /*!< Defines the information stored in the memory's Common flash interface
emilmont 77:869cf507173a 112 which contains a description of various electrical and timing parameters,
emilmont 77:869cf507173a 113 density information and functions supported by the memory */
bogdanm 85:024bf7f99721 114
bogdanm 85:024bf7f99721 115 uint16_t CFI_1;
bogdanm 85:024bf7f99721 116
bogdanm 85:024bf7f99721 117 uint16_t CFI_2;
bogdanm 85:024bf7f99721 118
bogdanm 85:024bf7f99721 119 uint16_t CFI_3;
bogdanm 85:024bf7f99721 120
bogdanm 85:024bf7f99721 121 uint16_t CFI_4;
emilmont 77:869cf507173a 122 }NOR_CFITypeDef;
emilmont 77:869cf507173a 123
emilmont 77:869cf507173a 124 /**
bogdanm 85:024bf7f99721 125 * @brief NOR handle Structure definition
emilmont 77:869cf507173a 126 */
emilmont 77:869cf507173a 127 typedef struct
emilmont 77:869cf507173a 128 {
bogdanm 85:024bf7f99721 129 FMC_NORSRAM_TypeDef *Instance; /*!< Register base address */
bogdanm 85:024bf7f99721 130
emilmont 77:869cf507173a 131 FMC_NORSRAM_EXTENDED_TypeDef *Extended; /*!< Extended mode register base address */
bogdanm 85:024bf7f99721 132
emilmont 77:869cf507173a 133 FMC_NORSRAM_InitTypeDef Init; /*!< NOR device control configuration parameters */
emilmont 77:869cf507173a 134
bogdanm 85:024bf7f99721 135 HAL_LockTypeDef Lock; /*!< NOR locking object */
bogdanm 85:024bf7f99721 136
emilmont 77:869cf507173a 137 __IO HAL_NOR_StateTypeDef State; /*!< NOR device access state */
bogdanm 85:024bf7f99721 138
emilmont 77:869cf507173a 139 }NOR_HandleTypeDef;
emilmont 77:869cf507173a 140
emilmont 77:869cf507173a 141 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 142 /** @defgroup NOR_Exported_Constants
emilmont 77:869cf507173a 143 * @{
emilmont 77:869cf507173a 144 */
emilmont 77:869cf507173a 145 /* NOR device IDs addresses */
emilmont 77:869cf507173a 146 #define MC_ADDRESS ((uint16_t)0x0000)
emilmont 77:869cf507173a 147 #define DEVICE_CODE1_ADDR ((uint16_t)0x0001)
emilmont 77:869cf507173a 148 #define DEVICE_CODE2_ADDR ((uint16_t)0x000E)
emilmont 77:869cf507173a 149 #define DEVICE_CODE3_ADDR ((uint16_t)0x000F)
emilmont 77:869cf507173a 150
emilmont 77:869cf507173a 151 /* NOR CFI IDs addresses */
emilmont 77:869cf507173a 152 #define CFI1_ADDRESS ((uint16_t)0x61)
emilmont 77:869cf507173a 153 #define CFI2_ADDRESS ((uint16_t)0x62)
emilmont 77:869cf507173a 154 #define CFI3_ADDRESS ((uint16_t)0x63)
emilmont 77:869cf507173a 155 #define CFI4_ADDRESS ((uint16_t)0x64)
emilmont 77:869cf507173a 156
emilmont 77:869cf507173a 157 /* NOR operation wait timeout */
emilmont 77:869cf507173a 158 #define NOR_TMEOUT ((uint16_t)0xFFFF)
emilmont 77:869cf507173a 159
Kojto 90:cb3d968589d8 160 /* NOR memory data width */
Kojto 90:cb3d968589d8 161 #define NOR_MEMORY_8B ((uint8_t)0x0)
Kojto 90:cb3d968589d8 162 #define NOR_MEMORY_16B ((uint8_t)0x1)
emilmont 77:869cf507173a 163
emilmont 77:869cf507173a 164 /* NOR memory device read/write start address */
Kojto 90:cb3d968589d8 165 #define NOR_MEMORY_ADRESS1 ((uint32_t)0x60000000)
Kojto 90:cb3d968589d8 166 #define NOR_MEMORY_ADRESS2 ((uint32_t)0x64000000)
Kojto 90:cb3d968589d8 167 #define NOR_MEMORY_ADRESS3 ((uint32_t)0x68000000)
Kojto 90:cb3d968589d8 168 #define NOR_MEMORY_ADRESS4 ((uint32_t)0x6C000000)
emilmont 77:869cf507173a 169
emilmont 77:869cf507173a 170 /**
emilmont 77:869cf507173a 171 * @}
emilmont 77:869cf507173a 172 */
emilmont 77:869cf507173a 173
emilmont 77:869cf507173a 174 /* Exported macro ------------------------------------------------------------*/
bogdanm 85:024bf7f99721 175
bogdanm 85:024bf7f99721 176 /** @brief Reset NOR handle state
bogdanm 85:024bf7f99721 177 * @param __HANDLE__: specifies the NOR handle.
bogdanm 85:024bf7f99721 178 * @retval None
bogdanm 85:024bf7f99721 179 */
bogdanm 85:024bf7f99721 180 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
bogdanm 85:024bf7f99721 181
emilmont 77:869cf507173a 182 /**
emilmont 77:869cf507173a 183 * @brief NOR memory address shifting.
emilmont 77:869cf507173a 184 * @param __ADDRESS__: NOR memory address
emilmont 77:869cf507173a 185 * @retval NOR shifted address value
emilmont 77:869cf507173a 186 */
Kojto 90:cb3d968589d8 187 #define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) (((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_8B)? ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):\
Kojto 90:cb3d968589d8 188 ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__))))
emilmont 77:869cf507173a 189
emilmont 77:869cf507173a 190 /**
emilmont 77:869cf507173a 191 * @brief NOR memory write data to specified address.
emilmont 77:869cf507173a 192 * @param __ADDRESS__: NOR memory address
emilmont 77:869cf507173a 193 * @param __DATA__: Data to write
emilmont 77:869cf507173a 194 * @retval None
emilmont 77:869cf507173a 195 */
bogdanm 81:7d30d6019079 196 #define __NOR_WRITE(__ADDRESS__, __DATA__) (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
emilmont 77:869cf507173a 197
emilmont 77:869cf507173a 198 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 199
bogdanm 85:024bf7f99721 200 /* Initialization/de-initialization functions ********************************/
emilmont 77:869cf507173a 201 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
emilmont 77:869cf507173a 202 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
bogdanm 81:7d30d6019079 203 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
bogdanm 81:7d30d6019079 204 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
bogdanm 81:7d30d6019079 205 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
emilmont 77:869cf507173a 206
bogdanm 85:024bf7f99721 207 /* I/O operation functions ***************************************************/
emilmont 77:869cf507173a 208 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
emilmont 77:869cf507173a 209 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
emilmont 77:869cf507173a 210 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
emilmont 77:869cf507173a 211 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
emilmont 77:869cf507173a 212
emilmont 77:869cf507173a 213 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
emilmont 77:869cf507173a 214 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
emilmont 77:869cf507173a 215
emilmont 77:869cf507173a 216 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
emilmont 77:869cf507173a 217 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
emilmont 77:869cf507173a 218 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
emilmont 77:869cf507173a 219
bogdanm 85:024bf7f99721 220 /* NOR Control functions *****************************************************/
emilmont 77:869cf507173a 221 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
emilmont 77:869cf507173a 222 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
emilmont 77:869cf507173a 223
bogdanm 85:024bf7f99721 224 /* NOR State functions ********************************************************/
emilmont 77:869cf507173a 225 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
emilmont 77:869cf507173a 226 NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
emilmont 77:869cf507173a 227
emilmont 77:869cf507173a 228 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 229 /**
emilmont 77:869cf507173a 230 * @}
emilmont 77:869cf507173a 231 */
emilmont 77:869cf507173a 232
emilmont 77:869cf507173a 233 /**
emilmont 77:869cf507173a 234 * @}
emilmont 77:869cf507173a 235 */
emilmont 77:869cf507173a 236
emilmont 77:869cf507173a 237 #ifdef __cplusplus
emilmont 77:869cf507173a 238 }
emilmont 77:869cf507173a 239 #endif
emilmont 77:869cf507173a 240
emilmont 77:869cf507173a 241 #endif /* __STM32F4xx_HAL_NOR_H */
emilmont 77:869cf507173a 242
emilmont 77:869cf507173a 243 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/