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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_dma.h@106:ba1f97679dad, 2015-09-02 (annotated)

Committer:
Kojto
Date:
Wed Sep 02 14:17:43 2015 +0100
Revision:
106:ba1f97679dad
Parent:
99:dbbf35b96557
Child:
110:165afa46840b
Release 106  of the mbed library



Changes:

- new platform - Nucleo F446RE

- STM32F4 Cube driver update v2.3.2

- ST cmsis driver v2.3.2

- nordic bugfix gcc linker start address

- lpc11u68 - bugfix for serial ports

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_dma.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
Kojto 106:ba1f97679dad 5 * @version V1.3.2
Kojto 106:ba1f97679dad 6 * @date 26-June-2015
bogdanm 92:4fc01daae5a5 7 * @brief Header file of DMA HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_DMA_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_DMA_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup DMA
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58
Kojto 99:dbbf35b96557 59 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 99:dbbf35b96557 60 * @brief DMA Exported Types
Kojto 99:dbbf35b96557 61 * @{
Kojto 99:dbbf35b96557 62 */
Kojto 99:dbbf35b96557 63
bogdanm 92:4fc01daae5a5 64 /**
bogdanm 92:4fc01daae5a5 65 * @brief DMA Configuration Structure definition
bogdanm 92:4fc01daae5a5 66 */
bogdanm 92:4fc01daae5a5 67 typedef struct
bogdanm 92:4fc01daae5a5 68 {
bogdanm 92:4fc01daae5a5 69 uint32_t Channel; /*!< Specifies the channel used for the specified stream.
bogdanm 92:4fc01daae5a5 70 This parameter can be a value of @ref DMA_Channel_selection */
bogdanm 92:4fc01daae5a5 71
bogdanm 92:4fc01daae5a5 72 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 92:4fc01daae5a5 73 from memory to memory or from peripheral to memory.
bogdanm 92:4fc01daae5a5 74 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 92:4fc01daae5a5 77 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 92:4fc01daae5a5 80 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 92:4fc01daae5a5 83 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 92:4fc01daae5a5 84
bogdanm 92:4fc01daae5a5 85 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 92:4fc01daae5a5 86 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Streamx.
bogdanm 92:4fc01daae5a5 89 This parameter can be a value of @ref DMA_mode
bogdanm 92:4fc01daae5a5 90 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 92:4fc01daae5a5 91 data transfer is configured on the selected Stream */
bogdanm 92:4fc01daae5a5 92
bogdanm 92:4fc01daae5a5 93 uint32_t Priority; /*!< Specifies the software priority for the DMAy Streamx.
bogdanm 92:4fc01daae5a5 94 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 92:4fc01daae5a5 95
bogdanm 92:4fc01daae5a5 96 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
bogdanm 92:4fc01daae5a5 97 This parameter can be a value of @ref DMA_FIFO_direct_mode
bogdanm 92:4fc01daae5a5 98 @note The Direct mode (FIFO mode disabled) cannot be used if the
bogdanm 92:4fc01daae5a5 99 memory-to-memory data transfer is configured on the selected stream */
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
bogdanm 92:4fc01daae5a5 102 This parameter can be a value of @ref DMA_FIFO_threshold_level */
bogdanm 92:4fc01daae5a5 103
bogdanm 92:4fc01daae5a5 104 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
Kojto 99:dbbf35b96557 105 It specifies the amount of data to be transferred in a single non interruptible
bogdanm 92:4fc01daae5a5 106 transaction.
bogdanm 92:4fc01daae5a5 107 This parameter can be a value of @ref DMA_Memory_burst
bogdanm 92:4fc01daae5a5 108 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 92:4fc01daae5a5 109
bogdanm 92:4fc01daae5a5 110 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
bogdanm 92:4fc01daae5a5 111 It specifies the amount of data to be transferred in a single non interruptable
bogdanm 92:4fc01daae5a5 112 transaction.
bogdanm 92:4fc01daae5a5 113 This parameter can be a value of @ref DMA_Peripheral_burst
bogdanm 92:4fc01daae5a5 114 @note The burst mode is possible only if the address Increment mode is enabled. */
bogdanm 92:4fc01daae5a5 115 }DMA_InitTypeDef;
bogdanm 92:4fc01daae5a5 116
Kojto 99:dbbf35b96557 117
bogdanm 92:4fc01daae5a5 118 /**
bogdanm 92:4fc01daae5a5 119 * @brief HAL DMA State structures definition
bogdanm 92:4fc01daae5a5 120 */
bogdanm 92:4fc01daae5a5 121 typedef enum
bogdanm 92:4fc01daae5a5 122 {
bogdanm 92:4fc01daae5a5 123 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 124 HAL_DMA_STATE_READY = 0x01, /*!< DMA initialized and ready for use */
bogdanm 92:4fc01daae5a5 125 HAL_DMA_STATE_READY_MEM0 = 0x11, /*!< DMA Mem0 process success */
bogdanm 92:4fc01daae5a5 126 HAL_DMA_STATE_READY_MEM1 = 0x21, /*!< DMA Mem1 process success */
bogdanm 92:4fc01daae5a5 127 HAL_DMA_STATE_READY_HALF_MEM0 = 0x31, /*!< DMA Mem0 Half process success */
bogdanm 92:4fc01daae5a5 128 HAL_DMA_STATE_READY_HALF_MEM1 = 0x41, /*!< DMA Mem1 Half process success */
bogdanm 92:4fc01daae5a5 129 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 92:4fc01daae5a5 130 HAL_DMA_STATE_BUSY_MEM0 = 0x12, /*!< DMA Mem0 process is ongoing */
bogdanm 92:4fc01daae5a5 131 HAL_DMA_STATE_BUSY_MEM1 = 0x22, /*!< DMA Mem1 process is ongoing */
bogdanm 92:4fc01daae5a5 132 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 92:4fc01daae5a5 133 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 92:4fc01daae5a5 134 }HAL_DMA_StateTypeDef;
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136 /**
bogdanm 92:4fc01daae5a5 137 * @brief HAL DMA Error Code structure definition
bogdanm 92:4fc01daae5a5 138 */
bogdanm 92:4fc01daae5a5 139 typedef enum
bogdanm 92:4fc01daae5a5 140 {
bogdanm 92:4fc01daae5a5 141 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 92:4fc01daae5a5 142 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 92:4fc01daae5a5 143 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 92:4fc01daae5a5 144
bogdanm 92:4fc01daae5a5 145 /**
bogdanm 92:4fc01daae5a5 146 * @brief DMA handle Structure definition
bogdanm 92:4fc01daae5a5 147 */
bogdanm 92:4fc01daae5a5 148 typedef struct __DMA_HandleTypeDef
bogdanm 92:4fc01daae5a5 149 {
bogdanm 92:4fc01daae5a5 150 DMA_Stream_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 92:4fc01daae5a5 153
bogdanm 92:4fc01daae5a5 154 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 92:4fc01daae5a5 155
bogdanm 92:4fc01daae5a5 156 __IO HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 92:4fc01daae5a5 157
bogdanm 92:4fc01daae5a5 158 void *Parent; /*!< Parent object state */
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 92:4fc01daae5a5 163
bogdanm 92:4fc01daae5a5 164 void (* XferM1CpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete Memory1 callback */
bogdanm 92:4fc01daae5a5 165
bogdanm 92:4fc01daae5a5 166 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 92:4fc01daae5a5 167
Kojto 99:dbbf35b96557 168 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 92:4fc01daae5a5 169 }DMA_HandleTypeDef;
bogdanm 92:4fc01daae5a5 170
Kojto 99:dbbf35b96557 171 /**
Kojto 99:dbbf35b96557 172 * @}
Kojto 99:dbbf35b96557 173 */
Kojto 99:dbbf35b96557 174
bogdanm 92:4fc01daae5a5 175 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 176
Kojto 99:dbbf35b96557 177 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 99:dbbf35b96557 178 * @brief DMA Exported constants
bogdanm 92:4fc01daae5a5 179 * @{
bogdanm 92:4fc01daae5a5 180 */
bogdanm 92:4fc01daae5a5 181
Kojto 99:dbbf35b96557 182 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 99:dbbf35b96557 183 * @brief DMA Error Code
bogdanm 92:4fc01daae5a5 184 * @{
bogdanm 92:4fc01daae5a5 185 */
bogdanm 92:4fc01daae5a5 186 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 92:4fc01daae5a5 187 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 92:4fc01daae5a5 188 #define HAL_DMA_ERROR_FE ((uint32_t)0x00000002) /*!< FIFO error */
bogdanm 92:4fc01daae5a5 189 #define HAL_DMA_ERROR_DME ((uint32_t)0x00000004) /*!< Direct Mode error */
bogdanm 92:4fc01daae5a5 190 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 92:4fc01daae5a5 191 /**
bogdanm 92:4fc01daae5a5 192 * @}
bogdanm 92:4fc01daae5a5 193 */
bogdanm 92:4fc01daae5a5 194
Kojto 99:dbbf35b96557 195 /** @defgroup DMA_Channel_selection DMA Channel selection
Kojto 99:dbbf35b96557 196 * @brief DMA channel selection
bogdanm 92:4fc01daae5a5 197 * @{
bogdanm 92:4fc01daae5a5 198 */
bogdanm 92:4fc01daae5a5 199 #define DMA_CHANNEL_0 ((uint32_t)0x00000000) /*!< DMA Channel 0 */
bogdanm 92:4fc01daae5a5 200 #define DMA_CHANNEL_1 ((uint32_t)0x02000000) /*!< DMA Channel 1 */
bogdanm 92:4fc01daae5a5 201 #define DMA_CHANNEL_2 ((uint32_t)0x04000000) /*!< DMA Channel 2 */
bogdanm 92:4fc01daae5a5 202 #define DMA_CHANNEL_3 ((uint32_t)0x06000000) /*!< DMA Channel 3 */
bogdanm 92:4fc01daae5a5 203 #define DMA_CHANNEL_4 ((uint32_t)0x08000000) /*!< DMA Channel 4 */
bogdanm 92:4fc01daae5a5 204 #define DMA_CHANNEL_5 ((uint32_t)0x0A000000) /*!< DMA Channel 5 */
bogdanm 92:4fc01daae5a5 205 #define DMA_CHANNEL_6 ((uint32_t)0x0C000000) /*!< DMA Channel 6 */
bogdanm 92:4fc01daae5a5 206 #define DMA_CHANNEL_7 ((uint32_t)0x0E000000) /*!< DMA Channel 7 */
bogdanm 92:4fc01daae5a5 207 /**
bogdanm 92:4fc01daae5a5 208 * @}
bogdanm 92:4fc01daae5a5 209 */
bogdanm 92:4fc01daae5a5 210
Kojto 99:dbbf35b96557 211 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 99:dbbf35b96557 212 * @brief DMA data transfer direction
bogdanm 92:4fc01daae5a5 213 * @{
bogdanm 92:4fc01daae5a5 214 */
bogdanm 92:4fc01daae5a5 215 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 92:4fc01daae5a5 216 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
bogdanm 92:4fc01daae5a5 217 #define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
bogdanm 92:4fc01daae5a5 218 /**
bogdanm 92:4fc01daae5a5 219 * @}
Kojto 99:dbbf35b96557 220 */
bogdanm 92:4fc01daae5a5 221
Kojto 99:dbbf35b96557 222 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 99:dbbf35b96557 223 * @brief DMA peripheral incremented mode
bogdanm 92:4fc01daae5a5 224 * @{
bogdanm 92:4fc01daae5a5 225 */
bogdanm 92:4fc01daae5a5 226 #define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
bogdanm 92:4fc01daae5a5 227 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode disable */
bogdanm 92:4fc01daae5a5 228 /**
bogdanm 92:4fc01daae5a5 229 * @}
bogdanm 92:4fc01daae5a5 230 */
bogdanm 92:4fc01daae5a5 231
Kojto 99:dbbf35b96557 232 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 99:dbbf35b96557 233 * @brief DMA memory incremented mode
bogdanm 92:4fc01daae5a5 234 * @{
bogdanm 92:4fc01daae5a5 235 */
bogdanm 92:4fc01daae5a5 236 #define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
bogdanm 92:4fc01daae5a5 237 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode disable */
bogdanm 92:4fc01daae5a5 238 /**
bogdanm 92:4fc01daae5a5 239 * @}
bogdanm 92:4fc01daae5a5 240 */
bogdanm 92:4fc01daae5a5 241
Kojto 99:dbbf35b96557 242 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 99:dbbf35b96557 243 * @brief DMA peripheral data size
bogdanm 92:4fc01daae5a5 244 * @{
bogdanm 92:4fc01daae5a5 245 */
bogdanm 92:4fc01daae5a5 246 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment: Byte */
bogdanm 92:4fc01daae5a5 247 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
bogdanm 92:4fc01daae5a5 248 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
bogdanm 92:4fc01daae5a5 249 /**
bogdanm 92:4fc01daae5a5 250 * @}
bogdanm 92:4fc01daae5a5 251 */
bogdanm 92:4fc01daae5a5 252
Kojto 99:dbbf35b96557 253 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 99:dbbf35b96557 254 * @brief DMA memory data size
bogdanm 92:4fc01daae5a5 255 * @{
bogdanm 92:4fc01daae5a5 256 */
bogdanm 92:4fc01daae5a5 257 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment: Byte */
bogdanm 92:4fc01daae5a5 258 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
bogdanm 92:4fc01daae5a5 259 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
bogdanm 92:4fc01daae5a5 260 /**
bogdanm 92:4fc01daae5a5 261 * @}
bogdanm 92:4fc01daae5a5 262 */
bogdanm 92:4fc01daae5a5 263
Kojto 99:dbbf35b96557 264 /** @defgroup DMA_mode DMA mode
Kojto 99:dbbf35b96557 265 * @brief DMA mode
bogdanm 92:4fc01daae5a5 266 * @{
bogdanm 92:4fc01daae5a5 267 */
bogdanm 92:4fc01daae5a5 268 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal mode */
bogdanm 92:4fc01daae5a5 269 #define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
bogdanm 92:4fc01daae5a5 270 #define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
bogdanm 92:4fc01daae5a5 271 /**
bogdanm 92:4fc01daae5a5 272 * @}
bogdanm 92:4fc01daae5a5 273 */
bogdanm 92:4fc01daae5a5 274
Kojto 99:dbbf35b96557 275 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 99:dbbf35b96557 276 * @brief DMA priority levels
bogdanm 92:4fc01daae5a5 277 * @{
bogdanm 92:4fc01daae5a5 278 */
bogdanm 92:4fc01daae5a5 279 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level: Low */
bogdanm 92:4fc01daae5a5 280 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
bogdanm 92:4fc01daae5a5 281 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
bogdanm 92:4fc01daae5a5 282 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
bogdanm 92:4fc01daae5a5 283 /**
bogdanm 92:4fc01daae5a5 284 * @}
bogdanm 92:4fc01daae5a5 285 */
bogdanm 92:4fc01daae5a5 286
Kojto 99:dbbf35b96557 287 /** @defgroup DMA_FIFO_direct_mode DMA FIFO direct mode
Kojto 99:dbbf35b96557 288 * @brief DMA FIFO direct mode
bogdanm 92:4fc01daae5a5 289 * @{
bogdanm 92:4fc01daae5a5 290 */
bogdanm 92:4fc01daae5a5 291 #define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000) /*!< FIFO mode disable */
bogdanm 92:4fc01daae5a5 292 #define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
bogdanm 92:4fc01daae5a5 293 /**
bogdanm 92:4fc01daae5a5 294 * @}
bogdanm 92:4fc01daae5a5 295 */
bogdanm 92:4fc01daae5a5 296
Kojto 99:dbbf35b96557 297 /** @defgroup DMA_FIFO_threshold_level DMA FIFO threshold level
Kojto 99:dbbf35b96557 298 * @brief DMA FIFO level
bogdanm 92:4fc01daae5a5 299 * @{
bogdanm 92:4fc01daae5a5 300 */
bogdanm 92:4fc01daae5a5 301 #define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000) /*!< FIFO threshold 1 quart full configuration */
bogdanm 92:4fc01daae5a5 302 #define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
bogdanm 92:4fc01daae5a5 303 #define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
bogdanm 92:4fc01daae5a5 304 #define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
bogdanm 92:4fc01daae5a5 305 /**
bogdanm 92:4fc01daae5a5 306 * @}
bogdanm 92:4fc01daae5a5 307 */
bogdanm 92:4fc01daae5a5 308
Kojto 99:dbbf35b96557 309 /** @defgroup DMA_Memory_burst DMA Memory burst
Kojto 99:dbbf35b96557 310 * @brief DMA memory burst
bogdanm 92:4fc01daae5a5 311 * @{
bogdanm 92:4fc01daae5a5 312 */
bogdanm 92:4fc01daae5a5 313 #define DMA_MBURST_SINGLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 314 #define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
bogdanm 92:4fc01daae5a5 315 #define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
bogdanm 92:4fc01daae5a5 316 #define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
bogdanm 92:4fc01daae5a5 317 /**
bogdanm 92:4fc01daae5a5 318 * @}
bogdanm 92:4fc01daae5a5 319 */
bogdanm 92:4fc01daae5a5 320
Kojto 99:dbbf35b96557 321 /** @defgroup DMA_Peripheral_burst DMA Peripheral burst
Kojto 99:dbbf35b96557 322 * @brief DMA peripheral burst
bogdanm 92:4fc01daae5a5 323 * @{
bogdanm 92:4fc01daae5a5 324 */
bogdanm 92:4fc01daae5a5 325 #define DMA_PBURST_SINGLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 326 #define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
bogdanm 92:4fc01daae5a5 327 #define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
bogdanm 92:4fc01daae5a5 328 #define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
bogdanm 92:4fc01daae5a5 329 /**
bogdanm 92:4fc01daae5a5 330 * @}
bogdanm 92:4fc01daae5a5 331 */
bogdanm 92:4fc01daae5a5 332
Kojto 99:dbbf35b96557 333 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 99:dbbf35b96557 334 * @brief DMA interrupts definition
bogdanm 92:4fc01daae5a5 335 * @{
bogdanm 92:4fc01daae5a5 336 */
bogdanm 92:4fc01daae5a5 337 #define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
bogdanm 92:4fc01daae5a5 338 #define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
bogdanm 92:4fc01daae5a5 339 #define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
bogdanm 92:4fc01daae5a5 340 #define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
bogdanm 92:4fc01daae5a5 341 #define DMA_IT_FE ((uint32_t)0x00000080)
bogdanm 92:4fc01daae5a5 342 /**
bogdanm 92:4fc01daae5a5 343 * @}
bogdanm 92:4fc01daae5a5 344 */
bogdanm 92:4fc01daae5a5 345
Kojto 99:dbbf35b96557 346 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 99:dbbf35b96557 347 * @brief DMA flag definitions
bogdanm 92:4fc01daae5a5 348 * @{
bogdanm 92:4fc01daae5a5 349 */
bogdanm 92:4fc01daae5a5 350 #define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001)
bogdanm 92:4fc01daae5a5 351 #define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004)
bogdanm 92:4fc01daae5a5 352 #define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 353 #define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 354 #define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 355 #define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040)
bogdanm 92:4fc01daae5a5 356 #define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100)
bogdanm 92:4fc01daae5a5 357 #define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200)
bogdanm 92:4fc01daae5a5 358 #define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400)
bogdanm 92:4fc01daae5a5 359 #define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800)
bogdanm 92:4fc01daae5a5 360 #define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000)
bogdanm 92:4fc01daae5a5 361 #define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 362 #define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000)
bogdanm 92:4fc01daae5a5 363 #define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000)
bogdanm 92:4fc01daae5a5 364 #define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000)
bogdanm 92:4fc01daae5a5 365 #define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000)
bogdanm 92:4fc01daae5a5 366 #define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000)
bogdanm 92:4fc01daae5a5 367 #define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000)
bogdanm 92:4fc01daae5a5 368 #define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000)
bogdanm 92:4fc01daae5a5 369 #define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000)
bogdanm 92:4fc01daae5a5 370 /**
bogdanm 92:4fc01daae5a5 371 * @}
bogdanm 92:4fc01daae5a5 372 */
Kojto 99:dbbf35b96557 373
bogdanm 92:4fc01daae5a5 374 /**
bogdanm 92:4fc01daae5a5 375 * @}
bogdanm 92:4fc01daae5a5 376 */
Kojto 99:dbbf35b96557 377
bogdanm 92:4fc01daae5a5 378 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 379
bogdanm 92:4fc01daae5a5 380 /** @brief Reset DMA handle state
bogdanm 92:4fc01daae5a5 381 * @param __HANDLE__: specifies the DMA handle.
bogdanm 92:4fc01daae5a5 382 * @retval None
bogdanm 92:4fc01daae5a5 383 */
bogdanm 92:4fc01daae5a5 384 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 92:4fc01daae5a5 385
bogdanm 92:4fc01daae5a5 386 /**
bogdanm 92:4fc01daae5a5 387 * @brief Return the current DMA Stream FIFO filled level.
bogdanm 92:4fc01daae5a5 388 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 389 * @retval The FIFO filling state.
bogdanm 92:4fc01daae5a5 390 * - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
bogdanm 92:4fc01daae5a5 391 * and not empty.
bogdanm 92:4fc01daae5a5 392 * - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
bogdanm 92:4fc01daae5a5 393 * - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
bogdanm 92:4fc01daae5a5 394 * - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
bogdanm 92:4fc01daae5a5 395 * - DMA_FIFOStatus_Empty: when FIFO is empty
bogdanm 92:4fc01daae5a5 396 * - DMA_FIFOStatus_Full: when FIFO is full
bogdanm 92:4fc01daae5a5 397 */
bogdanm 92:4fc01daae5a5 398 #define __HAL_DMA_GET_FS(__HANDLE__) (((__HANDLE__)->Instance->FCR & (DMA_SxFCR_FS)))
bogdanm 92:4fc01daae5a5 399
bogdanm 92:4fc01daae5a5 400 /**
bogdanm 92:4fc01daae5a5 401 * @brief Enable the specified DMA Stream.
bogdanm 92:4fc01daae5a5 402 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 403 * @retval None
bogdanm 92:4fc01daae5a5 404 */
bogdanm 92:4fc01daae5a5 405 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
bogdanm 92:4fc01daae5a5 406
bogdanm 92:4fc01daae5a5 407 /**
bogdanm 92:4fc01daae5a5 408 * @brief Disable the specified DMA Stream.
bogdanm 92:4fc01daae5a5 409 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 410 * @retval None
bogdanm 92:4fc01daae5a5 411 */
bogdanm 92:4fc01daae5a5 412 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
bogdanm 92:4fc01daae5a5 413
bogdanm 92:4fc01daae5a5 414 /* Interrupt & Flag management */
bogdanm 92:4fc01daae5a5 415
bogdanm 92:4fc01daae5a5 416 /**
bogdanm 92:4fc01daae5a5 417 * @brief Return the current DMA Stream transfer complete flag.
bogdanm 92:4fc01daae5a5 418 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 419 * @retval The specified transfer complete flag index.
bogdanm 92:4fc01daae5a5 420 */
bogdanm 92:4fc01daae5a5 421 #define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
bogdanm 92:4fc01daae5a5 422 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 423 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 424 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 425 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TCIF0_4 :\
bogdanm 92:4fc01daae5a5 426 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 427 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 428 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 429 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TCIF1_5 :\
bogdanm 92:4fc01daae5a5 430 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 431 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 432 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 433 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TCIF2_6 :\
bogdanm 92:4fc01daae5a5 434 DMA_FLAG_TCIF3_7)
bogdanm 92:4fc01daae5a5 435
bogdanm 92:4fc01daae5a5 436 /**
bogdanm 92:4fc01daae5a5 437 * @brief Return the current DMA Stream half transfer complete flag.
bogdanm 92:4fc01daae5a5 438 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 439 * @retval The specified half transfer complete flag index.
bogdanm 92:4fc01daae5a5 440 */
bogdanm 92:4fc01daae5a5 441 #define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 442 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 443 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 444 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 445 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_HTIF0_4 :\
bogdanm 92:4fc01daae5a5 446 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 447 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 448 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 449 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_HTIF1_5 :\
bogdanm 92:4fc01daae5a5 450 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 451 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 452 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 453 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_HTIF2_6 :\
bogdanm 92:4fc01daae5a5 454 DMA_FLAG_HTIF3_7)
bogdanm 92:4fc01daae5a5 455
bogdanm 92:4fc01daae5a5 456 /**
bogdanm 92:4fc01daae5a5 457 * @brief Return the current DMA Stream transfer error flag.
bogdanm 92:4fc01daae5a5 458 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 459 * @retval The specified transfer error flag index.
bogdanm 92:4fc01daae5a5 460 */
bogdanm 92:4fc01daae5a5 461 #define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 462 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 463 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 464 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 465 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_TEIF0_4 :\
bogdanm 92:4fc01daae5a5 466 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 467 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 468 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 469 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_TEIF1_5 :\
bogdanm 92:4fc01daae5a5 470 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 471 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 472 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 473 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_TEIF2_6 :\
bogdanm 92:4fc01daae5a5 474 DMA_FLAG_TEIF3_7)
bogdanm 92:4fc01daae5a5 475
bogdanm 92:4fc01daae5a5 476 /**
bogdanm 92:4fc01daae5a5 477 * @brief Return the current DMA Stream FIFO error flag.
bogdanm 92:4fc01daae5a5 478 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 479 * @retval The specified FIFO error flag index.
bogdanm 92:4fc01daae5a5 480 */
bogdanm 92:4fc01daae5a5 481 #define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 482 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 483 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 484 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 485 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_FEIF0_4 :\
bogdanm 92:4fc01daae5a5 486 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 487 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 488 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 489 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_FEIF1_5 :\
bogdanm 92:4fc01daae5a5 490 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 491 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 492 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 493 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_FEIF2_6 :\
bogdanm 92:4fc01daae5a5 494 DMA_FLAG_FEIF3_7)
bogdanm 92:4fc01daae5a5 495
bogdanm 92:4fc01daae5a5 496 /**
bogdanm 92:4fc01daae5a5 497 * @brief Return the current DMA Stream direct mode error flag.
bogdanm 92:4fc01daae5a5 498 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 499 * @retval The specified direct mode error flag index.
bogdanm 92:4fc01daae5a5 500 */
bogdanm 92:4fc01daae5a5 501 #define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
bogdanm 92:4fc01daae5a5 502 (((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 503 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream0))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 504 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 505 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream4))? DMA_FLAG_DMEIF0_4 :\
bogdanm 92:4fc01daae5a5 506 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 507 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream1))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 508 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 509 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream5))? DMA_FLAG_DMEIF1_5 :\
bogdanm 92:4fc01daae5a5 510 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 511 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream2))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 512 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 513 ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Stream6))? DMA_FLAG_DMEIF2_6 :\
bogdanm 92:4fc01daae5a5 514 DMA_FLAG_DMEIF3_7)
bogdanm 92:4fc01daae5a5 515
bogdanm 92:4fc01daae5a5 516 /**
bogdanm 92:4fc01daae5a5 517 * @brief Get the DMA Stream pending flags.
bogdanm 92:4fc01daae5a5 518 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 519 * @param __FLAG__: Get the specified flag.
bogdanm 92:4fc01daae5a5 520 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 521 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 92:4fc01daae5a5 522 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 92:4fc01daae5a5 523 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 92:4fc01daae5a5 524 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 92:4fc01daae5a5 525 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 92:4fc01daae5a5 526 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 92:4fc01daae5a5 527 * @retval The state of FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 528 */
bogdanm 92:4fc01daae5a5 529 #define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
bogdanm 92:4fc01daae5a5 530 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HISR & (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 531 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LISR & (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 532 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HISR & (__FLAG__)) : (DMA1->LISR & (__FLAG__)))
bogdanm 92:4fc01daae5a5 533
bogdanm 92:4fc01daae5a5 534 /**
bogdanm 92:4fc01daae5a5 535 * @brief Clear the DMA Stream pending flags.
bogdanm 92:4fc01daae5a5 536 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 537 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 538 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 539 * @arg DMA_FLAG_TCIFx: Transfer complete flag.
bogdanm 92:4fc01daae5a5 540 * @arg DMA_FLAG_HTIFx: Half transfer complete flag.
bogdanm 92:4fc01daae5a5 541 * @arg DMA_FLAG_TEIFx: Transfer error flag.
bogdanm 92:4fc01daae5a5 542 * @arg DMA_FLAG_DMEIFx: Direct mode error flag.
bogdanm 92:4fc01daae5a5 543 * @arg DMA_FLAG_FEIFx: FIFO error flag.
bogdanm 92:4fc01daae5a5 544 * Where x can be 0_4, 1_5, 2_6 or 3_7 to select the DMA Stream flag.
bogdanm 92:4fc01daae5a5 545 * @retval None
bogdanm 92:4fc01daae5a5 546 */
bogdanm 92:4fc01daae5a5 547 #define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
bogdanm 92:4fc01daae5a5 548 (((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA2_Stream3)? (DMA2->HIFCR = (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 549 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream7)? (DMA2->LIFCR = (__FLAG__)) :\
bogdanm 92:4fc01daae5a5 550 ((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Stream3)? (DMA1->HIFCR = (__FLAG__)) : (DMA1->LIFCR = (__FLAG__)))
bogdanm 92:4fc01daae5a5 551
bogdanm 92:4fc01daae5a5 552 /**
bogdanm 92:4fc01daae5a5 553 * @brief Enable the specified DMA Stream interrupts.
bogdanm 92:4fc01daae5a5 554 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 555 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 556 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 557 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 558 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 559 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 92:4fc01daae5a5 560 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 92:4fc01daae5a5 561 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 92:4fc01daae5a5 562 * @retval None
bogdanm 92:4fc01daae5a5 563 */
bogdanm 92:4fc01daae5a5 564 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 92:4fc01daae5a5 565 ((__HANDLE__)->Instance->CR |= (__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR |= (__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 566
bogdanm 92:4fc01daae5a5 567 /**
bogdanm 92:4fc01daae5a5 568 * @brief Disable the specified DMA Stream interrupts.
bogdanm 92:4fc01daae5a5 569 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 570 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 92:4fc01daae5a5 571 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 572 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 573 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 574 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 92:4fc01daae5a5 575 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 92:4fc01daae5a5 576 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 92:4fc01daae5a5 577 * @retval None
bogdanm 92:4fc01daae5a5 578 */
bogdanm 92:4fc01daae5a5 579 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 92:4fc01daae5a5 580 ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) : ((__HANDLE__)->Instance->FCR &= ~(__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 581
bogdanm 92:4fc01daae5a5 582 /**
Kojto 106:ba1f97679dad 583 * @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
bogdanm 92:4fc01daae5a5 584 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 585 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 92:4fc01daae5a5 586 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 587 * @arg DMA_IT_TC: Transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 588 * @arg DMA_IT_HT: Half transfer complete interrupt mask.
bogdanm 92:4fc01daae5a5 589 * @arg DMA_IT_TE: Transfer error interrupt mask.
bogdanm 92:4fc01daae5a5 590 * @arg DMA_IT_FE: FIFO error interrupt mask.
bogdanm 92:4fc01daae5a5 591 * @arg DMA_IT_DME: Direct mode error interrupt.
bogdanm 92:4fc01daae5a5 592 * @retval The state of DMA_IT.
bogdanm 92:4fc01daae5a5 593 */
bogdanm 92:4fc01daae5a5 594 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) != DMA_IT_FE)? \
bogdanm 92:4fc01daae5a5 595 ((__HANDLE__)->Instance->CR & (__INTERRUPT__)) : \
bogdanm 92:4fc01daae5a5 596 ((__HANDLE__)->Instance->FCR & (__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 597
bogdanm 92:4fc01daae5a5 598 /**
bogdanm 92:4fc01daae5a5 599 * @brief Writes the number of data units to be transferred on the DMA Stream.
bogdanm 92:4fc01daae5a5 600 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 601 * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
bogdanm 92:4fc01daae5a5 602 * Number of data items depends only on the Peripheral data format.
bogdanm 92:4fc01daae5a5 603 *
bogdanm 92:4fc01daae5a5 604 * @note If Peripheral data format is Bytes: number of data units is equal
bogdanm 92:4fc01daae5a5 605 * to total number of bytes to be transferred.
bogdanm 92:4fc01daae5a5 606 *
bogdanm 92:4fc01daae5a5 607 * @note If Peripheral data format is Half-Word: number of data units is
bogdanm 92:4fc01daae5a5 608 * equal to total number of bytes to be transferred / 2.
bogdanm 92:4fc01daae5a5 609 *
bogdanm 92:4fc01daae5a5 610 * @note If Peripheral data format is Word: number of data units is equal
bogdanm 92:4fc01daae5a5 611 * to total number of bytes to be transferred / 4.
bogdanm 92:4fc01daae5a5 612 *
bogdanm 92:4fc01daae5a5 613 * @retval The number of remaining data units in the current DMAy Streamx transfer.
bogdanm 92:4fc01daae5a5 614 */
bogdanm 92:4fc01daae5a5 615 #define __HAL_DMA_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->NDTR = (uint16_t)(__COUNTER__))
bogdanm 92:4fc01daae5a5 616
bogdanm 92:4fc01daae5a5 617 /**
bogdanm 92:4fc01daae5a5 618 * @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
bogdanm 92:4fc01daae5a5 619 * @param __HANDLE__: DMA handle
bogdanm 92:4fc01daae5a5 620 *
bogdanm 92:4fc01daae5a5 621 * @retval The number of remaining data units in the current DMA Stream transfer.
bogdanm 92:4fc01daae5a5 622 */
bogdanm 92:4fc01daae5a5 623 #define __HAL_DMA_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->NDTR)
bogdanm 92:4fc01daae5a5 624
bogdanm 92:4fc01daae5a5 625
bogdanm 92:4fc01daae5a5 626 /* Include DMA HAL Extension module */
bogdanm 92:4fc01daae5a5 627 #include "stm32f4xx_hal_dma_ex.h"
bogdanm 92:4fc01daae5a5 628
bogdanm 92:4fc01daae5a5 629 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 630
Kojto 99:dbbf35b96557 631 /** @defgroup DMA_Exported_Functions DMA Exported Functions
Kojto 99:dbbf35b96557 632 * @brief DMA Exported functions
Kojto 99:dbbf35b96557 633 * @{
Kojto 99:dbbf35b96557 634 */
Kojto 99:dbbf35b96557 635
Kojto 99:dbbf35b96557 636 /** @defgroup DMA_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 99:dbbf35b96557 637 * @brief Initialization and de-initialization functions
Kojto 99:dbbf35b96557 638 * @{
Kojto 99:dbbf35b96557 639 */
bogdanm 92:4fc01daae5a5 640 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 641 HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 642 /**
Kojto 99:dbbf35b96557 643 * @}
Kojto 99:dbbf35b96557 644 */
bogdanm 92:4fc01daae5a5 645
Kojto 99:dbbf35b96557 646 /** @defgroup DMA_Exported_Functions_Group2 I/O operation functions
Kojto 99:dbbf35b96557 647 * @brief I/O operation functions
Kojto 99:dbbf35b96557 648 * @{
Kojto 99:dbbf35b96557 649 */
bogdanm 92:4fc01daae5a5 650 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 92:4fc01daae5a5 651 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 92:4fc01daae5a5 652 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 653 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 654 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 655 /**
Kojto 99:dbbf35b96557 656 * @}
Kojto 99:dbbf35b96557 657 */
bogdanm 92:4fc01daae5a5 658
Kojto 99:dbbf35b96557 659 /** @defgroup DMA_Exported_Functions_Group3 Peripheral State functions
Kojto 99:dbbf35b96557 660 * @brief Peripheral State functions
Kojto 99:dbbf35b96557 661 * @{
Kojto 99:dbbf35b96557 662 */
bogdanm 92:4fc01daae5a5 663 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 664 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 99:dbbf35b96557 665 /**
Kojto 99:dbbf35b96557 666 * @}
Kojto 99:dbbf35b96557 667 */
Kojto 99:dbbf35b96557 668 /**
Kojto 99:dbbf35b96557 669 * @}
Kojto 99:dbbf35b96557 670 */
Kojto 99:dbbf35b96557 671 /* Private Constants -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 672 /** @defgroup DMA_Private_Constants DMA Private Constants
Kojto 99:dbbf35b96557 673 * @brief DMA private defines and constants
Kojto 99:dbbf35b96557 674 * @{
Kojto 99:dbbf35b96557 675 */
Kojto 99:dbbf35b96557 676 /**
Kojto 99:dbbf35b96557 677 * @}
Kojto 99:dbbf35b96557 678 */
Kojto 99:dbbf35b96557 679
Kojto 99:dbbf35b96557 680 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 681 /** @defgroup DMA_Private_Macros DMA Private Macros
Kojto 99:dbbf35b96557 682 * @brief DMA private macros
Kojto 99:dbbf35b96557 683 * @{
Kojto 99:dbbf35b96557 684 */
Kojto 99:dbbf35b96557 685 #define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_CHANNEL_0) || \
Kojto 99:dbbf35b96557 686 ((CHANNEL) == DMA_CHANNEL_1) || \
Kojto 99:dbbf35b96557 687 ((CHANNEL) == DMA_CHANNEL_2) || \
Kojto 99:dbbf35b96557 688 ((CHANNEL) == DMA_CHANNEL_3) || \
Kojto 99:dbbf35b96557 689 ((CHANNEL) == DMA_CHANNEL_4) || \
Kojto 99:dbbf35b96557 690 ((CHANNEL) == DMA_CHANNEL_5) || \
Kojto 99:dbbf35b96557 691 ((CHANNEL) == DMA_CHANNEL_6) || \
Kojto 99:dbbf35b96557 692 ((CHANNEL) == DMA_CHANNEL_7))
Kojto 99:dbbf35b96557 693
Kojto 99:dbbf35b96557 694 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 99:dbbf35b96557 695 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 99:dbbf35b96557 696 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 99:dbbf35b96557 697
Kojto 99:dbbf35b96557 698 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
Kojto 99:dbbf35b96557 699
Kojto 99:dbbf35b96557 700 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 99:dbbf35b96557 701 ((STATE) == DMA_PINC_DISABLE))
Kojto 99:dbbf35b96557 702
Kojto 99:dbbf35b96557 703 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 99:dbbf35b96557 704 ((STATE) == DMA_MINC_DISABLE))
Kojto 99:dbbf35b96557 705
Kojto 99:dbbf35b96557 706 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 707 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 708 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 99:dbbf35b96557 709
Kojto 99:dbbf35b96557 710 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 99:dbbf35b96557 711 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 99:dbbf35b96557 712 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 99:dbbf35b96557 713
Kojto 99:dbbf35b96557 714 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 99:dbbf35b96557 715 ((MODE) == DMA_CIRCULAR) || \
Kojto 99:dbbf35b96557 716 ((MODE) == DMA_PFCTRL))
Kojto 99:dbbf35b96557 717
Kojto 99:dbbf35b96557 718 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 99:dbbf35b96557 719 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 99:dbbf35b96557 720 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 99:dbbf35b96557 721 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 99:dbbf35b96557 722
Kojto 99:dbbf35b96557 723 #define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMODE_DISABLE ) || \
Kojto 99:dbbf35b96557 724 ((STATE) == DMA_FIFOMODE_ENABLE))
Kojto 99:dbbf35b96557 725
Kojto 99:dbbf35b96557 726 #define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFO_THRESHOLD_1QUARTERFULL ) || \
Kojto 99:dbbf35b96557 727 ((THRESHOLD) == DMA_FIFO_THRESHOLD_HALFFULL) || \
Kojto 99:dbbf35b96557 728 ((THRESHOLD) == DMA_FIFO_THRESHOLD_3QUARTERSFULL) || \
Kojto 99:dbbf35b96557 729 ((THRESHOLD) == DMA_FIFO_THRESHOLD_FULL))
Kojto 99:dbbf35b96557 730
Kojto 99:dbbf35b96557 731 #define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MBURST_SINGLE) || \
Kojto 99:dbbf35b96557 732 ((BURST) == DMA_MBURST_INC4) || \
Kojto 99:dbbf35b96557 733 ((BURST) == DMA_MBURST_INC8) || \
Kojto 99:dbbf35b96557 734 ((BURST) == DMA_MBURST_INC16))
Kojto 99:dbbf35b96557 735
Kojto 99:dbbf35b96557 736 #define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PBURST_SINGLE) || \
Kojto 99:dbbf35b96557 737 ((BURST) == DMA_PBURST_INC4) || \
Kojto 99:dbbf35b96557 738 ((BURST) == DMA_PBURST_INC8) || \
Kojto 99:dbbf35b96557 739 ((BURST) == DMA_PBURST_INC16))
Kojto 99:dbbf35b96557 740 /**
Kojto 99:dbbf35b96557 741 * @}
Kojto 99:dbbf35b96557 742 */
Kojto 99:dbbf35b96557 743
Kojto 99:dbbf35b96557 744 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 745 /** @defgroup DMA_Private_Functions DMA Private Functions
Kojto 99:dbbf35b96557 746 * @brief DMA private functions
Kojto 99:dbbf35b96557 747 * @{
Kojto 99:dbbf35b96557 748 */
Kojto 99:dbbf35b96557 749 /**
Kojto 99:dbbf35b96557 750 * @}
Kojto 99:dbbf35b96557 751 */
bogdanm 92:4fc01daae5a5 752
bogdanm 92:4fc01daae5a5 753 /**
bogdanm 92:4fc01daae5a5 754 * @}
bogdanm 92:4fc01daae5a5 755 */
bogdanm 92:4fc01daae5a5 756
bogdanm 92:4fc01daae5a5 757 /**
bogdanm 92:4fc01daae5a5 758 * @}
bogdanm 92:4fc01daae5a5 759 */
bogdanm 92:4fc01daae5a5 760
bogdanm 92:4fc01daae5a5 761 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 762 }
bogdanm 92:4fc01daae5a5 763 #endif
bogdanm 92:4fc01daae5a5 764
bogdanm 92:4fc01daae5a5 765 #endif /* __STM32F4xx_HAL_DMA_H */
bogdanm 92:4fc01daae5a5 766
bogdanm 92:4fc01daae5a5 767 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/