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TARGET_DISCO_F746NG/stm32f7xx_hal_rcc_ex.h@107:4f6c30876dfa, 2015-09-16 (annotated)

Committer:
Kojto
Date:
Wed Sep 16 15:32:31 2015 +0100
Revision:
107:4f6c30876dfa
Child:
116:c0f6e94411f5
Release 107  of the mbed library



Changes:

- new platforms - DISCO_F746NG, DISCO_L476VG, NUCLEO_L476RG

- KL43Z - bugfix RTC init function

- K20 - SPI mode fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 107:4f6c30876dfa 1 /**
Kojto 107:4f6c30876dfa 2 ******************************************************************************
Kojto 107:4f6c30876dfa 3 * @file stm32f7xx_hal_rcc_ex.h
Kojto 107:4f6c30876dfa 4 * @author MCD Application Team
Kojto 107:4f6c30876dfa 5 * @version V1.0.1
Kojto 107:4f6c30876dfa 6 * @date 25-June-2015
Kojto 107:4f6c30876dfa 7 * @brief Header file of RCC HAL Extension module.
Kojto 107:4f6c30876dfa 8 ******************************************************************************
Kojto 107:4f6c30876dfa 9 * @attention
Kojto 107:4f6c30876dfa 10 *
Kojto 107:4f6c30876dfa 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 107:4f6c30876dfa 12 *
Kojto 107:4f6c30876dfa 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 107:4f6c30876dfa 14 * are permitted provided that the following conditions are met:
Kojto 107:4f6c30876dfa 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 107:4f6c30876dfa 16 * this list of conditions and the following disclaimer.
Kojto 107:4f6c30876dfa 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 107:4f6c30876dfa 18 * this list of conditions and the following disclaimer in the documentation
Kojto 107:4f6c30876dfa 19 * and/or other materials provided with the distribution.
Kojto 107:4f6c30876dfa 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 107:4f6c30876dfa 21 * may be used to endorse or promote products derived from this software
Kojto 107:4f6c30876dfa 22 * without specific prior written permission.
Kojto 107:4f6c30876dfa 23 *
Kojto 107:4f6c30876dfa 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 107:4f6c30876dfa 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 107:4f6c30876dfa 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 107:4f6c30876dfa 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 107:4f6c30876dfa 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 107:4f6c30876dfa 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 107:4f6c30876dfa 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 107:4f6c30876dfa 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 107:4f6c30876dfa 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 107:4f6c30876dfa 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 107:4f6c30876dfa 34 *
Kojto 107:4f6c30876dfa 35 ******************************************************************************
Kojto 107:4f6c30876dfa 36 */
Kojto 107:4f6c30876dfa 37
Kojto 107:4f6c30876dfa 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 107:4f6c30876dfa 39 #ifndef __STM32F7xx_HAL_RCC_EX_H
Kojto 107:4f6c30876dfa 40 #define __STM32F7xx_HAL_RCC_EX_H
Kojto 107:4f6c30876dfa 41
Kojto 107:4f6c30876dfa 42 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 43 extern "C" {
Kojto 107:4f6c30876dfa 44 #endif
Kojto 107:4f6c30876dfa 45
Kojto 107:4f6c30876dfa 46 /* Includes ------------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 47 #include "stm32f7xx_hal_def.h"
Kojto 107:4f6c30876dfa 48
Kojto 107:4f6c30876dfa 49 /** @addtogroup STM32F7xx_HAL_Driver
Kojto 107:4f6c30876dfa 50 * @{
Kojto 107:4f6c30876dfa 51 */
Kojto 107:4f6c30876dfa 52
Kojto 107:4f6c30876dfa 53 /** @addtogroup RCCEx
Kojto 107:4f6c30876dfa 54 * @{
Kojto 107:4f6c30876dfa 55 */
Kojto 107:4f6c30876dfa 56
Kojto 107:4f6c30876dfa 57 /* Exported types ------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 107:4f6c30876dfa 59 * @{
Kojto 107:4f6c30876dfa 60 */
Kojto 107:4f6c30876dfa 61
Kojto 107:4f6c30876dfa 62 /**
Kojto 107:4f6c30876dfa 63 * @brief PLLI2S Clock structure definition
Kojto 107:4f6c30876dfa 64 */
Kojto 107:4f6c30876dfa 65 typedef struct
Kojto 107:4f6c30876dfa 66 {
Kojto 107:4f6c30876dfa 67 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 107:4f6c30876dfa 68 This parameter must be a number between Min_Data = 49 and Max_Data = 432.
Kojto 107:4f6c30876dfa 69 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 107:4f6c30876dfa 70
Kojto 107:4f6c30876dfa 71 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto 107:4f6c30876dfa 72 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 107:4f6c30876dfa 73 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 107:4f6c30876dfa 74
Kojto 107:4f6c30876dfa 75 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
Kojto 107:4f6c30876dfa 76 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 107:4f6c30876dfa 77 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 107:4f6c30876dfa 78
Kojto 107:4f6c30876dfa 79 uint32_t PLLI2SP; /*!< Specifies the division factor for SPDIF-RX clock.
Kojto 107:4f6c30876dfa 80 This parameter must be a number between 0 and 3 for respective values 2, 4, 6 and 8.
Kojto 107:4f6c30876dfa 81 This parameter will be used only when PLLI2S is selected as Clock Source SPDDIF-RX */
Kojto 107:4f6c30876dfa 82 }RCC_PLLI2SInitTypeDef;
Kojto 107:4f6c30876dfa 83
Kojto 107:4f6c30876dfa 84 /**
Kojto 107:4f6c30876dfa 85 * @brief PLLSAI Clock structure definition
Kojto 107:4f6c30876dfa 86 */
Kojto 107:4f6c30876dfa 87 typedef struct
Kojto 107:4f6c30876dfa 88 {
Kojto 107:4f6c30876dfa 89 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 107:4f6c30876dfa 90 This parameter must be a number between Min_Data = 49 and Max_Data = 432.
Kojto 107:4f6c30876dfa 91 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto 107:4f6c30876dfa 92
Kojto 107:4f6c30876dfa 93 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
Kojto 107:4f6c30876dfa 94 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 107:4f6c30876dfa 95 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto 107:4f6c30876dfa 96
Kojto 107:4f6c30876dfa 97 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
Kojto 107:4f6c30876dfa 98 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 107:4f6c30876dfa 99 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
Kojto 107:4f6c30876dfa 100
Kojto 107:4f6c30876dfa 101 uint32_t PLLSAIP; /*!< Specifies the division factor for 48MHz clock.
Kojto 107:4f6c30876dfa 102 This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider
Kojto 107:4f6c30876dfa 103 This parameter will be used only when PLLSAI is disabled */
Kojto 107:4f6c30876dfa 104 }RCC_PLLSAIInitTypeDef;
Kojto 107:4f6c30876dfa 105
Kojto 107:4f6c30876dfa 106 /**
Kojto 107:4f6c30876dfa 107 * @brief RCC extended clocks structure definition
Kojto 107:4f6c30876dfa 108 */
Kojto 107:4f6c30876dfa 109 typedef struct
Kojto 107:4f6c30876dfa 110 {
Kojto 107:4f6c30876dfa 111 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 107:4f6c30876dfa 112 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 107:4f6c30876dfa 113
Kojto 107:4f6c30876dfa 114 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto 107:4f6c30876dfa 115 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 107:4f6c30876dfa 116
Kojto 107:4f6c30876dfa 117 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto 107:4f6c30876dfa 118 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto 107:4f6c30876dfa 119
Kojto 107:4f6c30876dfa 120 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 107:4f6c30876dfa 121 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 107:4f6c30876dfa 122 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 107:4f6c30876dfa 123
Kojto 107:4f6c30876dfa 124 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 107:4f6c30876dfa 125 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 107:4f6c30876dfa 126 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto 107:4f6c30876dfa 127
Kojto 107:4f6c30876dfa 128 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
Kojto 107:4f6c30876dfa 129 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
Kojto 107:4f6c30876dfa 130
Kojto 107:4f6c30876dfa 131 uint32_t RTCClockSelection; /*!< Specifies RTC Clock source Selection.
Kojto 107:4f6c30876dfa 132 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 107:4f6c30876dfa 133
Kojto 107:4f6c30876dfa 134 uint32_t I2sClockSelection; /*!< Specifies I2S Clock source Selection.
Kojto 107:4f6c30876dfa 135 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 107:4f6c30876dfa 136
Kojto 107:4f6c30876dfa 137 uint32_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
Kojto 107:4f6c30876dfa 138 This parameter can be a value of @ref RCCEx_TIM_Prescaler_Selection */
Kojto 107:4f6c30876dfa 139
Kojto 107:4f6c30876dfa 140 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Prescalers Selection
Kojto 107:4f6c30876dfa 141 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto 107:4f6c30876dfa 142
Kojto 107:4f6c30876dfa 143 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Prescalers Selection
Kojto 107:4f6c30876dfa 144 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto 107:4f6c30876dfa 145
Kojto 107:4f6c30876dfa 146 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 107:4f6c30876dfa 147 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 107:4f6c30876dfa 148
Kojto 107:4f6c30876dfa 149 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 107:4f6c30876dfa 150 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 107:4f6c30876dfa 151
Kojto 107:4f6c30876dfa 152 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 107:4f6c30876dfa 153 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto 107:4f6c30876dfa 154
Kojto 107:4f6c30876dfa 155 uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto 107:4f6c30876dfa 156 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 107:4f6c30876dfa 157
Kojto 107:4f6c30876dfa 158 uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto 107:4f6c30876dfa 159 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 107:4f6c30876dfa 160
Kojto 107:4f6c30876dfa 161 uint32_t Usart6ClockSelection; /*!< USART6 clock source
Kojto 107:4f6c30876dfa 162 This parameter can be a value of @ref RCCEx_USART6_Clock_Source */
Kojto 107:4f6c30876dfa 163
Kojto 107:4f6c30876dfa 164 uint32_t Uart7ClockSelection; /*!< UART7 clock source
Kojto 107:4f6c30876dfa 165 This parameter can be a value of @ref RCCEx_UART7_Clock_Source */
Kojto 107:4f6c30876dfa 166
Kojto 107:4f6c30876dfa 167 uint32_t Uart8ClockSelection; /*!< UART8 clock source
Kojto 107:4f6c30876dfa 168 This parameter can be a value of @ref RCCEx_UART8_Clock_Source */
Kojto 107:4f6c30876dfa 169
Kojto 107:4f6c30876dfa 170 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 107:4f6c30876dfa 171 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
Kojto 107:4f6c30876dfa 172
Kojto 107:4f6c30876dfa 173 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 107:4f6c30876dfa 174 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 107:4f6c30876dfa 175
Kojto 107:4f6c30876dfa 176 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto 107:4f6c30876dfa 177 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 107:4f6c30876dfa 178
Kojto 107:4f6c30876dfa 179 uint32_t I2c4ClockSelection; /*!< I2C4 clock source
Kojto 107:4f6c30876dfa 180 This parameter can be a value of @ref RCCEx_I2C4_Clock_Source */
Kojto 107:4f6c30876dfa 181
Kojto 107:4f6c30876dfa 182 uint32_t Lptim1ClockSelection; /*!< Specifies LPTIM1 clock source
Kojto 107:4f6c30876dfa 183 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto 107:4f6c30876dfa 184
Kojto 107:4f6c30876dfa 185 uint32_t CecClockSelection; /*!< CEC clock source
Kojto 107:4f6c30876dfa 186 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 107:4f6c30876dfa 187
Kojto 107:4f6c30876dfa 188 uint32_t Clk48ClockSelection; /*!< Specifies 48Mhz clock source used by USB OTG FS, RNG and SDMMC
Kojto 107:4f6c30876dfa 189 This parameter can be a value of @ref RCCEx_CLK48_Clock_Source */
Kojto 107:4f6c30876dfa 190
Kojto 107:4f6c30876dfa 191 uint32_t Sdmmc1ClockSelection; /*!< SDMMC1 clock source
Kojto 107:4f6c30876dfa 192 This parameter can be a value of @ref RCCEx_SDMMC1_Clock_Source */
Kojto 107:4f6c30876dfa 193
Kojto 107:4f6c30876dfa 194 }RCC_PeriphCLKInitTypeDef;
Kojto 107:4f6c30876dfa 195 /**
Kojto 107:4f6c30876dfa 196 * @}
Kojto 107:4f6c30876dfa 197 */
Kojto 107:4f6c30876dfa 198
Kojto 107:4f6c30876dfa 199 /* Exported constants --------------------------------------------------------*/
Kojto 107:4f6c30876dfa 200 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 107:4f6c30876dfa 201 * @{
Kojto 107:4f6c30876dfa 202 */
Kojto 107:4f6c30876dfa 203
Kojto 107:4f6c30876dfa 204 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
Kojto 107:4f6c30876dfa 205 * @{
Kojto 107:4f6c30876dfa 206 */
Kojto 107:4f6c30876dfa 207 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 208 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 209 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
Kojto 107:4f6c30876dfa 210 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 211 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto 107:4f6c30876dfa 212 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto 107:4f6c30876dfa 213 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000040)
Kojto 107:4f6c30876dfa 214 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000080)
Kojto 107:4f6c30876dfa 215 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000100)
Kojto 107:4f6c30876dfa 216 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000200)
Kojto 107:4f6c30876dfa 217 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000400)
Kojto 107:4f6c30876dfa 218 #define RCC_PERIPHCLK_USART6 ((uint32_t)0x00000800)
Kojto 107:4f6c30876dfa 219 #define RCC_PERIPHCLK_UART7 ((uint32_t)0x00001000)
Kojto 107:4f6c30876dfa 220 #define RCC_PERIPHCLK_UART8 ((uint32_t)0x00002000)
Kojto 107:4f6c30876dfa 221 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00004000)
Kojto 107:4f6c30876dfa 222 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00008000)
Kojto 107:4f6c30876dfa 223 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00010000)
Kojto 107:4f6c30876dfa 224 #define RCC_PERIPHCLK_I2C4 ((uint32_t)0x00020000)
Kojto 107:4f6c30876dfa 225 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00040000)
Kojto 107:4f6c30876dfa 226 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00080000)
Kojto 107:4f6c30876dfa 227 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00100000)
Kojto 107:4f6c30876dfa 228 #define RCC_PERIPHCLK_CLK48 ((uint32_t)0x00200000)
Kojto 107:4f6c30876dfa 229 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00400000)
Kojto 107:4f6c30876dfa 230 #define RCC_PERIPHCLK_SDMMC1 ((uint32_t)0x00800000)
Kojto 107:4f6c30876dfa 231 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x01000000)
Kojto 107:4f6c30876dfa 232 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x02000000)
Kojto 107:4f6c30876dfa 233
Kojto 107:4f6c30876dfa 234
Kojto 107:4f6c30876dfa 235 /**
Kojto 107:4f6c30876dfa 236 * @}
Kojto 107:4f6c30876dfa 237 */
Kojto 107:4f6c30876dfa 238
Kojto 107:4f6c30876dfa 239 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCCEx PLLSAIP Clock Divider
Kojto 107:4f6c30876dfa 240 * @{
Kojto 107:4f6c30876dfa 241 */
Kojto 107:4f6c30876dfa 242 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 243 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000001)
Kojto 107:4f6c30876dfa 244 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000002)
Kojto 107:4f6c30876dfa 245 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000003)
Kojto 107:4f6c30876dfa 246 /**
Kojto 107:4f6c30876dfa 247 * @}
Kojto 107:4f6c30876dfa 248 */
Kojto 107:4f6c30876dfa 249
Kojto 107:4f6c30876dfa 250 /** @defgroup RCCEx_PLLSAI_DIVR RCCEx PLLSAI DIVR
Kojto 107:4f6c30876dfa 251 * @{
Kojto 107:4f6c30876dfa 252 */
Kojto 107:4f6c30876dfa 253 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 254 #define RCC_PLLSAIDIVR_4 RCC_DCKCFGR1_PLLSAIDIVR_0
Kojto 107:4f6c30876dfa 255 #define RCC_PLLSAIDIVR_8 RCC_DCKCFGR1_PLLSAIDIVR_1
Kojto 107:4f6c30876dfa 256 #define RCC_PLLSAIDIVR_16 RCC_DCKCFGR1_PLLSAIDIVR
Kojto 107:4f6c30876dfa 257 /**
Kojto 107:4f6c30876dfa 258 * @}
Kojto 107:4f6c30876dfa 259 */
Kojto 107:4f6c30876dfa 260
Kojto 107:4f6c30876dfa 261 /** @defgroup RCCEx_I2S_Clock_Source RCCEx I2S Clock Source
Kojto 107:4f6c30876dfa 262 * @{
Kojto 107:4f6c30876dfa 263 */
Kojto 107:4f6c30876dfa 264 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 265 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC
Kojto 107:4f6c30876dfa 266
Kojto 107:4f6c30876dfa 267 /**
Kojto 107:4f6c30876dfa 268 * @}
Kojto 107:4f6c30876dfa 269 */
Kojto 107:4f6c30876dfa 270
Kojto 107:4f6c30876dfa 271
Kojto 107:4f6c30876dfa 272 /** @defgroup RCCEx_SAI1_Clock_Source RCCEx SAI1 Clock Source
Kojto 107:4f6c30876dfa 273 * @{
Kojto 107:4f6c30876dfa 274 */
Kojto 107:4f6c30876dfa 275 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 276 #define RCC_SAI1CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI1SEL_0
Kojto 107:4f6c30876dfa 277 #define RCC_SAI1CLKSOURCE_PIN RCC_DCKCFGR1_SAI1SEL_1
Kojto 107:4f6c30876dfa 278
Kojto 107:4f6c30876dfa 279 /**
Kojto 107:4f6c30876dfa 280 * @}
Kojto 107:4f6c30876dfa 281 */
Kojto 107:4f6c30876dfa 282
Kojto 107:4f6c30876dfa 283 /** @defgroup RCCEx_SAI2_Clock_Source RCCEx SAI2 Clock Source
Kojto 107:4f6c30876dfa 284 * @{
Kojto 107:4f6c30876dfa 285 */
Kojto 107:4f6c30876dfa 286 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 287 #define RCC_SAI2CLKSOURCE_PLLI2S RCC_DCKCFGR1_SAI2SEL_0
Kojto 107:4f6c30876dfa 288 #define RCC_SAI2CLKSOURCE_PIN RCC_DCKCFGR1_SAI2SEL_1
Kojto 107:4f6c30876dfa 289 /**
Kojto 107:4f6c30876dfa 290 * @}
Kojto 107:4f6c30876dfa 291 */
Kojto 107:4f6c30876dfa 292
Kojto 107:4f6c30876dfa 293 /** @defgroup RCCEx_SDMMC1_Clock_Source RCCEx SDMMC1 Clock Source
Kojto 107:4f6c30876dfa 294 * @{
Kojto 107:4f6c30876dfa 295 */
Kojto 107:4f6c30876dfa 296 #define RCC_SDMMC1CLKSOURCE_CLK48 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 297 #define RCC_SDMMC1CLKSOURCE_SYSCLK RCC_DCKCFGR2_SDMMC1SEL
Kojto 107:4f6c30876dfa 298 /**
Kojto 107:4f6c30876dfa 299 * @}
Kojto 107:4f6c30876dfa 300 */
Kojto 107:4f6c30876dfa 301
Kojto 107:4f6c30876dfa 302 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
Kojto 107:4f6c30876dfa 303 * @{
Kojto 107:4f6c30876dfa 304 */
Kojto 107:4f6c30876dfa 305 #define RCC_CECCLKSOURCE_LSE ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 306 #define RCC_CECCLKSOURCE_HSI RCC_DCKCFGR2_CECSEL /* CEC clock is HSI/488*/
Kojto 107:4f6c30876dfa 307 /**
Kojto 107:4f6c30876dfa 308 * @}
Kojto 107:4f6c30876dfa 309 */
Kojto 107:4f6c30876dfa 310
Kojto 107:4f6c30876dfa 311 /** @defgroup RCCEx_USART1_Clock_Source RCCEx USART1 Clock Source
Kojto 107:4f6c30876dfa 312 * @{
Kojto 107:4f6c30876dfa 313 */
Kojto 107:4f6c30876dfa 314 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 315 #define RCC_USART1CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART1SEL_0
Kojto 107:4f6c30876dfa 316 #define RCC_USART1CLKSOURCE_HSI RCC_DCKCFGR2_USART1SEL_1
Kojto 107:4f6c30876dfa 317 #define RCC_USART1CLKSOURCE_LSE RCC_DCKCFGR2_USART1SEL
Kojto 107:4f6c30876dfa 318 /**
Kojto 107:4f6c30876dfa 319 * @}
Kojto 107:4f6c30876dfa 320 */
Kojto 107:4f6c30876dfa 321
Kojto 107:4f6c30876dfa 322 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
Kojto 107:4f6c30876dfa 323 * @{
Kojto 107:4f6c30876dfa 324 */
Kojto 107:4f6c30876dfa 325 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 326 #define RCC_USART2CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART2SEL_0
Kojto 107:4f6c30876dfa 327 #define RCC_USART2CLKSOURCE_HSI RCC_DCKCFGR2_USART2SEL_1
Kojto 107:4f6c30876dfa 328 #define RCC_USART2CLKSOURCE_LSE RCC_DCKCFGR2_USART2SEL
Kojto 107:4f6c30876dfa 329 /**
Kojto 107:4f6c30876dfa 330 * @}
Kojto 107:4f6c30876dfa 331 */
Kojto 107:4f6c30876dfa 332
Kojto 107:4f6c30876dfa 333 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
Kojto 107:4f6c30876dfa 334 * @{
Kojto 107:4f6c30876dfa 335 */
Kojto 107:4f6c30876dfa 336 #define RCC_USART3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 337 #define RCC_USART3CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART3SEL_0
Kojto 107:4f6c30876dfa 338 #define RCC_USART3CLKSOURCE_HSI RCC_DCKCFGR2_USART3SEL_1
Kojto 107:4f6c30876dfa 339 #define RCC_USART3CLKSOURCE_LSE RCC_DCKCFGR2_USART3SEL
Kojto 107:4f6c30876dfa 340 /**
Kojto 107:4f6c30876dfa 341 * @}
Kojto 107:4f6c30876dfa 342 */
Kojto 107:4f6c30876dfa 343
Kojto 107:4f6c30876dfa 344 /** @defgroup RCCEx_UART4_Clock_Source RCCEx UART4 Clock Source
Kojto 107:4f6c30876dfa 345 * @{
Kojto 107:4f6c30876dfa 346 */
Kojto 107:4f6c30876dfa 347 #define RCC_UART4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 348 #define RCC_UART4CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART4SEL_0
Kojto 107:4f6c30876dfa 349 #define RCC_UART4CLKSOURCE_HSI RCC_DCKCFGR2_UART4SEL_1
Kojto 107:4f6c30876dfa 350 #define RCC_UART4CLKSOURCE_LSE RCC_DCKCFGR2_UART4SEL
Kojto 107:4f6c30876dfa 351 /**
Kojto 107:4f6c30876dfa 352 * @}
Kojto 107:4f6c30876dfa 353 */
Kojto 107:4f6c30876dfa 354
Kojto 107:4f6c30876dfa 355 /** @defgroup RCCEx_UART5_Clock_Source RCCEx UART5 Clock Source
Kojto 107:4f6c30876dfa 356 * @{
Kojto 107:4f6c30876dfa 357 */
Kojto 107:4f6c30876dfa 358 #define RCC_UART5CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 359 #define RCC_UART5CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART5SEL_0
Kojto 107:4f6c30876dfa 360 #define RCC_UART5CLKSOURCE_HSI RCC_DCKCFGR2_UART5SEL_1
Kojto 107:4f6c30876dfa 361 #define RCC_UART5CLKSOURCE_LSE RCC_DCKCFGR2_UART5SEL
Kojto 107:4f6c30876dfa 362 /**
Kojto 107:4f6c30876dfa 363 * @}
Kojto 107:4f6c30876dfa 364 */
Kojto 107:4f6c30876dfa 365
Kojto 107:4f6c30876dfa 366 /** @defgroup RCCEx_USART6_Clock_Source RCCEx USART6 Clock Source
Kojto 107:4f6c30876dfa 367 * @{
Kojto 107:4f6c30876dfa 368 */
Kojto 107:4f6c30876dfa 369 #define RCC_USART6CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 370 #define RCC_USART6CLKSOURCE_SYSCLK RCC_DCKCFGR2_USART6SEL_0
Kojto 107:4f6c30876dfa 371 #define RCC_USART6CLKSOURCE_HSI RCC_DCKCFGR2_USART6SEL_1
Kojto 107:4f6c30876dfa 372 #define RCC_USART6CLKSOURCE_LSE RCC_DCKCFGR2_USART6SEL
Kojto 107:4f6c30876dfa 373 /**
Kojto 107:4f6c30876dfa 374 * @}
Kojto 107:4f6c30876dfa 375 */
Kojto 107:4f6c30876dfa 376
Kojto 107:4f6c30876dfa 377 /** @defgroup RCCEx_UART7_Clock_Source RCCEx UART7 Clock Source
Kojto 107:4f6c30876dfa 378 * @{
Kojto 107:4f6c30876dfa 379 */
Kojto 107:4f6c30876dfa 380 #define RCC_UART7CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 381 #define RCC_UART7CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART7SEL_0
Kojto 107:4f6c30876dfa 382 #define RCC_UART7CLKSOURCE_HSI RCC_DCKCFGR2_UART7SEL_1
Kojto 107:4f6c30876dfa 383 #define RCC_UART7CLKSOURCE_LSE RCC_DCKCFGR2_UART7SEL
Kojto 107:4f6c30876dfa 384 /**
Kojto 107:4f6c30876dfa 385 * @}
Kojto 107:4f6c30876dfa 386 */
Kojto 107:4f6c30876dfa 387
Kojto 107:4f6c30876dfa 388 /** @defgroup RCCEx_UART8_Clock_Source RCCEx UART8 Clock Source
Kojto 107:4f6c30876dfa 389 * @{
Kojto 107:4f6c30876dfa 390 */
Kojto 107:4f6c30876dfa 391 #define RCC_UART8CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 392 #define RCC_UART8CLKSOURCE_SYSCLK RCC_DCKCFGR2_UART8SEL_0
Kojto 107:4f6c30876dfa 393 #define RCC_UART8CLKSOURCE_HSI RCC_DCKCFGR2_UART8SEL_1
Kojto 107:4f6c30876dfa 394 #define RCC_UART8CLKSOURCE_LSE RCC_DCKCFGR2_UART8SEL
Kojto 107:4f6c30876dfa 395 /**
Kojto 107:4f6c30876dfa 396 * @}
Kojto 107:4f6c30876dfa 397 */
Kojto 107:4f6c30876dfa 398
Kojto 107:4f6c30876dfa 399 /** @defgroup RCCEx_I2C1_Clock_Source RCCEx I2C1 Clock Source
Kojto 107:4f6c30876dfa 400 * @{
Kojto 107:4f6c30876dfa 401 */
Kojto 107:4f6c30876dfa 402 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 403 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C1SEL_0
Kojto 107:4f6c30876dfa 404 #define RCC_I2C1CLKSOURCE_HSI RCC_DCKCFGR2_I2C1SEL_1
Kojto 107:4f6c30876dfa 405 /**
Kojto 107:4f6c30876dfa 406 * @}
Kojto 107:4f6c30876dfa 407 */
Kojto 107:4f6c30876dfa 408
Kojto 107:4f6c30876dfa 409 /** @defgroup RCCEx_I2C2_Clock_Source RCCEx I2C2 Clock Source
Kojto 107:4f6c30876dfa 410 * @{
Kojto 107:4f6c30876dfa 411 */
Kojto 107:4f6c30876dfa 412 #define RCC_I2C2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 413 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C2SEL_0
Kojto 107:4f6c30876dfa 414 #define RCC_I2C2CLKSOURCE_HSI RCC_DCKCFGR2_I2C2SEL_1
Kojto 107:4f6c30876dfa 415
Kojto 107:4f6c30876dfa 416 /**
Kojto 107:4f6c30876dfa 417 * @}
Kojto 107:4f6c30876dfa 418 */
Kojto 107:4f6c30876dfa 419
Kojto 107:4f6c30876dfa 420 /** @defgroup RCCEx_I2C3_Clock_Source RCCEx I2C3 Clock Source
Kojto 107:4f6c30876dfa 421 * @{
Kojto 107:4f6c30876dfa 422 */
Kojto 107:4f6c30876dfa 423 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 424 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C3SEL_0
Kojto 107:4f6c30876dfa 425 #define RCC_I2C3CLKSOURCE_HSI RCC_DCKCFGR2_I2C3SEL_1
Kojto 107:4f6c30876dfa 426 /**
Kojto 107:4f6c30876dfa 427 * @}
Kojto 107:4f6c30876dfa 428 */
Kojto 107:4f6c30876dfa 429
Kojto 107:4f6c30876dfa 430 /** @defgroup RCCEx_I2C4_Clock_Source RCCEx I2C4 Clock Source
Kojto 107:4f6c30876dfa 431 * @{
Kojto 107:4f6c30876dfa 432 */
Kojto 107:4f6c30876dfa 433 #define RCC_I2C4CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 434 #define RCC_I2C4CLKSOURCE_SYSCLK RCC_DCKCFGR2_I2C4SEL_0
Kojto 107:4f6c30876dfa 435 #define RCC_I2C4CLKSOURCE_HSI RCC_DCKCFGR2_I2C4SEL_1
Kojto 107:4f6c30876dfa 436 /**
Kojto 107:4f6c30876dfa 437 * @}
Kojto 107:4f6c30876dfa 438 */
Kojto 107:4f6c30876dfa 439
Kojto 107:4f6c30876dfa 440
Kojto 107:4f6c30876dfa 441 /** @defgroup RCCEx_LPTIM1_Clock_Source RCCEx LPTIM1 Clock Source
Kojto 107:4f6c30876dfa 442 * @{
Kojto 107:4f6c30876dfa 443 */
Kojto 107:4f6c30876dfa 444 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 445 #define RCC_LPTIM1CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0
Kojto 107:4f6c30876dfa 446 #define RCC_LPTIM1CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1
Kojto 107:4f6c30876dfa 447 #define RCC_LPTIM1CLKSOURCE_LSE RCC_DCKCFGR2_LPTIM1SEL
Kojto 107:4f6c30876dfa 448
Kojto 107:4f6c30876dfa 449 /**
Kojto 107:4f6c30876dfa 450 * @}
Kojto 107:4f6c30876dfa 451 */
Kojto 107:4f6c30876dfa 452
Kojto 107:4f6c30876dfa 453 /** @defgroup RCCEx_CLK48_Clock_Source RCCEx CLK48 Clock Source
Kojto 107:4f6c30876dfa 454 * @{
Kojto 107:4f6c30876dfa 455 */
Kojto 107:4f6c30876dfa 456 #define RCC_CLK48SOURCE_PLL ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 457 #define RCC_CLK48SOURCE_PLLSAIP RCC_DCKCFGR2_CK48MSEL
Kojto 107:4f6c30876dfa 458 /**
Kojto 107:4f6c30876dfa 459 * @}
Kojto 107:4f6c30876dfa 460 */
Kojto 107:4f6c30876dfa 461
Kojto 107:4f6c30876dfa 462 /** @defgroup RCCEx_TIM_Prescaler_Selection RCCEx TIM Prescaler Selection
Kojto 107:4f6c30876dfa 463 * @{
Kojto 107:4f6c30876dfa 464 */
Kojto 107:4f6c30876dfa 465 #define RCC_TIMPRES_DESACTIVATED ((uint32_t)0x00000000)
Kojto 107:4f6c30876dfa 466 #define RCC_TIMPRES_ACTIVATED RCC_DCKCFGR1_TIMPRE
Kojto 107:4f6c30876dfa 467
Kojto 107:4f6c30876dfa 468
Kojto 107:4f6c30876dfa 469 /**
Kojto 107:4f6c30876dfa 470 * @}
Kojto 107:4f6c30876dfa 471 */
Kojto 107:4f6c30876dfa 472
Kojto 107:4f6c30876dfa 473 /**
Kojto 107:4f6c30876dfa 474 * @}
Kojto 107:4f6c30876dfa 475 */
Kojto 107:4f6c30876dfa 476
Kojto 107:4f6c30876dfa 477 /* Exported macro ------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 478 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 107:4f6c30876dfa 479 * @{
Kojto 107:4f6c30876dfa 480 */
Kojto 107:4f6c30876dfa 481 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
Kojto 107:4f6c30876dfa 482 * @brief Enables or disables the AHB/APB peripheral clock.
Kojto 107:4f6c30876dfa 483 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 484 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 485 * using it.
Kojto 107:4f6c30876dfa 486 * @{
Kojto 107:4f6c30876dfa 487 */
Kojto 107:4f6c30876dfa 488
Kojto 107:4f6c30876dfa 489 /** @brief Enables or disables the AHB1 peripheral clock.
Kojto 107:4f6c30876dfa 490 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 491 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 492 * using it.
Kojto 107:4f6c30876dfa 493 */
Kojto 107:4f6c30876dfa 494 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 495 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 496 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto 107:4f6c30876dfa 497 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 498 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto 107:4f6c30876dfa 499 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 500 } while(0)
Kojto 107:4f6c30876dfa 501
Kojto 107:4f6c30876dfa 502 #define __HAL_RCC_DTCMRAMEN_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 503 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 504 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
Kojto 107:4f6c30876dfa 505 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 506 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DTCMRAMEN);\
Kojto 107:4f6c30876dfa 507 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 508 } while(0)
Kojto 107:4f6c30876dfa 509
Kojto 107:4f6c30876dfa 510 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 511 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 512 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 107:4f6c30876dfa 513 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 514 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 107:4f6c30876dfa 515 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 516 } while(0)
Kojto 107:4f6c30876dfa 517
Kojto 107:4f6c30876dfa 518 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 519 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 520 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto 107:4f6c30876dfa 521 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 522 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto 107:4f6c30876dfa 523 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 524 } while(0)
Kojto 107:4f6c30876dfa 525
Kojto 107:4f6c30876dfa 526 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 527 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 528 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 107:4f6c30876dfa 529 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 530 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 107:4f6c30876dfa 531 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 532 } while(0)
Kojto 107:4f6c30876dfa 533
Kojto 107:4f6c30876dfa 534 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 535 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 536 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 107:4f6c30876dfa 537 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 538 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 107:4f6c30876dfa 539 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 540 } while(0)
Kojto 107:4f6c30876dfa 541
Kojto 107:4f6c30876dfa 542 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 543 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 544 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 107:4f6c30876dfa 545 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 546 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 107:4f6c30876dfa 547 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 548 } while(0)
Kojto 107:4f6c30876dfa 549
Kojto 107:4f6c30876dfa 550 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 551 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 552 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 107:4f6c30876dfa 553 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 554 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 107:4f6c30876dfa 555 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 556 } while(0)
Kojto 107:4f6c30876dfa 557
Kojto 107:4f6c30876dfa 558 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 559 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 560 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 107:4f6c30876dfa 561 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 562 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 107:4f6c30876dfa 563 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 564 } while(0)
Kojto 107:4f6c30876dfa 565
Kojto 107:4f6c30876dfa 566 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 567 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 568 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto 107:4f6c30876dfa 569 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 570 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto 107:4f6c30876dfa 571 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 572 } while(0)
Kojto 107:4f6c30876dfa 573
Kojto 107:4f6c30876dfa 574 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 575 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 576 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto 107:4f6c30876dfa 577 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 578 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto 107:4f6c30876dfa 579 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 580 } while(0)
Kojto 107:4f6c30876dfa 581
Kojto 107:4f6c30876dfa 582 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 583 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 584 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 107:4f6c30876dfa 585 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 586 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 107:4f6c30876dfa 587 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 588 } while(0)
Kojto 107:4f6c30876dfa 589
Kojto 107:4f6c30876dfa 590 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 591 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 592 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 107:4f6c30876dfa 593 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 594 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 107:4f6c30876dfa 595 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 596 } while(0)
Kojto 107:4f6c30876dfa 597
Kojto 107:4f6c30876dfa 598 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 599 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 600 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 107:4f6c30876dfa 601 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 602 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 107:4f6c30876dfa 603 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 604 } while(0)
Kojto 107:4f6c30876dfa 605
Kojto 107:4f6c30876dfa 606 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 607 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 608 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto 107:4f6c30876dfa 609 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 610 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto 107:4f6c30876dfa 611 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 612 } while(0)
Kojto 107:4f6c30876dfa 613
Kojto 107:4f6c30876dfa 614 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 615 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 616 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto 107:4f6c30876dfa 617 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 618 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto 107:4f6c30876dfa 619 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 620 } while(0)
Kojto 107:4f6c30876dfa 621
Kojto 107:4f6c30876dfa 622 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 623 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 624 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto 107:4f6c30876dfa 625 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 626 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto 107:4f6c30876dfa 627 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 628 } while(0)
Kojto 107:4f6c30876dfa 629
Kojto 107:4f6c30876dfa 630 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto 107:4f6c30876dfa 631 #define __HAL_RCC_DTCMRAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DTCMRAMEN))
Kojto 107:4f6c30876dfa 632 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
Kojto 107:4f6c30876dfa 633 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto 107:4f6c30876dfa 634 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto 107:4f6c30876dfa 635 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto 107:4f6c30876dfa 636 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 107:4f6c30876dfa 637 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 107:4f6c30876dfa 638 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 107:4f6c30876dfa 639 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto 107:4f6c30876dfa 640 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto 107:4f6c30876dfa 641 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 107:4f6c30876dfa 642 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 107:4f6c30876dfa 643 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 107:4f6c30876dfa 644 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto 107:4f6c30876dfa 645 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto 107:4f6c30876dfa 646 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto 107:4f6c30876dfa 647 /**
Kojto 107:4f6c30876dfa 648 * @brief Enable ETHERNET clock.
Kojto 107:4f6c30876dfa 649 */
Kojto 107:4f6c30876dfa 650 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 651 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 652 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto 107:4f6c30876dfa 653 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 654 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto 107:4f6c30876dfa 655 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 656 } while(0)
Kojto 107:4f6c30876dfa 657
Kojto 107:4f6c30876dfa 658 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 659 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 660 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto 107:4f6c30876dfa 661 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 662 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto 107:4f6c30876dfa 663 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 664 } while(0)
Kojto 107:4f6c30876dfa 665
Kojto 107:4f6c30876dfa 666 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 667 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 668 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto 107:4f6c30876dfa 669 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 670 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto 107:4f6c30876dfa 671 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 672 } while(0)
Kojto 107:4f6c30876dfa 673
Kojto 107:4f6c30876dfa 674 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 675 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 676 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto 107:4f6c30876dfa 677 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 678 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto 107:4f6c30876dfa 679 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 680 } while(0)
Kojto 107:4f6c30876dfa 681
Kojto 107:4f6c30876dfa 682 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 683 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto 107:4f6c30876dfa 684 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto 107:4f6c30876dfa 685 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto 107:4f6c30876dfa 686 } while(0)
Kojto 107:4f6c30876dfa 687 /**
Kojto 107:4f6c30876dfa 688 * @brief Disable ETHERNET clock.
Kojto 107:4f6c30876dfa 689 */
Kojto 107:4f6c30876dfa 690 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto 107:4f6c30876dfa 691 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto 107:4f6c30876dfa 692 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto 107:4f6c30876dfa 693 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto 107:4f6c30876dfa 694 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto 107:4f6c30876dfa 695 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto 107:4f6c30876dfa 696 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto 107:4f6c30876dfa 697 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto 107:4f6c30876dfa 698 } while(0)
Kojto 107:4f6c30876dfa 699
Kojto 107:4f6c30876dfa 700 /** @brief Enable or disable the AHB2 peripheral clock.
Kojto 107:4f6c30876dfa 701 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 702 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 703 * using it.
Kojto 107:4f6c30876dfa 704 */
Kojto 107:4f6c30876dfa 705 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 706 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 707 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 107:4f6c30876dfa 708 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 709 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 107:4f6c30876dfa 710 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 711 } while(0)
Kojto 107:4f6c30876dfa 712
Kojto 107:4f6c30876dfa 713 #define __HAL_RCC_RNG_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 714 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 715 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto 107:4f6c30876dfa 716 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 717 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_RNGEN);\
Kojto 107:4f6c30876dfa 718 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 719 } while(0)
Kojto 107:4f6c30876dfa 720
Kojto 107:4f6c30876dfa 721 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 722 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 723 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
Kojto 107:4f6c30876dfa 724 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 725 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_OTGFSEN);\
Kojto 107:4f6c30876dfa 726 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 727 __HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto 107:4f6c30876dfa 728 } while(0)
Kojto 107:4f6c30876dfa 729
Kojto 107:4f6c30876dfa 730 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto 107:4f6c30876dfa 731 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
Kojto 107:4f6c30876dfa 732
Kojto 107:4f6c30876dfa 733 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto 107:4f6c30876dfa 734 __HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto 107:4f6c30876dfa 735 }while(0)
Kojto 107:4f6c30876dfa 736 #if defined(STM32F756xx)
Kojto 107:4f6c30876dfa 737 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 738 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 739 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto 107:4f6c30876dfa 740 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 741 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto 107:4f6c30876dfa 742 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 743 } while(0)
Kojto 107:4f6c30876dfa 744
Kojto 107:4f6c30876dfa 745 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 746 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 747 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto 107:4f6c30876dfa 748 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 749 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto 107:4f6c30876dfa 750 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 751 } while(0)
Kojto 107:4f6c30876dfa 752
Kojto 107:4f6c30876dfa 753 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto 107:4f6c30876dfa 754 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto 107:4f6c30876dfa 755 #endif /* STM32F756x */
Kojto 107:4f6c30876dfa 756 /** @brief Enables or disables the AHB3 peripheral clock.
Kojto 107:4f6c30876dfa 757 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 758 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 759 * using it.
Kojto 107:4f6c30876dfa 760 */
Kojto 107:4f6c30876dfa 761 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 762 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 763 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto 107:4f6c30876dfa 764 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 765 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto 107:4f6c30876dfa 766 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 767 } while(0)
Kojto 107:4f6c30876dfa 768
Kojto 107:4f6c30876dfa 769 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 770 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 771 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto 107:4f6c30876dfa 772 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 773 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto 107:4f6c30876dfa 774 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 775 } while(0)
Kojto 107:4f6c30876dfa 776
Kojto 107:4f6c30876dfa 777 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto 107:4f6c30876dfa 778 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto 107:4f6c30876dfa 779
Kojto 107:4f6c30876dfa 780 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 107:4f6c30876dfa 781 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 782 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 783 * using it.
Kojto 107:4f6c30876dfa 784 */
Kojto 107:4f6c30876dfa 785 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 786 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 787 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto 107:4f6c30876dfa 788 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 789 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto 107:4f6c30876dfa 790 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 791 } while(0)
Kojto 107:4f6c30876dfa 792
Kojto 107:4f6c30876dfa 793 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 794 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 795 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 107:4f6c30876dfa 796 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 797 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 107:4f6c30876dfa 798 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 799 } while(0)
Kojto 107:4f6c30876dfa 800
Kojto 107:4f6c30876dfa 801 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 802 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 803 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 107:4f6c30876dfa 804 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 805 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 107:4f6c30876dfa 806 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 807 } while(0)
Kojto 107:4f6c30876dfa 808
Kojto 107:4f6c30876dfa 809 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 810 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 811 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 107:4f6c30876dfa 812 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 813 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 107:4f6c30876dfa 814 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 815 } while(0)
Kojto 107:4f6c30876dfa 816
Kojto 107:4f6c30876dfa 817 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 818 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 819 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 107:4f6c30876dfa 820 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 821 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 107:4f6c30876dfa 822 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 823 } while(0)
Kojto 107:4f6c30876dfa 824
Kojto 107:4f6c30876dfa 825 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 826 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 827 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 107:4f6c30876dfa 828 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 829 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 107:4f6c30876dfa 830 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 831 } while(0)
Kojto 107:4f6c30876dfa 832
Kojto 107:4f6c30876dfa 833 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 834 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 835 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 107:4f6c30876dfa 836 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 837 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 107:4f6c30876dfa 838 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 839 } while(0)
Kojto 107:4f6c30876dfa 840
Kojto 107:4f6c30876dfa 841 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 842 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 843 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 107:4f6c30876dfa 844 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 845 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 107:4f6c30876dfa 846 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 847 } while(0)
Kojto 107:4f6c30876dfa 848
Kojto 107:4f6c30876dfa 849 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 850 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 851 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 107:4f6c30876dfa 852 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 853 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 107:4f6c30876dfa 854 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 855 } while(0)
Kojto 107:4f6c30876dfa 856
Kojto 107:4f6c30876dfa 857 #define __HAL_RCC_LPTIM1_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 858 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 859 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto 107:4f6c30876dfa 860 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 861 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_LPTIM1EN);\
Kojto 107:4f6c30876dfa 862 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 863 } while(0)
Kojto 107:4f6c30876dfa 864
Kojto 107:4f6c30876dfa 865 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 866 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 867 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 107:4f6c30876dfa 868 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 869 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 107:4f6c30876dfa 870 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 871 } while(0)
Kojto 107:4f6c30876dfa 872
Kojto 107:4f6c30876dfa 873 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 874 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 875 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 107:4f6c30876dfa 876 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 877 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 107:4f6c30876dfa 878 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 879 } while(0)
Kojto 107:4f6c30876dfa 880
Kojto 107:4f6c30876dfa 881 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 882 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 883 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto 107:4f6c30876dfa 884 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 885 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto 107:4f6c30876dfa 886 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 887 } while(0)
Kojto 107:4f6c30876dfa 888
Kojto 107:4f6c30876dfa 889 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 890 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 891 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 107:4f6c30876dfa 892 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 893 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 107:4f6c30876dfa 894 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 895 } while(0)
Kojto 107:4f6c30876dfa 896
Kojto 107:4f6c30876dfa 897 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 898 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 899 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 107:4f6c30876dfa 900 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 901 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 107:4f6c30876dfa 902 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 903 } while(0)
Kojto 107:4f6c30876dfa 904
Kojto 107:4f6c30876dfa 905 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 906 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 907 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 107:4f6c30876dfa 908 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 909 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 107:4f6c30876dfa 910 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 911 } while(0)
Kojto 107:4f6c30876dfa 912
Kojto 107:4f6c30876dfa 913 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 914 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 915 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 107:4f6c30876dfa 916 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 917 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 107:4f6c30876dfa 918 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 919 } while(0)
Kojto 107:4f6c30876dfa 920
Kojto 107:4f6c30876dfa 921 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 922 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 923 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 107:4f6c30876dfa 924 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 925 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 107:4f6c30876dfa 926 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 927 } while(0)
Kojto 107:4f6c30876dfa 928
Kojto 107:4f6c30876dfa 929 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 930 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 931 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 107:4f6c30876dfa 932 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 933 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 107:4f6c30876dfa 934 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 935 } while(0)
Kojto 107:4f6c30876dfa 936
Kojto 107:4f6c30876dfa 937 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 938 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 939 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 107:4f6c30876dfa 940 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 941 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 107:4f6c30876dfa 942 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 943 } while(0)
Kojto 107:4f6c30876dfa 944
Kojto 107:4f6c30876dfa 945 #define __HAL_RCC_I2C4_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 946 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 947 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
Kojto 107:4f6c30876dfa 948 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 949 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C4EN);\
Kojto 107:4f6c30876dfa 950 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 951 } while(0)
Kojto 107:4f6c30876dfa 952
Kojto 107:4f6c30876dfa 953 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 954 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 955 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 107:4f6c30876dfa 956 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 957 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 107:4f6c30876dfa 958 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 959 } while(0)
Kojto 107:4f6c30876dfa 960
Kojto 107:4f6c30876dfa 961 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 962 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 963 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 107:4f6c30876dfa 964 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 965 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 107:4f6c30876dfa 966 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 967 } while(0)
Kojto 107:4f6c30876dfa 968
Kojto 107:4f6c30876dfa 969 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 970 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 971 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 107:4f6c30876dfa 972 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 973 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 107:4f6c30876dfa 974 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 975 } while(0)
Kojto 107:4f6c30876dfa 976
Kojto 107:4f6c30876dfa 977 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 978 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 979 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 107:4f6c30876dfa 980 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 981 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 107:4f6c30876dfa 982 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 983 } while(0)
Kojto 107:4f6c30876dfa 984
Kojto 107:4f6c30876dfa 985 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 986 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 987 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto 107:4f6c30876dfa 988 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 989 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto 107:4f6c30876dfa 990 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 991 } while(0)
Kojto 107:4f6c30876dfa 992
Kojto 107:4f6c30876dfa 993 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 994 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 995 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto 107:4f6c30876dfa 996 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 997 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto 107:4f6c30876dfa 998 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 999 } while(0)
Kojto 107:4f6c30876dfa 1000
Kojto 107:4f6c30876dfa 1001 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto 107:4f6c30876dfa 1002 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 107:4f6c30876dfa 1003 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 107:4f6c30876dfa 1004 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 107:4f6c30876dfa 1005 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 107:4f6c30876dfa 1006 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 107:4f6c30876dfa 1007 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 107:4f6c30876dfa 1008 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 107:4f6c30876dfa 1009 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 107:4f6c30876dfa 1010 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_LPTIM1EN))
Kojto 107:4f6c30876dfa 1011 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 107:4f6c30876dfa 1012 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 107:4f6c30876dfa 1013 #define __HAL_RCC_SPDIFRX_CLK_DISABLE()(RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto 107:4f6c30876dfa 1014 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 107:4f6c30876dfa 1015 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 107:4f6c30876dfa 1016 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 107:4f6c30876dfa 1017 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 107:4f6c30876dfa 1018 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 107:4f6c30876dfa 1019 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 107:4f6c30876dfa 1020 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto 107:4f6c30876dfa 1021 #define __HAL_RCC_I2C4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C4EN))
Kojto 107:4f6c30876dfa 1022 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto 107:4f6c30876dfa 1023 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto 107:4f6c30876dfa 1024 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto 107:4f6c30876dfa 1025 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 107:4f6c30876dfa 1026 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto 107:4f6c30876dfa 1027 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto 107:4f6c30876dfa 1028
Kojto 107:4f6c30876dfa 1029 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 107:4f6c30876dfa 1030 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 1031 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 1032 * using it.
Kojto 107:4f6c30876dfa 1033 */
Kojto 107:4f6c30876dfa 1034 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1035 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1036 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 107:4f6c30876dfa 1037 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1038 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 107:4f6c30876dfa 1039 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1040 } while(0)
Kojto 107:4f6c30876dfa 1041
Kojto 107:4f6c30876dfa 1042 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1043 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1044 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 107:4f6c30876dfa 1045 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1046 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 107:4f6c30876dfa 1047 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1048 } while(0)
Kojto 107:4f6c30876dfa 1049
Kojto 107:4f6c30876dfa 1050 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1051 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1052 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 107:4f6c30876dfa 1053 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1054 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 107:4f6c30876dfa 1055 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1056 } while(0)
Kojto 107:4f6c30876dfa 1057
Kojto 107:4f6c30876dfa 1058 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1059 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1060 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 107:4f6c30876dfa 1061 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1062 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 107:4f6c30876dfa 1063 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1064 } while(0)
Kojto 107:4f6c30876dfa 1065
Kojto 107:4f6c30876dfa 1066 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1067 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1068 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 107:4f6c30876dfa 1069 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1070 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 107:4f6c30876dfa 1071 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1072 } while(0)
Kojto 107:4f6c30876dfa 1073
Kojto 107:4f6c30876dfa 1074 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1075 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1076 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 107:4f6c30876dfa 1077 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1078 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 107:4f6c30876dfa 1079 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1080 } while(0)
Kojto 107:4f6c30876dfa 1081
Kojto 107:4f6c30876dfa 1082 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1083 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1084 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 107:4f6c30876dfa 1085 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1086 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 107:4f6c30876dfa 1087 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1088 } while(0)
Kojto 107:4f6c30876dfa 1089
Kojto 107:4f6c30876dfa 1090 #define __HAL_RCC_SDMMC1_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1091 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1092 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
Kojto 107:4f6c30876dfa 1093 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1094 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDMMC1EN);\
Kojto 107:4f6c30876dfa 1095 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1096 } while(0)
Kojto 107:4f6c30876dfa 1097
Kojto 107:4f6c30876dfa 1098 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1099 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1100 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 107:4f6c30876dfa 1101 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1102 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 107:4f6c30876dfa 1103 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1104 } while(0)
Kojto 107:4f6c30876dfa 1105
Kojto 107:4f6c30876dfa 1106 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1107 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1108 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 107:4f6c30876dfa 1109 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1110 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 107:4f6c30876dfa 1111 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1112 } while(0)
Kojto 107:4f6c30876dfa 1113
Kojto 107:4f6c30876dfa 1114 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1115 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1116 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 107:4f6c30876dfa 1117 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1118 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 107:4f6c30876dfa 1119 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1120 } while(0)
Kojto 107:4f6c30876dfa 1121
Kojto 107:4f6c30876dfa 1122 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1123 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1124 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 107:4f6c30876dfa 1125 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1126 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 107:4f6c30876dfa 1127 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1128 } while(0)
Kojto 107:4f6c30876dfa 1129
Kojto 107:4f6c30876dfa 1130 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1131 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1132 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 107:4f6c30876dfa 1133 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1134 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 107:4f6c30876dfa 1135 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1136 } while(0)
Kojto 107:4f6c30876dfa 1137
Kojto 107:4f6c30876dfa 1138 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1139 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1140 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto 107:4f6c30876dfa 1141 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1142 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto 107:4f6c30876dfa 1143 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1144 } while(0)
Kojto 107:4f6c30876dfa 1145
Kojto 107:4f6c30876dfa 1146 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1147 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1148 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto 107:4f6c30876dfa 1149 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1150 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto 107:4f6c30876dfa 1151 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1152 } while(0)
Kojto 107:4f6c30876dfa 1153
Kojto 107:4f6c30876dfa 1154 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1155 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1156 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto 107:4f6c30876dfa 1157 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1158 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto 107:4f6c30876dfa 1159 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1160 } while(0)
Kojto 107:4f6c30876dfa 1161
Kojto 107:4f6c30876dfa 1162 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1163 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1164 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto 107:4f6c30876dfa 1165 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1166 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto 107:4f6c30876dfa 1167 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1168 } while(0)
Kojto 107:4f6c30876dfa 1169
Kojto 107:4f6c30876dfa 1170 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 1171 #define __HAL_RCC_LTDC_CLK_ENABLE() do { \
Kojto 107:4f6c30876dfa 1172 __IO uint32_t tmpreg; \
Kojto 107:4f6c30876dfa 1173 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto 107:4f6c30876dfa 1174 /* Delay after an RCC peripheral clock enabling */ \
Kojto 107:4f6c30876dfa 1175 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_LTDCEN);\
Kojto 107:4f6c30876dfa 1176 UNUSED(tmpreg); \
Kojto 107:4f6c30876dfa 1177 } while(0)
Kojto 107:4f6c30876dfa 1178 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 1179
Kojto 107:4f6c30876dfa 1180 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 107:4f6c30876dfa 1181 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 107:4f6c30876dfa 1182 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 107:4f6c30876dfa 1183 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 107:4f6c30876dfa 1184 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 107:4f6c30876dfa 1185 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto 107:4f6c30876dfa 1186 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto 107:4f6c30876dfa 1187 #define __HAL_RCC_SDMMC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDMMC1EN))
Kojto 107:4f6c30876dfa 1188 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 107:4f6c30876dfa 1189 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto 107:4f6c30876dfa 1190 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 107:4f6c30876dfa 1191 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto 107:4f6c30876dfa 1192 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 107:4f6c30876dfa 1193 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto 107:4f6c30876dfa 1194 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto 107:4f6c30876dfa 1195 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto 107:4f6c30876dfa 1196 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto 107:4f6c30876dfa 1197 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 1198 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto 107:4f6c30876dfa 1199 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 1200 /**
Kojto 107:4f6c30876dfa 1201 * @}
Kojto 107:4f6c30876dfa 1202 */
Kojto 107:4f6c30876dfa 1203
Kojto 107:4f6c30876dfa 1204
Kojto 107:4f6c30876dfa 1205 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable_Status Peripheral Clock Enable Disable Status
Kojto 107:4f6c30876dfa 1206 * @brief Get the enable or disable status of the AHB/APB peripheral clock.
Kojto 107:4f6c30876dfa 1207 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 1208 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 1209 * using it.
Kojto 107:4f6c30876dfa 1210 * @{
Kojto 107:4f6c30876dfa 1211 */
Kojto 107:4f6c30876dfa 1212
Kojto 107:4f6c30876dfa 1213 /** @brief Get the enable or disable status of the AHB1 peripheral clock.
Kojto 107:4f6c30876dfa 1214 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 1215 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 1216 * using it.
Kojto 107:4f6c30876dfa 1217 */
Kojto 107:4f6c30876dfa 1218 #define __HAL_RCC_BKPSRAM_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) != RESET)
Kojto 107:4f6c30876dfa 1219 #define __HAL_RCC_DTCMRAMEN_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) != RESET)
Kojto 107:4f6c30876dfa 1220 #define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) != RESET)
Kojto 107:4f6c30876dfa 1221 #define __HAL_RCC_DMA2D_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) != RESET)
Kojto 107:4f6c30876dfa 1222 #define __HAL_RCC_USB_OTG_HS_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) != RESET)
Kojto 107:4f6c30876dfa 1223 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) != RESET)
Kojto 107:4f6c30876dfa 1224 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) != RESET)
Kojto 107:4f6c30876dfa 1225 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) != RESET)
Kojto 107:4f6c30876dfa 1226 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) != RESET)
Kojto 107:4f6c30876dfa 1227 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) != RESET)
Kojto 107:4f6c30876dfa 1228 #define __HAL_RCC_GPIOE_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) != RESET)
Kojto 107:4f6c30876dfa 1229 #define __HAL_RCC_GPIOF_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) != RESET)
Kojto 107:4f6c30876dfa 1230 #define __HAL_RCC_GPIOG_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) != RESET)
Kojto 107:4f6c30876dfa 1231 #define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) != RESET)
Kojto 107:4f6c30876dfa 1232 #define __HAL_RCC_GPIOI_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) != RESET)
Kojto 107:4f6c30876dfa 1233 #define __HAL_RCC_GPIOJ_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) != RESET)
Kojto 107:4f6c30876dfa 1234 #define __HAL_RCC_GPIOK_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) != RESET)
Kojto 107:4f6c30876dfa 1235
Kojto 107:4f6c30876dfa 1236 #define __HAL_RCC_BKPSRAM_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_BKPSRAMEN)) == RESET)
Kojto 107:4f6c30876dfa 1237 #define __HAL_RCC_DTCMRAMEN_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DTCMRAMEN)) == RESET)
Kojto 107:4f6c30876dfa 1238 #define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2EN)) == RESET)
Kojto 107:4f6c30876dfa 1239 #define __HAL_RCC_DMA2D_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_DMA2DEN)) == RESET)
Kojto 107:4f6c30876dfa 1240 #define __HAL_RCC_USB_OTG_HS_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSEN)) == RESET)
Kojto 107:4f6c30876dfa 1241 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_OTGHSULPIEN)) == RESET)
Kojto 107:4f6c30876dfa 1242 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOAEN)) == RESET)
Kojto 107:4f6c30876dfa 1243 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOBEN)) == RESET)
Kojto 107:4f6c30876dfa 1244 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOCEN)) == RESET)
Kojto 107:4f6c30876dfa 1245 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIODEN)) == RESET)
Kojto 107:4f6c30876dfa 1246 #define __HAL_RCC_GPIOE_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOEEN)) == RESET)
Kojto 107:4f6c30876dfa 1247 #define __HAL_RCC_GPIOF_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOFEN)) == RESET)
Kojto 107:4f6c30876dfa 1248 #define __HAL_RCC_GPIOG_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOGEN)) == RESET)
Kojto 107:4f6c30876dfa 1249 #define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOHEN)) == RESET)
Kojto 107:4f6c30876dfa 1250 #define __HAL_RCC_GPIOI_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOIEN)) == RESET)
Kojto 107:4f6c30876dfa 1251 #define __HAL_RCC_GPIOJ_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOJEN)) == RESET)
Kojto 107:4f6c30876dfa 1252 #define __HAL_RCC_GPIOK_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_GPIOKEN)) == RESET)
Kojto 107:4f6c30876dfa 1253 /**
Kojto 107:4f6c30876dfa 1254 * @brief Enable ETHERNET clock.
Kojto 107:4f6c30876dfa 1255 */
Kojto 107:4f6c30876dfa 1256 #define __HAL_RCC_ETHMAC_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) != RESET)
Kojto 107:4f6c30876dfa 1257 #define __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) != RESET)
Kojto 107:4f6c30876dfa 1258 #define __HAL_RCC_ETHMACRX_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) != RESET)
Kojto 107:4f6c30876dfa 1259 #define __HAL_RCC_ETHMACPTP_IS_CLK_ENABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) != RESET)
Kojto 107:4f6c30876dfa 1260 #define __HAL_RCC_ETH_IS_CLK_ENABLED() (__HAL_RCC_ETHMAC_IS_CLK_ENABLED() && \
Kojto 107:4f6c30876dfa 1261 __HAL_RCC_ETHMACTX_IS_CLK_ENABLED() && \
Kojto 107:4f6c30876dfa 1262 __HAL_RCC_ETHMACRX_IS_CLK_ENABLED())
Kojto 107:4f6c30876dfa 1263
Kojto 107:4f6c30876dfa 1264 /**
Kojto 107:4f6c30876dfa 1265 * @brief Disable ETHERNET clock.
Kojto 107:4f6c30876dfa 1266 */
Kojto 107:4f6c30876dfa 1267 #define __HAL_RCC_ETHMAC_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACEN)) == RESET)
Kojto 107:4f6c30876dfa 1268 #define __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACTXEN)) == RESET)
Kojto 107:4f6c30876dfa 1269 #define __HAL_RCC_ETHMACRX_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACRXEN)) == RESET)
Kojto 107:4f6c30876dfa 1270 #define __HAL_RCC_ETHMACPTP_IS_CLK_DISABLED() ((RCC->AHB1ENR & (RCC_AHB1ENR_ETHMACPTPEN)) == RESET)
Kojto 107:4f6c30876dfa 1271 #define __HAL_RCC_ETH_IS_CLK_DISABLED() (__HAL_RCC_ETHMAC_IS_CLK_DISABLED() && \
Kojto 107:4f6c30876dfa 1272 __HAL_RCC_ETHMACTX_IS_CLK_DISABLED() && \
Kojto 107:4f6c30876dfa 1273 __HAL_RCC_ETHMACRX_IS_CLK_DISABLED())
Kojto 107:4f6c30876dfa 1274
Kojto 107:4f6c30876dfa 1275 /** @brief Get the enable or disable status of the AHB2 peripheral clock.
Kojto 107:4f6c30876dfa 1276 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 1277 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 1278 * using it.
Kojto 107:4f6c30876dfa 1279 */
Kojto 107:4f6c30876dfa 1280 #define __HAL_RCC_DCMI_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) != RESET)
Kojto 107:4f6c30876dfa 1281 #define __HAL_RCC_RNG_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) != RESET)
Kojto 107:4f6c30876dfa 1282 #define __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) != RESET)
Kojto 107:4f6c30876dfa 1283
Kojto 107:4f6c30876dfa 1284
Kojto 107:4f6c30876dfa 1285 #define __HAL_RCC_DCMI_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_DCMIEN)) == RESET)
Kojto 107:4f6c30876dfa 1286 #define __HAL_RCC_RNG_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_RNGEN)) == RESET)
Kojto 107:4f6c30876dfa 1287 #define __HAL_RCC_USB_IS_OTG_FS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_OTGFSEN)) == RESET)
Kojto 107:4f6c30876dfa 1288
Kojto 107:4f6c30876dfa 1289 #if defined(STM32F756xx)
Kojto 107:4f6c30876dfa 1290 #define __HAL_RCC_CRYP_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) != RESET)
Kojto 107:4f6c30876dfa 1291 #define __HAL_RCC_HASH_IS_CLK_ENABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) != RESET)
Kojto 107:4f6c30876dfa 1292 #define __HAL_RCC_CRYP_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_CRYPEN)) == RESET)
Kojto 107:4f6c30876dfa 1293 #define __HAL_RCC_HASH_IS_CLK_DISABLED() ((RCC->AHB2ENR & (RCC_AHB2ENR_HASHEN)) == RESET)
Kojto 107:4f6c30876dfa 1294 #endif /* STM32F756x */
Kojto 107:4f6c30876dfa 1295
Kojto 107:4f6c30876dfa 1296 /** @brief Get the enable or disable status of the AHB3 peripheral clock.
Kojto 107:4f6c30876dfa 1297 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 1298 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 1299 * using it.
Kojto 107:4f6c30876dfa 1300 */
Kojto 107:4f6c30876dfa 1301 #define __HAL_RCC_FMC_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) != RESET)
Kojto 107:4f6c30876dfa 1302 #define __HAL_RCC_QSPI_IS_CLK_ENABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) != RESET)
Kojto 107:4f6c30876dfa 1303
Kojto 107:4f6c30876dfa 1304 #define __HAL_RCC_FMC_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_FMCEN)) == RESET)
Kojto 107:4f6c30876dfa 1305 #define __HAL_RCC_QSPI_IS_CLK_DISABLED() ((RCC->AHB3ENR & (RCC_AHB3ENR_QSPIEN)) == RESET)
Kojto 107:4f6c30876dfa 1306
Kojto 107:4f6c30876dfa 1307 /** @brief Get the enable or disable status of the APB1 peripheral clock.
Kojto 107:4f6c30876dfa 1308 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 1309 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 1310 * using it.
Kojto 107:4f6c30876dfa 1311 */
Kojto 107:4f6c30876dfa 1312 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
Kojto 107:4f6c30876dfa 1313 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
Kojto 107:4f6c30876dfa 1314 #define __HAL_RCC_TIM4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) != RESET)
Kojto 107:4f6c30876dfa 1315 #define __HAL_RCC_TIM5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) != RESET)
Kojto 107:4f6c30876dfa 1316 #define __HAL_RCC_TIM6_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) != RESET)
Kojto 107:4f6c30876dfa 1317 #define __HAL_RCC_TIM7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) != RESET)
Kojto 107:4f6c30876dfa 1318 #define __HAL_RCC_TIM12_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) != RESET)
Kojto 107:4f6c30876dfa 1319 #define __HAL_RCC_TIM13_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) != RESET)
Kojto 107:4f6c30876dfa 1320 #define __HAL_RCC_TIM14_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) != RESET)
Kojto 107:4f6c30876dfa 1321 #define __HAL_RCC_LPTIM1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) != RESET)
Kojto 107:4f6c30876dfa 1322 #define __HAL_RCC_SPI2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) != RESET)
Kojto 107:4f6c30876dfa 1323 #define __HAL_RCC_SPI3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) != RESET)
Kojto 107:4f6c30876dfa 1324 #define __HAL_RCC_SPDIFRX_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) != RESET)
Kojto 107:4f6c30876dfa 1325 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
Kojto 107:4f6c30876dfa 1326 #define __HAL_RCC_USART3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) != RESET)
Kojto 107:4f6c30876dfa 1327 #define __HAL_RCC_UART4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) != RESET)
Kojto 107:4f6c30876dfa 1328 #define __HAL_RCC_UART5_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) != RESET)
Kojto 107:4f6c30876dfa 1329 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
Kojto 107:4f6c30876dfa 1330 #define __HAL_RCC_I2C2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) != RESET)
Kojto 107:4f6c30876dfa 1331 #define __HAL_RCC_I2C3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) != RESET)
Kojto 107:4f6c30876dfa 1332 #define __HAL_RCC_I2C4_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) != RESET)
Kojto 107:4f6c30876dfa 1333 #define __HAL_RCC_CAN1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) != RESET)
Kojto 107:4f6c30876dfa 1334 #define __HAL_RCC_CAN2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) != RESET)
Kojto 107:4f6c30876dfa 1335 #define __HAL_RCC_CEC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) != RESET)
Kojto 107:4f6c30876dfa 1336 #define __HAL_RCC_DAC_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) != RESET)
Kojto 107:4f6c30876dfa 1337 #define __HAL_RCC_UART7_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) != RESET)
Kojto 107:4f6c30876dfa 1338 #define __HAL_RCC_UART8_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) != RESET)
Kojto 107:4f6c30876dfa 1339
Kojto 107:4f6c30876dfa 1340 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
Kojto 107:4f6c30876dfa 1341 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
Kojto 107:4f6c30876dfa 1342 #define __HAL_RCC_TIM4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM4EN)) == RESET)
Kojto 107:4f6c30876dfa 1343 #define __HAL_RCC_TIM5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM5EN)) == RESET)
Kojto 107:4f6c30876dfa 1344 #define __HAL_RCC_TIM6_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM6EN)) == RESET)
Kojto 107:4f6c30876dfa 1345 #define __HAL_RCC_TIM7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM7EN)) == RESET)
Kojto 107:4f6c30876dfa 1346 #define __HAL_RCC_TIM12_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM12EN)) == RESET)
Kojto 107:4f6c30876dfa 1347 #define __HAL_RCC_TIM13_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM13EN)) == RESET)
Kojto 107:4f6c30876dfa 1348 #define __HAL_RCC_TIM14_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM14EN)) == RESET)
Kojto 107:4f6c30876dfa 1349 #define __HAL_RCC_LPTIM1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_LPTIM1EN)) == RESET)
Kojto 107:4f6c30876dfa 1350 #define __HAL_RCC_SPI2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI2EN)) == RESET)
Kojto 107:4f6c30876dfa 1351 #define __HAL_RCC_SPI3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_SPI3EN)) == RESET)
Kojto 107:4f6c30876dfa 1352 #define __HAL_RCC_SPDIFRX_IS_CLK_DISABLED()((RCC->APB1ENR & (RCC_APB1ENR_SPDIFRXEN)) == RESET)
Kojto 107:4f6c30876dfa 1353 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
Kojto 107:4f6c30876dfa 1354 #define __HAL_RCC_USART3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART3EN)) == RESET)
Kojto 107:4f6c30876dfa 1355 #define __HAL_RCC_UART4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART4EN)) == RESET)
Kojto 107:4f6c30876dfa 1356 #define __HAL_RCC_UART5_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART5EN)) == RESET)
Kojto 107:4f6c30876dfa 1357 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
Kojto 107:4f6c30876dfa 1358 #define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
Kojto 107:4f6c30876dfa 1359 #define __HAL_RCC_I2C3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C3EN)) == RESET)
Kojto 107:4f6c30876dfa 1360 #define __HAL_RCC_I2C4_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C4EN)) == RESET)
Kojto 107:4f6c30876dfa 1361 #define __HAL_RCC_CAN1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN1EN)) == RESET)
Kojto 107:4f6c30876dfa 1362 #define __HAL_RCC_CAN2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CAN2EN)) == RESET)
Kojto 107:4f6c30876dfa 1363 #define __HAL_RCC_CEC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_CECEN)) == RESET)
Kojto 107:4f6c30876dfa 1364 #define __HAL_RCC_DAC_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_DACEN)) == RESET)
Kojto 107:4f6c30876dfa 1365 #define __HAL_RCC_UART7_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART7EN)) == RESET)
Kojto 107:4f6c30876dfa 1366 #define __HAL_RCC_UART8_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_UART8EN)) == RESET)
Kojto 107:4f6c30876dfa 1367
Kojto 107:4f6c30876dfa 1368 /** @brief Get the enable or disable status of the APB2 peripheral clock.
Kojto 107:4f6c30876dfa 1369 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 107:4f6c30876dfa 1370 * is disabled and the application software has to enable this clock before
Kojto 107:4f6c30876dfa 1371 * using it.
Kojto 107:4f6c30876dfa 1372 */
Kojto 107:4f6c30876dfa 1373 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
Kojto 107:4f6c30876dfa 1374 #define __HAL_RCC_TIM8_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) != RESET)
Kojto 107:4f6c30876dfa 1375 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
Kojto 107:4f6c30876dfa 1376 #define __HAL_RCC_USART6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) != RESET)
Kojto 107:4f6c30876dfa 1377 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
Kojto 107:4f6c30876dfa 1378 #define __HAL_RCC_ADC2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) != RESET)
Kojto 107:4f6c30876dfa 1379 #define __HAL_RCC_ADC3_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) != RESET)
Kojto 107:4f6c30876dfa 1380 #define __HAL_RCC_SDMMC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) != RESET)
Kojto 107:4f6c30876dfa 1381 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
Kojto 107:4f6c30876dfa 1382 #define __HAL_RCC_SPI4_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) != RESET)
Kojto 107:4f6c30876dfa 1383 #define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
Kojto 107:4f6c30876dfa 1384 #define __HAL_RCC_TIM10_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) != RESET)
Kojto 107:4f6c30876dfa 1385 #define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
Kojto 107:4f6c30876dfa 1386 #define __HAL_RCC_SPI5_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) != RESET)
Kojto 107:4f6c30876dfa 1387 #define __HAL_RCC_SPI6_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) != RESET)
Kojto 107:4f6c30876dfa 1388 #define __HAL_RCC_SAI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) != RESET)
Kojto 107:4f6c30876dfa 1389 #define __HAL_RCC_SAI2_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) != RESET)
Kojto 107:4f6c30876dfa 1390 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 1391 #define __HAL_RCC_LTDC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) != RESET)
Kojto 107:4f6c30876dfa 1392 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 1393 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
Kojto 107:4f6c30876dfa 1394 #define __HAL_RCC_TIM8_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM8EN)) == RESET)
Kojto 107:4f6c30876dfa 1395 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
Kojto 107:4f6c30876dfa 1396 #define __HAL_RCC_USART6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART6EN)) == RESET)
Kojto 107:4f6c30876dfa 1397 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
Kojto 107:4f6c30876dfa 1398 #define __HAL_RCC_ADC2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC2EN)) == RESET)
Kojto 107:4f6c30876dfa 1399 #define __HAL_RCC_ADC3_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC3EN)) == RESET)
Kojto 107:4f6c30876dfa 1400 #define __HAL_RCC_SDMMC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SDMMC1EN)) == RESET)
Kojto 107:4f6c30876dfa 1401 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
Kojto 107:4f6c30876dfa 1402 #define __HAL_RCC_SPI4_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI4EN)) == RESET)
Kojto 107:4f6c30876dfa 1403 #define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
Kojto 107:4f6c30876dfa 1404 #define __HAL_RCC_TIM10_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM10EN)) == RESET)
Kojto 107:4f6c30876dfa 1405 #define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
Kojto 107:4f6c30876dfa 1406 #define __HAL_RCC_SPI5_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI5EN)) == RESET)
Kojto 107:4f6c30876dfa 1407 #define __HAL_RCC_SPI6_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI6EN)) == RESET)
Kojto 107:4f6c30876dfa 1408 #define __HAL_RCC_SAI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI1EN)) == RESET)
Kojto 107:4f6c30876dfa 1409 #define __HAL_RCC_SAI2_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SAI2EN)) == RESET)
Kojto 107:4f6c30876dfa 1410 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 1411 #define __HAL_RCC_LTDC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_LTDCEN)) == RESET)
Kojto 107:4f6c30876dfa 1412 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 1413 /**
Kojto 107:4f6c30876dfa 1414 * @}
Kojto 107:4f6c30876dfa 1415 */
Kojto 107:4f6c30876dfa 1416
Kojto 107:4f6c30876dfa 1417 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
Kojto 107:4f6c30876dfa 1418 * @brief Forces or releases AHB/APB peripheral reset.
Kojto 107:4f6c30876dfa 1419 * @{
Kojto 107:4f6c30876dfa 1420 */
Kojto 107:4f6c30876dfa 1421
Kojto 107:4f6c30876dfa 1422 /** @brief Force or release AHB1 peripheral reset.
Kojto 107:4f6c30876dfa 1423 */
Kojto 107:4f6c30876dfa 1424 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
Kojto 107:4f6c30876dfa 1425 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
Kojto 107:4f6c30876dfa 1426 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
Kojto 107:4f6c30876dfa 1427 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
Kojto 107:4f6c30876dfa 1428 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 107:4f6c30876dfa 1429 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 107:4f6c30876dfa 1430 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 107:4f6c30876dfa 1431 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
Kojto 107:4f6c30876dfa 1432 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
Kojto 107:4f6c30876dfa 1433 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
Kojto 107:4f6c30876dfa 1434 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
Kojto 107:4f6c30876dfa 1435 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 107:4f6c30876dfa 1436 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
Kojto 107:4f6c30876dfa 1437 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
Kojto 107:4f6c30876dfa 1438 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
Kojto 107:4f6c30876dfa 1439
Kojto 107:4f6c30876dfa 1440 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 107:4f6c30876dfa 1441 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto 107:4f6c30876dfa 1442 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto 107:4f6c30876dfa 1443 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto 107:4f6c30876dfa 1444 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 107:4f6c30876dfa 1445 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 107:4f6c30876dfa 1446 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 107:4f6c30876dfa 1447 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto 107:4f6c30876dfa 1448 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto 107:4f6c30876dfa 1449 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 107:4f6c30876dfa 1450 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 107:4f6c30876dfa 1451 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 107:4f6c30876dfa 1452 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 107:4f6c30876dfa 1453 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto 107:4f6c30876dfa 1454 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto 107:4f6c30876dfa 1455
Kojto 107:4f6c30876dfa 1456 /** @brief Force or release AHB2 peripheral reset.
Kojto 107:4f6c30876dfa 1457 */
Kojto 107:4f6c30876dfa 1458 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto 107:4f6c30876dfa 1459 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
Kojto 107:4f6c30876dfa 1460
Kojto 107:4f6c30876dfa 1461 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
Kojto 107:4f6c30876dfa 1462 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
Kojto 107:4f6c30876dfa 1463
Kojto 107:4f6c30876dfa 1464 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto 107:4f6c30876dfa 1465 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto 107:4f6c30876dfa 1466 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto 107:4f6c30876dfa 1467 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto 107:4f6c30876dfa 1468
Kojto 107:4f6c30876dfa 1469 #if defined(STM32F756xx)
Kojto 107:4f6c30876dfa 1470 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
Kojto 107:4f6c30876dfa 1471 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
Kojto 107:4f6c30876dfa 1472 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto 107:4f6c30876dfa 1473 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto 107:4f6c30876dfa 1474 #endif /* STM32F756xx */
Kojto 107:4f6c30876dfa 1475
Kojto 107:4f6c30876dfa 1476 /** @brief Force or release AHB3 peripheral reset
Kojto 107:4f6c30876dfa 1477 */
Kojto 107:4f6c30876dfa 1478 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto 107:4f6c30876dfa 1479 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
Kojto 107:4f6c30876dfa 1480 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
Kojto 107:4f6c30876dfa 1481
Kojto 107:4f6c30876dfa 1482 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto 107:4f6c30876dfa 1483 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto 107:4f6c30876dfa 1484 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto 107:4f6c30876dfa 1485
Kojto 107:4f6c30876dfa 1486 /** @brief Force or release APB1 peripheral reset.
Kojto 107:4f6c30876dfa 1487 */
Kojto 107:4f6c30876dfa 1488 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 107:4f6c30876dfa 1489 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 107:4f6c30876dfa 1490 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 107:4f6c30876dfa 1491 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 107:4f6c30876dfa 1492 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 107:4f6c30876dfa 1493 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 107:4f6c30876dfa 1494 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 107:4f6c30876dfa 1495 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 107:4f6c30876dfa 1496 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 107:4f6c30876dfa 1497 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
Kojto 107:4f6c30876dfa 1498 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 107:4f6c30876dfa 1499 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 107:4f6c30876dfa 1500 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
Kojto 107:4f6c30876dfa 1501 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 107:4f6c30876dfa 1502 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 107:4f6c30876dfa 1503 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 107:4f6c30876dfa 1504 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 107:4f6c30876dfa 1505 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 107:4f6c30876dfa 1506 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 107:4f6c30876dfa 1507 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 107:4f6c30876dfa 1508 #define __HAL_RCC_I2C4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C4RST))
Kojto 107:4f6c30876dfa 1509 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
Kojto 107:4f6c30876dfa 1510 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
Kojto 107:4f6c30876dfa 1511 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
Kojto 107:4f6c30876dfa 1512 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 107:4f6c30876dfa 1513 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
Kojto 107:4f6c30876dfa 1514 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
Kojto 107:4f6c30876dfa 1515
Kojto 107:4f6c30876dfa 1516 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto 107:4f6c30876dfa 1517 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 107:4f6c30876dfa 1518 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 107:4f6c30876dfa 1519 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 107:4f6c30876dfa 1520 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 107:4f6c30876dfa 1521 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 107:4f6c30876dfa 1522 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 107:4f6c30876dfa 1523 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 107:4f6c30876dfa 1524 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 107:4f6c30876dfa 1525 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LPTIM1RST))
Kojto 107:4f6c30876dfa 1526 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 107:4f6c30876dfa 1527 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 107:4f6c30876dfa 1528 #define __HAL_RCC_SPDIFRX_RELEASE_RESET()(RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto 107:4f6c30876dfa 1529 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 107:4f6c30876dfa 1530 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 107:4f6c30876dfa 1531 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 107:4f6c30876dfa 1532 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 107:4f6c30876dfa 1533 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 107:4f6c30876dfa 1534 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 107:4f6c30876dfa 1535 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto 107:4f6c30876dfa 1536 #define __HAL_RCC_I2C4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C4RST))
Kojto 107:4f6c30876dfa 1537 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto 107:4f6c30876dfa 1538 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto 107:4f6c30876dfa 1539 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto 107:4f6c30876dfa 1540 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 107:4f6c30876dfa 1541 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto 107:4f6c30876dfa 1542 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto 107:4f6c30876dfa 1543
Kojto 107:4f6c30876dfa 1544 /** @brief Force or release APB2 peripheral reset.
Kojto 107:4f6c30876dfa 1545 */
Kojto 107:4f6c30876dfa 1546 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 107:4f6c30876dfa 1547 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 107:4f6c30876dfa 1548 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 107:4f6c30876dfa 1549 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 107:4f6c30876dfa 1550 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 107:4f6c30876dfa 1551 #define __HAL_RCC_SDMMC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDMMC1RST))
Kojto 107:4f6c30876dfa 1552 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 107:4f6c30876dfa 1553 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
Kojto 107:4f6c30876dfa 1554 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 107:4f6c30876dfa 1555 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
Kojto 107:4f6c30876dfa 1556 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
Kojto 107:4f6c30876dfa 1557 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
Kojto 107:4f6c30876dfa 1558 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
Kojto 107:4f6c30876dfa 1559 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
Kojto 107:4f6c30876dfa 1560 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
Kojto 107:4f6c30876dfa 1561 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 1562 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
Kojto 107:4f6c30876dfa 1563 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 1564
Kojto 107:4f6c30876dfa 1565 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 107:4f6c30876dfa 1566 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 107:4f6c30876dfa 1567 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 107:4f6c30876dfa 1568 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 107:4f6c30876dfa 1569 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 107:4f6c30876dfa 1570 #define __HAL_RCC_SDMMC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDMMC1RST))
Kojto 107:4f6c30876dfa 1571 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 107:4f6c30876dfa 1572 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto 107:4f6c30876dfa 1573 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 107:4f6c30876dfa 1574 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto 107:4f6c30876dfa 1575 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 107:4f6c30876dfa 1576 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto 107:4f6c30876dfa 1577 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto 107:4f6c30876dfa 1578 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto 107:4f6c30876dfa 1579 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto 107:4f6c30876dfa 1580 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 1581 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto 107:4f6c30876dfa 1582 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 1583 /**
Kojto 107:4f6c30876dfa 1584 * @}
Kojto 107:4f6c30876dfa 1585 */
Kojto 107:4f6c30876dfa 1586
Kojto 107:4f6c30876dfa 1587 /** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
Kojto 107:4f6c30876dfa 1588 * @brief Enables or disables the AHB/APB peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1589 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1590 * power consumption.
Kojto 107:4f6c30876dfa 1591 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1592 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1593 * @{
Kojto 107:4f6c30876dfa 1594 */
Kojto 107:4f6c30876dfa 1595
Kojto 107:4f6c30876dfa 1596 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1597 */
Kojto 107:4f6c30876dfa 1598 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
Kojto 107:4f6c30876dfa 1599 #define __HAL_RCC_AXI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_AXILPEN))
Kojto 107:4f6c30876dfa 1600 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto 107:4f6c30876dfa 1601 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto 107:4f6c30876dfa 1602 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 107:4f6c30876dfa 1603 #define __HAL_RCC_DTCM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DTCMLPEN))
Kojto 107:4f6c30876dfa 1604 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
Kojto 107:4f6c30876dfa 1605 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto 107:4f6c30876dfa 1606 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto 107:4f6c30876dfa 1607 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 107:4f6c30876dfa 1608 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 107:4f6c30876dfa 1609 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 107:4f6c30876dfa 1610 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto 107:4f6c30876dfa 1611 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 107:4f6c30876dfa 1612 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 107:4f6c30876dfa 1613 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 107:4f6c30876dfa 1614 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 107:4f6c30876dfa 1615 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
Kojto 107:4f6c30876dfa 1616 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
Kojto 107:4f6c30876dfa 1617 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto 107:4f6c30876dfa 1618 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto 107:4f6c30876dfa 1619 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 107:4f6c30876dfa 1620 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
Kojto 107:4f6c30876dfa 1621 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto 107:4f6c30876dfa 1622 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto 107:4f6c30876dfa 1623
Kojto 107:4f6c30876dfa 1624 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto 107:4f6c30876dfa 1625 #define __HAL_RCC_AXI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_AXILPEN))
Kojto 107:4f6c30876dfa 1626 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto 107:4f6c30876dfa 1627 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto 107:4f6c30876dfa 1628 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 107:4f6c30876dfa 1629 #define __HAL_RCC_DTCM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DTCMLPEN))
Kojto 107:4f6c30876dfa 1630 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 107:4f6c30876dfa 1631 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto 107:4f6c30876dfa 1632 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto 107:4f6c30876dfa 1633 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 107:4f6c30876dfa 1634 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 107:4f6c30876dfa 1635 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 107:4f6c30876dfa 1636 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto 107:4f6c30876dfa 1637 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 107:4f6c30876dfa 1638 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 107:4f6c30876dfa 1639 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 107:4f6c30876dfa 1640 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 107:4f6c30876dfa 1641 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto 107:4f6c30876dfa 1642 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto 107:4f6c30876dfa 1643 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto 107:4f6c30876dfa 1644 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto 107:4f6c30876dfa 1645 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 107:4f6c30876dfa 1646 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto 107:4f6c30876dfa 1647 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto 107:4f6c30876dfa 1648 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto 107:4f6c30876dfa 1649
Kojto 107:4f6c30876dfa 1650 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1651 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1652 * power consumption.
Kojto 107:4f6c30876dfa 1653 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1654 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1655 */
Kojto 107:4f6c30876dfa 1656 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Kojto 107:4f6c30876dfa 1657 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto 107:4f6c30876dfa 1658
Kojto 107:4f6c30876dfa 1659 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
Kojto 107:4f6c30876dfa 1660 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto 107:4f6c30876dfa 1661
Kojto 107:4f6c30876dfa 1662 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto 107:4f6c30876dfa 1663 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
Kojto 107:4f6c30876dfa 1664
Kojto 107:4f6c30876dfa 1665 #if defined(STM32F756xx)
Kojto 107:4f6c30876dfa 1666 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
Kojto 107:4f6c30876dfa 1667 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
Kojto 107:4f6c30876dfa 1668
Kojto 107:4f6c30876dfa 1669 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto 107:4f6c30876dfa 1670 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto 107:4f6c30876dfa 1671 #endif /* STM32F756xx */
Kojto 107:4f6c30876dfa 1672
Kojto 107:4f6c30876dfa 1673 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1674 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1675 * power consumption.
Kojto 107:4f6c30876dfa 1676 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1677 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1678 */
Kojto 107:4f6c30876dfa 1679 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
Kojto 107:4f6c30876dfa 1680 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto 107:4f6c30876dfa 1681
Kojto 107:4f6c30876dfa 1682 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
Kojto 107:4f6c30876dfa 1683 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto 107:4f6c30876dfa 1684
Kojto 107:4f6c30876dfa 1685 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1686 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1687 * power consumption.
Kojto 107:4f6c30876dfa 1688 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1689 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1690 */
Kojto 107:4f6c30876dfa 1691 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
Kojto 107:4f6c30876dfa 1692 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
Kojto 107:4f6c30876dfa 1693 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
Kojto 107:4f6c30876dfa 1694 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 107:4f6c30876dfa 1695 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
Kojto 107:4f6c30876dfa 1696 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
Kojto 107:4f6c30876dfa 1697 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
Kojto 107:4f6c30876dfa 1698 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
Kojto 107:4f6c30876dfa 1699 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
Kojto 107:4f6c30876dfa 1700 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_LPTIM1LPEN))
Kojto 107:4f6c30876dfa 1701 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 107:4f6c30876dfa 1702 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
Kojto 107:4f6c30876dfa 1703 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto 107:4f6c30876dfa 1704 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 107:4f6c30876dfa 1705 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
Kojto 107:4f6c30876dfa 1706 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
Kojto 107:4f6c30876dfa 1707 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
Kojto 107:4f6c30876dfa 1708 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 107:4f6c30876dfa 1709 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 107:4f6c30876dfa 1710 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
Kojto 107:4f6c30876dfa 1711 #define __HAL_RCC_I2C4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C4LPEN))
Kojto 107:4f6c30876dfa 1712 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
Kojto 107:4f6c30876dfa 1713 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
Kojto 107:4f6c30876dfa 1714 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
Kojto 107:4f6c30876dfa 1715 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
Kojto 107:4f6c30876dfa 1716 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
Kojto 107:4f6c30876dfa 1717 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
Kojto 107:4f6c30876dfa 1718
Kojto 107:4f6c30876dfa 1719 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto 107:4f6c30876dfa 1720 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto 107:4f6c30876dfa 1721 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto 107:4f6c30876dfa 1722 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 107:4f6c30876dfa 1723 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto 107:4f6c30876dfa 1724 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto 107:4f6c30876dfa 1725 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto 107:4f6c30876dfa 1726 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto 107:4f6c30876dfa 1727 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto 107:4f6c30876dfa 1728 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LPTIM1LPEN))
Kojto 107:4f6c30876dfa 1729 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 107:4f6c30876dfa 1730 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto 107:4f6c30876dfa 1731 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE()(RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto 107:4f6c30876dfa 1732 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 107:4f6c30876dfa 1733 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto 107:4f6c30876dfa 1734 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto 107:4f6c30876dfa 1735 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto 107:4f6c30876dfa 1736 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 107:4f6c30876dfa 1737 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 107:4f6c30876dfa 1738 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto 107:4f6c30876dfa 1739 #define __HAL_RCC_I2C4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C4LPEN))
Kojto 107:4f6c30876dfa 1740 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto 107:4f6c30876dfa 1741 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto 107:4f6c30876dfa 1742 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto 107:4f6c30876dfa 1743 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto 107:4f6c30876dfa 1744 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto 107:4f6c30876dfa 1745 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto 107:4f6c30876dfa 1746
Kojto 107:4f6c30876dfa 1747 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1748 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1749 * power consumption.
Kojto 107:4f6c30876dfa 1750 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1751 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1752 */
Kojto 107:4f6c30876dfa 1753 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 107:4f6c30876dfa 1754 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
Kojto 107:4f6c30876dfa 1755 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 107:4f6c30876dfa 1756 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 107:4f6c30876dfa 1757 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 107:4f6c30876dfa 1758 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
Kojto 107:4f6c30876dfa 1759 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
Kojto 107:4f6c30876dfa 1760 #define __HAL_RCC_SDMMC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDMMC1LPEN))
Kojto 107:4f6c30876dfa 1761 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 107:4f6c30876dfa 1762 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
Kojto 107:4f6c30876dfa 1763 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 107:4f6c30876dfa 1764 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
Kojto 107:4f6c30876dfa 1765 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
Kojto 107:4f6c30876dfa 1766 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
Kojto 107:4f6c30876dfa 1767 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
Kojto 107:4f6c30876dfa 1768 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
Kojto 107:4f6c30876dfa 1769 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
Kojto 107:4f6c30876dfa 1770 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 1771 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
Kojto 107:4f6c30876dfa 1772 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 1773
Kojto 107:4f6c30876dfa 1774 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 107:4f6c30876dfa 1775 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto 107:4f6c30876dfa 1776 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 107:4f6c30876dfa 1777 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 107:4f6c30876dfa 1778 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 107:4f6c30876dfa 1779 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto 107:4f6c30876dfa 1780 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto 107:4f6c30876dfa 1781 #define __HAL_RCC_SDMMC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDMMC1LPEN))
Kojto 107:4f6c30876dfa 1782 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 107:4f6c30876dfa 1783 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto 107:4f6c30876dfa 1784 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 107:4f6c30876dfa 1785 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto 107:4f6c30876dfa 1786 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 107:4f6c30876dfa 1787 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto 107:4f6c30876dfa 1788 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto 107:4f6c30876dfa 1789 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto 107:4f6c30876dfa 1790 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto 107:4f6c30876dfa 1791 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 1792 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto 107:4f6c30876dfa 1793 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 1794 /**
Kojto 107:4f6c30876dfa 1795 * @}
Kojto 107:4f6c30876dfa 1796 */
Kojto 107:4f6c30876dfa 1797
Kojto 107:4f6c30876dfa 1798 /** @defgroup RCC_Clock_Sleep_Enable_Disable_Status AHB/APB Peripheral Clock Sleep Enable Disable Status
Kojto 107:4f6c30876dfa 1799 * @brief Get the enable or disable status of the AHB/APB peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1800 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1801 * power consumption.
Kojto 107:4f6c30876dfa 1802 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1803 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1804 * @{
Kojto 107:4f6c30876dfa 1805 */
Kojto 107:4f6c30876dfa 1806
Kojto 107:4f6c30876dfa 1807 /** @brief Get the enable or disable status of the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1808 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1809 * power consumption.
Kojto 107:4f6c30876dfa 1810 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1811 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1812 */
Kojto 107:4f6c30876dfa 1813 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1814 #define __HAL_RCC_AXI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) != RESET)
Kojto 107:4f6c30876dfa 1815 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1816 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1817 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1818 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1819 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1820 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1821 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1822 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1823 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1824 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1825 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1826 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) != RESET)
Kojto 107:4f6c30876dfa 1827 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) != RESET)
Kojto 107:4f6c30876dfa 1828 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1829 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1830 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1831 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) != RESET)
Kojto 107:4f6c30876dfa 1832 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1833 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1834 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1835 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) != RESET)
Kojto 107:4f6c30876dfa 1836 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1837 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_ENABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1838
Kojto 107:4f6c30876dfa 1839 #define __HAL_RCC_FLITF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_FLITFLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1840 #define __HAL_RCC_AXI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_AXILPEN)) == RESET)
Kojto 107:4f6c30876dfa 1841 #define __HAL_RCC_SRAM1_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1842 #define __HAL_RCC_SRAM2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_SRAM2LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1843 #define __HAL_RCC_BKPSRAM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_BKPSRAMLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1844 #define __HAL_RCC_DTCM_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DTCMLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1845 #define __HAL_RCC_DMA2_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1846 #define __HAL_RCC_DMA2D_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_DMA2DLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1847 #define __HAL_RCC_ETHMAC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1848 #define __HAL_RCC_ETHMACTX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACTXLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1849 #define __HAL_RCC_ETHMACRX_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACRXLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1850 #define __HAL_RCC_ETHMACPTP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_ETHMACPTPLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1851 #define __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1852 #define __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_OTGHSULPILPEN)) == RESET)
Kojto 107:4f6c30876dfa 1853 #define __HAL_RCC_GPIOA_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOALPEN)) == RESET)
Kojto 107:4f6c30876dfa 1854 #define __HAL_RCC_GPIOB_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOBLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1855 #define __HAL_RCC_GPIOC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOCLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1856 #define __HAL_RCC_GPIOD_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIODLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1857 #define __HAL_RCC_GPIOE_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOELPEN)) == RESET)
Kojto 107:4f6c30876dfa 1858 #define __HAL_RCC_GPIOF_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOFLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1859 #define __HAL_RCC_GPIOG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOGLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1860 #define __HAL_RCC_GPIOH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOHLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1861 #define __HAL_RCC_GPIOI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOILPEN)) == RESET)
Kojto 107:4f6c30876dfa 1862 #define __HAL_RCC_GPIOJ_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOJLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1863 #define __HAL_RCC_GPIOK_IS_CLK_SLEEP_DISABLED() ((RCC->AHB1LPENR & (RCC_AHB1LPENR_GPIOKLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1864
Kojto 107:4f6c30876dfa 1865 /** @brief Get the enable or disable status of the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1866 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1867 * power consumption.
Kojto 107:4f6c30876dfa 1868 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1869 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1870 */
Kojto 107:4f6c30876dfa 1871 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) != RESET)
Kojto 107:4f6c30876dfa 1872 #define __HAL_RCC_DCMI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_DCMILPEN)) == RESET)
Kojto 107:4f6c30876dfa 1873
Kojto 107:4f6c30876dfa 1874 #define __HAL_RCC_RNG_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1875 #define __HAL_RCC_RNG_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_RNGLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1876
Kojto 107:4f6c30876dfa 1877 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1878 #define __HAL_RCC_USB_OTG_FS_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_OTGFSLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1879
Kojto 107:4f6c30876dfa 1880 #if defined(STM32F756xx)
Kojto 107:4f6c30876dfa 1881 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1882 #define __HAL_RCC_HASH_IS_CLK_SLEEP_ENABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1883
Kojto 107:4f6c30876dfa 1884 #define __HAL_RCC_CRYP_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_CRYPLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1885 #define __HAL_RCC_HASH_IS_CLK_SLEEP_DISABLED() ((RCC->AHB2LPENR & (RCC_AHB2LPENR_HASHLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1886 #endif /* STM32F756xx */
Kojto 107:4f6c30876dfa 1887
Kojto 107:4f6c30876dfa 1888 /** @brief Get the enable or disable status of the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1889 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1890 * power consumption.
Kojto 107:4f6c30876dfa 1891 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1892 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1893 */
Kojto 107:4f6c30876dfa 1894 #define __HAL_RCC_FMC_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1895 #define __HAL_RCC_FMC_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_FMCLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1896
Kojto 107:4f6c30876dfa 1897 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) != RESET)
Kojto 107:4f6c30876dfa 1898 #define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED() ((RCC->AHB3LPENR & (RCC_AHB3LPENR_QSPILPEN)) == RESET)
Kojto 107:4f6c30876dfa 1899
Kojto 107:4f6c30876dfa 1900 /** @brief Get the enable or disable status of the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1901 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1902 * power consumption.
Kojto 107:4f6c30876dfa 1903 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1904 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1905 */
Kojto 107:4f6c30876dfa 1906 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1907 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1908 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1909 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1910 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1911 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1912 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1913 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1914 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1915 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1916 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1917 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1918 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1919 #define __HAL_RCC_USART2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1920 #define __HAL_RCC_USART3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1921 #define __HAL_RCC_UART4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1922 #define __HAL_RCC_UART5_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1923 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1924 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1925 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1926 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1927 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1928 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1929 #define __HAL_RCC_CEC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1930 #define __HAL_RCC_DAC_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1931 #define __HAL_RCC_UART7_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1932 #define __HAL_RCC_UART8_IS_CLK_SLEEP_ENABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1933
Kojto 107:4f6c30876dfa 1934 #define __HAL_RCC_TIM2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM2LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1935 #define __HAL_RCC_TIM3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM3LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1936 #define __HAL_RCC_TIM4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM4LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1937 #define __HAL_RCC_TIM5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM5LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1938 #define __HAL_RCC_TIM6_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM6LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1939 #define __HAL_RCC_TIM7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM7LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1940 #define __HAL_RCC_TIM12_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM12LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1941 #define __HAL_RCC_TIM13_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM13LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1942 #define __HAL_RCC_TIM14_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_TIM14LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1943 #define __HAL_RCC_LPTIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_LPTIM1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1944 #define __HAL_RCC_SPI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI2LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1945 #define __HAL_RCC_SPI3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_SPI3LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1946 #define __HAL_RCC_SPDIFRX_IS_CLK_SLEEP_DISABLED()((RCC->APB1LPENR & (RCC_APB1LPENR_SPDIFRXLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1947 #define __HAL_RCC_USART2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART2LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1948 #define __HAL_RCC_USART3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_USART3LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1949 #define __HAL_RCC_UART4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART4LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1950 #define __HAL_RCC_UART5_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART5LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1951 #define __HAL_RCC_I2C1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1952 #define __HAL_RCC_I2C2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C2LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1953 #define __HAL_RCC_I2C3_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C3LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1954 #define __HAL_RCC_I2C4_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_I2C4LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1955 #define __HAL_RCC_CAN1_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1956 #define __HAL_RCC_CAN2_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CAN2LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1957 #define __HAL_RCC_CEC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_CECLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1958 #define __HAL_RCC_DAC_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_DACLPEN)) == RESET)
Kojto 107:4f6c30876dfa 1959 #define __HAL_RCC_UART7_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART7LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1960 #define __HAL_RCC_UART8_IS_CLK_SLEEP_DISABLED() ((RCC->APB1LPENR & (RCC_APB1LPENR_UART8LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1961
Kojto 107:4f6c30876dfa 1962 /** @brief Get the enable or disable status of the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 107:4f6c30876dfa 1963 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 107:4f6c30876dfa 1964 * power consumption.
Kojto 107:4f6c30876dfa 1965 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 107:4f6c30876dfa 1966 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 107:4f6c30876dfa 1967 */
Kojto 107:4f6c30876dfa 1968 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1969 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1970 #define __HAL_RCC_USART1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1971 #define __HAL_RCC_USART6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1972 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1973 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1974 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1975 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1976 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1977 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1978 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1979 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1980 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1981 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1982 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1983 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1984 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) != RESET)
Kojto 107:4f6c30876dfa 1985 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 1986 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_ENABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) != RESET)
Kojto 107:4f6c30876dfa 1987 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 1988
Kojto 107:4f6c30876dfa 1989 #define __HAL_RCC_TIM1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1990 #define __HAL_RCC_TIM8_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM8LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1991 #define __HAL_RCC_USART1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1992 #define __HAL_RCC_USART6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_USART6LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1993 #define __HAL_RCC_ADC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1994 #define __HAL_RCC_ADC2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC2LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1995 #define __HAL_RCC_ADC3_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_ADC3LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1996 #define __HAL_RCC_SDMMC1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SDMMC1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1997 #define __HAL_RCC_SPI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1998 #define __HAL_RCC_SPI4_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI4LPEN)) == RESET)
Kojto 107:4f6c30876dfa 1999 #define __HAL_RCC_TIM9_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM9LPEN)) == RESET)
Kojto 107:4f6c30876dfa 2000 #define __HAL_RCC_TIM10_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM10LPEN)) == RESET)
Kojto 107:4f6c30876dfa 2001 #define __HAL_RCC_TIM11_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_TIM11LPEN)) == RESET)
Kojto 107:4f6c30876dfa 2002 #define __HAL_RCC_SPI5_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI5LPEN)) == RESET)
Kojto 107:4f6c30876dfa 2003 #define __HAL_RCC_SPI6_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SPI6LPEN)) == RESET)
Kojto 107:4f6c30876dfa 2004 #define __HAL_RCC_SAI1_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI1LPEN)) == RESET)
Kojto 107:4f6c30876dfa 2005 #define __HAL_RCC_SAI2_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_SAI2LPEN)) == RESET)
Kojto 107:4f6c30876dfa 2006 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 2007 #define __HAL_RCC_LTDC_IS_CLK_SLEEP_DISABLED() ((RCC->APB2LPENR & (RCC_APB2LPENR_LTDCLPEN)) == RESET)
Kojto 107:4f6c30876dfa 2008 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 2009 /**
Kojto 107:4f6c30876dfa 2010 * @}
Kojto 107:4f6c30876dfa 2011 */
Kojto 107:4f6c30876dfa 2012
Kojto 107:4f6c30876dfa 2013 /*---------------------------------------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 2014
Kojto 107:4f6c30876dfa 2015 /** @brief Macro to configure the Timers clocks prescalers
Kojto 107:4f6c30876dfa 2016 * @param __PRESC__ : specifies the Timers clocks prescalers selection
Kojto 107:4f6c30876dfa 2017 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2018 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
Kojto 107:4f6c30876dfa 2019 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
Kojto 107:4f6c30876dfa 2020 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
Kojto 107:4f6c30876dfa 2021 * division by 4 or more.
Kojto 107:4f6c30876dfa 2022 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
Kojto 107:4f6c30876dfa 2023 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
Kojto 107:4f6c30876dfa 2024 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
Kojto 107:4f6c30876dfa 2025 * to division by 8 or more.
Kojto 107:4f6c30876dfa 2026 */
Kojto 107:4f6c30876dfa 2027 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) do {RCC->DCKCFGR1 &= ~(RCC_DCKCFGR1_TIMPRE);\
Kojto 107:4f6c30876dfa 2028 RCC->DCKCFGR1 |= (__PRESC__);\
Kojto 107:4f6c30876dfa 2029 }while(0)
Kojto 107:4f6c30876dfa 2030
Kojto 107:4f6c30876dfa 2031 /** @brief Macros to Enable or Disable the PLLISAI.
Kojto 107:4f6c30876dfa 2032 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto 107:4f6c30876dfa 2033 */
Kojto 107:4f6c30876dfa 2034 #define __HAL_RCC_PLLSAI_ENABLE() (RCC->CR |= (RCC_CR_PLLSAION))
Kojto 107:4f6c30876dfa 2035 #define __HAL_RCC_PLLSAI_DISABLE() (RCC->CR &= ~(RCC_CR_PLLSAION))
Kojto 107:4f6c30876dfa 2036
Kojto 107:4f6c30876dfa 2037 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto 107:4f6c30876dfa 2038 * @note This function must be used only when the PLLSAI is disabled.
Kojto 107:4f6c30876dfa 2039 * @note PLLSAI clock source is common with the main PLL (configured in
Kojto 107:4f6c30876dfa 2040 * RCC_PLLConfig function )
Kojto 107:4f6c30876dfa 2041 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto 107:4f6c30876dfa 2042 * This parameter must be a number between Min_Data = 49 and Max_Data = 432.
Kojto 107:4f6c30876dfa 2043 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto 107:4f6c30876dfa 2044 * output frequency is between Min_Data = 49 and Max_Data = 432 MHz.
Kojto 107:4f6c30876dfa 2045 * @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto 107:4f6c30876dfa 2046 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 107:4f6c30876dfa 2047 * @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto 107:4f6c30876dfa 2048 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 107:4f6c30876dfa 2049 * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
Kojto 107:4f6c30876dfa 2050 * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider .
Kojto 107:4f6c30876dfa 2051 */
Kojto 107:4f6c30876dfa 2052 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) (RCC->PLLSAICFGR = ((__PLLSAIN__) << 6) | ((__PLLSAIP__) << 16) | ((__PLLSAIQ__) << 24) | ((__PLLSAIR__) << 28))
Kojto 107:4f6c30876dfa 2053
Kojto 107:4f6c30876dfa 2054 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
Kojto 107:4f6c30876dfa 2055 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 107:4f6c30876dfa 2056 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 107:4f6c30876dfa 2057 * HAL_RCC_ClockConfig() API)
Kojto 107:4f6c30876dfa 2058 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 107:4f6c30876dfa 2059 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 107:4f6c30876dfa 2060 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 107:4f6c30876dfa 2061 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 107:4f6c30876dfa 2062 * @param __PLLI2SQ__: specifies the division factor for SAI clock.
Kojto 107:4f6c30876dfa 2063 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 107:4f6c30876dfa 2064 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 107:4f6c30876dfa 2065 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 107:4f6c30876dfa 2066 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 107:4f6c30876dfa 2067 * on the I2S clock frequency.
Kojto 107:4f6c30876dfa 2068 * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
Kojto 107:4f6c30876dfa 2069 * This parameter can be a number between 0 and 3 for respective values 2, 4, 6 and 8
Kojto 107:4f6c30876dfa 2070 */
Kojto 107:4f6c30876dfa 2071 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) | ((__PLLI2SP__) << 16) | ((__PLLI2SQ__) << 24) | ((__PLLI2SR__) << 28))
Kojto 107:4f6c30876dfa 2072
Kojto 107:4f6c30876dfa 2073 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto 107:4f6c30876dfa 2074 * @note This function must be called before enabling the PLLI2S.
Kojto 107:4f6c30876dfa 2075 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
Kojto 107:4f6c30876dfa 2076 * This parameter must be a number between 1 and 32.
Kojto 107:4f6c30876dfa 2077 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto 107:4f6c30876dfa 2078 */
Kojto 107:4f6c30876dfa 2079 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto 107:4f6c30876dfa 2080
Kojto 107:4f6c30876dfa 2081 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto 107:4f6c30876dfa 2082 * @note This function must be called before enabling the PLLSAI.
Kojto 107:4f6c30876dfa 2083 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto 107:4f6c30876dfa 2084 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto 107:4f6c30876dfa 2085 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto 107:4f6c30876dfa 2086 */
Kojto 107:4f6c30876dfa 2087 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto 107:4f6c30876dfa 2088
Kojto 107:4f6c30876dfa 2089 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto 107:4f6c30876dfa 2090 *
Kojto 107:4f6c30876dfa 2091 * @note This function must be called before enabling the PLLSAI.
Kojto 107:4f6c30876dfa 2092 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto 107:4f6c30876dfa 2093 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
Kojto 107:4f6c30876dfa 2094 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto 107:4f6c30876dfa 2095 */
Kojto 107:4f6c30876dfa 2096 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__)\
Kojto 107:4f6c30876dfa 2097 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, (uint32_t)(__PLLSAIDivR__))
Kojto 107:4f6c30876dfa 2098
Kojto 107:4f6c30876dfa 2099 /** @brief Macro to configure SAI1 clock source selection.
Kojto 107:4f6c30876dfa 2100 * @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto 107:4f6c30876dfa 2101 * the SAI clock.
Kojto 107:4f6c30876dfa 2102 * @param __SOURCE__: specifies the SAI1 clock source.
Kojto 107:4f6c30876dfa 2103 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2104 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 107:4f6c30876dfa 2105 * as SAI1 clock.
Kojto 107:4f6c30876dfa 2106 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 107:4f6c30876dfa 2107 * as SAI1 clock.
Kojto 107:4f6c30876dfa 2108 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto 107:4f6c30876dfa 2109 * used as SAI1 clock.
Kojto 107:4f6c30876dfa 2110 */
Kojto 107:4f6c30876dfa 2111 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__)\
Kojto 107:4f6c30876dfa 2112 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL, (uint32_t)(__SOURCE__))
Kojto 107:4f6c30876dfa 2113
Kojto 107:4f6c30876dfa 2114 /** @brief Macro to get the SAI1 clock source.
Kojto 107:4f6c30876dfa 2115 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2116 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 107:4f6c30876dfa 2117 * as SAI1 clock.
Kojto 107:4f6c30876dfa 2118 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 107:4f6c30876dfa 2119 * as SAI1 clock.
Kojto 107:4f6c30876dfa 2120 * @arg RCC_SAI1CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto 107:4f6c30876dfa 2121 * used as SAI1 clock.
Kojto 107:4f6c30876dfa 2122 */
Kojto 107:4f6c30876dfa 2123 #define __HAL_RCC_GET_SAI1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI1SEL)))
Kojto 107:4f6c30876dfa 2124
Kojto 107:4f6c30876dfa 2125
Kojto 107:4f6c30876dfa 2126 /** @brief Macro to configure SAI2 clock source selection.
Kojto 107:4f6c30876dfa 2127 * @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto 107:4f6c30876dfa 2128 * the SAI clock.
Kojto 107:4f6c30876dfa 2129 * @param __SOURCE__: specifies the SAI2 clock source.
Kojto 107:4f6c30876dfa 2130 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2131 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 107:4f6c30876dfa 2132 * as SAI2 clock.
Kojto 107:4f6c30876dfa 2133 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 107:4f6c30876dfa 2134 * as SAI2 clock.
Kojto 107:4f6c30876dfa 2135 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto 107:4f6c30876dfa 2136 * used as SAI2 clock.
Kojto 107:4f6c30876dfa 2137 */
Kojto 107:4f6c30876dfa 2138 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__)\
Kojto 107:4f6c30876dfa 2139 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL, (uint32_t)(__SOURCE__))
Kojto 107:4f6c30876dfa 2140
Kojto 107:4f6c30876dfa 2141
Kojto 107:4f6c30876dfa 2142 /** @brief Macro to get the SAI2 clock source.
Kojto 107:4f6c30876dfa 2143 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2144 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 107:4f6c30876dfa 2145 * as SAI2 clock.
Kojto 107:4f6c30876dfa 2146 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 107:4f6c30876dfa 2147 * as SAI2 clock.
Kojto 107:4f6c30876dfa 2148 * @arg RCC_SAI2CLKSOURCE_PIN: External clock mapped on the I2S_CKIN pin
Kojto 107:4f6c30876dfa 2149 * used as SAI2 clock.
Kojto 107:4f6c30876dfa 2150 */
Kojto 107:4f6c30876dfa 2151 #define __HAL_RCC_GET_SAI2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_SAI2SEL)))
Kojto 107:4f6c30876dfa 2152
Kojto 107:4f6c30876dfa 2153
Kojto 107:4f6c30876dfa 2154 /** @brief Enable PLLSAI_RDY interrupt.
Kojto 107:4f6c30876dfa 2155 */
Kojto 107:4f6c30876dfa 2156 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
Kojto 107:4f6c30876dfa 2157
Kojto 107:4f6c30876dfa 2158 /** @brief Disable PLLSAI_RDY interrupt.
Kojto 107:4f6c30876dfa 2159 */
Kojto 107:4f6c30876dfa 2160 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
Kojto 107:4f6c30876dfa 2161
Kojto 107:4f6c30876dfa 2162 /** @brief Clear the PLLSAI RDY interrupt pending bits.
Kojto 107:4f6c30876dfa 2163 */
Kojto 107:4f6c30876dfa 2164 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
Kojto 107:4f6c30876dfa 2165
Kojto 107:4f6c30876dfa 2166 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
Kojto 107:4f6c30876dfa 2167 * @retval The new state (TRUE or FALSE).
Kojto 107:4f6c30876dfa 2168 */
Kojto 107:4f6c30876dfa 2169 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
Kojto 107:4f6c30876dfa 2170
Kojto 107:4f6c30876dfa 2171 /** @brief Check PLLSAI RDY flag is set or not.
Kojto 107:4f6c30876dfa 2172 * @retval The new state (TRUE or FALSE).
Kojto 107:4f6c30876dfa 2173 */
Kojto 107:4f6c30876dfa 2174 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
Kojto 107:4f6c30876dfa 2175
Kojto 107:4f6c30876dfa 2176 /** @brief Macro to Get I2S clock source selection.
Kojto 107:4f6c30876dfa 2177 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2178 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto 107:4f6c30876dfa 2179 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S clock source
Kojto 107:4f6c30876dfa 2180 */
Kojto 107:4f6c30876dfa 2181 #define __HAL_RCC_GET_I2SCLKSOURCE() (READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC))
Kojto 107:4f6c30876dfa 2182
Kojto 107:4f6c30876dfa 2183 /** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto 107:4f6c30876dfa 2184 *
Kojto 107:4f6c30876dfa 2185 * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
Kojto 107:4f6c30876dfa 2186 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2187 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto 107:4f6c30876dfa 2188 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 107:4f6c30876dfa 2189 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 107:4f6c30876dfa 2190 */
Kojto 107:4f6c30876dfa 2191 #define __HAL_RCC_I2C1_CONFIG(__I2C1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2192 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL, (uint32_t)(__I2C1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2193
Kojto 107:4f6c30876dfa 2194 /** @brief Macro to get the I2C1 clock source.
Kojto 107:4f6c30876dfa 2195 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2196 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto 107:4f6c30876dfa 2197 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 107:4f6c30876dfa 2198 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 107:4f6c30876dfa 2199 */
Kojto 107:4f6c30876dfa 2200 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C1SEL)))
Kojto 107:4f6c30876dfa 2201
Kojto 107:4f6c30876dfa 2202 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 107:4f6c30876dfa 2203 *
Kojto 107:4f6c30876dfa 2204 * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
Kojto 107:4f6c30876dfa 2205 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2206 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
Kojto 107:4f6c30876dfa 2207 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 107:4f6c30876dfa 2208 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 107:4f6c30876dfa 2209 */
Kojto 107:4f6c30876dfa 2210 #define __HAL_RCC_I2C2_CONFIG(__I2C2_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2211 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL, (uint32_t)(__I2C2_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2212
Kojto 107:4f6c30876dfa 2213 /** @brief Macro to get the I2C2 clock source.
Kojto 107:4f6c30876dfa 2214 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2215 * @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
Kojto 107:4f6c30876dfa 2216 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 107:4f6c30876dfa 2217 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 107:4f6c30876dfa 2218 */
Kojto 107:4f6c30876dfa 2219 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C2SEL)))
Kojto 107:4f6c30876dfa 2220
Kojto 107:4f6c30876dfa 2221 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto 107:4f6c30876dfa 2222 *
Kojto 107:4f6c30876dfa 2223 * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
Kojto 107:4f6c30876dfa 2224 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2225 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto 107:4f6c30876dfa 2226 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 107:4f6c30876dfa 2227 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 107:4f6c30876dfa 2228 */
Kojto 107:4f6c30876dfa 2229 #define __HAL_RCC_I2C3_CONFIG(__I2C3_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2230 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL, (uint32_t)(__I2C3_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2231
Kojto 107:4f6c30876dfa 2232 /** @brief macro to get the I2C3 clock source.
Kojto 107:4f6c30876dfa 2233 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2234 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto 107:4f6c30876dfa 2235 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 107:4f6c30876dfa 2236 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 107:4f6c30876dfa 2237 */
Kojto 107:4f6c30876dfa 2238 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C3SEL)))
Kojto 107:4f6c30876dfa 2239
Kojto 107:4f6c30876dfa 2240 /** @brief Macro to configure the I2C4 clock (I2C4CLK).
Kojto 107:4f6c30876dfa 2241 *
Kojto 107:4f6c30876dfa 2242 * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
Kojto 107:4f6c30876dfa 2243 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2244 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
Kojto 107:4f6c30876dfa 2245 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
Kojto 107:4f6c30876dfa 2246 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
Kojto 107:4f6c30876dfa 2247 */
Kojto 107:4f6c30876dfa 2248 #define __HAL_RCC_I2C4_CONFIG(__I2C4_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2249 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL, (uint32_t)(__I2C4_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2250
Kojto 107:4f6c30876dfa 2251 /** @brief macro to get the I2C4 clock source.
Kojto 107:4f6c30876dfa 2252 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2253 * @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
Kojto 107:4f6c30876dfa 2254 * @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
Kojto 107:4f6c30876dfa 2255 * @arg RCC_I2C4CLKSOURCE_SYSCLK: System Clock selected as I2C4 clock
Kojto 107:4f6c30876dfa 2256 */
Kojto 107:4f6c30876dfa 2257 #define __HAL_RCC_GET_I2C4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_I2C4SEL)))
Kojto 107:4f6c30876dfa 2258
Kojto 107:4f6c30876dfa 2259 /** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto 107:4f6c30876dfa 2260 *
Kojto 107:4f6c30876dfa 2261 * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
Kojto 107:4f6c30876dfa 2262 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2263 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto 107:4f6c30876dfa 2264 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 107:4f6c30876dfa 2265 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 107:4f6c30876dfa 2266 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 107:4f6c30876dfa 2267 */
Kojto 107:4f6c30876dfa 2268 #define __HAL_RCC_USART1_CONFIG(__USART1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2269 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL, (uint32_t)(__USART1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2270
Kojto 107:4f6c30876dfa 2271 /** @brief macro to get the USART1 clock source.
Kojto 107:4f6c30876dfa 2272 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2273 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto 107:4f6c30876dfa 2274 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 107:4f6c30876dfa 2275 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 107:4f6c30876dfa 2276 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 107:4f6c30876dfa 2277 */
Kojto 107:4f6c30876dfa 2278 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART1SEL)))
Kojto 107:4f6c30876dfa 2279
Kojto 107:4f6c30876dfa 2280 /** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto 107:4f6c30876dfa 2281 *
Kojto 107:4f6c30876dfa 2282 * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
Kojto 107:4f6c30876dfa 2283 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2284 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 107:4f6c30876dfa 2285 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 107:4f6c30876dfa 2286 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 107:4f6c30876dfa 2287 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 107:4f6c30876dfa 2288 */
Kojto 107:4f6c30876dfa 2289 #define __HAL_RCC_USART2_CONFIG(__USART2_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2290 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL, (uint32_t)(__USART2_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2291
Kojto 107:4f6c30876dfa 2292 /** @brief macro to get the USART2 clock source.
Kojto 107:4f6c30876dfa 2293 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2294 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 107:4f6c30876dfa 2295 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 107:4f6c30876dfa 2296 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 107:4f6c30876dfa 2297 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 107:4f6c30876dfa 2298 */
Kojto 107:4f6c30876dfa 2299 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART2SEL)))
Kojto 107:4f6c30876dfa 2300
Kojto 107:4f6c30876dfa 2301 /** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto 107:4f6c30876dfa 2302 *
Kojto 107:4f6c30876dfa 2303 * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
Kojto 107:4f6c30876dfa 2304 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2305 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 107:4f6c30876dfa 2306 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 107:4f6c30876dfa 2307 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 107:4f6c30876dfa 2308 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 107:4f6c30876dfa 2309 */
Kojto 107:4f6c30876dfa 2310 #define __HAL_RCC_USART3_CONFIG(__USART3_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2311 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL, (uint32_t)(__USART3_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2312
Kojto 107:4f6c30876dfa 2313 /** @brief macro to get the USART3 clock source.
Kojto 107:4f6c30876dfa 2314 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2315 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 107:4f6c30876dfa 2316 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 107:4f6c30876dfa 2317 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 107:4f6c30876dfa 2318 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 107:4f6c30876dfa 2319 */
Kojto 107:4f6c30876dfa 2320 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART3SEL)))
Kojto 107:4f6c30876dfa 2321
Kojto 107:4f6c30876dfa 2322 /** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto 107:4f6c30876dfa 2323 *
Kojto 107:4f6c30876dfa 2324 * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
Kojto 107:4f6c30876dfa 2325 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2326 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto 107:4f6c30876dfa 2327 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto 107:4f6c30876dfa 2328 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto 107:4f6c30876dfa 2329 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto 107:4f6c30876dfa 2330 */
Kojto 107:4f6c30876dfa 2331 #define __HAL_RCC_UART4_CONFIG(__UART4_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2332 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL, (uint32_t)(__UART4_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2333
Kojto 107:4f6c30876dfa 2334 /** @brief macro to get the UART4 clock source.
Kojto 107:4f6c30876dfa 2335 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2336 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto 107:4f6c30876dfa 2337 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto 107:4f6c30876dfa 2338 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto 107:4f6c30876dfa 2339 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto 107:4f6c30876dfa 2340 */
Kojto 107:4f6c30876dfa 2341 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART4SEL)))
Kojto 107:4f6c30876dfa 2342
Kojto 107:4f6c30876dfa 2343 /** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto 107:4f6c30876dfa 2344 *
Kojto 107:4f6c30876dfa 2345 * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
Kojto 107:4f6c30876dfa 2346 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2347 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto 107:4f6c30876dfa 2348 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto 107:4f6c30876dfa 2349 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto 107:4f6c30876dfa 2350 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto 107:4f6c30876dfa 2351 */
Kojto 107:4f6c30876dfa 2352 #define __HAL_RCC_UART5_CONFIG(__UART5_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2353 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL, (uint32_t)(__UART5_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2354
Kojto 107:4f6c30876dfa 2355 /** @brief macro to get the UART5 clock source.
Kojto 107:4f6c30876dfa 2356 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2357 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto 107:4f6c30876dfa 2358 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto 107:4f6c30876dfa 2359 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto 107:4f6c30876dfa 2360 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto 107:4f6c30876dfa 2361 */
Kojto 107:4f6c30876dfa 2362 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART5SEL)))
Kojto 107:4f6c30876dfa 2363
Kojto 107:4f6c30876dfa 2364 /** @brief Macro to configure the USART6 clock (USART6CLK).
Kojto 107:4f6c30876dfa 2365 *
Kojto 107:4f6c30876dfa 2366 * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
Kojto 107:4f6c30876dfa 2367 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2368 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
Kojto 107:4f6c30876dfa 2369 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
Kojto 107:4f6c30876dfa 2370 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
Kojto 107:4f6c30876dfa 2371 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Kojto 107:4f6c30876dfa 2372 */
Kojto 107:4f6c30876dfa 2373 #define __HAL_RCC_USART6_CONFIG(__USART6_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2374 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL, (uint32_t)(__USART6_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2375
Kojto 107:4f6c30876dfa 2376 /** @brief macro to get the USART6 clock source.
Kojto 107:4f6c30876dfa 2377 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2378 * @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
Kojto 107:4f6c30876dfa 2379 * @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
Kojto 107:4f6c30876dfa 2380 * @arg RCC_USART6CLKSOURCE_SYSCLK: System Clock selected as USART6 clock
Kojto 107:4f6c30876dfa 2381 * @arg RCC_USART6CLKSOURCE_LSE: LSE selected as USART6 clock
Kojto 107:4f6c30876dfa 2382 */
Kojto 107:4f6c30876dfa 2383 #define __HAL_RCC_GET_USART6_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_USART6SEL)))
Kojto 107:4f6c30876dfa 2384
Kojto 107:4f6c30876dfa 2385 /** @brief Macro to configure the UART7 clock (UART7CLK).
Kojto 107:4f6c30876dfa 2386 *
Kojto 107:4f6c30876dfa 2387 * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
Kojto 107:4f6c30876dfa 2388 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2389 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
Kojto 107:4f6c30876dfa 2390 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
Kojto 107:4f6c30876dfa 2391 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
Kojto 107:4f6c30876dfa 2392 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Kojto 107:4f6c30876dfa 2393 */
Kojto 107:4f6c30876dfa 2394 #define __HAL_RCC_UART7_CONFIG(__UART7_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2395 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL, (uint32_t)(__UART7_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2396
Kojto 107:4f6c30876dfa 2397 /** @brief macro to get the UART7 clock source.
Kojto 107:4f6c30876dfa 2398 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2399 * @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
Kojto 107:4f6c30876dfa 2400 * @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
Kojto 107:4f6c30876dfa 2401 * @arg RCC_UART7CLKSOURCE_SYSCLK: System Clock selected as UART7 clock
Kojto 107:4f6c30876dfa 2402 * @arg RCC_UART7CLKSOURCE_LSE: LSE selected as UART7 clock
Kojto 107:4f6c30876dfa 2403 */
Kojto 107:4f6c30876dfa 2404 #define __HAL_RCC_GET_UART7_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART7SEL)))
Kojto 107:4f6c30876dfa 2405
Kojto 107:4f6c30876dfa 2406 /** @brief Macro to configure the UART8 clock (UART8CLK).
Kojto 107:4f6c30876dfa 2407 *
Kojto 107:4f6c30876dfa 2408 * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
Kojto 107:4f6c30876dfa 2409 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2410 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
Kojto 107:4f6c30876dfa 2411 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
Kojto 107:4f6c30876dfa 2412 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
Kojto 107:4f6c30876dfa 2413 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Kojto 107:4f6c30876dfa 2414 */
Kojto 107:4f6c30876dfa 2415 #define __HAL_RCC_UART8_CONFIG(__UART8_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2416 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL, (uint32_t)(__UART8_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2417
Kojto 107:4f6c30876dfa 2418 /** @brief macro to get the UART8 clock source.
Kojto 107:4f6c30876dfa 2419 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2420 * @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
Kojto 107:4f6c30876dfa 2421 * @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
Kojto 107:4f6c30876dfa 2422 * @arg RCC_UART8CLKSOURCE_SYSCLK: System Clock selected as UART8 clock
Kojto 107:4f6c30876dfa 2423 * @arg RCC_UART8CLKSOURCE_LSE: LSE selected as UART8 clock
Kojto 107:4f6c30876dfa 2424 */
Kojto 107:4f6c30876dfa 2425 #define __HAL_RCC_GET_UART8_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_UART8SEL)))
Kojto 107:4f6c30876dfa 2426
Kojto 107:4f6c30876dfa 2427 /** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
Kojto 107:4f6c30876dfa 2428 *
Kojto 107:4f6c30876dfa 2429 * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
Kojto 107:4f6c30876dfa 2430 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2431 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 2432 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 2433 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 2434 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 2435 */
Kojto 107:4f6c30876dfa 2436 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2437 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, (uint32_t)(__LPTIM1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2438
Kojto 107:4f6c30876dfa 2439 /** @brief macro to get the LPTIM1 clock source.
Kojto 107:4f6c30876dfa 2440 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2441 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 2442 * @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 2443 * @arg RCC_LPTIM1CLKSOURCE_LSI: LSI selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 2444 * @arg RCC_LPTIM1CLKSOURCE_LSE: LSE selected as LPTIM1 clock
Kojto 107:4f6c30876dfa 2445 */
Kojto 107:4f6c30876dfa 2446 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL)))
Kojto 107:4f6c30876dfa 2447
Kojto 107:4f6c30876dfa 2448 /** @brief Macro to configure the CEC clock (CECCLK).
Kojto 107:4f6c30876dfa 2449 *
Kojto 107:4f6c30876dfa 2450 * @param __CEC_CLKSOURCE__: specifies the CEC clock source.
Kojto 107:4f6c30876dfa 2451 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2452 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 107:4f6c30876dfa 2453 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 107:4f6c30876dfa 2454 */
Kojto 107:4f6c30876dfa 2455 #define __HAL_RCC_CEC_CONFIG(__CEC_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2456 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__CEC_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2457
Kojto 107:4f6c30876dfa 2458 /** @brief macro to get the CEC clock source.
Kojto 107:4f6c30876dfa 2459 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2460 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 107:4f6c30876dfa 2461 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 107:4f6c30876dfa 2462 */
Kojto 107:4f6c30876dfa 2463 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL)))
Kojto 107:4f6c30876dfa 2464
Kojto 107:4f6c30876dfa 2465 /** @brief Macro to configure the CLK48 source (CLK48CLK).
Kojto 107:4f6c30876dfa 2466 *
Kojto 107:4f6c30876dfa 2467 * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
Kojto 107:4f6c30876dfa 2468 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2469 * @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
Kojto 107:4f6c30876dfa 2470 * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 selected as CLK48 source
Kojto 107:4f6c30876dfa 2471 */
Kojto 107:4f6c30876dfa 2472 #define __HAL_RCC_CLK48_CONFIG(__CLK48_SOURCE__) \
Kojto 107:4f6c30876dfa 2473 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__CLK48_SOURCE__))
Kojto 107:4f6c30876dfa 2474
Kojto 107:4f6c30876dfa 2475 /** @brief macro to get the CLK48 source.
Kojto 107:4f6c30876dfa 2476 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2477 * @arg RCC_CLK48SOURCE_PLL: PLL used as CLK48 source
Kojto 107:4f6c30876dfa 2478 * @arg RCC_CLK48SOURCE_PLSAI1: PLLSAI1 used as CLK48 source
Kojto 107:4f6c30876dfa 2479 */
Kojto 107:4f6c30876dfa 2480 #define __HAL_RCC_GET_CLK48_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL)))
Kojto 107:4f6c30876dfa 2481
Kojto 107:4f6c30876dfa 2482 /** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
Kojto 107:4f6c30876dfa 2483 *
Kojto 107:4f6c30876dfa 2484 * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
Kojto 107:4f6c30876dfa 2485 * This parameter can be one of the following values:
Kojto 107:4f6c30876dfa 2486 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
Kojto 107:4f6c30876dfa 2487 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
Kojto 107:4f6c30876dfa 2488 */
Kojto 107:4f6c30876dfa 2489 #define __HAL_RCC_SDMMC1_CONFIG(__SDMMC1_CLKSOURCE__) \
Kojto 107:4f6c30876dfa 2490 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL, (uint32_t)(__SDMMC1_CLKSOURCE__))
Kojto 107:4f6c30876dfa 2491
Kojto 107:4f6c30876dfa 2492 /** @brief macro to get the SDMMC1 clock source.
Kojto 107:4f6c30876dfa 2493 * @retval The clock source can be one of the following values:
Kojto 107:4f6c30876dfa 2494 * @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 2495 * @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC1 clock
Kojto 107:4f6c30876dfa 2496 */
Kojto 107:4f6c30876dfa 2497 #define __HAL_RCC_GET_SDMMC1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDMMC1SEL)))
Kojto 107:4f6c30876dfa 2498
Kojto 107:4f6c30876dfa 2499 /**
Kojto 107:4f6c30876dfa 2500 * @}
Kojto 107:4f6c30876dfa 2501 */
Kojto 107:4f6c30876dfa 2502
Kojto 107:4f6c30876dfa 2503 /* Exported functions --------------------------------------------------------*/
Kojto 107:4f6c30876dfa 2504 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 107:4f6c30876dfa 2505 * @{
Kojto 107:4f6c30876dfa 2506 */
Kojto 107:4f6c30876dfa 2507 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 107:4f6c30876dfa 2508 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 107:4f6c30876dfa 2509 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto 107:4f6c30876dfa 2510
Kojto 107:4f6c30876dfa 2511 /**
Kojto 107:4f6c30876dfa 2512 * @}
Kojto 107:4f6c30876dfa 2513 */
Kojto 107:4f6c30876dfa 2514 /* Private macros ------------------------------------------------------------*/
Kojto 107:4f6c30876dfa 2515 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
Kojto 107:4f6c30876dfa 2516 * @{
Kojto 107:4f6c30876dfa 2517 */
Kojto 107:4f6c30876dfa 2518 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 107:4f6c30876dfa 2519 * @{
Kojto 107:4f6c30876dfa 2520 */
Kojto 107:4f6c30876dfa 2521 #if defined(STM32F756xx) || defined(STM32F746xx)
Kojto 107:4f6c30876dfa 2522 #define IS_RCC_PERIPHCLOCK(SELECTION) \
Kojto 107:4f6c30876dfa 2523 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
Kojto 107:4f6c30876dfa 2524 (((SELECTION) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) || \
Kojto 107:4f6c30876dfa 2525 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
Kojto 107:4f6c30876dfa 2526 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 107:4f6c30876dfa 2527 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 107:4f6c30876dfa 2528 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 107:4f6c30876dfa 2529 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 107:4f6c30876dfa 2530 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 107:4f6c30876dfa 2531 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
Kojto 107:4f6c30876dfa 2532 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
Kojto 107:4f6c30876dfa 2533 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
Kojto 107:4f6c30876dfa 2534 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 107:4f6c30876dfa 2535 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 107:4f6c30876dfa 2536 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 107:4f6c30876dfa 2537 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
Kojto 107:4f6c30876dfa 2538 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 107:4f6c30876dfa 2539 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 107:4f6c30876dfa 2540 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 107:4f6c30876dfa 2541 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
Kojto 107:4f6c30876dfa 2542 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
Kojto 107:4f6c30876dfa 2543 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
Kojto 107:4f6c30876dfa 2544 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
Kojto 107:4f6c30876dfa 2545 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
Kojto 107:4f6c30876dfa 2546 #elif defined(STM32F745xx)
Kojto 107:4f6c30876dfa 2547 #define IS_RCC_PERIPHCLOCK(SELECTION) \
Kojto 107:4f6c30876dfa 2548 ((((SELECTION) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) || \
Kojto 107:4f6c30876dfa 2549 (((SELECTION) & RCC_PERIPHCLK_TIM) == RCC_PERIPHCLK_TIM) || \
Kojto 107:4f6c30876dfa 2550 (((SELECTION) & RCC_PERIPHCLK_USART1) == RCC_PERIPHCLK_USART1) || \
Kojto 107:4f6c30876dfa 2551 (((SELECTION) & RCC_PERIPHCLK_USART2) == RCC_PERIPHCLK_USART2) || \
Kojto 107:4f6c30876dfa 2552 (((SELECTION) & RCC_PERIPHCLK_USART3) == RCC_PERIPHCLK_USART3) || \
Kojto 107:4f6c30876dfa 2553 (((SELECTION) & RCC_PERIPHCLK_UART4) == RCC_PERIPHCLK_UART4) || \
Kojto 107:4f6c30876dfa 2554 (((SELECTION) & RCC_PERIPHCLK_UART5) == RCC_PERIPHCLK_UART5) || \
Kojto 107:4f6c30876dfa 2555 (((SELECTION) & RCC_PERIPHCLK_USART6) == RCC_PERIPHCLK_USART6) || \
Kojto 107:4f6c30876dfa 2556 (((SELECTION) & RCC_PERIPHCLK_UART7) == RCC_PERIPHCLK_UART7) || \
Kojto 107:4f6c30876dfa 2557 (((SELECTION) & RCC_PERIPHCLK_UART8) == RCC_PERIPHCLK_UART8) || \
Kojto 107:4f6c30876dfa 2558 (((SELECTION) & RCC_PERIPHCLK_I2C1) == RCC_PERIPHCLK_I2C1) || \
Kojto 107:4f6c30876dfa 2559 (((SELECTION) & RCC_PERIPHCLK_I2C2) == RCC_PERIPHCLK_I2C2) || \
Kojto 107:4f6c30876dfa 2560 (((SELECTION) & RCC_PERIPHCLK_I2C3) == RCC_PERIPHCLK_I2C3) || \
Kojto 107:4f6c30876dfa 2561 (((SELECTION) & RCC_PERIPHCLK_I2C4) == RCC_PERIPHCLK_I2C4) || \
Kojto 107:4f6c30876dfa 2562 (((SELECTION) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1) || \
Kojto 107:4f6c30876dfa 2563 (((SELECTION) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) || \
Kojto 107:4f6c30876dfa 2564 (((SELECTION) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) || \
Kojto 107:4f6c30876dfa 2565 (((SELECTION) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) || \
Kojto 107:4f6c30876dfa 2566 (((SELECTION) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC) || \
Kojto 107:4f6c30876dfa 2567 (((SELECTION) & RCC_PERIPHCLK_SDMMC1) == RCC_PERIPHCLK_SDMMC1) || \
Kojto 107:4f6c30876dfa 2568 (((SELECTION) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) || \
Kojto 107:4f6c30876dfa 2569 (((SELECTION) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC))
Kojto 107:4f6c30876dfa 2570 #endif /* STM32F756xx || STM32F746xx */
Kojto 107:4f6c30876dfa 2571 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
Kojto 107:4f6c30876dfa 2572 #define IS_RCC_PLLI2SP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
Kojto 107:4f6c30876dfa 2573 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto 107:4f6c30876dfa 2574 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 107:4f6c30876dfa 2575
Kojto 107:4f6c30876dfa 2576 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
Kojto 107:4f6c30876dfa 2577 #define IS_RCC_PLLSAIP_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 8))
Kojto 107:4f6c30876dfa 2578 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto 107:4f6c30876dfa 2579 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 107:4f6c30876dfa 2580
Kojto 107:4f6c30876dfa 2581 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto 107:4f6c30876dfa 2582
Kojto 107:4f6c30876dfa 2583 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto 107:4f6c30876dfa 2584
Kojto 107:4f6c30876dfa 2585 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
Kojto 107:4f6c30876dfa 2586 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
Kojto 107:4f6c30876dfa 2587 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
Kojto 107:4f6c30876dfa 2588 ((VALUE) == RCC_PLLSAIDIVR_16))
Kojto 107:4f6c30876dfa 2589 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_PLLI2S) || \
Kojto 107:4f6c30876dfa 2590 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto 107:4f6c30876dfa 2591 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) || \
Kojto 107:4f6c30876dfa 2592 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) || \
Kojto 107:4f6c30876dfa 2593 ((SOURCE) == RCC_SAI1CLKSOURCE_PIN))
Kojto 107:4f6c30876dfa 2594 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) || \
Kojto 107:4f6c30876dfa 2595 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) || \
Kojto 107:4f6c30876dfa 2596 ((SOURCE) == RCC_SAI2CLKSOURCE_PIN))
Kojto 107:4f6c30876dfa 2597
Kojto 107:4f6c30876dfa 2598 #define IS_RCC_SDMMC1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SDMMC1CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 2599 ((SOURCE) == RCC_SDMMC1CLKSOURCE_CLK48))
Kojto 107:4f6c30876dfa 2600
Kojto 107:4f6c30876dfa 2601 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
Kojto 107:4f6c30876dfa 2602 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto 107:4f6c30876dfa 2603 #define IS_RCC_USART1CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2604 (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 107:4f6c30876dfa 2605 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 2606 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 2607 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2608
Kojto 107:4f6c30876dfa 2609 #define IS_RCC_USART2CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2610 (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2611 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 2612 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 2613 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2614 #define IS_RCC_USART3CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2615 (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2616 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 2617 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 2618 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2619
Kojto 107:4f6c30876dfa 2620 #define IS_RCC_UART4CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2621 (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2622 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 2623 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 2624 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2625
Kojto 107:4f6c30876dfa 2626 #define IS_RCC_UART5CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2627 (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2628 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 2629 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 2630 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2631
Kojto 107:4f6c30876dfa 2632 #define IS_RCC_USART6CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2633 (((SOURCE) == RCC_USART6CLKSOURCE_PCLK2) || \
Kojto 107:4f6c30876dfa 2634 ((SOURCE) == RCC_USART6CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 2635 ((SOURCE) == RCC_USART6CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 2636 ((SOURCE) == RCC_USART6CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2637
Kojto 107:4f6c30876dfa 2638 #define IS_RCC_UART7CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2639 (((SOURCE) == RCC_UART7CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2640 ((SOURCE) == RCC_UART7CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 2641 ((SOURCE) == RCC_UART7CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 2642 ((SOURCE) == RCC_UART7CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2643
Kojto 107:4f6c30876dfa 2644 #define IS_RCC_UART8CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2645 (((SOURCE) == RCC_UART8CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2646 ((SOURCE) == RCC_UART8CLKSOURCE_SYSCLK) || \
Kojto 107:4f6c30876dfa 2647 ((SOURCE) == RCC_UART8CLKSOURCE_LSE) || \
Kojto 107:4f6c30876dfa 2648 ((SOURCE) == RCC_UART8CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2649 #define IS_RCC_I2C1CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2650 (((SOURCE) == RCC_I2C1CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2651 ((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
Kojto 107:4f6c30876dfa 2652 ((SOURCE) == RCC_I2C1CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2653 #define IS_RCC_I2C2CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2654 (((SOURCE) == RCC_I2C2CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2655 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK)|| \
Kojto 107:4f6c30876dfa 2656 ((SOURCE) == RCC_I2C2CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2657
Kojto 107:4f6c30876dfa 2658 #define IS_RCC_I2C3CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2659 (((SOURCE) == RCC_I2C3CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2660 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
Kojto 107:4f6c30876dfa 2661 ((SOURCE) == RCC_I2C3CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2662 #define IS_RCC_I2C4CLKSOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2663 (((SOURCE) == RCC_I2C4CLKSOURCE_PCLK1) || \
Kojto 107:4f6c30876dfa 2664 ((SOURCE) == RCC_I2C4CLKSOURCE_SYSCLK)|| \
Kojto 107:4f6c30876dfa 2665 ((SOURCE) == RCC_I2C4CLKSOURCE_HSI))
Kojto 107:4f6c30876dfa 2666 #define IS_RCC_LPTIM1CLK(SOURCE) \
Kojto 107:4f6c30876dfa 2667 (((SOURCE) == RCC_LPTIM1CLKSOURCE_PCLK) || \
Kojto 107:4f6c30876dfa 2668 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSI) || \
Kojto 107:4f6c30876dfa 2669 ((SOURCE) == RCC_LPTIM1CLKSOURCE_HSI) || \
Kojto 107:4f6c30876dfa 2670 ((SOURCE) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto 107:4f6c30876dfa 2671 #define IS_RCC_CLK48SOURCE(SOURCE) \
Kojto 107:4f6c30876dfa 2672 (((SOURCE) == RCC_CLK48SOURCE_PLLSAIP) || \
Kojto 107:4f6c30876dfa 2673 ((SOURCE) == RCC_CLK48SOURCE_PLL))
Kojto 107:4f6c30876dfa 2674 #define IS_RCC_TIMPRES(VALUE) \
Kojto 107:4f6c30876dfa 2675 (((VALUE) == RCC_TIMPRES_DESACTIVATED) || \
Kojto 107:4f6c30876dfa 2676 ((VALUE) == RCC_TIMPRES_ACTIVATED))
Kojto 107:4f6c30876dfa 2677 /**
Kojto 107:4f6c30876dfa 2678 * @}
Kojto 107:4f6c30876dfa 2679 */
Kojto 107:4f6c30876dfa 2680
Kojto 107:4f6c30876dfa 2681 /**
Kojto 107:4f6c30876dfa 2682 * @}
Kojto 107:4f6c30876dfa 2683 */
Kojto 107:4f6c30876dfa 2684
Kojto 107:4f6c30876dfa 2685 /**
Kojto 107:4f6c30876dfa 2686 * @}
Kojto 107:4f6c30876dfa 2687 */
Kojto 107:4f6c30876dfa 2688
Kojto 107:4f6c30876dfa 2689 /**
Kojto 107:4f6c30876dfa 2690 * @}
Kojto 107:4f6c30876dfa 2691 */
Kojto 107:4f6c30876dfa 2692 #ifdef __cplusplus
Kojto 107:4f6c30876dfa 2693 }
Kojto 107:4f6c30876dfa 2694 #endif
Kojto 107:4f6c30876dfa 2695
Kojto 107:4f6c30876dfa 2696 #endif /* __STM32F7xx_HAL_RCC_EX_H */
Kojto 107:4f6c30876dfa 2697
Kojto 107:4f6c30876dfa 2698 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/