Ricardo Benitez / mbed

meh

Fork of mbed by mbed official

LPC2368/LPC23xx.h@17:49a220cc26e0, 2009-12-01 (annotated)

Committer:
simon.ford@mbed.co.uk
Date:
Tue Dec 01 14:24:15 2009 +0000
Revision:
17:49a220cc26e0
Parent:
14:20a79241b4a0
Child:
21:3944f1e2fa4f
* Update LPC1768 clock to 96MHz

 * Update Serial to support up to 921600 baud

 * Fix USB clock divider and base address

 * Improve stackheap model and enforce alignment

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rolf.meyer@arm.com 11:1c1ebd0324fa 1 /* mbed Microcontroller Library - LPC23xx CMSIS-like structs
rolf.meyer@arm.com 11:1c1ebd0324fa 2 * Copyright (C) 2009 ARM Limited. All rights reserved.
rolf.meyer@arm.com 11:1c1ebd0324fa 3 *
rolf.meyer@arm.com 11:1c1ebd0324fa 4 * An LPC23xx header file, based on the CMSIS LPC17xx.h and old LPC23xx.h
rolf.meyer@arm.com 11:1c1ebd0324fa 5 */
rolf.meyer@arm.com 11:1c1ebd0324fa 6
rolf.meyer@arm.com 11:1c1ebd0324fa 7 #ifndef __LPC23xx_H
rolf.meyer@arm.com 11:1c1ebd0324fa 8 #define __LPC23xx_H
rolf.meyer@arm.com 11:1c1ebd0324fa 9
rolf.meyer@arm.com 11:1c1ebd0324fa 10 #ifdef __cplusplus
rolf.meyer@arm.com 11:1c1ebd0324fa 11 extern "C" {
rolf.meyer@arm.com 11:1c1ebd0324fa 12 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 13
rolf.meyer@arm.com 11:1c1ebd0324fa 14 /*
rolf.meyer@arm.com 11:1c1ebd0324fa 15 * ==========================================================================
rolf.meyer@arm.com 11:1c1ebd0324fa 16 * ---------- Interrupt Number Definition -----------------------------------
rolf.meyer@arm.com 11:1c1ebd0324fa 17 * ==========================================================================
rolf.meyer@arm.com 11:1c1ebd0324fa 18 */
rolf.meyer@arm.com 11:1c1ebd0324fa 19
rolf.meyer@arm.com 11:1c1ebd0324fa 20 typedef enum IRQn
rolf.meyer@arm.com 11:1c1ebd0324fa 21 {
rolf.meyer@arm.com 11:1c1ebd0324fa 22 /****** LPC23xx Specific Interrupt Numbers *******************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 23 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 24
rolf.meyer@arm.com 11:1c1ebd0324fa 25 TIMER0_IRQn = 4, /*!< Timer0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 26 TIMER1_IRQn = 5, /*!< Timer1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 27 UART0_IRQn = 6, /*!< UART0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 28 UART1_IRQn = 7, /*!< UART1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 29 PWM1_IRQn = 8, /*!< PWM1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 30 I2C0_IRQn = 9, /*!< I2C0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 31 SPI_IRQn = 10, /*!< SPI Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 32 SSP0_IRQn = 10, /*!< SSP0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 33 SSP1_IRQn = 11, /*!< SSP1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 34 PLL0_IRQn = 12, /*!< PLL0 Lock (Main PLL) Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 35 RTC_IRQn = 13, /*!< Real Time Clock Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 36 EINT0_IRQn = 14, /*!< External Interrupt 0 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 37 EINT1_IRQn = 15, /*!< External Interrupt 1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 38 EINT2_IRQn = 16, /*!< External Interrupt 2 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 39 EINT3_IRQn = 17, /*!< External Interrupt 3 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 40 ADC_IRQn = 18, /*!< A/D Converter Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 41 I2C1_IRQn = 19, /*!< I2C1 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 42 BOD_IRQn = 20, /*!< Brown-Out Detect Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 43 ENET_IRQn = 21, /*!< Ethernet Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 44 USB_IRQn = 22, /*!< USB Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 45 CAN_IRQn = 23, /*!< CAN Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 46 MIC_IRQn = 24, /*!< Multimedia Interface Controler */
rolf.meyer@arm.com 11:1c1ebd0324fa 47 DMA_IRQn = 25, /*!< General Purpose DMA Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 48 TIMER2_IRQn = 26, /*!< Timer2 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 49 TIMER3_IRQn = 27, /*!< Timer3 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 50 UART2_IRQn = 28, /*!< UART2 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 51 UART3_IRQn = 29, /*!< UART3 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 52 I2C2_IRQn = 30, /*!< I2C2 Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 53 I2S_IRQn = 31, /*!< I2S Interrupt */
rolf.meyer@arm.com 11:1c1ebd0324fa 54 } IRQn_Type;
rolf.meyer@arm.com 11:1c1ebd0324fa 55
rolf.meyer@arm.com 11:1c1ebd0324fa 56 /*
rolf.meyer@arm.com 11:1c1ebd0324fa 57 * ==========================================================================
rolf.meyer@arm.com 11:1c1ebd0324fa 58 * ----------- Processor and Core Peripheral Section ------------------------
rolf.meyer@arm.com 11:1c1ebd0324fa 59 * ==========================================================================
rolf.meyer@arm.com 11:1c1ebd0324fa 60 */
rolf.meyer@arm.com 11:1c1ebd0324fa 61
rolf.meyer@arm.com 11:1c1ebd0324fa 62 /* Configuration of the ARM7 Processor and Core Peripherals */
rolf.meyer@arm.com 11:1c1ebd0324fa 63 #define __MPU_PRESENT 0 /*!< MPU present or not */
rolf.meyer@arm.com 11:1c1ebd0324fa 64 #define __NVIC_PRIO_BITS 4 /*!< Number of Bits used for Priority Levels */
rolf.meyer@arm.com 11:1c1ebd0324fa 65 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
rolf.meyer@arm.com 11:1c1ebd0324fa 66
rolf.meyer@arm.com 11:1c1ebd0324fa 67
rolf.meyer@arm.com 11:1c1ebd0324fa 68 #include <core_arm7.h>
rolf.meyer@arm.com 11:1c1ebd0324fa 69 #include "system_LPC23xx.h" /* System Header */
rolf.meyer@arm.com 11:1c1ebd0324fa 70
rolf.meyer@arm.com 11:1c1ebd0324fa 71
rolf.meyer@arm.com 11:1c1ebd0324fa 72 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 73 /* Device Specific Peripheral registers structures */
rolf.meyer@arm.com 11:1c1ebd0324fa 74 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 75
rolf.meyer@arm.com 11:1c1ebd0324fa 76 #pragma anon_unions
rolf.meyer@arm.com 11:1c1ebd0324fa 77
rolf.meyer@arm.com 11:1c1ebd0324fa 78 /*------------- Vector Interupt Controler (VIC) ------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 79 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 80 {
rolf.meyer@arm.com 11:1c1ebd0324fa 81 __I uint32_t IRQStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 82 __I uint32_t FIQStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 83 __I uint32_t RawIntr;
rolf.meyer@arm.com 11:1c1ebd0324fa 84 __IO uint32_t IntSelect;
rolf.meyer@arm.com 11:1c1ebd0324fa 85 __IO uint32_t IntEnable;
rolf.meyer@arm.com 11:1c1ebd0324fa 86 __O uint32_t IntEnClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 87 __IO uint32_t SoftInt;
rolf.meyer@arm.com 11:1c1ebd0324fa 88 __O uint32_t SoftIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 89 __IO uint32_t Protection;
rolf.meyer@arm.com 11:1c1ebd0324fa 90 __IO uint32_t SWPriorityMask;
rolf.meyer@arm.com 11:1c1ebd0324fa 91 __IO uint32_t RESERVED0[54];
rolf.meyer@arm.com 11:1c1ebd0324fa 92 __IO uint32_t VectAddr[32];
rolf.meyer@arm.com 11:1c1ebd0324fa 93 __IO uint32_t RESERVED1[32];
rolf.meyer@arm.com 11:1c1ebd0324fa 94 __IO uint32_t VectPriority[32];
rolf.meyer@arm.com 11:1c1ebd0324fa 95 __IO uint32_t RESERVED2[800];
rolf.meyer@arm.com 11:1c1ebd0324fa 96 __IO uint32_t Address;
rolf.meyer@arm.com 11:1c1ebd0324fa 97 } LPC_VIC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 98
rolf.meyer@arm.com 11:1c1ebd0324fa 99 /*------------- System Control (SC) ------------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 100 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 101 {
rolf.meyer@arm.com 11:1c1ebd0324fa 102 __IO uint32_t MAMCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 103 __IO uint32_t MAMTIM;
rolf.meyer@arm.com 11:1c1ebd0324fa 104 uint32_t RESERVED0[14];
rolf.meyer@arm.com 11:1c1ebd0324fa 105 __IO uint32_t MEMMAP;
rolf.meyer@arm.com 11:1c1ebd0324fa 106 uint32_t RESERVED1[15];
rolf.meyer@arm.com 11:1c1ebd0324fa 107 __IO uint32_t PLL0CON; /* Clocking and Power Control */
rolf.meyer@arm.com 11:1c1ebd0324fa 108 __IO uint32_t PLL0CFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 109 __I uint32_t PLL0STAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 110 __O uint32_t PLL0FEED;
rolf.meyer@arm.com 11:1c1ebd0324fa 111 uint32_t RESERVED2[12];
rolf.meyer@arm.com 11:1c1ebd0324fa 112 __IO uint32_t PCON;
rolf.meyer@arm.com 11:1c1ebd0324fa 113 __IO uint32_t PCONP;
rolf.meyer@arm.com 11:1c1ebd0324fa 114 uint32_t RESERVED3[15];
rolf.meyer@arm.com 11:1c1ebd0324fa 115 __IO uint32_t CCLKCFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 116 __IO uint32_t USBCLKCFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 117 __IO uint32_t CLKSRCSEL;
rolf.meyer@arm.com 11:1c1ebd0324fa 118 uint32_t RESERVED4[12];
rolf.meyer@arm.com 11:1c1ebd0324fa 119 __IO uint32_t EXTINT; /* External Interrupts */
rolf.meyer@arm.com 11:1c1ebd0324fa 120 __IO uint32_t INTWAKE;
rolf.meyer@arm.com 11:1c1ebd0324fa 121 __IO uint32_t EXTMODE;
rolf.meyer@arm.com 11:1c1ebd0324fa 122 __IO uint32_t EXTPOLAR;
rolf.meyer@arm.com 11:1c1ebd0324fa 123 uint32_t RESERVED6[12];
rolf.meyer@arm.com 11:1c1ebd0324fa 124 __IO uint32_t RSID; /* Reset */
rolf.meyer@arm.com 11:1c1ebd0324fa 125 __IO uint32_t CSPR;
rolf.meyer@arm.com 11:1c1ebd0324fa 126 __IO uint32_t AHBCFG1;
rolf.meyer@arm.com 11:1c1ebd0324fa 127 __IO uint32_t AHBCFG2;
rolf.meyer@arm.com 11:1c1ebd0324fa 128 uint32_t RESERVED7[4];
rolf.meyer@arm.com 11:1c1ebd0324fa 129 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 130 __IO uint32_t IRCTRIM; /* Clock Dividers */
rolf.meyer@arm.com 11:1c1ebd0324fa 131 __IO uint32_t PCLKSEL0;
rolf.meyer@arm.com 11:1c1ebd0324fa 132 __IO uint32_t PCLKSEL1;
rolf.meyer@arm.com 11:1c1ebd0324fa 133 uint32_t RESERVED8[4];
rolf.meyer@arm.com 11:1c1ebd0324fa 134 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
rolf.meyer@arm.com 11:1c1ebd0324fa 135 uint32_t RESERVED9;
rolf.meyer@arm.com 11:1c1ebd0324fa 136 // __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
rolf.meyer@arm.com 11:1c1ebd0324fa 137 } LPC_SC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 138
rolf.meyer@arm.com 11:1c1ebd0324fa 139 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 140 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 141 {
rolf.meyer@arm.com 11:1c1ebd0324fa 142 __IO uint32_t PINSEL0;
rolf.meyer@arm.com 11:1c1ebd0324fa 143 __IO uint32_t PINSEL1;
rolf.meyer@arm.com 11:1c1ebd0324fa 144 __IO uint32_t PINSEL2;
rolf.meyer@arm.com 11:1c1ebd0324fa 145 __IO uint32_t PINSEL3;
rolf.meyer@arm.com 11:1c1ebd0324fa 146 __IO uint32_t PINSEL4;
rolf.meyer@arm.com 11:1c1ebd0324fa 147 __IO uint32_t PINSEL5;
rolf.meyer@arm.com 11:1c1ebd0324fa 148 __IO uint32_t PINSEL6;
rolf.meyer@arm.com 11:1c1ebd0324fa 149 __IO uint32_t PINSEL7;
rolf.meyer@arm.com 11:1c1ebd0324fa 150 __IO uint32_t PINSEL8;
rolf.meyer@arm.com 11:1c1ebd0324fa 151 __IO uint32_t PINSEL9;
rolf.meyer@arm.com 11:1c1ebd0324fa 152 __IO uint32_t PINSEL10;
rolf.meyer@arm.com 11:1c1ebd0324fa 153 uint32_t RESERVED0[5];
rolf.meyer@arm.com 11:1c1ebd0324fa 154 __IO uint32_t PINMODE0;
rolf.meyer@arm.com 11:1c1ebd0324fa 155 __IO uint32_t PINMODE1;
rolf.meyer@arm.com 11:1c1ebd0324fa 156 __IO uint32_t PINMODE2;
rolf.meyer@arm.com 11:1c1ebd0324fa 157 __IO uint32_t PINMODE3;
rolf.meyer@arm.com 11:1c1ebd0324fa 158 __IO uint32_t PINMODE4;
rolf.meyer@arm.com 11:1c1ebd0324fa 159 __IO uint32_t PINMODE5;
rolf.meyer@arm.com 11:1c1ebd0324fa 160 __IO uint32_t PINMODE6;
rolf.meyer@arm.com 11:1c1ebd0324fa 161 __IO uint32_t PINMODE7;
rolf.meyer@arm.com 11:1c1ebd0324fa 162 __IO uint32_t PINMODE8;
rolf.meyer@arm.com 11:1c1ebd0324fa 163 __IO uint32_t PINMODE9;
rolf.meyer@arm.com 11:1c1ebd0324fa 164 __IO uint32_t PINMODE_OD0;
rolf.meyer@arm.com 11:1c1ebd0324fa 165 __IO uint32_t PINMODE_OD1;
rolf.meyer@arm.com 11:1c1ebd0324fa 166 __IO uint32_t PINMODE_OD2;
rolf.meyer@arm.com 11:1c1ebd0324fa 167 __IO uint32_t PINMODE_OD3;
rolf.meyer@arm.com 11:1c1ebd0324fa 168 __IO uint32_t PINMODE_OD4;
rolf.meyer@arm.com 11:1c1ebd0324fa 169 } LPC_PINCON_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 170
rolf.meyer@arm.com 11:1c1ebd0324fa 171 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 172 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 173 {
rolf.meyer@arm.com 11:1c1ebd0324fa 174 __IO uint32_t FIODIR;
rolf.meyer@arm.com 11:1c1ebd0324fa 175 uint32_t RESERVED0[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 176 __IO uint32_t FIOMASK;
rolf.meyer@arm.com 11:1c1ebd0324fa 177 __IO uint32_t FIOPIN;
rolf.meyer@arm.com 11:1c1ebd0324fa 178 __IO uint32_t FIOSET;
rolf.meyer@arm.com 11:1c1ebd0324fa 179 __O uint32_t FIOCLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 180 } LPC_GPIO_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 181
rolf.meyer@arm.com 11:1c1ebd0324fa 182 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 183 {
rolf.meyer@arm.com 11:1c1ebd0324fa 184 __I uint32_t IntStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 185 __I uint32_t IO0IntStatR;
rolf.meyer@arm.com 11:1c1ebd0324fa 186 __I uint32_t IO0IntStatF;
rolf.meyer@arm.com 11:1c1ebd0324fa 187 __O uint32_t IO0IntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 188 __IO uint32_t IO0IntEnR;
rolf.meyer@arm.com 11:1c1ebd0324fa 189 __IO uint32_t IO0IntEnF;
rolf.meyer@arm.com 11:1c1ebd0324fa 190 uint32_t RESERVED0[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 191 __I uint32_t IO2IntStatR;
rolf.meyer@arm.com 11:1c1ebd0324fa 192 __I uint32_t IO2IntStatF;
rolf.meyer@arm.com 11:1c1ebd0324fa 193 __O uint32_t IO2IntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 194 __IO uint32_t IO2IntEnR;
rolf.meyer@arm.com 11:1c1ebd0324fa 195 __IO uint32_t IO2IntEnF;
rolf.meyer@arm.com 11:1c1ebd0324fa 196 } LPC_GPIOINT_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 197
rolf.meyer@arm.com 11:1c1ebd0324fa 198 /*------------- Timer (TIM) --------------------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 199 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 200 {
rolf.meyer@arm.com 11:1c1ebd0324fa 201 __IO uint32_t IR;
rolf.meyer@arm.com 11:1c1ebd0324fa 202 __IO uint32_t TCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 203 __IO uint32_t TC;
rolf.meyer@arm.com 11:1c1ebd0324fa 204 __IO uint32_t PR;
rolf.meyer@arm.com 11:1c1ebd0324fa 205 __IO uint32_t PC;
rolf.meyer@arm.com 11:1c1ebd0324fa 206 __IO uint32_t MCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 207 __IO uint32_t MR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 208 __IO uint32_t MR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 209 __IO uint32_t MR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 210 __IO uint32_t MR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 211 __IO uint32_t CCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 212 __I uint32_t CR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 213 __I uint32_t CR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 214 uint32_t RESERVED0[2];
rolf.meyer@arm.com 11:1c1ebd0324fa 215 __IO uint32_t EMR;
rolf.meyer@arm.com 11:1c1ebd0324fa 216 uint32_t RESERVED1[24];
rolf.meyer@arm.com 11:1c1ebd0324fa 217 __IO uint32_t CTCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 218 } LPC_TIM_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 219
rolf.meyer@arm.com 11:1c1ebd0324fa 220 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 221 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 222 {
rolf.meyer@arm.com 11:1c1ebd0324fa 223 __IO uint32_t IR;
rolf.meyer@arm.com 11:1c1ebd0324fa 224 __IO uint32_t TCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 225 __IO uint32_t TC;
rolf.meyer@arm.com 11:1c1ebd0324fa 226 __IO uint32_t PR;
rolf.meyer@arm.com 11:1c1ebd0324fa 227 __IO uint32_t PC;
rolf.meyer@arm.com 11:1c1ebd0324fa 228 __IO uint32_t MCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 229 __IO uint32_t MR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 230 __IO uint32_t MR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 231 __IO uint32_t MR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 232 __IO uint32_t MR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 233 __IO uint32_t CCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 234 __I uint32_t CR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 235 __I uint32_t CR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 236 __I uint32_t CR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 237 __I uint32_t CR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 238 uint32_t RESERVED0;
rolf.meyer@arm.com 11:1c1ebd0324fa 239 __IO uint32_t MR4;
rolf.meyer@arm.com 11:1c1ebd0324fa 240 __IO uint32_t MR5;
rolf.meyer@arm.com 11:1c1ebd0324fa 241 __IO uint32_t MR6;
rolf.meyer@arm.com 11:1c1ebd0324fa 242 __IO uint32_t PCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 243 __IO uint32_t LER;
rolf.meyer@arm.com 11:1c1ebd0324fa 244 uint32_t RESERVED1[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 245 __IO uint32_t CTCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 246 } LPC_PWM_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 247
rolf.meyer@arm.com 11:1c1ebd0324fa 248 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 249 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 250 {
rolf.meyer@arm.com 11:1c1ebd0324fa 251 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 252 __I uint8_t RBR;
rolf.meyer@arm.com 11:1c1ebd0324fa 253 __O uint8_t THR;
rolf.meyer@arm.com 11:1c1ebd0324fa 254 __IO uint8_t DLL;
rolf.meyer@arm.com 11:1c1ebd0324fa 255 uint32_t RESERVED0;
rolf.meyer@arm.com 11:1c1ebd0324fa 256 };
rolf.meyer@arm.com 11:1c1ebd0324fa 257 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 258 __IO uint8_t DLM;
rolf.meyer@arm.com 11:1c1ebd0324fa 259 __IO uint32_t IER;
rolf.meyer@arm.com 11:1c1ebd0324fa 260 };
rolf.meyer@arm.com 11:1c1ebd0324fa 261 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 262 __I uint32_t IIR;
rolf.meyer@arm.com 11:1c1ebd0324fa 263 __O uint8_t FCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 264 };
rolf.meyer@arm.com 11:1c1ebd0324fa 265 __IO uint8_t LCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 266 uint8_t RESERVED1[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 267 __IO uint8_t LSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 268 uint8_t RESERVED2[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 269 __IO uint8_t SCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 270 uint8_t RESERVED3[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 271 __IO uint32_t ACR;
rolf.meyer@arm.com 11:1c1ebd0324fa 272 __IO uint8_t ICR;
rolf.meyer@arm.com 11:1c1ebd0324fa 273 uint8_t RESERVED4[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 274 __IO uint8_t FDR;
rolf.meyer@arm.com 11:1c1ebd0324fa 275 uint8_t RESERVED5[7];
rolf.meyer@arm.com 11:1c1ebd0324fa 276 __IO uint8_t TER;
rolf.meyer@arm.com 11:1c1ebd0324fa 277 uint8_t RESERVED6[27];
rolf.meyer@arm.com 11:1c1ebd0324fa 278 __IO uint8_t RS485CTRL;
rolf.meyer@arm.com 11:1c1ebd0324fa 279 uint8_t RESERVED7[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 280 __IO uint8_t ADRMATCH;
rolf.meyer@arm.com 11:1c1ebd0324fa 281 } LPC_UART_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 282
rolf.meyer@arm.com 11:1c1ebd0324fa 283 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 284 {
rolf.meyer@arm.com 11:1c1ebd0324fa 285 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 286 __I uint8_t RBR;
rolf.meyer@arm.com 11:1c1ebd0324fa 287 __O uint8_t THR;
rolf.meyer@arm.com 11:1c1ebd0324fa 288 __IO uint8_t DLL;
rolf.meyer@arm.com 11:1c1ebd0324fa 289 uint32_t RESERVED0;
rolf.meyer@arm.com 11:1c1ebd0324fa 290 };
rolf.meyer@arm.com 11:1c1ebd0324fa 291 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 292 __IO uint8_t DLM;
rolf.meyer@arm.com 11:1c1ebd0324fa 293 __IO uint32_t IER;
rolf.meyer@arm.com 11:1c1ebd0324fa 294 };
rolf.meyer@arm.com 11:1c1ebd0324fa 295 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 296 __I uint32_t IIR;
rolf.meyer@arm.com 11:1c1ebd0324fa 297 __O uint8_t FCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 298 };
rolf.meyer@arm.com 11:1c1ebd0324fa 299 __IO uint8_t LCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 300 uint8_t RESERVED1[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 301 __IO uint8_t MCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 302 uint8_t RESERVED2[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 303 __IO uint8_t LSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 304 uint8_t RESERVED3[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 305 __IO uint8_t MSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 306 uint8_t RESERVED4[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 307 __IO uint8_t SCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 308 uint8_t RESERVED5[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 309 __IO uint32_t ACR;
rolf.meyer@arm.com 11:1c1ebd0324fa 310 uint32_t RESERVED6;
rolf.meyer@arm.com 11:1c1ebd0324fa 311 __IO uint32_t FDR;
rolf.meyer@arm.com 11:1c1ebd0324fa 312 uint32_t RESERVED7;
rolf.meyer@arm.com 11:1c1ebd0324fa 313 __IO uint8_t TER;
rolf.meyer@arm.com 11:1c1ebd0324fa 314 uint8_t RESERVED8[27];
rolf.meyer@arm.com 11:1c1ebd0324fa 315 __IO uint8_t RS485CTRL;
rolf.meyer@arm.com 11:1c1ebd0324fa 316 uint8_t RESERVED9[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 317 __IO uint8_t ADRMATCH;
rolf.meyer@arm.com 11:1c1ebd0324fa 318 uint8_t RESERVED10[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 319 __IO uint8_t RS485DLY;
rolf.meyer@arm.com 11:1c1ebd0324fa 320 } LPC_UART1_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 321
rolf.meyer@arm.com 11:1c1ebd0324fa 322 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 323 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 324 {
rolf.meyer@arm.com 11:1c1ebd0324fa 325 __IO uint32_t SPCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 326 __I uint32_t SPSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 327 __IO uint32_t SPDR;
rolf.meyer@arm.com 11:1c1ebd0324fa 328 __IO uint32_t SPCCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 329 uint32_t RESERVED0[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 330 __IO uint32_t SPINT;
rolf.meyer@arm.com 11:1c1ebd0324fa 331 } LPC_SPI_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 332
rolf.meyer@arm.com 11:1c1ebd0324fa 333 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 334 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 335 {
rolf.meyer@arm.com 11:1c1ebd0324fa 336 __IO uint32_t CR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 337 __IO uint32_t CR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 338 __IO uint32_t DR;
rolf.meyer@arm.com 11:1c1ebd0324fa 339 __I uint32_t SR;
rolf.meyer@arm.com 11:1c1ebd0324fa 340 __IO uint32_t CPSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 341 __IO uint32_t IMSC;
rolf.meyer@arm.com 11:1c1ebd0324fa 342 __IO uint32_t RIS;
rolf.meyer@arm.com 11:1c1ebd0324fa 343 __IO uint32_t MIS;
rolf.meyer@arm.com 11:1c1ebd0324fa 344 __IO uint32_t ICR;
rolf.meyer@arm.com 11:1c1ebd0324fa 345 __IO uint32_t DMACR;
rolf.meyer@arm.com 11:1c1ebd0324fa 346 } LPC_SSP_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 347
rolf.meyer@arm.com 11:1c1ebd0324fa 348 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 349 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 350 {
rolf.meyer@arm.com 11:1c1ebd0324fa 351 __IO uint32_t I2CONSET;
rolf.meyer@arm.com 11:1c1ebd0324fa 352 __I uint32_t I2STAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 353 __IO uint32_t I2DAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 354 __IO uint32_t I2ADR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 355 __IO uint32_t I2SCLH;
rolf.meyer@arm.com 11:1c1ebd0324fa 356 __IO uint32_t I2SCLL;
rolf.meyer@arm.com 11:1c1ebd0324fa 357 __O uint32_t I2CONCLR;
rolf.meyer@arm.com 11:1c1ebd0324fa 358 __IO uint32_t MMCTRL;
rolf.meyer@arm.com 11:1c1ebd0324fa 359 __IO uint32_t I2ADR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 360 __IO uint32_t I2ADR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 361 __IO uint32_t I2ADR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 362 __I uint32_t I2DATA_BUFFER;
rolf.meyer@arm.com 11:1c1ebd0324fa 363 __IO uint32_t I2MASK0;
rolf.meyer@arm.com 11:1c1ebd0324fa 364 __IO uint32_t I2MASK1;
rolf.meyer@arm.com 11:1c1ebd0324fa 365 __IO uint32_t I2MASK2;
rolf.meyer@arm.com 11:1c1ebd0324fa 366 __IO uint32_t I2MASK3;
rolf.meyer@arm.com 11:1c1ebd0324fa 367 } LPC_I2C_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 368
rolf.meyer@arm.com 11:1c1ebd0324fa 369 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 370 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 371 {
rolf.meyer@arm.com 11:1c1ebd0324fa 372 __IO uint32_t I2SDAO;
rolf.meyer@arm.com 11:1c1ebd0324fa 373 __I uint32_t I2SDAI;
rolf.meyer@arm.com 11:1c1ebd0324fa 374 __O uint32_t I2STXFIFO;
rolf.meyer@arm.com 11:1c1ebd0324fa 375 __I uint32_t I2SRXFIFO;
rolf.meyer@arm.com 11:1c1ebd0324fa 376 __I uint32_t I2SSTATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 377 __IO uint32_t I2SDMA1;
rolf.meyer@arm.com 11:1c1ebd0324fa 378 __IO uint32_t I2SDMA2;
rolf.meyer@arm.com 11:1c1ebd0324fa 379 __IO uint32_t I2SIRQ;
rolf.meyer@arm.com 11:1c1ebd0324fa 380 __IO uint32_t I2STXRATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 381 __IO uint32_t I2SRXRATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 382 __IO uint32_t I2STXBITRATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 383 __IO uint32_t I2SRXBITRATE;
rolf.meyer@arm.com 11:1c1ebd0324fa 384 __IO uint32_t I2STXMODE;
rolf.meyer@arm.com 11:1c1ebd0324fa 385 __IO uint32_t I2SRXMODE;
rolf.meyer@arm.com 11:1c1ebd0324fa 386 } LPC_I2S_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 387
rolf.meyer@arm.com 11:1c1ebd0324fa 388 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 389 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 390 {
rolf.meyer@arm.com 11:1c1ebd0324fa 391 __IO uint8_t ILR;
rolf.meyer@arm.com 11:1c1ebd0324fa 392 uint8_t RESERVED0[3];
rolf.meyer@arm.com 14:20a79241b4a0 393 __IO uint8_t CTC;
rolf.meyer@arm.com 14:20a79241b4a0 394 uint8_t RESERVED1[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 395 __IO uint8_t CCR;
rolf.meyer@arm.com 14:20a79241b4a0 396 uint8_t RESERVED2[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 397 __IO uint8_t CIIR;
rolf.meyer@arm.com 14:20a79241b4a0 398 uint8_t RESERVED3[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 399 __IO uint8_t AMR;
rolf.meyer@arm.com 14:20a79241b4a0 400 uint8_t RESERVED4[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 401 __I uint32_t CTIME0;
rolf.meyer@arm.com 11:1c1ebd0324fa 402 __I uint32_t CTIME1;
rolf.meyer@arm.com 11:1c1ebd0324fa 403 __I uint32_t CTIME2;
rolf.meyer@arm.com 11:1c1ebd0324fa 404 __IO uint8_t SEC;
rolf.meyer@arm.com 14:20a79241b4a0 405 uint8_t RESERVED5[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 406 __IO uint8_t MIN;
rolf.meyer@arm.com 14:20a79241b4a0 407 uint8_t RESERVED6[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 408 __IO uint8_t HOUR;
rolf.meyer@arm.com 14:20a79241b4a0 409 uint8_t RESERVED7[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 410 __IO uint8_t DOM;
rolf.meyer@arm.com 14:20a79241b4a0 411 uint8_t RESERVED8[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 412 __IO uint8_t DOW;
rolf.meyer@arm.com 14:20a79241b4a0 413 uint8_t RESERVED9[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 414 __IO uint16_t DOY;
rolf.meyer@arm.com 14:20a79241b4a0 415 uint16_t RESERVED10;
rolf.meyer@arm.com 11:1c1ebd0324fa 416 __IO uint8_t MONTH;
rolf.meyer@arm.com 14:20a79241b4a0 417 uint8_t RESERVED11[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 418 __IO uint16_t YEAR;
rolf.meyer@arm.com 14:20a79241b4a0 419 uint16_t RESERVED12;
rolf.meyer@arm.com 11:1c1ebd0324fa 420 __IO uint32_t CALIBRATION;
rolf.meyer@arm.com 11:1c1ebd0324fa 421 __IO uint32_t GPREG0;
rolf.meyer@arm.com 11:1c1ebd0324fa 422 __IO uint32_t GPREG1;
rolf.meyer@arm.com 11:1c1ebd0324fa 423 __IO uint32_t GPREG2;
rolf.meyer@arm.com 11:1c1ebd0324fa 424 __IO uint32_t GPREG3;
rolf.meyer@arm.com 11:1c1ebd0324fa 425 __IO uint32_t GPREG4;
rolf.meyer@arm.com 11:1c1ebd0324fa 426 __IO uint8_t WAKEUPDIS;
rolf.meyer@arm.com 14:20a79241b4a0 427 uint8_t RESERVED13[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 428 __IO uint8_t PWRCTRL;
rolf.meyer@arm.com 11:1c1ebd0324fa 429 uint8_t RESERVED14[3];
rolf.meyer@arm.com 14:20a79241b4a0 430 __IO uint8_t ALSEC;
rolf.meyer@arm.com 11:1c1ebd0324fa 431 uint8_t RESERVED15[3];
rolf.meyer@arm.com 14:20a79241b4a0 432 __IO uint8_t ALMIN;
rolf.meyer@arm.com 14:20a79241b4a0 433 uint8_t RESERVED16[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 434 __IO uint8_t ALHOUR;
rolf.meyer@arm.com 14:20a79241b4a0 435 uint8_t RESERVED17[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 436 __IO uint8_t ALDOM;
rolf.meyer@arm.com 14:20a79241b4a0 437 uint8_t RESERVED18[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 438 __IO uint8_t ALDOW;
rolf.meyer@arm.com 14:20a79241b4a0 439 uint8_t RESERVED19[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 440 __IO uint16_t ALDOY;
rolf.meyer@arm.com 14:20a79241b4a0 441 uint16_t RESERVED20;
rolf.meyer@arm.com 11:1c1ebd0324fa 442 __IO uint8_t ALMON;
rolf.meyer@arm.com 14:20a79241b4a0 443 uint8_t RESERVED21[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 444 __IO uint16_t ALYEAR;
rolf.meyer@arm.com 14:20a79241b4a0 445 uint16_t RESERVED22;
rolf.meyer@arm.com 11:1c1ebd0324fa 446 } LPC_RTC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 447
rolf.meyer@arm.com 11:1c1ebd0324fa 448 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 449 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 450 {
rolf.meyer@arm.com 11:1c1ebd0324fa 451 __IO uint8_t WDMOD;
rolf.meyer@arm.com 11:1c1ebd0324fa 452 uint8_t RESERVED0[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 453 __IO uint32_t WDTC;
rolf.meyer@arm.com 11:1c1ebd0324fa 454 __O uint8_t WDFEED;
rolf.meyer@arm.com 11:1c1ebd0324fa 455 uint8_t RESERVED1[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 456 __I uint32_t WDTV;
rolf.meyer@arm.com 11:1c1ebd0324fa 457 __IO uint32_t WDCLKSEL;
rolf.meyer@arm.com 11:1c1ebd0324fa 458 } LPC_WDT_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 459
rolf.meyer@arm.com 11:1c1ebd0324fa 460 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 461 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 462 {
rolf.meyer@arm.com 11:1c1ebd0324fa 463 __IO uint32_t ADCR;
rolf.meyer@arm.com 11:1c1ebd0324fa 464 __IO uint32_t ADGDR;
rolf.meyer@arm.com 11:1c1ebd0324fa 465 uint32_t RESERVED0;
rolf.meyer@arm.com 11:1c1ebd0324fa 466 __IO uint32_t ADINTEN;
rolf.meyer@arm.com 11:1c1ebd0324fa 467 __I uint32_t ADDR0;
rolf.meyer@arm.com 11:1c1ebd0324fa 468 __I uint32_t ADDR1;
rolf.meyer@arm.com 11:1c1ebd0324fa 469 __I uint32_t ADDR2;
rolf.meyer@arm.com 11:1c1ebd0324fa 470 __I uint32_t ADDR3;
rolf.meyer@arm.com 11:1c1ebd0324fa 471 __I uint32_t ADDR4;
rolf.meyer@arm.com 11:1c1ebd0324fa 472 __I uint32_t ADDR5;
rolf.meyer@arm.com 11:1c1ebd0324fa 473 __I uint32_t ADDR6;
rolf.meyer@arm.com 11:1c1ebd0324fa 474 __I uint32_t ADDR7;
rolf.meyer@arm.com 11:1c1ebd0324fa 475 __I uint32_t ADSTAT;
rolf.meyer@arm.com 11:1c1ebd0324fa 476 __IO uint32_t ADTRM;
rolf.meyer@arm.com 11:1c1ebd0324fa 477 } LPC_ADC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 478
rolf.meyer@arm.com 11:1c1ebd0324fa 479 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 480 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 481 {
rolf.meyer@arm.com 11:1c1ebd0324fa 482 __IO uint32_t DACR;
rolf.meyer@arm.com 11:1c1ebd0324fa 483 __IO uint32_t DACCTRL;
rolf.meyer@arm.com 11:1c1ebd0324fa 484 __IO uint16_t DACCNTVAL;
rolf.meyer@arm.com 11:1c1ebd0324fa 485 } LPC_DAC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 486
rolf.meyer@arm.com 11:1c1ebd0324fa 487 /*------------- Multimedia Card Interface (MCI) ------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 488 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 489 {
rolf.meyer@arm.com 11:1c1ebd0324fa 490 __IO uint32_t MCIPower; /* Power control */
rolf.meyer@arm.com 11:1c1ebd0324fa 491 __IO uint32_t MCIClock; /* Clock control */
rolf.meyer@arm.com 11:1c1ebd0324fa 492 __IO uint32_t MCIArgument;
rolf.meyer@arm.com 11:1c1ebd0324fa 493 __IO uint32_t MMCCommand;
rolf.meyer@arm.com 11:1c1ebd0324fa 494 __I uint32_t MCIRespCmd;
rolf.meyer@arm.com 11:1c1ebd0324fa 495 __I uint32_t MCIResponse0;
rolf.meyer@arm.com 11:1c1ebd0324fa 496 __I uint32_t MCIResponse1;
rolf.meyer@arm.com 11:1c1ebd0324fa 497 __I uint32_t MCIResponse2;
rolf.meyer@arm.com 11:1c1ebd0324fa 498 __I uint32_t MCIResponse3;
rolf.meyer@arm.com 11:1c1ebd0324fa 499 __IO uint32_t MCIDataTimer;
rolf.meyer@arm.com 11:1c1ebd0324fa 500 __IO uint32_t MCIDataLength;
rolf.meyer@arm.com 11:1c1ebd0324fa 501 __IO uint32_t MCIDataCtrl;
rolf.meyer@arm.com 11:1c1ebd0324fa 502 __I uint32_t MCIDataCnt;
rolf.meyer@arm.com 11:1c1ebd0324fa 503 } LPC_MCI_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 504
rolf.meyer@arm.com 11:1c1ebd0324fa 505 /*------------- Controller Area Network (CAN) --------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 506 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 507 {
rolf.meyer@arm.com 11:1c1ebd0324fa 508 __IO uint32_t mask[512]; /* ID Masks */
rolf.meyer@arm.com 11:1c1ebd0324fa 509 } LPC_CANAF_RAM_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 510
rolf.meyer@arm.com 11:1c1ebd0324fa 511 typedef struct /* Acceptance Filter Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 512 {
rolf.meyer@arm.com 11:1c1ebd0324fa 513 __IO uint32_t AFMR;
rolf.meyer@arm.com 11:1c1ebd0324fa 514 __IO uint32_t SFF_sa;
rolf.meyer@arm.com 11:1c1ebd0324fa 515 __IO uint32_t SFF_GRP_sa;
rolf.meyer@arm.com 11:1c1ebd0324fa 516 __IO uint32_t EFF_sa;
rolf.meyer@arm.com 11:1c1ebd0324fa 517 __IO uint32_t EFF_GRP_sa;
rolf.meyer@arm.com 11:1c1ebd0324fa 518 __IO uint32_t ENDofTable;
rolf.meyer@arm.com 11:1c1ebd0324fa 519 __I uint32_t LUTerrAd;
rolf.meyer@arm.com 11:1c1ebd0324fa 520 __I uint32_t LUTerr;
rolf.meyer@arm.com 11:1c1ebd0324fa 521 } LPC_CANAF_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 522
rolf.meyer@arm.com 11:1c1ebd0324fa 523 typedef struct /* Central Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 524 {
rolf.meyer@arm.com 11:1c1ebd0324fa 525 __I uint32_t CANTxSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 526 __I uint32_t CANRxSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 527 __I uint32_t CANMSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 528 } LPC_CANCR_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 529
rolf.meyer@arm.com 11:1c1ebd0324fa 530 typedef struct /* Controller Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 531 {
rolf.meyer@arm.com 11:1c1ebd0324fa 532 __IO uint32_t MOD;
rolf.meyer@arm.com 11:1c1ebd0324fa 533 __O uint32_t CMR;
rolf.meyer@arm.com 11:1c1ebd0324fa 534 __IO uint32_t GSR;
rolf.meyer@arm.com 11:1c1ebd0324fa 535 __I uint32_t ICR;
rolf.meyer@arm.com 11:1c1ebd0324fa 536 __IO uint32_t IER;
rolf.meyer@arm.com 11:1c1ebd0324fa 537 __IO uint32_t BTR;
rolf.meyer@arm.com 11:1c1ebd0324fa 538 __IO uint32_t EWL;
rolf.meyer@arm.com 11:1c1ebd0324fa 539 __I uint32_t SR;
rolf.meyer@arm.com 11:1c1ebd0324fa 540 __IO uint32_t RFS;
rolf.meyer@arm.com 11:1c1ebd0324fa 541 __IO uint32_t RID;
rolf.meyer@arm.com 11:1c1ebd0324fa 542 __IO uint32_t RDA;
rolf.meyer@arm.com 11:1c1ebd0324fa 543 __IO uint32_t RDB;
rolf.meyer@arm.com 11:1c1ebd0324fa 544 __IO uint32_t TFI1;
rolf.meyer@arm.com 11:1c1ebd0324fa 545 __IO uint32_t TID1;
rolf.meyer@arm.com 11:1c1ebd0324fa 546 __IO uint32_t TDA1;
rolf.meyer@arm.com 11:1c1ebd0324fa 547 __IO uint32_t TDB1;
rolf.meyer@arm.com 11:1c1ebd0324fa 548 __IO uint32_t TFI2;
rolf.meyer@arm.com 11:1c1ebd0324fa 549 __IO uint32_t TID2;
rolf.meyer@arm.com 11:1c1ebd0324fa 550 __IO uint32_t TDA2;
rolf.meyer@arm.com 11:1c1ebd0324fa 551 __IO uint32_t TDB2;
rolf.meyer@arm.com 11:1c1ebd0324fa 552 __IO uint32_t TFI3;
rolf.meyer@arm.com 11:1c1ebd0324fa 553 __IO uint32_t TID3;
rolf.meyer@arm.com 11:1c1ebd0324fa 554 __IO uint32_t TDA3;
rolf.meyer@arm.com 11:1c1ebd0324fa 555 __IO uint32_t TDB3;
rolf.meyer@arm.com 11:1c1ebd0324fa 556 } LPC_CAN_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 557
rolf.meyer@arm.com 11:1c1ebd0324fa 558 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 559 typedef struct /* Common Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 560 {
rolf.meyer@arm.com 11:1c1ebd0324fa 561 __I uint32_t DMACIntStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 562 __I uint32_t DMACIntTCStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 563 __O uint32_t DMACIntTCClear;
rolf.meyer@arm.com 11:1c1ebd0324fa 564 __I uint32_t DMACIntErrStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 565 __O uint32_t DMACIntErrClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 566 __I uint32_t DMACRawIntTCStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 567 __I uint32_t DMACRawIntErrStat;
rolf.meyer@arm.com 11:1c1ebd0324fa 568 __I uint32_t DMACEnbldChns;
rolf.meyer@arm.com 11:1c1ebd0324fa 569 __IO uint32_t DMACSoftBReq;
rolf.meyer@arm.com 11:1c1ebd0324fa 570 __IO uint32_t DMACSoftSReq;
rolf.meyer@arm.com 11:1c1ebd0324fa 571 __IO uint32_t DMACSoftLBReq;
rolf.meyer@arm.com 11:1c1ebd0324fa 572 __IO uint32_t DMACSoftLSReq;
rolf.meyer@arm.com 11:1c1ebd0324fa 573 __IO uint32_t DMACConfig;
rolf.meyer@arm.com 11:1c1ebd0324fa 574 __IO uint32_t DMACSync;
rolf.meyer@arm.com 11:1c1ebd0324fa 575 } LPC_GPDMA_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 576
rolf.meyer@arm.com 11:1c1ebd0324fa 577 typedef struct /* Channel Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 578 {
rolf.meyer@arm.com 11:1c1ebd0324fa 579 __IO uint32_t DMACCSrcAddr;
rolf.meyer@arm.com 11:1c1ebd0324fa 580 __IO uint32_t DMACCDestAddr;
rolf.meyer@arm.com 11:1c1ebd0324fa 581 __IO uint32_t DMACCLLI;
rolf.meyer@arm.com 11:1c1ebd0324fa 582 __IO uint32_t DMACCControl;
rolf.meyer@arm.com 11:1c1ebd0324fa 583 __IO uint32_t DMACCConfig;
rolf.meyer@arm.com 11:1c1ebd0324fa 584 } LPC_GPDMACH_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 585
rolf.meyer@arm.com 11:1c1ebd0324fa 586 /*------------- Universal Serial Bus (USB) -----------------------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 587 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 588 {
rolf.meyer@arm.com 11:1c1ebd0324fa 589 __I uint32_t HcRevision; /* USB Host Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 590 __IO uint32_t HcControl;
rolf.meyer@arm.com 11:1c1ebd0324fa 591 __IO uint32_t HcCommandStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 592 __IO uint32_t HcInterruptStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 593 __IO uint32_t HcInterruptEnable;
rolf.meyer@arm.com 11:1c1ebd0324fa 594 __IO uint32_t HcInterruptDisable;
rolf.meyer@arm.com 11:1c1ebd0324fa 595 __IO uint32_t HcHCCA;
rolf.meyer@arm.com 11:1c1ebd0324fa 596 __I uint32_t HcPeriodCurrentED;
rolf.meyer@arm.com 11:1c1ebd0324fa 597 __IO uint32_t HcControlHeadED;
rolf.meyer@arm.com 11:1c1ebd0324fa 598 __IO uint32_t HcControlCurrentED;
rolf.meyer@arm.com 11:1c1ebd0324fa 599 __IO uint32_t HcBulkHeadED;
rolf.meyer@arm.com 11:1c1ebd0324fa 600 __IO uint32_t HcBulkCurrentED;
rolf.meyer@arm.com 11:1c1ebd0324fa 601 __I uint32_t HcDoneHead;
rolf.meyer@arm.com 11:1c1ebd0324fa 602 __IO uint32_t HcFmInterval;
rolf.meyer@arm.com 11:1c1ebd0324fa 603 __I uint32_t HcFmRemaining;
rolf.meyer@arm.com 11:1c1ebd0324fa 604 __I uint32_t HcFmNumber;
rolf.meyer@arm.com 11:1c1ebd0324fa 605 __IO uint32_t HcPeriodicStart;
rolf.meyer@arm.com 11:1c1ebd0324fa 606 __IO uint32_t HcLSTreshold;
rolf.meyer@arm.com 11:1c1ebd0324fa 607 __IO uint32_t HcRhDescriptorA;
rolf.meyer@arm.com 11:1c1ebd0324fa 608 __IO uint32_t HcRhDescriptorB;
rolf.meyer@arm.com 11:1c1ebd0324fa 609 __IO uint32_t HcRhStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 610 __IO uint32_t HcRhPortStatus1;
rolf.meyer@arm.com 11:1c1ebd0324fa 611 __IO uint32_t HcRhPortStatus2;
rolf.meyer@arm.com 11:1c1ebd0324fa 612 uint32_t RESERVED0[40];
rolf.meyer@arm.com 11:1c1ebd0324fa 613 __I uint32_t Module_ID;
rolf.meyer@arm.com 11:1c1ebd0324fa 614
rolf.meyer@arm.com 11:1c1ebd0324fa 615 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 616 __IO uint32_t OTGIntEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 617 __O uint32_t OTGIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 618 __O uint32_t OTGIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 619 __IO uint32_t OTGStCtrl;
rolf.meyer@arm.com 11:1c1ebd0324fa 620 __IO uint32_t OTGTmr;
rolf.meyer@arm.com 11:1c1ebd0324fa 621 uint32_t RESERVED1[58];
rolf.meyer@arm.com 11:1c1ebd0324fa 622
rolf.meyer@arm.com 11:1c1ebd0324fa 623 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 624 __IO uint32_t USBDevIntEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 625 __O uint32_t USBDevIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 626 __O uint32_t USBDevIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 627
rolf.meyer@arm.com 11:1c1ebd0324fa 628 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 629 __I uint32_t USBCmdData;
rolf.meyer@arm.com 11:1c1ebd0324fa 630
rolf.meyer@arm.com 11:1c1ebd0324fa 631 __I uint32_t USBRxData; /* USB Device Transfer Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 632 __O uint32_t USBTxData;
rolf.meyer@arm.com 11:1c1ebd0324fa 633 __I uint32_t USBRxPLen;
rolf.meyer@arm.com 11:1c1ebd0324fa 634 __O uint32_t USBTxPLen;
rolf.meyer@arm.com 11:1c1ebd0324fa 635 __IO uint32_t USBCtrl;
rolf.meyer@arm.com 11:1c1ebd0324fa 636 __O uint32_t USBDevIntPri;
rolf.meyer@arm.com 11:1c1ebd0324fa 637
rolf.meyer@arm.com 11:1c1ebd0324fa 638 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
rolf.meyer@arm.com 11:1c1ebd0324fa 639 __IO uint32_t USBEpIntEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 640 __O uint32_t USBEpIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 641 __O uint32_t USBEpIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 642 __O uint32_t USBEpIntPri;
rolf.meyer@arm.com 11:1c1ebd0324fa 643
rolf.meyer@arm.com 11:1c1ebd0324fa 644 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
rolf.meyer@arm.com 11:1c1ebd0324fa 645 __O uint32_t USBEpInd;
rolf.meyer@arm.com 11:1c1ebd0324fa 646 __IO uint32_t USBMaxPSize;
rolf.meyer@arm.com 11:1c1ebd0324fa 647
rolf.meyer@arm.com 11:1c1ebd0324fa 648 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 649 __O uint32_t USBDMARClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 650 __O uint32_t USBDMARSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 651 uint32_t RESERVED2[9];
rolf.meyer@arm.com 11:1c1ebd0324fa 652 __IO uint32_t USBUDCAH;
rolf.meyer@arm.com 11:1c1ebd0324fa 653 __I uint32_t USBEpDMASt;
rolf.meyer@arm.com 11:1c1ebd0324fa 654 __O uint32_t USBEpDMAEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 655 __O uint32_t USBEpDMADis;
rolf.meyer@arm.com 11:1c1ebd0324fa 656 __I uint32_t USBDMAIntSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 657 __IO uint32_t USBDMAIntEn;
rolf.meyer@arm.com 11:1c1ebd0324fa 658 uint32_t RESERVED3[2];
rolf.meyer@arm.com 11:1c1ebd0324fa 659 __I uint32_t USBEoTIntSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 660 __O uint32_t USBEoTIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 661 __O uint32_t USBEoTIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 662 __I uint32_t USBNDDRIntSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 663 __O uint32_t USBNDDRIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 664 __O uint32_t USBNDDRIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 665 __I uint32_t USBSysErrIntSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 666 __O uint32_t USBSysErrIntClr;
rolf.meyer@arm.com 11:1c1ebd0324fa 667 __O uint32_t USBSysErrIntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 668 uint32_t RESERVED4[15];
rolf.meyer@arm.com 11:1c1ebd0324fa 669
rolf.meyer@arm.com 11:1c1ebd0324fa 670 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 671 __O uint32_t I2C_WO;
rolf.meyer@arm.com 11:1c1ebd0324fa 672 __I uint32_t I2C_STS;
rolf.meyer@arm.com 11:1c1ebd0324fa 673 __IO uint32_t I2C_CTL;
rolf.meyer@arm.com 11:1c1ebd0324fa 674 __IO uint32_t I2C_CLKHI;
rolf.meyer@arm.com 11:1c1ebd0324fa 675 __O uint32_t I2C_CLKLO;
rolf.meyer@arm.com 11:1c1ebd0324fa 676 uint32_t RESERVED5[823];
rolf.meyer@arm.com 11:1c1ebd0324fa 677
rolf.meyer@arm.com 11:1c1ebd0324fa 678 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 679 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 680 __IO uint32_t OTGClkCtrl;
rolf.meyer@arm.com 11:1c1ebd0324fa 681 };
rolf.meyer@arm.com 11:1c1ebd0324fa 682 union {
rolf.meyer@arm.com 11:1c1ebd0324fa 683 __I uint32_t USBClkSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 684 __I uint32_t OTGClkSt;
rolf.meyer@arm.com 11:1c1ebd0324fa 685 };
rolf.meyer@arm.com 11:1c1ebd0324fa 686 } LPC_USB_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 687
rolf.meyer@arm.com 11:1c1ebd0324fa 688 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
rolf.meyer@arm.com 11:1c1ebd0324fa 689 typedef struct
rolf.meyer@arm.com 11:1c1ebd0324fa 690 {
rolf.meyer@arm.com 11:1c1ebd0324fa 691 __IO uint32_t MAC1; /* MAC Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 692 __IO uint32_t MAC2;
rolf.meyer@arm.com 11:1c1ebd0324fa 693 __IO uint32_t IPGT;
rolf.meyer@arm.com 11:1c1ebd0324fa 694 __IO uint32_t IPGR;
rolf.meyer@arm.com 11:1c1ebd0324fa 695 __IO uint32_t CLRT;
rolf.meyer@arm.com 11:1c1ebd0324fa 696 __IO uint32_t MAXF;
rolf.meyer@arm.com 11:1c1ebd0324fa 697 __IO uint32_t SUPP;
rolf.meyer@arm.com 11:1c1ebd0324fa 698 __IO uint32_t TEST;
rolf.meyer@arm.com 11:1c1ebd0324fa 699 __IO uint32_t MCFG;
rolf.meyer@arm.com 11:1c1ebd0324fa 700 __IO uint32_t MCMD;
rolf.meyer@arm.com 11:1c1ebd0324fa 701 __IO uint32_t MADR;
rolf.meyer@arm.com 11:1c1ebd0324fa 702 __O uint32_t MWTD;
rolf.meyer@arm.com 11:1c1ebd0324fa 703 __I uint32_t MRDD;
rolf.meyer@arm.com 11:1c1ebd0324fa 704 __I uint32_t MIND;
rolf.meyer@arm.com 11:1c1ebd0324fa 705 uint32_t RESERVED0[2];
rolf.meyer@arm.com 11:1c1ebd0324fa 706 __IO uint32_t SA0;
rolf.meyer@arm.com 11:1c1ebd0324fa 707 __IO uint32_t SA1;
rolf.meyer@arm.com 11:1c1ebd0324fa 708 __IO uint32_t SA2;
rolf.meyer@arm.com 11:1c1ebd0324fa 709 uint32_t RESERVED1[45];
rolf.meyer@arm.com 11:1c1ebd0324fa 710 __IO uint32_t Command; /* Control Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 711 __I uint32_t Status;
rolf.meyer@arm.com 11:1c1ebd0324fa 712 __IO uint32_t RxDescriptor;
rolf.meyer@arm.com 11:1c1ebd0324fa 713 __IO uint32_t RxStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 714 __IO uint32_t RxDescriptorNumber;
rolf.meyer@arm.com 11:1c1ebd0324fa 715 __I uint32_t RxProduceIndex;
rolf.meyer@arm.com 11:1c1ebd0324fa 716 __IO uint32_t RxConsumeIndex;
rolf.meyer@arm.com 11:1c1ebd0324fa 717 __IO uint32_t TxDescriptor;
rolf.meyer@arm.com 11:1c1ebd0324fa 718 __IO uint32_t TxStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 719 __IO uint32_t TxDescriptorNumber;
rolf.meyer@arm.com 11:1c1ebd0324fa 720 __IO uint32_t TxProduceIndex;
rolf.meyer@arm.com 11:1c1ebd0324fa 721 __I uint32_t TxConsumeIndex;
rolf.meyer@arm.com 11:1c1ebd0324fa 722 uint32_t RESERVED2[10];
rolf.meyer@arm.com 11:1c1ebd0324fa 723 __I uint32_t TSV0;
rolf.meyer@arm.com 11:1c1ebd0324fa 724 __I uint32_t TSV1;
rolf.meyer@arm.com 11:1c1ebd0324fa 725 __I uint32_t RSV;
rolf.meyer@arm.com 11:1c1ebd0324fa 726 uint32_t RESERVED3[3];
rolf.meyer@arm.com 11:1c1ebd0324fa 727 __IO uint32_t FlowControlCounter;
rolf.meyer@arm.com 11:1c1ebd0324fa 728 __I uint32_t FlowControlStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 729 uint32_t RESERVED4[34];
rolf.meyer@arm.com 11:1c1ebd0324fa 730 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 731 __IO uint32_t RxFilterWoLStatus;
rolf.meyer@arm.com 11:1c1ebd0324fa 732 __IO uint32_t RxFilterWoLClear;
rolf.meyer@arm.com 11:1c1ebd0324fa 733 uint32_t RESERVED5;
rolf.meyer@arm.com 11:1c1ebd0324fa 734 __IO uint32_t HashFilterL;
rolf.meyer@arm.com 11:1c1ebd0324fa 735 __IO uint32_t HashFilterH;
rolf.meyer@arm.com 11:1c1ebd0324fa 736 uint32_t RESERVED6[882];
rolf.meyer@arm.com 11:1c1ebd0324fa 737 __I uint32_t IntStatus; /* Module Control Registers */
rolf.meyer@arm.com 11:1c1ebd0324fa 738 __IO uint32_t IntEnable;
rolf.meyer@arm.com 11:1c1ebd0324fa 739 __O uint32_t IntClear;
rolf.meyer@arm.com 11:1c1ebd0324fa 740 __O uint32_t IntSet;
rolf.meyer@arm.com 11:1c1ebd0324fa 741 uint32_t RESERVED7;
rolf.meyer@arm.com 11:1c1ebd0324fa 742 __IO uint32_t PowerDown;
rolf.meyer@arm.com 11:1c1ebd0324fa 743 uint32_t RESERVED8;
rolf.meyer@arm.com 11:1c1ebd0324fa 744 __IO uint32_t Module_ID;
rolf.meyer@arm.com 11:1c1ebd0324fa 745 } LPC_EMAC_TypeDef;
rolf.meyer@arm.com 11:1c1ebd0324fa 746
rolf.meyer@arm.com 11:1c1ebd0324fa 747 #pragma no_anon_unions
rolf.meyer@arm.com 11:1c1ebd0324fa 748
rolf.meyer@arm.com 11:1c1ebd0324fa 749
rolf.meyer@arm.com 11:1c1ebd0324fa 750 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 751 /* Peripheral memory map */
rolf.meyer@arm.com 11:1c1ebd0324fa 752 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 753 /* Base addresses */
rolf.meyer@arm.com 11:1c1ebd0324fa 754
rolf.meyer@arm.com 11:1c1ebd0324fa 755 /* AHB Peripheral # 0 */
rolf.meyer@arm.com 11:1c1ebd0324fa 756
rolf.meyer@arm.com 11:1c1ebd0324fa 757 /*
rolf.meyer@arm.com 11:1c1ebd0324fa 758 #define FLASH_BASE (0x00000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 759 #define RAM_BASE (0x10000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 760 #define GPIO_BASE (0x2009C000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 761 #define APB0_BASE (0x40000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 762 #define APB1_BASE (0x40080000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 763 #define AHB_BASE (0x50000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 764 #define CM3_BASE (0xE0000000UL)
rolf.meyer@arm.com 11:1c1ebd0324fa 765 */
rolf.meyer@arm.com 11:1c1ebd0324fa 766
rolf.meyer@arm.com 11:1c1ebd0324fa 767 // TODO - #define VIC_BASE_ADDR 0xFFFFF000
rolf.meyer@arm.com 11:1c1ebd0324fa 768
rolf.meyer@arm.com 11:1c1ebd0324fa 769 #define LPC_WDT_BASE (0xE0000000)
rolf.meyer@arm.com 11:1c1ebd0324fa 770 #define LPC_TIM0_BASE (0xE0004000)
rolf.meyer@arm.com 11:1c1ebd0324fa 771 #define LPC_TIM1_BASE (0xE0008000)
rolf.meyer@arm.com 11:1c1ebd0324fa 772 #define LPC_UART0_BASE (0xE000C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 773 #define LPC_UART1_BASE (0xE0010000)
rolf.meyer@arm.com 11:1c1ebd0324fa 774 #define LPC_PWM1_BASE (0xE0018000)
rolf.meyer@arm.com 11:1c1ebd0324fa 775 #define LPC_I2C0_BASE (0xE001C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 776 #define LPC_SPI_BASE (0xE0020000)
rolf.meyer@arm.com 11:1c1ebd0324fa 777 #define LPC_RTC_BASE (0xE0024000)
rolf.meyer@arm.com 11:1c1ebd0324fa 778 #define LPC_GPIOINT_BASE (0xE0028080)
rolf.meyer@arm.com 11:1c1ebd0324fa 779 #define LPC_PINCON_BASE (0xE002C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 780 #define LPC_SSP1_BASE (0xE0030000)
rolf.meyer@arm.com 11:1c1ebd0324fa 781 #define LPC_ADC_BASE (0xE0034000)
rolf.meyer@arm.com 11:1c1ebd0324fa 782 #define LPC_CANAF_RAM_BASE (0xE0038000)
rolf.meyer@arm.com 11:1c1ebd0324fa 783 #define LPC_CANAF_BASE (0xE003C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 784 #define LPC_CANCR_BASE (0xE0040000)
rolf.meyer@arm.com 11:1c1ebd0324fa 785 #define LPC_CAN1_BASE (0xE0044000)
rolf.meyer@arm.com 11:1c1ebd0324fa 786 #define LPC_CAN2_BASE (0xE0048000)
rolf.meyer@arm.com 11:1c1ebd0324fa 787 #define LPC_I2C1_BASE (0xE005C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 788 #define LPC_SSP0_BASE (0xE0068000)
rolf.meyer@arm.com 11:1c1ebd0324fa 789 #define LPC_DAC_BASE (0xE006C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 790 #define LPC_TIM2_BASE (0xE0070000)
rolf.meyer@arm.com 11:1c1ebd0324fa 791 #define LPC_TIM3_BASE (0xE0074000)
rolf.meyer@arm.com 11:1c1ebd0324fa 792 #define LPC_UART2_BASE (0xE0078000)
rolf.meyer@arm.com 11:1c1ebd0324fa 793 #define LPC_UART3_BASE (0xE007C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 794 #define LPC_I2C2_BASE (0xE0080000)
rolf.meyer@arm.com 11:1c1ebd0324fa 795 #define LPC_I2S_BASE (0xE0088000)
rolf.meyer@arm.com 11:1c1ebd0324fa 796 #define LPC_MCI_BASE (0xE008C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 797 #define LPC_SC_BASE (0xE01FC000)
rolf.meyer@arm.com 11:1c1ebd0324fa 798 #define LPC_EMAC_BASE (0xFFE00000)
rolf.meyer@arm.com 11:1c1ebd0324fa 799 #define LPC_GPDMA_BASE (0xFFE04000)
rolf.meyer@arm.com 11:1c1ebd0324fa 800 #define LPC_GPDMACH0_BASE (0xFFE04100)
rolf.meyer@arm.com 11:1c1ebd0324fa 801 #define LPC_GPDMACH1_BASE (0xFFE04120)
simon.ford@mbed.co.uk 17:49a220cc26e0 802 #define LPC_USB_BASE (0xFFE0C000)
rolf.meyer@arm.com 11:1c1ebd0324fa 803 #define LPC_VIC_BASE (0xFFFFF000)
rolf.meyer@arm.com 11:1c1ebd0324fa 804
rolf.meyer@arm.com 11:1c1ebd0324fa 805 /* GPIOs */
rolf.meyer@arm.com 11:1c1ebd0324fa 806 #define LPC_GPIO0_BASE (0x3FFFC000)
rolf.meyer@arm.com 11:1c1ebd0324fa 807 #define LPC_GPIO1_BASE (0x3FFFC020)
rolf.meyer@arm.com 11:1c1ebd0324fa 808 #define LPC_GPIO2_BASE (0x3FFFC040)
rolf.meyer@arm.com 11:1c1ebd0324fa 809 #define LPC_GPIO3_BASE (0x3FFFC060)
rolf.meyer@arm.com 11:1c1ebd0324fa 810 #define LPC_GPIO4_BASE (0x3FFFC080)
rolf.meyer@arm.com 11:1c1ebd0324fa 811
rolf.meyer@arm.com 11:1c1ebd0324fa 812
rolf.meyer@arm.com 11:1c1ebd0324fa 813 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 814 /* Peripheral declaration */
rolf.meyer@arm.com 11:1c1ebd0324fa 815 /******************************************************************************/
rolf.meyer@arm.com 11:1c1ebd0324fa 816 #define LPC_SC (( LPC_SC_TypeDef *) LPC_SC_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 817 #define LPC_GPIO0 (( LPC_GPIO_TypeDef *) LPC_GPIO0_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 818 #define LPC_GPIO1 (( LPC_GPIO_TypeDef *) LPC_GPIO1_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 819 #define LPC_GPIO2 (( LPC_GPIO_TypeDef *) LPC_GPIO2_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 820 #define LPC_GPIO3 (( LPC_GPIO_TypeDef *) LPC_GPIO3_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 821 #define LPC_GPIO4 (( LPC_GPIO_TypeDef *) LPC_GPIO4_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 822 #define LPC_WDT (( LPC_WDT_TypeDef *) LPC_WDT_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 823 #define LPC_TIM0 (( LPC_TIM_TypeDef *) LPC_TIM0_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 824 #define LPC_TIM1 (( LPC_TIM_TypeDef *) LPC_TIM1_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 825 #define LPC_TIM2 (( LPC_TIM_TypeDef *) LPC_TIM2_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 826 #define LPC_TIM3 (( LPC_TIM_TypeDef *) LPC_TIM3_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 827 #define LPC_UART0 (( LPC_UART_TypeDef *) LPC_UART0_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 828 #define LPC_UART1 (( LPC_UART1_TypeDef *) LPC_UART1_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 829 #define LPC_UART2 (( LPC_UART_TypeDef *) LPC_UART2_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 830 #define LPC_UART3 (( LPC_UART_TypeDef *) LPC_UART3_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 831 #define LPC_PWM1 (( LPC_PWM_TypeDef *) LPC_PWM1_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 832 #define LPC_I2C0 (( LPC_I2C_TypeDef *) LPC_I2C0_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 833 #define LPC_I2C1 (( LPC_I2C_TypeDef *) LPC_I2C1_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 834 #define LPC_I2C2 (( LPC_I2C_TypeDef *) LPC_I2C2_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 835 #define LPC_I2S (( LPC_I2S_TypeDef *) LPC_I2S_BASE)
rolf.meyer@arm.com 13:a0336ede94ce 836 #define LPC_SPI (( LPC_SPI_TypeDef *) LPC_SPI_BASE)
rolf.meyer@arm.com 13:a0336ede94ce 837 #define LPC_RTC (( LPC_RTC_TypeDef *) LPC_RTC_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 838 #define LPC_GPIOINT (( LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 839 #define LPC_PINCON (( LPC_PINCON_TypeDef *) LPC_PINCON_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 840 #define LPC_SSP0 (( LPC_SSP_TypeDef *) LPC_SSP0_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 841 #define LPC_SSP1 (( LPC_SSP_TypeDef *) LPC_SSP1_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 842 #define LPC_ADC (( LPC_ADC_TypeDef *) LPC_ADC_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 843 #define LPC_DAC (( LPC_DAC_TypeDef *) LPC_DAC_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 844 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 845 #define LPC_CANAF (( LPC_CANAF_TypeDef *) LPC_CANAF_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 846 #define LPC_CANCR (( LPC_CANCR_TypeDef *) LPC_CANCR_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 847 #define LPC_CAN1 (( LPC_CAN_TypeDef *) LPC_CAN1_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 848 #define LPC_CAN2 (( LPC_CAN_TypeDef *) LPC_CAN2_BASE)
rolf.meyer@arm.com 13:a0336ede94ce 849 #define LPC_MCI (( LPC_MCI_TypeDef *) LPC_MCI_BASE)
rolf.meyer@arm.com 13:a0336ede94ce 850 #define LPC_EMAC (( LPC_EMAC_TypeDef *) LPC_EMAC_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 851 #define LPC_GPDMA (( LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 852 #define LPC_GPDMACH0 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 853 #define LPC_GPDMACH1 (( LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 854 #define LPC_USB (( LPC_USB_TypeDef *) LPC_USB_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 855 #define LPC_VIC (( LPC_VIC_TypeDef *) LPC_VIC_BASE)
rolf.meyer@arm.com 11:1c1ebd0324fa 856
rolf.meyer@arm.com 11:1c1ebd0324fa 857 #ifdef __cplusplus
rolf.meyer@arm.com 11:1c1ebd0324fa 858 }
rolf.meyer@arm.com 11:1c1ebd0324fa 859 #endif
rolf.meyer@arm.com 11:1c1ebd0324fa 860
rolf.meyer@arm.com 11:1c1ebd0324fa 861 #endif // __LPC23xx_H
rolf.meyer@arm.com 11:1c1ebd0324fa 862