Ricardo Benitez / mbed

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TARGET_NUCLEO_F401RE/cmsis_nvic.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
77:869cf507173a 
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /* mbed Microcontroller Library
emilmont 77:869cf507173a 2 * CMSIS-style functionality to support dynamic vectors
emilmont 77:869cf507173a 3 *******************************************************************************
emilmont 77:869cf507173a 4 * Copyright (c) 2014, STMicroelectronics
emilmont 77:869cf507173a 5 * All rights reserved.
emilmont 77:869cf507173a 6 *
emilmont 77:869cf507173a 7 * Redistribution and use in source and binary forms, with or without
emilmont 77:869cf507173a 8 * modification, are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 9 *
emilmont 77:869cf507173a 10 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 11 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 12 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 13 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 14 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 15 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 16 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 17 * without specific prior written permission.
emilmont 77:869cf507173a 18 *
emilmont 77:869cf507173a 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 20 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 21 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 23 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 24 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 25 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 26 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 27 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 28 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 29 *******************************************************************************
emilmont 77:869cf507173a 30 */
emilmont 77:869cf507173a 31
emilmont 77:869cf507173a 32 #ifndef MBED_CMSIS_NVIC_H
emilmont 77:869cf507173a 33 #define MBED_CMSIS_NVIC_H
emilmont 77:869cf507173a 34
emilmont 77:869cf507173a 35 // STM32F401RE
emilmont 77:869cf507173a 36 // CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
emilmont 77:869cf507173a 37 // MCU Peripherals: 85 vectors = 340 bytes from 0x40 to ...
emilmont 77:869cf507173a 38 // Total: 101 vectors = 404 bytes (0x194) to be reserved in RAM
emilmont 77:869cf507173a 39 #define NVIC_NUM_VECTORS 101
emilmont 77:869cf507173a 40 #define NVIC_USER_IRQ_OFFSET 16
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #include "cmsis.h"
emilmont 77:869cf507173a 43
emilmont 77:869cf507173a 44 #ifdef __cplusplus
emilmont 77:869cf507173a 45 extern "C" {
emilmont 77:869cf507173a 46 #endif
emilmont 77:869cf507173a 47
emilmont 77:869cf507173a 48 void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
emilmont 77:869cf507173a 49 uint32_t NVIC_GetVector(IRQn_Type IRQn);
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 #ifdef __cplusplus
emilmont 77:869cf507173a 52 }
emilmont 77:869cf507173a 53 #endif
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55 #endif