Ricardo Benitez / mbed

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TARGET_KL05Z/core_cmFunc.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
78:ed8466a608b4 
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 78:ed8466a608b4 1 /**************************************************************************//**
emilmont 78:ed8466a608b4 2 * @file core_cmFunc.h
emilmont 78:ed8466a608b4 3 * @brief CMSIS Cortex-M Core Function Access Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
emilmont 78:ed8466a608b4 6 *
emilmont 78:ed8466a608b4 7 * @note
emilmont 78:ed8466a608b4 8 *
emilmont 78:ed8466a608b4 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
emilmont 78:ed8466a608b4 11
emilmont 78:ed8466a608b4 12 All rights reserved.
emilmont 78:ed8466a608b4 13 Redistribution and use in source and binary forms, with or without
emilmont 78:ed8466a608b4 14 modification, are permitted provided that the following conditions are met:
emilmont 78:ed8466a608b4 15 - Redistributions of source code must retain the above copyright
emilmont 78:ed8466a608b4 16 notice, this list of conditions and the following disclaimer.
emilmont 78:ed8466a608b4 17 - Redistributions in binary form must reproduce the above copyright
emilmont 78:ed8466a608b4 18 notice, this list of conditions and the following disclaimer in the
emilmont 78:ed8466a608b4 19 documentation and/or other materials provided with the distribution.
emilmont 78:ed8466a608b4 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 78:ed8466a608b4 21 to endorse or promote products derived from this software without
emilmont 78:ed8466a608b4 22 specific prior written permission.
emilmont 78:ed8466a608b4 23 *
emilmont 78:ed8466a608b4 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 78:ed8466a608b4 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 78:ed8466a608b4 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 78:ed8466a608b4 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 78:ed8466a608b4 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 78:ed8466a608b4 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 78:ed8466a608b4 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 78:ed8466a608b4 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 78:ed8466a608b4 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 78:ed8466a608b4 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 78:ed8466a608b4 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 78:ed8466a608b4 35 ---------------------------------------------------------------------------*/
emilmont 78:ed8466a608b4 36
emilmont 78:ed8466a608b4 37
emilmont 78:ed8466a608b4 38 #ifndef __CORE_CMFUNC_H
emilmont 78:ed8466a608b4 39 #define __CORE_CMFUNC_H
emilmont 78:ed8466a608b4 40
emilmont 78:ed8466a608b4 41
emilmont 78:ed8466a608b4 42 /* ########################### Core Function Access ########################### */
emilmont 78:ed8466a608b4 43 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 78:ed8466a608b4 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
emilmont 78:ed8466a608b4 45 @{
emilmont 78:ed8466a608b4 46 */
emilmont 78:ed8466a608b4 47
emilmont 78:ed8466a608b4 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
emilmont 78:ed8466a608b4 49 /* ARM armcc specific functions */
emilmont 78:ed8466a608b4 50
emilmont 78:ed8466a608b4 51 #if (__ARMCC_VERSION < 400677)
emilmont 78:ed8466a608b4 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
emilmont 78:ed8466a608b4 53 #endif
emilmont 78:ed8466a608b4 54
emilmont 78:ed8466a608b4 55 /* intrinsic void __enable_irq(); */
emilmont 78:ed8466a608b4 56 /* intrinsic void __disable_irq(); */
emilmont 78:ed8466a608b4 57
emilmont 78:ed8466a608b4 58 /** \brief Get Control Register
emilmont 78:ed8466a608b4 59
emilmont 78:ed8466a608b4 60 This function returns the content of the Control Register.
emilmont 78:ed8466a608b4 61
emilmont 78:ed8466a608b4 62 \return Control Register value
emilmont 78:ed8466a608b4 63 */
emilmont 78:ed8466a608b4 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 78:ed8466a608b4 65 {
emilmont 78:ed8466a608b4 66 register uint32_t __regControl __ASM("control");
emilmont 78:ed8466a608b4 67 return(__regControl);
emilmont 78:ed8466a608b4 68 }
emilmont 78:ed8466a608b4 69
emilmont 78:ed8466a608b4 70
emilmont 78:ed8466a608b4 71 /** \brief Set Control Register
emilmont 78:ed8466a608b4 72
emilmont 78:ed8466a608b4 73 This function writes the given value to the Control Register.
emilmont 78:ed8466a608b4 74
emilmont 78:ed8466a608b4 75 \param [in] control Control Register value to set
emilmont 78:ed8466a608b4 76 */
emilmont 78:ed8466a608b4 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 78:ed8466a608b4 78 {
emilmont 78:ed8466a608b4 79 register uint32_t __regControl __ASM("control");
emilmont 78:ed8466a608b4 80 __regControl = control;
emilmont 78:ed8466a608b4 81 }
emilmont 78:ed8466a608b4 82
emilmont 78:ed8466a608b4 83
emilmont 78:ed8466a608b4 84 /** \brief Get IPSR Register
emilmont 78:ed8466a608b4 85
emilmont 78:ed8466a608b4 86 This function returns the content of the IPSR Register.
emilmont 78:ed8466a608b4 87
emilmont 78:ed8466a608b4 88 \return IPSR Register value
emilmont 78:ed8466a608b4 89 */
emilmont 78:ed8466a608b4 90 __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 78:ed8466a608b4 91 {
emilmont 78:ed8466a608b4 92 register uint32_t __regIPSR __ASM("ipsr");
emilmont 78:ed8466a608b4 93 return(__regIPSR);
emilmont 78:ed8466a608b4 94 }
emilmont 78:ed8466a608b4 95
emilmont 78:ed8466a608b4 96
emilmont 78:ed8466a608b4 97 /** \brief Get APSR Register
emilmont 78:ed8466a608b4 98
emilmont 78:ed8466a608b4 99 This function returns the content of the APSR Register.
emilmont 78:ed8466a608b4 100
emilmont 78:ed8466a608b4 101 \return APSR Register value
emilmont 78:ed8466a608b4 102 */
emilmont 78:ed8466a608b4 103 __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 78:ed8466a608b4 104 {
emilmont 78:ed8466a608b4 105 register uint32_t __regAPSR __ASM("apsr");
emilmont 78:ed8466a608b4 106 return(__regAPSR);
emilmont 78:ed8466a608b4 107 }
emilmont 78:ed8466a608b4 108
emilmont 78:ed8466a608b4 109
emilmont 78:ed8466a608b4 110 /** \brief Get xPSR Register
emilmont 78:ed8466a608b4 111
emilmont 78:ed8466a608b4 112 This function returns the content of the xPSR Register.
emilmont 78:ed8466a608b4 113
emilmont 78:ed8466a608b4 114 \return xPSR Register value
emilmont 78:ed8466a608b4 115 */
emilmont 78:ed8466a608b4 116 __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 78:ed8466a608b4 117 {
emilmont 78:ed8466a608b4 118 register uint32_t __regXPSR __ASM("xpsr");
emilmont 78:ed8466a608b4 119 return(__regXPSR);
emilmont 78:ed8466a608b4 120 }
emilmont 78:ed8466a608b4 121
emilmont 78:ed8466a608b4 122
emilmont 78:ed8466a608b4 123 /** \brief Get Process Stack Pointer
emilmont 78:ed8466a608b4 124
emilmont 78:ed8466a608b4 125 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 78:ed8466a608b4 126
emilmont 78:ed8466a608b4 127 \return PSP Register value
emilmont 78:ed8466a608b4 128 */
emilmont 78:ed8466a608b4 129 __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 78:ed8466a608b4 130 {
emilmont 78:ed8466a608b4 131 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 78:ed8466a608b4 132 return(__regProcessStackPointer);
emilmont 78:ed8466a608b4 133 }
emilmont 78:ed8466a608b4 134
emilmont 78:ed8466a608b4 135
emilmont 78:ed8466a608b4 136 /** \brief Set Process Stack Pointer
emilmont 78:ed8466a608b4 137
emilmont 78:ed8466a608b4 138 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 78:ed8466a608b4 139
emilmont 78:ed8466a608b4 140 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 78:ed8466a608b4 141 */
emilmont 78:ed8466a608b4 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 78:ed8466a608b4 143 {
emilmont 78:ed8466a608b4 144 register uint32_t __regProcessStackPointer __ASM("psp");
emilmont 78:ed8466a608b4 145 __regProcessStackPointer = topOfProcStack;
emilmont 78:ed8466a608b4 146 }
emilmont 78:ed8466a608b4 147
emilmont 78:ed8466a608b4 148
emilmont 78:ed8466a608b4 149 /** \brief Get Main Stack Pointer
emilmont 78:ed8466a608b4 150
emilmont 78:ed8466a608b4 151 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 78:ed8466a608b4 152
emilmont 78:ed8466a608b4 153 \return MSP Register value
emilmont 78:ed8466a608b4 154 */
emilmont 78:ed8466a608b4 155 __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 78:ed8466a608b4 156 {
emilmont 78:ed8466a608b4 157 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 78:ed8466a608b4 158 return(__regMainStackPointer);
emilmont 78:ed8466a608b4 159 }
emilmont 78:ed8466a608b4 160
emilmont 78:ed8466a608b4 161
emilmont 78:ed8466a608b4 162 /** \brief Set Main Stack Pointer
emilmont 78:ed8466a608b4 163
emilmont 78:ed8466a608b4 164 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 78:ed8466a608b4 165
emilmont 78:ed8466a608b4 166 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 78:ed8466a608b4 167 */
emilmont 78:ed8466a608b4 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 78:ed8466a608b4 169 {
emilmont 78:ed8466a608b4 170 register uint32_t __regMainStackPointer __ASM("msp");
emilmont 78:ed8466a608b4 171 __regMainStackPointer = topOfMainStack;
emilmont 78:ed8466a608b4 172 }
emilmont 78:ed8466a608b4 173
emilmont 78:ed8466a608b4 174
emilmont 78:ed8466a608b4 175 /** \brief Get Priority Mask
emilmont 78:ed8466a608b4 176
emilmont 78:ed8466a608b4 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 78:ed8466a608b4 178
emilmont 78:ed8466a608b4 179 \return Priority Mask value
emilmont 78:ed8466a608b4 180 */
emilmont 78:ed8466a608b4 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 78:ed8466a608b4 182 {
emilmont 78:ed8466a608b4 183 register uint32_t __regPriMask __ASM("primask");
emilmont 78:ed8466a608b4 184 return(__regPriMask);
emilmont 78:ed8466a608b4 185 }
emilmont 78:ed8466a608b4 186
emilmont 78:ed8466a608b4 187
emilmont 78:ed8466a608b4 188 /** \brief Set Priority Mask
emilmont 78:ed8466a608b4 189
emilmont 78:ed8466a608b4 190 This function assigns the given value to the Priority Mask Register.
emilmont 78:ed8466a608b4 191
emilmont 78:ed8466a608b4 192 \param [in] priMask Priority Mask
emilmont 78:ed8466a608b4 193 */
emilmont 78:ed8466a608b4 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 78:ed8466a608b4 195 {
emilmont 78:ed8466a608b4 196 register uint32_t __regPriMask __ASM("primask");
emilmont 78:ed8466a608b4 197 __regPriMask = (priMask);
emilmont 78:ed8466a608b4 198 }
emilmont 78:ed8466a608b4 199
emilmont 78:ed8466a608b4 200
Kojto 110:165afa46840b 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
emilmont 78:ed8466a608b4 202
emilmont 78:ed8466a608b4 203 /** \brief Enable FIQ
emilmont 78:ed8466a608b4 204
emilmont 78:ed8466a608b4 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 78:ed8466a608b4 206 Can only be executed in Privileged modes.
emilmont 78:ed8466a608b4 207 */
emilmont 78:ed8466a608b4 208 #define __enable_fault_irq __enable_fiq
emilmont 78:ed8466a608b4 209
emilmont 78:ed8466a608b4 210
emilmont 78:ed8466a608b4 211 /** \brief Disable FIQ
emilmont 78:ed8466a608b4 212
emilmont 78:ed8466a608b4 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 78:ed8466a608b4 214 Can only be executed in Privileged modes.
emilmont 78:ed8466a608b4 215 */
emilmont 78:ed8466a608b4 216 #define __disable_fault_irq __disable_fiq
emilmont 78:ed8466a608b4 217
emilmont 78:ed8466a608b4 218
emilmont 78:ed8466a608b4 219 /** \brief Get Base Priority
emilmont 78:ed8466a608b4 220
emilmont 78:ed8466a608b4 221 This function returns the current value of the Base Priority register.
emilmont 78:ed8466a608b4 222
emilmont 78:ed8466a608b4 223 \return Base Priority register value
emilmont 78:ed8466a608b4 224 */
emilmont 78:ed8466a608b4 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 78:ed8466a608b4 226 {
emilmont 78:ed8466a608b4 227 register uint32_t __regBasePri __ASM("basepri");
emilmont 78:ed8466a608b4 228 return(__regBasePri);
emilmont 78:ed8466a608b4 229 }
emilmont 78:ed8466a608b4 230
emilmont 78:ed8466a608b4 231
emilmont 78:ed8466a608b4 232 /** \brief Set Base Priority
emilmont 78:ed8466a608b4 233
emilmont 78:ed8466a608b4 234 This function assigns the given value to the Base Priority register.
emilmont 78:ed8466a608b4 235
emilmont 78:ed8466a608b4 236 \param [in] basePri Base Priority value to set
emilmont 78:ed8466a608b4 237 */
emilmont 78:ed8466a608b4 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
emilmont 78:ed8466a608b4 239 {
emilmont 78:ed8466a608b4 240 register uint32_t __regBasePri __ASM("basepri");
emilmont 78:ed8466a608b4 241 __regBasePri = (basePri & 0xff);
emilmont 78:ed8466a608b4 242 }
emilmont 78:ed8466a608b4 243
emilmont 78:ed8466a608b4 244
Kojto 110:165afa46840b 245 /** \brief Set Base Priority with condition
Kojto 110:165afa46840b 246
Kojto 110:165afa46840b 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
Kojto 110:165afa46840b 248 or the new value increases the BASEPRI priority level.
Kojto 110:165afa46840b 249
Kojto 110:165afa46840b 250 \param [in] basePri Base Priority value to set
Kojto 110:165afa46840b 251 */
Kojto 110:165afa46840b 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
Kojto 110:165afa46840b 253 {
Kojto 110:165afa46840b 254 register uint32_t __regBasePriMax __ASM("basepri_max");
Kojto 110:165afa46840b 255 __regBasePriMax = (basePri & 0xff);
Kojto 110:165afa46840b 256 }
Kojto 110:165afa46840b 257
Kojto 110:165afa46840b 258
emilmont 78:ed8466a608b4 259 /** \brief Get Fault Mask
emilmont 78:ed8466a608b4 260
emilmont 78:ed8466a608b4 261 This function returns the current value of the Fault Mask register.
emilmont 78:ed8466a608b4 262
emilmont 78:ed8466a608b4 263 \return Fault Mask register value
emilmont 78:ed8466a608b4 264 */
emilmont 78:ed8466a608b4 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 78:ed8466a608b4 266 {
emilmont 78:ed8466a608b4 267 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 78:ed8466a608b4 268 return(__regFaultMask);
emilmont 78:ed8466a608b4 269 }
emilmont 78:ed8466a608b4 270
emilmont 78:ed8466a608b4 271
emilmont 78:ed8466a608b4 272 /** \brief Set Fault Mask
emilmont 78:ed8466a608b4 273
emilmont 78:ed8466a608b4 274 This function assigns the given value to the Fault Mask register.
emilmont 78:ed8466a608b4 275
emilmont 78:ed8466a608b4 276 \param [in] faultMask Fault Mask value to set
emilmont 78:ed8466a608b4 277 */
emilmont 78:ed8466a608b4 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 78:ed8466a608b4 279 {
emilmont 78:ed8466a608b4 280 register uint32_t __regFaultMask __ASM("faultmask");
emilmont 78:ed8466a608b4 281 __regFaultMask = (faultMask & (uint32_t)1);
emilmont 78:ed8466a608b4 282 }
emilmont 78:ed8466a608b4 283
Kojto 110:165afa46840b 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
emilmont 78:ed8466a608b4 285
emilmont 78:ed8466a608b4 286
Kojto 110:165afa46840b 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
emilmont 78:ed8466a608b4 288
emilmont 78:ed8466a608b4 289 /** \brief Get FPSCR
emilmont 78:ed8466a608b4 290
emilmont 78:ed8466a608b4 291 This function returns the current value of the Floating Point Status/Control register.
emilmont 78:ed8466a608b4 292
emilmont 78:ed8466a608b4 293 \return Floating Point Status/Control register value
emilmont 78:ed8466a608b4 294 */
emilmont 78:ed8466a608b4 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 78:ed8466a608b4 296 {
emilmont 78:ed8466a608b4 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 78:ed8466a608b4 298 register uint32_t __regfpscr __ASM("fpscr");
emilmont 78:ed8466a608b4 299 return(__regfpscr);
emilmont 78:ed8466a608b4 300 #else
emilmont 78:ed8466a608b4 301 return(0);
emilmont 78:ed8466a608b4 302 #endif
emilmont 78:ed8466a608b4 303 }
emilmont 78:ed8466a608b4 304
emilmont 78:ed8466a608b4 305
emilmont 78:ed8466a608b4 306 /** \brief Set FPSCR
emilmont 78:ed8466a608b4 307
emilmont 78:ed8466a608b4 308 This function assigns the given value to the Floating Point Status/Control register.
emilmont 78:ed8466a608b4 309
emilmont 78:ed8466a608b4 310 \param [in] fpscr Floating Point Status/Control value to set
emilmont 78:ed8466a608b4 311 */
emilmont 78:ed8466a608b4 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 78:ed8466a608b4 313 {
emilmont 78:ed8466a608b4 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 78:ed8466a608b4 315 register uint32_t __regfpscr __ASM("fpscr");
emilmont 78:ed8466a608b4 316 __regfpscr = (fpscr);
emilmont 78:ed8466a608b4 317 #endif
emilmont 78:ed8466a608b4 318 }
emilmont 78:ed8466a608b4 319
Kojto 110:165afa46840b 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
emilmont 78:ed8466a608b4 321
emilmont 78:ed8466a608b4 322
emilmont 78:ed8466a608b4 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
emilmont 78:ed8466a608b4 324 /* GNU gcc specific functions */
emilmont 78:ed8466a608b4 325
emilmont 78:ed8466a608b4 326 /** \brief Enable IRQ Interrupts
emilmont 78:ed8466a608b4 327
emilmont 78:ed8466a608b4 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
emilmont 78:ed8466a608b4 329 Can only be executed in Privileged modes.
emilmont 78:ed8466a608b4 330 */
emilmont 78:ed8466a608b4 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
emilmont 78:ed8466a608b4 332 {
emilmont 78:ed8466a608b4 333 __ASM volatile ("cpsie i" : : : "memory");
emilmont 78:ed8466a608b4 334 }
emilmont 78:ed8466a608b4 335
emilmont 78:ed8466a608b4 336
emilmont 78:ed8466a608b4 337 /** \brief Disable IRQ Interrupts
emilmont 78:ed8466a608b4 338
emilmont 78:ed8466a608b4 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
emilmont 78:ed8466a608b4 340 Can only be executed in Privileged modes.
emilmont 78:ed8466a608b4 341 */
emilmont 78:ed8466a608b4 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
emilmont 78:ed8466a608b4 343 {
emilmont 78:ed8466a608b4 344 __ASM volatile ("cpsid i" : : : "memory");
emilmont 78:ed8466a608b4 345 }
emilmont 78:ed8466a608b4 346
emilmont 78:ed8466a608b4 347
emilmont 78:ed8466a608b4 348 /** \brief Get Control Register
emilmont 78:ed8466a608b4 349
emilmont 78:ed8466a608b4 350 This function returns the content of the Control Register.
emilmont 78:ed8466a608b4 351
emilmont 78:ed8466a608b4 352 \return Control Register value
emilmont 78:ed8466a608b4 353 */
emilmont 78:ed8466a608b4 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
emilmont 78:ed8466a608b4 355 {
emilmont 78:ed8466a608b4 356 uint32_t result;
emilmont 78:ed8466a608b4 357
emilmont 78:ed8466a608b4 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
emilmont 78:ed8466a608b4 359 return(result);
emilmont 78:ed8466a608b4 360 }
emilmont 78:ed8466a608b4 361
emilmont 78:ed8466a608b4 362
emilmont 78:ed8466a608b4 363 /** \brief Set Control Register
emilmont 78:ed8466a608b4 364
emilmont 78:ed8466a608b4 365 This function writes the given value to the Control Register.
emilmont 78:ed8466a608b4 366
emilmont 78:ed8466a608b4 367 \param [in] control Control Register value to set
emilmont 78:ed8466a608b4 368 */
emilmont 78:ed8466a608b4 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
emilmont 78:ed8466a608b4 370 {
emilmont 78:ed8466a608b4 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
emilmont 78:ed8466a608b4 372 }
emilmont 78:ed8466a608b4 373
emilmont 78:ed8466a608b4 374
emilmont 78:ed8466a608b4 375 /** \brief Get IPSR Register
emilmont 78:ed8466a608b4 376
emilmont 78:ed8466a608b4 377 This function returns the content of the IPSR Register.
emilmont 78:ed8466a608b4 378
emilmont 78:ed8466a608b4 379 \return IPSR Register value
emilmont 78:ed8466a608b4 380 */
emilmont 78:ed8466a608b4 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
emilmont 78:ed8466a608b4 382 {
emilmont 78:ed8466a608b4 383 uint32_t result;
emilmont 78:ed8466a608b4 384
emilmont 78:ed8466a608b4 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
emilmont 78:ed8466a608b4 386 return(result);
emilmont 78:ed8466a608b4 387 }
emilmont 78:ed8466a608b4 388
emilmont 78:ed8466a608b4 389
emilmont 78:ed8466a608b4 390 /** \brief Get APSR Register
emilmont 78:ed8466a608b4 391
emilmont 78:ed8466a608b4 392 This function returns the content of the APSR Register.
emilmont 78:ed8466a608b4 393
emilmont 78:ed8466a608b4 394 \return APSR Register value
emilmont 78:ed8466a608b4 395 */
emilmont 78:ed8466a608b4 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
emilmont 78:ed8466a608b4 397 {
emilmont 78:ed8466a608b4 398 uint32_t result;
emilmont 78:ed8466a608b4 399
emilmont 78:ed8466a608b4 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
emilmont 78:ed8466a608b4 401 return(result);
emilmont 78:ed8466a608b4 402 }
emilmont 78:ed8466a608b4 403
emilmont 78:ed8466a608b4 404
emilmont 78:ed8466a608b4 405 /** \brief Get xPSR Register
emilmont 78:ed8466a608b4 406
emilmont 78:ed8466a608b4 407 This function returns the content of the xPSR Register.
emilmont 78:ed8466a608b4 408
emilmont 78:ed8466a608b4 409 \return xPSR Register value
emilmont 78:ed8466a608b4 410 */
emilmont 78:ed8466a608b4 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
emilmont 78:ed8466a608b4 412 {
emilmont 78:ed8466a608b4 413 uint32_t result;
emilmont 78:ed8466a608b4 414
emilmont 78:ed8466a608b4 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
emilmont 78:ed8466a608b4 416 return(result);
emilmont 78:ed8466a608b4 417 }
emilmont 78:ed8466a608b4 418
emilmont 78:ed8466a608b4 419
emilmont 78:ed8466a608b4 420 /** \brief Get Process Stack Pointer
emilmont 78:ed8466a608b4 421
emilmont 78:ed8466a608b4 422 This function returns the current value of the Process Stack Pointer (PSP).
emilmont 78:ed8466a608b4 423
emilmont 78:ed8466a608b4 424 \return PSP Register value
emilmont 78:ed8466a608b4 425 */
emilmont 78:ed8466a608b4 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
emilmont 78:ed8466a608b4 427 {
emilmont 78:ed8466a608b4 428 register uint32_t result;
emilmont 78:ed8466a608b4 429
emilmont 78:ed8466a608b4 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
emilmont 78:ed8466a608b4 431 return(result);
emilmont 78:ed8466a608b4 432 }
emilmont 78:ed8466a608b4 433
emilmont 78:ed8466a608b4 434
emilmont 78:ed8466a608b4 435 /** \brief Set Process Stack Pointer
emilmont 78:ed8466a608b4 436
emilmont 78:ed8466a608b4 437 This function assigns the given value to the Process Stack Pointer (PSP).
emilmont 78:ed8466a608b4 438
emilmont 78:ed8466a608b4 439 \param [in] topOfProcStack Process Stack Pointer value to set
emilmont 78:ed8466a608b4 440 */
emilmont 78:ed8466a608b4 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
emilmont 78:ed8466a608b4 442 {
emilmont 78:ed8466a608b4 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
emilmont 78:ed8466a608b4 444 }
emilmont 78:ed8466a608b4 445
emilmont 78:ed8466a608b4 446
emilmont 78:ed8466a608b4 447 /** \brief Get Main Stack Pointer
emilmont 78:ed8466a608b4 448
emilmont 78:ed8466a608b4 449 This function returns the current value of the Main Stack Pointer (MSP).
emilmont 78:ed8466a608b4 450
emilmont 78:ed8466a608b4 451 \return MSP Register value
emilmont 78:ed8466a608b4 452 */
emilmont 78:ed8466a608b4 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
emilmont 78:ed8466a608b4 454 {
emilmont 78:ed8466a608b4 455 register uint32_t result;
emilmont 78:ed8466a608b4 456
emilmont 78:ed8466a608b4 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
emilmont 78:ed8466a608b4 458 return(result);
emilmont 78:ed8466a608b4 459 }
emilmont 78:ed8466a608b4 460
emilmont 78:ed8466a608b4 461
emilmont 78:ed8466a608b4 462 /** \brief Set Main Stack Pointer
emilmont 78:ed8466a608b4 463
emilmont 78:ed8466a608b4 464 This function assigns the given value to the Main Stack Pointer (MSP).
emilmont 78:ed8466a608b4 465
emilmont 78:ed8466a608b4 466 \param [in] topOfMainStack Main Stack Pointer value to set
emilmont 78:ed8466a608b4 467 */
emilmont 78:ed8466a608b4 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
emilmont 78:ed8466a608b4 469 {
emilmont 78:ed8466a608b4 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
emilmont 78:ed8466a608b4 471 }
emilmont 78:ed8466a608b4 472
emilmont 78:ed8466a608b4 473
emilmont 78:ed8466a608b4 474 /** \brief Get Priority Mask
emilmont 78:ed8466a608b4 475
emilmont 78:ed8466a608b4 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
emilmont 78:ed8466a608b4 477
emilmont 78:ed8466a608b4 478 \return Priority Mask value
emilmont 78:ed8466a608b4 479 */
emilmont 78:ed8466a608b4 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
emilmont 78:ed8466a608b4 481 {
emilmont 78:ed8466a608b4 482 uint32_t result;
emilmont 78:ed8466a608b4 483
emilmont 78:ed8466a608b4 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
emilmont 78:ed8466a608b4 485 return(result);
emilmont 78:ed8466a608b4 486 }
emilmont 78:ed8466a608b4 487
emilmont 78:ed8466a608b4 488
emilmont 78:ed8466a608b4 489 /** \brief Set Priority Mask
emilmont 78:ed8466a608b4 490
emilmont 78:ed8466a608b4 491 This function assigns the given value to the Priority Mask Register.
emilmont 78:ed8466a608b4 492
emilmont 78:ed8466a608b4 493 \param [in] priMask Priority Mask
emilmont 78:ed8466a608b4 494 */
emilmont 78:ed8466a608b4 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
emilmont 78:ed8466a608b4 496 {
emilmont 78:ed8466a608b4 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
emilmont 78:ed8466a608b4 498 }
emilmont 78:ed8466a608b4 499
emilmont 78:ed8466a608b4 500
emilmont 78:ed8466a608b4 501 #if (__CORTEX_M >= 0x03)
emilmont 78:ed8466a608b4 502
emilmont 78:ed8466a608b4 503 /** \brief Enable FIQ
emilmont 78:ed8466a608b4 504
emilmont 78:ed8466a608b4 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
emilmont 78:ed8466a608b4 506 Can only be executed in Privileged modes.
emilmont 78:ed8466a608b4 507 */
emilmont 78:ed8466a608b4 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
emilmont 78:ed8466a608b4 509 {
emilmont 78:ed8466a608b4 510 __ASM volatile ("cpsie f" : : : "memory");
emilmont 78:ed8466a608b4 511 }
emilmont 78:ed8466a608b4 512
emilmont 78:ed8466a608b4 513
emilmont 78:ed8466a608b4 514 /** \brief Disable FIQ
emilmont 78:ed8466a608b4 515
emilmont 78:ed8466a608b4 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
emilmont 78:ed8466a608b4 517 Can only be executed in Privileged modes.
emilmont 78:ed8466a608b4 518 */
emilmont 78:ed8466a608b4 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
emilmont 78:ed8466a608b4 520 {
emilmont 78:ed8466a608b4 521 __ASM volatile ("cpsid f" : : : "memory");
emilmont 78:ed8466a608b4 522 }
emilmont 78:ed8466a608b4 523
emilmont 78:ed8466a608b4 524
emilmont 78:ed8466a608b4 525 /** \brief Get Base Priority
emilmont 78:ed8466a608b4 526
emilmont 78:ed8466a608b4 527 This function returns the current value of the Base Priority register.
emilmont 78:ed8466a608b4 528
emilmont 78:ed8466a608b4 529 \return Base Priority register value
emilmont 78:ed8466a608b4 530 */
emilmont 78:ed8466a608b4 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
emilmont 78:ed8466a608b4 532 {
emilmont 78:ed8466a608b4 533 uint32_t result;
emilmont 78:ed8466a608b4 534
Kojto 110:165afa46840b 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
emilmont 78:ed8466a608b4 536 return(result);
emilmont 78:ed8466a608b4 537 }
emilmont 78:ed8466a608b4 538
emilmont 78:ed8466a608b4 539
emilmont 78:ed8466a608b4 540 /** \brief Set Base Priority
emilmont 78:ed8466a608b4 541
emilmont 78:ed8466a608b4 542 This function assigns the given value to the Base Priority register.
emilmont 78:ed8466a608b4 543
emilmont 78:ed8466a608b4 544 \param [in] basePri Base Priority value to set
emilmont 78:ed8466a608b4 545 */
emilmont 78:ed8466a608b4 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
emilmont 78:ed8466a608b4 547 {
emilmont 78:ed8466a608b4 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
emilmont 78:ed8466a608b4 549 }
emilmont 78:ed8466a608b4 550
emilmont 78:ed8466a608b4 551
Kojto 110:165afa46840b 552 /** \brief Set Base Priority with condition
Kojto 110:165afa46840b 553
Kojto 110:165afa46840b 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
Kojto 110:165afa46840b 555 or the new value increases the BASEPRI priority level.
Kojto 110:165afa46840b 556
Kojto 110:165afa46840b 557 \param [in] basePri Base Priority value to set
Kojto 110:165afa46840b 558 */
Kojto 110:165afa46840b 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
Kojto 110:165afa46840b 560 {
Kojto 110:165afa46840b 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
Kojto 110:165afa46840b 562 }
Kojto 110:165afa46840b 563
Kojto 110:165afa46840b 564
emilmont 78:ed8466a608b4 565 /** \brief Get Fault Mask
emilmont 78:ed8466a608b4 566
emilmont 78:ed8466a608b4 567 This function returns the current value of the Fault Mask register.
emilmont 78:ed8466a608b4 568
emilmont 78:ed8466a608b4 569 \return Fault Mask register value
emilmont 78:ed8466a608b4 570 */
emilmont 78:ed8466a608b4 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
emilmont 78:ed8466a608b4 572 {
emilmont 78:ed8466a608b4 573 uint32_t result;
emilmont 78:ed8466a608b4 574
emilmont 78:ed8466a608b4 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
emilmont 78:ed8466a608b4 576 return(result);
emilmont 78:ed8466a608b4 577 }
emilmont 78:ed8466a608b4 578
emilmont 78:ed8466a608b4 579
emilmont 78:ed8466a608b4 580 /** \brief Set Fault Mask
emilmont 78:ed8466a608b4 581
emilmont 78:ed8466a608b4 582 This function assigns the given value to the Fault Mask register.
emilmont 78:ed8466a608b4 583
emilmont 78:ed8466a608b4 584 \param [in] faultMask Fault Mask value to set
emilmont 78:ed8466a608b4 585 */
emilmont 78:ed8466a608b4 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
emilmont 78:ed8466a608b4 587 {
emilmont 78:ed8466a608b4 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
emilmont 78:ed8466a608b4 589 }
emilmont 78:ed8466a608b4 590
emilmont 78:ed8466a608b4 591 #endif /* (__CORTEX_M >= 0x03) */
emilmont 78:ed8466a608b4 592
emilmont 78:ed8466a608b4 593
Kojto 110:165afa46840b 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
emilmont 78:ed8466a608b4 595
emilmont 78:ed8466a608b4 596 /** \brief Get FPSCR
emilmont 78:ed8466a608b4 597
emilmont 78:ed8466a608b4 598 This function returns the current value of the Floating Point Status/Control register.
emilmont 78:ed8466a608b4 599
emilmont 78:ed8466a608b4 600 \return Floating Point Status/Control register value
emilmont 78:ed8466a608b4 601 */
emilmont 78:ed8466a608b4 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
emilmont 78:ed8466a608b4 603 {
emilmont 78:ed8466a608b4 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 78:ed8466a608b4 605 uint32_t result;
emilmont 78:ed8466a608b4 606
emilmont 78:ed8466a608b4 607 /* Empty asm statement works as a scheduling barrier */
emilmont 78:ed8466a608b4 608 __ASM volatile ("");
emilmont 78:ed8466a608b4 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
emilmont 78:ed8466a608b4 610 __ASM volatile ("");
emilmont 78:ed8466a608b4 611 return(result);
emilmont 78:ed8466a608b4 612 #else
emilmont 78:ed8466a608b4 613 return(0);
emilmont 78:ed8466a608b4 614 #endif
emilmont 78:ed8466a608b4 615 }
emilmont 78:ed8466a608b4 616
emilmont 78:ed8466a608b4 617
emilmont 78:ed8466a608b4 618 /** \brief Set FPSCR
emilmont 78:ed8466a608b4 619
emilmont 78:ed8466a608b4 620 This function assigns the given value to the Floating Point Status/Control register.
emilmont 78:ed8466a608b4 621
emilmont 78:ed8466a608b4 622 \param [in] fpscr Floating Point Status/Control value to set
emilmont 78:ed8466a608b4 623 */
emilmont 78:ed8466a608b4 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
emilmont 78:ed8466a608b4 625 {
emilmont 78:ed8466a608b4 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
emilmont 78:ed8466a608b4 627 /* Empty asm statement works as a scheduling barrier */
emilmont 78:ed8466a608b4 628 __ASM volatile ("");
emilmont 78:ed8466a608b4 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
emilmont 78:ed8466a608b4 630 __ASM volatile ("");
emilmont 78:ed8466a608b4 631 #endif
emilmont 78:ed8466a608b4 632 }
emilmont 78:ed8466a608b4 633
Kojto 110:165afa46840b 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
Kojto 110:165afa46840b 635
Kojto 110:165afa46840b 636
Kojto 110:165afa46840b 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
Kojto 110:165afa46840b 638 /* IAR iccarm specific functions */
Kojto 110:165afa46840b 639 #include <cmsis_iar.h>
Kojto 110:165afa46840b 640
Kojto 110:165afa46840b 641
Kojto 110:165afa46840b 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
Kojto 110:165afa46840b 643 /* TI CCS specific functions */
Kojto 110:165afa46840b 644 #include <cmsis_ccs.h>
emilmont 78:ed8466a608b4 645
emilmont 78:ed8466a608b4 646
emilmont 78:ed8466a608b4 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
emilmont 78:ed8466a608b4 648 /* TASKING carm specific functions */
emilmont 78:ed8466a608b4 649 /*
emilmont 78:ed8466a608b4 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
Kojto 110:165afa46840b 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
emilmont 78:ed8466a608b4 652 * Including the CMSIS ones.
emilmont 78:ed8466a608b4 653 */
emilmont 78:ed8466a608b4 654
Kojto 110:165afa46840b 655
Kojto 110:165afa46840b 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
Kojto 110:165afa46840b 657 /* Cosmic specific functions */
Kojto 110:165afa46840b 658 #include <cmsis_csm.h>
Kojto 110:165afa46840b 659
emilmont 78:ed8466a608b4 660 #endif
emilmont 78:ed8466a608b4 661
emilmont 78:ed8466a608b4 662 /*@} end of CMSIS_Core_RegAccFunctions */
emilmont 78:ed8466a608b4 663
emilmont 78:ed8466a608b4 664 #endif /* __CORE_CMFUNC_H */