Diff: TARGET_NUCLEO_F401RE/TOOLCHAIN_IAR/stm32f401xe.icf

Revision:

93:e188a91d3eaa

Parent:

90:cb3d968589d8

Child:

95:7e07b6fb45cf

--- a/TARGET_NUCLEO_F401RE/TOOLCHAIN_IAR/stm32f401xe.icf	Thu Nov 27 13:33:22 2014 +0000
+++ b/TARGET_NUCLEO_F401RE/TOOLCHAIN_IAR/stm32f401xe.icf	Tue Feb 03 15:31:20 2015 +0000
@@ -1,30 +1,32 @@
-/* [ROM] */
-define symbol __intvec_start__        = 0x08000000;
-define symbol __region_ROM_start__    = 0x08000000;
-define symbol __region_ROM_end__      = 0x0807FFFF;
-
-/* [RAM] Vector table dynamic copy: 101 vectors * 4 bytes = 404 bytes (0x194) */
+/*###ICF### Section handled by ICF editor, don't touch! ****/
+/*-Editor annotation file-*/
+/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_0.xml" */
+/*-Specials-*/
+define symbol __ICFEDIT_intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __ICFEDIT_region_ROM_start__ = 0x08000000;
+define symbol __ICFEDIT_region_ROM_end__   = 0x0807FFFF;
 define symbol __NVIC_start__          = 0x20000000;
 define symbol __NVIC_end__            = 0x20000197; /* to be aligned on 8 bytes */
-define symbol __region_RAM_start__    = 0x20000198;
-define symbol __region_RAM_end__      = 0x20017E67; /* 0x17FFF - 0x198 */
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region      = mem:[from __region_ROM_start__   to __region_ROM_end__];
-define region RAM_region      = mem:[from __region_RAM_start__   to __region_RAM_end__];
+define symbol __ICFEDIT_region_RAM_start__ = 0x20000198;
+define symbol __ICFEDIT_region_RAM_end__   = 0x20017FFF;
+/*-Sizes-*/
+define symbol __ICFEDIT_size_cstack__ = 0x2000;
+define symbol __ICFEDIT_size_heap__   = 0x2000;
+/**** End of ICF editor section. ###ICF###*/
 
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x400;
-define symbol __size_heap__   = 0x400;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+define memory mem with size = 4G;
+define region ROM_region   = mem:[from __ICFEDIT_region_ROM_start__   to __ICFEDIT_region_ROM_end__];
+define region RAM_region   = mem:[from __ICFEDIT_region_RAM_start__   to __ICFEDIT_region_RAM_end__];
 
-initialize by copy with packing = zeros { readwrite };
+define block CSTACK    with alignment = 8, size = __ICFEDIT_size_cstack__   { };
+define block HEAP      with alignment = 8, size = __ICFEDIT_size_heap__     { };
+
+initialize by copy { readwrite };
 do not initialize  { section .noinit };
 
-place at address mem:__intvec_start__ { readonly section .intvec };
+place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
 
 place in ROM_region   { readonly };
-place in RAM_region   { readwrite, block STACKHEAP };
+place in RAM_region   { readwrite,
+                        block HEAP, block CSTACK };