Diff: TARGET_LPC4088/TOOLCHAIN_GCC_CR/LPC407x_8x.ld

Revision:

69:4a7918f48478

Child:

76:824293ae5e43

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/TARGET_LPC4088/TOOLCHAIN_GCC_CR/LPC407x_8x.ld	Mon Nov 18 11:49:24 2013 +0200
@@ -0,0 +1,180 @@
+/*
+ * GENERATED FILE - DO NOT EDIT
+ * (C) Code Red Technologies Ltd, 2008-2013
+ * Generated linker script file for LPC4088
+ * Created from generic_c.ld (vLPCXpresso v5.1 (2 [Build 2065] [2013-02-20] ))
+ * By LPCXpresso v5.1.2 [Build 2065] [2013-02-20]  on Wed Apr 17 14:50:07 CEST 2013
+ */
+
+
+GROUP(libgcc.a libc.a libstdc++.a libm.a libcr_newlib_nohost.a crti.o crtn.o crtbegin.o crtend.o)
+
+MEMORY
+{
+  /* Define each memory region */
+  MFlash512 (rx) : ORIGIN = 0x0, LENGTH = 0x80000 /* 512k */
+  RamLoc64 (rwx) : ORIGIN = 0x100000E8, LENGTH = 0xFF18 /* 64k */
+  RamPeriph32 (rwx) : ORIGIN = 0x20000000, LENGTH = 0x8000 /* 32k */
+
+}
+  /* Define a symbol for the top of each memory region */
+  __top_MFlash512 = 0x0 + 0x80000;
+  __top_RamLoc64 = 0x10000000 + 0x10000;
+  __top_RamPeriph32 = 0x20000000 + 0x8000;
+
+ENTRY(ResetISR)
+
+SECTIONS
+{
+
+    /* MAIN TEXT SECTION */    
+    .text : ALIGN(4)
+    {
+        FILL(0xff)
+        KEEP(*(.isr_vector))
+        
+        /* Global Section Table */
+        . = ALIGN(4) ;
+        __section_table_start = .;
+        __data_section_table = .;
+        LONG(LOADADDR(.data));
+        LONG(    ADDR(.data)) ;
+        LONG(  SIZEOF(.data));
+        LONG(LOADADDR(.data_RAM2));
+        LONG(    ADDR(.data_RAM2)) ;
+        LONG(  SIZEOF(.data_RAM2));
+        __data_section_table_end = .;
+        __bss_section_table = .;
+        LONG(    ADDR(.bss));
+        LONG(  SIZEOF(.bss));
+        LONG(    ADDR(.bss_RAM2));
+        LONG(  SIZEOF(.bss_RAM2));
+        __bss_section_table_end = .;
+        __section_table_end = . ;
+        /* End of Global Section Table */
+        
+
+        *(.after_vectors*)
+        
+        *(.text*)
+        *(.rodata .rodata.*)
+        . = ALIGN(4);
+        
+        /* C++ constructors etc */
+        . = ALIGN(4);
+        KEEP(*(.init))
+        
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+        
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+        
+        KEEP(*(.fini));
+        
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+        
+        . = ALIGN(4);
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+        /* End C++ */
+    } > MFlash512
+
+    /*
+     * for exception handling/unwind - some Newlib functions (in common
+     * with C++ and STDC++) use this. 
+     */
+    .ARM.extab : ALIGN(4)
+    {
+    	*(.ARM.extab* .gnu.linkonce.armextab.*)
+    } > MFlash512
+    __exidx_start = .;
+    
+    .ARM.exidx : ALIGN(4)
+    {
+    	*(.ARM.exidx* .gnu.linkonce.armexidx.*)
+    } > MFlash512
+    __exidx_end = .;
+    
+    _etext = .;
+        
+    
+    /* DATA section for RamPeriph32 */
+    .data_RAM2 : ALIGN(4)
+    {
+       FILL(0xff)
+    	*(.data.$RAM2*)
+    	*(.data.$RamPeriph32*)
+       . = ALIGN(4) ;
+    } > RamPeriph32 AT>MFlash512
+    
+    /* MAIN DATA SECTION */
+    
+
+    .uninit_RESERVED : ALIGN(4)
+    {
+        KEEP(*(.bss.$RESERVED*))
+        . = ALIGN(4) ;
+        _end_uninit_RESERVED = .;
+    } > RamLoc64
+
+    .data : ALIGN(4)
+    {
+        FILL(0xff)
+        _data = .;
+        *(vtable)
+        *(.data*)
+        . = ALIGN(4) ;
+        _edata = .;
+    } > RamLoc64 AT>MFlash512
+
+    /* BSS section for RamPeriph32 */
+    .bss_RAM2 : ALIGN(4)
+    {
+    	*(.bss.$RAM2*)
+    	*(.bss.$RamPeriph32*)
+       . = ALIGN(4) ;
+    } > RamPeriph32
+
+    /* MAIN BSS SECTION */
+    .bss : ALIGN(4)
+    {
+        _bss = .;
+        *(.bss*)
+        *(COMMON)
+        . = ALIGN(4) ;
+        _ebss = .;
+        PROVIDE(end = .);
+    } > RamLoc64
+        
+    /* NOINIT section for RamPeriph32 */
+    .noinit_RAM2 (NOLOAD) : ALIGN(4)
+    {
+    	*(.noinit.$RAM2*)
+    	*(.noinit.$RamPeriph32*)
+       . = ALIGN(4) ;
+    } > RamPeriph32 
+    
+    /* DEFAULT NOINIT SECTION */
+    .noinit (NOLOAD): ALIGN(4)
+    {
+        _noinit = .;
+        *(.noinit*) 
+         . = ALIGN(4) ;
+        _end_noinit = .;
+    } > RamLoc64
+    
+    PROVIDE(_pvHeapStart = .);
+    PROVIDE(_vStackTop = __top_RamLoc64 - 0);
+}