meh
Fork of mbed by
Diff: TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h
- Revision:
- 85:024bf7f99721
- Parent:
- 81:7d30d6019079
- Child:
- 90:cb3d968589d8
--- a/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h Mon May 19 18:14:09 2014 +0100 +++ b/TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h Wed Jun 11 15:14:05 2014 +0100 @@ -2,8 +2,8 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.h * @author MCD Application Team - * @version V1.0.0 - * @date 18-February-2014 + * @version V1.1.0RC2 + * @date 14-May-2014 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -61,8 +61,8 @@ */ typedef struct { - uint32_t InjectedChannel; /*!< Configure the ADC injected channel - This parameter can be a value of @ref ADC_channels. */ + uint32_t InjectedChannel; /*!< Configure the ADC injected channel. + This parameter can be a value of @ref ADC_channels */ uint32_t InjectedRank; /*!< The rank in the injected group sequencer This parameter must be a number between Min_Data = 1 and Max_Data = 4. */ uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel. @@ -77,9 +77,9 @@ uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels. This parameter can be set to ENABLE or DISABLE. */ uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels. - This parameter can be a value of @ref ADC_External_trigger_Source_Injected. */ + This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected */ uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels. - This parameter can be a value of @ref ADC_External_trigger_Source_Injected */ + This parameter can be a value of @ref ADCEx_External_trigger_Source_Injected */ }ADC_InjectionConfTypeDef; /** @@ -88,11 +88,11 @@ typedef struct { uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode. - This parameter can be a value of @ref ADC_Common_mode */ + This parameter can be a value of @ref ADCEx_Common_mode */ uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode. - This parameter can be a value of @ref ADC_Direct_memory_access_mode_for_multi_mode */ + This parameter can be a value of @ref ADCEx_Direct_memory_access_mode_for_multi_mode */ uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases. - This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */ + This parameter can be a value of @ref ADCEx_delay_between_2_sampling_phases */ }ADC_MultiModeTypeDef; /* Exported constants --------------------------------------------------------*/ @@ -152,6 +152,46 @@ * @} */ + /** @defgroup ADCEx_delay_between_2_sampling_phases + * @{ + */ +#define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000) +#define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0) +#define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1) +#define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2) +#define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3) +#define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2)) +#define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0)) +#define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1)) +#define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY) + +#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \ + ((DELAY) == ADC_TWOSAMPLINGDELAY_20CYCLES)) +/** + * @} + */ + /** @defgroup ADCEx_External_trigger_edge_Injected * @{ */