Ricardo Benitez / mbed

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TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:
Kojto
Date:
Wed May 13 08:08:21 2015 +0200
Revision:
99:dbbf35b96557
Parent:
98:8ab26030e058
Child:
106:ba1f97679dad
Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_rcc.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 99:dbbf35b96557 5 * @version V1.3.0
Kojto 99:dbbf35b96557 6 * @date 09-March-2015
emilmont 77:869cf507173a 7 * @brief Header file of RCC HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_RCC_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_RCC_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
Kojto 99:dbbf35b96557 49 /* Include RCC HAL Extended module */
Kojto 99:dbbf35b96557 50 /* (include on top of file since RCC structures are defined in extended file) */
Kojto 99:dbbf35b96557 51 #include "stm32f4xx_hal_rcc_ex.h"
Kojto 99:dbbf35b96557 52
emilmont 77:869cf507173a 53 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
Kojto 99:dbbf35b96557 57 /** @addtogroup RCC
emilmont 77:869cf507173a 58 * @{
emilmont 77:869cf507173a 59 */
emilmont 77:869cf507173a 60
Kojto 99:dbbf35b96557 61 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 62 /** @defgroup RCC_Exported_Types RCC Exported Types
Kojto 99:dbbf35b96557 63 * @{
emilmont 77:869cf507173a 64 */
Kojto 99:dbbf35b96557 65
emilmont 77:869cf507173a 66 /**
emilmont 77:869cf507173a 67 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
emilmont 77:869cf507173a 68 */
emilmont 77:869cf507173a 69 typedef struct
emilmont 77:869cf507173a 70 {
emilmont 77:869cf507173a 71 uint32_t OscillatorType; /*!< The oscillators to be configured.
emilmont 77:869cf507173a 72 This parameter can be a value of @ref RCC_Oscillator_Type */
emilmont 77:869cf507173a 73
emilmont 77:869cf507173a 74 uint32_t HSEState; /*!< The new state of the HSE.
emilmont 77:869cf507173a 75 This parameter can be a value of @ref RCC_HSE_Config */
emilmont 77:869cf507173a 76
emilmont 77:869cf507173a 77 uint32_t LSEState; /*!< The new state of the LSE.
emilmont 77:869cf507173a 78 This parameter can be a value of @ref RCC_LSE_Config */
emilmont 77:869cf507173a 79
emilmont 77:869cf507173a 80 uint32_t HSIState; /*!< The new state of the HSI.
emilmont 77:869cf507173a 81 This parameter can be a value of @ref RCC_HSI_Config */
emilmont 77:869cf507173a 82
emilmont 77:869cf507173a 83 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
emilmont 77:869cf507173a 84 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
emilmont 77:869cf507173a 85
emilmont 77:869cf507173a 86 uint32_t LSIState; /*!< The new state of the LSI.
emilmont 77:869cf507173a 87 This parameter can be a value of @ref RCC_LSI_Config */
emilmont 77:869cf507173a 88
emilmont 77:869cf507173a 89 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
emilmont 77:869cf507173a 90
emilmont 77:869cf507173a 91 }RCC_OscInitTypeDef;
emilmont 77:869cf507173a 92
emilmont 77:869cf507173a 93 /**
emilmont 77:869cf507173a 94 * @brief RCC System, AHB and APB busses clock configuration structure definition
emilmont 77:869cf507173a 95 */
emilmont 77:869cf507173a 96 typedef struct
emilmont 77:869cf507173a 97 {
emilmont 77:869cf507173a 98 uint32_t ClockType; /*!< The clock to be configured.
emilmont 77:869cf507173a 99 This parameter can be a value of @ref RCC_System_Clock_Type */
emilmont 77:869cf507173a 100
emilmont 77:869cf507173a 101 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
emilmont 77:869cf507173a 102 This parameter can be a value of @ref RCC_System_Clock_Source */
emilmont 77:869cf507173a 103
emilmont 77:869cf507173a 104 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
emilmont 77:869cf507173a 105 This parameter can be a value of @ref RCC_AHB_Clock_Source */
emilmont 77:869cf507173a 106
emilmont 77:869cf507173a 107 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
emilmont 77:869cf507173a 108 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
emilmont 77:869cf507173a 111 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
emilmont 77:869cf507173a 112
emilmont 77:869cf507173a 113 }RCC_ClkInitTypeDef;
emilmont 77:869cf507173a 114
emilmont 77:869cf507173a 115 /**
emilmont 77:869cf507173a 116 * @}
emilmont 77:869cf507173a 117 */
emilmont 77:869cf507173a 118
Kojto 99:dbbf35b96557 119 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 120 /** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto 99:dbbf35b96557 121 * @{
Kojto 99:dbbf35b96557 122 */
Kojto 99:dbbf35b96557 123
Kojto 99:dbbf35b96557 124 /** @defgroup RCC_Oscillator_Type Oscillator Type
emilmont 77:869cf507173a 125 * @{
emilmont 77:869cf507173a 126 */
bogdanm 81:7d30d6019079 127 #define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
emilmont 77:869cf507173a 128 #define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
emilmont 77:869cf507173a 129 #define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
emilmont 77:869cf507173a 130 #define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
emilmont 77:869cf507173a 131 #define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
emilmont 77:869cf507173a 132 /**
emilmont 77:869cf507173a 133 * @}
emilmont 77:869cf507173a 134 */
emilmont 77:869cf507173a 135
Kojto 99:dbbf35b96557 136 /** @defgroup RCC_HSE_Config HSE Config
emilmont 77:869cf507173a 137 * @{
emilmont 77:869cf507173a 138 */
emilmont 77:869cf507173a 139 #define RCC_HSE_OFF ((uint8_t)0x00)
emilmont 77:869cf507173a 140 #define RCC_HSE_ON ((uint8_t)0x01)
emilmont 77:869cf507173a 141 #define RCC_HSE_BYPASS ((uint8_t)0x05)
emilmont 77:869cf507173a 142 /**
emilmont 77:869cf507173a 143 * @}
emilmont 77:869cf507173a 144 */
emilmont 77:869cf507173a 145
Kojto 99:dbbf35b96557 146 /** @defgroup RCC_LSE_Config LSE Config
emilmont 77:869cf507173a 147 * @{
emilmont 77:869cf507173a 148 */
emilmont 77:869cf507173a 149 #define RCC_LSE_OFF ((uint8_t)0x00)
emilmont 77:869cf507173a 150 #define RCC_LSE_ON ((uint8_t)0x01)
emilmont 77:869cf507173a 151 #define RCC_LSE_BYPASS ((uint8_t)0x05)
emilmont 77:869cf507173a 152 /**
emilmont 77:869cf507173a 153 * @}
emilmont 77:869cf507173a 154 */
emilmont 77:869cf507173a 155
Kojto 99:dbbf35b96557 156 /** @defgroup RCC_HSI_Config HSI Config
emilmont 77:869cf507173a 157 * @{
emilmont 77:869cf507173a 158 */
emilmont 77:869cf507173a 159 #define RCC_HSI_OFF ((uint8_t)0x00)
emilmont 77:869cf507173a 160 #define RCC_HSI_ON ((uint8_t)0x01)
emilmont 77:869cf507173a 161 /**
emilmont 77:869cf507173a 162 * @}
emilmont 77:869cf507173a 163 */
emilmont 77:869cf507173a 164
Kojto 99:dbbf35b96557 165 /** @defgroup RCC_LSI_Config LSI Config
emilmont 77:869cf507173a 166 * @{
emilmont 77:869cf507173a 167 */
emilmont 77:869cf507173a 168 #define RCC_LSI_OFF ((uint8_t)0x00)
emilmont 77:869cf507173a 169 #define RCC_LSI_ON ((uint8_t)0x01)
emilmont 77:869cf507173a 170 /**
emilmont 77:869cf507173a 171 * @}
emilmont 77:869cf507173a 172 */
emilmont 77:869cf507173a 173
Kojto 99:dbbf35b96557 174 /** @defgroup RCC_PLL_Config PLL Config
emilmont 77:869cf507173a 175 * @{
emilmont 77:869cf507173a 176 */
emilmont 77:869cf507173a 177 #define RCC_PLL_NONE ((uint8_t)0x00)
emilmont 77:869cf507173a 178 #define RCC_PLL_OFF ((uint8_t)0x01)
emilmont 77:869cf507173a 179 #define RCC_PLL_ON ((uint8_t)0x02)
emilmont 77:869cf507173a 180 /**
emilmont 77:869cf507173a 181 * @}
emilmont 77:869cf507173a 182 */
emilmont 77:869cf507173a 183
Kojto 99:dbbf35b96557 184 /** @defgroup RCC_PLLP_Clock_Divider PLLP Clock Divider
emilmont 77:869cf507173a 185 * @{
emilmont 77:869cf507173a 186 */
emilmont 77:869cf507173a 187 #define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 188 #define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 189 #define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
emilmont 77:869cf507173a 190 #define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 191 /**
emilmont 77:869cf507173a 192 * @}
emilmont 77:869cf507173a 193 */
emilmont 77:869cf507173a 194
Kojto 99:dbbf35b96557 195 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
emilmont 77:869cf507173a 196 * @{
emilmont 77:869cf507173a 197 */
emilmont 77:869cf507173a 198 #define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
emilmont 77:869cf507173a 199 #define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
emilmont 77:869cf507173a 200 /**
emilmont 77:869cf507173a 201 * @}
emilmont 77:869cf507173a 202 */
emilmont 77:869cf507173a 203
Kojto 99:dbbf35b96557 204 /** @defgroup RCC_System_Clock_Type System Clock Type
emilmont 77:869cf507173a 205 * @{
emilmont 77:869cf507173a 206 */
emilmont 77:869cf507173a 207 #define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
emilmont 77:869cf507173a 208 #define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
emilmont 77:869cf507173a 209 #define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 210 #define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 211 /**
emilmont 77:869cf507173a 212 * @}
emilmont 77:869cf507173a 213 */
emilmont 77:869cf507173a 214
Kojto 99:dbbf35b96557 215 /** @defgroup RCC_System_Clock_Source System Clock Source
emilmont 77:869cf507173a 216 * @{
emilmont 77:869cf507173a 217 */
emilmont 77:869cf507173a 218 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
emilmont 77:869cf507173a 219 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
emilmont 77:869cf507173a 220 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto 99:dbbf35b96557 221 #define RCC_SYSCLKSOURCE_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1))
emilmont 77:869cf507173a 222 /**
emilmont 77:869cf507173a 223 * @}
Kojto 99:dbbf35b96557 224 */
emilmont 77:869cf507173a 225
Kojto 99:dbbf35b96557 226 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
Kojto 99:dbbf35b96557 227 * @{
Kojto 99:dbbf35b96557 228 */
Kojto 99:dbbf35b96557 229 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
Kojto 99:dbbf35b96557 230 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
Kojto 99:dbbf35b96557 231 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
Kojto 99:dbbf35b96557 232 #define RCC_SYSCLKSOURCE_STATUS_PLLRCLK ((uint32_t)(RCC_CFGR_SW_0 | RCC_CFGR_SW_1)) /*!< PLLR used as system clock */
Kojto 99:dbbf35b96557 233 /**
Kojto 99:dbbf35b96557 234 * @}
Kojto 99:dbbf35b96557 235 */
Kojto 99:dbbf35b96557 236
Kojto 99:dbbf35b96557 237 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
emilmont 77:869cf507173a 238 * @{
emilmont 77:869cf507173a 239 */
emilmont 77:869cf507173a 240 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
emilmont 77:869cf507173a 241 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
emilmont 77:869cf507173a 242 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
emilmont 77:869cf507173a 243 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
emilmont 77:869cf507173a 244 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
emilmont 77:869cf507173a 245 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
emilmont 77:869cf507173a 246 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
emilmont 77:869cf507173a 247 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
emilmont 77:869cf507173a 248 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
emilmont 77:869cf507173a 249 /**
emilmont 77:869cf507173a 250 * @}
emilmont 77:869cf507173a 251 */
emilmont 77:869cf507173a 252
Kojto 99:dbbf35b96557 253 /** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
emilmont 77:869cf507173a 254 * @{
emilmont 77:869cf507173a 255 */
emilmont 77:869cf507173a 256 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
emilmont 77:869cf507173a 257 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
emilmont 77:869cf507173a 258 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
emilmont 77:869cf507173a 259 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
emilmont 77:869cf507173a 260 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
emilmont 77:869cf507173a 261 /**
emilmont 77:869cf507173a 262 * @}
emilmont 77:869cf507173a 263 */
emilmont 77:869cf507173a 264
Kojto 99:dbbf35b96557 265 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
emilmont 77:869cf507173a 266 * @{
emilmont 77:869cf507173a 267 */
emilmont 77:869cf507173a 268 #define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
emilmont 77:869cf507173a 269 #define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
emilmont 77:869cf507173a 270 #define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
emilmont 77:869cf507173a 271 #define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
emilmont 77:869cf507173a 272 #define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
emilmont 77:869cf507173a 273 #define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
emilmont 77:869cf507173a 274 #define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
emilmont 77:869cf507173a 275 #define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
emilmont 77:869cf507173a 276 #define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
emilmont 77:869cf507173a 277 #define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
emilmont 77:869cf507173a 278 #define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
emilmont 77:869cf507173a 279 #define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
emilmont 77:869cf507173a 280 #define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
emilmont 77:869cf507173a 281 #define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
emilmont 77:869cf507173a 282 #define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
emilmont 77:869cf507173a 283 #define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
emilmont 77:869cf507173a 284 #define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
emilmont 77:869cf507173a 285 #define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
emilmont 77:869cf507173a 286 #define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
emilmont 77:869cf507173a 287 #define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
emilmont 77:869cf507173a 288 #define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
emilmont 77:869cf507173a 289 #define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
emilmont 77:869cf507173a 290 #define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
emilmont 77:869cf507173a 291 #define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
emilmont 77:869cf507173a 292 #define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
emilmont 77:869cf507173a 293 #define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
emilmont 77:869cf507173a 294 #define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
emilmont 77:869cf507173a 295 #define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
emilmont 77:869cf507173a 296 #define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
emilmont 77:869cf507173a 297 #define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
emilmont 77:869cf507173a 298 #define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
emilmont 77:869cf507173a 299 #define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
emilmont 77:869cf507173a 300 /**
emilmont 77:869cf507173a 301 * @}
emilmont 77:869cf507173a 302 */
emilmont 77:869cf507173a 303
Kojto 99:dbbf35b96557 304 /** @defgroup RCC_I2S_Clock_Source I2S Clock Source
emilmont 77:869cf507173a 305 * @{
emilmont 77:869cf507173a 306 */
emilmont 77:869cf507173a 307 #define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
emilmont 77:869cf507173a 308 #define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
emilmont 77:869cf507173a 309 /**
emilmont 77:869cf507173a 310 * @}
emilmont 77:869cf507173a 311 */
emilmont 77:869cf507173a 312
Kojto 99:dbbf35b96557 313 /** @defgroup RCC_MCO_Index MCO Index
emilmont 77:869cf507173a 314 * @{
emilmont 77:869cf507173a 315 */
emilmont 77:869cf507173a 316 #define RCC_MCO1 ((uint32_t)0x00000000)
emilmont 77:869cf507173a 317 #define RCC_MCO2 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 318 /**
emilmont 77:869cf507173a 319 * @}
emilmont 77:869cf507173a 320 */
emilmont 77:869cf507173a 321
Kojto 99:dbbf35b96557 322 /** @defgroup RCC_MCO1_Clock_Source MCO1 Clock Source
emilmont 77:869cf507173a 323 * @{
emilmont 77:869cf507173a 324 */
emilmont 77:869cf507173a 325 #define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
emilmont 77:869cf507173a 326 #define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
emilmont 77:869cf507173a 327 #define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
emilmont 77:869cf507173a 328 #define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
emilmont 77:869cf507173a 329 /**
emilmont 77:869cf507173a 330 * @}
emilmont 77:869cf507173a 331 */
emilmont 77:869cf507173a 332
Kojto 99:dbbf35b96557 333 /** @defgroup RCC_MCO2_Clock_Source MCO2 Clock Source
emilmont 77:869cf507173a 334 * @{
emilmont 77:869cf507173a 335 */
emilmont 77:869cf507173a 336 #define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
emilmont 77:869cf507173a 337 #define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
emilmont 77:869cf507173a 338 #define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
emilmont 77:869cf507173a 339 #define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
emilmont 77:869cf507173a 340 /**
emilmont 77:869cf507173a 341 * @}
emilmont 77:869cf507173a 342 */
emilmont 77:869cf507173a 343
Kojto 99:dbbf35b96557 344 /** @defgroup RCC_MCOx_Clock_Prescaler MCOx Clock Prescaler
emilmont 77:869cf507173a 345 * @{
emilmont 77:869cf507173a 346 */
emilmont 77:869cf507173a 347 #define RCC_MCODIV_1 ((uint32_t)0x00000000)
emilmont 77:869cf507173a 348 #define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
emilmont 77:869cf507173a 349 #define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
emilmont 77:869cf507173a 350 #define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
emilmont 77:869cf507173a 351 #define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
emilmont 77:869cf507173a 352 /**
emilmont 77:869cf507173a 353 * @}
emilmont 77:869cf507173a 354 */
emilmont 77:869cf507173a 355
Kojto 99:dbbf35b96557 356 /** @defgroup RCC_Interrupt Interrupts
emilmont 77:869cf507173a 357 * @{
emilmont 77:869cf507173a 358 */
emilmont 77:869cf507173a 359 #define RCC_IT_LSIRDY ((uint8_t)0x01)
emilmont 77:869cf507173a 360 #define RCC_IT_LSERDY ((uint8_t)0x02)
emilmont 77:869cf507173a 361 #define RCC_IT_HSIRDY ((uint8_t)0x04)
emilmont 77:869cf507173a 362 #define RCC_IT_HSERDY ((uint8_t)0x08)
emilmont 77:869cf507173a 363 #define RCC_IT_PLLRDY ((uint8_t)0x10)
emilmont 77:869cf507173a 364 #define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
emilmont 77:869cf507173a 365 #define RCC_IT_CSS ((uint8_t)0x80)
emilmont 77:869cf507173a 366 /**
emilmont 77:869cf507173a 367 * @}
emilmont 77:869cf507173a 368 */
emilmont 77:869cf507173a 369
Kojto 99:dbbf35b96557 370 /** @defgroup RCC_Flag Flags
emilmont 77:869cf507173a 371 * Elements values convention: 0XXYYYYYb
emilmont 77:869cf507173a 372 * - YYYYY : Flag position in the register
emilmont 77:869cf507173a 373 * - 0XX : Register index
emilmont 77:869cf507173a 374 * - 01: CR register
emilmont 77:869cf507173a 375 * - 10: BDCR register
emilmont 77:869cf507173a 376 * - 11: CSR register
emilmont 77:869cf507173a 377 * @{
emilmont 77:869cf507173a 378 */
emilmont 77:869cf507173a 379 /* Flags in the CR register */
emilmont 77:869cf507173a 380 #define RCC_FLAG_HSIRDY ((uint8_t)0x21)
emilmont 77:869cf507173a 381 #define RCC_FLAG_HSERDY ((uint8_t)0x31)
emilmont 77:869cf507173a 382 #define RCC_FLAG_PLLRDY ((uint8_t)0x39)
emilmont 77:869cf507173a 383 #define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
emilmont 77:869cf507173a 384
emilmont 77:869cf507173a 385 /* Flags in the BDCR register */
emilmont 77:869cf507173a 386 #define RCC_FLAG_LSERDY ((uint8_t)0x41)
emilmont 77:869cf507173a 387
emilmont 77:869cf507173a 388 /* Flags in the CSR register */
emilmont 77:869cf507173a 389 #define RCC_FLAG_LSIRDY ((uint8_t)0x61)
emilmont 77:869cf507173a 390 #define RCC_FLAG_BORRST ((uint8_t)0x79)
emilmont 77:869cf507173a 391 #define RCC_FLAG_PINRST ((uint8_t)0x7A)
emilmont 77:869cf507173a 392 #define RCC_FLAG_PORRST ((uint8_t)0x7B)
emilmont 77:869cf507173a 393 #define RCC_FLAG_SFTRST ((uint8_t)0x7C)
emilmont 77:869cf507173a 394 #define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
emilmont 77:869cf507173a 395 #define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
emilmont 77:869cf507173a 396 #define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
emilmont 77:869cf507173a 397 /**
emilmont 77:869cf507173a 398 * @}
emilmont 77:869cf507173a 399 */
emilmont 77:869cf507173a 400
emilmont 77:869cf507173a 401 /**
emilmont 77:869cf507173a 402 * @}
Kojto 99:dbbf35b96557 403 */
Kojto 99:dbbf35b96557 404
emilmont 77:869cf507173a 405 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 406 /** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto 99:dbbf35b96557 407 * @{
Kojto 99:dbbf35b96557 408 */
emilmont 77:869cf507173a 409
Kojto 99:dbbf35b96557 410 /** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 411 * @brief Enable or disable the AHB1 peripheral clock.
emilmont 77:869cf507173a 412 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 413 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 414 * using it.
Kojto 99:dbbf35b96557 415 * @{
emilmont 77:869cf507173a 416 */
Kojto 99:dbbf35b96557 417 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 418 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 419 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 99:dbbf35b96557 420 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 421 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOAEN);\
Kojto 99:dbbf35b96557 422 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 423 } while(0)
Kojto 99:dbbf35b96557 424 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 425 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 426 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 99:dbbf35b96557 427 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 428 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOBEN);\
Kojto 99:dbbf35b96557 429 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 430 } while(0)
Kojto 99:dbbf35b96557 431 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 432 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 433 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 99:dbbf35b96557 434 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 435 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOCEN);\
Kojto 99:dbbf35b96557 436 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 437 } while(0)
Kojto 99:dbbf35b96557 438 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 439 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 440 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto 99:dbbf35b96557 441 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 442 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIODEN);\
Kojto 99:dbbf35b96557 443 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 444 } while(0)
Kojto 99:dbbf35b96557 445 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 446 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 447 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto 99:dbbf35b96557 448 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 449 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOEEN);\
Kojto 99:dbbf35b96557 450 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 451 } while(0)
Kojto 99:dbbf35b96557 452 #define __HAL_RCC_GPIOH_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 453 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 454 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 99:dbbf35b96557 455 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 456 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOHEN);\
Kojto 99:dbbf35b96557 457 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 458 } while(0)
Kojto 99:dbbf35b96557 459 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 460 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 461 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto 99:dbbf35b96557 462 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 463 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CRCEN);\
Kojto 99:dbbf35b96557 464 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 465 } while(0)
Kojto 99:dbbf35b96557 466 #define __HAL_RCC_BKPSRAM_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 467 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 468 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto 99:dbbf35b96557 469 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 470 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_BKPSRAMEN);\
Kojto 99:dbbf35b96557 471 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 472 } while(0)
Kojto 99:dbbf35b96557 473 #define __HAL_RCC_CCMDATARAMEN_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 474 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 475 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto 99:dbbf35b96557 476 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 477 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_CCMDATARAMEN);\
Kojto 99:dbbf35b96557 478 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 479 } while(0)
Kojto 99:dbbf35b96557 480 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 481 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 482 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 99:dbbf35b96557 483 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 484 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA1EN);\
Kojto 99:dbbf35b96557 485 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 486 } while(0)
Kojto 99:dbbf35b96557 487 #define __HAL_RCC_DMA2_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 488 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 489 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 99:dbbf35b96557 490 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 491 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2EN);\
Kojto 99:dbbf35b96557 492 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 493 } while(0)
emilmont 77:869cf507173a 494
Kojto 99:dbbf35b96557 495 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
Kojto 99:dbbf35b96557 496 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
Kojto 99:dbbf35b96557 497 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
Kojto 99:dbbf35b96557 498 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
Kojto 99:dbbf35b96557 499 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
Kojto 99:dbbf35b96557 500 #define __HAL_RCC_GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
Kojto 99:dbbf35b96557 501 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
Kojto 99:dbbf35b96557 502 #define __HAL_RCC_BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
Kojto 99:dbbf35b96557 503 #define __HAL_RCC_CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
Kojto 99:dbbf35b96557 504 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
Kojto 99:dbbf35b96557 505 #define __HAL_RCC_DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
emilmont 77:869cf507173a 506
Kojto 99:dbbf35b96557 507 /**
Kojto 99:dbbf35b96557 508 * @}
Kojto 99:dbbf35b96557 509 */
Kojto 99:dbbf35b96557 510
Kojto 99:dbbf35b96557 511 /** @defgroup RCC_AHB2_Clock_Enable_Disable AHB2 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 512 * @brief Enable or disable the AHB2 peripheral clock.
emilmont 77:869cf507173a 513 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 514 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 515 * using it.
Kojto 99:dbbf35b96557 516 * @{
emilmont 77:869cf507173a 517 */
Kojto 99:dbbf35b96557 518 #define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR |= (RCC_AHB2ENR_OTGFSEN));\
Kojto 99:dbbf35b96557 519 __HAL_RCC_SYSCFG_CLK_ENABLE();\
Kojto 99:dbbf35b96557 520 }while(0)
emilmont 77:869cf507173a 521
Kojto 99:dbbf35b96557 522 #define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
Kojto 99:dbbf35b96557 523 __HAL_RCC_SYSCFG_CLK_DISABLE();\
Kojto 99:dbbf35b96557 524 }while(0)
emilmont 77:869cf507173a 525
Kojto 99:dbbf35b96557 526 #define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHB2ENR |= (RCC_AHB2ENR_RNGEN))
Kojto 99:dbbf35b96557 527 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
emilmont 77:869cf507173a 528
Kojto 99:dbbf35b96557 529 /**
Kojto 99:dbbf35b96557 530 * @}
Kojto 99:dbbf35b96557 531 */
Kojto 99:dbbf35b96557 532
Kojto 99:dbbf35b96557 533 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 534 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
emilmont 77:869cf507173a 535 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 536 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 537 * using it.
Kojto 99:dbbf35b96557 538 * @{
emilmont 77:869cf507173a 539 */
Kojto 99:dbbf35b96557 540 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 541 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 542 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto 99:dbbf35b96557 543 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 544 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
Kojto 99:dbbf35b96557 545 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 546 } while(0)
Kojto 99:dbbf35b96557 547 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 548 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 549 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 99:dbbf35b96557 550 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 551 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
Kojto 99:dbbf35b96557 552 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 553 } while(0)
Kojto 99:dbbf35b96557 554 #define __HAL_RCC_TIM4_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 555 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 556 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 99:dbbf35b96557 557 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 558 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM4EN);\
Kojto 99:dbbf35b96557 559 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 560 } while(0)
Kojto 99:dbbf35b96557 561 #define __HAL_RCC_TIM5_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 562 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 563 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 99:dbbf35b96557 564 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 565 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM5EN);\
Kojto 99:dbbf35b96557 566 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 567 } while(0)
Kojto 99:dbbf35b96557 568 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 569 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 570 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 99:dbbf35b96557 571 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 572 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
Kojto 99:dbbf35b96557 573 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 574 } while(0)
Kojto 99:dbbf35b96557 575 #define __HAL_RCC_SPI2_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 576 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 577 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 99:dbbf35b96557 578 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 579 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI2EN);\
Kojto 99:dbbf35b96557 580 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 581 } while(0)
Kojto 99:dbbf35b96557 582 #define __HAL_RCC_SPI3_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 583 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 584 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 99:dbbf35b96557 585 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 586 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPI3EN);\
Kojto 99:dbbf35b96557 587 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 588 } while(0)
Kojto 99:dbbf35b96557 589 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 590 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 591 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 99:dbbf35b96557 592 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 593 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
Kojto 99:dbbf35b96557 594 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 595 } while(0)
Kojto 99:dbbf35b96557 596 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 597 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 598 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 99:dbbf35b96557 599 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 600 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
Kojto 99:dbbf35b96557 601 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 602 } while(0)
Kojto 99:dbbf35b96557 603 #define __HAL_RCC_I2C2_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 604 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 605 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 99:dbbf35b96557 606 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 607 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C2EN);\
Kojto 99:dbbf35b96557 608 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 609 } while(0)
Kojto 99:dbbf35b96557 610 #define __HAL_RCC_I2C3_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 611 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 612 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 99:dbbf35b96557 613 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 614 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C3EN);\
Kojto 99:dbbf35b96557 615 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 616 } while(0)
Kojto 99:dbbf35b96557 617 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 618 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 619 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 99:dbbf35b96557 620 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 621 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
Kojto 99:dbbf35b96557 622 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 623 } while(0)
Kojto 99:dbbf35b96557 624 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto 99:dbbf35b96557 625 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 99:dbbf35b96557 626 #define __HAL_RCC_TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 99:dbbf35b96557 627 #define __HAL_RCC_TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 99:dbbf35b96557 628 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto 99:dbbf35b96557 629 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 99:dbbf35b96557 630 #define __HAL_RCC_SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 99:dbbf35b96557 631 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 99:dbbf35b96557 632 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto 99:dbbf35b96557 633 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 99:dbbf35b96557 634 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto 99:dbbf35b96557 635 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto 99:dbbf35b96557 636 /**
Kojto 99:dbbf35b96557 637 * @}
Kojto 99:dbbf35b96557 638 */
emilmont 77:869cf507173a 639
Kojto 99:dbbf35b96557 640 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
Kojto 99:dbbf35b96557 641 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
emilmont 77:869cf507173a 642 * @note After reset, the peripheral clock (used for registers read/write access)
emilmont 77:869cf507173a 643 * is disabled and the application software has to enable this clock before
emilmont 77:869cf507173a 644 * using it.
Kojto 99:dbbf35b96557 645 * @{
emilmont 77:869cf507173a 646 */
Kojto 99:dbbf35b96557 647 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 648 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 649 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 99:dbbf35b96557 650 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 651 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
Kojto 99:dbbf35b96557 652 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 653 } while(0)
Kojto 99:dbbf35b96557 654 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 655 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 656 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 99:dbbf35b96557 657 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 658 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
Kojto 99:dbbf35b96557 659 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 660 } while(0)
Kojto 99:dbbf35b96557 661 #define __HAL_RCC_USART6_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 662 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 663 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 99:dbbf35b96557 664 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 665 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART6EN);\
Kojto 99:dbbf35b96557 666 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 667 } while(0)
Kojto 99:dbbf35b96557 668 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 669 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 670 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 99:dbbf35b96557 671 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 672 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
Kojto 99:dbbf35b96557 673 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 674 } while(0)
Kojto 99:dbbf35b96557 675 #define __HAL_RCC_SDIO_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 676 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 677 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto 99:dbbf35b96557 678 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 679 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SDIOEN);\
Kojto 99:dbbf35b96557 680 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 681 } while(0)
Kojto 99:dbbf35b96557 682 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 683 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 684 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 99:dbbf35b96557 685 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 686 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
Kojto 99:dbbf35b96557 687 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 688 } while(0)
Kojto 99:dbbf35b96557 689 #define __HAL_RCC_SPI4_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 690 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 691 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 99:dbbf35b96557 692 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 693 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI4EN);\
Kojto 99:dbbf35b96557 694 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 695 } while(0)
Kojto 99:dbbf35b96557 696 #define __HAL_RCC_SYSCFG_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 697 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 698 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 99:dbbf35b96557 699 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 700 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SYSCFGEN);\
Kojto 99:dbbf35b96557 701 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 702 } while(0)
Kojto 99:dbbf35b96557 703 #define __HAL_RCC_TIM9_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 704 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 705 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 99:dbbf35b96557 706 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 707 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM9EN);\
Kojto 99:dbbf35b96557 708 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 709 } while(0)
Kojto 99:dbbf35b96557 710 #define __HAL_RCC_TIM10_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 711 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 712 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 99:dbbf35b96557 713 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 714 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM10EN);\
Kojto 99:dbbf35b96557 715 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 716 } while(0)
Kojto 99:dbbf35b96557 717 #define __HAL_RCC_TIM11_CLK_ENABLE() do { \
Kojto 99:dbbf35b96557 718 __IO uint32_t tmpreg; \
Kojto 99:dbbf35b96557 719 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 99:dbbf35b96557 720 /* Delay after an RCC peripheral clock enabling */ \
Kojto 99:dbbf35b96557 721 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM11EN);\
Kojto 99:dbbf35b96557 722 UNUSED(tmpreg); \
Kojto 99:dbbf35b96557 723 } while(0)
emilmont 77:869cf507173a 724
Kojto 99:dbbf35b96557 725 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 99:dbbf35b96557 726 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto 99:dbbf35b96557 727 #define __HAL_RCC_USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 99:dbbf35b96557 728 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 99:dbbf35b96557 729 #define __HAL_RCC_SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
Kojto 99:dbbf35b96557 730 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 99:dbbf35b96557 731 #define __HAL_RCC_SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto 99:dbbf35b96557 732 #define __HAL_RCC_SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto 99:dbbf35b96557 733 #define __HAL_RCC_TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto 99:dbbf35b96557 734 #define __HAL_RCC_TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto 99:dbbf35b96557 735 #define __HAL_RCC_TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto 99:dbbf35b96557 736 /**
Kojto 99:dbbf35b96557 737 * @}
Kojto 99:dbbf35b96557 738 */
emilmont 77:869cf507173a 739
Kojto 99:dbbf35b96557 740 /** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
Kojto 99:dbbf35b96557 741 * @brief Force or release AHB1 peripheral reset.
Kojto 99:dbbf35b96557 742 * @{
emilmont 77:869cf507173a 743 */
Kojto 99:dbbf35b96557 744 #define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
Kojto 99:dbbf35b96557 745 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
Kojto 99:dbbf35b96557 746 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
Kojto 99:dbbf35b96557 747 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOCRST))
Kojto 99:dbbf35b96557 748 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIODRST))
Kojto 99:dbbf35b96557 749 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOERST))
Kojto 99:dbbf35b96557 750 #define __HAL_RCC_GPIOH_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOHRST))
Kojto 99:dbbf35b96557 751 #define __HAL_RCC_CRC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_CRCRST))
Kojto 99:dbbf35b96557 752 #define __HAL_RCC_DMA1_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA1RST))
Kojto 99:dbbf35b96557 753 #define __HAL_RCC_DMA2_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2RST))
emilmont 77:869cf507173a 754
Kojto 99:dbbf35b96557 755 #define __HAL_RCC_AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
Kojto 99:dbbf35b96557 756 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
Kojto 99:dbbf35b96557 757 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
Kojto 99:dbbf35b96557 758 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
Kojto 99:dbbf35b96557 759 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
Kojto 99:dbbf35b96557 760 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
Kojto 99:dbbf35b96557 761 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 99:dbbf35b96557 762 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 99:dbbf35b96557 763 #define __HAL_RCC_GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
Kojto 99:dbbf35b96557 764 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 99:dbbf35b96557 765 #define __HAL_RCC_CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
Kojto 99:dbbf35b96557 766 #define __HAL_RCC_DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
Kojto 99:dbbf35b96557 767 #define __HAL_RCC_DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
Kojto 99:dbbf35b96557 768 /**
Kojto 99:dbbf35b96557 769 * @}
Kojto 99:dbbf35b96557 770 */
emilmont 77:869cf507173a 771
Kojto 99:dbbf35b96557 772 /** @defgroup RCC_AHB2_Force_Release_Reset AHB2 Force Release Reset
Kojto 99:dbbf35b96557 773 * @brief Force or release AHB2 peripheral reset.
Kojto 99:dbbf35b96557 774 * @{
emilmont 77:869cf507173a 775 */
Kojto 99:dbbf35b96557 776 #define __HAL_RCC_AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
Kojto 99:dbbf35b96557 777 #define __HAL_RCC_USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_OTGFSRST))
Kojto 99:dbbf35b96557 778
Kojto 99:dbbf35b96557 779 #define __HAL_RCC_AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
Kojto 99:dbbf35b96557 780 #define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
Kojto 99:dbbf35b96557 781
Kojto 99:dbbf35b96557 782 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_RNGRST))
Kojto 99:dbbf35b96557 783 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
Kojto 99:dbbf35b96557 784 /**
Kojto 99:dbbf35b96557 785 * @}
Kojto 99:dbbf35b96557 786 */
Kojto 99:dbbf35b96557 787
Kojto 99:dbbf35b96557 788 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
Kojto 99:dbbf35b96557 789 * @brief Force or release APB1 peripheral reset.
Kojto 99:dbbf35b96557 790 * @{
Kojto 99:dbbf35b96557 791 */
Kojto 99:dbbf35b96557 792 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto 99:dbbf35b96557 793 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 99:dbbf35b96557 794 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 99:dbbf35b96557 795 #define __HAL_RCC_TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 99:dbbf35b96557 796 #define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 99:dbbf35b96557 797 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
Kojto 99:dbbf35b96557 798 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 99:dbbf35b96557 799 #define __HAL_RCC_SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 99:dbbf35b96557 800 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 99:dbbf35b96557 801 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 99:dbbf35b96557 802 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 99:dbbf35b96557 803 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 99:dbbf35b96557 804 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
emilmont 77:869cf507173a 805
Kojto 99:dbbf35b96557 806 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto 99:dbbf35b96557 807 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto 99:dbbf35b96557 808 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 99:dbbf35b96557 809 #define __HAL_RCC_TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 99:dbbf35b96557 810 #define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 99:dbbf35b96557 811 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto 99:dbbf35b96557 812 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 99:dbbf35b96557 813 #define __HAL_RCC_SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 99:dbbf35b96557 814 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 99:dbbf35b96557 815 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto 99:dbbf35b96557 816 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 99:dbbf35b96557 817 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto 99:dbbf35b96557 818 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto 99:dbbf35b96557 819 /**
Kojto 99:dbbf35b96557 820 * @}
Kojto 99:dbbf35b96557 821 */
emilmont 77:869cf507173a 822
Kojto 99:dbbf35b96557 823 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
Kojto 99:dbbf35b96557 824 * @brief Force or release APB2 peripheral reset.
Kojto 99:dbbf35b96557 825 * @{
emilmont 77:869cf507173a 826 */
Kojto 99:dbbf35b96557 827 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto 99:dbbf35b96557 828 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 99:dbbf35b96557 829 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 99:dbbf35b96557 830 #define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 99:dbbf35b96557 831 #define __HAL_RCC_ADC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADCRST))
Kojto 99:dbbf35b96557 832 #define __HAL_RCC_SDIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
Kojto 99:dbbf35b96557 833 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 99:dbbf35b96557 834 #define __HAL_RCC_SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
Kojto 99:dbbf35b96557 835 #define __HAL_RCC_SYSCFG_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
Kojto 99:dbbf35b96557 836 #define __HAL_RCC_TIM9_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
Kojto 99:dbbf35b96557 837 #define __HAL_RCC_TIM10_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
Kojto 99:dbbf35b96557 838 #define __HAL_RCC_TIM11_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
emilmont 77:869cf507173a 839
Kojto 99:dbbf35b96557 840 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto 99:dbbf35b96557 841 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 99:dbbf35b96557 842 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto 99:dbbf35b96557 843 #define __HAL_RCC_USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 99:dbbf35b96557 844 #define __HAL_RCC_ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
Kojto 99:dbbf35b96557 845 #define __HAL_RCC_SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
Kojto 99:dbbf35b96557 846 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 99:dbbf35b96557 847 #define __HAL_RCC_SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto 99:dbbf35b96557 848 #define __HAL_RCC_SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto 99:dbbf35b96557 849 #define __HAL_RCC_TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto 99:dbbf35b96557 850 #define __HAL_RCC_TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto 99:dbbf35b96557 851 #define __HAL_RCC_TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto 99:dbbf35b96557 852 /**
Kojto 99:dbbf35b96557 853 * @}
Kojto 99:dbbf35b96557 854 */
emilmont 77:869cf507173a 855
Kojto 99:dbbf35b96557 856 /** @defgroup RCC_AHB3_Force_Release_Reset AHB3 Force Release Reset
Kojto 99:dbbf35b96557 857 * @brief Force or release AHB3 peripheral reset.
Kojto 99:dbbf35b96557 858 * @{
Kojto 99:dbbf35b96557 859 */
Kojto 99:dbbf35b96557 860 #define __HAL_RCC_AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
Kojto 99:dbbf35b96557 861 #define __HAL_RCC_AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
Kojto 99:dbbf35b96557 862 /**
Kojto 99:dbbf35b96557 863 * @}
Kojto 99:dbbf35b96557 864 */
emilmont 77:869cf507173a 865
Kojto 99:dbbf35b96557 866 /** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 867 * @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 868 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 869 * power consumption.
Kojto 99:dbbf35b96557 870 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 871 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 872 * @{
emilmont 77:869cf507173a 873 */
Kojto 99:dbbf35b96557 874 #define __HAL_RCC_GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOALPEN))
Kojto 99:dbbf35b96557 875 #define __HAL_RCC_GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOBLPEN))
Kojto 99:dbbf35b96557 876 #define __HAL_RCC_GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOCLPEN))
Kojto 99:dbbf35b96557 877 #define __HAL_RCC_GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIODLPEN))
Kojto 99:dbbf35b96557 878 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOELPEN))
Kojto 99:dbbf35b96557 879 #define __HAL_RCC_GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOHLPEN))
Kojto 99:dbbf35b96557 880 #define __HAL_RCC_CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_CRCLPEN))
Kojto 99:dbbf35b96557 881 #define __HAL_RCC_FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_FLITFLPEN))
Kojto 99:dbbf35b96557 882 #define __HAL_RCC_SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM1LPEN))
Kojto 99:dbbf35b96557 883 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 99:dbbf35b96557 884 #define __HAL_RCC_DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA1LPEN))
Kojto 99:dbbf35b96557 885 #define __HAL_RCC_DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2LPEN))
emilmont 77:869cf507173a 886
Kojto 99:dbbf35b96557 887 #define __HAL_RCC_GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
Kojto 99:dbbf35b96557 888 #define __HAL_RCC_GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
Kojto 99:dbbf35b96557 889 #define __HAL_RCC_GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
Kojto 99:dbbf35b96557 890 #define __HAL_RCC_GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
Kojto 99:dbbf35b96557 891 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
Kojto 99:dbbf35b96557 892 #define __HAL_RCC_GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
Kojto 99:dbbf35b96557 893 #define __HAL_RCC_CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
Kojto 99:dbbf35b96557 894 #define __HAL_RCC_FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
Kojto 99:dbbf35b96557 895 #define __HAL_RCC_SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
Kojto 99:dbbf35b96557 896 #define __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
Kojto 99:dbbf35b96557 897 #define __HAL_RCC_DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
Kojto 99:dbbf35b96557 898 #define __HAL_RCC_DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
Kojto 99:dbbf35b96557 899 /**
Kojto 99:dbbf35b96557 900 * @}
Kojto 99:dbbf35b96557 901 */
emilmont 77:869cf507173a 902
Kojto 99:dbbf35b96557 903 /** @defgroup RCC_AHB2_LowPower_Enable_Disable AHB2 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 904 * @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 905 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 906 * power consumption.
Kojto 99:dbbf35b96557 907 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 908 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 909 * @{
emilmont 77:869cf507173a 910 */
Kojto 99:dbbf35b96557 911 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_OTGFSLPEN))
Kojto 90:cb3d968589d8 912
Kojto 99:dbbf35b96557 913 #define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
emilmont 77:869cf507173a 914
Kojto 99:dbbf35b96557 915 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_RNGLPEN))
Kojto 99:dbbf35b96557 916 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
Kojto 99:dbbf35b96557 917 /**
Kojto 99:dbbf35b96557 918 * @}
Kojto 99:dbbf35b96557 919 */
emilmont 77:869cf507173a 920
Kojto 99:dbbf35b96557 921 /** @defgroup RCC_APB1_LowPower_Enable_Disable APB1 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 922 * @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 923 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 924 * power consumption.
Kojto 99:dbbf35b96557 925 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 926 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 927 * @{
emilmont 77:869cf507173a 928 */
Kojto 99:dbbf35b96557 929 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
Kojto 99:dbbf35b96557 930 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
Kojto 99:dbbf35b96557 931 #define __HAL_RCC_TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
Kojto 99:dbbf35b96557 932 #define __HAL_RCC_TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
Kojto 99:dbbf35b96557 933 #define __HAL_RCC_WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
Kojto 99:dbbf35b96557 934 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
Kojto 99:dbbf35b96557 935 #define __HAL_RCC_SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
Kojto 99:dbbf35b96557 936 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
Kojto 99:dbbf35b96557 937 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
Kojto 99:dbbf35b96557 938 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
Kojto 99:dbbf35b96557 939 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C3LPEN))
Kojto 99:dbbf35b96557 940 #define __HAL_RCC_PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
emilmont 77:869cf507173a 941
Kojto 99:dbbf35b96557 942 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto 99:dbbf35b96557 943 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto 99:dbbf35b96557 944 #define __HAL_RCC_TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto 99:dbbf35b96557 945 #define __HAL_RCC_TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
Kojto 99:dbbf35b96557 946 #define __HAL_RCC_WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto 99:dbbf35b96557 947 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto 99:dbbf35b96557 948 #define __HAL_RCC_SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
Kojto 99:dbbf35b96557 949 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto 99:dbbf35b96557 950 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto 99:dbbf35b96557 951 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto 99:dbbf35b96557 952 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
Kojto 99:dbbf35b96557 953 #define __HAL_RCC_PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto 99:dbbf35b96557 954 /**
Kojto 99:dbbf35b96557 955 * @}
Kojto 99:dbbf35b96557 956 */
emilmont 77:869cf507173a 957
Kojto 99:dbbf35b96557 958 /** @defgroup RCC_APB2_LowPower_Enable_Disable APB2 Peripheral Low Power Enable Disable
Kojto 99:dbbf35b96557 959 * @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
emilmont 77:869cf507173a 960 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont 77:869cf507173a 961 * power consumption.
Kojto 99:dbbf35b96557 962 * @note After wake-up from SLEEP mode, the peripheral clock is enabled again.
emilmont 77:869cf507173a 963 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 99:dbbf35b96557 964 * @{
emilmont 77:869cf507173a 965 */
Kojto 99:dbbf35b96557 966 #define __HAL_RCC_TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM1LPEN))
Kojto 99:dbbf35b96557 967 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
Kojto 99:dbbf35b96557 968 #define __HAL_RCC_USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_USART6LPEN))
Kojto 99:dbbf35b96557 969 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
Kojto 99:dbbf35b96557 970 #define __HAL_RCC_SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
Kojto 99:dbbf35b96557 971 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
Kojto 99:dbbf35b96557 972 #define __HAL_RCC_SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI4LPEN))
Kojto 99:dbbf35b96557 973 #define __HAL_RCC_SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto 99:dbbf35b96557 974 #define __HAL_RCC_TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
Kojto 99:dbbf35b96557 975 #define __HAL_RCC_TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
Kojto 99:dbbf35b96557 976 #define __HAL_RCC_TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
emilmont 77:869cf507173a 977
Kojto 99:dbbf35b96557 978 #define __HAL_RCC_TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
Kojto 99:dbbf35b96557 979 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto 99:dbbf35b96557 980 #define __HAL_RCC_USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
Kojto 99:dbbf35b96557 981 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto 99:dbbf35b96557 982 #define __HAL_RCC_SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
Kojto 99:dbbf35b96557 983 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto 99:dbbf35b96557 984 #define __HAL_RCC_SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
Kojto 99:dbbf35b96557 985 #define __HAL_RCC_SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto 99:dbbf35b96557 986 #define __HAL_RCC_TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto 99:dbbf35b96557 987 #define __HAL_RCC_TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto 99:dbbf35b96557 988 #define __HAL_RCC_TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto 99:dbbf35b96557 989 /**
Kojto 99:dbbf35b96557 990 * @}
Kojto 99:dbbf35b96557 991 */
emilmont 77:869cf507173a 992
Kojto 99:dbbf35b96557 993 /** @defgroup RCC_HSI_Configuration HSI Configuration
Kojto 99:dbbf35b96557 994 * @{
Kojto 99:dbbf35b96557 995 */
Kojto 99:dbbf35b96557 996
emilmont 77:869cf507173a 997 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
emilmont 77:869cf507173a 998 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
emilmont 77:869cf507173a 999 * It is used (enabled by hardware) as system clock source after startup
Kojto 99:dbbf35b96557 1000 * from Reset, wake-up from STOP and STANDBY mode, or in case of failure
emilmont 77:869cf507173a 1001 * of the HSE used directly or indirectly as system clock (if the Clock
emilmont 77:869cf507173a 1002 * Security System CSS is enabled).
emilmont 77:869cf507173a 1003 * @note HSI can not be stopped if it is used as system clock source. In this case,
emilmont 77:869cf507173a 1004 * you have to select another source of the system clock then stop the HSI.
emilmont 77:869cf507173a 1005 * @note After enabling the HSI, the application software should wait on HSIRDY
emilmont 77:869cf507173a 1006 * flag to be set indicating that HSI clock is stable and can be used as
emilmont 77:869cf507173a 1007 * system clock source.
emilmont 77:869cf507173a 1008 * This parameter can be: ENABLE or DISABLE.
emilmont 77:869cf507173a 1009 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
emilmont 77:869cf507173a 1010 * clock cycles.
emilmont 77:869cf507173a 1011 */
Kojto 99:dbbf35b96557 1012 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
Kojto 99:dbbf35b96557 1013 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
emilmont 77:869cf507173a 1014
emilmont 77:869cf507173a 1015 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
emilmont 77:869cf507173a 1016 * @note The calibration is used to compensate for the variations in voltage
emilmont 77:869cf507173a 1017 * and temperature that influence the frequency of the internal HSI RC.
emilmont 77:869cf507173a 1018 * @param __HSICalibrationValue__: specifies the calibration trimming value.
emilmont 77:869cf507173a 1019 * This parameter must be a number between 0 and 0x1F.
emilmont 77:869cf507173a 1020 */
emilmont 77:869cf507173a 1021 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
emilmont 77:869cf507173a 1022 RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
Kojto 99:dbbf35b96557 1023 /**
Kojto 99:dbbf35b96557 1024 * @}
Kojto 99:dbbf35b96557 1025 */
Kojto 99:dbbf35b96557 1026
Kojto 99:dbbf35b96557 1027 /** @defgroup RCC_LSI_Configuration LSI Configuration
Kojto 99:dbbf35b96557 1028 * @{
Kojto 99:dbbf35b96557 1029 */
emilmont 77:869cf507173a 1030
emilmont 77:869cf507173a 1031 /** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
emilmont 77:869cf507173a 1032 * @note After enabling the LSI, the application software should wait on
emilmont 77:869cf507173a 1033 * LSIRDY flag to be set indicating that LSI clock is stable and can
emilmont 77:869cf507173a 1034 * be used to clock the IWDG and/or the RTC.
emilmont 77:869cf507173a 1035 * @note LSI can not be disabled if the IWDG is running.
emilmont 77:869cf507173a 1036 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
emilmont 77:869cf507173a 1037 * clock cycles.
emilmont 77:869cf507173a 1038 */
Kojto 99:dbbf35b96557 1039 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
Kojto 99:dbbf35b96557 1040 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
Kojto 99:dbbf35b96557 1041 /**
Kojto 99:dbbf35b96557 1042 * @}
Kojto 99:dbbf35b96557 1043 */
Kojto 99:dbbf35b96557 1044
Kojto 99:dbbf35b96557 1045 /** @defgroup RCC_HSE_Configuration HSE Configuration
Kojto 99:dbbf35b96557 1046 * @{
Kojto 99:dbbf35b96557 1047 */
emilmont 77:869cf507173a 1048
emilmont 77:869cf507173a 1049 /**
emilmont 77:869cf507173a 1050 * @brief Macro to configure the External High Speed oscillator (HSE).
Kojto 99:dbbf35b96557 1051 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
Kojto 99:dbbf35b96557 1052 * User should request a transition to HSE Off first and then HSE On or HSE Bypass.
emilmont 77:869cf507173a 1053 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
emilmont 77:869cf507173a 1054 * software should wait on HSERDY flag to be set indicating that HSE clock
emilmont 77:869cf507173a 1055 * is stable and can be used to clock the PLL and/or system clock.
emilmont 77:869cf507173a 1056 * @note HSE state can not be changed if it is used directly or through the
emilmont 77:869cf507173a 1057 * PLL as system clock. In this case, you have to select another source
emilmont 77:869cf507173a 1058 * of the system clock then change the HSE state (ex. disable it).
emilmont 77:869cf507173a 1059 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
emilmont 77:869cf507173a 1060 * @note This function reset the CSSON bit, so if the clock security system(CSS)
emilmont 77:869cf507173a 1061 * was previously enabled you have to enable it again after calling this
emilmont 77:869cf507173a 1062 * function.
emilmont 77:869cf507173a 1063 * @param __STATE__: specifies the new state of the HSE.
emilmont 77:869cf507173a 1064 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1065 * @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
emilmont 77:869cf507173a 1066 * 6 HSE oscillator clock cycles.
emilmont 77:869cf507173a 1067 * @arg RCC_HSE_ON: turn ON the HSE oscillator.
emilmont 77:869cf507173a 1068 * @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
emilmont 77:869cf507173a 1069 */
Kojto 99:dbbf35b96557 1070 #define __HAL_RCC_HSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto 99:dbbf35b96557 1071 /**
Kojto 99:dbbf35b96557 1072 * @}
Kojto 99:dbbf35b96557 1073 */
Kojto 99:dbbf35b96557 1074
Kojto 99:dbbf35b96557 1075 /** @defgroup RCC_LSE_Configuration LSE Configuration
Kojto 99:dbbf35b96557 1076 * @{
Kojto 99:dbbf35b96557 1077 */
emilmont 77:869cf507173a 1078
emilmont 77:869cf507173a 1079 /**
emilmont 77:869cf507173a 1080 * @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto 99:dbbf35b96557 1081 * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
Kojto 99:dbbf35b96557 1082 * User should request a transition to LSE Off first and then LSE On or LSE Bypass.
emilmont 77:869cf507173a 1083 * @note As the LSE is in the Backup domain and write access is denied to
emilmont 77:869cf507173a 1084 * this domain after reset, you have to enable write access using
emilmont 77:869cf507173a 1085 * HAL_PWR_EnableBkUpAccess() function before to configure the LSE
emilmont 77:869cf507173a 1086 * (to be done once after reset).
emilmont 77:869cf507173a 1087 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
emilmont 77:869cf507173a 1088 * software should wait on LSERDY flag to be set indicating that LSE clock
emilmont 77:869cf507173a 1089 * is stable and can be used to clock the RTC.
emilmont 77:869cf507173a 1090 * @param __STATE__: specifies the new state of the LSE.
emilmont 77:869cf507173a 1091 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1092 * @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
emilmont 77:869cf507173a 1093 * 6 LSE oscillator clock cycles.
emilmont 77:869cf507173a 1094 * @arg RCC_LSE_ON: turn ON the LSE oscillator.
emilmont 77:869cf507173a 1095 * @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
emilmont 77:869cf507173a 1096 */
Kojto 99:dbbf35b96557 1097 #define __HAL_RCC_LSE_CONFIG(__STATE__) (*(__IO uint8_t *) RCC_BDCR_BYTE0_ADDRESS = (__STATE__))
Kojto 99:dbbf35b96557 1098
Kojto 99:dbbf35b96557 1099 /**
Kojto 99:dbbf35b96557 1100 * @}
Kojto 99:dbbf35b96557 1101 */
emilmont 77:869cf507173a 1102
Kojto 99:dbbf35b96557 1103 /** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
Kojto 99:dbbf35b96557 1104 * @{
Kojto 99:dbbf35b96557 1105 */
Kojto 99:dbbf35b96557 1106
Kojto 99:dbbf35b96557 1107 /** @brief Macros to enable or disable the RTC clock.
emilmont 77:869cf507173a 1108 * @note These macros must be used only after the RTC clock source was selected.
emilmont 77:869cf507173a 1109 */
Kojto 99:dbbf35b96557 1110 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
Kojto 99:dbbf35b96557 1111 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
emilmont 77:869cf507173a 1112
emilmont 77:869cf507173a 1113 /** @brief Macros to configure the RTC clock (RTCCLK).
emilmont 77:869cf507173a 1114 * @note As the RTC clock configuration bits are in the Backup domain and write
emilmont 77:869cf507173a 1115 * access is denied to this domain after reset, you have to enable write
emilmont 77:869cf507173a 1116 * access using the Power Backup Access macro before to configure
emilmont 77:869cf507173a 1117 * the RTC clock source (to be done once after reset).
emilmont 77:869cf507173a 1118 * @note Once the RTC clock is configured it can't be changed unless the
emilmont 77:869cf507173a 1119 * Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
emilmont 77:869cf507173a 1120 * a Power On Reset (POR).
emilmont 77:869cf507173a 1121 * @param __RTCCLKSource__: specifies the RTC clock source.
emilmont 77:869cf507173a 1122 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1123 * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
emilmont 77:869cf507173a 1124 * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
emilmont 77:869cf507173a 1125 * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
emilmont 77:869cf507173a 1126 * as RTC clock, where x:[2,31]
emilmont 77:869cf507173a 1127 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto 99:dbbf35b96557 1128 * work in STOP and STANDBY modes, and can be used as wake-up source.
emilmont 77:869cf507173a 1129 * However, when the HSE clock is used as RTC clock source, the RTC
emilmont 77:869cf507173a 1130 * cannot be used in STOP and STANDBY modes.
emilmont 77:869cf507173a 1131 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
emilmont 77:869cf507173a 1132 * RTC clock source).
emilmont 77:869cf507173a 1133 */
emilmont 77:869cf507173a 1134 #define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
bogdanm 81:7d30d6019079 1135 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm 81:7d30d6019079 1136
emilmont 77:869cf507173a 1137 #define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
emilmont 77:869cf507173a 1138 RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
emilmont 77:869cf507173a 1139 } while (0)
emilmont 77:869cf507173a 1140
emilmont 77:869cf507173a 1141 /** @brief Macros to force or release the Backup domain reset.
emilmont 77:869cf507173a 1142 * @note This function resets the RTC peripheral (including the backup registers)
emilmont 77:869cf507173a 1143 * and the RTC clock source selection in RCC_CSR register.
emilmont 77:869cf507173a 1144 * @note The BKPSRAM is not affected by this reset.
emilmont 77:869cf507173a 1145 */
Kojto 99:dbbf35b96557 1146 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
Kojto 99:dbbf35b96557 1147 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
Kojto 99:dbbf35b96557 1148 /**
Kojto 99:dbbf35b96557 1149 * @}
Kojto 99:dbbf35b96557 1150 */
Kojto 99:dbbf35b96557 1151
Kojto 99:dbbf35b96557 1152 /** @defgroup RCC_PLL_Configuration PLL Configuration
Kojto 99:dbbf35b96557 1153 * @{
Kojto 99:dbbf35b96557 1154 */
emilmont 77:869cf507173a 1155
emilmont 77:869cf507173a 1156 /** @brief Macros to enable or disable the main PLL.
emilmont 77:869cf507173a 1157 * @note After enabling the main PLL, the application software should wait on
emilmont 77:869cf507173a 1158 * PLLRDY flag to be set indicating that PLL clock is stable and can
emilmont 77:869cf507173a 1159 * be used as system clock source.
emilmont 77:869cf507173a 1160 * @note The main PLL can not be disabled if it is used as system clock source
emilmont 77:869cf507173a 1161 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
emilmont 77:869cf507173a 1162 */
Kojto 99:dbbf35b96557 1163 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
Kojto 99:dbbf35b96557 1164 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
Kojto 99:dbbf35b96557 1165 /**
Kojto 99:dbbf35b96557 1166 * @}
Kojto 99:dbbf35b96557 1167 */
emilmont 77:869cf507173a 1168
Kojto 99:dbbf35b96557 1169 /** @brief Macro to configure the PLL clock source.
emilmont 77:869cf507173a 1170 * @note This function must be used only when the main PLL is disabled.
Kojto 99:dbbf35b96557 1171 * @param __PLLSOURCE__: specifies the PLL entry clock source.
emilmont 77:869cf507173a 1172 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1173 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
emilmont 77:869cf507173a 1174 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 99:dbbf35b96557 1175 *
Kojto 99:dbbf35b96557 1176 */
Kojto 99:dbbf35b96557 1177 #define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
Kojto 99:dbbf35b96557 1178
Kojto 99:dbbf35b96557 1179 /** @brief Macro to configure the PLL multiplication factor.
Kojto 99:dbbf35b96557 1180 * @note This function must be used only when the main PLL is disabled.
emilmont 77:869cf507173a 1181 * @param __PLLM__: specifies the division factor for PLL VCO input clock
emilmont 77:869cf507173a 1182 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
emilmont 77:869cf507173a 1183 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
emilmont 77:869cf507173a 1184 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
emilmont 77:869cf507173a 1185 * of 2 MHz to limit PLL jitter.
Kojto 99:dbbf35b96557 1186 *
emilmont 77:869cf507173a 1187 */
Kojto 99:dbbf35b96557 1188 #define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
Kojto 99:dbbf35b96557 1189
Kojto 99:dbbf35b96557 1190 /** @defgroup RCC_PLL_I2S_Configuration PLL I2S Configuration
Kojto 99:dbbf35b96557 1191 * @{
emilmont 77:869cf507173a 1192 */
emilmont 77:869cf507173a 1193
emilmont 77:869cf507173a 1194 /** @brief Macros to enable or disable the PLLI2S.
emilmont 77:869cf507173a 1195 * @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
emilmont 77:869cf507173a 1196 */
Kojto 99:dbbf35b96557 1197 #define __HAL_RCC_PLLI2S_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = ENABLE)
Kojto 99:dbbf35b96557 1198 #define __HAL_RCC_PLLI2S_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLI2SON_BB = DISABLE)
Kojto 99:dbbf35b96557 1199 /**
Kojto 99:dbbf35b96557 1200 * @}
Kojto 99:dbbf35b96557 1201 */
emilmont 77:869cf507173a 1202
Kojto 99:dbbf35b96557 1203 /** @defgroup RCC_Get_Clock_source Get Clock source
Kojto 99:dbbf35b96557 1204 * @{
emilmont 77:869cf507173a 1205 */
Kojto 99:dbbf35b96557 1206 /**
Kojto 99:dbbf35b96557 1207 * @brief Macro to configure the system clock source.
Kojto 99:dbbf35b96557 1208 * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
Kojto 99:dbbf35b96557 1209 * This parameter can be one of the following values:
Kojto 99:dbbf35b96557 1210 * - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
Kojto 99:dbbf35b96557 1211 * - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
Kojto 99:dbbf35b96557 1212 * - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
Kojto 99:dbbf35b96557 1213 * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source.
Kojto 99:dbbf35b96557 1214 */
Kojto 99:dbbf35b96557 1215 #define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
emilmont 77:869cf507173a 1216
emilmont 77:869cf507173a 1217 /** @brief Macro to get the clock source used as system clock.
emilmont 77:869cf507173a 1218 * @retval The clock source used as system clock. The returned value can be one
emilmont 77:869cf507173a 1219 * of the following:
Kojto 99:dbbf35b96557 1220 * - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
Kojto 99:dbbf35b96557 1221 * - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
Kojto 99:dbbf35b96557 1222 * - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
Kojto 99:dbbf35b96557 1223 * - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock.
emilmont 77:869cf507173a 1224 */
emilmont 77:869cf507173a 1225 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
emilmont 77:869cf507173a 1226
emilmont 77:869cf507173a 1227 /** @brief Macro to get the oscillator used as PLL clock source.
emilmont 77:869cf507173a 1228 * @retval The oscillator used as PLL clock source. The returned value can be one
emilmont 77:869cf507173a 1229 * of the following:
emilmont 77:869cf507173a 1230 * - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
emilmont 77:869cf507173a 1231 * - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
emilmont 77:869cf507173a 1232 */
emilmont 77:869cf507173a 1233 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
Kojto 99:dbbf35b96557 1234 /**
Kojto 99:dbbf35b96557 1235 * @}
Kojto 99:dbbf35b96557 1236 */
Kojto 99:dbbf35b96557 1237
Kojto 99:dbbf35b96557 1238 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
Kojto 99:dbbf35b96557 1239 * @brief macros to manage the specified RCC Flags and interrupts.
Kojto 99:dbbf35b96557 1240 * @{
Kojto 99:dbbf35b96557 1241 */
emilmont 77:869cf507173a 1242
emilmont 77:869cf507173a 1243 /** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
emilmont 77:869cf507173a 1244 * the selected interrupts).
emilmont 77:869cf507173a 1245 * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
emilmont 77:869cf507173a 1246 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 1247 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont 77:869cf507173a 1248 * @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont 77:869cf507173a 1249 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont 77:869cf507173a 1250 * @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont 77:869cf507173a 1251 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont 77:869cf507173a 1252 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont 77:869cf507173a 1253 */
Kojto 99:dbbf35b96557 1254 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
emilmont 77:869cf507173a 1255
emilmont 77:869cf507173a 1256 /** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
emilmont 77:869cf507173a 1257 * the selected interrupts).
emilmont 77:869cf507173a 1258 * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
emilmont 77:869cf507173a 1259 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 1260 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont 77:869cf507173a 1261 * @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont 77:869cf507173a 1262 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont 77:869cf507173a 1263 * @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont 77:869cf507173a 1264 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont 77:869cf507173a 1265 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont 77:869cf507173a 1266 */
Kojto 99:dbbf35b96557 1267 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
emilmont 77:869cf507173a 1268
emilmont 77:869cf507173a 1269 /** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
emilmont 77:869cf507173a 1270 * bits to clear the selected interrupt pending bits.
emilmont 77:869cf507173a 1271 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
emilmont 77:869cf507173a 1272 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 1273 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont 77:869cf507173a 1274 * @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont 77:869cf507173a 1275 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont 77:869cf507173a 1276 * @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont 77:869cf507173a 1277 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont 77:869cf507173a 1278 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont 77:869cf507173a 1279 * @arg RCC_IT_CSS: Clock Security System interrupt
emilmont 77:869cf507173a 1280 */
Kojto 99:dbbf35b96557 1281 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
emilmont 77:869cf507173a 1282
emilmont 77:869cf507173a 1283 /** @brief Check the RCC's interrupt has occurred or not.
emilmont 77:869cf507173a 1284 * @param __INTERRUPT__: specifies the RCC interrupt source to check.
emilmont 77:869cf507173a 1285 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1286 * @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont 77:869cf507173a 1287 * @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont 77:869cf507173a 1288 * @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont 77:869cf507173a 1289 * @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont 77:869cf507173a 1290 * @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont 77:869cf507173a 1291 * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont 77:869cf507173a 1292 * @arg RCC_IT_CSS: Clock Security System interrupt
emilmont 77:869cf507173a 1293 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
emilmont 77:869cf507173a 1294 */
emilmont 77:869cf507173a 1295 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
emilmont 77:869cf507173a 1296
emilmont 77:869cf507173a 1297 /** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
emilmont 77:869cf507173a 1298 * RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
emilmont 77:869cf507173a 1299 */
bogdanm 81:7d30d6019079 1300 #define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
emilmont 77:869cf507173a 1301
emilmont 77:869cf507173a 1302 /** @brief Check RCC flag is set or not.
emilmont 77:869cf507173a 1303 * @param __FLAG__: specifies the flag to check.
emilmont 77:869cf507173a 1304 * This parameter can be one of the following values:
emilmont 77:869cf507173a 1305 * @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
emilmont 77:869cf507173a 1306 * @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
emilmont 77:869cf507173a 1307 * @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
emilmont 77:869cf507173a 1308 * @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
emilmont 77:869cf507173a 1309 * @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
emilmont 77:869cf507173a 1310 * @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
emilmont 77:869cf507173a 1311 * @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
emilmont 77:869cf507173a 1312 * @arg RCC_FLAG_PINRST: Pin reset.
emilmont 77:869cf507173a 1313 * @arg RCC_FLAG_PORRST: POR/PDR reset.
emilmont 77:869cf507173a 1314 * @arg RCC_FLAG_SFTRST: Software reset.
emilmont 77:869cf507173a 1315 * @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
emilmont 77:869cf507173a 1316 * @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
emilmont 77:869cf507173a 1317 * @arg RCC_FLAG_LPWRRST: Low Power reset.
emilmont 77:869cf507173a 1318 * @retval The new state of __FLAG__ (TRUE or FALSE).
emilmont 77:869cf507173a 1319 */
emilmont 77:869cf507173a 1320 #define RCC_FLAG_MASK ((uint8_t)0x1F)
emilmont 77:869cf507173a 1321 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
emilmont 77:869cf507173a 1322
Kojto 99:dbbf35b96557 1323 /**
Kojto 99:dbbf35b96557 1324 * @}
Kojto 99:dbbf35b96557 1325 */
Kojto 99:dbbf35b96557 1326
Kojto 99:dbbf35b96557 1327 /**
Kojto 99:dbbf35b96557 1328 * @}
Kojto 99:dbbf35b96557 1329 */
emilmont 77:869cf507173a 1330
emilmont 77:869cf507173a 1331 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 1332 /** @addtogroup RCC_Exported_Functions
Kojto 99:dbbf35b96557 1333 * @{
Kojto 99:dbbf35b96557 1334 */
Kojto 99:dbbf35b96557 1335
Kojto 99:dbbf35b96557 1336 /** @addtogroup RCC_Exported_Functions_Group1
Kojto 99:dbbf35b96557 1337 * @{
Kojto 99:dbbf35b96557 1338 */
emilmont 77:869cf507173a 1339 /* Initialization and de-initialization functions ******************************/
emilmont 77:869cf507173a 1340 void HAL_RCC_DeInit(void);
emilmont 77:869cf507173a 1341 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
emilmont 77:869cf507173a 1342 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto 99:dbbf35b96557 1343 /**
Kojto 99:dbbf35b96557 1344 * @}
Kojto 99:dbbf35b96557 1345 */
emilmont 77:869cf507173a 1346
Kojto 99:dbbf35b96557 1347 /** @addtogroup RCC_Exported_Functions_Group2
Kojto 99:dbbf35b96557 1348 * @{
Kojto 99:dbbf35b96557 1349 */
emilmont 77:869cf507173a 1350 /* Peripheral Control functions ************************************************/
emilmont 77:869cf507173a 1351 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
emilmont 77:869cf507173a 1352 void HAL_RCC_EnableCSS(void);
emilmont 77:869cf507173a 1353 void HAL_RCC_DisableCSS(void);
emilmont 77:869cf507173a 1354 uint32_t HAL_RCC_GetSysClockFreq(void);
emilmont 77:869cf507173a 1355 uint32_t HAL_RCC_GetHCLKFreq(void);
emilmont 77:869cf507173a 1356 uint32_t HAL_RCC_GetPCLK1Freq(void);
emilmont 77:869cf507173a 1357 uint32_t HAL_RCC_GetPCLK2Freq(void);
emilmont 77:869cf507173a 1358 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
emilmont 77:869cf507173a 1359 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
emilmont 77:869cf507173a 1360
emilmont 77:869cf507173a 1361 /* CSS NMI IRQ handler */
emilmont 77:869cf507173a 1362 void HAL_RCC_NMI_IRQHandler(void);
emilmont 77:869cf507173a 1363
emilmont 77:869cf507173a 1364 /* User Callbacks in non blocking mode (IT mode) */
Kojto 99:dbbf35b96557 1365 void HAL_RCC_CSSCallback(void);
Kojto 99:dbbf35b96557 1366
Kojto 99:dbbf35b96557 1367 /**
Kojto 99:dbbf35b96557 1368 * @}
Kojto 99:dbbf35b96557 1369 */
Kojto 99:dbbf35b96557 1370
Kojto 99:dbbf35b96557 1371 /**
Kojto 99:dbbf35b96557 1372 * @}
Kojto 99:dbbf35b96557 1373 */
Kojto 99:dbbf35b96557 1374
Kojto 99:dbbf35b96557 1375 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1376 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1377 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 1378 /** @defgroup RCC_Private_Constants RCC Private Constants
Kojto 99:dbbf35b96557 1379 * @{
Kojto 99:dbbf35b96557 1380 */
Kojto 99:dbbf35b96557 1381
Kojto 99:dbbf35b96557 1382 /** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 99:dbbf35b96557 1383 * @brief RCC registers bit address in the alias region
Kojto 99:dbbf35b96557 1384 * @{
Kojto 99:dbbf35b96557 1385 */
Kojto 99:dbbf35b96557 1386 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto 99:dbbf35b96557 1387 /* --- CR Register ---*/
Kojto 99:dbbf35b96557 1388 /* Alias word address of HSION bit */
Kojto 99:dbbf35b96557 1389 #define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto 99:dbbf35b96557 1390 #define RCC_HSION_BIT_NUMBER 0x00
Kojto 99:dbbf35b96557 1391 #define RCC_CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_HSION_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1392 /* Alias word address of CSSON bit */
Kojto 99:dbbf35b96557 1393 #define RCC_CSSON_BIT_NUMBER 0x13
Kojto 99:dbbf35b96557 1394 #define RCC_CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_CSSON_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1395 /* Alias word address of PLLON bit */
Kojto 99:dbbf35b96557 1396 #define RCC_PLLON_BIT_NUMBER 0x18
Kojto 99:dbbf35b96557 1397 #define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLON_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1398 /* Alias word address of PLLI2SON bit */
Kojto 99:dbbf35b96557 1399 #define RCC_PLLI2SON_BIT_NUMBER 0x1A
Kojto 99:dbbf35b96557 1400 #define RCC_CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLI2SON_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1401
Kojto 99:dbbf35b96557 1402 /* --- CFGR Register ---*/
Kojto 99:dbbf35b96557 1403 /* Alias word address of I2SSRC bit */
Kojto 99:dbbf35b96557 1404 #define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
Kojto 99:dbbf35b96557 1405 #define RCC_I2SSRC_BIT_NUMBER 0x17
Kojto 99:dbbf35b96557 1406 #define RCC_CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (RCC_I2SSRC_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1407
Kojto 99:dbbf35b96557 1408 /* --- BDCR Register ---*/
Kojto 99:dbbf35b96557 1409 /* Alias word address of RTCEN bit */
Kojto 99:dbbf35b96557 1410 #define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
Kojto 99:dbbf35b96557 1411 #define RCC_RTCEN_BIT_NUMBER 0x0F
Kojto 99:dbbf35b96557 1412 #define RCC_BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_RTCEN_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1413 /* Alias word address of BDRST bit */
Kojto 99:dbbf35b96557 1414 #define RCC_BDRST_BIT_NUMBER 0x10
Kojto 99:dbbf35b96557 1415 #define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RCC_BDRST_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1416
Kojto 99:dbbf35b96557 1417 /* --- CSR Register ---*/
Kojto 99:dbbf35b96557 1418 /* Alias word address of LSION bit */
Kojto 99:dbbf35b96557 1419 #define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
Kojto 99:dbbf35b96557 1420 #define RCC_LSION_BIT_NUMBER 0x00
Kojto 99:dbbf35b96557 1421 #define RCC_CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (RCC_LSION_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 1422
Kojto 99:dbbf35b96557 1423 /* CR register byte 3 (Bits[23:16]) base address */
Kojto 99:dbbf35b96557 1424 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
Kojto 99:dbbf35b96557 1425
Kojto 99:dbbf35b96557 1426 /* CIR register byte 2 (Bits[15:8]) base address */
Kojto 99:dbbf35b96557 1427 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
Kojto 99:dbbf35b96557 1428
Kojto 99:dbbf35b96557 1429 /* CIR register byte 3 (Bits[23:16]) base address */
Kojto 99:dbbf35b96557 1430 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
Kojto 99:dbbf35b96557 1431
Kojto 99:dbbf35b96557 1432 /* BDCR register base address */
Kojto 99:dbbf35b96557 1433 #define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto 99:dbbf35b96557 1434
Kojto 99:dbbf35b96557 1435 #define RCC_DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto 99:dbbf35b96557 1436 #define RCC_LSE_TIMEOUT_VALUE ((uint32_t)5000)
Kojto 99:dbbf35b96557 1437
Kojto 99:dbbf35b96557 1438 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto 99:dbbf35b96557 1439 #define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 99:dbbf35b96557 1440 #define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 99:dbbf35b96557 1441
Kojto 99:dbbf35b96557 1442 #define PLLI2S_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
Kojto 99:dbbf35b96557 1443 #define PLLSAI_TIMEOUT_VALUE ((uint32_t)100) /* Timeout value fixed to 100 ms */
Kojto 99:dbbf35b96557 1444 /**
Kojto 99:dbbf35b96557 1445 * @}
Kojto 99:dbbf35b96557 1446 */
Kojto 99:dbbf35b96557 1447
Kojto 99:dbbf35b96557 1448 /**
Kojto 99:dbbf35b96557 1449 * @}
Kojto 99:dbbf35b96557 1450 */
Kojto 99:dbbf35b96557 1451
Kojto 99:dbbf35b96557 1452 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 1453 /** @addtogroup RCC_Private_Macros RCC Private Macros
Kojto 99:dbbf35b96557 1454 * @{
Kojto 99:dbbf35b96557 1455 */
Kojto 99:dbbf35b96557 1456
Kojto 99:dbbf35b96557 1457 /** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 99:dbbf35b96557 1458 * @{
Kojto 99:dbbf35b96557 1459 */
Kojto 99:dbbf35b96557 1460 #define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
Kojto 99:dbbf35b96557 1461
Kojto 99:dbbf35b96557 1462 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
Kojto 99:dbbf35b96557 1463 ((HSE) == RCC_HSE_BYPASS))
Kojto 99:dbbf35b96557 1464
Kojto 99:dbbf35b96557 1465 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
Kojto 99:dbbf35b96557 1466 ((LSE) == RCC_LSE_BYPASS))
Kojto 99:dbbf35b96557 1467
Kojto 99:dbbf35b96557 1468 #define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) || ((HSI) == RCC_HSI_ON))
Kojto 99:dbbf35b96557 1469
Kojto 99:dbbf35b96557 1470 #define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) || ((LSI) == RCC_LSI_ON))
Kojto 99:dbbf35b96557 1471
Kojto 99:dbbf35b96557 1472 #define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) ||((PLL) == RCC_PLL_OFF) || ((PLL) == RCC_PLL_ON))
Kojto 99:dbbf35b96557 1473
Kojto 99:dbbf35b96557 1474 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 99:dbbf35b96557 1475 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 99:dbbf35b96557 1476
Kojto 99:dbbf35b96557 1477 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 99:dbbf35b96557 1478 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 99:dbbf35b96557 1479 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Kojto 99:dbbf35b96557 1480 ((SOURCE) == RCC_SYSCLKSOURCE_PLLRCLK))
Kojto 99:dbbf35b96557 1481
Kojto 99:dbbf35b96557 1482 #define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
Kojto 99:dbbf35b96557 1483
Kojto 99:dbbf35b96557 1484 #define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto 99:dbbf35b96557 1485
Kojto 99:dbbf35b96557 1486 #define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
Kojto 99:dbbf35b96557 1487
Kojto 99:dbbf35b96557 1488 #define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
Kojto 99:dbbf35b96557 1489
Kojto 99:dbbf35b96557 1490 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) || ((HCLK) == RCC_SYSCLK_DIV2) || \
Kojto 99:dbbf35b96557 1491 ((HCLK) == RCC_SYSCLK_DIV4) || ((HCLK) == RCC_SYSCLK_DIV8) || \
Kojto 99:dbbf35b96557 1492 ((HCLK) == RCC_SYSCLK_DIV16) || ((HCLK) == RCC_SYSCLK_DIV64) || \
Kojto 99:dbbf35b96557 1493 ((HCLK) == RCC_SYSCLK_DIV128) || ((HCLK) == RCC_SYSCLK_DIV256) || \
Kojto 99:dbbf35b96557 1494 ((HCLK) == RCC_SYSCLK_DIV512))
Kojto 99:dbbf35b96557 1495
Kojto 99:dbbf35b96557 1496 #define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
Kojto 99:dbbf35b96557 1497
Kojto 99:dbbf35b96557 1498 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) || ((PCLK) == RCC_HCLK_DIV2) || \
Kojto 99:dbbf35b96557 1499 ((PCLK) == RCC_HCLK_DIV4) || ((PCLK) == RCC_HCLK_DIV8) || \
Kojto 99:dbbf35b96557 1500 ((PCLK) == RCC_HCLK_DIV16))
Kojto 99:dbbf35b96557 1501
Kojto 99:dbbf35b96557 1502 #define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) || ((MCOx) == RCC_MCO2))
Kojto 99:dbbf35b96557 1503
Kojto 99:dbbf35b96557 1504 #define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) || ((SOURCE) == RCC_MCO1SOURCE_LSE) || \
Kojto 99:dbbf35b96557 1505 ((SOURCE) == RCC_MCO1SOURCE_HSE) || ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
Kojto 99:dbbf35b96557 1506
Kojto 99:dbbf35b96557 1507 #define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) || ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)|| \
Kojto 99:dbbf35b96557 1508 ((SOURCE) == RCC_MCO2SOURCE_HSE) || ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
Kojto 99:dbbf35b96557 1509
Kojto 99:dbbf35b96557 1510 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
Kojto 99:dbbf35b96557 1511 ((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
Kojto 99:dbbf35b96557 1512 ((DIV) == RCC_MCODIV_5))
Kojto 99:dbbf35b96557 1513 #define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto 99:dbbf35b96557 1514
Kojto 99:dbbf35b96557 1515 /**
Kojto 99:dbbf35b96557 1516 * @}
Kojto 99:dbbf35b96557 1517 */
Kojto 99:dbbf35b96557 1518
Kojto 99:dbbf35b96557 1519 /**
Kojto 99:dbbf35b96557 1520 * @}
Kojto 99:dbbf35b96557 1521 */
emilmont 77:869cf507173a 1522
emilmont 77:869cf507173a 1523 /**
emilmont 77:869cf507173a 1524 * @}
emilmont 77:869cf507173a 1525 */
emilmont 77:869cf507173a 1526
emilmont 77:869cf507173a 1527 /**
emilmont 77:869cf507173a 1528 * @}
emilmont 77:869cf507173a 1529 */
emilmont 77:869cf507173a 1530
emilmont 77:869cf507173a 1531 #ifdef __cplusplus
emilmont 77:869cf507173a 1532 }
emilmont 77:869cf507173a 1533 #endif
emilmont 77:869cf507173a 1534
emilmont 77:869cf507173a 1535 #endif /* __STM32F4xx_HAL_RCC_H */
emilmont 77:869cf507173a 1536
emilmont 77:869cf507173a 1537 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/