Ricardo Benitez / mbed

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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_dma2d.h@99:dbbf35b96557, 2015-05-13 (annotated)

Committer:
Kojto
Date:
Wed May 13 08:08:21 2015 +0200
Revision:
99:dbbf35b96557
Parent:
92:4fc01daae5a5
Child:
106:ba1f97679dad
Release 99 of the mbed library



Changes:

 - new targets - MAXWSNENV, DISCO_L053C8

 - STM32F4xx - ST Cube driver

 - KSDK mcu - SPI timing fix

 - Nordic - update to softdevice s130

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_dma2d.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
Kojto 99:dbbf35b96557 5 * @version V1.3.0
Kojto 99:dbbf35b96557 6 * @date 09-March-2015
bogdanm 92:4fc01daae5a5 7 * @brief Header file of DMA2D HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_DMA2D_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_DMA2D_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 92:4fc01daae5a5 47 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 48 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 49
bogdanm 92:4fc01daae5a5 50 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 51 * @{
bogdanm 92:4fc01daae5a5 52 */
bogdanm 92:4fc01daae5a5 53
Kojto 99:dbbf35b96557 54 /** @defgroup DMA2D DMA2D
Kojto 99:dbbf35b96557 55 * @brief DMA2D HAL module driver
bogdanm 92:4fc01daae5a5 56 * @{
Kojto 99:dbbf35b96557 57 */
Kojto 99:dbbf35b96557 58
bogdanm 92:4fc01daae5a5 59 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 60 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
Kojto 99:dbbf35b96557 61 * @{
Kojto 99:dbbf35b96557 62 */
bogdanm 92:4fc01daae5a5 63 #define MAX_DMA2D_LAYER 2
bogdanm 92:4fc01daae5a5 64
bogdanm 92:4fc01daae5a5 65 /**
bogdanm 92:4fc01daae5a5 66 * @brief DMA2D color Structure definition
bogdanm 92:4fc01daae5a5 67 */
bogdanm 92:4fc01daae5a5 68 typedef struct
bogdanm 92:4fc01daae5a5 69 {
bogdanm 92:4fc01daae5a5 70 uint32_t Blue; /*!< Configures the blue value.
bogdanm 92:4fc01daae5a5 71 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 uint32_t Green; /*!< Configures the green value.
bogdanm 92:4fc01daae5a5 74 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 uint32_t Red; /*!< Configures the red value.
bogdanm 92:4fc01daae5a5 77 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 92:4fc01daae5a5 78 } DMA2D_ColorTypeDef;
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 /**
bogdanm 92:4fc01daae5a5 81 * @brief DMA2D CLUT Structure definition
bogdanm 92:4fc01daae5a5 82 */
bogdanm 92:4fc01daae5a5 83 typedef struct
bogdanm 92:4fc01daae5a5 84 {
bogdanm 92:4fc01daae5a5 85 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
bogdanm 92:4fc01daae5a5 86
bogdanm 92:4fc01daae5a5 87 uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
bogdanm 92:4fc01daae5a5 88 This parameter can be one value of @ref DMA2D_CLUT_CM */
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 uint32_t Size; /*!< configures the DMA2D CLUT size.
bogdanm 92:4fc01daae5a5 91 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
bogdanm 92:4fc01daae5a5 92 } DMA2D_CLUTCfgTypeDef;
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 /**
bogdanm 92:4fc01daae5a5 95 * @brief DMA2D Init structure definition
bogdanm 92:4fc01daae5a5 96 */
bogdanm 92:4fc01daae5a5 97 typedef struct
bogdanm 92:4fc01daae5a5 98 {
bogdanm 92:4fc01daae5a5 99 uint32_t Mode; /*!< configures the DMA2D transfer mode.
bogdanm 92:4fc01daae5a5 100 This parameter can be one value of @ref DMA2D_Mode */
bogdanm 92:4fc01daae5a5 101
bogdanm 92:4fc01daae5a5 102 uint32_t ColorMode; /*!< configures the color format of the output image.
bogdanm 92:4fc01daae5a5 103 This parameter can be one value of @ref DMA2D_Color_Mode */
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 uint32_t OutputOffset; /*!< Specifies the Offset value.
bogdanm 92:4fc01daae5a5 106 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
bogdanm 92:4fc01daae5a5 107 } DMA2D_InitTypeDef;
bogdanm 92:4fc01daae5a5 108
bogdanm 92:4fc01daae5a5 109 /**
bogdanm 92:4fc01daae5a5 110 * @brief DMA2D Layer structure definition
bogdanm 92:4fc01daae5a5 111 */
bogdanm 92:4fc01daae5a5 112 typedef struct
bogdanm 92:4fc01daae5a5 113 {
bogdanm 92:4fc01daae5a5 114 uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
bogdanm 92:4fc01daae5a5 115 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
bogdanm 92:4fc01daae5a5 118 This parameter can be one value of @ref DMA2D_Input_Color_Mode */
bogdanm 92:4fc01daae5a5 119
bogdanm 92:4fc01daae5a5 120 uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
bogdanm 92:4fc01daae5a5 121 This parameter can be one value of @ref DMA2D_ALPHA_MODE */
bogdanm 92:4fc01daae5a5 122
bogdanm 92:4fc01daae5a5 123 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode.
bogdanm 92:4fc01daae5a5 124 This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF
bogdanm 92:4fc01daae5a5 125 in case of A8 or A4 color mode (ARGB).
bogdanm 92:4fc01daae5a5 126 Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
bogdanm 92:4fc01daae5a5 127
bogdanm 92:4fc01daae5a5 128 } DMA2D_LayerCfgTypeDef;
bogdanm 92:4fc01daae5a5 129
bogdanm 92:4fc01daae5a5 130 /**
bogdanm 92:4fc01daae5a5 131 * @brief HAL DMA2D State structures definition
bogdanm 92:4fc01daae5a5 132 */
bogdanm 92:4fc01daae5a5 133 typedef enum
bogdanm 92:4fc01daae5a5 134 {
bogdanm 92:4fc01daae5a5 135 HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 136 HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 92:4fc01daae5a5 137 HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
bogdanm 92:4fc01daae5a5 138 HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
bogdanm 92:4fc01daae5a5 139 HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
bogdanm 92:4fc01daae5a5 140 HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
bogdanm 92:4fc01daae5a5 141 }HAL_DMA2D_StateTypeDef;
bogdanm 92:4fc01daae5a5 142
bogdanm 92:4fc01daae5a5 143 /**
bogdanm 92:4fc01daae5a5 144 * @brief DMA2D handle Structure definition
bogdanm 92:4fc01daae5a5 145 */
bogdanm 92:4fc01daae5a5 146 typedef struct __DMA2D_HandleTypeDef
bogdanm 92:4fc01daae5a5 147 {
bogdanm 92:4fc01daae5a5 148 DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
bogdanm 92:4fc01daae5a5 149
bogdanm 92:4fc01daae5a5 150 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
bogdanm 92:4fc01daae5a5 153
bogdanm 92:4fc01daae5a5 154 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
bogdanm 92:4fc01daae5a5 155
bogdanm 92:4fc01daae5a5 156 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
bogdanm 92:4fc01daae5a5 157
bogdanm 92:4fc01daae5a5 158 HAL_LockTypeDef Lock; /*!< DMA2D Lock */
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 __IO uint32_t ErrorCode; /*!< DMA2D Error code */
bogdanm 92:4fc01daae5a5 163 } DMA2D_HandleTypeDef;
bogdanm 92:4fc01daae5a5 164 /**
bogdanm 92:4fc01daae5a5 165 * @}
bogdanm 92:4fc01daae5a5 166 */
bogdanm 92:4fc01daae5a5 167
Kojto 99:dbbf35b96557 168 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 169 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
Kojto 99:dbbf35b96557 170 * @{
Kojto 99:dbbf35b96557 171 */
Kojto 99:dbbf35b96557 172
Kojto 99:dbbf35b96557 173 /** @defgroup DMA2D_Error_Code DMA2D Error Code
bogdanm 92:4fc01daae5a5 174 * @{
bogdanm 92:4fc01daae5a5 175 */
bogdanm 92:4fc01daae5a5 176 #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 92:4fc01daae5a5 177 #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 92:4fc01daae5a5 178 #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
bogdanm 92:4fc01daae5a5 179 #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 92:4fc01daae5a5 180 /**
bogdanm 92:4fc01daae5a5 181 * @}
bogdanm 92:4fc01daae5a5 182 */
bogdanm 92:4fc01daae5a5 183
Kojto 99:dbbf35b96557 184 /** @defgroup DMA2D_Mode DMA2D Mode
bogdanm 92:4fc01daae5a5 185 * @{
bogdanm 92:4fc01daae5a5 186 */
bogdanm 92:4fc01daae5a5 187 #define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
bogdanm 92:4fc01daae5a5 188 #define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
bogdanm 92:4fc01daae5a5 189 #define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
bogdanm 92:4fc01daae5a5 190 #define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
bogdanm 92:4fc01daae5a5 191 /**
bogdanm 92:4fc01daae5a5 192 * @}
bogdanm 92:4fc01daae5a5 193 */
bogdanm 92:4fc01daae5a5 194
Kojto 99:dbbf35b96557 195 /** @defgroup DMA2D_Color_Mode DMA2D Color Mode
bogdanm 92:4fc01daae5a5 196 * @{
bogdanm 92:4fc01daae5a5 197 */
bogdanm 92:4fc01daae5a5 198 #define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
bogdanm 92:4fc01daae5a5 199 #define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */
bogdanm 92:4fc01daae5a5 200 #define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
bogdanm 92:4fc01daae5a5 201 #define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
bogdanm 92:4fc01daae5a5 202 #define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
bogdanm 92:4fc01daae5a5 203 /**
bogdanm 92:4fc01daae5a5 204 * @}
bogdanm 92:4fc01daae5a5 205 */
bogdanm 92:4fc01daae5a5 206
Kojto 99:dbbf35b96557 207 /** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE
bogdanm 92:4fc01daae5a5 208 * @{
bogdanm 92:4fc01daae5a5 209 */
bogdanm 92:4fc01daae5a5 210 #define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
bogdanm 92:4fc01daae5a5 211 /**
bogdanm 92:4fc01daae5a5 212 * @}
bogdanm 92:4fc01daae5a5 213 */
bogdanm 92:4fc01daae5a5 214
Kojto 99:dbbf35b96557 215 /** @defgroup DMA2D_SIZE DMA2D SIZE
bogdanm 92:4fc01daae5a5 216 * @{
bogdanm 92:4fc01daae5a5 217 */
bogdanm 92:4fc01daae5a5 218 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
bogdanm 92:4fc01daae5a5 219 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
bogdanm 92:4fc01daae5a5 220 /**
bogdanm 92:4fc01daae5a5 221 * @}
bogdanm 92:4fc01daae5a5 222 */
bogdanm 92:4fc01daae5a5 223
Kojto 99:dbbf35b96557 224 /** @defgroup DMA2D_Offset DMA2D Offset
bogdanm 92:4fc01daae5a5 225 * @{
bogdanm 92:4fc01daae5a5 226 */
bogdanm 92:4fc01daae5a5 227 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
bogdanm 92:4fc01daae5a5 228 /**
bogdanm 92:4fc01daae5a5 229 * @}
bogdanm 92:4fc01daae5a5 230 */
bogdanm 92:4fc01daae5a5 231
Kojto 99:dbbf35b96557 232 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
bogdanm 92:4fc01daae5a5 233 * @{
bogdanm 92:4fc01daae5a5 234 */
bogdanm 92:4fc01daae5a5 235 #define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
bogdanm 92:4fc01daae5a5 236 #define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */
bogdanm 92:4fc01daae5a5 237 #define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */
bogdanm 92:4fc01daae5a5 238 #define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */
bogdanm 92:4fc01daae5a5 239 #define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */
bogdanm 92:4fc01daae5a5 240 #define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */
bogdanm 92:4fc01daae5a5 241 #define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */
bogdanm 92:4fc01daae5a5 242 #define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */
bogdanm 92:4fc01daae5a5 243 #define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
bogdanm 92:4fc01daae5a5 244 #define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
bogdanm 92:4fc01daae5a5 245 #define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
bogdanm 92:4fc01daae5a5 246 /**
bogdanm 92:4fc01daae5a5 247 * @}
bogdanm 92:4fc01daae5a5 248 */
bogdanm 92:4fc01daae5a5 249
Kojto 99:dbbf35b96557 250 /** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE
bogdanm 92:4fc01daae5a5 251 * @{
bogdanm 92:4fc01daae5a5 252 */
bogdanm 92:4fc01daae5a5 253 #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
bogdanm 92:4fc01daae5a5 254 #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
bogdanm 92:4fc01daae5a5 255 #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
bogdanm 92:4fc01daae5a5 256 with original alpha channel value */
bogdanm 92:4fc01daae5a5 257 /**
bogdanm 92:4fc01daae5a5 258 * @}
bogdanm 92:4fc01daae5a5 259 */
bogdanm 92:4fc01daae5a5 260
Kojto 99:dbbf35b96557 261 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM
bogdanm 92:4fc01daae5a5 262 * @{
bogdanm 92:4fc01daae5a5 263 */
bogdanm 92:4fc01daae5a5 264 #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
bogdanm 92:4fc01daae5a5 265 #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
bogdanm 92:4fc01daae5a5 266 /**
bogdanm 92:4fc01daae5a5 267 * @}
bogdanm 92:4fc01daae5a5 268 */
bogdanm 92:4fc01daae5a5 269
Kojto 99:dbbf35b96557 270 /** @defgroup DMA2D_Size_Clut DMA2D Size Clut
bogdanm 92:4fc01daae5a5 271 * @{
bogdanm 92:4fc01daae5a5 272 */
bogdanm 92:4fc01daae5a5 273 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
bogdanm 92:4fc01daae5a5 274 /**
bogdanm 92:4fc01daae5a5 275 * @}
bogdanm 92:4fc01daae5a5 276 */
bogdanm 92:4fc01daae5a5 277
Kojto 99:dbbf35b96557 278 /** @defgroup DMA2D_DeadTime DMA2D DeadTime
bogdanm 92:4fc01daae5a5 279 * @{
bogdanm 92:4fc01daae5a5 280 */
bogdanm 92:4fc01daae5a5 281 #define LINE_WATERMARK DMA2D_LWR_LW
bogdanm 92:4fc01daae5a5 282 /**
bogdanm 92:4fc01daae5a5 283 * @}
bogdanm 92:4fc01daae5a5 284 */
bogdanm 92:4fc01daae5a5 285
Kojto 99:dbbf35b96557 286 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
bogdanm 92:4fc01daae5a5 287 * @{
bogdanm 92:4fc01daae5a5 288 */
bogdanm 92:4fc01daae5a5 289 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
bogdanm 92:4fc01daae5a5 290 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */
bogdanm 92:4fc01daae5a5 291 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */
bogdanm 92:4fc01daae5a5 292 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
bogdanm 92:4fc01daae5a5 293 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
bogdanm 92:4fc01daae5a5 294 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
bogdanm 92:4fc01daae5a5 295 /**
bogdanm 92:4fc01daae5a5 296 * @}
bogdanm 92:4fc01daae5a5 297 */
bogdanm 92:4fc01daae5a5 298
Kojto 99:dbbf35b96557 299 /** @defgroup DMA2D_Flag DMA2D Flag
bogdanm 92:4fc01daae5a5 300 * @{
bogdanm 92:4fc01daae5a5 301 */
bogdanm 92:4fc01daae5a5 302 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
bogdanm 92:4fc01daae5a5 303 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */
bogdanm 92:4fc01daae5a5 304 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */
bogdanm 92:4fc01daae5a5 305 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
bogdanm 92:4fc01daae5a5 306 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
bogdanm 92:4fc01daae5a5 307 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
bogdanm 92:4fc01daae5a5 308 /**
bogdanm 92:4fc01daae5a5 309 * @}
bogdanm 92:4fc01daae5a5 310 */
bogdanm 92:4fc01daae5a5 311
bogdanm 92:4fc01daae5a5 312 /**
bogdanm 92:4fc01daae5a5 313 * @}
bogdanm 92:4fc01daae5a5 314 */
bogdanm 92:4fc01daae5a5 315 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 316 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
Kojto 99:dbbf35b96557 317 * @{
Kojto 99:dbbf35b96557 318 */
bogdanm 92:4fc01daae5a5 319
bogdanm 92:4fc01daae5a5 320 /** @brief Reset DMA2D handle state
bogdanm 92:4fc01daae5a5 321 * @param __HANDLE__: specifies the DMA2D handle.
bogdanm 92:4fc01daae5a5 322 * @retval None
bogdanm 92:4fc01daae5a5 323 */
bogdanm 92:4fc01daae5a5 324 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
bogdanm 92:4fc01daae5a5 325
bogdanm 92:4fc01daae5a5 326 /**
bogdanm 92:4fc01daae5a5 327 * @brief Enable the DMA2D.
bogdanm 92:4fc01daae5a5 328 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 329 * @retval None.
bogdanm 92:4fc01daae5a5 330 */
bogdanm 92:4fc01daae5a5 331 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
bogdanm 92:4fc01daae5a5 332
bogdanm 92:4fc01daae5a5 333 /**
bogdanm 92:4fc01daae5a5 334 * @brief Disable the DMA2D.
bogdanm 92:4fc01daae5a5 335 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 336 * @retval None.
bogdanm 92:4fc01daae5a5 337 */
bogdanm 92:4fc01daae5a5 338 #define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
bogdanm 92:4fc01daae5a5 339
bogdanm 92:4fc01daae5a5 340 /* Interrupt & Flag management */
bogdanm 92:4fc01daae5a5 341 /**
bogdanm 92:4fc01daae5a5 342 * @brief Get the DMA2D pending flags.
bogdanm 92:4fc01daae5a5 343 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 344 * @param __FLAG__: Get the specified flag.
bogdanm 92:4fc01daae5a5 345 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 346 * @arg DMA2D_FLAG_CE: Configuration error flag
bogdanm 92:4fc01daae5a5 347 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
bogdanm 92:4fc01daae5a5 348 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
bogdanm 92:4fc01daae5a5 349 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
bogdanm 92:4fc01daae5a5 350 * @arg DMA2D_FLAG_TC: Transfer complete flag
bogdanm 92:4fc01daae5a5 351 * @arg DMA2D_FLAG_TE: Transfer error flag
bogdanm 92:4fc01daae5a5 352 * @retval The state of FLAG.
bogdanm 92:4fc01daae5a5 353 */
bogdanm 92:4fc01daae5a5 354 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 /**
bogdanm 92:4fc01daae5a5 357 * @brief Clears the DMA2D pending flags.
bogdanm 92:4fc01daae5a5 358 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 359 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 360 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 361 * @arg DMA2D_FLAG_CE: Configuration error flag
bogdanm 92:4fc01daae5a5 362 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
bogdanm 92:4fc01daae5a5 363 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
bogdanm 92:4fc01daae5a5 364 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
bogdanm 92:4fc01daae5a5 365 * @arg DMA2D_FLAG_TC: Transfer complete flag
bogdanm 92:4fc01daae5a5 366 * @arg DMA2D_FLAG_TE: Transfer error flag
bogdanm 92:4fc01daae5a5 367 * @retval None
bogdanm 92:4fc01daae5a5 368 */
bogdanm 92:4fc01daae5a5 369 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
bogdanm 92:4fc01daae5a5 370
bogdanm 92:4fc01daae5a5 371 /**
bogdanm 92:4fc01daae5a5 372 * @brief Enables the specified DMA2D interrupts.
bogdanm 92:4fc01daae5a5 373 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 374 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
bogdanm 92:4fc01daae5a5 375 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 376 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 92:4fc01daae5a5 377 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 378 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 92:4fc01daae5a5 379 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 92:4fc01daae5a5 380 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 381 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 92:4fc01daae5a5 382 * @retval None
bogdanm 92:4fc01daae5a5 383 */
bogdanm 92:4fc01daae5a5 384 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 385
bogdanm 92:4fc01daae5a5 386 /**
bogdanm 92:4fc01daae5a5 387 * @brief Disables the specified DMA2D interrupts.
bogdanm 92:4fc01daae5a5 388 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 389 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
bogdanm 92:4fc01daae5a5 390 * This parameter can be any combination of the following values:
bogdanm 92:4fc01daae5a5 391 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 92:4fc01daae5a5 392 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 393 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 92:4fc01daae5a5 394 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 92:4fc01daae5a5 395 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 396 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 92:4fc01daae5a5 397 * @retval None
bogdanm 92:4fc01daae5a5 398 */
bogdanm 92:4fc01daae5a5 399 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 400
bogdanm 92:4fc01daae5a5 401 /**
bogdanm 92:4fc01daae5a5 402 * @brief Checks whether the specified DMA2D interrupt has occurred or not.
bogdanm 92:4fc01daae5a5 403 * @param __HANDLE__: DMA2D handle
bogdanm 92:4fc01daae5a5 404 * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
bogdanm 92:4fc01daae5a5 405 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 406 * @arg DMA2D_IT_CE: Configuration error interrupt mask
bogdanm 92:4fc01daae5a5 407 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 408 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
bogdanm 92:4fc01daae5a5 409 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
bogdanm 92:4fc01daae5a5 410 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
bogdanm 92:4fc01daae5a5 411 * @arg DMA2D_IT_TE: Transfer error interrupt mask
bogdanm 92:4fc01daae5a5 412 * @retval The state of INTERRUPT.
bogdanm 92:4fc01daae5a5 413 */
bogdanm 92:4fc01daae5a5 414 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Kojto 99:dbbf35b96557 415 /**
Kojto 99:dbbf35b96557 416 * @}
Kojto 99:dbbf35b96557 417 */
bogdanm 92:4fc01daae5a5 418
bogdanm 92:4fc01daae5a5 419 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 420 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
Kojto 99:dbbf35b96557 421 * @{
Kojto 99:dbbf35b96557 422 */
bogdanm 92:4fc01daae5a5 423 /* Initialization and de-initialization functions *******************************/
bogdanm 92:4fc01daae5a5 424 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 425 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 426 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
bogdanm 92:4fc01daae5a5 427 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
bogdanm 92:4fc01daae5a5 428
bogdanm 92:4fc01daae5a5 429 /* IO operation functions *******************************************************/
Kojto 99:dbbf35b96557 430 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
Kojto 99:dbbf35b96557 431 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
Kojto 99:dbbf35b96557 432 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
Kojto 99:dbbf35b96557 433 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
bogdanm 92:4fc01daae5a5 434 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 435 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 436 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 437 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 438 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 439
bogdanm 92:4fc01daae5a5 440 /* Peripheral Control functions *************************************************/
bogdanm 92:4fc01daae5a5 441 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 92:4fc01daae5a5 442 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
bogdanm 92:4fc01daae5a5 443 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 92:4fc01daae5a5 444 HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
bogdanm 92:4fc01daae5a5 445 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
bogdanm 92:4fc01daae5a5 446
bogdanm 92:4fc01daae5a5 447 /* Peripheral State functions ***************************************************/
bogdanm 92:4fc01daae5a5 448 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
bogdanm 92:4fc01daae5a5 449 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
Kojto 99:dbbf35b96557 450 /**
Kojto 99:dbbf35b96557 451 * @}
Kojto 99:dbbf35b96557 452 */
bogdanm 92:4fc01daae5a5 453
Kojto 99:dbbf35b96557 454 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 455 /** @defgroup DMA2D_Private_Types DMA2D Private Types
Kojto 99:dbbf35b96557 456 * @{
Kojto 99:dbbf35b96557 457 */
Kojto 99:dbbf35b96557 458
Kojto 99:dbbf35b96557 459 /**
Kojto 99:dbbf35b96557 460 * @}
Kojto 99:dbbf35b96557 461 */
Kojto 99:dbbf35b96557 462
Kojto 99:dbbf35b96557 463 /* Private defines -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 464 /** @defgroup DMA2D_Private_Defines DMA2D Private Defines
Kojto 99:dbbf35b96557 465 * @{
Kojto 99:dbbf35b96557 466 */
Kojto 99:dbbf35b96557 467
Kojto 99:dbbf35b96557 468 /**
Kojto 99:dbbf35b96557 469 * @}
Kojto 99:dbbf35b96557 470 */
Kojto 99:dbbf35b96557 471
Kojto 99:dbbf35b96557 472 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 473 /** @defgroup DMA2D_Private_Variables DMA2D Private Variables
Kojto 99:dbbf35b96557 474 * @{
Kojto 99:dbbf35b96557 475 */
Kojto 99:dbbf35b96557 476
Kojto 99:dbbf35b96557 477 /**
Kojto 99:dbbf35b96557 478 * @}
Kojto 99:dbbf35b96557 479 */
Kojto 99:dbbf35b96557 480
Kojto 99:dbbf35b96557 481 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 482 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
Kojto 99:dbbf35b96557 483 * @{
Kojto 99:dbbf35b96557 484 */
Kojto 99:dbbf35b96557 485
Kojto 99:dbbf35b96557 486 /**
Kojto 99:dbbf35b96557 487 * @}
Kojto 99:dbbf35b96557 488 */
Kojto 99:dbbf35b96557 489
Kojto 99:dbbf35b96557 490 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 491 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
Kojto 99:dbbf35b96557 492 * @{
Kojto 99:dbbf35b96557 493 */
Kojto 99:dbbf35b96557 494 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
Kojto 99:dbbf35b96557 495 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
Kojto 99:dbbf35b96557 496 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
Kojto 99:dbbf35b96557 497 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
Kojto 99:dbbf35b96557 498 ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
Kojto 99:dbbf35b96557 499 ((MODE_ARGB) == DMA2D_ARGB4444))
Kojto 99:dbbf35b96557 500 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
Kojto 99:dbbf35b96557 501 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
Kojto 99:dbbf35b96557 502 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
Kojto 99:dbbf35b96557 503 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
Kojto 99:dbbf35b96557 504 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
Kojto 99:dbbf35b96557 505 ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
Kojto 99:dbbf35b96557 506 ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
Kojto 99:dbbf35b96557 507 ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
Kojto 99:dbbf35b96557 508 ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
Kojto 99:dbbf35b96557 509 ((INPUT_CM) == CM_A4))
Kojto 99:dbbf35b96557 510 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
Kojto 99:dbbf35b96557 511 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
Kojto 99:dbbf35b96557 512 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
Kojto 99:dbbf35b96557 513 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
Kojto 99:dbbf35b96557 514 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
Kojto 99:dbbf35b96557 515 #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
Kojto 99:dbbf35b96557 516 /**
Kojto 99:dbbf35b96557 517 * @}
Kojto 99:dbbf35b96557 518 */
Kojto 99:dbbf35b96557 519
Kojto 99:dbbf35b96557 520 /* Private functions prototypes ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 521 /** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes
Kojto 99:dbbf35b96557 522 * @{
Kojto 99:dbbf35b96557 523 */
Kojto 99:dbbf35b96557 524
Kojto 99:dbbf35b96557 525 /**
Kojto 99:dbbf35b96557 526 * @}
Kojto 99:dbbf35b96557 527 */
Kojto 99:dbbf35b96557 528
Kojto 99:dbbf35b96557 529 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 530 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
Kojto 99:dbbf35b96557 531 * @{
Kojto 99:dbbf35b96557 532 */
Kojto 99:dbbf35b96557 533
Kojto 99:dbbf35b96557 534 /**
Kojto 99:dbbf35b96557 535 * @}
Kojto 99:dbbf35b96557 536 */
bogdanm 92:4fc01daae5a5 537
bogdanm 92:4fc01daae5a5 538 /**
bogdanm 92:4fc01daae5a5 539 * @}
bogdanm 92:4fc01daae5a5 540 */
bogdanm 92:4fc01daae5a5 541
bogdanm 92:4fc01daae5a5 542 /**
bogdanm 92:4fc01daae5a5 543 * @}
bogdanm 92:4fc01daae5a5 544 */
Kojto 99:dbbf35b96557 545
Kojto 99:dbbf35b96557 546 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 99:dbbf35b96557 547
bogdanm 92:4fc01daae5a5 548 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 549 }
bogdanm 92:4fc01daae5a5 550 #endif
bogdanm 92:4fc01daae5a5 551
bogdanm 92:4fc01daae5a5 552 #endif /* __STM32F4xx_HAL_DMA2D_H */
bogdanm 92:4fc01daae5a5 553
bogdanm 92:4fc01daae5a5 554 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/