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TARGET_NUCLEO_L073RZ/stm32l0xx_hal_rcc_ex.h@116:c0f6e94411f5, 2016-03-15 (annotated)

Committer:
Kojto
Date:
Tue Mar 15 14:34:00 2016 +0000
Revision:
116:c0f6e94411f5
Release 116 of the mbed library



Changes:

- new targets - NUCLEO_L073RZ

- fixes to IOTSS BEID platform

- LPC824, LPC1549 and LPC11U68 - fix PWMOut SCT bugs

- STM32F7 - Cube driver

- STM32F4 - add RTC LSI macro, defined as 0

- STM32F3 - fix multiple ADC clock initialization

- retarget - binary mode fix for GCC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 116:c0f6e94411f5 1 /**
Kojto 116:c0f6e94411f5 2 ******************************************************************************
Kojto 116:c0f6e94411f5 3 * @file stm32l0xx_hal_rcc_ex.h
Kojto 116:c0f6e94411f5 4 * @author MCD Application Team
Kojto 116:c0f6e94411f5 5 * @version V1.2.0
Kojto 116:c0f6e94411f5 6 * @date 06-February-2015
Kojto 116:c0f6e94411f5 7 * @brief Header file of RCC HAL Extension module.
Kojto 116:c0f6e94411f5 8 ******************************************************************************
Kojto 116:c0f6e94411f5 9 * @attention
Kojto 116:c0f6e94411f5 10 *
Kojto 116:c0f6e94411f5 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 116:c0f6e94411f5 12 *
Kojto 116:c0f6e94411f5 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 116:c0f6e94411f5 14 * are permitted provided that the following conditions are met:
Kojto 116:c0f6e94411f5 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 116:c0f6e94411f5 16 * this list of conditions and the following disclaimer.
Kojto 116:c0f6e94411f5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 116:c0f6e94411f5 18 * this list of conditions and the following disclaimer in the documentation
Kojto 116:c0f6e94411f5 19 * and/or other materials provided with the distribution.
Kojto 116:c0f6e94411f5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 116:c0f6e94411f5 21 * may be used to endorse or promote products derived from this software
Kojto 116:c0f6e94411f5 22 * without specific prior written permission.
Kojto 116:c0f6e94411f5 23 *
Kojto 116:c0f6e94411f5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 116:c0f6e94411f5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 116:c0f6e94411f5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 116:c0f6e94411f5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 116:c0f6e94411f5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 116:c0f6e94411f5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 116:c0f6e94411f5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 116:c0f6e94411f5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 116:c0f6e94411f5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 116:c0f6e94411f5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 116:c0f6e94411f5 34 *
Kojto 116:c0f6e94411f5 35 ******************************************************************************
Kojto 116:c0f6e94411f5 36 */
Kojto 116:c0f6e94411f5 37
Kojto 116:c0f6e94411f5 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 116:c0f6e94411f5 39 #ifndef __STM32L0xx_HAL_RCC_EX_H
Kojto 116:c0f6e94411f5 40 #define __STM32L0xx_HAL_RCC_EX_H
Kojto 116:c0f6e94411f5 41
Kojto 116:c0f6e94411f5 42 #ifdef __cplusplus
Kojto 116:c0f6e94411f5 43 extern "C" {
Kojto 116:c0f6e94411f5 44 #endif
Kojto 116:c0f6e94411f5 45
Kojto 116:c0f6e94411f5 46 /* Includes ------------------------------------------------------------------*/
Kojto 116:c0f6e94411f5 47 #include "stm32l0xx_hal_def.h"
Kojto 116:c0f6e94411f5 48
Kojto 116:c0f6e94411f5 49 /** @addtogroup STM32L0xx_HAL_Driver
Kojto 116:c0f6e94411f5 50 * @{
Kojto 116:c0f6e94411f5 51 */
Kojto 116:c0f6e94411f5 52
Kojto 116:c0f6e94411f5 53 /** @defgroup RCCEx
Kojto 116:c0f6e94411f5 54 * @{
Kojto 116:c0f6e94411f5 55 */
Kojto 116:c0f6e94411f5 56
Kojto 116:c0f6e94411f5 57 /* Exported types ------------------------------------------------------------*/
Kojto 116:c0f6e94411f5 58 /**
Kojto 116:c0f6e94411f5 59 * @brief RCC extended clocks structure definition
Kojto 116:c0f6e94411f5 60 */
Kojto 116:c0f6e94411f5 61 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 62 typedef struct
Kojto 116:c0f6e94411f5 63 {
Kojto 116:c0f6e94411f5 64 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 116:c0f6e94411f5 65 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 116:c0f6e94411f5 66 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 116:c0f6e94411f5 67 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 116:c0f6e94411f5 68
Kojto 116:c0f6e94411f5 69 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 116:c0f6e94411f5 70 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 116:c0f6e94411f5 71
Kojto 116:c0f6e94411f5 72 uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
Kojto 116:c0f6e94411f5 73 This parameter can be a value of @ref RCCEx_LPUART_Clock_Source */
Kojto 116:c0f6e94411f5 74
Kojto 116:c0f6e94411f5 75 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 116:c0f6e94411f5 76 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
Kojto 116:c0f6e94411f5 77 #if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 78 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto 116:c0f6e94411f5 79 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 116:c0f6e94411f5 80 #endif
Kojto 116:c0f6e94411f5 81
Kojto 116:c0f6e94411f5 82 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 116:c0f6e94411f5 83 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 116:c0f6e94411f5 84 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 85 uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
Kojto 116:c0f6e94411f5 86 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 116:c0f6e94411f5 87 #endif
Kojto 116:c0f6e94411f5 88
Kojto 116:c0f6e94411f5 89 uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
Kojto 116:c0f6e94411f5 90 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 116:c0f6e94411f5 91
Kojto 116:c0f6e94411f5 92 uint32_t LptimClockSelection; /*!< LPTIM1 clock source
Kojto 116:c0f6e94411f5 93 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto 116:c0f6e94411f5 94
Kojto 116:c0f6e94411f5 95 }RCC_PeriphCLKInitTypeDef;
Kojto 116:c0f6e94411f5 96
Kojto 116:c0f6e94411f5 97
Kojto 116:c0f6e94411f5 98 #else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
Kojto 116:c0f6e94411f5 99
Kojto 116:c0f6e94411f5 100 typedef struct
Kojto 116:c0f6e94411f5 101 {
Kojto 116:c0f6e94411f5 102 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 116:c0f6e94411f5 103 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 116:c0f6e94411f5 104 #if !defined (STM32L031xx) && !defined (STM32L041xx)
Kojto 116:c0f6e94411f5 105 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 116:c0f6e94411f5 106 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 116:c0f6e94411f5 107 #endif
Kojto 116:c0f6e94411f5 108 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 116:c0f6e94411f5 109 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 116:c0f6e94411f5 110
Kojto 116:c0f6e94411f5 111 uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
Kojto 116:c0f6e94411f5 112 This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
Kojto 116:c0f6e94411f5 113
Kojto 116:c0f6e94411f5 114 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 116:c0f6e94411f5 115 This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
Kojto 116:c0f6e94411f5 116
Kojto 116:c0f6e94411f5 117 #if defined (STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 118 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto 116:c0f6e94411f5 119 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 116:c0f6e94411f5 120 #endif
Kojto 116:c0f6e94411f5 121
Kojto 116:c0f6e94411f5 122 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 116:c0f6e94411f5 123 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 116:c0f6e94411f5 124
Kojto 116:c0f6e94411f5 125 uint32_t LptimClockSelection; /*!< LPTIM1 clock source
Kojto 116:c0f6e94411f5 126 This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
Kojto 116:c0f6e94411f5 127
Kojto 116:c0f6e94411f5 128 }RCC_PeriphCLKInitTypeDef;
Kojto 116:c0f6e94411f5 129
Kojto 116:c0f6e94411f5 130 #endif /* STM32L0x1xx */
Kojto 116:c0f6e94411f5 131
Kojto 116:c0f6e94411f5 132
Kojto 116:c0f6e94411f5 133 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 134 /** @defgroup RCCEx_Exported_Constants
Kojto 116:c0f6e94411f5 135 * @{
Kojto 116:c0f6e94411f5 136 */
Kojto 116:c0f6e94411f5 137 /**
Kojto 116:c0f6e94411f5 138 * @brief RCC CRS Status definition
Kojto 116:c0f6e94411f5 139 */
Kojto 116:c0f6e94411f5 140
Kojto 116:c0f6e94411f5 141 #define RCC_CRS_NONE ((uint32_t) 0x00000000)
Kojto 116:c0f6e94411f5 142 #define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001)
Kojto 116:c0f6e94411f5 143 #define RCC_CRS_SYNCOK ((uint32_t) 0x00000002)
Kojto 116:c0f6e94411f5 144 #define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004)
Kojto 116:c0f6e94411f5 145 #define RCC_CRS_SYNCERR ((uint32_t) 0x00000008)
Kojto 116:c0f6e94411f5 146 #define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010)
Kojto 116:c0f6e94411f5 147 #define RCC_CRS_TRIMOV ((uint32_t) 0x00000020)
Kojto 116:c0f6e94411f5 148
Kojto 116:c0f6e94411f5 149 /**
Kojto 116:c0f6e94411f5 150 * @}
Kojto 116:c0f6e94411f5 151 */
Kojto 116:c0f6e94411f5 152 /**
Kojto 116:c0f6e94411f5 153 * @brief RCC_CRS Init structure definition
Kojto 116:c0f6e94411f5 154 */
Kojto 116:c0f6e94411f5 155 typedef struct
Kojto 116:c0f6e94411f5 156 {
Kojto 116:c0f6e94411f5 157 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
Kojto 116:c0f6e94411f5 158 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
Kojto 116:c0f6e94411f5 159
Kojto 116:c0f6e94411f5 160 uint32_t Source; /*!< Specifies the SYNC signal source.
Kojto 116:c0f6e94411f5 161 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
Kojto 116:c0f6e94411f5 162
Kojto 116:c0f6e94411f5 163 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
Kojto 116:c0f6e94411f5 164 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
Kojto 116:c0f6e94411f5 165
Kojto 116:c0f6e94411f5 166 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
Kojto 116:c0f6e94411f5 167 It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
Kojto 116:c0f6e94411f5 168 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
Kojto 116:c0f6e94411f5 169
Kojto 116:c0f6e94411f5 170 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
Kojto 116:c0f6e94411f5 171 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
Kojto 116:c0f6e94411f5 172
Kojto 116:c0f6e94411f5 173 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
Kojto 116:c0f6e94411f5 174 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
Kojto 116:c0f6e94411f5 175
Kojto 116:c0f6e94411f5 176 }RCC_CRSInitTypeDef;
Kojto 116:c0f6e94411f5 177
Kojto 116:c0f6e94411f5 178 /**
Kojto 116:c0f6e94411f5 179 * @brief RCC_CRS Synchronization structure definition
Kojto 116:c0f6e94411f5 180 */
Kojto 116:c0f6e94411f5 181 typedef struct
Kojto 116:c0f6e94411f5 182 {
Kojto 116:c0f6e94411f5 183 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Kojto 116:c0f6e94411f5 184 This parameter must be a number between 0 and 0xFFFF*/
Kojto 116:c0f6e94411f5 185
Kojto 116:c0f6e94411f5 186 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
Kojto 116:c0f6e94411f5 187 This parameter must be a number between 0 and 0x3F */
Kojto 116:c0f6e94411f5 188
Kojto 116:c0f6e94411f5 189 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
Kojto 116:c0f6e94411f5 190 value latched in the time of the last SYNC event.
Kojto 116:c0f6e94411f5 191 This parameter must be a number between 0 and 0xFFFF */
Kojto 116:c0f6e94411f5 192
Kojto 116:c0f6e94411f5 193 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
Kojto 116:c0f6e94411f5 194 frequency error counter latched in the time of the last SYNC event.
Kojto 116:c0f6e94411f5 195 It shows whether the actual frequency is below or above the target.
Kojto 116:c0f6e94411f5 196 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
Kojto 116:c0f6e94411f5 197
Kojto 116:c0f6e94411f5 198 }RCC_CRSSynchroInfoTypeDef;
Kojto 116:c0f6e94411f5 199 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 200
Kojto 116:c0f6e94411f5 201 /* Exported constants --------------------------------------------------------*/
Kojto 116:c0f6e94411f5 202 /** @addtogroup RCCEx_Exported_Constants
Kojto 116:c0f6e94411f5 203 * @{
Kojto 116:c0f6e94411f5 204 */
Kojto 116:c0f6e94411f5 205
Kojto 116:c0f6e94411f5 206 /** @defgroup RCCEx_Periph_Clock_Selection
Kojto 116:c0f6e94411f5 207 * @{
Kojto 116:c0f6e94411f5 208 */
Kojto 116:c0f6e94411f5 209 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 210
Kojto 116:c0f6e94411f5 211 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 116:c0f6e94411f5 212 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 116:c0f6e94411f5 213 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
Kojto 116:c0f6e94411f5 214 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
Kojto 116:c0f6e94411f5 215 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
Kojto 116:c0f6e94411f5 216 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto 116:c0f6e94411f5 217 #define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
Kojto 116:c0f6e94411f5 218 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
Kojto 116:c0f6e94411f5 219 #if defined (STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 220 #define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
Kojto 116:c0f6e94411f5 221 #endif
Kojto 116:c0f6e94411f5 222 #if defined (STM32L072xx) || defined(STM32L073xx) || defined(STM32L082xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 223 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
Kojto 116:c0f6e94411f5 224 #endif
Kojto 116:c0f6e94411f5 225
Kojto 116:c0f6e94411f5 226 #if defined (STM32L052xx) || defined(STM32L062xx)
Kojto 116:c0f6e94411f5 227 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
Kojto 116:c0f6e94411f5 228 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
Kojto 116:c0f6e94411f5 229 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1))
Kojto 116:c0f6e94411f5 230 #elif defined (STM32L053xx) || defined(STM32L063xx)
Kojto 116:c0f6e94411f5 231 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
Kojto 116:c0f6e94411f5 232 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
Kojto 116:c0f6e94411f5 233 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_LCD))
Kojto 116:c0f6e94411f5 234 #elif defined (STM32L072xx) || defined(STM32L082xx)
Kojto 116:c0f6e94411f5 235 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
Kojto 116:c0f6e94411f5 236 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
Kojto 116:c0f6e94411f5 237 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 ))
Kojto 116:c0f6e94411f5 238 #elif defined (STM32L073xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 239 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
Kojto 116:c0f6e94411f5 240 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
Kojto 116:c0f6e94411f5 241 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3 | \
Kojto 116:c0f6e94411f5 242 RCC_PERIPHCLK_LCD))
Kojto 116:c0f6e94411f5 243 #endif
Kojto 116:c0f6e94411f5 244
Kojto 116:c0f6e94411f5 245 #else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
Kojto 116:c0f6e94411f5 246
Kojto 116:c0f6e94411f5 247 #if !defined(STM32L031xx) && !defined(STM32L041xx)
Kojto 116:c0f6e94411f5 248 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 116:c0f6e94411f5 249 #endif
Kojto 116:c0f6e94411f5 250 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 116:c0f6e94411f5 251 #define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
Kojto 116:c0f6e94411f5 252 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
Kojto 116:c0f6e94411f5 253 #if !defined(STM32L031xx) && !defined(STM32L041xx)
Kojto 116:c0f6e94411f5 254 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
Kojto 116:c0f6e94411f5 255 #endif
Kojto 116:c0f6e94411f5 256 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto 116:c0f6e94411f5 257 #define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
Kojto 116:c0f6e94411f5 258 #if defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 259 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
Kojto 116:c0f6e94411f5 260 #endif
Kojto 116:c0f6e94411f5 261
Kojto 116:c0f6e94411f5 262 #if defined(STM32L031xx) || defined(STM32L041xx)
Kojto 116:c0f6e94411f5 263 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
Kojto 116:c0f6e94411f5 264 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_RTC ))
Kojto 116:c0f6e94411f5 265 #elif defined(STM32L051xx) || defined(STM32L061xx)
Kojto 116:c0f6e94411f5 266 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
Kojto 116:c0f6e94411f5 267 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
Kojto 116:c0f6e94411f5 268 RCC_PERIPHCLK_LPTIM1))
Kojto 116:c0f6e94411f5 269 #elif defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 270 #define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_LPUART1 | \
Kojto 116:c0f6e94411f5 271 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | RCC_PERIPHCLK_RTC | \
Kojto 116:c0f6e94411f5 272 RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_I2C3))
Kojto 116:c0f6e94411f5 273 #endif
Kojto 116:c0f6e94411f5 274
Kojto 116:c0f6e94411f5 275 #endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
Kojto 116:c0f6e94411f5 276 /**
Kojto 116:c0f6e94411f5 277 * @}
Kojto 116:c0f6e94411f5 278 */
Kojto 116:c0f6e94411f5 279
Kojto 116:c0f6e94411f5 280 /** @defgroup RCCEx_USART1_Clock_Source
Kojto 116:c0f6e94411f5 281 * @{
Kojto 116:c0f6e94411f5 282 */
Kojto 116:c0f6e94411f5 283 #define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 284 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
Kojto 116:c0f6e94411f5 285 #define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
Kojto 116:c0f6e94411f5 286 #define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 | RCC_CCIPR_USART1SEL_1)
Kojto 116:c0f6e94411f5 287 #define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 116:c0f6e94411f5 288 ((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 116:c0f6e94411f5 289 ((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 116:c0f6e94411f5 290 ((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
Kojto 116:c0f6e94411f5 291 /**
Kojto 116:c0f6e94411f5 292 * @}
Kojto 116:c0f6e94411f5 293 */
Kojto 116:c0f6e94411f5 294
Kojto 116:c0f6e94411f5 295 /** @defgroup RCCEx_USART2_Clock_Source
Kojto 116:c0f6e94411f5 296 * @{
Kojto 116:c0f6e94411f5 297 */
Kojto 116:c0f6e94411f5 298 #define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 299 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
Kojto 116:c0f6e94411f5 300 #define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
Kojto 116:c0f6e94411f5 301 #define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 | RCC_CCIPR_USART2SEL_1)
Kojto 116:c0f6e94411f5 302 #define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) || \
Kojto 116:c0f6e94411f5 303 ((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) || \
Kojto 116:c0f6e94411f5 304 ((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) || \
Kojto 116:c0f6e94411f5 305 ((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
Kojto 116:c0f6e94411f5 306 /**
Kojto 116:c0f6e94411f5 307 * @}
Kojto 116:c0f6e94411f5 308 */
Kojto 116:c0f6e94411f5 309
Kojto 116:c0f6e94411f5 310 /** @defgroup RCCEx_LPUART_Clock_Source
Kojto 116:c0f6e94411f5 311 * @{
Kojto 116:c0f6e94411f5 312 */
Kojto 116:c0f6e94411f5 313 #define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 314 #define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
Kojto 116:c0f6e94411f5 315 #define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
Kojto 116:c0f6e94411f5 316 #define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 | RCC_CCIPR_LPUART1SEL_1)
Kojto 116:c0f6e94411f5 317 #define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) || \
Kojto 116:c0f6e94411f5 318 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) || \
Kojto 116:c0f6e94411f5 319 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) || \
Kojto 116:c0f6e94411f5 320 ((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
Kojto 116:c0f6e94411f5 321 /**
Kojto 116:c0f6e94411f5 322 * @}
Kojto 116:c0f6e94411f5 323 */
Kojto 116:c0f6e94411f5 324
Kojto 116:c0f6e94411f5 325 /** @defgroup RCCEx_I2C1_Clock_Source
Kojto 116:c0f6e94411f5 326 * @{
Kojto 116:c0f6e94411f5 327 */
Kojto 116:c0f6e94411f5 328 #define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 329 #define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
Kojto 116:c0f6e94411f5 330 #define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
Kojto 116:c0f6e94411f5 331 #define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) || \
Kojto 116:c0f6e94411f5 332 ((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)|| \
Kojto 116:c0f6e94411f5 333 ((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
Kojto 116:c0f6e94411f5 334 /**
Kojto 116:c0f6e94411f5 335 * @}
Kojto 116:c0f6e94411f5 336 */
Kojto 116:c0f6e94411f5 337
Kojto 116:c0f6e94411f5 338 #if defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx)|| defined(STM32L081xx) || defined(STM32L082xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 339
Kojto 116:c0f6e94411f5 340 /** @defgroup RCCEx_I2C3_Clock_Source
Kojto 116:c0f6e94411f5 341 * @{
Kojto 116:c0f6e94411f5 342 */
Kojto 116:c0f6e94411f5 343 #define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 344 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
Kojto 116:c0f6e94411f5 345 #define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
Kojto 116:c0f6e94411f5 346 #define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) || \
Kojto 116:c0f6e94411f5 347 ((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)|| \
Kojto 116:c0f6e94411f5 348 ((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
Kojto 116:c0f6e94411f5 349 #endif /* defined(STM32L071xx) || defined(STM32L072xx) || defined(STM32L073xx) || defined(STM32L081xx)|| defined(STM32L082xx) || defined(STM32L083xx) */
Kojto 116:c0f6e94411f5 350
Kojto 116:c0f6e94411f5 351 /**
Kojto 116:c0f6e94411f5 352 * @}
Kojto 116:c0f6e94411f5 353 */
Kojto 116:c0f6e94411f5 354
Kojto 116:c0f6e94411f5 355 /** @defgroup RCCEx_TIM_PRescaler_Selection
Kojto 116:c0f6e94411f5 356 * @{
Kojto 116:c0f6e94411f5 357 */
Kojto 116:c0f6e94411f5 358 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
Kojto 116:c0f6e94411f5 359 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
Kojto 116:c0f6e94411f5 360 /**
Kojto 116:c0f6e94411f5 361 * @}
Kojto 116:c0f6e94411f5 362 */
Kojto 116:c0f6e94411f5 363
Kojto 116:c0f6e94411f5 364 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 365 /** @defgroup RCCEx_USB_Clock_Source
Kojto 116:c0f6e94411f5 366 * @{
Kojto 116:c0f6e94411f5 367 */
Kojto 116:c0f6e94411f5 368 #define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
Kojto 116:c0f6e94411f5 369 #define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 370
Kojto 116:c0f6e94411f5 371 #define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) || \
Kojto 116:c0f6e94411f5 372 ((__SOURCE__) == RCC_USBCLKSOURCE_PLLCLK))
Kojto 116:c0f6e94411f5 373 /**
Kojto 116:c0f6e94411f5 374 * @}
Kojto 116:c0f6e94411f5 375 */
Kojto 116:c0f6e94411f5 376
Kojto 116:c0f6e94411f5 377 /** @defgroup RCCEx_RNG_Clock_Source
Kojto 116:c0f6e94411f5 378 * @{
Kojto 116:c0f6e94411f5 379 */
Kojto 116:c0f6e94411f5 380 #define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
Kojto 116:c0f6e94411f5 381 #define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 382
Kojto 116:c0f6e94411f5 383 #define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) || \
Kojto 116:c0f6e94411f5 384 ((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
Kojto 116:c0f6e94411f5 385 /**
Kojto 116:c0f6e94411f5 386 * @}
Kojto 116:c0f6e94411f5 387 */
Kojto 116:c0f6e94411f5 388
Kojto 116:c0f6e94411f5 389 /** @defgroup RCCEx_HSI48M_Clock_Source
Kojto 116:c0f6e94411f5 390 * @{
Kojto 116:c0f6e94411f5 391 */
Kojto 116:c0f6e94411f5 392 #define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF
Kojto 116:c0f6e94411f5 393
Kojto 116:c0f6e94411f5 394 #define RCC_HSI48M_PLL ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 395 #define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
Kojto 116:c0f6e94411f5 396
Kojto 116:c0f6e94411f5 397 #define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) || ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
Kojto 116:c0f6e94411f5 398
Kojto 116:c0f6e94411f5 399 /**
Kojto 116:c0f6e94411f5 400 * @}
Kojto 116:c0f6e94411f5 401 */
Kojto 116:c0f6e94411f5 402 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 403
Kojto 116:c0f6e94411f5 404 /** @defgroup RCC_HSI_Config
Kojto 116:c0f6e94411f5 405 * @{
Kojto 116:c0f6e94411f5 406 */
Kojto 116:c0f6e94411f5 407 #define RCC_HSI_OFF ((uint8_t)0x00)
Kojto 116:c0f6e94411f5 408 #define RCC_HSI_ON RCC_CR_HSION
Kojto 116:c0f6e94411f5 409 #define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN | RCC_CR_HSION)
Kojto 116:c0f6e94411f5 410 #if defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 411 defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 412 defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 413 #define RCC_HSI_OUTEN RCC_CR_HSIOUTEN
Kojto 116:c0f6e94411f5 414
Kojto 116:c0f6e94411f5 415 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
Kojto 116:c0f6e94411f5 416 ((__HSI__) == RCC_HSI_DIV4) || ((__HSI__) == RCC_HSI_OUTEN ))
Kojto 116:c0f6e94411f5 417 #else
Kojto 116:c0f6e94411f5 418 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON) || \
Kojto 116:c0f6e94411f5 419 ((__HSI__) == RCC_HSI_DIV4))
Kojto 116:c0f6e94411f5 420 #endif
Kojto 116:c0f6e94411f5 421
Kojto 116:c0f6e94411f5 422 /**
Kojto 116:c0f6e94411f5 423 * @}
Kojto 116:c0f6e94411f5 424 */
Kojto 116:c0f6e94411f5 425
Kojto 116:c0f6e94411f5 426 /** @defgroup RCCEx_LPTIM1_Clock_Source
Kojto 116:c0f6e94411f5 427 * @{
Kojto 116:c0f6e94411f5 428 */
Kojto 116:c0f6e94411f5 429 #define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 430 #define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
Kojto 116:c0f6e94411f5 431 #define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
Kojto 116:c0f6e94411f5 432 #define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
Kojto 116:c0f6e94411f5 433
Kojto 116:c0f6e94411f5 434 #define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) || \
Kojto 116:c0f6e94411f5 435 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) || \
Kojto 116:c0f6e94411f5 436 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) || \
Kojto 116:c0f6e94411f5 437 ((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
Kojto 116:c0f6e94411f5 438 /**
Kojto 116:c0f6e94411f5 439 * @}
Kojto 116:c0f6e94411f5 440 */
Kojto 116:c0f6e94411f5 441
Kojto 116:c0f6e94411f5 442 /** @defgroup RCCEx_StopWakeUp_Clock
Kojto 116:c0f6e94411f5 443 * @{
Kojto 116:c0f6e94411f5 444 */
Kojto 116:c0f6e94411f5 445
Kojto 116:c0f6e94411f5 446 #define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00)
Kojto 116:c0f6e94411f5 447 #define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
Kojto 116:c0f6e94411f5 448
Kojto 116:c0f6e94411f5 449 #define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) || \
Kojto 116:c0f6e94411f5 450 ((__SOURCE__) == RCC_StopWakeUpClock_HSI))
Kojto 116:c0f6e94411f5 451 /**
Kojto 116:c0f6e94411f5 452 * @}
Kojto 116:c0f6e94411f5 453 */
Kojto 116:c0f6e94411f5 454
Kojto 116:c0f6e94411f5 455 /** @defgroup RCCEx_LSEDrive_Configuration
Kojto 116:c0f6e94411f5 456 * @{
Kojto 116:c0f6e94411f5 457 */
Kojto 116:c0f6e94411f5 458
Kojto 116:c0f6e94411f5 459 #define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
Kojto 116:c0f6e94411f5 460 #define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
Kojto 116:c0f6e94411f5 461 #define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
Kojto 116:c0f6e94411f5 462 #define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
Kojto 116:c0f6e94411f5 463 #define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) || ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) || \
Kojto 116:c0f6e94411f5 464 ((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) || ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
Kojto 116:c0f6e94411f5 465 /**
Kojto 116:c0f6e94411f5 466 * @}
Kojto 116:c0f6e94411f5 467 */
Kojto 116:c0f6e94411f5 468
Kojto 116:c0f6e94411f5 469 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 470 /** @defgroup RCCEx_CRS_SynchroSource
Kojto 116:c0f6e94411f5 471 * @{
Kojto 116:c0f6e94411f5 472 */
Kojto 116:c0f6e94411f5 473 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal source GPIO */
Kojto 116:c0f6e94411f5 474 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
Kojto 116:c0f6e94411f5 475 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
Kojto 116:c0f6e94411f5 476
Kojto 116:c0f6e94411f5 477 #define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) || \
Kojto 116:c0f6e94411f5 478 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) ||\
Kojto 116:c0f6e94411f5 479 ((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
Kojto 116:c0f6e94411f5 480 /**
Kojto 116:c0f6e94411f5 481 * @}
Kojto 116:c0f6e94411f5 482 */
Kojto 116:c0f6e94411f5 483
Kojto 116:c0f6e94411f5 484 /** @defgroup RCCEx_CRS_SynchroDivider
Kojto 116:c0f6e94411f5 485 * @{
Kojto 116:c0f6e94411f5 486 */
Kojto 116:c0f6e94411f5 487 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
Kojto 116:c0f6e94411f5 488 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
Kojto 116:c0f6e94411f5 489 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
Kojto 116:c0f6e94411f5 490 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
Kojto 116:c0f6e94411f5 491 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
Kojto 116:c0f6e94411f5 492 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
Kojto 116:c0f6e94411f5 493 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
Kojto 116:c0f6e94411f5 494 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
Kojto 116:c0f6e94411f5 495
Kojto 116:c0f6e94411f5 496 #define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) || ((__DIV__) == RCC_CRS_SYNC_DIV2) ||\
Kojto 116:c0f6e94411f5 497 ((__DIV__) == RCC_CRS_SYNC_DIV4) || ((__DIV__) == RCC_CRS_SYNC_DIV8) || \
Kojto 116:c0f6e94411f5 498 ((__DIV__) == RCC_CRS_SYNC_DIV16) || ((__DIV__) == RCC_CRS_SYNC_DIV32) || \
Kojto 116:c0f6e94411f5 499 ((__DIV__) == RCC_CRS_SYNC_DIV64) || ((__DIV__) == RCC_CRS_SYNC_DIV128))
Kojto 116:c0f6e94411f5 500 /**
Kojto 116:c0f6e94411f5 501 * @}
Kojto 116:c0f6e94411f5 502 */
Kojto 116:c0f6e94411f5 503
Kojto 116:c0f6e94411f5 504 /** @defgroup RCCEx_CRS_SynchroPolarity
Kojto 116:c0f6e94411f5 505 * @{
Kojto 116:c0f6e94411f5 506 */
Kojto 116:c0f6e94411f5 507 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
Kojto 116:c0f6e94411f5 508 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
Kojto 116:c0f6e94411f5 509
Kojto 116:c0f6e94411f5 510 #define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) || \
Kojto 116:c0f6e94411f5 511 ((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
Kojto 116:c0f6e94411f5 512 /**
Kojto 116:c0f6e94411f5 513 * @}
Kojto 116:c0f6e94411f5 514 */
Kojto 116:c0f6e94411f5 515
Kojto 116:c0f6e94411f5 516 /** @defgroup RCCEx_CRS_ReloadValueDefault
Kojto 116:c0f6e94411f5 517 * @{
Kojto 116:c0f6e94411f5 518 */
Kojto 116:c0f6e94411f5 519 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
Kojto 116:c0f6e94411f5 520 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
Kojto 116:c0f6e94411f5 521
Kojto 116:c0f6e94411f5 522 #define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
Kojto 116:c0f6e94411f5 523 /**
Kojto 116:c0f6e94411f5 524 * @}
Kojto 116:c0f6e94411f5 525 */
Kojto 116:c0f6e94411f5 526
Kojto 116:c0f6e94411f5 527 /** @defgroup RCCEx_CRS_ErrorLimitDefault
Kojto 116:c0f6e94411f5 528 * @{
Kojto 116:c0f6e94411f5 529 */
Kojto 116:c0f6e94411f5 530 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
Kojto 116:c0f6e94411f5 531
Kojto 116:c0f6e94411f5 532 #define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
Kojto 116:c0f6e94411f5 533 /**
Kojto 116:c0f6e94411f5 534 * @}
Kojto 116:c0f6e94411f5 535 */
Kojto 116:c0f6e94411f5 536
Kojto 116:c0f6e94411f5 537 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault
Kojto 116:c0f6e94411f5 538 * @{
Kojto 116:c0f6e94411f5 539 */
Kojto 116:c0f6e94411f5 540 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
Kojto 116:c0f6e94411f5 541 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
Kojto 116:c0f6e94411f5 542 corresponds to a higher output frequency */
Kojto 116:c0f6e94411f5 543
Kojto 116:c0f6e94411f5 544 #define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
Kojto 116:c0f6e94411f5 545 /**
Kojto 116:c0f6e94411f5 546 * @}
Kojto 116:c0f6e94411f5 547 */
Kojto 116:c0f6e94411f5 548
Kojto 116:c0f6e94411f5 549 /** @defgroup RCCEx_CRS_FreqErrorDirection
Kojto 116:c0f6e94411f5 550 * @{
Kojto 116:c0f6e94411f5 551 */
Kojto 116:c0f6e94411f5 552 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
Kojto 116:c0f6e94411f5 553 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
Kojto 116:c0f6e94411f5 554
Kojto 116:c0f6e94411f5 555 #define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) || \
Kojto 116:c0f6e94411f5 556 ((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
Kojto 116:c0f6e94411f5 557 /**
Kojto 116:c0f6e94411f5 558 * @}
Kojto 116:c0f6e94411f5 559 */
Kojto 116:c0f6e94411f5 560
Kojto 116:c0f6e94411f5 561 /** @defgroup RCCEx_CRS_Interrupt_Sources
Kojto 116:c0f6e94411f5 562 * @{
Kojto 116:c0f6e94411f5 563 */
Kojto 116:c0f6e94411f5 564 #define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
Kojto 116:c0f6e94411f5 565 #define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
Kojto 116:c0f6e94411f5 566 #define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */
Kojto 116:c0f6e94411f5 567 #define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
Kojto 116:c0f6e94411f5 568 #define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
Kojto 116:c0f6e94411f5 569 #define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
Kojto 116:c0f6e94411f5 570 #define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
Kojto 116:c0f6e94411f5 571
Kojto 116:c0f6e94411f5 572 /**
Kojto 116:c0f6e94411f5 573 * @}
Kojto 116:c0f6e94411f5 574 */
Kojto 116:c0f6e94411f5 575
Kojto 116:c0f6e94411f5 576 /** @defgroup RCCEx_CRS_Flags
Kojto 116:c0f6e94411f5 577 * @{
Kojto 116:c0f6e94411f5 578 */
Kojto 116:c0f6e94411f5 579 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
Kojto 116:c0f6e94411f5 580 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
Kojto 116:c0f6e94411f5 581 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
Kojto 116:c0f6e94411f5 582 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
Kojto 116:c0f6e94411f5 583 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
Kojto 116:c0f6e94411f5 584 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
Kojto 116:c0f6e94411f5 585 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
Kojto 116:c0f6e94411f5 586
Kojto 116:c0f6e94411f5 587 /**
Kojto 116:c0f6e94411f5 588 * @}
Kojto 116:c0f6e94411f5 589 */
Kojto 116:c0f6e94411f5 590
Kojto 116:c0f6e94411f5 591 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 592 /**
Kojto 116:c0f6e94411f5 593 * @}
Kojto 116:c0f6e94411f5 594 */
Kojto 116:c0f6e94411f5 595
Kojto 116:c0f6e94411f5 596 /* Exported macro ------------------------------------------------------------*/
Kojto 116:c0f6e94411f5 597 /** @defgroup RCCEx_Exported_Macros RCC Ex Exported Macros
Kojto 116:c0f6e94411f5 598 * @{
Kojto 116:c0f6e94411f5 599 */
Kojto 116:c0f6e94411f5 600
Kojto 116:c0f6e94411f5 601 /** @brief Enable or disable the AHB peripheral clock.
Kojto 116:c0f6e94411f5 602 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 116:c0f6e94411f5 603 * is disabled and the application software has to enable this clock before
Kojto 116:c0f6e94411f5 604 * using it.
Kojto 116:c0f6e94411f5 605 */
Kojto 116:c0f6e94411f5 606
Kojto 116:c0f6e94411f5 607 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 608 #define __HAL_RCC_AES_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_CRYPEN))
Kojto 116:c0f6e94411f5 609 #define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN))
Kojto 116:c0f6e94411f5 610 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
Kojto 116:c0f6e94411f5 611
Kojto 116:c0f6e94411f5 612 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 613 #define __HAL_RCC_TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
Kojto 116:c0f6e94411f5 614 #define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN))
Kojto 116:c0f6e94411f5 615
Kojto 116:c0f6e94411f5 616 #define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_RNGEN))
Kojto 116:c0f6e94411f5 617 #define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN))
Kojto 116:c0f6e94411f5 618 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 619
Kojto 116:c0f6e94411f5 620
Kojto 116:c0f6e94411f5 621 #if defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 622 defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 623 defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 624 /** @brief Enable or disable the IOPORT peripheral clock.
Kojto 116:c0f6e94411f5 625 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 116:c0f6e94411f5 626 * is disabled and the application software has to enable this clock before
Kojto 116:c0f6e94411f5 627 * using it.
Kojto 116:c0f6e94411f5 628 */
Kojto 116:c0f6e94411f5 629 #define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto 116:c0f6e94411f5 630 __IO uint32_t tmpreg; \
Kojto 116:c0f6e94411f5 631 SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
Kojto 116:c0f6e94411f5 632 /* Delay after an RCC peripheral clock enabling */ \
Kojto 116:c0f6e94411f5 633 tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
Kojto 116:c0f6e94411f5 634 UNUSED(tmpreg); \
Kojto 116:c0f6e94411f5 635 } while(0)
Kojto 116:c0f6e94411f5 636
Kojto 116:c0f6e94411f5 637 #define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOEEN))
Kojto 116:c0f6e94411f5 638
Kojto 116:c0f6e94411f5 639 #endif /* STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 640 /* STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 641 /* STM32L073xx || STM32L083xx */
Kojto 116:c0f6e94411f5 642
Kojto 116:c0f6e94411f5 643 /** @brief Enable or disable the APB1 peripheral clock.
Kojto 116:c0f6e94411f5 644 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 116:c0f6e94411f5 645 * is disabled and the application software has to enable this clock before
Kojto 116:c0f6e94411f5 646 * using it.
Kojto 116:c0f6e94411f5 647 */
Kojto 116:c0f6e94411f5 648
Kojto 116:c0f6e94411f5 649 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 650 #define __HAL_RCC_USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
Kojto 116:c0f6e94411f5 651 #define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
Kojto 116:c0f6e94411f5 652
Kojto 116:c0f6e94411f5 653 #define __HAL_RCC_CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
Kojto 116:c0f6e94411f5 654 #define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
Kojto 116:c0f6e94411f5 655 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 656
Kojto 116:c0f6e94411f5 657
Kojto 116:c0f6e94411f5 658 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 659 #define __HAL_RCC_LCD_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN))
Kojto 116:c0f6e94411f5 660 #define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
Kojto 116:c0f6e94411f5 661 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
Kojto 116:c0f6e94411f5 662
Kojto 116:c0f6e94411f5 663 #if defined(STM32L053xx) || defined(STM32L063xx) || \
Kojto 116:c0f6e94411f5 664 defined(STM32L052xx) || defined(STM32L062xx) || \
Kojto 116:c0f6e94411f5 665 defined(STM32L051xx) || defined(STM32L061xx)
Kojto 116:c0f6e94411f5 666 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
Kojto 116:c0f6e94411f5 667 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
Kojto 116:c0f6e94411f5 668 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
Kojto 116:c0f6e94411f5 669 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
Kojto 116:c0f6e94411f5 670 #define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
Kojto 116:c0f6e94411f5 671 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
Kojto 116:c0f6e94411f5 672 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
Kojto 116:c0f6e94411f5 673 #define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
Kojto 116:c0f6e94411f5 674 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
Kojto 116:c0f6e94411f5 675
Kojto 116:c0f6e94411f5 676 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
Kojto 116:c0f6e94411f5 677 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
Kojto 116:c0f6e94411f5 678 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
Kojto 116:c0f6e94411f5 679 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
Kojto 116:c0f6e94411f5 680 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
Kojto 116:c0f6e94411f5 681 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
Kojto 116:c0f6e94411f5 682 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
Kojto 116:c0f6e94411f5 683 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
Kojto 116:c0f6e94411f5 684 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
Kojto 116:c0f6e94411f5 685 #endif /* STM32L051xx || STM32L061xx || */
Kojto 116:c0f6e94411f5 686 /* STM32L052xx || STM32L062xx || */
Kojto 116:c0f6e94411f5 687 /* STM32L053xx || STM32L063xx || */
Kojto 116:c0f6e94411f5 688
Kojto 116:c0f6e94411f5 689 #if defined(STM32L031xx) || defined(STM32L041xx)
Kojto 116:c0f6e94411f5 690 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
Kojto 116:c0f6e94411f5 691 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
Kojto 116:c0f6e94411f5 692 #define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
Kojto 116:c0f6e94411f5 693 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
Kojto 116:c0f6e94411f5 694 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
Kojto 116:c0f6e94411f5 695
Kojto 116:c0f6e94411f5 696 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
Kojto 116:c0f6e94411f5 697 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
Kojto 116:c0f6e94411f5 698 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
Kojto 116:c0f6e94411f5 699 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
Kojto 116:c0f6e94411f5 700 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
Kojto 116:c0f6e94411f5 701 #endif /* STM32L031xx || STM32L041xx || */
Kojto 116:c0f6e94411f5 702
Kojto 116:c0f6e94411f5 703
Kojto 116:c0f6e94411f5 704 #if defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 705 defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 706 defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 707 #define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
Kojto 116:c0f6e94411f5 708 #define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
Kojto 116:c0f6e94411f5 709 #define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
Kojto 116:c0f6e94411f5 710 #define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
Kojto 116:c0f6e94411f5 711 #define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
Kojto 116:c0f6e94411f5 712 #define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
Kojto 116:c0f6e94411f5 713 #define __HAL_RCC_USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
Kojto 116:c0f6e94411f5 714 #define __HAL_RCC_USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
Kojto 116:c0f6e94411f5 715 #define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPUART1EN))
Kojto 116:c0f6e94411f5 716 #define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
Kojto 116:c0f6e94411f5 717 #define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
Kojto 116:c0f6e94411f5 718 #define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
Kojto 116:c0f6e94411f5 719 #define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
Kojto 116:c0f6e94411f5 720 #define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_LPTIM1EN))
Kojto 116:c0f6e94411f5 721
Kojto 116:c0f6e94411f5 722 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
Kojto 116:c0f6e94411f5 723 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM3EN))
Kojto 116:c0f6e94411f5 724 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
Kojto 116:c0f6e94411f5 725 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM7EN))
Kojto 116:c0f6e94411f5 726 #define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
Kojto 116:c0f6e94411f5 727 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
Kojto 116:c0f6e94411f5 728 #define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART4EN))
Kojto 116:c0f6e94411f5 729 #define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART5EN))
Kojto 116:c0f6e94411f5 730 #define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
Kojto 116:c0f6e94411f5 731 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
Kojto 116:c0f6e94411f5 732 #define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
Kojto 116:c0f6e94411f5 733 #define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C3EN))
Kojto 116:c0f6e94411f5 734 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
Kojto 116:c0f6e94411f5 735 #define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
Kojto 116:c0f6e94411f5 736 #endif /* STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 737 /* STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 738 /* STM32L073xx || STM32L083xx */
Kojto 116:c0f6e94411f5 739
Kojto 116:c0f6e94411f5 740 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 741 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 742 defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx) || \
Kojto 116:c0f6e94411f5 743 defined(STM32L031xx) || defined(STM32L041xx)
Kojto 116:c0f6e94411f5 744
Kojto 116:c0f6e94411f5 745 /** @brief Enable or disable the APB2 peripheral clock.
Kojto 116:c0f6e94411f5 746 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 116:c0f6e94411f5 747 * is disabled and the application software has to enable this clock before
Kojto 116:c0f6e94411f5 748 * using it.
Kojto 116:c0f6e94411f5 749 */
Kojto 116:c0f6e94411f5 750 #define __HAL_RCC_TIM21_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM21EN))
Kojto 116:c0f6e94411f5 751 #define __HAL_RCC_TIM22_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM22EN))
Kojto 116:c0f6e94411f5 752 #define __HAL_RCC_FIREWALL_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_MIFIEN))
Kojto 116:c0f6e94411f5 753 #define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
Kojto 116:c0f6e94411f5 754 #define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
Kojto 116:c0f6e94411f5 755 #define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
Kojto 116:c0f6e94411f5 756
Kojto 116:c0f6e94411f5 757 #define __HAL_RCC_TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN))
Kojto 116:c0f6e94411f5 758 #define __HAL_RCC_TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN))
Kojto 116:c0f6e94411f5 759 #define __HAL_RCC_FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN))
Kojto 116:c0f6e94411f5 760 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN))
Kojto 116:c0f6e94411f5 761 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN))
Kojto 116:c0f6e94411f5 762 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN))
Kojto 116:c0f6e94411f5 763 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 764 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 765 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
Kojto 116:c0f6e94411f5 766
Kojto 116:c0f6e94411f5 767 /** @brief Force or release AHB peripheral reset.
Kojto 116:c0f6e94411f5 768 */
Kojto 116:c0f6e94411f5 769 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 770 #define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_CRYPRST))
Kojto 116:c0f6e94411f5 771 #define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
Kojto 116:c0f6e94411f5 772 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
Kojto 116:c0f6e94411f5 773
Kojto 116:c0f6e94411f5 774 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 775 #define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
Kojto 116:c0f6e94411f5 776 #define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
Kojto 116:c0f6e94411f5 777 #define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_RNGRST))
Kojto 116:c0f6e94411f5 778 #define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
Kojto 116:c0f6e94411f5 779 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 780
Kojto 116:c0f6e94411f5 781 /** @brief Force or release IOPORT peripheral reset.
Kojto 116:c0f6e94411f5 782 */
Kojto 116:c0f6e94411f5 783 #if defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 784 defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 785 defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 786 #define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->IOPRSTR |= (RCC_IOPRSTR_GPIOERST))
Kojto 116:c0f6e94411f5 787
Kojto 116:c0f6e94411f5 788 #define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOERST))
Kojto 116:c0f6e94411f5 789
Kojto 116:c0f6e94411f5 790 #endif /* STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 791 /* STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 792 /* STM32L073xx || STM32L083xx */
Kojto 116:c0f6e94411f5 793
Kojto 116:c0f6e94411f5 794 /** @brief Force or release APB1 peripheral reset.
Kojto 116:c0f6e94411f5 795 */
Kojto 116:c0f6e94411f5 796
Kojto 116:c0f6e94411f5 797 #if defined(STM32L053xx) || defined(STM32L063xx) || \
Kojto 116:c0f6e94411f5 798 defined(STM32L052xx) || defined(STM32L062xx) || \
Kojto 116:c0f6e94411f5 799 defined(STM32L051xx) || defined(STM32L061xx)
Kojto 116:c0f6e94411f5 800 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 116:c0f6e94411f5 801 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 116:c0f6e94411f5 802 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
Kojto 116:c0f6e94411f5 803 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 116:c0f6e94411f5 804 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 116:c0f6e94411f5 805 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 116:c0f6e94411f5 806 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
Kojto 116:c0f6e94411f5 807 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 116:c0f6e94411f5 808 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 116:c0f6e94411f5 809
Kojto 116:c0f6e94411f5 810 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
Kojto 116:c0f6e94411f5 811 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
Kojto 116:c0f6e94411f5 812 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
Kojto 116:c0f6e94411f5 813 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
Kojto 116:c0f6e94411f5 814 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
Kojto 116:c0f6e94411f5 815 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
Kojto 116:c0f6e94411f5 816 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
Kojto 116:c0f6e94411f5 817 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
Kojto 116:c0f6e94411f5 818 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
Kojto 116:c0f6e94411f5 819 #endif /* STM32L051xx || STM32L061xx || */
Kojto 116:c0f6e94411f5 820 /* STM32L052xx || STM32L062xx || */
Kojto 116:c0f6e94411f5 821 /* STM32L053xx || STM32L063xx */
Kojto 116:c0f6e94411f5 822 #if defined(STM32L031xx) || defined(STM32L041xx)
Kojto 116:c0f6e94411f5 823 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 116:c0f6e94411f5 824 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
Kojto 116:c0f6e94411f5 825 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 116:c0f6e94411f5 826 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 116:c0f6e94411f5 827 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
Kojto 116:c0f6e94411f5 828
Kojto 116:c0f6e94411f5 829 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
Kojto 116:c0f6e94411f5 830 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
Kojto 116:c0f6e94411f5 831 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
Kojto 116:c0f6e94411f5 832 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
Kojto 116:c0f6e94411f5 833 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
Kojto 116:c0f6e94411f5 834 #endif /* STM32L031xx || STM32L041xx || */
Kojto 116:c0f6e94411f5 835
Kojto 116:c0f6e94411f5 836 #if defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 837 defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 838 defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 839 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 116:c0f6e94411f5 840 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 116:c0f6e94411f5 841 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 116:c0f6e94411f5 842 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 116:c0f6e94411f5 843 #define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPTIM1RST))
Kojto 116:c0f6e94411f5 844 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
Kojto 116:c0f6e94411f5 845 #define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 116:c0f6e94411f5 846 #define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 116:c0f6e94411f5 847 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 116:c0f6e94411f5 848 #define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
Kojto 116:c0f6e94411f5 849 #define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
Kojto 116:c0f6e94411f5 850 #define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LPUART1RST))
Kojto 116:c0f6e94411f5 851 #define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 116:c0f6e94411f5 852 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 116:c0f6e94411f5 853
Kojto 116:c0f6e94411f5 854 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
Kojto 116:c0f6e94411f5 855 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM3RST))
Kojto 116:c0f6e94411f5 856 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
Kojto 116:c0f6e94411f5 857 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM7RST))
Kojto 116:c0f6e94411f5 858 #define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
Kojto 116:c0f6e94411f5 859 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
Kojto 116:c0f6e94411f5 860 #define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
Kojto 116:c0f6e94411f5 861 #define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C3RST))
Kojto 116:c0f6e94411f5 862 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
Kojto 116:c0f6e94411f5 863 #define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART4RST))
Kojto 116:c0f6e94411f5 864 #define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART5RST))
Kojto 116:c0f6e94411f5 865 #define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
Kojto 116:c0f6e94411f5 866 #define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
Kojto 116:c0f6e94411f5 867 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
Kojto 116:c0f6e94411f5 868 #endif /* STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 869 /* STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 870 /* STM32L073xx || STM32L083xx || */
Kojto 116:c0f6e94411f5 871
Kojto 116:c0f6e94411f5 872 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 873 #define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
Kojto 116:c0f6e94411f5 874 #define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
Kojto 116:c0f6e94411f5 875 #define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
Kojto 116:c0f6e94411f5 876 #define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
Kojto 116:c0f6e94411f5 877 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 878
Kojto 116:c0f6e94411f5 879 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 880 #define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
Kojto 116:c0f6e94411f5 881 #define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
Kojto 116:c0f6e94411f5 882 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
Kojto 116:c0f6e94411f5 883
Kojto 116:c0f6e94411f5 884 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 885 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 886 defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 887 /** @brief Force or release APB2 peripheral reset.
Kojto 116:c0f6e94411f5 888 */
Kojto 116:c0f6e94411f5 889 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
Kojto 116:c0f6e94411f5 890 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
Kojto 116:c0f6e94411f5 891 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 116:c0f6e94411f5 892 #define __HAL_RCC_TIM21_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM21RST))
Kojto 116:c0f6e94411f5 893 #define __HAL_RCC_TIM22_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM22RST))
Kojto 116:c0f6e94411f5 894
Kojto 116:c0f6e94411f5 895 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
Kojto 116:c0f6e94411f5 896 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
Kojto 116:c0f6e94411f5 897 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
Kojto 116:c0f6e94411f5 898 #define __HAL_RCC_TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
Kojto 116:c0f6e94411f5 899 #define __HAL_RCC_TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
Kojto 116:c0f6e94411f5 900 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 901 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 902 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
Kojto 116:c0f6e94411f5 903
Kojto 116:c0f6e94411f5 904 /** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
Kojto 116:c0f6e94411f5 905 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 116:c0f6e94411f5 906 * power consumption.
Kojto 116:c0f6e94411f5 907 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 116:c0f6e94411f5 908 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 116:c0f6e94411f5 909 */
Kojto 116:c0f6e94411f5 910
Kojto 116:c0f6e94411f5 911 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 912 #define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_TSCSMEN))
Kojto 116:c0f6e94411f5 913 #define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR |= (RCC_AHBSMENR_RNGSMEN))
Kojto 116:c0f6e94411f5 914 #define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN))
Kojto 116:c0f6e94411f5 915 #define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN))
Kojto 116:c0f6e94411f5 916 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 917
Kojto 116:c0f6e94411f5 918 #if defined(STM32L062xx) || defined(STM32L063xx)|| defined(STM32L082xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 919 #define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR |= (RCC_AHBSMENR_CRYPSMEN))
Kojto 116:c0f6e94411f5 920 #define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN))
Kojto 116:c0f6e94411f5 921 #endif /* STM32L062xx || STM32L063xx || STM32L072xx || STM32L073xx || STM32L082xx || STM32L083xx */
Kojto 116:c0f6e94411f5 922
Kojto 116:c0f6e94411f5 923 #if defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 924 defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 925 defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 926 /** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
Kojto 116:c0f6e94411f5 927 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 116:c0f6e94411f5 928 * power consumption.
Kojto 116:c0f6e94411f5 929 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 116:c0f6e94411f5 930 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 116:c0f6e94411f5 931 */
Kojto 116:c0f6e94411f5 932
Kojto 116:c0f6e94411f5 933 #define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->IOPSMENR |= (RCC_IOPSMENR_GPIOESMEN))
Kojto 116:c0f6e94411f5 934 #define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOESMEN))
Kojto 116:c0f6e94411f5 935
Kojto 116:c0f6e94411f5 936 #endif /* STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 937 /* STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 938 /* STM32L073xx || STM32L083xx || */
Kojto 116:c0f6e94411f5 939
Kojto 116:c0f6e94411f5 940 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 116:c0f6e94411f5 941 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 116:c0f6e94411f5 942 * power consumption.
Kojto 116:c0f6e94411f5 943 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 116:c0f6e94411f5 944 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 116:c0f6e94411f5 945 */
Kojto 116:c0f6e94411f5 946
Kojto 116:c0f6e94411f5 947 #if defined(STM32L053xx) || defined(STM32L063xx) || \
Kojto 116:c0f6e94411f5 948 defined(STM32L052xx) || defined(STM32L062xx) || \
Kojto 116:c0f6e94411f5 949 defined(STM32L051xx) || defined(STM32L061xx)
Kojto 116:c0f6e94411f5 950 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
Kojto 116:c0f6e94411f5 951 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
Kojto 116:c0f6e94411f5 952 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
Kojto 116:c0f6e94411f5 953 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
Kojto 116:c0f6e94411f5 954 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
Kojto 116:c0f6e94411f5 955 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
Kojto 116:c0f6e94411f5 956 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
Kojto 116:c0f6e94411f5 957 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
Kojto 116:c0f6e94411f5 958 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
Kojto 116:c0f6e94411f5 959
Kojto 116:c0f6e94411f5 960 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
Kojto 116:c0f6e94411f5 961 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
Kojto 116:c0f6e94411f5 962 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
Kojto 116:c0f6e94411f5 963 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
Kojto 116:c0f6e94411f5 964 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
Kojto 116:c0f6e94411f5 965 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
Kojto 116:c0f6e94411f5 966 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
Kojto 116:c0f6e94411f5 967 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
Kojto 116:c0f6e94411f5 968 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
Kojto 116:c0f6e94411f5 969 #endif /* STM32L051xx || STM32L061xx || */
Kojto 116:c0f6e94411f5 970 /* STM32L052xx || STM32L062xx || */
Kojto 116:c0f6e94411f5 971 /* STM32L053xx || STM32L063xx */
Kojto 116:c0f6e94411f5 972
Kojto 116:c0f6e94411f5 973 #if defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 974 defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 975 defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 976 #define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM2SMEN))
Kojto 116:c0f6e94411f5 977 #define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM3SMEN))
Kojto 116:c0f6e94411f5 978 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM6SMEN))
Kojto 116:c0f6e94411f5 979 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_TIM7SMEN))
Kojto 116:c0f6e94411f5 980 #define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_SPI2SMEN))
Kojto 116:c0f6e94411f5 981 #define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART2SMEN))
Kojto 116:c0f6e94411f5 982 #define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART4SMEN))
Kojto 116:c0f6e94411f5 983 #define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USART5SMEN))
Kojto 116:c0f6e94411f5 984 #define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPUART1SMEN))
Kojto 116:c0f6e94411f5 985 #define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C1SMEN))
Kojto 116:c0f6e94411f5 986 #define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C2SMEN))
Kojto 116:c0f6e94411f5 987 #define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_I2C3SMEN))
Kojto 116:c0f6e94411f5 988 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_DACSMEN))
Kojto 116:c0f6e94411f5 989 #define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LPTIM1SMEN))
Kojto 116:c0f6e94411f5 990
Kojto 116:c0f6e94411f5 991 #define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
Kojto 116:c0f6e94411f5 992 #define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM3SMEN))
Kojto 116:c0f6e94411f5 993 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
Kojto 116:c0f6e94411f5 994 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM7SMEN))
Kojto 116:c0f6e94411f5 995 #define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
Kojto 116:c0f6e94411f5 996 #define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
Kojto 116:c0f6e94411f5 997 #define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART4SMEN))
Kojto 116:c0f6e94411f5 998 #define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART5SMEN))
Kojto 116:c0f6e94411f5 999 #define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
Kojto 116:c0f6e94411f5 1000 #define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
Kojto 116:c0f6e94411f5 1001 #define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
Kojto 116:c0f6e94411f5 1002 #define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C3SMEN))
Kojto 116:c0f6e94411f5 1003 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
Kojto 116:c0f6e94411f5 1004 #define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
Kojto 116:c0f6e94411f5 1005 #endif /* STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 1006 /* STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 1007 /* STM32L073xx || STM32L083xx || */
Kojto 116:c0f6e94411f5 1008
Kojto 116:c0f6e94411f5 1009 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 1010 #define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_USBSMEN))
Kojto 116:c0f6e94411f5 1011 #define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
Kojto 116:c0f6e94411f5 1012 #define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_CRSSMEN))
Kojto 116:c0f6e94411f5 1013 #define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
Kojto 116:c0f6e94411f5 1014 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 1015
Kojto 116:c0f6e94411f5 1016 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx)
Kojto 116:c0f6e94411f5 1017 #define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR |= (RCC_APB1SMENR_LCDSMEN))
Kojto 116:c0f6e94411f5 1018 #define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
Kojto 116:c0f6e94411f5 1019 #endif /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx */
Kojto 116:c0f6e94411f5 1020
Kojto 116:c0f6e94411f5 1021 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 1022 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 1023 defined(STM32L051xx) || defined(STM32L061xx) || defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 1024 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 116:c0f6e94411f5 1025 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 116:c0f6e94411f5 1026 * power consumption.
Kojto 116:c0f6e94411f5 1027 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 116:c0f6e94411f5 1028 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 116:c0f6e94411f5 1029 */
Kojto 116:c0f6e94411f5 1030 #define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM21SMEN))
Kojto 116:c0f6e94411f5 1031 #define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_TIM22SMEN))
Kojto 116:c0f6e94411f5 1032 #define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_ADC1SMEN))
Kojto 116:c0f6e94411f5 1033 #define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_SPI1SMEN))
Kojto 116:c0f6e94411f5 1034 #define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR |= (RCC_APB2SMENR_USART1SMEN))
Kojto 116:c0f6e94411f5 1035
Kojto 116:c0f6e94411f5 1036 #define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN))
Kojto 116:c0f6e94411f5 1037 #define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN))
Kojto 116:c0f6e94411f5 1038 #define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN))
Kojto 116:c0f6e94411f5 1039 #define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN))
Kojto 116:c0f6e94411f5 1040 #define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN))
Kojto 116:c0f6e94411f5 1041 #endif /* STM32L051xx || STM32L061xx || STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 1042 /* STM32L052xx || STM32L062xx || STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 1043 /* STM32L053xx || STM32L063xx || STM32L073xx || STM32L083xx || */
Kojto 116:c0f6e94411f5 1044
Kojto 116:c0f6e94411f5 1045 /** @brief macro to configure the I2C1 clock (I2C1CLK).
Kojto 116:c0f6e94411f5 1046 *
Kojto 116:c0f6e94411f5 1047 * @param __I2C1CLKSource__: specifies the I2C1 clock source.
Kojto 116:c0f6e94411f5 1048 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1049 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto 116:c0f6e94411f5 1050 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 116:c0f6e94411f5 1051 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 116:c0f6e94411f5 1052 */
Kojto 116:c0f6e94411f5 1053 #define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
Kojto 116:c0f6e94411f5 1054 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1CLKSource__))
Kojto 116:c0f6e94411f5 1055
Kojto 116:c0f6e94411f5 1056 /** @brief macro to get the I2C1 clock source.
Kojto 116:c0f6e94411f5 1057 * @retval The clock source can be one of the following values:
Kojto 116:c0f6e94411f5 1058 * @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
Kojto 116:c0f6e94411f5 1059 * @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto 116:c0f6e94411f5 1060 * @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto 116:c0f6e94411f5 1061 */
Kojto 116:c0f6e94411f5 1062 #define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
Kojto 116:c0f6e94411f5 1063
Kojto 116:c0f6e94411f5 1064 #if defined (STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 1065 defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 1066 defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 1067 /** @brief macro to configure the I2C3 clock (I2C3CLK).
Kojto 116:c0f6e94411f5 1068 *
Kojto 116:c0f6e94411f5 1069 * @param __I2C3CLKSource__: specifies the I2C3 clock source.
Kojto 116:c0f6e94411f5 1070 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1071 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto 116:c0f6e94411f5 1072 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 116:c0f6e94411f5 1073 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 116:c0f6e94411f5 1074 */
Kojto 116:c0f6e94411f5 1075 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
Kojto 116:c0f6e94411f5 1076 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3CLKSource__))
Kojto 116:c0f6e94411f5 1077
Kojto 116:c0f6e94411f5 1078 /** @brief macro to get the I2C3 clock source.
Kojto 116:c0f6e94411f5 1079 * @retval The clock source can be one of the following values:
Kojto 116:c0f6e94411f5 1080 * @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto 116:c0f6e94411f5 1081 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 116:c0f6e94411f5 1082 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 116:c0f6e94411f5 1083 */
Kojto 116:c0f6e94411f5 1084 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
Kojto 116:c0f6e94411f5 1085
Kojto 116:c0f6e94411f5 1086 #endif /* STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 1087 /* STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 1088 /* STM32L073xx || STM32L083xx || */
Kojto 116:c0f6e94411f5 1089
Kojto 116:c0f6e94411f5 1090 /** @brief macro to configure the USART1 clock (USART1CLK).
Kojto 116:c0f6e94411f5 1091 *
Kojto 116:c0f6e94411f5 1092 * @param __USART1CLKSource__: specifies the USART1 clock source.
Kojto 116:c0f6e94411f5 1093 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1094 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto 116:c0f6e94411f5 1095 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 116:c0f6e94411f5 1096 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 116:c0f6e94411f5 1097 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 116:c0f6e94411f5 1098 */
Kojto 116:c0f6e94411f5 1099 #define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
Kojto 116:c0f6e94411f5 1100 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1CLKSource__))
Kojto 116:c0f6e94411f5 1101
Kojto 116:c0f6e94411f5 1102 /** @brief macro to get the USART1 clock source.
Kojto 116:c0f6e94411f5 1103 * @retval The clock source can be one of the following values:
Kojto 116:c0f6e94411f5 1104 * @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
Kojto 116:c0f6e94411f5 1105 * @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto 116:c0f6e94411f5 1106 * @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto 116:c0f6e94411f5 1107 * @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto 116:c0f6e94411f5 1108 */
Kojto 116:c0f6e94411f5 1109 #define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
Kojto 116:c0f6e94411f5 1110
Kojto 116:c0f6e94411f5 1111 /** @brief macro to configure the USART2 clock (USART2CLK).
Kojto 116:c0f6e94411f5 1112 *
Kojto 116:c0f6e94411f5 1113 * @param __USART2CLKSource__: specifies the USART2 clock source.
Kojto 116:c0f6e94411f5 1114 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1115 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 116:c0f6e94411f5 1116 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 116:c0f6e94411f5 1117 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 116:c0f6e94411f5 1118 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 116:c0f6e94411f5 1119 */
Kojto 116:c0f6e94411f5 1120 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
Kojto 116:c0f6e94411f5 1121 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2CLKSource__))
Kojto 116:c0f6e94411f5 1122
Kojto 116:c0f6e94411f5 1123 /** @brief macro to get the USART2 clock source.
Kojto 116:c0f6e94411f5 1124 * @retval The clock source can be one of the following values:
Kojto 116:c0f6e94411f5 1125 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 116:c0f6e94411f5 1126 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 116:c0f6e94411f5 1127 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 116:c0f6e94411f5 1128 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 116:c0f6e94411f5 1129 */
Kojto 116:c0f6e94411f5 1130 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
Kojto 116:c0f6e94411f5 1131
Kojto 116:c0f6e94411f5 1132 /** @brief macro to configure the LPUART1 clock (LPUART1CLK).
Kojto 116:c0f6e94411f5 1133 *
Kojto 116:c0f6e94411f5 1134 * @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
Kojto 116:c0f6e94411f5 1135 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1136 * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1137 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1138 * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1139 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1140 */
Kojto 116:c0f6e94411f5 1141 #define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
Kojto 116:c0f6e94411f5 1142 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
Kojto 116:c0f6e94411f5 1143
Kojto 116:c0f6e94411f5 1144 /** @brief macro to get the LPUART1 clock source.
Kojto 116:c0f6e94411f5 1145 * @retval The clock source can be one of the following values:
Kojto 116:c0f6e94411f5 1146 * @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1147 * @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1148 * @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1149 * @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1150 */
Kojto 116:c0f6e94411f5 1151 #define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
Kojto 116:c0f6e94411f5 1152
Kojto 116:c0f6e94411f5 1153 /** @brief macro to configure the LPTIM1 clock (LPTIM1CLK).
Kojto 116:c0f6e94411f5 1154 *
Kojto 116:c0f6e94411f5 1155 * @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source.
Kojto 116:c0f6e94411f5 1156 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1157 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
Kojto 116:c0f6e94411f5 1158 * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
Kojto 116:c0f6e94411f5 1159 * @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
Kojto 116:c0f6e94411f5 1160 * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
Kojto 116:c0f6e94411f5 1161 */
Kojto 116:c0f6e94411f5 1162 #define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
Kojto 116:c0f6e94411f5 1163 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
Kojto 116:c0f6e94411f5 1164
Kojto 116:c0f6e94411f5 1165 /** @brief macro to get the LPTIM1 clock source.
Kojto 116:c0f6e94411f5 1166 * @retval The clock source can be one of the following values:
Kojto 116:c0f6e94411f5 1167 * @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1168 * @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1169 * @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1170 * @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock
Kojto 116:c0f6e94411f5 1171 */
Kojto 116:c0f6e94411f5 1172 #define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
Kojto 116:c0f6e94411f5 1173
Kojto 116:c0f6e94411f5 1174 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 1175 /** @brief Macro to configure the USB clock (USBCLK).
Kojto 116:c0f6e94411f5 1176 * @param __USBCLKSource__: specifies the USB clock source.
Kojto 116:c0f6e94411f5 1177 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1178 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
Kojto 116:c0f6e94411f5 1179 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto 116:c0f6e94411f5 1180 */
Kojto 116:c0f6e94411f5 1181 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
Kojto 116:c0f6e94411f5 1182 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
Kojto 116:c0f6e94411f5 1183
Kojto 116:c0f6e94411f5 1184 /** @brief Macro to get the USB clock source.
Kojto 116:c0f6e94411f5 1185 * @retval The clock source can be one of the following values:
Kojto 116:c0f6e94411f5 1186 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
Kojto 116:c0f6e94411f5 1187 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto 116:c0f6e94411f5 1188 */
Kojto 116:c0f6e94411f5 1189 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
Kojto 116:c0f6e94411f5 1190
Kojto 116:c0f6e94411f5 1191 /** @brief Macro to configure the RNG clock (RNGCLK).
Kojto 116:c0f6e94411f5 1192 * @param __RNGCLKSource__: specifies the USB clock source.
Kojto 116:c0f6e94411f5 1193 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1194 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
Kojto 116:c0f6e94411f5 1195 * @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
Kojto 116:c0f6e94411f5 1196 */
Kojto 116:c0f6e94411f5 1197 #define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
Kojto 116:c0f6e94411f5 1198 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNGCLKSource__))
Kojto 116:c0f6e94411f5 1199
Kojto 116:c0f6e94411f5 1200 /** @brief Macro to get the RNG clock source.
Kojto 116:c0f6e94411f5 1201 * @retval The clock source can be one of the following values:
Kojto 116:c0f6e94411f5 1202 * @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
Kojto 116:c0f6e94411f5 1203 * @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
Kojto 116:c0f6e94411f5 1204 */
Kojto 116:c0f6e94411f5 1205 #define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
Kojto 116:c0f6e94411f5 1206
Kojto 116:c0f6e94411f5 1207 /** @brief macro to select the HSI48M clock source
Kojto 116:c0f6e94411f5 1208 * @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
Kojto 116:c0f6e94411f5 1209 * __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
Kojto 116:c0f6e94411f5 1210 *
Kojto 116:c0f6e94411f5 1211 * @param __HSI48MCLKSource__: specifies the HSI48M clock source dedicated for
Kojto 116:c0f6e94411f5 1212 * USB an RNG peripherals.
Kojto 116:c0f6e94411f5 1213 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1214 * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
Kojto 116:c0f6e94411f5 1215 * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
Kojto 116:c0f6e94411f5 1216 */
Kojto 116:c0f6e94411f5 1217 #define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \
Kojto 116:c0f6e94411f5 1218 MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__))
Kojto 116:c0f6e94411f5 1219
Kojto 116:c0f6e94411f5 1220 /** @brief macro to get the HSI48M clock source.
Kojto 116:c0f6e94411f5 1221 * @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
Kojto 116:c0f6e94411f5 1222 * __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
Kojto 116:c0f6e94411f5 1223 * @retval The clock source can be one of the following values:
Kojto 116:c0f6e94411f5 1224 * @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
Kojto 116:c0f6e94411f5 1225 * @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
Kojto 116:c0f6e94411f5 1226 */
Kojto 116:c0f6e94411f5 1227 #define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
Kojto 116:c0f6e94411f5 1228 #endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto 116:c0f6e94411f5 1229
Kojto 116:c0f6e94411f5 1230 /**
Kojto 116:c0f6e94411f5 1231 * @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
Kojto 116:c0f6e94411f5 1232 * in STOP mode to be quickly available as kernel clock for USART and I2C.
Kojto 116:c0f6e94411f5 1233 * @note The Enable of this function has not effect on the HSION bit.
Kojto 116:c0f6e94411f5 1234 * This parameter can be: ENABLE or DISABLE.
Kojto 116:c0f6e94411f5 1235 * @retval None
Kojto 116:c0f6e94411f5 1236 */
Kojto 116:c0f6e94411f5 1237 #define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
Kojto 116:c0f6e94411f5 1238 #define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
Kojto 116:c0f6e94411f5 1239
Kojto 116:c0f6e94411f5 1240 /**
Kojto 116:c0f6e94411f5 1241 * @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
Kojto 116:c0f6e94411f5 1242 * @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
Kojto 116:c0f6e94411f5 1243 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1244 * @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
Kojto 116:c0f6e94411f5 1245 * @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
Kojto 116:c0f6e94411f5 1246 * @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
Kojto 116:c0f6e94411f5 1247 * @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
Kojto 116:c0f6e94411f5 1248 * @retval None
Kojto 116:c0f6e94411f5 1249 */
Kojto 116:c0f6e94411f5 1250 #define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDrive__) (MODIFY_REG(RCC->CSR,\
Kojto 116:c0f6e94411f5 1251 RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDrive__) ))
Kojto 116:c0f6e94411f5 1252
Kojto 116:c0f6e94411f5 1253 /**
Kojto 116:c0f6e94411f5 1254 * @brief Macro to configures the wake up from stop clock.
Kojto 116:c0f6e94411f5 1255 * @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop
Kojto 116:c0f6e94411f5 1256 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1257 * @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
Kojto 116:c0f6e94411f5 1258 * @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
Kojto 116:c0f6e94411f5 1259 * @retval None
Kojto 116:c0f6e94411f5 1260 */
Kojto 116:c0f6e94411f5 1261 #define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
Kojto 116:c0f6e94411f5 1262 RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
Kojto 116:c0f6e94411f5 1263
Kojto 116:c0f6e94411f5 1264 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 1265 /**
Kojto 116:c0f6e94411f5 1266 * @brief Enables the specified CRS interrupts.
Kojto 116:c0f6e94411f5 1267 * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
Kojto 116:c0f6e94411f5 1268 * This parameter can be any combination of the following values:
Kojto 116:c0f6e94411f5 1269 * @arg RCC_CRS_IT_SYNCOK
Kojto 116:c0f6e94411f5 1270 * @arg RCC_CRS_IT_SYNCWARN
Kojto 116:c0f6e94411f5 1271 * @arg RCC_CRS_IT_ERR
Kojto 116:c0f6e94411f5 1272 * @arg RCC_CRS_IT_ESYNC
Kojto 116:c0f6e94411f5 1273 * @retval None
Kojto 116:c0f6e94411f5 1274 */
Kojto 116:c0f6e94411f5 1275 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__))
Kojto 116:c0f6e94411f5 1276
Kojto 116:c0f6e94411f5 1277 /**
Kojto 116:c0f6e94411f5 1278 * @brief Disables the specified CRS interrupts.
Kojto 116:c0f6e94411f5 1279 * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
Kojto 116:c0f6e94411f5 1280 * This parameter can be any combination of the following values:
Kojto 116:c0f6e94411f5 1281 * @arg RCC_CRS_IT_SYNCOK
Kojto 116:c0f6e94411f5 1282 * @arg RCC_CRS_IT_SYNCWARN
Kojto 116:c0f6e94411f5 1283 * @arg RCC_CRS_IT_ERR
Kojto 116:c0f6e94411f5 1284 * @arg RCC_CRS_IT_ESYNC
Kojto 116:c0f6e94411f5 1285 * @retval None
Kojto 116:c0f6e94411f5 1286 */
Kojto 116:c0f6e94411f5 1287 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
Kojto 116:c0f6e94411f5 1288
Kojto 116:c0f6e94411f5 1289 /** @brief Check the CRS interrupt has occurred or not.
Kojto 116:c0f6e94411f5 1290 * @param __INTERRUPT__: specifies the CRS interrupt source to check.
Kojto 116:c0f6e94411f5 1291 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1292 * @arg RCC_CRS_IT_SYNCOK
Kojto 116:c0f6e94411f5 1293 * @arg RCC_CRS_IT_SYNCWARN
Kojto 116:c0f6e94411f5 1294 * @arg RCC_CRS_IT_ERR
Kojto 116:c0f6e94411f5 1295 * @arg RCC_CRS_IT_ESYNC
Kojto 116:c0f6e94411f5 1296 * @retval The new state of __INTERRUPT__ (SET or RESET).
Kojto 116:c0f6e94411f5 1297 */
Kojto 116:c0f6e94411f5 1298 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
Kojto 116:c0f6e94411f5 1299
Kojto 116:c0f6e94411f5 1300 /** @brief Clear the CRS interrupt pending bits
Kojto 116:c0f6e94411f5 1301 * bits to clear the selected interrupt pending bits.
Kojto 116:c0f6e94411f5 1302 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 116:c0f6e94411f5 1303 * This parameter can be any combination of the following values:
Kojto 116:c0f6e94411f5 1304 * @arg RCC_CRS_IT_SYNCOK
Kojto 116:c0f6e94411f5 1305 * @arg RCC_CRS_IT_SYNCWARN
Kojto 116:c0f6e94411f5 1306 * @arg RCC_CRS_IT_ERR
Kojto 116:c0f6e94411f5 1307 * @arg RCC_CRS_IT_ESYNC
Kojto 116:c0f6e94411f5 1308 * @arg RCC_CRS_IT_TRIMOVF
Kojto 116:c0f6e94411f5 1309 * @arg RCC_CRS_IT_SYNCERR
Kojto 116:c0f6e94411f5 1310 * @arg RCC_CRS_IT_SYNCMISS
Kojto 116:c0f6e94411f5 1311 */
Kojto 116:c0f6e94411f5 1312 /* CRS IT Error Mask */
Kojto 116:c0f6e94411f5 1313 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
Kojto 116:c0f6e94411f5 1314
Kojto 116:c0f6e94411f5 1315 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
Kojto 116:c0f6e94411f5 1316 (CRS->ICR = (__INTERRUPT__)))
Kojto 116:c0f6e94411f5 1317
Kojto 116:c0f6e94411f5 1318 /**
Kojto 116:c0f6e94411f5 1319 * @brief Checks whether the specified CRS flag is set or not.
Kojto 116:c0f6e94411f5 1320 * @param _FLAG_: specifies the flag to check.
Kojto 116:c0f6e94411f5 1321 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1322 * @arg RCC_CRS_FLAG_SYNCOK
Kojto 116:c0f6e94411f5 1323 * @arg RCC_CRS_FLAG_SYNCWARN
Kojto 116:c0f6e94411f5 1324 * @arg RCC_CRS_FLAG_ERR
Kojto 116:c0f6e94411f5 1325 * @arg RCC_CRS_FLAG_ESYNC
Kojto 116:c0f6e94411f5 1326 * @arg RCC_CRS_FLAG_TRIMOVF
Kojto 116:c0f6e94411f5 1327 * @arg RCC_CRS_FLAG_SYNCERR
Kojto 116:c0f6e94411f5 1328 * @arg RCC_CRS_FLAG_SYNCMISS
Kojto 116:c0f6e94411f5 1329 * @retval The new state of _FLAG_ (TRUE or FALSE).
Kojto 116:c0f6e94411f5 1330 */
Kojto 116:c0f6e94411f5 1331 #define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
Kojto 116:c0f6e94411f5 1332
Kojto 116:c0f6e94411f5 1333 /**
Kojto 116:c0f6e94411f5 1334 * @brief Clears the CRS specified FLAG.
Kojto 116:c0f6e94411f5 1335 * @param _FLAG_: specifies the flag to clear.
Kojto 116:c0f6e94411f5 1336 * This parameter can be one of the following values:
Kojto 116:c0f6e94411f5 1337 * @arg RCC_CRS_FLAG_SYNCOK
Kojto 116:c0f6e94411f5 1338 * @arg RCC_CRS_FLAG_SYNCWARN
Kojto 116:c0f6e94411f5 1339 * @arg RCC_CRS_FLAG_ERR
Kojto 116:c0f6e94411f5 1340 * @arg RCC_CRS_FLAG_ESYNC
Kojto 116:c0f6e94411f5 1341 * @arg RCC_CRS_FLAG_TRIMOVF
Kojto 116:c0f6e94411f5 1342 * @arg RCC_CRS_FLAG_SYNCERR
Kojto 116:c0f6e94411f5 1343 * @arg RCC_CRS_FLAG_SYNCMISS
Kojto 116:c0f6e94411f5 1344 * @retval None
Kojto 116:c0f6e94411f5 1345 */
Kojto 116:c0f6e94411f5 1346
Kojto 116:c0f6e94411f5 1347 /* CRS Flag Error Mask */
Kojto 116:c0f6e94411f5 1348 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
Kojto 116:c0f6e94411f5 1349
Kojto 116:c0f6e94411f5 1350 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
Kojto 116:c0f6e94411f5 1351 (CRS->ICR = (__FLAG__)))
Kojto 116:c0f6e94411f5 1352
Kojto 116:c0f6e94411f5 1353
Kojto 116:c0f6e94411f5 1354 /**
Kojto 116:c0f6e94411f5 1355 * @brief Enables the oscillator clock for frequency error counter.
Kojto 116:c0f6e94411f5 1356 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 116:c0f6e94411f5 1357 * @param None
Kojto 116:c0f6e94411f5 1358 * @retval None
Kojto 116:c0f6e94411f5 1359 */
Kojto 116:c0f6e94411f5 1360 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
Kojto 116:c0f6e94411f5 1361
Kojto 116:c0f6e94411f5 1362 /**
Kojto 116:c0f6e94411f5 1363 * @brief Disables the oscillator clock for frequency error counter.
Kojto 116:c0f6e94411f5 1364 * @param None
Kojto 116:c0f6e94411f5 1365 * @retval None
Kojto 116:c0f6e94411f5 1366 */
Kojto 116:c0f6e94411f5 1367 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
Kojto 116:c0f6e94411f5 1368
Kojto 116:c0f6e94411f5 1369 /**
Kojto 116:c0f6e94411f5 1370 * @brief Enables the automatic hardware adjustment of TRIM bits.
Kojto 116:c0f6e94411f5 1371 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 116:c0f6e94411f5 1372 * @param None
Kojto 116:c0f6e94411f5 1373 * @retval None
Kojto 116:c0f6e94411f5 1374 */
Kojto 116:c0f6e94411f5 1375 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN)
Kojto 116:c0f6e94411f5 1376
Kojto 116:c0f6e94411f5 1377 /**
Kojto 116:c0f6e94411f5 1378 * @brief Enables or disables the automatic hardware adjustment of TRIM bits.
Kojto 116:c0f6e94411f5 1379 * @param None
Kojto 116:c0f6e94411f5 1380 * @retval None
Kojto 116:c0f6e94411f5 1381 */
Kojto 116:c0f6e94411f5 1382 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
Kojto 116:c0f6e94411f5 1383
Kojto 116:c0f6e94411f5 1384 /**
Kojto 116:c0f6e94411f5 1385 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
Kojto 116:c0f6e94411f5 1386 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
Kojto 116:c0f6e94411f5 1387 * of the synchronization source after prescaling. It is then decreased by one in order to
Kojto 116:c0f6e94411f5 1388 * reach the expected synchronization on the zero value. The formula is the following:
Kojto 116:c0f6e94411f5 1389 * RELOAD = (fTARGET / fSYNC) -1
Kojto 116:c0f6e94411f5 1390 * @param _FTARGET_ Target frequency (value in Hz)
Kojto 116:c0f6e94411f5 1391 * @param _FSYNC_ Synchronization signal frequency (value in Hz)
Kojto 116:c0f6e94411f5 1392 * @retval None
Kojto 116:c0f6e94411f5 1393 */
Kojto 116:c0f6e94411f5 1394 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
Kojto 116:c0f6e94411f5 1395
Kojto 116:c0f6e94411f5 1396 #endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
Kojto 116:c0f6e94411f5 1397
Kojto 116:c0f6e94411f5 1398 #if defined(STM32L073xx) || defined(STM32L083xx) || \
Kojto 116:c0f6e94411f5 1399 defined(STM32L072xx) || defined(STM32L082xx) || \
Kojto 116:c0f6e94411f5 1400 defined(STM32L071xx) || defined(STM32L081xx)
Kojto 116:c0f6e94411f5 1401 /** @brief Enable or disable the HSI OUT .
Kojto 116:c0f6e94411f5 1402 * @note After reset, the HSI output is not available
Kojto 116:c0f6e94411f5 1403 */
Kojto 116:c0f6e94411f5 1404
Kojto 116:c0f6e94411f5 1405 #define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
Kojto 116:c0f6e94411f5 1406 #define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
Kojto 116:c0f6e94411f5 1407
Kojto 116:c0f6e94411f5 1408 #endif /* STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 1409 /* STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 1410 /* STM32L073xx || STM32L083xx */
Kojto 116:c0f6e94411f5 1411
Kojto 116:c0f6e94411f5 1412 #if defined(STM32L053xx) || defined(STM32L063xx) || defined(STM32L073xx) || defined(STM32L083xx) ||\
Kojto 116:c0f6e94411f5 1413 defined(STM32L052xx) || defined(STM32L062xx) || defined(STM32L072xx) || defined(STM32L082xx)
Kojto 116:c0f6e94411f5 1414
Kojto 116:c0f6e94411f5 1415 /**
Kojto 116:c0f6e94411f5 1416 * @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
Kojto 116:c0f6e94411f5 1417 * @note After enabling the HSI48, the application software should wait on
Kojto 116:c0f6e94411f5 1418 * HSI48RDY flag to be set indicating that HSI48 clock is stable and can
Kojto 116:c0f6e94411f5 1419 * be used to clock the USB.
Kojto 116:c0f6e94411f5 1420 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
Kojto 116:c0f6e94411f5 1421 */
Kojto 116:c0f6e94411f5 1422 #define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
Kojto 116:c0f6e94411f5 1423 RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN; \
Kojto 116:c0f6e94411f5 1424 SYSCFG->CFGR3 |= (SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT); \
Kojto 116:c0f6e94411f5 1425 } while (0)
Kojto 116:c0f6e94411f5 1426 #define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
Kojto 116:c0f6e94411f5 1427 SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 | SYSCFG_CFGR3_EN_VREFINT)); \
Kojto 116:c0f6e94411f5 1428 } while (0)
Kojto 116:c0f6e94411f5 1429 /** @brief Enable or disable the HSI48M DIV6 OUT .
Kojto 116:c0f6e94411f5 1430 * @note After reset, the HSI48Mhz (divided by 6) output is not available
Kojto 116:c0f6e94411f5 1431 */
Kojto 116:c0f6e94411f5 1432
Kojto 116:c0f6e94411f5 1433 #define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
Kojto 116:c0f6e94411f5 1434 #define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
Kojto 116:c0f6e94411f5 1435
Kojto 116:c0f6e94411f5 1436 #endif /* STM32L071xx || STM32L081xx || */
Kojto 116:c0f6e94411f5 1437 /* STM32L072xx || STM32L082xx || */
Kojto 116:c0f6e94411f5 1438 /* STM32L073xx || STM32L083xx */
Kojto 116:c0f6e94411f5 1439
Kojto 116:c0f6e94411f5 1440 /**
Kojto 116:c0f6e94411f5 1441 * @}
Kojto 116:c0f6e94411f5 1442 */
Kojto 116:c0f6e94411f5 1443
Kojto 116:c0f6e94411f5 1444 /** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
Kojto 116:c0f6e94411f5 1445 * @{
Kojto 116:c0f6e94411f5 1446 */
Kojto 116:c0f6e94411f5 1447
Kojto 116:c0f6e94411f5 1448 /** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
Kojto 116:c0f6e94411f5 1449
Kojto 116:c0f6e94411f5 1450 * @{
Kojto 116:c0f6e94411f5 1451 */
Kojto 116:c0f6e94411f5 1452 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 116:c0f6e94411f5 1453 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 116:c0f6e94411f5 1454 void HAL_RCCEx_EnableLSECSS(void);
Kojto 116:c0f6e94411f5 1455 void HAL_RCCEx_DisableLSECSS(void);
Kojto 116:c0f6e94411f5 1456 #if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto 116:c0f6e94411f5 1457 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
Kojto 116:c0f6e94411f5 1458 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
Kojto 116:c0f6e94411f5 1459 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto 116:c0f6e94411f5 1460 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Kojto 116:c0f6e94411f5 1461 void HAL_RCCEx_EnableHSI48_VREFINT(void);
Kojto 116:c0f6e94411f5 1462 void HAL_RCCEx_DisableHSI48_VREFINT(void);
Kojto 116:c0f6e94411f5 1463 #endif /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
Kojto 116:c0f6e94411f5 1464
Kojto 116:c0f6e94411f5 1465 /**
Kojto 116:c0f6e94411f5 1466 * @}
Kojto 116:c0f6e94411f5 1467 */
Kojto 116:c0f6e94411f5 1468 /**
Kojto 116:c0f6e94411f5 1469 * @}
Kojto 116:c0f6e94411f5 1470 */
Kojto 116:c0f6e94411f5 1471
Kojto 116:c0f6e94411f5 1472 /**
Kojto 116:c0f6e94411f5 1473 * @}
Kojto 116:c0f6e94411f5 1474 */
Kojto 116:c0f6e94411f5 1475
Kojto 116:c0f6e94411f5 1476 /**
Kojto 116:c0f6e94411f5 1477 * @}
Kojto 116:c0f6e94411f5 1478 */
Kojto 116:c0f6e94411f5 1479
Kojto 116:c0f6e94411f5 1480 #ifdef __cplusplus
Kojto 116:c0f6e94411f5 1481 }
Kojto 116:c0f6e94411f5 1482 #endif
Kojto 116:c0f6e94411f5 1483
Kojto 116:c0f6e94411f5 1484 #endif /* __STM32L0xx_HAL_RCC_EX_H */
Kojto 116:c0f6e94411f5 1485
Kojto 116:c0f6e94411f5 1486 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 116:c0f6e94411f5 1487