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TARGET_NUCLEO_L073RZ/stm32l0xx_hal_pwr.h@116:c0f6e94411f5, 2016-03-15 (annotated)
- Committer:
- Kojto
- Date:
- Tue Mar 15 14:34:00 2016 +0000
- Revision:
- 116:c0f6e94411f5
Release 116 of the mbed library
Changes:
- new targets - NUCLEO_L073RZ
- fixes to IOTSS BEID platform
- LPC824, LPC1549 and LPC11U68 - fix PWMOut SCT bugs
- STM32F7 - Cube driver
- STM32F4 - add RTC LSI macro, defined as 0
- STM32F3 - fix multiple ADC clock initialization
- retarget - binary mode fix for GCC
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| Kojto | 116:c0f6e94411f5 | 1 | /** |
| Kojto | 116:c0f6e94411f5 | 2 | ****************************************************************************** |
| Kojto | 116:c0f6e94411f5 | 3 | * @file stm32l0xx_hal_pwr.h |
| Kojto | 116:c0f6e94411f5 | 4 | * @author MCD Application Team |
| Kojto | 116:c0f6e94411f5 | 5 | * @version V1.2.0 |
| Kojto | 116:c0f6e94411f5 | 6 | * @date 06-February-2015 |
| Kojto | 116:c0f6e94411f5 | 7 | * @brief Header file of PWR HAL module. |
| Kojto | 116:c0f6e94411f5 | 8 | ****************************************************************************** |
| Kojto | 116:c0f6e94411f5 | 9 | * @attention |
| Kojto | 116:c0f6e94411f5 | 10 | * |
| Kojto | 116:c0f6e94411f5 | 11 | * <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2> |
| Kojto | 116:c0f6e94411f5 | 12 | * |
| Kojto | 116:c0f6e94411f5 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
| Kojto | 116:c0f6e94411f5 | 14 | * are permitted provided that the following conditions are met: |
| Kojto | 116:c0f6e94411f5 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| Kojto | 116:c0f6e94411f5 | 16 | * this list of conditions and the following disclaimer. |
| Kojto | 116:c0f6e94411f5 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| Kojto | 116:c0f6e94411f5 | 18 | * this list of conditions and the following disclaimer in the documentation |
| Kojto | 116:c0f6e94411f5 | 19 | * and/or other materials provided with the distribution. |
| Kojto | 116:c0f6e94411f5 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| Kojto | 116:c0f6e94411f5 | 21 | * may be used to endorse or promote products derived from this software |
| Kojto | 116:c0f6e94411f5 | 22 | * without specific prior written permission. |
| Kojto | 116:c0f6e94411f5 | 23 | * |
| Kojto | 116:c0f6e94411f5 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| Kojto | 116:c0f6e94411f5 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| Kojto | 116:c0f6e94411f5 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| Kojto | 116:c0f6e94411f5 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| Kojto | 116:c0f6e94411f5 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| Kojto | 116:c0f6e94411f5 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| Kojto | 116:c0f6e94411f5 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| Kojto | 116:c0f6e94411f5 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| Kojto | 116:c0f6e94411f5 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| Kojto | 116:c0f6e94411f5 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| Kojto | 116:c0f6e94411f5 | 34 | * |
| Kojto | 116:c0f6e94411f5 | 35 | ****************************************************************************** |
| Kojto | 116:c0f6e94411f5 | 36 | */ |
| Kojto | 116:c0f6e94411f5 | 37 | |
| Kojto | 116:c0f6e94411f5 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| Kojto | 116:c0f6e94411f5 | 39 | #ifndef __STM32L0xx_HAL_PWR_H |
| Kojto | 116:c0f6e94411f5 | 40 | #define __STM32L0xx_HAL_PWR_H |
| Kojto | 116:c0f6e94411f5 | 41 | |
| Kojto | 116:c0f6e94411f5 | 42 | #ifdef __cplusplus |
| Kojto | 116:c0f6e94411f5 | 43 | extern "C" { |
| Kojto | 116:c0f6e94411f5 | 44 | #endif |
| Kojto | 116:c0f6e94411f5 | 45 | |
| Kojto | 116:c0f6e94411f5 | 46 | /* Includes ------------------------------------------------------------------*/ |
| Kojto | 116:c0f6e94411f5 | 47 | #include "stm32l0xx_hal_def.h" |
| Kojto | 116:c0f6e94411f5 | 48 | |
| Kojto | 116:c0f6e94411f5 | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
| Kojto | 116:c0f6e94411f5 | 50 | * @{ |
| Kojto | 116:c0f6e94411f5 | 51 | */ |
| Kojto | 116:c0f6e94411f5 | 52 | |
| Kojto | 116:c0f6e94411f5 | 53 | /** @defgroup PWR |
| Kojto | 116:c0f6e94411f5 | 54 | * @{ |
| Kojto | 116:c0f6e94411f5 | 55 | */ |
| Kojto | 116:c0f6e94411f5 | 56 | |
| Kojto | 116:c0f6e94411f5 | 57 | /** @defgroup PWR_Exported_Types PWR Exported Types |
| Kojto | 116:c0f6e94411f5 | 58 | * @{ |
| Kojto | 116:c0f6e94411f5 | 59 | */ |
| Kojto | 116:c0f6e94411f5 | 60 | |
| Kojto | 116:c0f6e94411f5 | 61 | /** |
| Kojto | 116:c0f6e94411f5 | 62 | * @brief PWR PVD configuration structure definition |
| Kojto | 116:c0f6e94411f5 | 63 | */ |
| Kojto | 116:c0f6e94411f5 | 64 | typedef struct |
| Kojto | 116:c0f6e94411f5 | 65 | { |
| Kojto | 116:c0f6e94411f5 | 66 | uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level. |
| Kojto | 116:c0f6e94411f5 | 67 | This parameter can be a value of @ref PWR_PVD_detection_level */ |
| Kojto | 116:c0f6e94411f5 | 68 | |
| Kojto | 116:c0f6e94411f5 | 69 | uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins. |
| Kojto | 116:c0f6e94411f5 | 70 | This parameter can be a value of @ref PWR_PVD_Mode */ |
| Kojto | 116:c0f6e94411f5 | 71 | }PWR_PVDTypeDef; |
| Kojto | 116:c0f6e94411f5 | 72 | |
| Kojto | 116:c0f6e94411f5 | 73 | /** |
| Kojto | 116:c0f6e94411f5 | 74 | * @} |
| Kojto | 116:c0f6e94411f5 | 75 | */ |
| Kojto | 116:c0f6e94411f5 | 76 | |
| Kojto | 116:c0f6e94411f5 | 77 | /** @defgroup PWR_Private_Defines PWR Private Defines |
| Kojto | 116:c0f6e94411f5 | 78 | * @{ |
| Kojto | 116:c0f6e94411f5 | 79 | */ |
| Kojto | 116:c0f6e94411f5 | 80 | |
| Kojto | 116:c0f6e94411f5 | 81 | #define PWR_EXTI_LINE_PVD EXTI_FTSR_TR16 /*!< External interrupt line 16 Connected to the PVD EXTI Line */ |
| Kojto | 116:c0f6e94411f5 | 82 | |
| Kojto | 116:c0f6e94411f5 | 83 | /** |
| Kojto | 116:c0f6e94411f5 | 84 | * @} |
| Kojto | 116:c0f6e94411f5 | 85 | */ |
| Kojto | 116:c0f6e94411f5 | 86 | |
| Kojto | 116:c0f6e94411f5 | 87 | /** @defgroup PWR_Exported_Constants PWR Exported Constants |
| Kojto | 116:c0f6e94411f5 | 88 | * @{ |
| Kojto | 116:c0f6e94411f5 | 89 | */ |
| Kojto | 116:c0f6e94411f5 | 90 | |
| Kojto | 116:c0f6e94411f5 | 91 | /** @defgroup PWR_register_alias_address PWR Register alias address |
| Kojto | 116:c0f6e94411f5 | 92 | * @{ |
| Kojto | 116:c0f6e94411f5 | 93 | */ |
| Kojto | 116:c0f6e94411f5 | 94 | #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP1 |
| Kojto | 116:c0f6e94411f5 | 95 | #define PWR_WAKEUP_PIN2 PWR_CSR_EWUP2 |
| Kojto | 116:c0f6e94411f5 | 96 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| Kojto | 116:c0f6e94411f5 | 97 | #define PWR_WAKEUP_PIN3 PWR_CSR_EWUP3 |
| Kojto | 116:c0f6e94411f5 | 98 | #endif |
| Kojto | 116:c0f6e94411f5 | 99 | /** |
| Kojto | 116:c0f6e94411f5 | 100 | * @} |
| Kojto | 116:c0f6e94411f5 | 101 | */ |
| Kojto | 116:c0f6e94411f5 | 102 | |
| Kojto | 116:c0f6e94411f5 | 103 | /** @defgroup PWR_PVD_detection_level PVD detection level |
| Kojto | 116:c0f6e94411f5 | 104 | * @{ |
| Kojto | 116:c0f6e94411f5 | 105 | */ |
| Kojto | 116:c0f6e94411f5 | 106 | #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0 |
| Kojto | 116:c0f6e94411f5 | 107 | #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1 |
| Kojto | 116:c0f6e94411f5 | 108 | #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2 |
| Kojto | 116:c0f6e94411f5 | 109 | #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3 |
| Kojto | 116:c0f6e94411f5 | 110 | #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4 |
| Kojto | 116:c0f6e94411f5 | 111 | #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5 |
| Kojto | 116:c0f6e94411f5 | 112 | #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6 |
| Kojto | 116:c0f6e94411f5 | 113 | #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage |
| Kojto | 116:c0f6e94411f5 | 114 | (Compare internally to VREFINT) */ |
| Kojto | 116:c0f6e94411f5 | 115 | /** |
| Kojto | 116:c0f6e94411f5 | 116 | * @} |
| Kojto | 116:c0f6e94411f5 | 117 | */ |
| Kojto | 116:c0f6e94411f5 | 118 | |
| Kojto | 116:c0f6e94411f5 | 119 | /** @defgroup PWR_PVD_Mode PWR PVD Mode |
| Kojto | 116:c0f6e94411f5 | 120 | * @{ |
| Kojto | 116:c0f6e94411f5 | 121 | */ |
| Kojto | 116:c0f6e94411f5 | 122 | #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */ |
| Kojto | 116:c0f6e94411f5 | 123 | #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */ |
| Kojto | 116:c0f6e94411f5 | 124 | #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */ |
| Kojto | 116:c0f6e94411f5 | 125 | #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */ |
| Kojto | 116:c0f6e94411f5 | 126 | #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */ |
| Kojto | 116:c0f6e94411f5 | 127 | #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */ |
| Kojto | 116:c0f6e94411f5 | 128 | #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */ |
| Kojto | 116:c0f6e94411f5 | 129 | |
| Kojto | 116:c0f6e94411f5 | 130 | /** |
| Kojto | 116:c0f6e94411f5 | 131 | * @} |
| Kojto | 116:c0f6e94411f5 | 132 | */ |
| Kojto | 116:c0f6e94411f5 | 133 | |
| Kojto | 116:c0f6e94411f5 | 134 | /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode |
| Kojto | 116:c0f6e94411f5 | 135 | * @{ |
| Kojto | 116:c0f6e94411f5 | 136 | */ |
| Kojto | 116:c0f6e94411f5 | 137 | #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000) |
| Kojto | 116:c0f6e94411f5 | 138 | #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR |
| Kojto | 116:c0f6e94411f5 | 139 | |
| Kojto | 116:c0f6e94411f5 | 140 | /** |
| Kojto | 116:c0f6e94411f5 | 141 | * @} |
| Kojto | 116:c0f6e94411f5 | 142 | */ |
| Kojto | 116:c0f6e94411f5 | 143 | |
| Kojto | 116:c0f6e94411f5 | 144 | /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry |
| Kojto | 116:c0f6e94411f5 | 145 | * @{ |
| Kojto | 116:c0f6e94411f5 | 146 | */ |
| Kojto | 116:c0f6e94411f5 | 147 | #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01) |
| Kojto | 116:c0f6e94411f5 | 148 | #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02) |
| Kojto | 116:c0f6e94411f5 | 149 | /** |
| Kojto | 116:c0f6e94411f5 | 150 | * @} |
| Kojto | 116:c0f6e94411f5 | 151 | */ |
| Kojto | 116:c0f6e94411f5 | 152 | |
| Kojto | 116:c0f6e94411f5 | 153 | /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry |
| Kojto | 116:c0f6e94411f5 | 154 | * @{ |
| Kojto | 116:c0f6e94411f5 | 155 | */ |
| Kojto | 116:c0f6e94411f5 | 156 | #define PWR_STOPENTRY_WFI ((uint8_t)0x01) |
| Kojto | 116:c0f6e94411f5 | 157 | #define PWR_STOPENTRY_WFE ((uint8_t)0x02) |
| Kojto | 116:c0f6e94411f5 | 158 | /** |
| Kojto | 116:c0f6e94411f5 | 159 | * @} |
| Kojto | 116:c0f6e94411f5 | 160 | */ |
| Kojto | 116:c0f6e94411f5 | 161 | |
| Kojto | 116:c0f6e94411f5 | 162 | /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale |
| Kojto | 116:c0f6e94411f5 | 163 | * @{ |
| Kojto | 116:c0f6e94411f5 | 164 | */ |
| Kojto | 116:c0f6e94411f5 | 165 | |
| Kojto | 116:c0f6e94411f5 | 166 | #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0 |
| Kojto | 116:c0f6e94411f5 | 167 | #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1 |
| Kojto | 116:c0f6e94411f5 | 168 | #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS |
| Kojto | 116:c0f6e94411f5 | 169 | |
| Kojto | 116:c0f6e94411f5 | 170 | #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \ |
| Kojto | 116:c0f6e94411f5 | 171 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \ |
| Kojto | 116:c0f6e94411f5 | 172 | ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3)) |
| Kojto | 116:c0f6e94411f5 | 173 | /** |
| Kojto | 116:c0f6e94411f5 | 174 | * @} |
| Kojto | 116:c0f6e94411f5 | 175 | */ |
| Kojto | 116:c0f6e94411f5 | 176 | |
| Kojto | 116:c0f6e94411f5 | 177 | /** @defgroup PWR_Flag PWR Flag |
| Kojto | 116:c0f6e94411f5 | 178 | * @{ |
| Kojto | 116:c0f6e94411f5 | 179 | */ |
| Kojto | 116:c0f6e94411f5 | 180 | #define PWR_FLAG_WU PWR_CSR_WUF |
| Kojto | 116:c0f6e94411f5 | 181 | #define PWR_FLAG_SB PWR_CSR_SBF |
| Kojto | 116:c0f6e94411f5 | 182 | #define PWR_FLAG_PVDO PWR_CSR_PVDO |
| Kojto | 116:c0f6e94411f5 | 183 | #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF |
| Kojto | 116:c0f6e94411f5 | 184 | #define PWR_FLAG_VOS PWR_CSR_VOSF |
| Kojto | 116:c0f6e94411f5 | 185 | #define PWR_FLAG_REGLP PWR_CSR_REGLPF |
| Kojto | 116:c0f6e94411f5 | 186 | |
| Kojto | 116:c0f6e94411f5 | 187 | #define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \ |
| Kojto | 116:c0f6e94411f5 | 188 | ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_VREFINTRDY) || \ |
| Kojto | 116:c0f6e94411f5 | 189 | ((FLAG) == PWR_FLAG_VOS) || ((FLAG) == PWR_FLAG_REGLP)) |
| Kojto | 116:c0f6e94411f5 | 190 | /** |
| Kojto | 116:c0f6e94411f5 | 191 | * @} |
| Kojto | 116:c0f6e94411f5 | 192 | */ |
| Kojto | 116:c0f6e94411f5 | 193 | |
| Kojto | 116:c0f6e94411f5 | 194 | /** |
| Kojto | 116:c0f6e94411f5 | 195 | * @} |
| Kojto | 116:c0f6e94411f5 | 196 | */ |
| Kojto | 116:c0f6e94411f5 | 197 | |
| Kojto | 116:c0f6e94411f5 | 198 | /** @defgroup PWR_Exported_Macro PWR Exported Macro |
| Kojto | 116:c0f6e94411f5 | 199 | * @{ |
| Kojto | 116:c0f6e94411f5 | 200 | */ |
| Kojto | 116:c0f6e94411f5 | 201 | /** @brief macros configure the main internal regulator output voltage. |
| Kojto | 116:c0f6e94411f5 | 202 | * @param __REGULATOR__: specifies the regulator output voltage to achieve |
| Kojto | 116:c0f6e94411f5 | 203 | * a tradeoff between performance and power consumption when the device does |
| Kojto | 116:c0f6e94411f5 | 204 | * not operate at the maximum frequency (refer to the datasheets for more details). |
| Kojto | 116:c0f6e94411f5 | 205 | * This parameter can be one of the following values: |
| Kojto | 116:c0f6e94411f5 | 206 | * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode, |
| Kojto | 116:c0f6e94411f5 | 207 | * System frequency up to 32 MHz. |
| Kojto | 116:c0f6e94411f5 | 208 | * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode, |
| Kojto | 116:c0f6e94411f5 | 209 | * System frequency up to 16 MHz. |
| Kojto | 116:c0f6e94411f5 | 210 | * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode, |
| Kojto | 116:c0f6e94411f5 | 211 | * System frequency up to 4.2 MHz |
| Kojto | 116:c0f6e94411f5 | 212 | * @retval None |
| Kojto | 116:c0f6e94411f5 | 213 | */ |
| Kojto | 116:c0f6e94411f5 | 214 | #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__))) |
| Kojto | 116:c0f6e94411f5 | 215 | |
| Kojto | 116:c0f6e94411f5 | 216 | /** @brief Check PWR flag is set or not. |
| Kojto | 116:c0f6e94411f5 | 217 | * @param __FLAG__: specifies the flag to check. |
| Kojto | 116:c0f6e94411f5 | 218 | * This parameter can be one of the following values: |
| Kojto | 116:c0f6e94411f5 | 219 | * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event |
| Kojto | 116:c0f6e94411f5 | 220 | * was received from the WKUP pin or from the RTC alarm (Alarm B), |
| Kojto | 116:c0f6e94411f5 | 221 | * RTC Tamper event, RTC TimeStamp event or RTC Wakeup. |
| Kojto | 116:c0f6e94411f5 | 222 | * An additional wakeup event is detected if the WKUP pin is enabled |
| Kojto | 116:c0f6e94411f5 | 223 | * (by setting the EWUP bit) when the WKUP pin level is already high. |
| Kojto | 116:c0f6e94411f5 | 224 | * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was |
| Kojto | 116:c0f6e94411f5 | 225 | * resumed from StandBy mode. |
| Kojto | 116:c0f6e94411f5 | 226 | * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled |
| Kojto | 116:c0f6e94411f5 | 227 | * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode. |
| Kojto | 116:c0f6e94411f5 | 228 | * For this reason, this bit is equal to 0 after Standby or reset |
| Kojto | 116:c0f6e94411f5 | 229 | * until the PVDE bit is set. |
| Kojto | 116:c0f6e94411f5 | 230 | * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag. |
| Kojto | 116:c0f6e94411f5 | 231 | * This bit indicates the state of the internal voltage reference, VREFINT. |
| Kojto | 116:c0f6e94411f5 | 232 | * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for |
| Kojto | 116:c0f6e94411f5 | 233 | * the internal regulator to be ready after the voltage range is changed. |
| Kojto | 116:c0f6e94411f5 | 234 | * The VOSF bit indicates that the regulator has reached the voltage level |
| Kojto | 116:c0f6e94411f5 | 235 | * defined with bits VOS of PWR_CR register. |
| Kojto | 116:c0f6e94411f5 | 236 | * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run |
| Kojto | 116:c0f6e94411f5 | 237 | * mode, this bit stays at 1 until the regulator is ready in main mode. |
| Kojto | 116:c0f6e94411f5 | 238 | * A polling on this bit is recommended to wait for the regulator main mode. |
| Kojto | 116:c0f6e94411f5 | 239 | * This bit is reset by hardware when the regulator is ready. |
| Kojto | 116:c0f6e94411f5 | 240 | * @retval The new state of __FLAG__ (TRUE or FALSE). |
| Kojto | 116:c0f6e94411f5 | 241 | */ |
| Kojto | 116:c0f6e94411f5 | 242 | #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) |
| Kojto | 116:c0f6e94411f5 | 243 | |
| Kojto | 116:c0f6e94411f5 | 244 | /** @brief Clear the PWR's pending flags. |
| Kojto | 116:c0f6e94411f5 | 245 | * @param __FLAG__: specifies the flag to clear. |
| Kojto | 116:c0f6e94411f5 | 246 | * This parameter can be one of the following values: |
| Kojto | 116:c0f6e94411f5 | 247 | * @arg PWR_FLAG_WU: Wake Up flag |
| Kojto | 116:c0f6e94411f5 | 248 | * @arg PWR_FLAG_SB: StandBy flag |
| Kojto | 116:c0f6e94411f5 | 249 | */ |
| Kojto | 116:c0f6e94411f5 | 250 | #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, (__FLAG__) << 2) |
| Kojto | 116:c0f6e94411f5 | 251 | |
| Kojto | 116:c0f6e94411f5 | 252 | /** |
| Kojto | 116:c0f6e94411f5 | 253 | * @brief Enable interrupt on PVD Exti Line 16. |
| Kojto | 116:c0f6e94411f5 | 254 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 255 | */ |
| Kojto | 116:c0f6e94411f5 | 256 | #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 257 | |
| Kojto | 116:c0f6e94411f5 | 258 | /** |
| Kojto | 116:c0f6e94411f5 | 259 | * @brief Disable interrupt on PVD Exti Line 16. |
| Kojto | 116:c0f6e94411f5 | 260 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 261 | */ |
| Kojto | 116:c0f6e94411f5 | 262 | #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 263 | |
| Kojto | 116:c0f6e94411f5 | 264 | /** |
| Kojto | 116:c0f6e94411f5 | 265 | * @brief Enable event on PVD Exti Line 16. |
| Kojto | 116:c0f6e94411f5 | 266 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 267 | */ |
| Kojto | 116:c0f6e94411f5 | 268 | #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 269 | |
| Kojto | 116:c0f6e94411f5 | 270 | /** |
| Kojto | 116:c0f6e94411f5 | 271 | * @brief Disable event on PVD Exti Line 16. |
| Kojto | 116:c0f6e94411f5 | 272 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 273 | */ |
| Kojto | 116:c0f6e94411f5 | 274 | #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 275 | |
| Kojto | 116:c0f6e94411f5 | 276 | |
| Kojto | 116:c0f6e94411f5 | 277 | /** |
| Kojto | 116:c0f6e94411f5 | 278 | * @brief PVD EXTI line configuration: set falling edge trigger. |
| Kojto | 116:c0f6e94411f5 | 279 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 280 | */ |
| Kojto | 116:c0f6e94411f5 | 281 | #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 282 | |
| Kojto | 116:c0f6e94411f5 | 283 | |
| Kojto | 116:c0f6e94411f5 | 284 | /** |
| Kojto | 116:c0f6e94411f5 | 285 | * @brief Disable the PVD Extended Interrupt Falling Trigger. |
| Kojto | 116:c0f6e94411f5 | 286 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 287 | */ |
| Kojto | 116:c0f6e94411f5 | 288 | #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 289 | |
| Kojto | 116:c0f6e94411f5 | 290 | |
| Kojto | 116:c0f6e94411f5 | 291 | /** |
| Kojto | 116:c0f6e94411f5 | 292 | * @brief PVD EXTI line configuration: set rising edge trigger. |
| Kojto | 116:c0f6e94411f5 | 293 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 294 | */ |
| Kojto | 116:c0f6e94411f5 | 295 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 296 | |
| Kojto | 116:c0f6e94411f5 | 297 | /** |
| Kojto | 116:c0f6e94411f5 | 298 | * @brief Disable the PVD Extended Interrupt Rising Trigger. |
| Kojto | 116:c0f6e94411f5 | 299 | * This parameter can be: |
| Kojto | 116:c0f6e94411f5 | 300 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 301 | */ |
| Kojto | 116:c0f6e94411f5 | 302 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 303 | |
| Kojto | 116:c0f6e94411f5 | 304 | /** |
| Kojto | 116:c0f6e94411f5 | 305 | * @brief PVD EXTI line configuration: set rising & falling edge trigger. |
| Kojto | 116:c0f6e94411f5 | 306 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 307 | */ |
| Kojto | 116:c0f6e94411f5 | 308 | #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE(); |
| Kojto | 116:c0f6e94411f5 | 309 | |
| Kojto | 116:c0f6e94411f5 | 310 | /** |
| Kojto | 116:c0f6e94411f5 | 311 | * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger. |
| Kojto | 116:c0f6e94411f5 | 312 | * This parameter can be: |
| Kojto | 116:c0f6e94411f5 | 313 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 314 | */ |
| Kojto | 116:c0f6e94411f5 | 315 | #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()(); |
| Kojto | 116:c0f6e94411f5 | 316 | |
| Kojto | 116:c0f6e94411f5 | 317 | |
| Kojto | 116:c0f6e94411f5 | 318 | |
| Kojto | 116:c0f6e94411f5 | 319 | /** |
| Kojto | 116:c0f6e94411f5 | 320 | * @brief Check whether the specified PVD EXTI interrupt flag is set or not. |
| Kojto | 116:c0f6e94411f5 | 321 | * @retval EXTI PVD Line Status. |
| Kojto | 116:c0f6e94411f5 | 322 | */ |
| Kojto | 116:c0f6e94411f5 | 323 | #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD)) |
| Kojto | 116:c0f6e94411f5 | 324 | |
| Kojto | 116:c0f6e94411f5 | 325 | /** |
| Kojto | 116:c0f6e94411f5 | 326 | * @brief Clear the PVD EXTI flag. |
| Kojto | 116:c0f6e94411f5 | 327 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 328 | */ |
| Kojto | 116:c0f6e94411f5 | 329 | #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD)) |
| Kojto | 116:c0f6e94411f5 | 330 | |
| Kojto | 116:c0f6e94411f5 | 331 | /** |
| Kojto | 116:c0f6e94411f5 | 332 | * @brief Generate a Software interrupt on selected EXTI line. |
| Kojto | 116:c0f6e94411f5 | 333 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 334 | */ |
| Kojto | 116:c0f6e94411f5 | 335 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 336 | /** |
| Kojto | 116:c0f6e94411f5 | 337 | * @} |
| Kojto | 116:c0f6e94411f5 | 338 | */ |
| Kojto | 116:c0f6e94411f5 | 339 | |
| Kojto | 116:c0f6e94411f5 | 340 | /** |
| Kojto | 116:c0f6e94411f5 | 341 | * @brief Generate a Software interrupt on selected EXTI line. |
| Kojto | 116:c0f6e94411f5 | 342 | * @retval None. |
| Kojto | 116:c0f6e94411f5 | 343 | */ |
| Kojto | 116:c0f6e94411f5 | 344 | #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD) |
| Kojto | 116:c0f6e94411f5 | 345 | |
| Kojto | 116:c0f6e94411f5 | 346 | /** |
| Kojto | 116:c0f6e94411f5 | 347 | * @} |
| Kojto | 116:c0f6e94411f5 | 348 | */ |
| Kojto | 116:c0f6e94411f5 | 349 | |
| Kojto | 116:c0f6e94411f5 | 350 | /** @defgroup PWR_Private_Macros PWR Private Macros |
| Kojto | 116:c0f6e94411f5 | 351 | * @{ |
| Kojto | 116:c0f6e94411f5 | 352 | */ |
| Kojto | 116:c0f6e94411f5 | 353 | #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \ |
| Kojto | 116:c0f6e94411f5 | 354 | ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \ |
| Kojto | 116:c0f6e94411f5 | 355 | ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \ |
| Kojto | 116:c0f6e94411f5 | 356 | ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7)) |
| Kojto | 116:c0f6e94411f5 | 357 | |
| Kojto | 116:c0f6e94411f5 | 358 | #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \ |
| Kojto | 116:c0f6e94411f5 | 359 | ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \ |
| Kojto | 116:c0f6e94411f5 | 360 | ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \ |
| Kojto | 116:c0f6e94411f5 | 361 | ((MODE) == PWR_PVD_MODE_NORMAL)) |
| Kojto | 116:c0f6e94411f5 | 362 | |
| Kojto | 116:c0f6e94411f5 | 363 | #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx) |
| Kojto | 116:c0f6e94411f5 | 364 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| Kojto | 116:c0f6e94411f5 | 365 | ((PIN) == PWR_WAKEUP_PIN2) || \ |
| Kojto | 116:c0f6e94411f5 | 366 | ((PIN) == PWR_WAKEUP_PIN3)) |
| Kojto | 116:c0f6e94411f5 | 367 | #else |
| Kojto | 116:c0f6e94411f5 | 368 | #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \ |
| Kojto | 116:c0f6e94411f5 | 369 | ((PIN) == PWR_WAKEUP_PIN2)) |
| Kojto | 116:c0f6e94411f5 | 370 | #endif |
| Kojto | 116:c0f6e94411f5 | 371 | |
| Kojto | 116:c0f6e94411f5 | 372 | #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \ |
| Kojto | 116:c0f6e94411f5 | 373 | ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON)) |
| Kojto | 116:c0f6e94411f5 | 374 | #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE)) |
| Kojto | 116:c0f6e94411f5 | 375 | |
| Kojto | 116:c0f6e94411f5 | 376 | #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE)) |
| Kojto | 116:c0f6e94411f5 | 377 | |
| Kojto | 116:c0f6e94411f5 | 378 | /** |
| Kojto | 116:c0f6e94411f5 | 379 | * @} |
| Kojto | 116:c0f6e94411f5 | 380 | */ |
| Kojto | 116:c0f6e94411f5 | 381 | |
| Kojto | 116:c0f6e94411f5 | 382 | /* Include PWR HAL Extension module */ |
| Kojto | 116:c0f6e94411f5 | 383 | #include "stm32l0xx_hal_pwr_ex.h" |
| Kojto | 116:c0f6e94411f5 | 384 | |
| Kojto | 116:c0f6e94411f5 | 385 | /** @defgroup PWR_Exported_Functions PWR Exported Functions |
| Kojto | 116:c0f6e94411f5 | 386 | * @{ |
| Kojto | 116:c0f6e94411f5 | 387 | */ |
| Kojto | 116:c0f6e94411f5 | 388 | |
| Kojto | 116:c0f6e94411f5 | 389 | /** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions |
| Kojto | 116:c0f6e94411f5 | 390 | * @{ |
| Kojto | 116:c0f6e94411f5 | 391 | */ |
| Kojto | 116:c0f6e94411f5 | 392 | void HAL_PWR_DeInit(void); |
| Kojto | 116:c0f6e94411f5 | 393 | void HAL_PWR_EnableBkUpAccess(void); |
| Kojto | 116:c0f6e94411f5 | 394 | void HAL_PWR_DisableBkUpAccess(void); |
| Kojto | 116:c0f6e94411f5 | 395 | /** |
| Kojto | 116:c0f6e94411f5 | 396 | * @} |
| Kojto | 116:c0f6e94411f5 | 397 | */ |
| Kojto | 116:c0f6e94411f5 | 398 | |
| Kojto | 116:c0f6e94411f5 | 399 | /** @defgroup PWR_Exported_Functions_Group2 Low Power modes configuration functions |
| Kojto | 116:c0f6e94411f5 | 400 | * @{ |
| Kojto | 116:c0f6e94411f5 | 401 | */ |
| Kojto | 116:c0f6e94411f5 | 402 | |
| Kojto | 116:c0f6e94411f5 | 403 | /* PVD control functions ************************************************/ |
| Kojto | 116:c0f6e94411f5 | 404 | void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD); |
| Kojto | 116:c0f6e94411f5 | 405 | void HAL_PWR_EnablePVD(void); |
| Kojto | 116:c0f6e94411f5 | 406 | void HAL_PWR_DisablePVD(void); |
| Kojto | 116:c0f6e94411f5 | 407 | void HAL_PWR_PVD_IRQHandler(void); |
| Kojto | 116:c0f6e94411f5 | 408 | void HAL_PWR_PVDCallback(void); |
| Kojto | 116:c0f6e94411f5 | 409 | |
| Kojto | 116:c0f6e94411f5 | 410 | /* WakeUp pins configuration functions ****************************************/ |
| Kojto | 116:c0f6e94411f5 | 411 | void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx); |
| Kojto | 116:c0f6e94411f5 | 412 | void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx); |
| Kojto | 116:c0f6e94411f5 | 413 | |
| Kojto | 116:c0f6e94411f5 | 414 | /* Low Power modes configuration functions ************************************/ |
| Kojto | 116:c0f6e94411f5 | 415 | void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry); |
| Kojto | 116:c0f6e94411f5 | 416 | void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry); |
| Kojto | 116:c0f6e94411f5 | 417 | void HAL_PWR_EnterSTANDBYMode(void); |
| Kojto | 116:c0f6e94411f5 | 418 | |
| Kojto | 116:c0f6e94411f5 | 419 | void HAL_PWR_EnableSleepOnExit(void); |
| Kojto | 116:c0f6e94411f5 | 420 | void HAL_PWR_DisableSleepOnExit(void); |
| Kojto | 116:c0f6e94411f5 | 421 | void HAL_PWR_EnableSEVOnPend(void); |
| Kojto | 116:c0f6e94411f5 | 422 | void HAL_PWR_DisableSEVOnPend(void); |
| Kojto | 116:c0f6e94411f5 | 423 | |
| Kojto | 116:c0f6e94411f5 | 424 | /** |
| Kojto | 116:c0f6e94411f5 | 425 | * @} |
| Kojto | 116:c0f6e94411f5 | 426 | */ |
| Kojto | 116:c0f6e94411f5 | 427 | |
| Kojto | 116:c0f6e94411f5 | 428 | /** |
| Kojto | 116:c0f6e94411f5 | 429 | * @} |
| Kojto | 116:c0f6e94411f5 | 430 | */ |
| Kojto | 116:c0f6e94411f5 | 431 | |
| Kojto | 116:c0f6e94411f5 | 432 | /** |
| Kojto | 116:c0f6e94411f5 | 433 | * @} |
| Kojto | 116:c0f6e94411f5 | 434 | */ |
| Kojto | 116:c0f6e94411f5 | 435 | |
| Kojto | 116:c0f6e94411f5 | 436 | /** |
| Kojto | 116:c0f6e94411f5 | 437 | * @} |
| Kojto | 116:c0f6e94411f5 | 438 | */ |
| Kojto | 116:c0f6e94411f5 | 439 | |
| Kojto | 116:c0f6e94411f5 | 440 | #ifdef __cplusplus |
| Kojto | 116:c0f6e94411f5 | 441 | } |
| Kojto | 116:c0f6e94411f5 | 442 | #endif |
| Kojto | 116:c0f6e94411f5 | 443 | |
| Kojto | 116:c0f6e94411f5 | 444 | |
| Kojto | 116:c0f6e94411f5 | 445 | #endif /* __STM32L0xx_HAL_PWR_H */ |
| Kojto | 116:c0f6e94411f5 | 446 | |
| Kojto | 116:c0f6e94411f5 | 447 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
| Kojto | 116:c0f6e94411f5 | 448 |