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TARGET_NUCLEO_F446RE/stm32f4xx_hal_rcc_ex.h@106:ba1f97679dad, 2015-09-02 (annotated)

Committer:
Kojto
Date:
Wed Sep 02 14:17:43 2015 +0100
Revision:
106:ba1f97679dad
Child:
110:165afa46840b
Release 106  of the mbed library



Changes:

- new platform - Nucleo F446RE

- STM32F4 Cube driver update v2.3.2

- ST cmsis driver v2.3.2

- nordic bugfix gcc linker start address

- lpc11u68 - bugfix for serial ports

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 106:ba1f97679dad 1 /**
Kojto 106:ba1f97679dad 2 ******************************************************************************
Kojto 106:ba1f97679dad 3 * @file stm32f4xx_hal_rcc_ex.h
Kojto 106:ba1f97679dad 4 * @author MCD Application Team
Kojto 106:ba1f97679dad 5 * @version V1.3.2
Kojto 106:ba1f97679dad 6 * @date 26-June-2015
Kojto 106:ba1f97679dad 7 * @brief Header file of RCC HAL Extension module.
Kojto 106:ba1f97679dad 8 ******************************************************************************
Kojto 106:ba1f97679dad 9 * @attention
Kojto 106:ba1f97679dad 10 *
Kojto 106:ba1f97679dad 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 106:ba1f97679dad 12 *
Kojto 106:ba1f97679dad 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 106:ba1f97679dad 14 * are permitted provided that the following conditions are met:
Kojto 106:ba1f97679dad 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 106:ba1f97679dad 16 * this list of conditions and the following disclaimer.
Kojto 106:ba1f97679dad 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 106:ba1f97679dad 18 * this list of conditions and the following disclaimer in the documentation
Kojto 106:ba1f97679dad 19 * and/or other materials provided with the distribution.
Kojto 106:ba1f97679dad 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 106:ba1f97679dad 21 * may be used to endorse or promote products derived from this software
Kojto 106:ba1f97679dad 22 * without specific prior written permission.
Kojto 106:ba1f97679dad 23 *
Kojto 106:ba1f97679dad 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 106:ba1f97679dad 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 106:ba1f97679dad 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 106:ba1f97679dad 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 106:ba1f97679dad 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 106:ba1f97679dad 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 106:ba1f97679dad 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 106:ba1f97679dad 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 106:ba1f97679dad 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 106:ba1f97679dad 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 106:ba1f97679dad 34 *
Kojto 106:ba1f97679dad 35 ******************************************************************************
Kojto 106:ba1f97679dad 36 */
Kojto 106:ba1f97679dad 37
Kojto 106:ba1f97679dad 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 106:ba1f97679dad 39 #ifndef __STM32F4xx_HAL_RCC_EX_H
Kojto 106:ba1f97679dad 40 #define __STM32F4xx_HAL_RCC_EX_H
Kojto 106:ba1f97679dad 41
Kojto 106:ba1f97679dad 42 #ifdef __cplusplus
Kojto 106:ba1f97679dad 43 extern "C" {
Kojto 106:ba1f97679dad 44 #endif
Kojto 106:ba1f97679dad 45
Kojto 106:ba1f97679dad 46 /* Includes ------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 47 #include "stm32f4xx_hal_def.h"
Kojto 106:ba1f97679dad 48
Kojto 106:ba1f97679dad 49 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 106:ba1f97679dad 50 * @{
Kojto 106:ba1f97679dad 51 */
Kojto 106:ba1f97679dad 52
Kojto 106:ba1f97679dad 53 /** @addtogroup RCCEx
Kojto 106:ba1f97679dad 54 * @{
Kojto 106:ba1f97679dad 55 */
Kojto 106:ba1f97679dad 56
Kojto 106:ba1f97679dad 57 /* Exported types ------------------------------------------------------------*/
Kojto 106:ba1f97679dad 58 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 106:ba1f97679dad 59 * @{
Kojto 106:ba1f97679dad 60 */
Kojto 106:ba1f97679dad 61
Kojto 106:ba1f97679dad 62 /**
Kojto 106:ba1f97679dad 63 * @brief RCC PLL configuration structure definition
Kojto 106:ba1f97679dad 64 */
Kojto 106:ba1f97679dad 65 typedef struct
Kojto 106:ba1f97679dad 66 {
Kojto 106:ba1f97679dad 67 uint32_t PLLState; /*!< The new state of the PLL.
Kojto 106:ba1f97679dad 68 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 106:ba1f97679dad 69
Kojto 106:ba1f97679dad 70 uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
Kojto 106:ba1f97679dad 71 This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto 106:ba1f97679dad 72
Kojto 106:ba1f97679dad 73 uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
Kojto 106:ba1f97679dad 74 This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
Kojto 106:ba1f97679dad 75
Kojto 106:ba1f97679dad 76 uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
Kojto 106:ba1f97679dad 77 This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto 106:ba1f97679dad 78
Kojto 106:ba1f97679dad 79 uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
Kojto 106:ba1f97679dad 80 This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
Kojto 106:ba1f97679dad 81
Kojto 106:ba1f97679dad 82 uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
Kojto 106:ba1f97679dad 83 This parameter must be a number between Min_Data = 4 and Max_Data = 15 */
Kojto 106:ba1f97679dad 84 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 85 uint32_t PLLR; /*!< PLLR: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto 106:ba1f97679dad 86 This parameter is only available in STM32F446xx devices.
Kojto 106:ba1f97679dad 87 This parameter must be a number between Min_Data = 2 and Max_Data = 7 */
Kojto 106:ba1f97679dad 88 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 89 }RCC_PLLInitTypeDef;
Kojto 106:ba1f97679dad 90
Kojto 106:ba1f97679dad 91 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 92 /**
Kojto 106:ba1f97679dad 93 * @brief PLLI2S Clock structure definition
Kojto 106:ba1f97679dad 94 */
Kojto 106:ba1f97679dad 95 typedef struct
Kojto 106:ba1f97679dad 96 {
Kojto 106:ba1f97679dad 97 uint32_t PLLI2SM; /*!< Specifies division factor for PLL VCO input clock.
Kojto 106:ba1f97679dad 98 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto 106:ba1f97679dad 99
Kojto 106:ba1f97679dad 100 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 106:ba1f97679dad 101 This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto 106:ba1f97679dad 102
Kojto 106:ba1f97679dad 103 uint32_t PLLI2SP; /*!< Specifies division factor for SPDIFRX Clock.
Kojto 106:ba1f97679dad 104 This parameter must be a value of @ref RCCEx_PLLI2SP_Clock_Divider */
Kojto 106:ba1f97679dad 105
Kojto 106:ba1f97679dad 106 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI clock.
Kojto 106:ba1f97679dad 107 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 108 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 106:ba1f97679dad 109
Kojto 106:ba1f97679dad 110 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto 106:ba1f97679dad 111 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 112 This parameter will be used only when PLLI2S is selected as Clock Source I2S */
Kojto 106:ba1f97679dad 113 }RCC_PLLI2SInitTypeDef;
Kojto 106:ba1f97679dad 114
Kojto 106:ba1f97679dad 115 /**
Kojto 106:ba1f97679dad 116 * @brief PLLSAI Clock structure definition
Kojto 106:ba1f97679dad 117 */
Kojto 106:ba1f97679dad 118 typedef struct
Kojto 106:ba1f97679dad 119 {
Kojto 106:ba1f97679dad 120 uint32_t PLLSAIM; /*!< Spcifies division factor for PLL VCO input clock.
Kojto 106:ba1f97679dad 121 This parameter must be a number between Min_Data = 2 and Max_Data = 63 */
Kojto 106:ba1f97679dad 122
Kojto 106:ba1f97679dad 123 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 106:ba1f97679dad 124 This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
Kojto 106:ba1f97679dad 125
Kojto 106:ba1f97679dad 126 uint32_t PLLSAIP; /*!< Specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto 106:ba1f97679dad 127 This parameter must be a value of @ref RCCEx_PLLSAIP_Clock_Divider */
Kojto 106:ba1f97679dad 128
Kojto 106:ba1f97679dad 129 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI clock.
Kojto 106:ba1f97679dad 130 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 131 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto 106:ba1f97679dad 132 }RCC_PLLSAIInitTypeDef;
Kojto 106:ba1f97679dad 133 /**
Kojto 106:ba1f97679dad 134 * @brief RCC extended clocks structure definition
Kojto 106:ba1f97679dad 135 */
Kojto 106:ba1f97679dad 136 typedef struct
Kojto 106:ba1f97679dad 137 {
Kojto 106:ba1f97679dad 138 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 106:ba1f97679dad 139 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 106:ba1f97679dad 140
Kojto 106:ba1f97679dad 141 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto 106:ba1f97679dad 142 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 106:ba1f97679dad 143
Kojto 106:ba1f97679dad 144 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto 106:ba1f97679dad 145 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto 106:ba1f97679dad 146
Kojto 106:ba1f97679dad 147 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 106:ba1f97679dad 148 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 106:ba1f97679dad 149 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 106:ba1f97679dad 150
Kojto 106:ba1f97679dad 151 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 106:ba1f97679dad 152 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 106:ba1f97679dad 153 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto 106:ba1f97679dad 154
Kojto 106:ba1f97679dad 155 uint32_t Sai1ClockSelection; /*!< Specifies SAI1 Clock Source Selection.
Kojto 106:ba1f97679dad 156 This parameter can be a value of @ref RCCEx_SAI1_Clock_Source */
Kojto 106:ba1f97679dad 157
Kojto 106:ba1f97679dad 158 uint32_t Sai2ClockSelection; /*!< Specifies SAI2 Clock Source Selection.
Kojto 106:ba1f97679dad 159 This parameter can be a value of @ref RCCEx_SAI2_Clock_Source */
Kojto 106:ba1f97679dad 160
Kojto 106:ba1f97679dad 161 uint32_t I2sApb1ClockSelection; /*!< Specifies I2S APB1 Clock Source Selection.
Kojto 106:ba1f97679dad 162 This parameter can be a value of @ref RCCEx_I2SAPB1_Clock_Source */
Kojto 106:ba1f97679dad 163
Kojto 106:ba1f97679dad 164 uint32_t I2sApb2ClockSelection; /*!< Specifies I2S APB2 Clock Source Selection.
Kojto 106:ba1f97679dad 165 This parameter can be a value of @ref RCCEx_I2SAPB2_Clock_Source */
Kojto 106:ba1f97679dad 166
Kojto 106:ba1f97679dad 167 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Source Selection.
Kojto 106:ba1f97679dad 168 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 106:ba1f97679dad 169
Kojto 106:ba1f97679dad 170 uint32_t SdioClockSelection; /*!< Specifies SDIO Clock Source Selection.
Kojto 106:ba1f97679dad 171 This parameter can be a value of @ref RCCEx_SDIO_Clock_Source */
Kojto 106:ba1f97679dad 172
Kojto 106:ba1f97679dad 173 uint32_t CecClockSelection; /*!< Specifies CEC Clock Source Selection.
Kojto 106:ba1f97679dad 174 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 106:ba1f97679dad 175
Kojto 106:ba1f97679dad 176 uint32_t Fmpi2c1ClockSelection; /*!< Specifies FMPI2C1 Clock Source Selection.
Kojto 106:ba1f97679dad 177 This parameter can be a value of @ref RCCEx_FMPI2C1_Clock_Source */
Kojto 106:ba1f97679dad 178
Kojto 106:ba1f97679dad 179 uint32_t SpdifClockSelection; /*!< Specifies SPDIFRX Clock Source Selection.
Kojto 106:ba1f97679dad 180 This parameter can be a value of @ref RCCEx_SPDIFRX_Clock_Source */
Kojto 106:ba1f97679dad 181
Kojto 106:ba1f97679dad 182 uint32_t Clk48ClockSelection; /*!< Specifies CK48 Clock Selection this clock used OTG FS, SDIO and RNG clocks.
Kojto 106:ba1f97679dad 183 This parameter can be a value of @ref RCCEx_CK48_Clock_Source */
Kojto 106:ba1f97679dad 184
Kojto 106:ba1f97679dad 185 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Source Selection.
Kojto 106:ba1f97679dad 186 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto 106:ba1f97679dad 187 }RCC_PeriphCLKInitTypeDef;
Kojto 106:ba1f97679dad 188 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 189
Kojto 106:ba1f97679dad 190 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 106:ba1f97679dad 191
Kojto 106:ba1f97679dad 192 /**
Kojto 106:ba1f97679dad 193 * @brief PLLI2S Clock structure definition
Kojto 106:ba1f97679dad 194 */
Kojto 106:ba1f97679dad 195 typedef struct
Kojto 106:ba1f97679dad 196 {
Kojto 106:ba1f97679dad 197 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 106:ba1f97679dad 198 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 199 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 106:ba1f97679dad 200
Kojto 106:ba1f97679dad 201 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto 106:ba1f97679dad 202 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 203 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 106:ba1f97679dad 204
Kojto 106:ba1f97679dad 205 uint32_t PLLI2SQ; /*!< Specifies the division factor for SAI1 clock.
Kojto 106:ba1f97679dad 206 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 207 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 106:ba1f97679dad 208 }RCC_PLLI2SInitTypeDef;
Kojto 106:ba1f97679dad 209
Kojto 106:ba1f97679dad 210 /**
Kojto 106:ba1f97679dad 211 * @brief PLLSAI Clock structure definition
Kojto 106:ba1f97679dad 212 */
Kojto 106:ba1f97679dad 213 typedef struct
Kojto 106:ba1f97679dad 214 {
Kojto 106:ba1f97679dad 215 uint32_t PLLSAIN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 106:ba1f97679dad 216 This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 217 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto 106:ba1f97679dad 218
Kojto 106:ba1f97679dad 219 uint32_t PLLSAIQ; /*!< Specifies the division factor for SAI1 clock.
Kojto 106:ba1f97679dad 220 This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 221 This parameter will be used only when PLLSAI is selected as Clock Source SAI or LTDC */
Kojto 106:ba1f97679dad 222
Kojto 106:ba1f97679dad 223 uint32_t PLLSAIR; /*!< specifies the division factor for LTDC clock
Kojto 106:ba1f97679dad 224 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 225 This parameter will be used only when PLLSAI is selected as Clock Source LTDC */
Kojto 106:ba1f97679dad 226
Kojto 106:ba1f97679dad 227 }RCC_PLLSAIInitTypeDef;
Kojto 106:ba1f97679dad 228 /**
Kojto 106:ba1f97679dad 229 * @brief RCC extended clocks structure definition
Kojto 106:ba1f97679dad 230 */
Kojto 106:ba1f97679dad 231 typedef struct
Kojto 106:ba1f97679dad 232 {
Kojto 106:ba1f97679dad 233 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 106:ba1f97679dad 234 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 106:ba1f97679dad 235
Kojto 106:ba1f97679dad 236 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto 106:ba1f97679dad 237 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 106:ba1f97679dad 238
Kojto 106:ba1f97679dad 239 RCC_PLLSAIInitTypeDef PLLSAI; /*!< PLL SAI structure parameters.
Kojto 106:ba1f97679dad 240 This parameter will be used only when PLLI2S is selected as Clock Source SAI or LTDC */
Kojto 106:ba1f97679dad 241
Kojto 106:ba1f97679dad 242 uint32_t PLLI2SDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 106:ba1f97679dad 243 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 106:ba1f97679dad 244 This parameter will be used only when PLLI2S is selected as Clock Source SAI */
Kojto 106:ba1f97679dad 245
Kojto 106:ba1f97679dad 246 uint32_t PLLSAIDivQ; /*!< Specifies the PLLI2S division factor for SAI1 clock.
Kojto 106:ba1f97679dad 247 This parameter must be a number between Min_Data = 1 and Max_Data = 32
Kojto 106:ba1f97679dad 248 This parameter will be used only when PLLSAI is selected as Clock Source SAI */
Kojto 106:ba1f97679dad 249
Kojto 106:ba1f97679dad 250 uint32_t PLLSAIDivR; /*!< Specifies the PLLSAI division factor for LTDC clock.
Kojto 106:ba1f97679dad 251 This parameter must be one value of @ref RCCEx_PLLSAI_DIVR */
Kojto 106:ba1f97679dad 252
Kojto 106:ba1f97679dad 253 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto 106:ba1f97679dad 254 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 106:ba1f97679dad 255
Kojto 106:ba1f97679dad 256 uint8_t TIMPresSelection; /*!< Specifies TIM Clock Prescalers Selection.
Kojto 106:ba1f97679dad 257 This parameter can be a value of @ref RCCEx_TIM_PRescaler_Selection */
Kojto 106:ba1f97679dad 258
Kojto 106:ba1f97679dad 259 }RCC_PeriphCLKInitTypeDef;
Kojto 106:ba1f97679dad 260 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 261
Kojto 106:ba1f97679dad 262 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
Kojto 106:ba1f97679dad 263 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
Kojto 106:ba1f97679dad 264 /**
Kojto 106:ba1f97679dad 265 * @brief PLLI2S Clock structure definition
Kojto 106:ba1f97679dad 266 */
Kojto 106:ba1f97679dad 267 typedef struct
Kojto 106:ba1f97679dad 268 {
Kojto 106:ba1f97679dad 269 #if defined(STM32F411xE)
Kojto 106:ba1f97679dad 270 uint32_t PLLI2SM; /*!< PLLM: Division factor for PLLI2S VCO input clock.
Kojto 106:ba1f97679dad 271 This parameter must be a number between Min_Data = 2 and Max_Data = 62 */
Kojto 106:ba1f97679dad 272 #endif /* STM32F411xE */
Kojto 106:ba1f97679dad 273
Kojto 106:ba1f97679dad 274 uint32_t PLLI2SN; /*!< Specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 106:ba1f97679dad 275 This parameter must be a number between Min_Data = 192 and Max_Data = 432
Kojto 106:ba1f97679dad 276 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 106:ba1f97679dad 277
Kojto 106:ba1f97679dad 278 uint32_t PLLI2SR; /*!< Specifies the division factor for I2S clock.
Kojto 106:ba1f97679dad 279 This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 280 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 106:ba1f97679dad 281
Kojto 106:ba1f97679dad 282 }RCC_PLLI2SInitTypeDef;
Kojto 106:ba1f97679dad 283
Kojto 106:ba1f97679dad 284
Kojto 106:ba1f97679dad 285 /**
Kojto 106:ba1f97679dad 286 * @brief RCC extended clocks structure definition
Kojto 106:ba1f97679dad 287 */
Kojto 106:ba1f97679dad 288 typedef struct
Kojto 106:ba1f97679dad 289 {
Kojto 106:ba1f97679dad 290 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 106:ba1f97679dad 291 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 106:ba1f97679dad 292
Kojto 106:ba1f97679dad 293 RCC_PLLI2SInitTypeDef PLLI2S; /*!< PLL I2S structure parameters.
Kojto 106:ba1f97679dad 294 This parameter will be used only when PLLI2S is selected as Clock Source I2S or SAI */
Kojto 106:ba1f97679dad 295
Kojto 106:ba1f97679dad 296 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection.
Kojto 106:ba1f97679dad 297 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 106:ba1f97679dad 298
Kojto 106:ba1f97679dad 299 }RCC_PeriphCLKInitTypeDef;
Kojto 106:ba1f97679dad 300 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
Kojto 106:ba1f97679dad 301 /**
Kojto 106:ba1f97679dad 302 * @}
Kojto 106:ba1f97679dad 303 */
Kojto 106:ba1f97679dad 304
Kojto 106:ba1f97679dad 305 /* Exported constants --------------------------------------------------------*/
Kojto 106:ba1f97679dad 306 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 106:ba1f97679dad 307 * @{
Kojto 106:ba1f97679dad 308 */
Kojto 106:ba1f97679dad 309
Kojto 106:ba1f97679dad 310 /** @defgroup RCCEx_Periph_Clock_Selection RCC Periph Clock Selection
Kojto 106:ba1f97679dad 311 * @{
Kojto 106:ba1f97679dad 312 */
Kojto 106:ba1f97679dad 313 /*------------------------------- Peripheral Clock source for STM32F446xx -----------------------------*/
Kojto 106:ba1f97679dad 314 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 315 #define RCC_PERIPHCLK_I2S_APB1 ((uint32_t)0x00000001)
Kojto 106:ba1f97679dad 316 #define RCC_PERIPHCLK_I2S_APB2 ((uint32_t)0x00000002)
Kojto 106:ba1f97679dad 317 #define RCC_PERIPHCLK_SAI1 ((uint32_t)0x00000004)
Kojto 106:ba1f97679dad 318 #define RCC_PERIPHCLK_SAI2 ((uint32_t)0x00000008)
Kojto 106:ba1f97679dad 319 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto 106:ba1f97679dad 320 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto 106:ba1f97679dad 321 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000040)
Kojto 106:ba1f97679dad 322 #define RCC_PERIPHCLK_FMPI2C1 ((uint32_t)0x00000080)
Kojto 106:ba1f97679dad 323 #define RCC_PERIPHCLK_CK48 ((uint32_t)0x00000100)
Kojto 106:ba1f97679dad 324 #define RCC_PERIPHCLK_SDIO ((uint32_t)0x00000200)
Kojto 106:ba1f97679dad 325 #define RCC_PERIPHCLK_SPDIFRX ((uint32_t)0x00000400)
Kojto 106:ba1f97679dad 326 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000800)
Kojto 106:ba1f97679dad 327 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 328 /*-----------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 329
Kojto 106:ba1f97679dad 330 /*--------------- Peripheral Clock source for STM32F42xxx/STM32F43xxx ---------------------*/
Kojto 106:ba1f97679dad 331 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 106:ba1f97679dad 332 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto 106:ba1f97679dad 333 #define RCC_PERIPHCLK_SAI_PLLI2S ((uint32_t)0x00000002)
Kojto 106:ba1f97679dad 334 #define RCC_PERIPHCLK_SAI_PLLSAI ((uint32_t)0x00000004)
Kojto 106:ba1f97679dad 335 #define RCC_PERIPHCLK_LTDC ((uint32_t)0x00000008)
Kojto 106:ba1f97679dad 336 #define RCC_PERIPHCLK_TIM ((uint32_t)0x00000010)
Kojto 106:ba1f97679dad 337 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
Kojto 106:ba1f97679dad 338 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000040)
Kojto 106:ba1f97679dad 339 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 340 /*-----------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 341
Kojto 106:ba1f97679dad 342 /*------------------------ Peripheral Clock source for STM32F40xxx/STM32F41xxx ------------------------*/
Kojto 106:ba1f97679dad 343 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
Kojto 106:ba1f97679dad 344 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
Kojto 106:ba1f97679dad 345 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000001)
Kojto 106:ba1f97679dad 346 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00000002)
Kojto 106:ba1f97679dad 347 #define RCC_PERIPHCLK_PLLI2S ((uint32_t)0x00000004)
Kojto 106:ba1f97679dad 348 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
Kojto 106:ba1f97679dad 349 /*-----------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 350 /**
Kojto 106:ba1f97679dad 351 * @}
Kojto 106:ba1f97679dad 352 */
Kojto 106:ba1f97679dad 353
Kojto 106:ba1f97679dad 354 /** @defgroup RCCEx_PLLSAI_DIVR RCC PLLSAI DIVR
Kojto 106:ba1f97679dad 355 * @{
Kojto 106:ba1f97679dad 356 */
Kojto 106:ba1f97679dad 357 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 358 #define RCC_PLLSAIDIVR_2 ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 359 #define RCC_PLLSAIDIVR_4 ((uint32_t)0x00010000)
Kojto 106:ba1f97679dad 360 #define RCC_PLLSAIDIVR_8 ((uint32_t)0x00020000)
Kojto 106:ba1f97679dad 361 #define RCC_PLLSAIDIVR_16 ((uint32_t)0x00030000)
Kojto 106:ba1f97679dad 362 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
Kojto 106:ba1f97679dad 363 /**
Kojto 106:ba1f97679dad 364 * @}
Kojto 106:ba1f97679dad 365 */
Kojto 106:ba1f97679dad 366
Kojto 106:ba1f97679dad 367 /** @defgroup RCCEx_PLLI2SP_Clock_Divider RCC PLLI2SP Clock Divider
Kojto 106:ba1f97679dad 368 * @{
Kojto 106:ba1f97679dad 369 */
Kojto 106:ba1f97679dad 370 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 371 #define RCC_PLLI2SP_DIV2 ((uint32_t)0x00000002)
Kojto 106:ba1f97679dad 372 #define RCC_PLLI2SP_DIV4 ((uint32_t)0x00000004)
Kojto 106:ba1f97679dad 373 #define RCC_PLLI2SP_DIV6 ((uint32_t)0x00000006)
Kojto 106:ba1f97679dad 374 #define RCC_PLLI2SP_DIV8 ((uint32_t)0x00000008)
Kojto 106:ba1f97679dad 375 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 376 /**
Kojto 106:ba1f97679dad 377 * @}
Kojto 106:ba1f97679dad 378 */
Kojto 106:ba1f97679dad 379
Kojto 106:ba1f97679dad 380 /** @defgroup RCCEx_PLLSAIP_Clock_Divider RCC PLLSAIP Clock Divider
Kojto 106:ba1f97679dad 381 * @{
Kojto 106:ba1f97679dad 382 */
Kojto 106:ba1f97679dad 383 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 384 #define RCC_PLLSAIP_DIV2 ((uint32_t)0x00000002)
Kojto 106:ba1f97679dad 385 #define RCC_PLLSAIP_DIV4 ((uint32_t)0x00000004)
Kojto 106:ba1f97679dad 386 #define RCC_PLLSAIP_DIV6 ((uint32_t)0x00000006)
Kojto 106:ba1f97679dad 387 #define RCC_PLLSAIP_DIV8 ((uint32_t)0x00000008)
Kojto 106:ba1f97679dad 388 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 389 /**
Kojto 106:ba1f97679dad 390 * @}
Kojto 106:ba1f97679dad 391 */
Kojto 106:ba1f97679dad 392
Kojto 106:ba1f97679dad 393 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 106:ba1f97679dad 394 /** @defgroup RCCEx_SAI_BlockA_Clock_Source RCC SAI BlockA Clock Source
Kojto 106:ba1f97679dad 395 * @{
Kojto 106:ba1f97679dad 396 */
Kojto 106:ba1f97679dad 397 #define RCC_SAIACLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 398 #define RCC_SAIACLKSOURCE_PLLI2S ((uint32_t)0x00100000)
Kojto 106:ba1f97679dad 399 #define RCC_SAIACLKSOURCE_EXT ((uint32_t)0x00200000)
Kojto 106:ba1f97679dad 400 /**
Kojto 106:ba1f97679dad 401 * @}
Kojto 106:ba1f97679dad 402 */
Kojto 106:ba1f97679dad 403
Kojto 106:ba1f97679dad 404 /** @defgroup RCCEx_SAI_BlockB_Clock_Source RCC SAI BlockB Clock Source
Kojto 106:ba1f97679dad 405 * @{
Kojto 106:ba1f97679dad 406 */
Kojto 106:ba1f97679dad 407 #define RCC_SAIBCLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 408 #define RCC_SAIBCLKSOURCE_PLLI2S ((uint32_t)0x00400000)
Kojto 106:ba1f97679dad 409 #define RCC_SAIBCLKSOURCE_EXT ((uint32_t)0x00800000)
Kojto 106:ba1f97679dad 410 /**
Kojto 106:ba1f97679dad 411 * @}
Kojto 106:ba1f97679dad 412 */
Kojto 106:ba1f97679dad 413 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 414
Kojto 106:ba1f97679dad 415 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 416 /** @defgroup RCCEx_SAI1_Clock_Source RCC SAI1 Clock Source
Kojto 106:ba1f97679dad 417 * @{
Kojto 106:ba1f97679dad 418 */
Kojto 106:ba1f97679dad 419 #define RCC_SAI1CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 420 #define RCC_SAI1CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI1SRC_0)
Kojto 106:ba1f97679dad 421 #define RCC_SAI1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI1SRC_1)
Kojto 106:ba1f97679dad 422 #define RCC_SAI1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_SAI1SRC)
Kojto 106:ba1f97679dad 423 /**
Kojto 106:ba1f97679dad 424 * @}
Kojto 106:ba1f97679dad 425 */
Kojto 106:ba1f97679dad 426
Kojto 106:ba1f97679dad 427 /** @defgroup RCCEx_SAI2_Clock_Source RCC SAI2 Clock Source
Kojto 106:ba1f97679dad 428 * @{
Kojto 106:ba1f97679dad 429 */
Kojto 106:ba1f97679dad 430 #define RCC_SAI2CLKSOURCE_PLLSAI ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 431 #define RCC_SAI2CLKSOURCE_PLLI2S ((uint32_t)RCC_DCKCFGR_SAI2SRC_0)
Kojto 106:ba1f97679dad 432 #define RCC_SAI2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_SAI2SRC_1)
Kojto 106:ba1f97679dad 433 #define RCC_SAI2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_SAI2SRC)
Kojto 106:ba1f97679dad 434 /**
Kojto 106:ba1f97679dad 435 * @}
Kojto 106:ba1f97679dad 436 */
Kojto 106:ba1f97679dad 437
Kojto 106:ba1f97679dad 438 /** @defgroup RCCEx_I2SAPB1_Clock_Source RCC I2S APB1 Clock Source
Kojto 106:ba1f97679dad 439 * @{
Kojto 106:ba1f97679dad 440 */
Kojto 106:ba1f97679dad 441 #define RCC_I2SAPB1CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 442 #define RCC_I2SAPB1CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S1SRC_0)
Kojto 106:ba1f97679dad 443 #define RCC_I2SAPB1CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S1SRC_1)
Kojto 106:ba1f97679dad 444 #define RCC_I2SAPB1CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S1SRC)
Kojto 106:ba1f97679dad 445 /**
Kojto 106:ba1f97679dad 446 * @}
Kojto 106:ba1f97679dad 447 */
Kojto 106:ba1f97679dad 448
Kojto 106:ba1f97679dad 449 /** @defgroup RCCEx_I2SAPB2_Clock_Source RCC I2S APB2 Clock Source
Kojto 106:ba1f97679dad 450 * @{
Kojto 106:ba1f97679dad 451 */
Kojto 106:ba1f97679dad 452 #define RCC_I2SAPB2CLKSOURCE_PLLI2S ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 453 #define RCC_I2SAPB2CLKSOURCE_EXT ((uint32_t)RCC_DCKCFGR_I2S2SRC_0)
Kojto 106:ba1f97679dad 454 #define RCC_I2SAPB2CLKSOURCE_PLLR ((uint32_t)RCC_DCKCFGR_I2S2SRC_1)
Kojto 106:ba1f97679dad 455 #define RCC_I2SAPB2CLKSOURCE_PLLSRC ((uint32_t)RCC_DCKCFGR_I2S2SRC)
Kojto 106:ba1f97679dad 456 /**
Kojto 106:ba1f97679dad 457 * @}
Kojto 106:ba1f97679dad 458 */
Kojto 106:ba1f97679dad 459
Kojto 106:ba1f97679dad 460 /** @defgroup RCCEx_FMPI2C1_Clock_Source RCC FMPI2C1 Clock Source
Kojto 106:ba1f97679dad 461 * @{
Kojto 106:ba1f97679dad 462 */
Kojto 106:ba1f97679dad 463 #define RCC_FMPI2C1CLKSOURCE_APB ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 464 #define RCC_FMPI2C1CLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_0)
Kojto 106:ba1f97679dad 465 #define RCC_FMPI2C1CLKSOURCE_HSI ((uint32_t)RCC_DCKCFGR2_FMPI2C1SEL_1)
Kojto 106:ba1f97679dad 466 /**
Kojto 106:ba1f97679dad 467 * @}
Kojto 106:ba1f97679dad 468 */
Kojto 106:ba1f97679dad 469
Kojto 106:ba1f97679dad 470 /** @defgroup RCCEx_CEC_Clock_Source RCC CEC Clock Source
Kojto 106:ba1f97679dad 471 * @{
Kojto 106:ba1f97679dad 472 */
Kojto 106:ba1f97679dad 473 #define RCC_CECCLKSOURCE_HSI ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 474 #define RCC_CECCLKSOURCE_LSE ((uint32_t)RCC_DCKCFGR2_CECSEL)
Kojto 106:ba1f97679dad 475 /**
Kojto 106:ba1f97679dad 476 * @}
Kojto 106:ba1f97679dad 477 */
Kojto 106:ba1f97679dad 478
Kojto 106:ba1f97679dad 479 /** @defgroup RCCEx_CK48_Clock_Source RCC CK48 Clock Source
Kojto 106:ba1f97679dad 480 * @{
Kojto 106:ba1f97679dad 481 */
Kojto 106:ba1f97679dad 482 #define RCC_CK48CLKSOURCE_PLLQ ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 483 #define RCC_CK48CLKSOURCE_PLLSAIP ((uint32_t)RCC_DCKCFGR2_CK48MSEL)
Kojto 106:ba1f97679dad 484 /**
Kojto 106:ba1f97679dad 485 * @}
Kojto 106:ba1f97679dad 486 */
Kojto 106:ba1f97679dad 487
Kojto 106:ba1f97679dad 488 /** @defgroup RCCEx_SDIO_Clock_Source RCC SDIO Clock Source
Kojto 106:ba1f97679dad 489 * @{
Kojto 106:ba1f97679dad 490 */
Kojto 106:ba1f97679dad 491 #define RCC_SDIOCLKSOURCE_CK48 ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 492 #define RCC_SDIOCLKSOURCE_SYSCLK ((uint32_t)RCC_DCKCFGR2_SDIOSEL)
Kojto 106:ba1f97679dad 493 /**
Kojto 106:ba1f97679dad 494 * @}
Kojto 106:ba1f97679dad 495 */
Kojto 106:ba1f97679dad 496
Kojto 106:ba1f97679dad 497 /** @defgroup RCCEx_SPDIFRX_Clock_Source RCC SPDIFRX Clock Source
Kojto 106:ba1f97679dad 498 * @{
Kojto 106:ba1f97679dad 499 */
Kojto 106:ba1f97679dad 500 #define RCC_SPDIFRXCLKSOURCE_PLLR ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 501 #define RCC_SPDIFRXCLKSOURCE_PLLI2SP ((uint32_t)RCC_DCKCFGR2_SPDIFRXSEL)
Kojto 106:ba1f97679dad 502 /**
Kojto 106:ba1f97679dad 503 * @}
Kojto 106:ba1f97679dad 504 */
Kojto 106:ba1f97679dad 505
Kojto 106:ba1f97679dad 506 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 507
Kojto 106:ba1f97679dad 508 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
Kojto 106:ba1f97679dad 509 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 510 /** @defgroup RCCEx_TIM_PRescaler_Selection RCC TIM PRescaler Selection
Kojto 106:ba1f97679dad 511 * @{
Kojto 106:ba1f97679dad 512 */
Kojto 106:ba1f97679dad 513 #define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
Kojto 106:ba1f97679dad 514 #define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
Kojto 106:ba1f97679dad 515 /**
Kojto 106:ba1f97679dad 516 * @}
Kojto 106:ba1f97679dad 517 */
Kojto 106:ba1f97679dad 518 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
Kojto 106:ba1f97679dad 519
Kojto 106:ba1f97679dad 520 #if defined(STM32F411xE) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 521 /** @defgroup RCCEx_LSE_Dual_Mode_Selection RCC LSE Dual Mode Selection
Kojto 106:ba1f97679dad 522 * @{
Kojto 106:ba1f97679dad 523 */
Kojto 106:ba1f97679dad 524 #define RCC_LSE_LOWPOWER_MODE ((uint8_t)0x00)
Kojto 106:ba1f97679dad 525 #define RCC_LSE_HIGHDRIVE_MODE ((uint8_t)0x01)
Kojto 106:ba1f97679dad 526 /**
Kojto 106:ba1f97679dad 527 * @}
Kojto 106:ba1f97679dad 528 */
Kojto 106:ba1f97679dad 529 #endif /* STM32F411xE || STM32F446xx */
Kojto 106:ba1f97679dad 530
Kojto 106:ba1f97679dad 531 /**
Kojto 106:ba1f97679dad 532 * @}
Kojto 106:ba1f97679dad 533 */
Kojto 106:ba1f97679dad 534
Kojto 106:ba1f97679dad 535 /* Exported macro ------------------------------------------------------------*/
Kojto 106:ba1f97679dad 536 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 106:ba1f97679dad 537 * @{
Kojto 106:ba1f97679dad 538 */
Kojto 106:ba1f97679dad 539 /*------------------------------- STM32F42xxx/STM32F43xxx ----------------------------------*/
Kojto 106:ba1f97679dad 540 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 106:ba1f97679dad 541 /** @brief Enables or disables the AHB1 peripheral clock.
Kojto 106:ba1f97679dad 542 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 543 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 544 * using it.
Kojto 106:ba1f97679dad 545 */
Kojto 106:ba1f97679dad 546 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 547 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 548 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto 106:ba1f97679dad 549 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 550 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto 106:ba1f97679dad 551 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 552 } while(0)
Kojto 106:ba1f97679dad 553 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 554 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 555 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 106:ba1f97679dad 556 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 557 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 106:ba1f97679dad 558 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 559 } while(0)
Kojto 106:ba1f97679dad 560 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 561 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 562 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 106:ba1f97679dad 563 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 564 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 106:ba1f97679dad 565 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 566 } while(0)
Kojto 106:ba1f97679dad 567 #define __HAL_RCC_GPIOJ_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 568 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 569 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto 106:ba1f97679dad 570 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 571 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOJEN);\
Kojto 106:ba1f97679dad 572 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 573 } while(0)
Kojto 106:ba1f97679dad 574 #define __HAL_RCC_GPIOK_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 575 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 576 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto 106:ba1f97679dad 577 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 578 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOKEN);\
Kojto 106:ba1f97679dad 579 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 580 } while(0)
Kojto 106:ba1f97679dad 581 #define __HAL_RCC_DMA2D_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 582 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 583 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto 106:ba1f97679dad 584 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 585 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_DMA2DEN);\
Kojto 106:ba1f97679dad 586 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 587 } while(0)
Kojto 106:ba1f97679dad 588 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 589 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 590 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto 106:ba1f97679dad 591 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 592 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto 106:ba1f97679dad 593 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 594 } while(0)
Kojto 106:ba1f97679dad 595 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 596 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 597 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto 106:ba1f97679dad 598 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 599 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto 106:ba1f97679dad 600 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 601 } while(0)
Kojto 106:ba1f97679dad 602 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 603 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 604 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto 106:ba1f97679dad 605 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 606 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto 106:ba1f97679dad 607 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 608 } while(0)
Kojto 106:ba1f97679dad 609 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 610 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 611 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto 106:ba1f97679dad 612 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 613 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto 106:ba1f97679dad 614 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 615 } while(0)
Kojto 106:ba1f97679dad 616 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 617 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 618 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 106:ba1f97679dad 619 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 620 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 106:ba1f97679dad 621 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 622 } while(0)
Kojto 106:ba1f97679dad 623 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 624 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 625 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 106:ba1f97679dad 626 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 627 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 106:ba1f97679dad 628 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 629 } while(0)
Kojto 106:ba1f97679dad 630
Kojto 106:ba1f97679dad 631 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 106:ba1f97679dad 632 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 106:ba1f97679dad 633 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto 106:ba1f97679dad 634 #define __HAL_RCC_GPIOJ_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOJEN))
Kojto 106:ba1f97679dad 635 #define __HAL_RCC_GPIOK_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOKEN))
Kojto 106:ba1f97679dad 636 #define __HAL_RCC_DMA2D_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2DEN))
Kojto 106:ba1f97679dad 637 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto 106:ba1f97679dad 638 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto 106:ba1f97679dad 639 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto 106:ba1f97679dad 640 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto 106:ba1f97679dad 641 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto 106:ba1f97679dad 642 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto 106:ba1f97679dad 643
Kojto 106:ba1f97679dad 644 /**
Kojto 106:ba1f97679dad 645 * @brief Enable ETHERNET clock.
Kojto 106:ba1f97679dad 646 */
Kojto 106:ba1f97679dad 647 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 648 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto 106:ba1f97679dad 649 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto 106:ba1f97679dad 650 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto 106:ba1f97679dad 651 } while(0)
Kojto 106:ba1f97679dad 652 /**
Kojto 106:ba1f97679dad 653 * @brief Disable ETHERNET clock.
Kojto 106:ba1f97679dad 654 */
Kojto 106:ba1f97679dad 655 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto 106:ba1f97679dad 656 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto 106:ba1f97679dad 657 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto 106:ba1f97679dad 658 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto 106:ba1f97679dad 659 } while(0)
Kojto 106:ba1f97679dad 660
Kojto 106:ba1f97679dad 661 /** @brief Enable or disable the AHB2 peripheral clock.
Kojto 106:ba1f97679dad 662 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 663 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 664 * using it.
Kojto 106:ba1f97679dad 665 */
Kojto 106:ba1f97679dad 666
Kojto 106:ba1f97679dad 667 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 668 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 669 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 106:ba1f97679dad 670 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 671 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 106:ba1f97679dad 672 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 673 } while(0)
Kojto 106:ba1f97679dad 674 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto 106:ba1f97679dad 675
Kojto 106:ba1f97679dad 676 #if defined(STM32F437xx)|| defined(STM32F439xx)
Kojto 106:ba1f97679dad 677 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 678 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 679 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto 106:ba1f97679dad 680 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 681 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto 106:ba1f97679dad 682 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 683 } while(0)
Kojto 106:ba1f97679dad 684 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 685 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 686 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto 106:ba1f97679dad 687 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 688 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto 106:ba1f97679dad 689 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 690 } while(0)
Kojto 106:ba1f97679dad 691
Kojto 106:ba1f97679dad 692 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto 106:ba1f97679dad 693 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto 106:ba1f97679dad 694 #endif /* STM32F437xx || STM32F439xx */
Kojto 106:ba1f97679dad 695
Kojto 106:ba1f97679dad 696 /** @brief Enables or disables the AHB3 peripheral clock.
Kojto 106:ba1f97679dad 697 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 698 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 699 * using it.
Kojto 106:ba1f97679dad 700 */
Kojto 106:ba1f97679dad 701 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 702 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 703 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto 106:ba1f97679dad 704 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 705 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto 106:ba1f97679dad 706 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 707 } while(0)
Kojto 106:ba1f97679dad 708 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto 106:ba1f97679dad 709
Kojto 106:ba1f97679dad 710 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 106:ba1f97679dad 711 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 712 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 713 * using it.
Kojto 106:ba1f97679dad 714 */
Kojto 106:ba1f97679dad 715 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 716 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 717 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 106:ba1f97679dad 718 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 719 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 106:ba1f97679dad 720 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 721 } while(0)
Kojto 106:ba1f97679dad 722 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 723 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 724 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 106:ba1f97679dad 725 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 726 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 106:ba1f97679dad 727 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 728 } while(0)
Kojto 106:ba1f97679dad 729 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 730 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 731 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 106:ba1f97679dad 732 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 733 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 106:ba1f97679dad 734 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 735 } while(0)
Kojto 106:ba1f97679dad 736 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 737 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 738 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 106:ba1f97679dad 739 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 740 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 106:ba1f97679dad 741 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 742 } while(0)
Kojto 106:ba1f97679dad 743 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 744 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 745 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 106:ba1f97679dad 746 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 747 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 106:ba1f97679dad 748 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 749 } while(0)
Kojto 106:ba1f97679dad 750 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 751 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 752 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 106:ba1f97679dad 753 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 754 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 106:ba1f97679dad 755 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 756 } while(0)
Kojto 106:ba1f97679dad 757 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 758 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 759 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 106:ba1f97679dad 760 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 761 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 106:ba1f97679dad 762 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 763 } while(0)
Kojto 106:ba1f97679dad 764 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 765 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 766 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 106:ba1f97679dad 767 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 768 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 106:ba1f97679dad 769 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 770 } while(0)
Kojto 106:ba1f97679dad 771 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 772 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 773 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 106:ba1f97679dad 774 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 775 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 106:ba1f97679dad 776 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 777 } while(0)
Kojto 106:ba1f97679dad 778 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 779 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 780 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 106:ba1f97679dad 781 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 782 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 106:ba1f97679dad 783 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 784 } while(0)
Kojto 106:ba1f97679dad 785 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 786 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 787 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 106:ba1f97679dad 788 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 789 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 106:ba1f97679dad 790 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 791 } while(0)
Kojto 106:ba1f97679dad 792 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 793 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 794 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 106:ba1f97679dad 795 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 796 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 106:ba1f97679dad 797 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 798 } while(0)
Kojto 106:ba1f97679dad 799 #define __HAL_RCC_UART7_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 800 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 801 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto 106:ba1f97679dad 802 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 803 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART7EN);\
Kojto 106:ba1f97679dad 804 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 805 } while(0)
Kojto 106:ba1f97679dad 806 #define __HAL_RCC_UART8_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 807 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 808 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto 106:ba1f97679dad 809 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 810 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART8EN);\
Kojto 106:ba1f97679dad 811 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 812 } while(0)
Kojto 106:ba1f97679dad 813
Kojto 106:ba1f97679dad 814 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 106:ba1f97679dad 815 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 106:ba1f97679dad 816 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 106:ba1f97679dad 817 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 106:ba1f97679dad 818 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 106:ba1f97679dad 819 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 106:ba1f97679dad 820 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 106:ba1f97679dad 821 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 106:ba1f97679dad 822 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto 106:ba1f97679dad 823 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto 106:ba1f97679dad 824 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 106:ba1f97679dad 825 #define __HAL_RCC_UART7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART7EN))
Kojto 106:ba1f97679dad 826 #define __HAL_RCC_UART8_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART8EN))
Kojto 106:ba1f97679dad 827
Kojto 106:ba1f97679dad 828 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 106:ba1f97679dad 829 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 830 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 831 * using it.
Kojto 106:ba1f97679dad 832 */
Kojto 106:ba1f97679dad 833 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 834 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 835 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 106:ba1f97679dad 836 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 837 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 106:ba1f97679dad 838 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 839 } while(0)
Kojto 106:ba1f97679dad 840 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 841 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 842 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 106:ba1f97679dad 843 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 844 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 106:ba1f97679dad 845 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 846 } while(0)
Kojto 106:ba1f97679dad 847 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 848 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 849 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 106:ba1f97679dad 850 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 851 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 106:ba1f97679dad 852 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 853 } while(0)
Kojto 106:ba1f97679dad 854 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 855 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 856 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto 106:ba1f97679dad 857 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 858 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto 106:ba1f97679dad 859 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 860 } while(0)
Kojto 106:ba1f97679dad 861 #define __HAL_RCC_SPI6_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 862 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 863 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto 106:ba1f97679dad 864 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 865 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI6EN);\
Kojto 106:ba1f97679dad 866 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 867 } while(0)
Kojto 106:ba1f97679dad 868 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 869 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 870 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto 106:ba1f97679dad 871 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 872 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto 106:ba1f97679dad 873 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 874 } while(0)
Kojto 106:ba1f97679dad 875
Kojto 106:ba1f97679dad 876 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 106:ba1f97679dad 877 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto 106:ba1f97679dad 878 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto 106:ba1f97679dad 879 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto 106:ba1f97679dad 880 #define __HAL_RCC_SPI6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI6EN))
Kojto 106:ba1f97679dad 881 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto 106:ba1f97679dad 882
Kojto 106:ba1f97679dad 883 #if defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 106:ba1f97679dad 884 #define __HAL_RCC_LTDC_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_LTDCEN))
Kojto 106:ba1f97679dad 885
Kojto 106:ba1f97679dad 886 #define __HAL_RCC_LTDC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_LTDCEN))
Kojto 106:ba1f97679dad 887 #endif /* STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 888
Kojto 106:ba1f97679dad 889 /** @brief Force or release AHB1 peripheral reset.
Kojto 106:ba1f97679dad 890 */
Kojto 106:ba1f97679dad 891 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
Kojto 106:ba1f97679dad 892 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
Kojto 106:ba1f97679dad 893 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
Kojto 106:ba1f97679dad 894 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
Kojto 106:ba1f97679dad 895 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
Kojto 106:ba1f97679dad 896 #define __HAL_RCC_GPIOJ_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOJRST))
Kojto 106:ba1f97679dad 897 #define __HAL_RCC_GPIOK_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOKRST))
Kojto 106:ba1f97679dad 898 #define __HAL_RCC_DMA2D_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_DMA2DRST))
Kojto 106:ba1f97679dad 899
Kojto 106:ba1f97679dad 900 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 106:ba1f97679dad 901 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 106:ba1f97679dad 902 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 106:ba1f97679dad 903 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto 106:ba1f97679dad 904 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto 106:ba1f97679dad 905 #define __HAL_RCC_GPIOJ_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOJRST))
Kojto 106:ba1f97679dad 906 #define __HAL_RCC_GPIOK_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOKRST))
Kojto 106:ba1f97679dad 907 #define __HAL_RCC_DMA2D_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2DRST))
Kojto 106:ba1f97679dad 908
Kojto 106:ba1f97679dad 909 /** @brief Force or release AHB2 peripheral reset.
Kojto 106:ba1f97679dad 910 */
Kojto 106:ba1f97679dad 911 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
Kojto 106:ba1f97679dad 912 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto 106:ba1f97679dad 913
Kojto 106:ba1f97679dad 914 #if defined(STM32F437xx)|| defined(STM32F439xx)
Kojto 106:ba1f97679dad 915 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
Kojto 106:ba1f97679dad 916 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
Kojto 106:ba1f97679dad 917
Kojto 106:ba1f97679dad 918 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto 106:ba1f97679dad 919 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto 106:ba1f97679dad 920 #endif /* STM32F437xx || STM32F439xx */
Kojto 106:ba1f97679dad 921
Kojto 106:ba1f97679dad 922 /** @brief Force or release AHB3 peripheral reset
Kojto 106:ba1f97679dad 923 */
Kojto 106:ba1f97679dad 924 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
Kojto 106:ba1f97679dad 925 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto 106:ba1f97679dad 926
Kojto 106:ba1f97679dad 927 /** @brief Force or release APB1 peripheral reset.
Kojto 106:ba1f97679dad 928 */
Kojto 106:ba1f97679dad 929 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 106:ba1f97679dad 930 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 106:ba1f97679dad 931 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 106:ba1f97679dad 932 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 106:ba1f97679dad 933 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 106:ba1f97679dad 934 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 106:ba1f97679dad 935 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 106:ba1f97679dad 936 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 106:ba1f97679dad 937 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
Kojto 106:ba1f97679dad 938 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
Kojto 106:ba1f97679dad 939 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 106:ba1f97679dad 940 #define __HAL_RCC_UART7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART7RST))
Kojto 106:ba1f97679dad 941 #define __HAL_RCC_UART8_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART8RST))
Kojto 106:ba1f97679dad 942
Kojto 106:ba1f97679dad 943 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 106:ba1f97679dad 944 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 106:ba1f97679dad 945 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 106:ba1f97679dad 946 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 106:ba1f97679dad 947 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 106:ba1f97679dad 948 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 106:ba1f97679dad 949 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 106:ba1f97679dad 950 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 106:ba1f97679dad 951 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto 106:ba1f97679dad 952 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto 106:ba1f97679dad 953 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 106:ba1f97679dad 954 #define __HAL_RCC_UART7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART7RST))
Kojto 106:ba1f97679dad 955 #define __HAL_RCC_UART8_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART8RST))
Kojto 106:ba1f97679dad 956
Kojto 106:ba1f97679dad 957 /** @brief Force or release APB2 peripheral reset.
Kojto 106:ba1f97679dad 958 */
Kojto 106:ba1f97679dad 959 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 106:ba1f97679dad 960 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
Kojto 106:ba1f97679dad 961 #define __HAL_RCC_SPI6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI6RST))
Kojto 106:ba1f97679dad 962 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
Kojto 106:ba1f97679dad 963
Kojto 106:ba1f97679dad 964 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 106:ba1f97679dad 965 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto 106:ba1f97679dad 966 #define __HAL_RCC_SPI6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI6RST))
Kojto 106:ba1f97679dad 967 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto 106:ba1f97679dad 968
Kojto 106:ba1f97679dad 969 #if defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 106:ba1f97679dad 970 #define __HAL_RCC_LTDC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_LTDCRST))
Kojto 106:ba1f97679dad 971 #define __HAL_RCC_LTDC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_LTDCRST))
Kojto 106:ba1f97679dad 972 #endif /* STM32F429xx|| STM32F439xx */
Kojto 106:ba1f97679dad 973
Kojto 106:ba1f97679dad 974 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 975 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 976 * power consumption.
Kojto 106:ba1f97679dad 977 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 978 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 979 */
Kojto 106:ba1f97679dad 980 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto 106:ba1f97679dad 981 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto 106:ba1f97679dad 982 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
Kojto 106:ba1f97679dad 983 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto 106:ba1f97679dad 984 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto 106:ba1f97679dad 985 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 106:ba1f97679dad 986 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 106:ba1f97679dad 987 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 106:ba1f97679dad 988 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto 106:ba1f97679dad 989 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 106:ba1f97679dad 990 #define __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOJLPEN))
Kojto 106:ba1f97679dad 991 #define __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOKLPEN))
Kojto 106:ba1f97679dad 992 #define __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM3LPEN))
Kojto 106:ba1f97679dad 993 #define __HAL_RCC_DMA2D_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_DMA2DLPEN))
Kojto 106:ba1f97679dad 994
Kojto 106:ba1f97679dad 995 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto 106:ba1f97679dad 996 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto 106:ba1f97679dad 997 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto 106:ba1f97679dad 998 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto 106:ba1f97679dad 999 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto 106:ba1f97679dad 1000 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 106:ba1f97679dad 1001 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 106:ba1f97679dad 1002 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 106:ba1f97679dad 1003 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto 106:ba1f97679dad 1004 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 106:ba1f97679dad 1005 #define __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOJLPEN))
Kojto 106:ba1f97679dad 1006 #define __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOKLPEN))
Kojto 106:ba1f97679dad 1007 #define __HAL_RCC_DMA2D_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2DLPEN))
Kojto 106:ba1f97679dad 1008
Kojto 106:ba1f97679dad 1009 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1010 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1011 * power consumption.
Kojto 106:ba1f97679dad 1012 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1013 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1014 */
Kojto 106:ba1f97679dad 1015 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Kojto 106:ba1f97679dad 1016 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto 106:ba1f97679dad 1017
Kojto 106:ba1f97679dad 1018 #if defined(STM32F437xx)|| defined(STM32F439xx)
Kojto 106:ba1f97679dad 1019 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
Kojto 106:ba1f97679dad 1020 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
Kojto 106:ba1f97679dad 1021
Kojto 106:ba1f97679dad 1022 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto 106:ba1f97679dad 1023 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto 106:ba1f97679dad 1024 #endif /* STM32F437xx || STM32F439xx */
Kojto 106:ba1f97679dad 1025
Kojto 106:ba1f97679dad 1026 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1027 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1028 * power consumption.
Kojto 106:ba1f97679dad 1029 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1030 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1031 */
Kojto 106:ba1f97679dad 1032 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
Kojto 106:ba1f97679dad 1033 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto 106:ba1f97679dad 1034
Kojto 106:ba1f97679dad 1035 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1036 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1037 * power consumption.
Kojto 106:ba1f97679dad 1038 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1039 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1040 */
Kojto 106:ba1f97679dad 1041 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
Kojto 106:ba1f97679dad 1042 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
Kojto 106:ba1f97679dad 1043 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
Kojto 106:ba1f97679dad 1044 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
Kojto 106:ba1f97679dad 1045 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
Kojto 106:ba1f97679dad 1046 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
Kojto 106:ba1f97679dad 1047 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
Kojto 106:ba1f97679dad 1048 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
Kojto 106:ba1f97679dad 1049 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
Kojto 106:ba1f97679dad 1050 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
Kojto 106:ba1f97679dad 1051 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
Kojto 106:ba1f97679dad 1052 #define __HAL_RCC_UART7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART7LPEN))
Kojto 106:ba1f97679dad 1053 #define __HAL_RCC_UART8_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART8LPEN))
Kojto 106:ba1f97679dad 1054
Kojto 106:ba1f97679dad 1055 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto 106:ba1f97679dad 1056 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto 106:ba1f97679dad 1057 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto 106:ba1f97679dad 1058 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto 106:ba1f97679dad 1059 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto 106:ba1f97679dad 1060 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto 106:ba1f97679dad 1061 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto 106:ba1f97679dad 1062 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto 106:ba1f97679dad 1063 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto 106:ba1f97679dad 1064 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto 106:ba1f97679dad 1065 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto 106:ba1f97679dad 1066 #define __HAL_RCC_UART7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART7LPEN))
Kojto 106:ba1f97679dad 1067 #define __HAL_RCC_UART8_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART8LPEN))
Kojto 106:ba1f97679dad 1068
Kojto 106:ba1f97679dad 1069 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1070 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1071 * power consumption.
Kojto 106:ba1f97679dad 1072 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1073 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1074 */
Kojto 106:ba1f97679dad 1075 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
Kojto 106:ba1f97679dad 1076 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
Kojto 106:ba1f97679dad 1077 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
Kojto 106:ba1f97679dad 1078 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
Kojto 106:ba1f97679dad 1079 #define __HAL_RCC_SPI6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI6LPEN))
Kojto 106:ba1f97679dad 1080 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
Kojto 106:ba1f97679dad 1081
Kojto 106:ba1f97679dad 1082 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto 106:ba1f97679dad 1083 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto 106:ba1f97679dad 1084 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto 106:ba1f97679dad 1085 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto 106:ba1f97679dad 1086 #define __HAL_RCC_SPI6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI6LPEN))
Kojto 106:ba1f97679dad 1087 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto 106:ba1f97679dad 1088
Kojto 106:ba1f97679dad 1089 #if defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 106:ba1f97679dad 1090 #define __HAL_RCC_LTDC_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_LTDCLPEN))
Kojto 106:ba1f97679dad 1091
Kojto 106:ba1f97679dad 1092 #define __HAL_RCC_LTDC_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_LTDCLPEN))
Kojto 106:ba1f97679dad 1093 #endif /* STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 1094
Kojto 106:ba1f97679dad 1095 #endif /* STM32F427xx || STM32F437xx || STM32F429xx|| STM32F439xx */
Kojto 106:ba1f97679dad 1096 /*---------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 1097
Kojto 106:ba1f97679dad 1098 /*----------------------------------- STM32F40xxx/STM32F41xxx----------------------------------*/
Kojto 106:ba1f97679dad 1099 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 106:ba1f97679dad 1100 /** @brief Enables or disables the AHB1 peripheral clock.
Kojto 106:ba1f97679dad 1101 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1102 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1103 * using it.
Kojto 106:ba1f97679dad 1104 */
Kojto 106:ba1f97679dad 1105 #define __HAL_RCC_GPIOI_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1106 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1107 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto 106:ba1f97679dad 1108 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1109 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOIEN);\
Kojto 106:ba1f97679dad 1110 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1111 } while(0)
Kojto 106:ba1f97679dad 1112 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1113 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1114 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 106:ba1f97679dad 1115 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1116 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 106:ba1f97679dad 1117 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1118 } while(0)
Kojto 106:ba1f97679dad 1119 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1120 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1121 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 106:ba1f97679dad 1122 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1123 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 106:ba1f97679dad 1124 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1125 } while(0)
Kojto 106:ba1f97679dad 1126 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1127 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1128 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 106:ba1f97679dad 1129 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1130 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 106:ba1f97679dad 1131 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1132 } while(0)
Kojto 106:ba1f97679dad 1133 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1134 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1135 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 106:ba1f97679dad 1136 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1137 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 106:ba1f97679dad 1138 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1139 } while(0)
Kojto 106:ba1f97679dad 1140
Kojto 106:ba1f97679dad 1141 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 106:ba1f97679dad 1142 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 106:ba1f97679dad 1143 #define __HAL_RCC_GPIOI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOIEN))
Kojto 106:ba1f97679dad 1144 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto 106:ba1f97679dad 1145 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto 106:ba1f97679dad 1146
Kojto 106:ba1f97679dad 1147 #if defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 106:ba1f97679dad 1148 /**
Kojto 106:ba1f97679dad 1149 * @brief Enable ETHERNET clock.
Kojto 106:ba1f97679dad 1150 */
Kojto 106:ba1f97679dad 1151 #define __HAL_RCC_ETHMAC_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1152 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1153 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto 106:ba1f97679dad 1154 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1155 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACEN);\
Kojto 106:ba1f97679dad 1156 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1157 } while(0)
Kojto 106:ba1f97679dad 1158 #define __HAL_RCC_ETHMACTX_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1159 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1160 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto 106:ba1f97679dad 1161 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1162 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACTXEN);\
Kojto 106:ba1f97679dad 1163 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1164 } while(0)
Kojto 106:ba1f97679dad 1165 #define __HAL_RCC_ETHMACRX_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1166 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1167 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto 106:ba1f97679dad 1168 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1169 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACRXEN);\
Kojto 106:ba1f97679dad 1170 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1171 } while(0)
Kojto 106:ba1f97679dad 1172 #define __HAL_RCC_ETHMACPTP_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1173 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1174 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto 106:ba1f97679dad 1175 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1176 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_ETHMACPTPEN);\
Kojto 106:ba1f97679dad 1177 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1178 } while(0)
Kojto 106:ba1f97679dad 1179 #define __HAL_RCC_ETH_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1180 __HAL_RCC_ETHMAC_CLK_ENABLE(); \
Kojto 106:ba1f97679dad 1181 __HAL_RCC_ETHMACTX_CLK_ENABLE(); \
Kojto 106:ba1f97679dad 1182 __HAL_RCC_ETHMACRX_CLK_ENABLE(); \
Kojto 106:ba1f97679dad 1183 } while(0)
Kojto 106:ba1f97679dad 1184
Kojto 106:ba1f97679dad 1185 /**
Kojto 106:ba1f97679dad 1186 * @brief Disable ETHERNET clock.
Kojto 106:ba1f97679dad 1187 */
Kojto 106:ba1f97679dad 1188 #define __HAL_RCC_ETHMAC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACEN))
Kojto 106:ba1f97679dad 1189 #define __HAL_RCC_ETHMACTX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACTXEN))
Kojto 106:ba1f97679dad 1190 #define __HAL_RCC_ETHMACRX_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACRXEN))
Kojto 106:ba1f97679dad 1191 #define __HAL_RCC_ETHMACPTP_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_ETHMACPTPEN))
Kojto 106:ba1f97679dad 1192 #define __HAL_RCC_ETH_CLK_DISABLE() do { \
Kojto 106:ba1f97679dad 1193 __HAL_RCC_ETHMACTX_CLK_DISABLE(); \
Kojto 106:ba1f97679dad 1194 __HAL_RCC_ETHMACRX_CLK_DISABLE(); \
Kojto 106:ba1f97679dad 1195 __HAL_RCC_ETHMAC_CLK_DISABLE(); \
Kojto 106:ba1f97679dad 1196 } while(0)
Kojto 106:ba1f97679dad 1197 #endif /* STM32F407xx || STM32F417xx */
Kojto 106:ba1f97679dad 1198
Kojto 106:ba1f97679dad 1199 /** @brief Enable or disable the AHB2 peripheral clock.
Kojto 106:ba1f97679dad 1200 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1201 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1202 * using it.
Kojto 106:ba1f97679dad 1203 */
Kojto 106:ba1f97679dad 1204 #if defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 106:ba1f97679dad 1205 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1206 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1207 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 106:ba1f97679dad 1208 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1209 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 106:ba1f97679dad 1210 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1211 } while(0)
Kojto 106:ba1f97679dad 1212 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto 106:ba1f97679dad 1213 #endif /* STM32F407xx || STM32F417xx */
Kojto 106:ba1f97679dad 1214
Kojto 106:ba1f97679dad 1215 #if defined(STM32F415xx) || defined(STM32F417xx)
Kojto 106:ba1f97679dad 1216 #define __HAL_RCC_CRYP_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1217 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1218 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto 106:ba1f97679dad 1219 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1220 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_CRYPEN);\
Kojto 106:ba1f97679dad 1221 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1222 } while(0)
Kojto 106:ba1f97679dad 1223 #define __HAL_RCC_HASH_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1224 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1225 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto 106:ba1f97679dad 1226 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1227 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_HASHEN);\
Kojto 106:ba1f97679dad 1228 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1229 } while(0)
Kojto 106:ba1f97679dad 1230 #define __HAL_RCC_CRYP_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_CRYPEN))
Kojto 106:ba1f97679dad 1231 #define __HAL_RCC_HASH_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_HASHEN))
Kojto 106:ba1f97679dad 1232 #endif /* STM32F415xx || STM32F417xx */
Kojto 106:ba1f97679dad 1233
Kojto 106:ba1f97679dad 1234 /** @brief Enables or disables the AHB3 peripheral clock.
Kojto 106:ba1f97679dad 1235 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1236 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1237 * using it.
Kojto 106:ba1f97679dad 1238 */
Kojto 106:ba1f97679dad 1239 #define __HAL_RCC_FSMC_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1240 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1241 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto 106:ba1f97679dad 1242 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1243 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FSMCEN);\
Kojto 106:ba1f97679dad 1244 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1245 } while(0)
Kojto 106:ba1f97679dad 1246 #define __HAL_RCC_FSMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FSMCEN))
Kojto 106:ba1f97679dad 1247
Kojto 106:ba1f97679dad 1248 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 106:ba1f97679dad 1249 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1250 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1251 * using it.
Kojto 106:ba1f97679dad 1252 */
Kojto 106:ba1f97679dad 1253 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1254 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1255 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 106:ba1f97679dad 1256 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1257 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 106:ba1f97679dad 1258 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1259 } while(0)
Kojto 106:ba1f97679dad 1260 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1261 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1262 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 106:ba1f97679dad 1263 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1264 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 106:ba1f97679dad 1265 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1266 } while(0)
Kojto 106:ba1f97679dad 1267 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1268 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1269 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 106:ba1f97679dad 1270 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1271 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 106:ba1f97679dad 1272 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1273 } while(0)
Kojto 106:ba1f97679dad 1274 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1275 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1276 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 106:ba1f97679dad 1277 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1278 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 106:ba1f97679dad 1279 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1280 } while(0)
Kojto 106:ba1f97679dad 1281 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1282 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1283 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 106:ba1f97679dad 1284 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1285 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 106:ba1f97679dad 1286 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1287 } while(0)
Kojto 106:ba1f97679dad 1288 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1289 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1290 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 106:ba1f97679dad 1291 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1292 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 106:ba1f97679dad 1293 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1294 } while(0)
Kojto 106:ba1f97679dad 1295 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1296 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1297 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 106:ba1f97679dad 1298 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1299 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 106:ba1f97679dad 1300 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1301 } while(0)
Kojto 106:ba1f97679dad 1302 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1303 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1304 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 106:ba1f97679dad 1305 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1306 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 106:ba1f97679dad 1307 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1308 } while(0)
Kojto 106:ba1f97679dad 1309 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1310 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1311 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 106:ba1f97679dad 1312 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1313 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 106:ba1f97679dad 1314 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1315 } while(0)
Kojto 106:ba1f97679dad 1316 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1317 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1318 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 106:ba1f97679dad 1319 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1320 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 106:ba1f97679dad 1321 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1322 } while(0)
Kojto 106:ba1f97679dad 1323 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1324 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1325 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 106:ba1f97679dad 1326 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1327 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 106:ba1f97679dad 1328 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1329 } while(0)
Kojto 106:ba1f97679dad 1330
Kojto 106:ba1f97679dad 1331 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 106:ba1f97679dad 1332 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 106:ba1f97679dad 1333 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 106:ba1f97679dad 1334 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 106:ba1f97679dad 1335 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 106:ba1f97679dad 1336 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 106:ba1f97679dad 1337 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 106:ba1f97679dad 1338 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 106:ba1f97679dad 1339 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto 106:ba1f97679dad 1340 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto 106:ba1f97679dad 1341 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 106:ba1f97679dad 1342
Kojto 106:ba1f97679dad 1343 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 106:ba1f97679dad 1344 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1345 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1346 * using it.
Kojto 106:ba1f97679dad 1347 */
Kojto 106:ba1f97679dad 1348 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1349 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1350 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 106:ba1f97679dad 1351 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1352 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 106:ba1f97679dad 1353 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1354 } while(0)
Kojto 106:ba1f97679dad 1355 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1356 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1357 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 106:ba1f97679dad 1358 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1359 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 106:ba1f97679dad 1360 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1361 } while(0)
Kojto 106:ba1f97679dad 1362 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1363 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1364 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 106:ba1f97679dad 1365 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1366 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 106:ba1f97679dad 1367 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1368 } while(0)
Kojto 106:ba1f97679dad 1369
Kojto 106:ba1f97679dad 1370 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 106:ba1f97679dad 1371 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto 106:ba1f97679dad 1372 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto 106:ba1f97679dad 1373
Kojto 106:ba1f97679dad 1374 /** @brief Force or release AHB1 peripheral reset.
Kojto 106:ba1f97679dad 1375 */
Kojto 106:ba1f97679dad 1376 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
Kojto 106:ba1f97679dad 1377 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
Kojto 106:ba1f97679dad 1378 #define __HAL_RCC_GPIOI_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOIRST))
Kojto 106:ba1f97679dad 1379 #define __HAL_RCC_ETHMAC_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_ETHMACRST))
Kojto 106:ba1f97679dad 1380 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
Kojto 106:ba1f97679dad 1381
Kojto 106:ba1f97679dad 1382 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 106:ba1f97679dad 1383 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 106:ba1f97679dad 1384 #define __HAL_RCC_GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
Kojto 106:ba1f97679dad 1385 #define __HAL_RCC_ETHMAC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_ETHMACRST))
Kojto 106:ba1f97679dad 1386 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto 106:ba1f97679dad 1387
Kojto 106:ba1f97679dad 1388 /** @brief Force or release AHB2 peripheral reset.
Kojto 106:ba1f97679dad 1389 */
Kojto 106:ba1f97679dad 1390 #if defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 106:ba1f97679dad 1391 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
Kojto 106:ba1f97679dad 1392 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto 106:ba1f97679dad 1393 #endif /* STM32F407xx || STM32F417xx */
Kojto 106:ba1f97679dad 1394
Kojto 106:ba1f97679dad 1395 #if defined(STM32F415xx) || defined(STM32F417xx)
Kojto 106:ba1f97679dad 1396 #define __HAL_RCC_CRYP_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_CRYPRST))
Kojto 106:ba1f97679dad 1397 #define __HAL_RCC_HASH_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_HASHRST))
Kojto 106:ba1f97679dad 1398
Kojto 106:ba1f97679dad 1399 #define __HAL_RCC_CRYP_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_CRYPRST))
Kojto 106:ba1f97679dad 1400 #define __HAL_RCC_HASH_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_HASHRST))
Kojto 106:ba1f97679dad 1401
Kojto 106:ba1f97679dad 1402 #endif /* STM32F415xx || STM32F417xx */
Kojto 106:ba1f97679dad 1403
Kojto 106:ba1f97679dad 1404 /** @brief Force or release AHB3 peripheral reset
Kojto 106:ba1f97679dad 1405 */
Kojto 106:ba1f97679dad 1406 #define __HAL_RCC_FSMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FSMCRST))
Kojto 106:ba1f97679dad 1407 #define __HAL_RCC_FSMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FSMCRST))
Kojto 106:ba1f97679dad 1408
Kojto 106:ba1f97679dad 1409 /** @brief Force or release APB1 peripheral reset.
Kojto 106:ba1f97679dad 1410 */
Kojto 106:ba1f97679dad 1411 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 106:ba1f97679dad 1412 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 106:ba1f97679dad 1413 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 106:ba1f97679dad 1414 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 106:ba1f97679dad 1415 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 106:ba1f97679dad 1416 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 106:ba1f97679dad 1417 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 106:ba1f97679dad 1418 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 106:ba1f97679dad 1419 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
Kojto 106:ba1f97679dad 1420 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
Kojto 106:ba1f97679dad 1421 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 106:ba1f97679dad 1422
Kojto 106:ba1f97679dad 1423 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 106:ba1f97679dad 1424 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 106:ba1f97679dad 1425 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 106:ba1f97679dad 1426 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 106:ba1f97679dad 1427 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 106:ba1f97679dad 1428 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 106:ba1f97679dad 1429 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 106:ba1f97679dad 1430 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 106:ba1f97679dad 1431 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto 106:ba1f97679dad 1432 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto 106:ba1f97679dad 1433 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 106:ba1f97679dad 1434
Kojto 106:ba1f97679dad 1435 /** @brief Force or release APB2 peripheral reset.
Kojto 106:ba1f97679dad 1436 */
Kojto 106:ba1f97679dad 1437 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 106:ba1f97679dad 1438 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 106:ba1f97679dad 1439
Kojto 106:ba1f97679dad 1440 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1441 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1442 * power consumption.
Kojto 106:ba1f97679dad 1443 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1444 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1445 */
Kojto 106:ba1f97679dad 1446 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto 106:ba1f97679dad 1447 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto 106:ba1f97679dad 1448 #define __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOILPEN))
Kojto 106:ba1f97679dad 1449 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto 106:ba1f97679dad 1450 #define __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACLPEN))
Kojto 106:ba1f97679dad 1451 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 106:ba1f97679dad 1452 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 106:ba1f97679dad 1453 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 106:ba1f97679dad 1454 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto 106:ba1f97679dad 1455 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 106:ba1f97679dad 1456
Kojto 106:ba1f97679dad 1457 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto 106:ba1f97679dad 1458 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto 106:ba1f97679dad 1459 #define __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOILPEN))
Kojto 106:ba1f97679dad 1460 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto 106:ba1f97679dad 1461 #define __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACLPEN))
Kojto 106:ba1f97679dad 1462 #define __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACTXLPEN))
Kojto 106:ba1f97679dad 1463 #define __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACRXLPEN))
Kojto 106:ba1f97679dad 1464 #define __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_ETHMACPTPLPEN))
Kojto 106:ba1f97679dad 1465 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto 106:ba1f97679dad 1466 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 106:ba1f97679dad 1467
Kojto 106:ba1f97679dad 1468 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1469 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1470 * power consumption.
Kojto 106:ba1f97679dad 1471 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1472 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1473 */
Kojto 106:ba1f97679dad 1474 #if defined(STM32F407xx)|| defined(STM32F417xx)
Kojto 106:ba1f97679dad 1475 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Kojto 106:ba1f97679dad 1476 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto 106:ba1f97679dad 1477 #endif /* STM32F407xx || STM32F417xx */
Kojto 106:ba1f97679dad 1478
Kojto 106:ba1f97679dad 1479 #if defined(STM32F415xx) || defined(STM32F417xx)
Kojto 106:ba1f97679dad 1480 #define __HAL_RCC_CRYP_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_CRYPLPEN))
Kojto 106:ba1f97679dad 1481 #define __HAL_RCC_HASH_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_HASHLPEN))
Kojto 106:ba1f97679dad 1482
Kojto 106:ba1f97679dad 1483 #define __HAL_RCC_CRYP_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_CRYPLPEN))
Kojto 106:ba1f97679dad 1484 #define __HAL_RCC_HASH_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_HASHLPEN))
Kojto 106:ba1f97679dad 1485 #endif /* STM32F415xx || STM32F417xx */
Kojto 106:ba1f97679dad 1486
Kojto 106:ba1f97679dad 1487 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1488 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1489 * power consumption.
Kojto 106:ba1f97679dad 1490 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1491 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1492 */
Kojto 106:ba1f97679dad 1493 #define __HAL_RCC_FSMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FSMCLPEN))
Kojto 106:ba1f97679dad 1494 #define __HAL_RCC_FSMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FSMCLPEN))
Kojto 106:ba1f97679dad 1495
Kojto 106:ba1f97679dad 1496 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1497 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1498 * power consumption.
Kojto 106:ba1f97679dad 1499 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1500 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1501 */
Kojto 106:ba1f97679dad 1502 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
Kojto 106:ba1f97679dad 1503 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
Kojto 106:ba1f97679dad 1504 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
Kojto 106:ba1f97679dad 1505 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
Kojto 106:ba1f97679dad 1506 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
Kojto 106:ba1f97679dad 1507 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
Kojto 106:ba1f97679dad 1508 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
Kojto 106:ba1f97679dad 1509 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
Kojto 106:ba1f97679dad 1510 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
Kojto 106:ba1f97679dad 1511 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
Kojto 106:ba1f97679dad 1512 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
Kojto 106:ba1f97679dad 1513
Kojto 106:ba1f97679dad 1514 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto 106:ba1f97679dad 1515 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto 106:ba1f97679dad 1516 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto 106:ba1f97679dad 1517 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto 106:ba1f97679dad 1518 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto 106:ba1f97679dad 1519 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto 106:ba1f97679dad 1520 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto 106:ba1f97679dad 1521 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto 106:ba1f97679dad 1522 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto 106:ba1f97679dad 1523 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto 106:ba1f97679dad 1524 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto 106:ba1f97679dad 1525
Kojto 106:ba1f97679dad 1526 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1527 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1528 * power consumption.
Kojto 106:ba1f97679dad 1529 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1530 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1531 */
Kojto 106:ba1f97679dad 1532 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
Kojto 106:ba1f97679dad 1533 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
Kojto 106:ba1f97679dad 1534 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
Kojto 106:ba1f97679dad 1535
Kojto 106:ba1f97679dad 1536 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto 106:ba1f97679dad 1537 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto 106:ba1f97679dad 1538 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto 106:ba1f97679dad 1539 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
Kojto 106:ba1f97679dad 1540 /*---------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 1541
Kojto 106:ba1f97679dad 1542 /*------------------------------------------ STM32F411xx --------------------------------------*/
Kojto 106:ba1f97679dad 1543 #if defined(STM32F411xE)
Kojto 106:ba1f97679dad 1544 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 106:ba1f97679dad 1545 */
Kojto 106:ba1f97679dad 1546 #define __HAL_RCC_SPI5_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1547 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1548 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto 106:ba1f97679dad 1549 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1550 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI5EN);\
Kojto 106:ba1f97679dad 1551 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1552 } while(0)
Kojto 106:ba1f97679dad 1553 #define __HAL_RCC_SPI5_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI5EN))
Kojto 106:ba1f97679dad 1554
Kojto 106:ba1f97679dad 1555 /** @brief Force or release APB2 peripheral reset.
Kojto 106:ba1f97679dad 1556 */
Kojto 106:ba1f97679dad 1557 #define __HAL_RCC_SPI5_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI5RST))
Kojto 106:ba1f97679dad 1558 #define __HAL_RCC_SPI5_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI5RST))
Kojto 106:ba1f97679dad 1559
Kojto 106:ba1f97679dad 1560 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1561 */
Kojto 106:ba1f97679dad 1562 #define __HAL_RCC_SPI5_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI5LPEN))
Kojto 106:ba1f97679dad 1563 #define __HAL_RCC_SPI5_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI5LPEN))
Kojto 106:ba1f97679dad 1564
Kojto 106:ba1f97679dad 1565 #endif /* STM32F411xE */
Kojto 106:ba1f97679dad 1566 /*---------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 1567
Kojto 106:ba1f97679dad 1568 /*----------------------------------------- STM32F446xx ---------------------------------------*/
Kojto 106:ba1f97679dad 1569 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 1570 /** @brief Enables or disables the AHB1 peripheral clock.
Kojto 106:ba1f97679dad 1571 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1572 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1573 * using it.
Kojto 106:ba1f97679dad 1574 */
Kojto 106:ba1f97679dad 1575 #define __HAL_RCC_GPIOF_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1576 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1577 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 106:ba1f97679dad 1578 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1579 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOFEN);\
Kojto 106:ba1f97679dad 1580 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1581 } while(0)
Kojto 106:ba1f97679dad 1582 #define __HAL_RCC_GPIOG_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1583 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1584 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 106:ba1f97679dad 1585 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1586 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_GPIOGEN);\
Kojto 106:ba1f97679dad 1587 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1588 } while(0)
Kojto 106:ba1f97679dad 1589 #define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1590 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1591 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 106:ba1f97679dad 1592 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1593 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSEN);\
Kojto 106:ba1f97679dad 1594 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1595 } while(0)
Kojto 106:ba1f97679dad 1596 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1597 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1598 SET_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 106:ba1f97679dad 1599 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1600 tmpreg = READ_BIT(RCC->AHB1ENR, RCC_AHB1ENR_OTGHSULPIEN);\
Kojto 106:ba1f97679dad 1601 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1602 } while(0)
Kojto 106:ba1f97679dad 1603
Kojto 106:ba1f97679dad 1604 #define __HAL_RCC_GPIOF_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOFEN))
Kojto 106:ba1f97679dad 1605 #define __HAL_RCC_GPIOG_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOGEN))
Kojto 106:ba1f97679dad 1606 #define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSEN))
Kojto 106:ba1f97679dad 1607 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_OTGHSULPIEN))
Kojto 106:ba1f97679dad 1608
Kojto 106:ba1f97679dad 1609 /** @brief Enable or disable the AHB2 peripheral clock.
Kojto 106:ba1f97679dad 1610 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1611 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1612 * using it.
Kojto 106:ba1f97679dad 1613 */
Kojto 106:ba1f97679dad 1614 #define __HAL_RCC_DCMI_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1615 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1616 SET_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 106:ba1f97679dad 1617 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1618 tmpreg = READ_BIT(RCC->AHB2ENR, RCC_AHB2ENR_DCMIEN);\
Kojto 106:ba1f97679dad 1619 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1620 } while(0)
Kojto 106:ba1f97679dad 1621 #define __HAL_RCC_DCMI_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_DCMIEN))
Kojto 106:ba1f97679dad 1622
Kojto 106:ba1f97679dad 1623 /** @brief Enables or disables the AHB3 peripheral clock.
Kojto 106:ba1f97679dad 1624 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1625 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1626 * using it.
Kojto 106:ba1f97679dad 1627 */
Kojto 106:ba1f97679dad 1628 #define __HAL_RCC_FMC_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1629 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1630 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto 106:ba1f97679dad 1631 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1632 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_FMCEN);\
Kojto 106:ba1f97679dad 1633 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1634 } while(0)
Kojto 106:ba1f97679dad 1635 #define __HAL_RCC_QSPI_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1636 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1637 SET_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto 106:ba1f97679dad 1638 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1639 tmpreg = READ_BIT(RCC->AHB3ENR, RCC_AHB3ENR_QSPIEN);\
Kojto 106:ba1f97679dad 1640 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1641 } while(0)
Kojto 106:ba1f97679dad 1642
Kojto 106:ba1f97679dad 1643 #define __HAL_RCC_FMC_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_FMCEN))
Kojto 106:ba1f97679dad 1644 #define __HAL_RCC_QSPI_CLK_DISABLE() (RCC->AHB3ENR &= ~(RCC_AHB3ENR_QSPIEN))
Kojto 106:ba1f97679dad 1645
Kojto 106:ba1f97679dad 1646 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 106:ba1f97679dad 1647 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1648 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1649 * using it.
Kojto 106:ba1f97679dad 1650 */
Kojto 106:ba1f97679dad 1651 #define __HAL_RCC_TIM6_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1652 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1653 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 106:ba1f97679dad 1654 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1655 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM6EN);\
Kojto 106:ba1f97679dad 1656 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1657 } while(0)
Kojto 106:ba1f97679dad 1658 #define __HAL_RCC_TIM7_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1659 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1660 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 106:ba1f97679dad 1661 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1662 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM7EN);\
Kojto 106:ba1f97679dad 1663 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1664 } while(0)
Kojto 106:ba1f97679dad 1665 #define __HAL_RCC_TIM12_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1666 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1667 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 106:ba1f97679dad 1668 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1669 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM12EN);\
Kojto 106:ba1f97679dad 1670 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1671 } while(0)
Kojto 106:ba1f97679dad 1672 #define __HAL_RCC_TIM13_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1673 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1674 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 106:ba1f97679dad 1675 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1676 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM13EN);\
Kojto 106:ba1f97679dad 1677 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1678 } while(0)
Kojto 106:ba1f97679dad 1679 #define __HAL_RCC_TIM14_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1680 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1681 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 106:ba1f97679dad 1682 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1683 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM14EN);\
Kojto 106:ba1f97679dad 1684 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1685 } while(0)
Kojto 106:ba1f97679dad 1686 #define __HAL_RCC_SPDIFRX_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1687 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1688 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto 106:ba1f97679dad 1689 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1690 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_SPDIFRXEN);\
Kojto 106:ba1f97679dad 1691 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1692 } while(0)
Kojto 106:ba1f97679dad 1693 #define __HAL_RCC_USART3_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1694 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1695 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 106:ba1f97679dad 1696 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1697 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART3EN);\
Kojto 106:ba1f97679dad 1698 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1699 } while(0)
Kojto 106:ba1f97679dad 1700 #define __HAL_RCC_UART4_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1701 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1702 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 106:ba1f97679dad 1703 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1704 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART4EN);\
Kojto 106:ba1f97679dad 1705 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1706 } while(0)
Kojto 106:ba1f97679dad 1707 #define __HAL_RCC_UART5_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1708 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1709 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 106:ba1f97679dad 1710 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1711 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_UART5EN);\
Kojto 106:ba1f97679dad 1712 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1713 } while(0)
Kojto 106:ba1f97679dad 1714 #define __HAL_RCC_FMPI2C1_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1715 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1716 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto 106:ba1f97679dad 1717 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1718 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_FMPI2C1EN);\
Kojto 106:ba1f97679dad 1719 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1720 } while(0)
Kojto 106:ba1f97679dad 1721 #define __HAL_RCC_CAN1_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1722 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1723 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 106:ba1f97679dad 1724 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1725 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN1EN);\
Kojto 106:ba1f97679dad 1726 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1727 } while(0)
Kojto 106:ba1f97679dad 1728 #define __HAL_RCC_CAN2_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1729 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1730 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 106:ba1f97679dad 1731 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1732 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CAN2EN);\
Kojto 106:ba1f97679dad 1733 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1734 } while(0)
Kojto 106:ba1f97679dad 1735 #define __HAL_RCC_CEC_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1736 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1737 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 106:ba1f97679dad 1738 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1739 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_CECEN);\
Kojto 106:ba1f97679dad 1740 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1741 } while(0)
Kojto 106:ba1f97679dad 1742 #define __HAL_RCC_DAC_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1743 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1744 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 106:ba1f97679dad 1745 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1746 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_DACEN);\
Kojto 106:ba1f97679dad 1747 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1748 } while(0)
Kojto 106:ba1f97679dad 1749
Kojto 106:ba1f97679dad 1750 #define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 106:ba1f97679dad 1751 #define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 106:ba1f97679dad 1752 #define __HAL_RCC_TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 106:ba1f97679dad 1753 #define __HAL_RCC_TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 106:ba1f97679dad 1754 #define __HAL_RCC_TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 106:ba1f97679dad 1755 #define __HAL_RCC_SPDIFRX_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPDIFRXEN))
Kojto 106:ba1f97679dad 1756 #define __HAL_RCC_USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 106:ba1f97679dad 1757 #define __HAL_RCC_UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 106:ba1f97679dad 1758 #define __HAL_RCC_UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 106:ba1f97679dad 1759 #define __HAL_RCC_FMPI2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_FMPI2C1EN))
Kojto 106:ba1f97679dad 1760 #define __HAL_RCC_CAN1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN1EN))
Kojto 106:ba1f97679dad 1761 #define __HAL_RCC_CAN2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CAN2EN))
Kojto 106:ba1f97679dad 1762 #define __HAL_RCC_CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto 106:ba1f97679dad 1763 #define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 106:ba1f97679dad 1764
Kojto 106:ba1f97679dad 1765 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 106:ba1f97679dad 1766 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 106:ba1f97679dad 1767 * is disabled and the application software has to enable this clock before
Kojto 106:ba1f97679dad 1768 * using it.
Kojto 106:ba1f97679dad 1769 */
Kojto 106:ba1f97679dad 1770 #define __HAL_RCC_TIM8_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1771 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1772 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 106:ba1f97679dad 1773 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1774 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM8EN);\
Kojto 106:ba1f97679dad 1775 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1776 } while(0)
Kojto 106:ba1f97679dad 1777 #define __HAL_RCC_ADC2_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1778 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1779 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 106:ba1f97679dad 1780 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1781 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC2EN);\
Kojto 106:ba1f97679dad 1782 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1783 } while(0)
Kojto 106:ba1f97679dad 1784 #define __HAL_RCC_ADC3_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1785 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1786 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 106:ba1f97679dad 1787 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1788 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC3EN);\
Kojto 106:ba1f97679dad 1789 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1790 } while(0)
Kojto 106:ba1f97679dad 1791 #define __HAL_RCC_SAI1_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1792 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1793 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto 106:ba1f97679dad 1794 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1795 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI1EN);\
Kojto 106:ba1f97679dad 1796 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1797 } while(0)
Kojto 106:ba1f97679dad 1798 #define __HAL_RCC_SAI2_CLK_ENABLE() do { \
Kojto 106:ba1f97679dad 1799 __IO uint32_t tmpreg; \
Kojto 106:ba1f97679dad 1800 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto 106:ba1f97679dad 1801 /* Delay after an RCC peripheral clock enabling */ \
Kojto 106:ba1f97679dad 1802 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SAI2EN);\
Kojto 106:ba1f97679dad 1803 UNUSED(tmpreg); \
Kojto 106:ba1f97679dad 1804 } while(0)
Kojto 106:ba1f97679dad 1805
Kojto 106:ba1f97679dad 1806 #define __HAL_RCC_TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 106:ba1f97679dad 1807 #define __HAL_RCC_ADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC2EN))
Kojto 106:ba1f97679dad 1808 #define __HAL_RCC_ADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC3EN))
Kojto 106:ba1f97679dad 1809 #define __HAL_RCC_SAI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI1EN))
Kojto 106:ba1f97679dad 1810 #define __HAL_RCC_SAI2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SAI2EN))
Kojto 106:ba1f97679dad 1811
Kojto 106:ba1f97679dad 1812 /** @brief Force or release AHB1 peripheral reset.
Kojto 106:ba1f97679dad 1813 */
Kojto 106:ba1f97679dad 1814 #define __HAL_RCC_GPIOF_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOFRST))
Kojto 106:ba1f97679dad 1815 #define __HAL_RCC_GPIOG_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOGRST))
Kojto 106:ba1f97679dad 1816 #define __HAL_RCC_USB_OTG_HS_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_OTGHRST))
Kojto 106:ba1f97679dad 1817
Kojto 106:ba1f97679dad 1818 #define __HAL_RCC_GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
Kojto 106:ba1f97679dad 1819 #define __HAL_RCC_GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
Kojto 106:ba1f97679dad 1820 #define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_OTGHRST))
Kojto 106:ba1f97679dad 1821
Kojto 106:ba1f97679dad 1822 /** @brief Force or release AHB2 peripheral reset.
Kojto 106:ba1f97679dad 1823 */
Kojto 106:ba1f97679dad 1824 #define __HAL_RCC_DCMI_FORCE_RESET() (RCC->AHB2RSTR |= (RCC_AHB2RSTR_DCMIRST))
Kojto 106:ba1f97679dad 1825 #define __HAL_RCC_DCMI_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_DCMIRST))
Kojto 106:ba1f97679dad 1826
Kojto 106:ba1f97679dad 1827 /** @brief Force or release AHB3 peripheral reset
Kojto 106:ba1f97679dad 1828 */
Kojto 106:ba1f97679dad 1829 #define __HAL_RCC_FMC_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_FMCRST))
Kojto 106:ba1f97679dad 1830 #define __HAL_RCC_QSPI_FORCE_RESET() (RCC->AHB3RSTR |= (RCC_AHB3RSTR_QSPIRST))
Kojto 106:ba1f97679dad 1831
Kojto 106:ba1f97679dad 1832 #define __HAL_RCC_FMC_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_FMCRST))
Kojto 106:ba1f97679dad 1833 #define __HAL_RCC_QSPI_RELEASE_RESET() (RCC->AHB3RSTR &= ~(RCC_AHB3RSTR_QSPIRST))
Kojto 106:ba1f97679dad 1834
Kojto 106:ba1f97679dad 1835 /** @brief Force or release APB1 peripheral reset.
Kojto 106:ba1f97679dad 1836 */
Kojto 106:ba1f97679dad 1837 #define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 106:ba1f97679dad 1838 #define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 106:ba1f97679dad 1839 #define __HAL_RCC_TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 106:ba1f97679dad 1840 #define __HAL_RCC_TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 106:ba1f97679dad 1841 #define __HAL_RCC_TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 106:ba1f97679dad 1842 #define __HAL_RCC_SPDIFRX_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPDIFRXRST))
Kojto 106:ba1f97679dad 1843 #define __HAL_RCC_USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 106:ba1f97679dad 1844 #define __HAL_RCC_UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 106:ba1f97679dad 1845 #define __HAL_RCC_UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 106:ba1f97679dad 1846 #define __HAL_RCC_FMPI2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_FMPI2C1RST))
Kojto 106:ba1f97679dad 1847 #define __HAL_RCC_CAN1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN1RST))
Kojto 106:ba1f97679dad 1848 #define __HAL_RCC_CAN2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CAN2RST))
Kojto 106:ba1f97679dad 1849 #define __HAL_RCC_CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
Kojto 106:ba1f97679dad 1850 #define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 106:ba1f97679dad 1851
Kojto 106:ba1f97679dad 1852 #define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 106:ba1f97679dad 1853 #define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 106:ba1f97679dad 1854 #define __HAL_RCC_TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 106:ba1f97679dad 1855 #define __HAL_RCC_TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 106:ba1f97679dad 1856 #define __HAL_RCC_TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 106:ba1f97679dad 1857 #define __HAL_RCC_SPDIFRX_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPDIFRXRST))
Kojto 106:ba1f97679dad 1858 #define __HAL_RCC_USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 106:ba1f97679dad 1859 #define __HAL_RCC_UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 106:ba1f97679dad 1860 #define __HAL_RCC_UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 106:ba1f97679dad 1861 #define __HAL_RCC_FMPI2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_FMPI2C1RST))
Kojto 106:ba1f97679dad 1862 #define __HAL_RCC_CAN1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN1RST))
Kojto 106:ba1f97679dad 1863 #define __HAL_RCC_CAN2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CAN2RST))
Kojto 106:ba1f97679dad 1864 #define __HAL_RCC_CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto 106:ba1f97679dad 1865 #define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 106:ba1f97679dad 1866
Kojto 106:ba1f97679dad 1867 /** @brief Force or release APB2 peripheral reset.
Kojto 106:ba1f97679dad 1868 */
Kojto 106:ba1f97679dad 1869 #define __HAL_RCC_TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 106:ba1f97679dad 1870 #define __HAL_RCC_SAI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI1RST))
Kojto 106:ba1f97679dad 1871 #define __HAL_RCC_SAI2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SAI2RST))
Kojto 106:ba1f97679dad 1872
Kojto 106:ba1f97679dad 1873 #define __HAL_RCC_TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 106:ba1f97679dad 1874 #define __HAL_RCC_SAI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI1RST))
Kojto 106:ba1f97679dad 1875 #define __HAL_RCC_SAI2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SAI2RST))
Kojto 106:ba1f97679dad 1876
Kojto 106:ba1f97679dad 1877 /** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1878 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1879 * power consumption.
Kojto 106:ba1f97679dad 1880 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1881 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1882 */
Kojto 106:ba1f97679dad 1883 #define __HAL_RCC_GPIOF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOFLPEN))
Kojto 106:ba1f97679dad 1884 #define __HAL_RCC_GPIOG_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_GPIOGLPEN))
Kojto 106:ba1f97679dad 1885 #define __HAL_RCC_SRAM2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_SRAM2LPEN))
Kojto 106:ba1f97679dad 1886 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSLPEN))
Kojto 106:ba1f97679dad 1887 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR |= (RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 106:ba1f97679dad 1888
Kojto 106:ba1f97679dad 1889 #define __HAL_RCC_GPIOF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOFLPEN))
Kojto 106:ba1f97679dad 1890 #define __HAL_RCC_GPIOG_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOGLPEN))
Kojto 106:ba1f97679dad 1891 #define __HAL_RCC_SRAM2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM2LPEN))
Kojto 106:ba1f97679dad 1892 #define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSLPEN))
Kojto 106:ba1f97679dad 1893 #define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_OTGHSULPILPEN))
Kojto 106:ba1f97679dad 1894 /** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1895 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1896 * power consumption.
Kojto 106:ba1f97679dad 1897 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1898 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1899 */
Kojto 106:ba1f97679dad 1900 #define __HAL_RCC_DCMI_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR |= (RCC_AHB2LPENR_DCMILPEN))
Kojto 106:ba1f97679dad 1901 #define __HAL_RCC_DCMI_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_DCMILPEN))
Kojto 106:ba1f97679dad 1902
Kojto 106:ba1f97679dad 1903 /** @brief Enable or disable the AHB3 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1904 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1905 * power consumption.
Kojto 106:ba1f97679dad 1906 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1907 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1908 */
Kojto 106:ba1f97679dad 1909 #define __HAL_RCC_FMC_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_FMCLPEN))
Kojto 106:ba1f97679dad 1910 #define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE() (RCC->AHB3LPENR |= (RCC_AHB3LPENR_QSPILPEN))
Kojto 106:ba1f97679dad 1911
Kojto 106:ba1f97679dad 1912 #define __HAL_RCC_FMC_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_FMCLPEN))
Kojto 106:ba1f97679dad 1913 #define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE() (RCC->AHB3LPENR &= ~(RCC_AHB3LPENR_QSPILPEN))
Kojto 106:ba1f97679dad 1914
Kojto 106:ba1f97679dad 1915 /** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1916 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1917 * power consumption.
Kojto 106:ba1f97679dad 1918 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1919 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1920 */
Kojto 106:ba1f97679dad 1921 #define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
Kojto 106:ba1f97679dad 1922 #define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
Kojto 106:ba1f97679dad 1923 #define __HAL_RCC_TIM12_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM12LPEN))
Kojto 106:ba1f97679dad 1924 #define __HAL_RCC_TIM13_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM13LPEN))
Kojto 106:ba1f97679dad 1925 #define __HAL_RCC_TIM14_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM14LPEN))
Kojto 106:ba1f97679dad 1926 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_SPDIFRXLPEN))
Kojto 106:ba1f97679dad 1927 #define __HAL_RCC_USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
Kojto 106:ba1f97679dad 1928 #define __HAL_RCC_UART4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
Kojto 106:ba1f97679dad 1929 #define __HAL_RCC_UART5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
Kojto 106:ba1f97679dad 1930 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_FMPI2C1LPEN))
Kojto 106:ba1f97679dad 1931 #define __HAL_RCC_CAN1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN1LPEN))
Kojto 106:ba1f97679dad 1932 #define __HAL_RCC_CAN2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CAN2LPEN))
Kojto 106:ba1f97679dad 1933 #define __HAL_RCC_CEC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_CECLPEN))
Kojto 106:ba1f97679dad 1934 #define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
Kojto 106:ba1f97679dad 1935
Kojto 106:ba1f97679dad 1936 #define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto 106:ba1f97679dad 1937 #define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto 106:ba1f97679dad 1938 #define __HAL_RCC_TIM12_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM12LPEN))
Kojto 106:ba1f97679dad 1939 #define __HAL_RCC_TIM13_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM13LPEN))
Kojto 106:ba1f97679dad 1940 #define __HAL_RCC_TIM14_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM14LPEN))
Kojto 106:ba1f97679dad 1941 #define __HAL_RCC_SPDIFRX_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPDIFRXLPEN))
Kojto 106:ba1f97679dad 1942 #define __HAL_RCC_USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto 106:ba1f97679dad 1943 #define __HAL_RCC_UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
Kojto 106:ba1f97679dad 1944 #define __HAL_RCC_UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
Kojto 106:ba1f97679dad 1945 #define __HAL_RCC_FMPI2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_FMPI2C1LPEN))
Kojto 106:ba1f97679dad 1946 #define __HAL_RCC_CAN1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN1LPEN))
Kojto 106:ba1f97679dad 1947 #define __HAL_RCC_CAN2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CAN2LPEN))
Kojto 106:ba1f97679dad 1948 #define __HAL_RCC_CEC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_CECLPEN))
Kojto 106:ba1f97679dad 1949 #define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto 106:ba1f97679dad 1950
Kojto 106:ba1f97679dad 1951 /** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto 106:ba1f97679dad 1952 * @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto 106:ba1f97679dad 1953 * power consumption.
Kojto 106:ba1f97679dad 1954 * @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto 106:ba1f97679dad 1955 * @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto 106:ba1f97679dad 1956 */
Kojto 106:ba1f97679dad 1957 #define __HAL_RCC_TIM8_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM8LPEN))
Kojto 106:ba1f97679dad 1958 #define __HAL_RCC_ADC2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC2LPEN))
Kojto 106:ba1f97679dad 1959 #define __HAL_RCC_ADC3_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC3LPEN))
Kojto 106:ba1f97679dad 1960 #define __HAL_RCC_SAI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI1LPEN))
Kojto 106:ba1f97679dad 1961 #define __HAL_RCC_SAI2_CLK_SLEEP_ENABLE() (RCC->APB2LPENR |= (RCC_APB2LPENR_SAI2LPEN))
Kojto 106:ba1f97679dad 1962
Kojto 106:ba1f97679dad 1963 #define __HAL_RCC_TIM8_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM8LPEN))
Kojto 106:ba1f97679dad 1964 #define __HAL_RCC_ADC2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC2LPEN))
Kojto 106:ba1f97679dad 1965 #define __HAL_RCC_ADC3_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC3LPEN))
Kojto 106:ba1f97679dad 1966 #define __HAL_RCC_SAI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI1LPEN))
Kojto 106:ba1f97679dad 1967 #define __HAL_RCC_SAI2_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SAI2LPEN))
Kojto 106:ba1f97679dad 1968
Kojto 106:ba1f97679dad 1969 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 1970 /*------------------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 1971
Kojto 106:ba1f97679dad 1972 /*------------------------------------------------- PLL Configuration ----------------------------------------*/
Kojto 106:ba1f97679dad 1973 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 1974 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto 106:ba1f97679dad 1975 * @note This function must be used only when the main PLL is disabled.
Kojto 106:ba1f97679dad 1976 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto 106:ba1f97679dad 1977 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 1978 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 106:ba1f97679dad 1979 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 106:ba1f97679dad 1980 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto 106:ba1f97679dad 1981 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 106:ba1f97679dad 1982 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 106:ba1f97679dad 1983 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 106:ba1f97679dad 1984 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 106:ba1f97679dad 1985 * of 2 MHz to limit PLL jitter.
Kojto 106:ba1f97679dad 1986 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto 106:ba1f97679dad 1987 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 1988 * @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto 106:ba1f97679dad 1989 * output frequency is between 192 and 432 MHz.
Kojto 106:ba1f97679dad 1990 *
Kojto 106:ba1f97679dad 1991 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto 106:ba1f97679dad 1992 * This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto 106:ba1f97679dad 1993 *
Kojto 106:ba1f97679dad 1994 * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto 106:ba1f97679dad 1995 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 1996 * @note If the USB OTG FS is used in your application, you have to set the
Kojto 106:ba1f97679dad 1997 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto 106:ba1f97679dad 1998 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto 106:ba1f97679dad 1999 * correctly.
Kojto 106:ba1f97679dad 2000 *
Kojto 106:ba1f97679dad 2001 * @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
Kojto 106:ba1f97679dad 2002 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 2003 * @note This parameter is only available in STM32F446xx devices.
Kojto 106:ba1f97679dad 2004 *
Kojto 106:ba1f97679dad 2005 */
Kojto 106:ba1f97679dad 2006 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
Kojto 106:ba1f97679dad 2007 (RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
Kojto 106:ba1f97679dad 2008 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
Kojto 106:ba1f97679dad 2009 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
Kojto 106:ba1f97679dad 2010 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
Kojto 106:ba1f97679dad 2011 ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
Kojto 106:ba1f97679dad 2012 #else
Kojto 106:ba1f97679dad 2013 /** @brief Macro to configure the main PLL clock source, multiplication and division factors.
Kojto 106:ba1f97679dad 2014 * @note This function must be used only when the main PLL is disabled.
Kojto 106:ba1f97679dad 2015 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto 106:ba1f97679dad 2016 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2017 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 106:ba1f97679dad 2018 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 106:ba1f97679dad 2019 * @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
Kojto 106:ba1f97679dad 2020 * @param __PLLM__: specifies the division factor for PLL VCO input clock
Kojto 106:ba1f97679dad 2021 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 106:ba1f97679dad 2022 * @note You have to set the PLLM parameter correctly to ensure that the VCO input
Kojto 106:ba1f97679dad 2023 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 106:ba1f97679dad 2024 * of 2 MHz to limit PLL jitter.
Kojto 106:ba1f97679dad 2025 * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
Kojto 106:ba1f97679dad 2026 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 2027 * @note You have to set the PLLN parameter correctly to ensure that the VCO
Kojto 106:ba1f97679dad 2028 * output frequency is between 192 and 432 MHz.
Kojto 106:ba1f97679dad 2029 *
Kojto 106:ba1f97679dad 2030 * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
Kojto 106:ba1f97679dad 2031 * This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto 106:ba1f97679dad 2032 *
Kojto 106:ba1f97679dad 2033 * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
Kojto 106:ba1f97679dad 2034 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 2035 * @note If the USB OTG FS is used in your application, you have to set the
Kojto 106:ba1f97679dad 2036 * PLLQ parameter correctly to have 48 MHz clock for the USB. However,
Kojto 106:ba1f97679dad 2037 * the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
Kojto 106:ba1f97679dad 2038 * correctly.
Kojto 106:ba1f97679dad 2039 *
Kojto 106:ba1f97679dad 2040 */
Kojto 106:ba1f97679dad 2041 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
Kojto 106:ba1f97679dad 2042 (RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
Kojto 106:ba1f97679dad 2043 ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
Kojto 106:ba1f97679dad 2044 ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
Kojto 106:ba1f97679dad 2045 ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
Kojto 106:ba1f97679dad 2046 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 2047 /*-------------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 2048
Kojto 106:ba1f97679dad 2049 /*------------------------------------------- PLLI2S Configuration --------------------------------------*/
Kojto 106:ba1f97679dad 2050 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 2051 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto 106:ba1f97679dad 2052 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 106:ba1f97679dad 2053 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 106:ba1f97679dad 2054 * HAL_RCC_ClockConfig() API).
Kojto 106:ba1f97679dad 2055 * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto 106:ba1f97679dad 2056 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 106:ba1f97679dad 2057 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto 106:ba1f97679dad 2058 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 106:ba1f97679dad 2059 * of 1 MHz to limit PLLI2S jitter.
Kojto 106:ba1f97679dad 2060 * @note The PLLI2SM parameter is only used with STM32F411xE and STM32F446xx Devices
Kojto 106:ba1f97679dad 2061 *
Kojto 106:ba1f97679dad 2062 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto 106:ba1f97679dad 2063 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 2064 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 106:ba1f97679dad 2065 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 106:ba1f97679dad 2066 *
Kojto 106:ba1f97679dad 2067 * @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
Kojto 106:ba1f97679dad 2068 * This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto 106:ba1f97679dad 2069 * @note the PLLI2SP parameter is only available with STM32F446xx Devices
Kojto 106:ba1f97679dad 2070 *
Kojto 106:ba1f97679dad 2071 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 106:ba1f97679dad 2072 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 2073 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 106:ba1f97679dad 2074 * on the I2S clock frequency.
Kojto 106:ba1f97679dad 2075 *
Kojto 106:ba1f97679dad 2076 * @param __PLLI2SQ__: specifies the division factor for SAI clock
Kojto 106:ba1f97679dad 2077 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 2078 * @note the PLLI2SQ parameter is only available with STM32F427/437/429x/439xx Devices
Kojto 106:ba1f97679dad 2079 *
Kojto 106:ba1f97679dad 2080 */
Kojto 106:ba1f97679dad 2081 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
Kojto 106:ba1f97679dad 2082 (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
Kojto 106:ba1f97679dad 2083 ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
Kojto 106:ba1f97679dad 2084 ((((__PLLI2SP__) >> 1) -1) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
Kojto 106:ba1f97679dad 2085 ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
Kojto 106:ba1f97679dad 2086 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto 106:ba1f97679dad 2087 #else
Kojto 106:ba1f97679dad 2088 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto 106:ba1f97679dad 2089 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 106:ba1f97679dad 2090 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 106:ba1f97679dad 2091 * HAL_RCC_ClockConfig() API).
Kojto 106:ba1f97679dad 2092 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto 106:ba1f97679dad 2093 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 2094 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 106:ba1f97679dad 2095 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 106:ba1f97679dad 2096 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 106:ba1f97679dad 2097 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 2098 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 106:ba1f97679dad 2099 * on the I2S clock frequency.
Kojto 106:ba1f97679dad 2100 *
Kojto 106:ba1f97679dad 2101 */
Kojto 106:ba1f97679dad 2102 #define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
Kojto 106:ba1f97679dad 2103 (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) | \
Kojto 106:ba1f97679dad 2104 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto 106:ba1f97679dad 2105 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 2106
Kojto 106:ba1f97679dad 2107 #if defined(STM32F411xE)
Kojto 106:ba1f97679dad 2108
Kojto 106:ba1f97679dad 2109 /** @brief Macro to configure the PLLI2S clock multiplication and division factors .
Kojto 106:ba1f97679dad 2110 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 106:ba1f97679dad 2111 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 106:ba1f97679dad 2112 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 106:ba1f97679dad 2113 * HAL_RCC_ClockConfig() API).
Kojto 106:ba1f97679dad 2114 * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
Kojto 106:ba1f97679dad 2115 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 106:ba1f97679dad 2116 * @note The PLLI2SM parameter is only used with STM32F411xE Devices
Kojto 106:ba1f97679dad 2117 * @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
Kojto 106:ba1f97679dad 2118 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 106:ba1f97679dad 2119 * of 2 MHz to limit PLLI2S jitter.
Kojto 106:ba1f97679dad 2120 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
Kojto 106:ba1f97679dad 2121 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 2122 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 106:ba1f97679dad 2123 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 106:ba1f97679dad 2124 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 106:ba1f97679dad 2125 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 2126 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 106:ba1f97679dad 2127 * on the I2S clock frequency.
Kojto 106:ba1f97679dad 2128 */
Kojto 106:ba1f97679dad 2129 #define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
Kojto 106:ba1f97679dad 2130 ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
Kojto 106:ba1f97679dad 2131 ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
Kojto 106:ba1f97679dad 2132 #endif /* STM32F411xE */
Kojto 106:ba1f97679dad 2133
Kojto 106:ba1f97679dad 2134 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 106:ba1f97679dad 2135 /** @brief Macro used by the SAI HAL driver to configure the PLLI2S clock multiplication and division factors.
Kojto 106:ba1f97679dad 2136 * @note This macro must be used only when the PLLI2S is disabled.
Kojto 106:ba1f97679dad 2137 * @note PLLI2S clock source is common with the main PLL (configured in
Kojto 106:ba1f97679dad 2138 * HAL_RCC_ClockConfig() API)
Kojto 106:ba1f97679dad 2139 * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
Kojto 106:ba1f97679dad 2140 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 2141 * @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
Kojto 106:ba1f97679dad 2142 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 106:ba1f97679dad 2143 * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
Kojto 106:ba1f97679dad 2144 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 2145 * @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx Devices
Kojto 106:ba1f97679dad 2146 * and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
Kojto 106:ba1f97679dad 2147 * @param __PLLI2SR__: specifies the division factor for I2S clock
Kojto 106:ba1f97679dad 2148 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 2149 * @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
Kojto 106:ba1f97679dad 2150 * on the I2S clock frequency.
Kojto 106:ba1f97679dad 2151 */
Kojto 106:ba1f97679dad 2152 #define __HAL_RCC_PLLI2S_SAICLK_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << 6) |\
Kojto 106:ba1f97679dad 2153 ((__PLLI2SQ__) << 24) |\
Kojto 106:ba1f97679dad 2154 ((__PLLI2SR__) << 28))
Kojto 106:ba1f97679dad 2155 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 2156 /*----------------------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 2157
Kojto 106:ba1f97679dad 2158 /*--------------------------------------------------- PLLSAI Configuration ---------------------------------------*/
Kojto 106:ba1f97679dad 2159 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 2160 /** @brief Macros to Enable or Disable the PLLISAI.
Kojto 106:ba1f97679dad 2161 * @note The PLLSAI is only available with STM32F429x/439x Devices.
Kojto 106:ba1f97679dad 2162 * @note The PLLSAI is disabled by hardware when entering STOP and STANDBY modes.
Kojto 106:ba1f97679dad 2163 */
Kojto 106:ba1f97679dad 2164 #define __HAL_RCC_PLLSAI_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = ENABLE)
Kojto 106:ba1f97679dad 2165 #define __HAL_RCC_PLLSAI_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLSAION_BB = DISABLE)
Kojto 106:ba1f97679dad 2166
Kojto 106:ba1f97679dad 2167 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 2168 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto 106:ba1f97679dad 2169 *
Kojto 106:ba1f97679dad 2170 * @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
Kojto 106:ba1f97679dad 2171 * This parameter must be a number between Min_Data = 2 and Max_Data = 63.
Kojto 106:ba1f97679dad 2172 * @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
Kojto 106:ba1f97679dad 2173 * frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
Kojto 106:ba1f97679dad 2174 * of 1 MHz to limit PLLI2S jitter.
Kojto 106:ba1f97679dad 2175 * @note The PLLSAIM parameter is only used with STM32F446xx Devices
Kojto 106:ba1f97679dad 2176 *
Kojto 106:ba1f97679dad 2177 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto 106:ba1f97679dad 2178 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 2179 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto 106:ba1f97679dad 2180 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 106:ba1f97679dad 2181 *
Kojto 106:ba1f97679dad 2182 * @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
Kojto 106:ba1f97679dad 2183 * This parameter must be a number in the range {2, 4, 6, or 8}.
Kojto 106:ba1f97679dad 2184 * @note the PLLSAIP parameter is only available with STM32F446xx Devices
Kojto 106:ba1f97679dad 2185 *
Kojto 106:ba1f97679dad 2186 * @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto 106:ba1f97679dad 2187 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 2188 *
Kojto 106:ba1f97679dad 2189 * @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto 106:ba1f97679dad 2190 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 2191 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto 106:ba1f97679dad 2192 */
Kojto 106:ba1f97679dad 2193 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
Kojto 106:ba1f97679dad 2194 (RCC->PLLSAICFGR = ((__PLLSAIM__) | \
Kojto 106:ba1f97679dad 2195 ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
Kojto 106:ba1f97679dad 2196 ((((__PLLSAIP__) >> 1) -1) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \
Kojto 106:ba1f97679dad 2197 ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
Kojto 106:ba1f97679dad 2198 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 2199
Kojto 106:ba1f97679dad 2200 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 106:ba1f97679dad 2201 /** @brief Macro to configure the PLLSAI clock multiplication and division factors.
Kojto 106:ba1f97679dad 2202 *
Kojto 106:ba1f97679dad 2203 * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
Kojto 106:ba1f97679dad 2204 * This parameter must be a number between Min_Data = 192 and Max_Data = 432.
Kojto 106:ba1f97679dad 2205 * @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
Kojto 106:ba1f97679dad 2206 * output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
Kojto 106:ba1f97679dad 2207 *
Kojto 106:ba1f97679dad 2208 * @param __PLLSAIQ__: specifies the division factor for SAI clock
Kojto 106:ba1f97679dad 2209 * This parameter must be a number between Min_Data = 2 and Max_Data = 15.
Kojto 106:ba1f97679dad 2210 *
Kojto 106:ba1f97679dad 2211 * @param __PLLSAIR__: specifies the division factor for LTDC clock
Kojto 106:ba1f97679dad 2212 * This parameter must be a number between Min_Data = 2 and Max_Data = 7.
Kojto 106:ba1f97679dad 2213 * @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
Kojto 106:ba1f97679dad 2214 */
Kojto 106:ba1f97679dad 2215 #define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
Kojto 106:ba1f97679dad 2216 (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
Kojto 106:ba1f97679dad 2217 ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) | \
Kojto 106:ba1f97679dad 2218 ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
Kojto 106:ba1f97679dad 2219 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 2220
Kojto 106:ba1f97679dad 2221 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
Kojto 106:ba1f97679dad 2222 /*----------------------------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 2223
Kojto 106:ba1f97679dad 2224 /*----------------------------------------- PLLSAI/PLLI2S Dividers Configuration ---------------------------------------*/
Kojto 106:ba1f97679dad 2225 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 2226 /** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
Kojto 106:ba1f97679dad 2227 * @note This function must be called before enabling the PLLI2S.
Kojto 106:ba1f97679dad 2228 * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
Kojto 106:ba1f97679dad 2229 * This parameter must be a number between 1 and 32.
Kojto 106:ba1f97679dad 2230 * SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
Kojto 106:ba1f97679dad 2231 */
Kojto 106:ba1f97679dad 2232 #define __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(__PLLI2SDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVQ, (__PLLI2SDivQ__)-1))
Kojto 106:ba1f97679dad 2233
Kojto 106:ba1f97679dad 2234 /** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
Kojto 106:ba1f97679dad 2235 * @note This function must be called before enabling the PLLSAI.
Kojto 106:ba1f97679dad 2236 * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
Kojto 106:ba1f97679dad 2237 * This parameter must be a number between Min_Data = 1 and Max_Data = 32.
Kojto 106:ba1f97679dad 2238 * SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
Kojto 106:ba1f97679dad 2239 */
Kojto 106:ba1f97679dad 2240 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(__PLLSAIDivQ__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVQ, ((__PLLSAIDivQ__)-1)<<8))
Kojto 106:ba1f97679dad 2241 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
Kojto 106:ba1f97679dad 2242
Kojto 106:ba1f97679dad 2243 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 106:ba1f97679dad 2244 /** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
Kojto 106:ba1f97679dad 2245 *
Kojto 106:ba1f97679dad 2246 * @note The LTDC peripheral is only available with STM32F427/437/429/439xx Devices.
Kojto 106:ba1f97679dad 2247 * @note This function must be called before enabling the PLLSAI.
Kojto 106:ba1f97679dad 2248 * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
Kojto 106:ba1f97679dad 2249 * This parameter must be a number between Min_Data = 2 and Max_Data = 16.
Kojto 106:ba1f97679dad 2250 * LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
Kojto 106:ba1f97679dad 2251 */
Kojto 106:ba1f97679dad 2252 #define __HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(__PLLSAIDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLSAIDIVR, (__PLLSAIDivR__)))
Kojto 106:ba1f97679dad 2253 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 2254 /*-----------------------------------------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 2255
Kojto 106:ba1f97679dad 2256 /*-------------------------------------------------- Peripheral Clock selection -----------------------------------------------------*/
Kojto 106:ba1f97679dad 2257 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
Kojto 106:ba1f97679dad 2258 defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 106:ba1f97679dad 2259 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
Kojto 106:ba1f97679dad 2260 /** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto 106:ba1f97679dad 2261 * @note This function must be called before enabling the I2S APB clock.
Kojto 106:ba1f97679dad 2262 * @param __SOURCE__: specifies the I2S clock source.
Kojto 106:ba1f97679dad 2263 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2264 * @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
Kojto 106:ba1f97679dad 2265 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto 106:ba1f97679dad 2266 * used as I2S clock source.
Kojto 106:ba1f97679dad 2267 */
Kojto 106:ba1f97679dad 2268 #define __HAL_RCC_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_CFGR_I2SSRC_BB = (__SOURCE__))
Kojto 106:ba1f97679dad 2269 #endif /* STM32F40xxx || STM32F41xxx || STM32F42xxx || STM32F43xxx */
Kojto 106:ba1f97679dad 2270
Kojto 106:ba1f97679dad 2271 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 106:ba1f97679dad 2272
Kojto 106:ba1f97679dad 2273 /** @brief Macro to configure SAI1BlockA clock source selection.
Kojto 106:ba1f97679dad 2274 * @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
Kojto 106:ba1f97679dad 2275 * @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto 106:ba1f97679dad 2276 * the SAI clock.
Kojto 106:ba1f97679dad 2277 * @param __SOURCE__: specifies the SAI Block A clock source.
Kojto 106:ba1f97679dad 2278 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2279 * @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 106:ba1f97679dad 2280 * as SAI1 Block A clock.
Kojto 106:ba1f97679dad 2281 * @arg RCC_SAIACLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 106:ba1f97679dad 2282 * as SAI1 Block A clock.
Kojto 106:ba1f97679dad 2283 * @arg RCC_SAIACLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto 106:ba1f97679dad 2284 * used as SAI1 Block A clock.
Kojto 106:ba1f97679dad 2285 */
Kojto 106:ba1f97679dad 2286 #define __HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1ASRC, (__SOURCE__)))
Kojto 106:ba1f97679dad 2287
Kojto 106:ba1f97679dad 2288 /** @brief Macro to configure SAI1BlockB clock source selection.
Kojto 106:ba1f97679dad 2289 * @note The SAI peripheral is only available with STM32F427/437/429/439xx Devices.
Kojto 106:ba1f97679dad 2290 * @note This function must be called before enabling PLLSAI, PLLI2S and
Kojto 106:ba1f97679dad 2291 * the SAI clock.
Kojto 106:ba1f97679dad 2292 * @param __SOURCE__: specifies the SAI Block B clock source.
Kojto 106:ba1f97679dad 2293 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2294 * @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
Kojto 106:ba1f97679dad 2295 * as SAI1 Block B clock.
Kojto 106:ba1f97679dad 2296 * @arg RCC_SAIBCLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used
Kojto 106:ba1f97679dad 2297 * as SAI1 Block B clock.
Kojto 106:ba1f97679dad 2298 * @arg RCC_SAIBCLKSOURCE_Ext: External clock mapped on the I2S_CKIN pin
Kojto 106:ba1f97679dad 2299 * used as SAI1 Block B clock.
Kojto 106:ba1f97679dad 2300 */
Kojto 106:ba1f97679dad 2301 #define __HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC, (__SOURCE__)))
Kojto 106:ba1f97679dad 2302 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 2303
Kojto 106:ba1f97679dad 2304 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 2305 /** @brief Macro to configure SAI1 clock source selection.
Kojto 106:ba1f97679dad 2306 * @note This configuration is only available with STM32F446xx Devices.
Kojto 106:ba1f97679dad 2307 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto 106:ba1f97679dad 2308 * the SAI clock.
Kojto 106:ba1f97679dad 2309 * @param __SOURCE__: specifies the SAI1 clock source.
Kojto 106:ba1f97679dad 2310 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2311 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto 106:ba1f97679dad 2312 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto 106:ba1f97679dad 2313 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto 106:ba1f97679dad 2314 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto 106:ba1f97679dad 2315 */
Kojto 106:ba1f97679dad 2316 #define __HAL_RCC_SAI1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC, (__SOURCE__)))
Kojto 106:ba1f97679dad 2317
Kojto 106:ba1f97679dad 2318 /** @brief Macro to Get SAI1 clock source selection.
Kojto 106:ba1f97679dad 2319 * @note This configuration is only available with STM32F446xx Devices.
Kojto 106:ba1f97679dad 2320 * @retval The clock source can be one of the following values:
Kojto 106:ba1f97679dad 2321 * @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
Kojto 106:ba1f97679dad 2322 * @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
Kojto 106:ba1f97679dad 2323 * @arg RCC_SAI1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto 106:ba1f97679dad 2324 * @arg RCC_SAI1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto 106:ba1f97679dad 2325 */
Kojto 106:ba1f97679dad 2326 #define __HAL_RCC_GET_SAI1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1SRC))
Kojto 106:ba1f97679dad 2327
Kojto 106:ba1f97679dad 2328 /** @brief Macro to configure SAI2 clock source selection.
Kojto 106:ba1f97679dad 2329 * @note This configuration is only available with STM32F446xx Devices.
Kojto 106:ba1f97679dad 2330 * @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
Kojto 106:ba1f97679dad 2331 * the SAI clock.
Kojto 106:ba1f97679dad 2332 * @param __SOURCE__: specifies the SAI2 clock source.
Kojto 106:ba1f97679dad 2333 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2334 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto 106:ba1f97679dad 2335 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto 106:ba1f97679dad 2336 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto 106:ba1f97679dad 2337 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto 106:ba1f97679dad 2338 */
Kojto 106:ba1f97679dad 2339 #define __HAL_RCC_SAI2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC, (__SOURCE__)))
Kojto 106:ba1f97679dad 2340
Kojto 106:ba1f97679dad 2341 /** @brief Macro to Get SAI2 clock source selection.
Kojto 106:ba1f97679dad 2342 * @note This configuration is only available with STM32F446xx Devices.
Kojto 106:ba1f97679dad 2343 * @retval The clock source can be one of the following values:
Kojto 106:ba1f97679dad 2344 * @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
Kojto 106:ba1f97679dad 2345 * @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
Kojto 106:ba1f97679dad 2346 * @arg RCC_SAI2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI2 clock.
Kojto 106:ba1f97679dad 2347 * @arg RCC_SAI2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL Source clock used as SAI2 clock.
Kojto 106:ba1f97679dad 2348 */
Kojto 106:ba1f97679dad 2349 #define __HAL_RCC_GET_SAI2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI2SRC))
Kojto 106:ba1f97679dad 2350
Kojto 106:ba1f97679dad 2351 /** @brief Macro to configure I2S APB1 clock source selection.
Kojto 106:ba1f97679dad 2352 * @note This configuration is only available with STM32F446xx Devices.
Kojto 106:ba1f97679dad 2353 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto 106:ba1f97679dad 2354 * @param __SOURCE__: specifies the I2S APB1 clock source.
Kojto 106:ba1f97679dad 2355 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2356 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto 106:ba1f97679dad 2357 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto 106:ba1f97679dad 2358 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto 106:ba1f97679dad 2359 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto 106:ba1f97679dad 2360 */
Kojto 106:ba1f97679dad 2361 #define __HAL_RCC_I2S_APB1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC, (__SOURCE__)))
Kojto 106:ba1f97679dad 2362
Kojto 106:ba1f97679dad 2363 /** @brief Macro to Get I2S APB1 clock source selection.
Kojto 106:ba1f97679dad 2364 * @note This configuration is only available with STM32F446xx Devices.
Kojto 106:ba1f97679dad 2365 * @retval The clock source can be one of the following values:
Kojto 106:ba1f97679dad 2366 * @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto 106:ba1f97679dad 2367 * @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto 106:ba1f97679dad 2368 * @arg RCC_I2SAPB1CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto 106:ba1f97679dad 2369 * @arg RCC_I2SAPB1CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto 106:ba1f97679dad 2370 */
Kojto 106:ba1f97679dad 2371 #define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
Kojto 106:ba1f97679dad 2372
Kojto 106:ba1f97679dad 2373 /** @brief Macro to configure I2S APB2 clock source selection.
Kojto 106:ba1f97679dad 2374 * @note This configuration is only available with STM32F446xx Devices.
Kojto 106:ba1f97679dad 2375 * @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
Kojto 106:ba1f97679dad 2376 * @param __SOURCE__: specifies the SAI Block A clock source.
Kojto 106:ba1f97679dad 2377 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2378 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto 106:ba1f97679dad 2379 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto 106:ba1f97679dad 2380 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto 106:ba1f97679dad 2381 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto 106:ba1f97679dad 2382 */
Kojto 106:ba1f97679dad 2383 #define __HAL_RCC_I2S_APB2_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC, (__SOURCE__)))
Kojto 106:ba1f97679dad 2384
Kojto 106:ba1f97679dad 2385 /** @brief Macro to Get I2S APB2 clock source selection.
Kojto 106:ba1f97679dad 2386 * @note This configuration is only available with STM32F446xx Devices.
Kojto 106:ba1f97679dad 2387 * @retval The clock source can be one of the following values:
Kojto 106:ba1f97679dad 2388 * @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
Kojto 106:ba1f97679dad 2389 * @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 clock.
Kojto 106:ba1f97679dad 2390 * @arg RCC_I2SAPB2CLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SAI1 clock.
Kojto 106:ba1f97679dad 2391 * @arg RCC_I2SAPB2CLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
Kojto 106:ba1f97679dad 2392 */
Kojto 106:ba1f97679dad 2393 #define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
Kojto 106:ba1f97679dad 2394
Kojto 106:ba1f97679dad 2395 /** @brief Macro to configure the CEC clock.
Kojto 106:ba1f97679dad 2396 * @param __SOURCE__: specifies the CEC clock source.
Kojto 106:ba1f97679dad 2397 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2398 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 106:ba1f97679dad 2399 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 106:ba1f97679dad 2400 */
Kojto 106:ba1f97679dad 2401 #define __HAL_RCC_CEC_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, (uint32_t)(__SOURCE__)))
Kojto 106:ba1f97679dad 2402
Kojto 106:ba1f97679dad 2403 /** @brief Macro to Get the CEC clock.
Kojto 106:ba1f97679dad 2404 * @retval The clock source can be one of the following values:
Kojto 106:ba1f97679dad 2405 * @arg RCC_CECCLKSOURCE_HSI488: HSI selected as CEC clock
Kojto 106:ba1f97679dad 2406 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 106:ba1f97679dad 2407 */
Kojto 106:ba1f97679dad 2408 #define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
Kojto 106:ba1f97679dad 2409
Kojto 106:ba1f97679dad 2410 /** @brief Macro to configure the FMPI2C1 clock.
Kojto 106:ba1f97679dad 2411 * @param __SOURCE__: specifies the FMPI2C1 clock source.
Kojto 106:ba1f97679dad 2412 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2413 * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
Kojto 106:ba1f97679dad 2414 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
Kojto 106:ba1f97679dad 2415 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
Kojto 106:ba1f97679dad 2416 */
Kojto 106:ba1f97679dad 2417 #define __HAL_RCC_FMPI2C1_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL, (uint32_t)(__SOURCE__)))
Kojto 106:ba1f97679dad 2418
Kojto 106:ba1f97679dad 2419 /** @brief Macro to Get the FMPI2C1 clock.
Kojto 106:ba1f97679dad 2420 * @retval The clock source can be one of the following values:
Kojto 106:ba1f97679dad 2421 * @arg RCC_FMPI2C1CLKSOURCE_APB: APB selected as CEC clock
Kojto 106:ba1f97679dad 2422 * @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as CEC clock
Kojto 106:ba1f97679dad 2423 * @arg RCC_FMPI2C1CLKSOURCE_HSI: HSI selected as CEC clock
Kojto 106:ba1f97679dad 2424 */
Kojto 106:ba1f97679dad 2425 #define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
Kojto 106:ba1f97679dad 2426
Kojto 106:ba1f97679dad 2427 /** @brief Macro to configure the CLK48 clock.
Kojto 106:ba1f97679dad 2428 * @param __SOURCE__: specifies the CK48 clock source.
Kojto 106:ba1f97679dad 2429 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2430 * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto 106:ba1f97679dad 2431 * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto 106:ba1f97679dad 2432 */
Kojto 106:ba1f97679dad 2433 #define __HAL_RCC_CLK48_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, (uint32_t)(__SOURCE__)))
Kojto 106:ba1f97679dad 2434
Kojto 106:ba1f97679dad 2435 /** @brief Macro to Get the CLK48 clock.
Kojto 106:ba1f97679dad 2436 * @retval The clock source can be one of the following values:
Kojto 106:ba1f97679dad 2437 * @arg RCC_CK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CK48 clock.
Kojto 106:ba1f97679dad 2438 * @arg RCC_CK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CK48 clock.
Kojto 106:ba1f97679dad 2439 */
Kojto 106:ba1f97679dad 2440 #define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
Kojto 106:ba1f97679dad 2441
Kojto 106:ba1f97679dad 2442 /** @brief Macro to configure the SDIO clock.
Kojto 106:ba1f97679dad 2443 * @param __SOURCE__: specifies the SDIO clock source.
Kojto 106:ba1f97679dad 2444 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2445 * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto 106:ba1f97679dad 2446 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto 106:ba1f97679dad 2447 */
Kojto 106:ba1f97679dad 2448 #define __HAL_RCC_SDIO_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL, (uint32_t)(__SOURCE__)))
Kojto 106:ba1f97679dad 2449
Kojto 106:ba1f97679dad 2450 /** @brief Macro to Get the SDIO clock.
Kojto 106:ba1f97679dad 2451 * @retval The clock source can be one of the following values:
Kojto 106:ba1f97679dad 2452 * @arg RCC_SDIOCLKSOURCE_CK48: CK48 output used as SDIO clock.
Kojto 106:ba1f97679dad 2453 * @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
Kojto 106:ba1f97679dad 2454 */
Kojto 106:ba1f97679dad 2455 #define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
Kojto 106:ba1f97679dad 2456
Kojto 106:ba1f97679dad 2457 /** @brief Macro to configure the SPDIFRX clock.
Kojto 106:ba1f97679dad 2458 * @param __SOURCE__: specifies the SPDIFRX clock source.
Kojto 106:ba1f97679dad 2459 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2460 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto 106:ba1f97679dad 2461 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto 106:ba1f97679dad 2462 */
Kojto 106:ba1f97679dad 2463 #define __HAL_RCC_SPDIFRX_CONFIG(__SOURCE__) (MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL, (uint32_t)(__SOURCE__)))
Kojto 106:ba1f97679dad 2464
Kojto 106:ba1f97679dad 2465 /** @brief Macro to Get the SPDIFRX clock.
Kojto 106:ba1f97679dad 2466 * @retval The clock source can be one of the following values:
Kojto 106:ba1f97679dad 2467 * @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
Kojto 106:ba1f97679dad 2468 * @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
Kojto 106:ba1f97679dad 2469 */
Kojto 106:ba1f97679dad 2470 #define __HAL_RCC_GET_SPDIFRX_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SPDIFRXSEL))
Kojto 106:ba1f97679dad 2471 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 2472
Kojto 106:ba1f97679dad 2473 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) ||\
Kojto 106:ba1f97679dad 2474 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 2475
Kojto 106:ba1f97679dad 2476 /** @brief Macro to configure the Timers clocks prescalers
Kojto 106:ba1f97679dad 2477 * @note This feature is only available with STM32F429x/439x Devices.
Kojto 106:ba1f97679dad 2478 * @param __PRESC__ : specifies the Timers clocks prescalers selection
Kojto 106:ba1f97679dad 2479 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2480 * @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
Kojto 106:ba1f97679dad 2481 * equal to HPRE if PPREx is corresponding to division by 1 or 2,
Kojto 106:ba1f97679dad 2482 * else it is equal to [(HPRE * PPREx) / 2] if PPREx is corresponding to
Kojto 106:ba1f97679dad 2483 * division by 4 or more.
Kojto 106:ba1f97679dad 2484 * @arg RCC_TIMPRES_ACTIVATED: The Timers kernels clocks prescaler is
Kojto 106:ba1f97679dad 2485 * equal to HPRE if PPREx is corresponding to division by 1, 2 or 4,
Kojto 106:ba1f97679dad 2486 * else it is equal to [(HPRE * PPREx) / 4] if PPREx is corresponding
Kojto 106:ba1f97679dad 2487 * to division by 8 or more.
Kojto 106:ba1f97679dad 2488 */
Kojto 106:ba1f97679dad 2489 #define __HAL_RCC_TIMCLKPRESCALER(__PRESC__) (*(__IO uint32_t *) RCC_DCKCFGR_TIMPRE_BB = (__PRESC__))
Kojto 106:ba1f97679dad 2490
Kojto 106:ba1f97679dad 2491 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx) || STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx */
Kojto 106:ba1f97679dad 2492
Kojto 106:ba1f97679dad 2493 /*-------------------------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 2494
Kojto 106:ba1f97679dad 2495 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 2496 /** @brief Enable PLLSAI_RDY interrupt.
Kojto 106:ba1f97679dad 2497 */
Kojto 106:ba1f97679dad 2498 #define __HAL_RCC_PLLSAI_ENABLE_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYIE))
Kojto 106:ba1f97679dad 2499
Kojto 106:ba1f97679dad 2500 /** @brief Disable PLLSAI_RDY interrupt.
Kojto 106:ba1f97679dad 2501 */
Kojto 106:ba1f97679dad 2502 #define __HAL_RCC_PLLSAI_DISABLE_IT() (RCC->CIR &= ~(RCC_CIR_PLLSAIRDYIE))
Kojto 106:ba1f97679dad 2503
Kojto 106:ba1f97679dad 2504 /** @brief Clear the PLLSAI RDY interrupt pending bits.
Kojto 106:ba1f97679dad 2505 */
Kojto 106:ba1f97679dad 2506 #define __HAL_RCC_PLLSAI_CLEAR_IT() (RCC->CIR |= (RCC_CIR_PLLSAIRDYF))
Kojto 106:ba1f97679dad 2507
Kojto 106:ba1f97679dad 2508 /** @brief Check the PLLSAI RDY interrupt has occurred or not.
Kojto 106:ba1f97679dad 2509 * @retval The new state (TRUE or FALSE).
Kojto 106:ba1f97679dad 2510 */
Kojto 106:ba1f97679dad 2511 #define __HAL_RCC_PLLSAI_GET_IT() ((RCC->CIR & (RCC_CIR_PLLSAIRDYIE)) == (RCC_CIR_PLLSAIRDYIE))
Kojto 106:ba1f97679dad 2512
Kojto 106:ba1f97679dad 2513 /** @brief Check PLLSAI RDY flag is set or not.
Kojto 106:ba1f97679dad 2514 * @retval The new state (TRUE or FALSE).
Kojto 106:ba1f97679dad 2515 */
Kojto 106:ba1f97679dad 2516 #define __HAL_RCC_PLLSAI_GET_FLAG() ((RCC->CR & (RCC_CR_PLLSAIRDY)) == (RCC_CR_PLLSAIRDY))
Kojto 106:ba1f97679dad 2517
Kojto 106:ba1f97679dad 2518 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
Kojto 106:ba1f97679dad 2519
Kojto 106:ba1f97679dad 2520 /**
Kojto 106:ba1f97679dad 2521 * @}
Kojto 106:ba1f97679dad 2522 */
Kojto 106:ba1f97679dad 2523
Kojto 106:ba1f97679dad 2524 /* Exported functions --------------------------------------------------------*/
Kojto 106:ba1f97679dad 2525 /** @addtogroup RCCEx_Exported_Functions
Kojto 106:ba1f97679dad 2526 * @{
Kojto 106:ba1f97679dad 2527 */
Kojto 106:ba1f97679dad 2528
Kojto 106:ba1f97679dad 2529 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 106:ba1f97679dad 2530 * @{
Kojto 106:ba1f97679dad 2531 */
Kojto 106:ba1f97679dad 2532 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 106:ba1f97679dad 2533 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 106:ba1f97679dad 2534
Kojto 106:ba1f97679dad 2535 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 2536 uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
Kojto 106:ba1f97679dad 2537 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 2538
Kojto 106:ba1f97679dad 2539 #if defined(STM32F411xE) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 2540 void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
Kojto 106:ba1f97679dad 2541 #endif /* STM32F411xE || STM32F446xx */
Kojto 106:ba1f97679dad 2542 /**
Kojto 106:ba1f97679dad 2543 * @}
Kojto 106:ba1f97679dad 2544 */
Kojto 106:ba1f97679dad 2545
Kojto 106:ba1f97679dad 2546 /**
Kojto 106:ba1f97679dad 2547 * @}
Kojto 106:ba1f97679dad 2548 */
Kojto 106:ba1f97679dad 2549 /* Private types -------------------------------------------------------------*/
Kojto 106:ba1f97679dad 2550 /* Private variables ---------------------------------------------------------*/
Kojto 106:ba1f97679dad 2551 /* Private constants ---------------------------------------------------------*/
Kojto 106:ba1f97679dad 2552 /** @defgroup RCCEx_Private_Constants RCCEx Private Constants
Kojto 106:ba1f97679dad 2553 * @{
Kojto 106:ba1f97679dad 2554 */
Kojto 106:ba1f97679dad 2555
Kojto 106:ba1f97679dad 2556 /** @defgroup RCCEx_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto 106:ba1f97679dad 2557 * @brief RCC registers bit address in the alias region
Kojto 106:ba1f97679dad 2558 * @{
Kojto 106:ba1f97679dad 2559 */
Kojto 106:ba1f97679dad 2560 /* --- CR Register ---*/
Kojto 106:ba1f97679dad 2561 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 2562 /* Alias word address of PLLSAION bit */
Kojto 106:ba1f97679dad 2563 #define RCC_PLLSAION_BIT_NUMBER 0x1C
Kojto 106:ba1f97679dad 2564 #define RCC_CR_PLLSAION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (RCC_PLLSAION_BIT_NUMBER * 4))
Kojto 106:ba1f97679dad 2565
Kojto 106:ba1f97679dad 2566 /* --- DCKCFGR Register ---*/
Kojto 106:ba1f97679dad 2567 /* Alias word address of TIMPRE bit */
Kojto 106:ba1f97679dad 2568 #define RCC_DCKCFGR_OFFSET (RCC_OFFSET + 0x8C)
Kojto 106:ba1f97679dad 2569 #define RCC_TIMPRE_BIT_NUMBER 0x18
Kojto 106:ba1f97679dad 2570 #define RCC_DCKCFGR_TIMPRE_BB (PERIPH_BB_BASE + (RCC_DCKCFGR_OFFSET * 32) + (RCC_TIMPRE_BIT_NUMBER * 4))
Kojto 106:ba1f97679dad 2571 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx */
Kojto 106:ba1f97679dad 2572
Kojto 106:ba1f97679dad 2573 #define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto 106:ba1f97679dad 2574
Kojto 106:ba1f97679dad 2575 /**
Kojto 106:ba1f97679dad 2576 * @}
Kojto 106:ba1f97679dad 2577 */
Kojto 106:ba1f97679dad 2578
Kojto 106:ba1f97679dad 2579 /**
Kojto 106:ba1f97679dad 2580 * @}
Kojto 106:ba1f97679dad 2581 */
Kojto 106:ba1f97679dad 2582
Kojto 106:ba1f97679dad 2583 /* Private macros ------------------------------------------------------------*/
Kojto 106:ba1f97679dad 2584 /** @addtogroup RCCEx_Private_Macros RCCEx Private Macros
Kojto 106:ba1f97679dad 2585 * @{
Kojto 106:ba1f97679dad 2586 */
Kojto 106:ba1f97679dad 2587 /** @defgroup RCCEx_IS_RCC_Definitions RCC Private macros to check input parameters
Kojto 106:ba1f97679dad 2588 * @{
Kojto 106:ba1f97679dad 2589 */
Kojto 106:ba1f97679dad 2590
Kojto 106:ba1f97679dad 2591 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
Kojto 106:ba1f97679dad 2592 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x0000002F))
Kojto 106:ba1f97679dad 2593 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 2594
Kojto 106:ba1f97679dad 2595 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx) ||\
Kojto 106:ba1f97679dad 2596 defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
Kojto 106:ba1f97679dad 2597 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x00000003))
Kojto 106:ba1f97679dad 2598 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
Kojto 106:ba1f97679dad 2599
Kojto 106:ba1f97679dad 2600 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 2601 #define IS_RCC_PERIPHCLOCK(SELECTION) ((1 <= (SELECTION)) && ((SELECTION) <= 0x000007FF))
Kojto 106:ba1f97679dad 2602 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 2603
Kojto 106:ba1f97679dad 2604 #define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
Kojto 106:ba1f97679dad 2605 #define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 106:ba1f97679dad 2606
Kojto 106:ba1f97679dad 2607
Kojto 106:ba1f97679dad 2608 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx) || defined(STM32F446xx)
Kojto 106:ba1f97679dad 2609 #define IS_RCC_PLLI2SQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto 106:ba1f97679dad 2610
Kojto 106:ba1f97679dad 2611 #define IS_RCC_PLLSAIN_VALUE(VALUE) ((49 <= (VALUE)) && ((VALUE) <= 432))
Kojto 106:ba1f97679dad 2612
Kojto 106:ba1f97679dad 2613 #define IS_RCC_PLLSAIQ_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 15))
Kojto 106:ba1f97679dad 2614
Kojto 106:ba1f97679dad 2615 #define IS_RCC_PLLSAIR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 106:ba1f97679dad 2616
Kojto 106:ba1f97679dad 2617 #define IS_RCC_PLLSAI_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto 106:ba1f97679dad 2618
Kojto 106:ba1f97679dad 2619 #define IS_RCC_PLLI2S_DIVQ_VALUE(VALUE) ((1 <= (VALUE)) && ((VALUE) <= 32))
Kojto 106:ba1f97679dad 2620
Kojto 106:ba1f97679dad 2621 #define IS_RCC_PLLSAI_DIVR_VALUE(VALUE) (((VALUE) == RCC_PLLSAIDIVR_2) ||\
Kojto 106:ba1f97679dad 2622 ((VALUE) == RCC_PLLSAIDIVR_4) ||\
Kojto 106:ba1f97679dad 2623 ((VALUE) == RCC_PLLSAIDIVR_8) ||\
Kojto 106:ba1f97679dad 2624 ((VALUE) == RCC_PLLSAIDIVR_16))
Kojto 106:ba1f97679dad 2625 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
Kojto 106:ba1f97679dad 2626
Kojto 106:ba1f97679dad 2627 #if defined(STM32F446xx) || defined(STM32F411xE)
Kojto 106:ba1f97679dad 2628 #define IS_RCC_PLLI2SM_VALUE(VALUE) ((VALUE) <= 63)
Kojto 106:ba1f97679dad 2629
Kojto 106:ba1f97679dad 2630 #define IS_RCC_LSE_MODE(MODE) (((MODE) == RCC_LSE_LOWPOWER_MODE) ||\
Kojto 106:ba1f97679dad 2631 ((MODE) == RCC_LSE_HIGHDRIVE_MODE))
Kojto 106:ba1f97679dad 2632 #endif /* STM32F446xx || STM32F411xE */
Kojto 106:ba1f97679dad 2633
Kojto 106:ba1f97679dad 2634 #if defined(STM32F446xx)
Kojto 106:ba1f97679dad 2635 #define IS_RCC_PLLR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
Kojto 106:ba1f97679dad 2636
Kojto 106:ba1f97679dad 2637 #define IS_RCC_PLLI2SP_VALUE(VALUE) (((VALUE) == RCC_PLLI2SP_DIV2) ||\
Kojto 106:ba1f97679dad 2638 ((VALUE) == RCC_PLLI2SP_DIV4) ||\
Kojto 106:ba1f97679dad 2639 ((VALUE) == RCC_PLLI2SP_DIV6) ||\
Kojto 106:ba1f97679dad 2640 ((VALUE) == RCC_PLLI2SP_DIV8))
Kojto 106:ba1f97679dad 2641
Kojto 106:ba1f97679dad 2642 #define IS_RCC_PLLSAIM_VALUE(VALUE) ((VALUE) <= 63)
Kojto 106:ba1f97679dad 2643
Kojto 106:ba1f97679dad 2644 #define IS_RCC_PLLSAIP_VALUE(VALUE) (((VALUE) == RCC_PLLSAIP_DIV2) ||\
Kojto 106:ba1f97679dad 2645 ((VALUE) == RCC_PLLSAIP_DIV4) ||\
Kojto 106:ba1f97679dad 2646 ((VALUE) == RCC_PLLSAIP_DIV6) ||\
Kojto 106:ba1f97679dad 2647 ((VALUE) == RCC_PLLSAIP_DIV8))
Kojto 106:ba1f97679dad 2648
Kojto 106:ba1f97679dad 2649 #define IS_RCC_SAI1CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI1CLKSOURCE_PLLSAI) ||\
Kojto 106:ba1f97679dad 2650 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLI2S) ||\
Kojto 106:ba1f97679dad 2651 ((SOURCE) == RCC_SAI1CLKSOURCE_PLLR) ||\
Kojto 106:ba1f97679dad 2652 ((SOURCE) == RCC_SAI1CLKSOURCE_EXT))
Kojto 106:ba1f97679dad 2653
Kojto 106:ba1f97679dad 2654 #define IS_RCC_SAI2CLKSOURCE(SOURCE) (((SOURCE) == RCC_SAI2CLKSOURCE_PLLSAI) ||\
Kojto 106:ba1f97679dad 2655 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLI2S) ||\
Kojto 106:ba1f97679dad 2656 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLR) ||\
Kojto 106:ba1f97679dad 2657 ((SOURCE) == RCC_SAI2CLKSOURCE_PLLSRC))
Kojto 106:ba1f97679dad 2658
Kojto 106:ba1f97679dad 2659 #define IS_RCC_I2SAPB1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLI2S) ||\
Kojto 106:ba1f97679dad 2660 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_EXT) ||\
Kojto 106:ba1f97679dad 2661 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLR) ||\
Kojto 106:ba1f97679dad 2662 ((SOURCE) == RCC_I2SAPB1CLKSOURCE_PLLSRC))
Kojto 106:ba1f97679dad 2663
Kojto 106:ba1f97679dad 2664 #define IS_RCC_I2SAPB2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLI2S) ||\
Kojto 106:ba1f97679dad 2665 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_EXT) ||\
Kojto 106:ba1f97679dad 2666 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLR) ||\
Kojto 106:ba1f97679dad 2667 ((SOURCE) == RCC_I2SAPB2CLKSOURCE_PLLSRC))
Kojto 106:ba1f97679dad 2668
Kojto 106:ba1f97679dad 2669 #define IS_RCC_FMPI2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_FMPI2C1CLKSOURCE_APB) ||\
Kojto 106:ba1f97679dad 2670 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_SYSCLK) ||\
Kojto 106:ba1f97679dad 2671 ((SOURCE) == RCC_FMPI2C1CLKSOURCE_HSI))
Kojto 106:ba1f97679dad 2672
Kojto 106:ba1f97679dad 2673 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) ||\
Kojto 106:ba1f97679dad 2674 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto 106:ba1f97679dad 2675
Kojto 106:ba1f97679dad 2676 #define IS_RCC_CK48CLKSOURCE(SOURCE) (((SOURCE) == RCC_CK48CLKSOURCE_PLLQ) ||\
Kojto 106:ba1f97679dad 2677 ((SOURCE) == RCC_CK48CLKSOURCE_PLLSAIP))
Kojto 106:ba1f97679dad 2678
Kojto 106:ba1f97679dad 2679 #define IS_RCC_SDIOCLKSOURCE(SOURCE) (((SOURCE) == RCC_SDIOCLKSOURCE_CK48) ||\
Kojto 106:ba1f97679dad 2680 ((SOURCE) == RCC_SDIOCLKSOURCE_SYSCLK))
Kojto 106:ba1f97679dad 2681
Kojto 106:ba1f97679dad 2682 #define IS_RCC_SPDIFRXCLKSOURCE(SOURCE) (((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLR) ||\
Kojto 106:ba1f97679dad 2683 ((SOURCE) == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
Kojto 106:ba1f97679dad 2684 #endif /* STM32F446xx */
Kojto 106:ba1f97679dad 2685
Kojto 106:ba1f97679dad 2686 /**
Kojto 106:ba1f97679dad 2687 * @}
Kojto 106:ba1f97679dad 2688 */
Kojto 106:ba1f97679dad 2689
Kojto 106:ba1f97679dad 2690 /**
Kojto 106:ba1f97679dad 2691 * @}
Kojto 106:ba1f97679dad 2692 */
Kojto 106:ba1f97679dad 2693
Kojto 106:ba1f97679dad 2694 /**
Kojto 106:ba1f97679dad 2695 * @}
Kojto 106:ba1f97679dad 2696 */
Kojto 106:ba1f97679dad 2697
Kojto 106:ba1f97679dad 2698 /**
Kojto 106:ba1f97679dad 2699 * @}
Kojto 106:ba1f97679dad 2700 */
Kojto 106:ba1f97679dad 2701 #ifdef __cplusplus
Kojto 106:ba1f97679dad 2702 }
Kojto 106:ba1f97679dad 2703 #endif
Kojto 106:ba1f97679dad 2704
Kojto 106:ba1f97679dad 2705 #endif /* __STM32F4xx_HAL_RCC_EX_H */
Kojto 106:ba1f97679dad 2706
Kojto 106:ba1f97679dad 2707 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/