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TARGET_MTS_MDOT_F405RG/stm32f4xx_ll_sdmmc.h@106:ba1f97679dad, 2015-09-02 (annotated)

Committer:
Kojto
Date:
Wed Sep 02 14:17:43 2015 +0100
Revision:
106:ba1f97679dad
Parent:
99:dbbf35b96557
Child:
110:165afa46840b
Release 106  of the mbed library



Changes:

- new platform - Nucleo F446RE

- STM32F4 Cube driver update v2.3.2

- ST cmsis driver v2.3.2

- nordic bugfix gcc linker start address

- lpc11u68 - bugfix for serial ports

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_ll_sdmmc.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
Kojto 106:ba1f97679dad 5 * @version V1.3.2
Kojto 106:ba1f97679dad 6 * @date 26-June-2015
bogdanm 92:4fc01daae5a5 7 * @brief Header file of SDMMC HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_LL_SDMMC_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_LL_SDMMC_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
Kojto 99:dbbf35b96557 53 /** @addtogroup SDMMC_LL
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
bogdanm 92:4fc01daae5a5 59 * @{
bogdanm 92:4fc01daae5a5 60 */
bogdanm 92:4fc01daae5a5 61
bogdanm 92:4fc01daae5a5 62 /**
bogdanm 92:4fc01daae5a5 63 * @brief SDMMC Configuration Structure definition
bogdanm 92:4fc01daae5a5 64 */
bogdanm 92:4fc01daae5a5 65 typedef struct
bogdanm 92:4fc01daae5a5 66 {
bogdanm 92:4fc01daae5a5 67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
bogdanm 92:4fc01daae5a5 68 This parameter can be a value of @ref SDIO_Clock_Edge */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 uint32_t ClockBypass; /*!< Specifies whether the SDIO Clock divider bypass is
bogdanm 92:4fc01daae5a5 71 enabled or disabled.
bogdanm 92:4fc01daae5a5 72 This parameter can be a value of @ref SDIO_Clock_Bypass */
bogdanm 92:4fc01daae5a5 73
bogdanm 92:4fc01daae5a5 74 uint32_t ClockPowerSave; /*!< Specifies whether SDIO Clock output is enabled or
bogdanm 92:4fc01daae5a5 75 disabled when the bus is idle.
bogdanm 92:4fc01daae5a5 76 This parameter can be a value of @ref SDIO_Clock_Power_Save */
bogdanm 92:4fc01daae5a5 77
bogdanm 92:4fc01daae5a5 78 uint32_t BusWide; /*!< Specifies the SDIO bus width.
bogdanm 92:4fc01daae5a5 79 This parameter can be a value of @ref SDIO_Bus_Wide */
bogdanm 92:4fc01daae5a5 80
bogdanm 92:4fc01daae5a5 81 uint32_t HardwareFlowControl; /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
bogdanm 92:4fc01daae5a5 82 This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
bogdanm 92:4fc01daae5a5 83
bogdanm 92:4fc01daae5a5 84 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDIO controller.
bogdanm 92:4fc01daae5a5 85 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm 92:4fc01daae5a5 86
bogdanm 92:4fc01daae5a5 87 }SDIO_InitTypeDef;
bogdanm 92:4fc01daae5a5 88
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 /**
bogdanm 92:4fc01daae5a5 91 * @brief SDIO Command Control structure
bogdanm 92:4fc01daae5a5 92 */
bogdanm 92:4fc01daae5a5 93 typedef struct
bogdanm 92:4fc01daae5a5 94 {
bogdanm 92:4fc01daae5a5 95 uint32_t Argument; /*!< Specifies the SDIO command argument which is sent
bogdanm 92:4fc01daae5a5 96 to a card as part of a command message. If a command
bogdanm 92:4fc01daae5a5 97 contains an argument, it must be loaded into this register
bogdanm 92:4fc01daae5a5 98 before writing the command to the command register. */
bogdanm 92:4fc01daae5a5 99
bogdanm 92:4fc01daae5a5 100 uint32_t CmdIndex; /*!< Specifies the SDIO command index. It must be Min_Data = 0 and
bogdanm 92:4fc01daae5a5 101 Max_Data = 64 */
bogdanm 92:4fc01daae5a5 102
bogdanm 92:4fc01daae5a5 103 uint32_t Response; /*!< Specifies the SDIO response type.
bogdanm 92:4fc01daae5a5 104 This parameter can be a value of @ref SDIO_Response_Type */
bogdanm 92:4fc01daae5a5 105
bogdanm 92:4fc01daae5a5 106 uint32_t WaitForInterrupt; /*!< Specifies whether SDIO wait for interrupt request is
bogdanm 92:4fc01daae5a5 107 enabled or disabled.
bogdanm 92:4fc01daae5a5 108 This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
bogdanm 92:4fc01daae5a5 109
bogdanm 92:4fc01daae5a5 110 uint32_t CPSM; /*!< Specifies whether SDIO Command path state machine (CPSM)
bogdanm 92:4fc01daae5a5 111 is enabled or disabled.
bogdanm 92:4fc01daae5a5 112 This parameter can be a value of @ref SDIO_CPSM_State */
bogdanm 92:4fc01daae5a5 113 }SDIO_CmdInitTypeDef;
bogdanm 92:4fc01daae5a5 114
bogdanm 92:4fc01daae5a5 115
bogdanm 92:4fc01daae5a5 116 /**
bogdanm 92:4fc01daae5a5 117 * @brief SDIO Data Control structure
bogdanm 92:4fc01daae5a5 118 */
bogdanm 92:4fc01daae5a5 119 typedef struct
bogdanm 92:4fc01daae5a5 120 {
bogdanm 92:4fc01daae5a5 121 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
bogdanm 92:4fc01daae5a5 122
bogdanm 92:4fc01daae5a5 123 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
bogdanm 92:4fc01daae5a5 124
bogdanm 92:4fc01daae5a5 125 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
bogdanm 92:4fc01daae5a5 126 This parameter can be a value of @ref SDIO_Data_Block_Size */
bogdanm 92:4fc01daae5a5 127
bogdanm 92:4fc01daae5a5 128 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
bogdanm 92:4fc01daae5a5 129 is a read or write.
bogdanm 92:4fc01daae5a5 130 This parameter can be a value of @ref SDIO_Transfer_Direction */
bogdanm 92:4fc01daae5a5 131
bogdanm 92:4fc01daae5a5 132 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
bogdanm 92:4fc01daae5a5 133 This parameter can be a value of @ref SDIO_Transfer_Type */
bogdanm 92:4fc01daae5a5 134
bogdanm 92:4fc01daae5a5 135 uint32_t DPSM; /*!< Specifies whether SDIO Data path state machine (DPSM)
bogdanm 92:4fc01daae5a5 136 is enabled or disabled.
bogdanm 92:4fc01daae5a5 137 This parameter can be a value of @ref SDIO_DPSM_State */
bogdanm 92:4fc01daae5a5 138 }SDIO_DataInitTypeDef;
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140 /**
bogdanm 92:4fc01daae5a5 141 * @}
bogdanm 92:4fc01daae5a5 142 */
bogdanm 92:4fc01daae5a5 143
bogdanm 92:4fc01daae5a5 144 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
bogdanm 92:4fc01daae5a5 146 * @{
bogdanm 92:4fc01daae5a5 147 */
bogdanm 92:4fc01daae5a5 148
Kojto 99:dbbf35b96557 149 /** @defgroup SDIO_Clock_Edge Clock Edge
bogdanm 92:4fc01daae5a5 150 * @{
bogdanm 92:4fc01daae5a5 151 */
bogdanm 92:4fc01daae5a5 152 #define SDIO_CLOCK_EDGE_RISING ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 153 #define SDIO_CLOCK_EDGE_FALLING SDIO_CLKCR_NEGEDGE
bogdanm 92:4fc01daae5a5 154
bogdanm 92:4fc01daae5a5 155 #define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
bogdanm 92:4fc01daae5a5 156 ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
bogdanm 92:4fc01daae5a5 157 /**
bogdanm 92:4fc01daae5a5 158 * @}
bogdanm 92:4fc01daae5a5 159 */
bogdanm 92:4fc01daae5a5 160
Kojto 99:dbbf35b96557 161 /** @defgroup SDIO_Clock_Bypass Clock Bypass
bogdanm 92:4fc01daae5a5 162 * @{
bogdanm 92:4fc01daae5a5 163 */
bogdanm 92:4fc01daae5a5 164 #define SDIO_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 165 #define SDIO_CLOCK_BYPASS_ENABLE SDIO_CLKCR_BYPASS
bogdanm 92:4fc01daae5a5 166
bogdanm 92:4fc01daae5a5 167 #define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
bogdanm 92:4fc01daae5a5 168 ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
bogdanm 92:4fc01daae5a5 169 /**
bogdanm 92:4fc01daae5a5 170 * @}
bogdanm 92:4fc01daae5a5 171 */
bogdanm 92:4fc01daae5a5 172
Kojto 99:dbbf35b96557 173 /** @defgroup SDIO_Clock_Power_Save Clock Power Saving
bogdanm 92:4fc01daae5a5 174 * @{
bogdanm 92:4fc01daae5a5 175 */
bogdanm 92:4fc01daae5a5 176 #define SDIO_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 177 #define SDIO_CLOCK_POWER_SAVE_ENABLE SDIO_CLKCR_PWRSAV
bogdanm 92:4fc01daae5a5 178
bogdanm 92:4fc01daae5a5 179 #define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
bogdanm 92:4fc01daae5a5 180 ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
bogdanm 92:4fc01daae5a5 181 /**
bogdanm 92:4fc01daae5a5 182 * @}
bogdanm 92:4fc01daae5a5 183 */
bogdanm 92:4fc01daae5a5 184
Kojto 99:dbbf35b96557 185 /** @defgroup SDIO_Bus_Wide Bus Width
bogdanm 92:4fc01daae5a5 186 * @{
bogdanm 92:4fc01daae5a5 187 */
bogdanm 92:4fc01daae5a5 188 #define SDIO_BUS_WIDE_1B ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 189 #define SDIO_BUS_WIDE_4B SDIO_CLKCR_WIDBUS_0
bogdanm 92:4fc01daae5a5 190 #define SDIO_BUS_WIDE_8B SDIO_CLKCR_WIDBUS_1
bogdanm 92:4fc01daae5a5 191
bogdanm 92:4fc01daae5a5 192 #define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
bogdanm 92:4fc01daae5a5 193 ((WIDE) == SDIO_BUS_WIDE_4B) || \
bogdanm 92:4fc01daae5a5 194 ((WIDE) == SDIO_BUS_WIDE_8B))
bogdanm 92:4fc01daae5a5 195 /**
bogdanm 92:4fc01daae5a5 196 * @}
bogdanm 92:4fc01daae5a5 197 */
bogdanm 92:4fc01daae5a5 198
Kojto 99:dbbf35b96557 199 /** @defgroup SDIO_Hardware_Flow_Control Hardware Flow Control
bogdanm 92:4fc01daae5a5 200 * @{
bogdanm 92:4fc01daae5a5 201 */
bogdanm 92:4fc01daae5a5 202 #define SDIO_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 203 #define SDIO_HARDWARE_FLOW_CONTROL_ENABLE SDIO_CLKCR_HWFC_EN
bogdanm 92:4fc01daae5a5 204
bogdanm 92:4fc01daae5a5 205 #define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
bogdanm 92:4fc01daae5a5 206 ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
bogdanm 92:4fc01daae5a5 207 /**
bogdanm 92:4fc01daae5a5 208 * @}
bogdanm 92:4fc01daae5a5 209 */
bogdanm 92:4fc01daae5a5 210
Kojto 99:dbbf35b96557 211 /** @defgroup SDIO_Clock_Division Clock Division
bogdanm 92:4fc01daae5a5 212 * @{
bogdanm 92:4fc01daae5a5 213 */
bogdanm 92:4fc01daae5a5 214 #define IS_SDIO_CLKDIV(DIV) ((DIV) <= 0xFF)
bogdanm 92:4fc01daae5a5 215 /**
bogdanm 92:4fc01daae5a5 216 * @}
bogdanm 92:4fc01daae5a5 217 */
bogdanm 92:4fc01daae5a5 218
Kojto 99:dbbf35b96557 219 /** @defgroup SDIO_Command_Index Command Index
bogdanm 92:4fc01daae5a5 220 * @{
bogdanm 92:4fc01daae5a5 221 */
bogdanm 92:4fc01daae5a5 222 #define IS_SDIO_CMD_INDEX(INDEX) ((INDEX) < 0x40)
bogdanm 92:4fc01daae5a5 223 /**
bogdanm 92:4fc01daae5a5 224 * @}
bogdanm 92:4fc01daae5a5 225 */
bogdanm 92:4fc01daae5a5 226
Kojto 99:dbbf35b96557 227 /** @defgroup SDIO_Response_Type Response Type
bogdanm 92:4fc01daae5a5 228 * @{
bogdanm 92:4fc01daae5a5 229 */
bogdanm 92:4fc01daae5a5 230 #define SDIO_RESPONSE_NO ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 231 #define SDIO_RESPONSE_SHORT SDIO_CMD_WAITRESP_0
bogdanm 92:4fc01daae5a5 232 #define SDIO_RESPONSE_LONG SDIO_CMD_WAITRESP
bogdanm 92:4fc01daae5a5 233
bogdanm 92:4fc01daae5a5 234 #define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO) || \
bogdanm 92:4fc01daae5a5 235 ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
bogdanm 92:4fc01daae5a5 236 ((RESPONSE) == SDIO_RESPONSE_LONG))
bogdanm 92:4fc01daae5a5 237 /**
bogdanm 92:4fc01daae5a5 238 * @}
bogdanm 92:4fc01daae5a5 239 */
bogdanm 92:4fc01daae5a5 240
Kojto 99:dbbf35b96557 241 /** @defgroup SDIO_Wait_Interrupt_State Wait Interrupt
bogdanm 92:4fc01daae5a5 242 * @{
bogdanm 92:4fc01daae5a5 243 */
bogdanm 92:4fc01daae5a5 244 #define SDIO_WAIT_NO ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 245 #define SDIO_WAIT_IT SDIO_CMD_WAITINT
bogdanm 92:4fc01daae5a5 246 #define SDIO_WAIT_PEND SDIO_CMD_WAITPEND
bogdanm 92:4fc01daae5a5 247
bogdanm 92:4fc01daae5a5 248 #define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
bogdanm 92:4fc01daae5a5 249 ((WAIT) == SDIO_WAIT_IT) || \
bogdanm 92:4fc01daae5a5 250 ((WAIT) == SDIO_WAIT_PEND))
bogdanm 92:4fc01daae5a5 251 /**
bogdanm 92:4fc01daae5a5 252 * @}
bogdanm 92:4fc01daae5a5 253 */
bogdanm 92:4fc01daae5a5 254
Kojto 99:dbbf35b96557 255 /** @defgroup SDIO_CPSM_State CPSM State
bogdanm 92:4fc01daae5a5 256 * @{
bogdanm 92:4fc01daae5a5 257 */
bogdanm 92:4fc01daae5a5 258 #define SDIO_CPSM_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 259 #define SDIO_CPSM_ENABLE SDIO_CMD_CPSMEN
bogdanm 92:4fc01daae5a5 260
bogdanm 92:4fc01daae5a5 261 #define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
bogdanm 92:4fc01daae5a5 262 ((CPSM) == SDIO_CPSM_ENABLE))
bogdanm 92:4fc01daae5a5 263 /**
bogdanm 92:4fc01daae5a5 264 * @}
bogdanm 92:4fc01daae5a5 265 */
bogdanm 92:4fc01daae5a5 266
Kojto 99:dbbf35b96557 267 /** @defgroup SDIO_Response_Registers Response Register
bogdanm 92:4fc01daae5a5 268 * @{
bogdanm 92:4fc01daae5a5 269 */
bogdanm 92:4fc01daae5a5 270 #define SDIO_RESP1 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 271 #define SDIO_RESP2 ((uint32_t)0x00000004)
bogdanm 92:4fc01daae5a5 272 #define SDIO_RESP3 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 273 #define SDIO_RESP4 ((uint32_t)0x0000000C)
bogdanm 92:4fc01daae5a5 274
bogdanm 92:4fc01daae5a5 275 #define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
bogdanm 92:4fc01daae5a5 276 ((RESP) == SDIO_RESP2) || \
bogdanm 92:4fc01daae5a5 277 ((RESP) == SDIO_RESP3) || \
bogdanm 92:4fc01daae5a5 278 ((RESP) == SDIO_RESP4))
bogdanm 92:4fc01daae5a5 279 /**
bogdanm 92:4fc01daae5a5 280 * @}
bogdanm 92:4fc01daae5a5 281 */
bogdanm 92:4fc01daae5a5 282
Kojto 99:dbbf35b96557 283 /** @defgroup SDIO_Data_Length Data Lenght
bogdanm 92:4fc01daae5a5 284 * @{
bogdanm 92:4fc01daae5a5 285 */
bogdanm 92:4fc01daae5a5 286 #define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
bogdanm 92:4fc01daae5a5 287 /**
bogdanm 92:4fc01daae5a5 288 * @}
bogdanm 92:4fc01daae5a5 289 */
bogdanm 92:4fc01daae5a5 290
Kojto 99:dbbf35b96557 291 /** @defgroup SDIO_Data_Block_Size Data Block Size
bogdanm 92:4fc01daae5a5 292 * @{
bogdanm 92:4fc01daae5a5 293 */
bogdanm 92:4fc01daae5a5 294 #define SDIO_DATABLOCK_SIZE_1B ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 295 #define SDIO_DATABLOCK_SIZE_2B SDIO_DCTRL_DBLOCKSIZE_0
bogdanm 92:4fc01daae5a5 296 #define SDIO_DATABLOCK_SIZE_4B SDIO_DCTRL_DBLOCKSIZE_1
bogdanm 92:4fc01daae5a5 297 #define SDIO_DATABLOCK_SIZE_8B ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 298 #define SDIO_DATABLOCK_SIZE_16B SDIO_DCTRL_DBLOCKSIZE_2
bogdanm 92:4fc01daae5a5 299 #define SDIO_DATABLOCK_SIZE_32B ((uint32_t)0x00000050)
bogdanm 92:4fc01daae5a5 300 #define SDIO_DATABLOCK_SIZE_64B ((uint32_t)0x00000060)
bogdanm 92:4fc01daae5a5 301 #define SDIO_DATABLOCK_SIZE_128B ((uint32_t)0x00000070)
bogdanm 92:4fc01daae5a5 302 #define SDIO_DATABLOCK_SIZE_256B SDIO_DCTRL_DBLOCKSIZE_3
bogdanm 92:4fc01daae5a5 303 #define SDIO_DATABLOCK_SIZE_512B ((uint32_t)0x00000090)
bogdanm 92:4fc01daae5a5 304 #define SDIO_DATABLOCK_SIZE_1024B ((uint32_t)0x000000A0)
bogdanm 92:4fc01daae5a5 305 #define SDIO_DATABLOCK_SIZE_2048B ((uint32_t)0x000000B0)
bogdanm 92:4fc01daae5a5 306 #define SDIO_DATABLOCK_SIZE_4096B ((uint32_t)0x000000C0)
bogdanm 92:4fc01daae5a5 307 #define SDIO_DATABLOCK_SIZE_8192B ((uint32_t)0x000000D0)
bogdanm 92:4fc01daae5a5 308 #define SDIO_DATABLOCK_SIZE_16384B ((uint32_t)0x000000E0)
bogdanm 92:4fc01daae5a5 309
bogdanm 92:4fc01daae5a5 310 #define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B) || \
bogdanm 92:4fc01daae5a5 311 ((SIZE) == SDIO_DATABLOCK_SIZE_2B) || \
bogdanm 92:4fc01daae5a5 312 ((SIZE) == SDIO_DATABLOCK_SIZE_4B) || \
bogdanm 92:4fc01daae5a5 313 ((SIZE) == SDIO_DATABLOCK_SIZE_8B) || \
bogdanm 92:4fc01daae5a5 314 ((SIZE) == SDIO_DATABLOCK_SIZE_16B) || \
bogdanm 92:4fc01daae5a5 315 ((SIZE) == SDIO_DATABLOCK_SIZE_32B) || \
bogdanm 92:4fc01daae5a5 316 ((SIZE) == SDIO_DATABLOCK_SIZE_64B) || \
bogdanm 92:4fc01daae5a5 317 ((SIZE) == SDIO_DATABLOCK_SIZE_128B) || \
bogdanm 92:4fc01daae5a5 318 ((SIZE) == SDIO_DATABLOCK_SIZE_256B) || \
bogdanm 92:4fc01daae5a5 319 ((SIZE) == SDIO_DATABLOCK_SIZE_512B) || \
bogdanm 92:4fc01daae5a5 320 ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
bogdanm 92:4fc01daae5a5 321 ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
bogdanm 92:4fc01daae5a5 322 ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
bogdanm 92:4fc01daae5a5 323 ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
bogdanm 92:4fc01daae5a5 324 ((SIZE) == SDIO_DATABLOCK_SIZE_16384B))
bogdanm 92:4fc01daae5a5 325 /**
bogdanm 92:4fc01daae5a5 326 * @}
bogdanm 92:4fc01daae5a5 327 */
bogdanm 92:4fc01daae5a5 328
Kojto 99:dbbf35b96557 329 /** @defgroup SDIO_Transfer_Direction Transfer Direction
bogdanm 92:4fc01daae5a5 330 * @{
bogdanm 92:4fc01daae5a5 331 */
bogdanm 92:4fc01daae5a5 332 #define SDIO_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 333 #define SDIO_TRANSFER_DIR_TO_SDIO SDIO_DCTRL_DTDIR
bogdanm 92:4fc01daae5a5 334
bogdanm 92:4fc01daae5a5 335 #define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
bogdanm 92:4fc01daae5a5 336 ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
bogdanm 92:4fc01daae5a5 337 /**
bogdanm 92:4fc01daae5a5 338 * @}
bogdanm 92:4fc01daae5a5 339 */
bogdanm 92:4fc01daae5a5 340
Kojto 99:dbbf35b96557 341 /** @defgroup SDIO_Transfer_Type Transfer Type
bogdanm 92:4fc01daae5a5 342 * @{
bogdanm 92:4fc01daae5a5 343 */
bogdanm 92:4fc01daae5a5 344 #define SDIO_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 345 #define SDIO_TRANSFER_MODE_STREAM SDIO_DCTRL_DTMODE
bogdanm 92:4fc01daae5a5 346
bogdanm 92:4fc01daae5a5 347 #define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
bogdanm 92:4fc01daae5a5 348 ((MODE) == SDIO_TRANSFER_MODE_STREAM))
bogdanm 92:4fc01daae5a5 349 /**
bogdanm 92:4fc01daae5a5 350 * @}
bogdanm 92:4fc01daae5a5 351 */
bogdanm 92:4fc01daae5a5 352
Kojto 99:dbbf35b96557 353 /** @defgroup SDIO_DPSM_State DPSM State
bogdanm 92:4fc01daae5a5 354 * @{
bogdanm 92:4fc01daae5a5 355 */
bogdanm 92:4fc01daae5a5 356 #define SDIO_DPSM_DISABLE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 357 #define SDIO_DPSM_ENABLE SDIO_DCTRL_DTEN
bogdanm 92:4fc01daae5a5 358
bogdanm 92:4fc01daae5a5 359 #define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
bogdanm 92:4fc01daae5a5 360 ((DPSM) == SDIO_DPSM_ENABLE))
bogdanm 92:4fc01daae5a5 361 /**
bogdanm 92:4fc01daae5a5 362 * @}
bogdanm 92:4fc01daae5a5 363 */
bogdanm 92:4fc01daae5a5 364
Kojto 99:dbbf35b96557 365 /** @defgroup SDIO_Read_Wait_Mode Read Wait Mode
bogdanm 92:4fc01daae5a5 366 * @{
bogdanm 92:4fc01daae5a5 367 */
Kojto 99:dbbf35b96557 368 #define SDIO_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000)
Kojto 99:dbbf35b96557 369 #define SDIO_READ_WAIT_MODE_CLK ((uint32_t)0x00000001)
bogdanm 92:4fc01daae5a5 370
bogdanm 92:4fc01daae5a5 371 #define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
bogdanm 92:4fc01daae5a5 372 ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
bogdanm 92:4fc01daae5a5 373 /**
bogdanm 92:4fc01daae5a5 374 * @}
bogdanm 92:4fc01daae5a5 375 */
bogdanm 92:4fc01daae5a5 376
Kojto 99:dbbf35b96557 377 /** @defgroup SDIO_Interrupt_sources Interrupt Sources
bogdanm 92:4fc01daae5a5 378 * @{
bogdanm 92:4fc01daae5a5 379 */
bogdanm 92:4fc01daae5a5 380 #define SDIO_IT_CCRCFAIL SDIO_STA_CCRCFAIL
bogdanm 92:4fc01daae5a5 381 #define SDIO_IT_DCRCFAIL SDIO_STA_DCRCFAIL
bogdanm 92:4fc01daae5a5 382 #define SDIO_IT_CTIMEOUT SDIO_STA_CTIMEOUT
bogdanm 92:4fc01daae5a5 383 #define SDIO_IT_DTIMEOUT SDIO_STA_DTIMEOUT
bogdanm 92:4fc01daae5a5 384 #define SDIO_IT_TXUNDERR SDIO_STA_TXUNDERR
bogdanm 92:4fc01daae5a5 385 #define SDIO_IT_RXOVERR SDIO_STA_RXOVERR
bogdanm 92:4fc01daae5a5 386 #define SDIO_IT_CMDREND SDIO_STA_CMDREND
bogdanm 92:4fc01daae5a5 387 #define SDIO_IT_CMDSENT SDIO_STA_CMDSENT
bogdanm 92:4fc01daae5a5 388 #define SDIO_IT_DATAEND SDIO_STA_DATAEND
bogdanm 92:4fc01daae5a5 389 #define SDIO_IT_STBITERR SDIO_STA_STBITERR
bogdanm 92:4fc01daae5a5 390 #define SDIO_IT_DBCKEND SDIO_STA_DBCKEND
bogdanm 92:4fc01daae5a5 391 #define SDIO_IT_CMDACT SDIO_STA_CMDACT
bogdanm 92:4fc01daae5a5 392 #define SDIO_IT_TXACT SDIO_STA_TXACT
bogdanm 92:4fc01daae5a5 393 #define SDIO_IT_RXACT SDIO_STA_RXACT
bogdanm 92:4fc01daae5a5 394 #define SDIO_IT_TXFIFOHE SDIO_STA_TXFIFOHE
bogdanm 92:4fc01daae5a5 395 #define SDIO_IT_RXFIFOHF SDIO_STA_RXFIFOHF
bogdanm 92:4fc01daae5a5 396 #define SDIO_IT_TXFIFOF SDIO_STA_TXFIFOF
bogdanm 92:4fc01daae5a5 397 #define SDIO_IT_RXFIFOF SDIO_STA_RXFIFOF
bogdanm 92:4fc01daae5a5 398 #define SDIO_IT_TXFIFOE SDIO_STA_TXFIFOE
bogdanm 92:4fc01daae5a5 399 #define SDIO_IT_RXFIFOE SDIO_STA_RXFIFOE
bogdanm 92:4fc01daae5a5 400 #define SDIO_IT_TXDAVL SDIO_STA_TXDAVL
bogdanm 92:4fc01daae5a5 401 #define SDIO_IT_RXDAVL SDIO_STA_RXDAVL
bogdanm 92:4fc01daae5a5 402 #define SDIO_IT_SDIOIT SDIO_STA_SDIOIT
bogdanm 92:4fc01daae5a5 403 #define SDIO_IT_CEATAEND SDIO_STA_CEATAEND
bogdanm 92:4fc01daae5a5 404 /**
bogdanm 92:4fc01daae5a5 405 * @}
bogdanm 92:4fc01daae5a5 406 */
bogdanm 92:4fc01daae5a5 407
Kojto 99:dbbf35b96557 408 /** @defgroup SDIO_Flags Flags
bogdanm 92:4fc01daae5a5 409 * @{
bogdanm 92:4fc01daae5a5 410 */
bogdanm 92:4fc01daae5a5 411 #define SDIO_FLAG_CCRCFAIL SDIO_STA_CCRCFAIL
bogdanm 92:4fc01daae5a5 412 #define SDIO_FLAG_DCRCFAIL SDIO_STA_DCRCFAIL
bogdanm 92:4fc01daae5a5 413 #define SDIO_FLAG_CTIMEOUT SDIO_STA_CTIMEOUT
bogdanm 92:4fc01daae5a5 414 #define SDIO_FLAG_DTIMEOUT SDIO_STA_DTIMEOUT
bogdanm 92:4fc01daae5a5 415 #define SDIO_FLAG_TXUNDERR SDIO_STA_TXUNDERR
bogdanm 92:4fc01daae5a5 416 #define SDIO_FLAG_RXOVERR SDIO_STA_RXOVERR
bogdanm 92:4fc01daae5a5 417 #define SDIO_FLAG_CMDREND SDIO_STA_CMDREND
bogdanm 92:4fc01daae5a5 418 #define SDIO_FLAG_CMDSENT SDIO_STA_CMDSENT
bogdanm 92:4fc01daae5a5 419 #define SDIO_FLAG_DATAEND SDIO_STA_DATAEND
bogdanm 92:4fc01daae5a5 420 #define SDIO_FLAG_STBITERR SDIO_STA_STBITERR
bogdanm 92:4fc01daae5a5 421 #define SDIO_FLAG_DBCKEND SDIO_STA_DBCKEND
bogdanm 92:4fc01daae5a5 422 #define SDIO_FLAG_CMDACT SDIO_STA_CMDACT
bogdanm 92:4fc01daae5a5 423 #define SDIO_FLAG_TXACT SDIO_STA_TXACT
bogdanm 92:4fc01daae5a5 424 #define SDIO_FLAG_RXACT SDIO_STA_RXACT
bogdanm 92:4fc01daae5a5 425 #define SDIO_FLAG_TXFIFOHE SDIO_STA_TXFIFOHE
bogdanm 92:4fc01daae5a5 426 #define SDIO_FLAG_RXFIFOHF SDIO_STA_RXFIFOHF
bogdanm 92:4fc01daae5a5 427 #define SDIO_FLAG_TXFIFOF SDIO_STA_TXFIFOF
bogdanm 92:4fc01daae5a5 428 #define SDIO_FLAG_RXFIFOF SDIO_STA_RXFIFOF
bogdanm 92:4fc01daae5a5 429 #define SDIO_FLAG_TXFIFOE SDIO_STA_TXFIFOE
bogdanm 92:4fc01daae5a5 430 #define SDIO_FLAG_RXFIFOE SDIO_STA_RXFIFOE
bogdanm 92:4fc01daae5a5 431 #define SDIO_FLAG_TXDAVL SDIO_STA_TXDAVL
bogdanm 92:4fc01daae5a5 432 #define SDIO_FLAG_RXDAVL SDIO_STA_RXDAVL
bogdanm 92:4fc01daae5a5 433 #define SDIO_FLAG_SDIOIT SDIO_STA_SDIOIT
bogdanm 92:4fc01daae5a5 434 #define SDIO_FLAG_CEATAEND SDIO_STA_CEATAEND
Kojto 99:dbbf35b96557 435 /**
Kojto 99:dbbf35b96557 436 * @}
Kojto 99:dbbf35b96557 437 */
bogdanm 92:4fc01daae5a5 438
bogdanm 92:4fc01daae5a5 439 /**
bogdanm 92:4fc01daae5a5 440 * @}
bogdanm 92:4fc01daae5a5 441 */
Kojto 99:dbbf35b96557 442 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 443 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
bogdanm 92:4fc01daae5a5 444 * @{
Kojto 99:dbbf35b96557 445 */
bogdanm 92:4fc01daae5a5 446
Kojto 99:dbbf35b96557 447 /** @defgroup SDMMC_LL_Alias_Region Bit Address in the alias region
Kojto 99:dbbf35b96557 448 * @{
bogdanm 92:4fc01daae5a5 449 */
bogdanm 92:4fc01daae5a5 450 /* ------------ SDIO registers bit address in the alias region -------------- */
bogdanm 92:4fc01daae5a5 451 #define SDIO_OFFSET (SDIO_BASE - PERIPH_BASE)
bogdanm 92:4fc01daae5a5 452
bogdanm 92:4fc01daae5a5 453 /* --- CLKCR Register ---*/
bogdanm 92:4fc01daae5a5 454 /* Alias word address of CLKEN bit */
bogdanm 92:4fc01daae5a5 455 #define CLKCR_OFFSET (SDIO_OFFSET + 0x04)
Kojto 99:dbbf35b96557 456 #define CLKEN_BITNUMBER 0x08
Kojto 99:dbbf35b96557 457 #define CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
bogdanm 92:4fc01daae5a5 458
bogdanm 92:4fc01daae5a5 459 /* --- CMD Register ---*/
bogdanm 92:4fc01daae5a5 460 /* Alias word address of SDIOSUSPEND bit */
bogdanm 92:4fc01daae5a5 461 #define CMD_OFFSET (SDIO_OFFSET + 0x0C)
Kojto 99:dbbf35b96557 462 #define SDIOSUSPEND_BITNUMBER 0x0B
Kojto 99:dbbf35b96557 463 #define CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
bogdanm 92:4fc01daae5a5 464
bogdanm 92:4fc01daae5a5 465 /* Alias word address of ENCMDCOMPL bit */
Kojto 99:dbbf35b96557 466 #define ENCMDCOMPL_BITNUMBER 0x0C
Kojto 99:dbbf35b96557 467 #define CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
bogdanm 92:4fc01daae5a5 468
bogdanm 92:4fc01daae5a5 469 /* Alias word address of NIEN bit */
Kojto 99:dbbf35b96557 470 #define NIEN_BITNUMBER 0x0D
Kojto 99:dbbf35b96557 471 #define CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
bogdanm 92:4fc01daae5a5 472
bogdanm 92:4fc01daae5a5 473 /* Alias word address of ATACMD bit */
Kojto 99:dbbf35b96557 474 #define ATACMD_BITNUMBER 0x0E
Kojto 99:dbbf35b96557 475 #define CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
bogdanm 92:4fc01daae5a5 476
bogdanm 92:4fc01daae5a5 477 /* --- DCTRL Register ---*/
bogdanm 92:4fc01daae5a5 478 /* Alias word address of DMAEN bit */
bogdanm 92:4fc01daae5a5 479 #define DCTRL_OFFSET (SDIO_OFFSET + 0x2C)
Kojto 99:dbbf35b96557 480 #define DMAEN_BITNUMBER 0x03
Kojto 99:dbbf35b96557 481 #define DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
bogdanm 92:4fc01daae5a5 482
bogdanm 92:4fc01daae5a5 483 /* Alias word address of RWSTART bit */
Kojto 99:dbbf35b96557 484 #define RWSTART_BITNUMBER 0x08
Kojto 99:dbbf35b96557 485 #define DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
bogdanm 92:4fc01daae5a5 486
bogdanm 92:4fc01daae5a5 487 /* Alias word address of RWSTOP bit */
Kojto 99:dbbf35b96557 488 #define RWSTOP_BITNUMBER 0x09
Kojto 99:dbbf35b96557 489 #define DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
bogdanm 92:4fc01daae5a5 490
bogdanm 92:4fc01daae5a5 491 /* Alias word address of RWMOD bit */
Kojto 99:dbbf35b96557 492 #define RWMOD_BITNUMBER 0x0A
Kojto 99:dbbf35b96557 493 #define DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
bogdanm 92:4fc01daae5a5 494
bogdanm 92:4fc01daae5a5 495 /* Alias word address of SDIOEN bit */
Kojto 99:dbbf35b96557 496 #define SDIOEN_BITNUMBER 0x0B
Kojto 99:dbbf35b96557 497 #define DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
Kojto 99:dbbf35b96557 498 /**
Kojto 99:dbbf35b96557 499 * @}
Kojto 99:dbbf35b96557 500 */
Kojto 99:dbbf35b96557 501
Kojto 99:dbbf35b96557 502 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
Kojto 99:dbbf35b96557 503 * @brief SDMMC_LL registers bit address in the alias region
Kojto 99:dbbf35b96557 504 * @{
Kojto 99:dbbf35b96557 505 */
bogdanm 92:4fc01daae5a5 506
bogdanm 92:4fc01daae5a5 507 /* ---------------------- SDIO registers bit mask --------------------------- */
bogdanm 92:4fc01daae5a5 508 /* --- CLKCR Register ---*/
bogdanm 92:4fc01daae5a5 509 /* CLKCR register clear mask */
bogdanm 92:4fc01daae5a5 510 #define CLKCR_CLEAR_MASK ((uint32_t)(SDIO_CLKCR_CLKDIV | SDIO_CLKCR_PWRSAV |\
bogdanm 92:4fc01daae5a5 511 SDIO_CLKCR_BYPASS | SDIO_CLKCR_WIDBUS |\
bogdanm 92:4fc01daae5a5 512 SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
bogdanm 92:4fc01daae5a5 513
bogdanm 92:4fc01daae5a5 514 /* --- PWRCTRL Register ---*/
bogdanm 92:4fc01daae5a5 515 /* --- DCTRL Register ---*/
bogdanm 92:4fc01daae5a5 516 /* SDIO DCTRL Clear Mask */
bogdanm 92:4fc01daae5a5 517 #define DCTRL_CLEAR_MASK ((uint32_t)(SDIO_DCTRL_DTEN | SDIO_DCTRL_DTDIR |\
bogdanm 92:4fc01daae5a5 518 SDIO_DCTRL_DTMODE | SDIO_DCTRL_DBLOCKSIZE))
bogdanm 92:4fc01daae5a5 519
bogdanm 92:4fc01daae5a5 520 /* --- CMD Register ---*/
bogdanm 92:4fc01daae5a5 521 /* CMD Register clear mask */
bogdanm 92:4fc01daae5a5 522 #define CMD_CLEAR_MASK ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
bogdanm 92:4fc01daae5a5 523 SDIO_CMD_WAITINT | SDIO_CMD_WAITPEND |\
bogdanm 92:4fc01daae5a5 524 SDIO_CMD_CPSMEN | SDIO_CMD_SDIOSUSPEND))
bogdanm 92:4fc01daae5a5 525
bogdanm 92:4fc01daae5a5 526 /* SDIO RESP Registers Address */
bogdanm 92:4fc01daae5a5 527 #define SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14))
bogdanm 92:4fc01daae5a5 528
Kojto 99:dbbf35b96557 529 /* SDIO Initialization Frequency (400KHz max) */
bogdanm 92:4fc01daae5a5 530 #define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
bogdanm 92:4fc01daae5a5 531
bogdanm 92:4fc01daae5a5 532 /* SDIO Data Transfer Frequency (25MHz max) */
bogdanm 92:4fc01daae5a5 533 #define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x0)
Kojto 99:dbbf35b96557 534 /**
Kojto 99:dbbf35b96557 535 * @}
Kojto 99:dbbf35b96557 536 */
bogdanm 92:4fc01daae5a5 537
Kojto 99:dbbf35b96557 538 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
Kojto 99:dbbf35b96557 539 * @brief macros to handle interrupts and specific clock configurations
Kojto 99:dbbf35b96557 540 * @{
Kojto 99:dbbf35b96557 541 */
Kojto 99:dbbf35b96557 542
bogdanm 92:4fc01daae5a5 543 /**
bogdanm 92:4fc01daae5a5 544 * @brief Enable the SDIO device.
bogdanm 92:4fc01daae5a5 545 * @retval None
bogdanm 92:4fc01daae5a5 546 */
bogdanm 92:4fc01daae5a5 547 #define __SDIO_ENABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
bogdanm 92:4fc01daae5a5 548
bogdanm 92:4fc01daae5a5 549 /**
bogdanm 92:4fc01daae5a5 550 * @brief Disable the SDIO device.
bogdanm 92:4fc01daae5a5 551 * @retval None
bogdanm 92:4fc01daae5a5 552 */
bogdanm 92:4fc01daae5a5 553 #define __SDIO_DISABLE() (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
bogdanm 92:4fc01daae5a5 554
bogdanm 92:4fc01daae5a5 555 /**
bogdanm 92:4fc01daae5a5 556 * @brief Enable the SDIO DMA transfer.
bogdanm 92:4fc01daae5a5 557 * @retval None
bogdanm 92:4fc01daae5a5 558 */
bogdanm 92:4fc01daae5a5 559 #define __SDIO_DMA_ENABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
bogdanm 92:4fc01daae5a5 560
bogdanm 92:4fc01daae5a5 561 /**
bogdanm 92:4fc01daae5a5 562 * @brief Disable the SDIO DMA transfer.
bogdanm 92:4fc01daae5a5 563 * @retval None
bogdanm 92:4fc01daae5a5 564 */
bogdanm 92:4fc01daae5a5 565 #define __SDIO_DMA_DISABLE() (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
bogdanm 92:4fc01daae5a5 566
bogdanm 92:4fc01daae5a5 567 /**
bogdanm 92:4fc01daae5a5 568 * @brief Enable the SDIO device interrupt.
bogdanm 92:4fc01daae5a5 569 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 92:4fc01daae5a5 570 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
bogdanm 92:4fc01daae5a5 571 * This parameter can be one or a combination of the following values:
bogdanm 92:4fc01daae5a5 572 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 92:4fc01daae5a5 573 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 92:4fc01daae5a5 574 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 92:4fc01daae5a5 575 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 92:4fc01daae5a5 576 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 92:4fc01daae5a5 577 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 92:4fc01daae5a5 578 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 92:4fc01daae5a5 579 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 92:4fc01daae5a5 580 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 92:4fc01daae5a5 581 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 92:4fc01daae5a5 582 * bus mode interrupt
bogdanm 92:4fc01daae5a5 583 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 92:4fc01daae5a5 584 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 92:4fc01daae5a5 585 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 92:4fc01daae5a5 586 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 92:4fc01daae5a5 587 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 92:4fc01daae5a5 588 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 92:4fc01daae5a5 589 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 92:4fc01daae5a5 590 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 92:4fc01daae5a5 591 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 92:4fc01daae5a5 592 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 92:4fc01daae5a5 593 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 92:4fc01daae5a5 594 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 92:4fc01daae5a5 595 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 92:4fc01daae5a5 596 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 92:4fc01daae5a5 597 * @retval None
bogdanm 92:4fc01daae5a5 598 */
bogdanm 92:4fc01daae5a5 599 #define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 600
bogdanm 92:4fc01daae5a5 601 /**
bogdanm 92:4fc01daae5a5 602 * @brief Disable the SDIO device interrupt.
bogdanm 92:4fc01daae5a5 603 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 92:4fc01daae5a5 604 * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
bogdanm 92:4fc01daae5a5 605 * This parameter can be one or a combination of the following values:
bogdanm 92:4fc01daae5a5 606 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 92:4fc01daae5a5 607 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 92:4fc01daae5a5 608 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 92:4fc01daae5a5 609 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 92:4fc01daae5a5 610 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 92:4fc01daae5a5 611 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 92:4fc01daae5a5 612 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 92:4fc01daae5a5 613 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 92:4fc01daae5a5 614 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 92:4fc01daae5a5 615 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 92:4fc01daae5a5 616 * bus mode interrupt
bogdanm 92:4fc01daae5a5 617 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 92:4fc01daae5a5 618 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 92:4fc01daae5a5 619 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 92:4fc01daae5a5 620 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 92:4fc01daae5a5 621 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 92:4fc01daae5a5 622 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 92:4fc01daae5a5 623 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 92:4fc01daae5a5 624 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 92:4fc01daae5a5 625 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 92:4fc01daae5a5 626 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 92:4fc01daae5a5 627 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 92:4fc01daae5a5 628 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 92:4fc01daae5a5 629 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 92:4fc01daae5a5 630 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 92:4fc01daae5a5 631 * @retval None
bogdanm 92:4fc01daae5a5 632 */
bogdanm 92:4fc01daae5a5 633 #define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
bogdanm 92:4fc01daae5a5 634
bogdanm 92:4fc01daae5a5 635 /**
bogdanm 92:4fc01daae5a5 636 * @brief Checks whether the specified SDIO flag is set or not.
bogdanm 92:4fc01daae5a5 637 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 92:4fc01daae5a5 638 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 639 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 640 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm 92:4fc01daae5a5 641 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm 92:4fc01daae5a5 642 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm 92:4fc01daae5a5 643 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm 92:4fc01daae5a5 644 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm 92:4fc01daae5a5 645 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm 92:4fc01daae5a5 646 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm 92:4fc01daae5a5 647 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm 92:4fc01daae5a5 648 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm 92:4fc01daae5a5 649 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
bogdanm 92:4fc01daae5a5 650 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm 92:4fc01daae5a5 651 * @arg SDIO_FLAG_CMDACT: Command transfer in progress
bogdanm 92:4fc01daae5a5 652 * @arg SDIO_FLAG_TXACT: Data transmit in progress
bogdanm 92:4fc01daae5a5 653 * @arg SDIO_FLAG_RXACT: Data receive in progress
bogdanm 92:4fc01daae5a5 654 * @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
bogdanm 92:4fc01daae5a5 655 * @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
bogdanm 92:4fc01daae5a5 656 * @arg SDIO_FLAG_TXFIFOF: Transmit FIFO full
bogdanm 92:4fc01daae5a5 657 * @arg SDIO_FLAG_RXFIFOF: Receive FIFO full
bogdanm 92:4fc01daae5a5 658 * @arg SDIO_FLAG_TXFIFOE: Transmit FIFO empty
bogdanm 92:4fc01daae5a5 659 * @arg SDIO_FLAG_RXFIFOE: Receive FIFO empty
bogdanm 92:4fc01daae5a5 660 * @arg SDIO_FLAG_TXDAVL: Data available in transmit FIFO
bogdanm 92:4fc01daae5a5 661 * @arg SDIO_FLAG_RXDAVL: Data available in receive FIFO
bogdanm 92:4fc01daae5a5 662 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm 92:4fc01daae5a5 663 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 92:4fc01daae5a5 664 * @retval The new state of SDIO_FLAG (SET or RESET).
bogdanm 92:4fc01daae5a5 665 */
bogdanm 92:4fc01daae5a5 666 #define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
bogdanm 92:4fc01daae5a5 667
bogdanm 92:4fc01daae5a5 668
bogdanm 92:4fc01daae5a5 669 /**
bogdanm 92:4fc01daae5a5 670 * @brief Clears the SDIO pending flags.
bogdanm 92:4fc01daae5a5 671 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 92:4fc01daae5a5 672 * @param __FLAG__: specifies the flag to clear.
bogdanm 92:4fc01daae5a5 673 * This parameter can be one or a combination of the following values:
bogdanm 92:4fc01daae5a5 674 * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
bogdanm 92:4fc01daae5a5 675 * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
bogdanm 92:4fc01daae5a5 676 * @arg SDIO_FLAG_CTIMEOUT: Command response timeout
bogdanm 92:4fc01daae5a5 677 * @arg SDIO_FLAG_DTIMEOUT: Data timeout
bogdanm 92:4fc01daae5a5 678 * @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
bogdanm 92:4fc01daae5a5 679 * @arg SDIO_FLAG_RXOVERR: Received FIFO overrun error
bogdanm 92:4fc01daae5a5 680 * @arg SDIO_FLAG_CMDREND: Command response received (CRC check passed)
bogdanm 92:4fc01daae5a5 681 * @arg SDIO_FLAG_CMDSENT: Command sent (no response required)
bogdanm 92:4fc01daae5a5 682 * @arg SDIO_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
bogdanm 92:4fc01daae5a5 683 * @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
bogdanm 92:4fc01daae5a5 684 * @arg SDIO_FLAG_DBCKEND: Data block sent/received (CRC check passed)
bogdanm 92:4fc01daae5a5 685 * @arg SDIO_FLAG_SDIOIT: SD I/O interrupt received
bogdanm 92:4fc01daae5a5 686 * @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 92:4fc01daae5a5 687 * @retval None
bogdanm 92:4fc01daae5a5 688 */
bogdanm 92:4fc01daae5a5 689 #define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
bogdanm 92:4fc01daae5a5 690
bogdanm 92:4fc01daae5a5 691 /**
bogdanm 92:4fc01daae5a5 692 * @brief Checks whether the specified SDIO interrupt has occurred or not.
bogdanm 92:4fc01daae5a5 693 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 92:4fc01daae5a5 694 * @param __INTERRUPT__: specifies the SDIO interrupt source to check.
bogdanm 92:4fc01daae5a5 695 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 696 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 92:4fc01daae5a5 697 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 92:4fc01daae5a5 698 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 92:4fc01daae5a5 699 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 92:4fc01daae5a5 700 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 92:4fc01daae5a5 701 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 92:4fc01daae5a5 702 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 92:4fc01daae5a5 703 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 92:4fc01daae5a5 704 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
bogdanm 92:4fc01daae5a5 705 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 92:4fc01daae5a5 706 * bus mode interrupt
bogdanm 92:4fc01daae5a5 707 * @arg SDIO_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
bogdanm 92:4fc01daae5a5 708 * @arg SDIO_IT_CMDACT: Command transfer in progress interrupt
bogdanm 92:4fc01daae5a5 709 * @arg SDIO_IT_TXACT: Data transmit in progress interrupt
bogdanm 92:4fc01daae5a5 710 * @arg SDIO_IT_RXACT: Data receive in progress interrupt
bogdanm 92:4fc01daae5a5 711 * @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
bogdanm 92:4fc01daae5a5 712 * @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
bogdanm 92:4fc01daae5a5 713 * @arg SDIO_IT_TXFIFOF: Transmit FIFO full interrupt
bogdanm 92:4fc01daae5a5 714 * @arg SDIO_IT_RXFIFOF: Receive FIFO full interrupt
bogdanm 92:4fc01daae5a5 715 * @arg SDIO_IT_TXFIFOE: Transmit FIFO empty interrupt
bogdanm 92:4fc01daae5a5 716 * @arg SDIO_IT_RXFIFOE: Receive FIFO empty interrupt
bogdanm 92:4fc01daae5a5 717 * @arg SDIO_IT_TXDAVL: Data available in transmit FIFO interrupt
bogdanm 92:4fc01daae5a5 718 * @arg SDIO_IT_RXDAVL: Data available in receive FIFO interrupt
bogdanm 92:4fc01daae5a5 719 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 92:4fc01daae5a5 720 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
bogdanm 92:4fc01daae5a5 721 * @retval The new state of SDIO_IT (SET or RESET).
bogdanm 92:4fc01daae5a5 722 */
bogdanm 92:4fc01daae5a5 723 #define __SDIO_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 724
bogdanm 92:4fc01daae5a5 725 /**
bogdanm 92:4fc01daae5a5 726 * @brief Clears the SDIO's interrupt pending bits.
bogdanm 92:4fc01daae5a5 727 * @param __INSTANCE__ : Pointer to SDIO register base
bogdanm 92:4fc01daae5a5 728 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm 92:4fc01daae5a5 729 * This parameter can be one or a combination of the following values:
bogdanm 92:4fc01daae5a5 730 * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
bogdanm 92:4fc01daae5a5 731 * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
bogdanm 92:4fc01daae5a5 732 * @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
bogdanm 92:4fc01daae5a5 733 * @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
bogdanm 92:4fc01daae5a5 734 * @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
bogdanm 92:4fc01daae5a5 735 * @arg SDIO_IT_RXOVERR: Received FIFO overrun error interrupt
bogdanm 92:4fc01daae5a5 736 * @arg SDIO_IT_CMDREND: Command response received (CRC check passed) interrupt
bogdanm 92:4fc01daae5a5 737 * @arg SDIO_IT_CMDSENT: Command sent (no response required) interrupt
bogdanm 92:4fc01daae5a5 738 * @arg SDIO_IT_DATAEND: Data end (data counter, SDIO_DCOUNT, is zero) interrupt
bogdanm 92:4fc01daae5a5 739 * @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide
bogdanm 92:4fc01daae5a5 740 * bus mode interrupt
bogdanm 92:4fc01daae5a5 741 * @arg SDIO_IT_SDIOIT: SD I/O interrupt received interrupt
bogdanm 92:4fc01daae5a5 742 * @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
bogdanm 92:4fc01daae5a5 743 * @retval None
bogdanm 92:4fc01daae5a5 744 */
bogdanm 92:4fc01daae5a5 745 #define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 746
bogdanm 92:4fc01daae5a5 747 /**
bogdanm 92:4fc01daae5a5 748 * @brief Enable Start the SD I/O Read Wait operation.
bogdanm 92:4fc01daae5a5 749 * @retval None
bogdanm 92:4fc01daae5a5 750 */
bogdanm 92:4fc01daae5a5 751 #define __SDIO_START_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
bogdanm 92:4fc01daae5a5 752
bogdanm 92:4fc01daae5a5 753 /**
bogdanm 92:4fc01daae5a5 754 * @brief Disable Start the SD I/O Read Wait operations.
bogdanm 92:4fc01daae5a5 755 * @retval None
bogdanm 92:4fc01daae5a5 756 */
bogdanm 92:4fc01daae5a5 757 #define __SDIO_START_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
bogdanm 92:4fc01daae5a5 758
bogdanm 92:4fc01daae5a5 759 /**
bogdanm 92:4fc01daae5a5 760 * @brief Enable Start the SD I/O Read Wait operation.
bogdanm 92:4fc01daae5a5 761 * @retval None
bogdanm 92:4fc01daae5a5 762 */
bogdanm 92:4fc01daae5a5 763 #define __SDIO_STOP_READWAIT_ENABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
bogdanm 92:4fc01daae5a5 764
bogdanm 92:4fc01daae5a5 765 /**
bogdanm 92:4fc01daae5a5 766 * @brief Disable Stop the SD I/O Read Wait operations.
bogdanm 92:4fc01daae5a5 767 * @retval None
bogdanm 92:4fc01daae5a5 768 */
bogdanm 92:4fc01daae5a5 769 #define __SDIO_STOP_READWAIT_DISABLE() (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
bogdanm 92:4fc01daae5a5 770
bogdanm 92:4fc01daae5a5 771 /**
bogdanm 92:4fc01daae5a5 772 * @brief Enable the SD I/O Mode Operation.
bogdanm 92:4fc01daae5a5 773 * @retval None
bogdanm 92:4fc01daae5a5 774 */
bogdanm 92:4fc01daae5a5 775 #define __SDIO_OPERATION_ENABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
bogdanm 92:4fc01daae5a5 776
bogdanm 92:4fc01daae5a5 777 /**
bogdanm 92:4fc01daae5a5 778 * @brief Disable the SD I/O Mode Operation.
bogdanm 92:4fc01daae5a5 779 * @retval None
bogdanm 92:4fc01daae5a5 780 */
bogdanm 92:4fc01daae5a5 781 #define __SDIO_OPERATION_DISABLE() (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
bogdanm 92:4fc01daae5a5 782
bogdanm 92:4fc01daae5a5 783 /**
bogdanm 92:4fc01daae5a5 784 * @brief Enable the SD I/O Suspend command sending.
bogdanm 92:4fc01daae5a5 785 * @retval None
bogdanm 92:4fc01daae5a5 786 */
bogdanm 92:4fc01daae5a5 787 #define __SDIO_SUSPEND_CMD_ENABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
bogdanm 92:4fc01daae5a5 788
bogdanm 92:4fc01daae5a5 789 /**
bogdanm 92:4fc01daae5a5 790 * @brief Disable the SD I/O Suspend command sending.
bogdanm 92:4fc01daae5a5 791 * @retval None
bogdanm 92:4fc01daae5a5 792 */
bogdanm 92:4fc01daae5a5 793 #define __SDIO_SUSPEND_CMD_DISABLE() (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
Kojto 99:dbbf35b96557 794
Kojto 99:dbbf35b96557 795 #if !defined(STM32F446xx)
bogdanm 92:4fc01daae5a5 796 /**
bogdanm 92:4fc01daae5a5 797 * @brief Enable the command completion signal.
bogdanm 92:4fc01daae5a5 798 * @retval None
bogdanm 92:4fc01daae5a5 799 */
bogdanm 92:4fc01daae5a5 800 #define __SDIO_CEATA_CMD_COMPLETION_ENABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
bogdanm 92:4fc01daae5a5 801
bogdanm 92:4fc01daae5a5 802 /**
bogdanm 92:4fc01daae5a5 803 * @brief Disable the command completion signal.
bogdanm 92:4fc01daae5a5 804 * @retval None
bogdanm 92:4fc01daae5a5 805 */
bogdanm 92:4fc01daae5a5 806 #define __SDIO_CEATA_CMD_COMPLETION_DISABLE() (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
bogdanm 92:4fc01daae5a5 807
bogdanm 92:4fc01daae5a5 808 /**
bogdanm 92:4fc01daae5a5 809 * @brief Enable the CE-ATA interrupt.
bogdanm 92:4fc01daae5a5 810 * @retval None
bogdanm 92:4fc01daae5a5 811 */
bogdanm 92:4fc01daae5a5 812 #define __SDIO_CEATA_ENABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
bogdanm 92:4fc01daae5a5 813
bogdanm 92:4fc01daae5a5 814 /**
bogdanm 92:4fc01daae5a5 815 * @brief Disable the CE-ATA interrupt.
bogdanm 92:4fc01daae5a5 816 * @retval None
bogdanm 92:4fc01daae5a5 817 */
bogdanm 92:4fc01daae5a5 818 #define __SDIO_CEATA_DISABLE_IT() (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
bogdanm 92:4fc01daae5a5 819
bogdanm 92:4fc01daae5a5 820 /**
bogdanm 92:4fc01daae5a5 821 * @brief Enable send CE-ATA command (CMD61).
bogdanm 92:4fc01daae5a5 822 * @retval None
bogdanm 92:4fc01daae5a5 823 */
bogdanm 92:4fc01daae5a5 824 #define __SDIO_CEATA_SENDCMD_ENABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
bogdanm 92:4fc01daae5a5 825
bogdanm 92:4fc01daae5a5 826 /**
bogdanm 92:4fc01daae5a5 827 * @brief Disable send CE-ATA command (CMD61).
bogdanm 92:4fc01daae5a5 828 * @retval None
bogdanm 92:4fc01daae5a5 829 */
bogdanm 92:4fc01daae5a5 830 #define __SDIO_CEATA_SENDCMD_DISABLE() (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
Kojto 99:dbbf35b96557 831 #endif /* !defined(STM32F446xx) */
bogdanm 92:4fc01daae5a5 832 /**
bogdanm 92:4fc01daae5a5 833 * @}
bogdanm 92:4fc01daae5a5 834 */
bogdanm 92:4fc01daae5a5 835
bogdanm 92:4fc01daae5a5 836 /**
bogdanm 92:4fc01daae5a5 837 * @}
bogdanm 92:4fc01daae5a5 838 */
bogdanm 92:4fc01daae5a5 839
bogdanm 92:4fc01daae5a5 840 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 841 /** @addtogroup SDMMC_LL_Exported_Functions
bogdanm 92:4fc01daae5a5 842 * @{
bogdanm 92:4fc01daae5a5 843 */
bogdanm 92:4fc01daae5a5 844
bogdanm 92:4fc01daae5a5 845 /* Initialization/de-initialization functions **********************************/
Kojto 99:dbbf35b96557 846 /** @addtogroup HAL_SDMMC_LL_Group1
bogdanm 92:4fc01daae5a5 847 * @{
bogdanm 92:4fc01daae5a5 848 */
bogdanm 92:4fc01daae5a5 849 HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
bogdanm 92:4fc01daae5a5 850 /**
bogdanm 92:4fc01daae5a5 851 * @}
bogdanm 92:4fc01daae5a5 852 */
bogdanm 92:4fc01daae5a5 853
bogdanm 92:4fc01daae5a5 854 /* I/O operation functions *****************************************************/
Kojto 99:dbbf35b96557 855 /** @addtogroup HAL_SDMMC_LL_Group2
bogdanm 92:4fc01daae5a5 856 * @{
bogdanm 92:4fc01daae5a5 857 */
bogdanm 92:4fc01daae5a5 858 /* Blocking mode: Polling */
bogdanm 92:4fc01daae5a5 859 uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
bogdanm 92:4fc01daae5a5 860 HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
bogdanm 92:4fc01daae5a5 861 /**
bogdanm 92:4fc01daae5a5 862 * @}
bogdanm 92:4fc01daae5a5 863 */
bogdanm 92:4fc01daae5a5 864
bogdanm 92:4fc01daae5a5 865 /* Peripheral Control functions ************************************************/
Kojto 99:dbbf35b96557 866 /** @addtogroup HAL_SDMMC_LL_Group3
bogdanm 92:4fc01daae5a5 867 * @{
bogdanm 92:4fc01daae5a5 868 */
bogdanm 92:4fc01daae5a5 869 HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
bogdanm 92:4fc01daae5a5 870 HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
bogdanm 92:4fc01daae5a5 871 uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
bogdanm 92:4fc01daae5a5 872
bogdanm 92:4fc01daae5a5 873 /* Command path state machine (CPSM) management functions */
bogdanm 92:4fc01daae5a5 874 HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
bogdanm 92:4fc01daae5a5 875 uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
bogdanm 92:4fc01daae5a5 876 uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
bogdanm 92:4fc01daae5a5 877
bogdanm 92:4fc01daae5a5 878 /* Data path state machine (DPSM) management functions */
bogdanm 92:4fc01daae5a5 879 HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
bogdanm 92:4fc01daae5a5 880 uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
bogdanm 92:4fc01daae5a5 881 uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
bogdanm 92:4fc01daae5a5 882
bogdanm 92:4fc01daae5a5 883 /* SDIO IO Cards mode management functions */
bogdanm 92:4fc01daae5a5 884 HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
bogdanm 92:4fc01daae5a5 885
bogdanm 92:4fc01daae5a5 886 /**
bogdanm 92:4fc01daae5a5 887 * @}
bogdanm 92:4fc01daae5a5 888 */
bogdanm 92:4fc01daae5a5 889
bogdanm 92:4fc01daae5a5 890 /**
bogdanm 92:4fc01daae5a5 891 * @}
bogdanm 92:4fc01daae5a5 892 */
bogdanm 92:4fc01daae5a5 893
bogdanm 92:4fc01daae5a5 894 /**
bogdanm 92:4fc01daae5a5 895 * @}
bogdanm 92:4fc01daae5a5 896 */
bogdanm 92:4fc01daae5a5 897
bogdanm 92:4fc01daae5a5 898 /**
bogdanm 92:4fc01daae5a5 899 * @}
bogdanm 92:4fc01daae5a5 900 */
bogdanm 92:4fc01daae5a5 901
bogdanm 92:4fc01daae5a5 902 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 903 }
bogdanm 92:4fc01daae5a5 904 #endif
bogdanm 92:4fc01daae5a5 905
bogdanm 92:4fc01daae5a5 906 #endif /* __STM32F4xx_LL_SDMMC_H */
bogdanm 92:4fc01daae5a5 907
bogdanm 92:4fc01daae5a5 908 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/