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TARGET_NUCLEO_F303K8/stm32f3xx_hal_rcc_ex.h@109:9296ab0bfc11, 2015-10-29 (annotated)

Committer:
Kojto
Date:
Thu Oct 29 08:40:18 2015 +0000
Revision:
109:9296ab0bfc11
Release 109  of the mbed library



Changes:

- new platforms - NUCLEO_F042K6, WIZNWIKI_W7500ECO

- MTS targets - bootloaders update to 0.1.1

- STM F7 - RTC enable fixes

- STM F4 - i2c pending stop before start fix

- STM all targets - analogout normalization fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**
Kojto 109:9296ab0bfc11 2 ******************************************************************************
Kojto 109:9296ab0bfc11 3 * @file stm32f3xx_hal_rcc_ex.h
Kojto 109:9296ab0bfc11 4 * @author MCD Application Team
Kojto 109:9296ab0bfc11 5 * @version V1.1.0
Kojto 109:9296ab0bfc11 6 * @date 12-Sept-2014
Kojto 109:9296ab0bfc11 7 * @brief Header file of RCC HAL Extended module.
Kojto 109:9296ab0bfc11 8 ******************************************************************************
Kojto 109:9296ab0bfc11 9 * @attention
Kojto 109:9296ab0bfc11 10 *
Kojto 109:9296ab0bfc11 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 109:9296ab0bfc11 12 *
Kojto 109:9296ab0bfc11 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 109:9296ab0bfc11 14 * are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 109:9296ab0bfc11 16 * this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 109:9296ab0bfc11 18 * this list of conditions and the following disclaimer in the documentation
Kojto 109:9296ab0bfc11 19 * and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 109:9296ab0bfc11 21 * may be used to endorse or promote products derived from this software
Kojto 109:9296ab0bfc11 22 * without specific prior written permission.
Kojto 109:9296ab0bfc11 23 *
Kojto 109:9296ab0bfc11 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 109:9296ab0bfc11 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 109:9296ab0bfc11 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 109:9296ab0bfc11 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 109:9296ab0bfc11 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 109:9296ab0bfc11 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 109:9296ab0bfc11 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 109:9296ab0bfc11 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 34 *
Kojto 109:9296ab0bfc11 35 ******************************************************************************
Kojto 109:9296ab0bfc11 36 */
Kojto 109:9296ab0bfc11 37
Kojto 109:9296ab0bfc11 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 109:9296ab0bfc11 39 #ifndef __STM32F3xx_HAL_RCC_EX_H
Kojto 109:9296ab0bfc11 40 #define __STM32F3xx_HAL_RCC_EX_H
Kojto 109:9296ab0bfc11 41
Kojto 109:9296ab0bfc11 42 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 43 extern "C" {
Kojto 109:9296ab0bfc11 44 #endif
Kojto 109:9296ab0bfc11 45
Kojto 109:9296ab0bfc11 46 /* Includes ------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 47 #include "stm32f3xx_hal_def.h"
Kojto 109:9296ab0bfc11 48
Kojto 109:9296ab0bfc11 49 /** @addtogroup STM32F3xx_HAL_Driver
Kojto 109:9296ab0bfc11 50 * @{
Kojto 109:9296ab0bfc11 51 */
Kojto 109:9296ab0bfc11 52
Kojto 109:9296ab0bfc11 53 /** @addtogroup RCCEx
Kojto 109:9296ab0bfc11 54 * @{
Kojto 109:9296ab0bfc11 55 */
Kojto 109:9296ab0bfc11 56
Kojto 109:9296ab0bfc11 57 /* Exported types ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 58
Kojto 109:9296ab0bfc11 59 /** @defgroup RCCEx_Exported_Types RCC Extended Exported Types
Kojto 109:9296ab0bfc11 60 * @{
Kojto 109:9296ab0bfc11 61 */
Kojto 109:9296ab0bfc11 62 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 63 /**
Kojto 109:9296ab0bfc11 64 * @brief RCC PLL configuration structure definition
Kojto 109:9296ab0bfc11 65 */
Kojto 109:9296ab0bfc11 66 typedef struct
Kojto 109:9296ab0bfc11 67 {
Kojto 109:9296ab0bfc11 68 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto 109:9296ab0bfc11 69 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 109:9296ab0bfc11 70
Kojto 109:9296ab0bfc11 71 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto 109:9296ab0bfc11 72 This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
Kojto 109:9296ab0bfc11 73
Kojto 109:9296ab0bfc11 74 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto 109:9296ab0bfc11 75 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto 109:9296ab0bfc11 76
Kojto 109:9296ab0bfc11 77 uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
Kojto 109:9296ab0bfc11 78 This parameter must be a value of @ref RCCEx_PLL_Prediv_Factor */
Kojto 109:9296ab0bfc11 79
Kojto 109:9296ab0bfc11 80 }RCC_PLLInitTypeDef;
Kojto 109:9296ab0bfc11 81
Kojto 109:9296ab0bfc11 82 /**
Kojto 109:9296ab0bfc11 83 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 109:9296ab0bfc11 84 */
Kojto 109:9296ab0bfc11 85 typedef struct
Kojto 109:9296ab0bfc11 86 {
Kojto 109:9296ab0bfc11 87 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 109:9296ab0bfc11 88 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 109:9296ab0bfc11 89
Kojto 109:9296ab0bfc11 90 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 109:9296ab0bfc11 91 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 109:9296ab0bfc11 92
Kojto 109:9296ab0bfc11 93 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 109:9296ab0bfc11 94 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 109:9296ab0bfc11 95
Kojto 109:9296ab0bfc11 96 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 109:9296ab0bfc11 97 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 109:9296ab0bfc11 98
Kojto 109:9296ab0bfc11 99 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto 109:9296ab0bfc11 100 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 109:9296ab0bfc11 101
Kojto 109:9296ab0bfc11 102 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 109:9296ab0bfc11 103 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 109:9296ab0bfc11 104
Kojto 109:9296ab0bfc11 105 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 109:9296ab0bfc11 106
Kojto 109:9296ab0bfc11 107 }RCC_OscInitTypeDef;
Kojto 109:9296ab0bfc11 108
Kojto 109:9296ab0bfc11 109 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 110
Kojto 109:9296ab0bfc11 111 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 112 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 113 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
Kojto 109:9296ab0bfc11 114 defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 115 /**
Kojto 109:9296ab0bfc11 116 * @brief RCC PLL configuration structure definition
Kojto 109:9296ab0bfc11 117 */
Kojto 109:9296ab0bfc11 118 typedef struct
Kojto 109:9296ab0bfc11 119 {
Kojto 109:9296ab0bfc11 120 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto 109:9296ab0bfc11 121 This parameter can be a value of @ref RCC_PLL_Config */
Kojto 109:9296ab0bfc11 122
Kojto 109:9296ab0bfc11 123 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto 109:9296ab0bfc11 124 This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
Kojto 109:9296ab0bfc11 125
Kojto 109:9296ab0bfc11 126 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto 109:9296ab0bfc11 127 This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto 109:9296ab0bfc11 128
Kojto 109:9296ab0bfc11 129 }RCC_PLLInitTypeDef;
Kojto 109:9296ab0bfc11 130
Kojto 109:9296ab0bfc11 131 /**
Kojto 109:9296ab0bfc11 132 * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto 109:9296ab0bfc11 133 */
Kojto 109:9296ab0bfc11 134 typedef struct
Kojto 109:9296ab0bfc11 135 {
Kojto 109:9296ab0bfc11 136 uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto 109:9296ab0bfc11 137 This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto 109:9296ab0bfc11 138
Kojto 109:9296ab0bfc11 139 uint32_t HSEState; /*!< The new state of the HSE.
Kojto 109:9296ab0bfc11 140 This parameter can be a value of @ref RCC_HSE_Config */
Kojto 109:9296ab0bfc11 141
Kojto 109:9296ab0bfc11 142 uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
Kojto 109:9296ab0bfc11 143 This parameter can be a value of @ref RCCEx_HSE_Predivision_Factor */
Kojto 109:9296ab0bfc11 144
Kojto 109:9296ab0bfc11 145 uint32_t LSEState; /*!< The new state of the LSE.
Kojto 109:9296ab0bfc11 146 This parameter can be a value of @ref RCC_LSE_Config */
Kojto 109:9296ab0bfc11 147
Kojto 109:9296ab0bfc11 148 uint32_t HSIState; /*!< The new state of the HSI.
Kojto 109:9296ab0bfc11 149 This parameter can be a value of @ref RCC_HSI_Config */
Kojto 109:9296ab0bfc11 150
Kojto 109:9296ab0bfc11 151 uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto 109:9296ab0bfc11 152 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto 109:9296ab0bfc11 153
Kojto 109:9296ab0bfc11 154 uint32_t LSIState; /*!< The new state of the LSI.
Kojto 109:9296ab0bfc11 155 This parameter can be a value of @ref RCC_LSI_Config */
Kojto 109:9296ab0bfc11 156
Kojto 109:9296ab0bfc11 157 RCC_PLLInitTypeDef PLL; /*!< PLL structure parameters */
Kojto 109:9296ab0bfc11 158
Kojto 109:9296ab0bfc11 159 }RCC_OscInitTypeDef;
Kojto 109:9296ab0bfc11 160 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 161 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 162 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 163 /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 164
Kojto 109:9296ab0bfc11 165 /**
Kojto 109:9296ab0bfc11 166 * @brief RCC extended clocks structure definition
Kojto 109:9296ab0bfc11 167 */
Kojto 109:9296ab0bfc11 168 #if defined(STM32F301x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 169 typedef struct
Kojto 109:9296ab0bfc11 170 {
Kojto 109:9296ab0bfc11 171 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 172 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 173
Kojto 109:9296ab0bfc11 174 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 175 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 176
Kojto 109:9296ab0bfc11 177 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 178 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 179
Kojto 109:9296ab0bfc11 180 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 181 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 182
Kojto 109:9296ab0bfc11 183 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 184 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 185
Kojto 109:9296ab0bfc11 186 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 187 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 188
Kojto 109:9296ab0bfc11 189 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 190 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 191
Kojto 109:9296ab0bfc11 192 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto 109:9296ab0bfc11 193 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 109:9296ab0bfc11 194
Kojto 109:9296ab0bfc11 195 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto 109:9296ab0bfc11 196 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto 109:9296ab0bfc11 197
Kojto 109:9296ab0bfc11 198 uint32_t I2sClockSelection; /*!< I2S clock source
Kojto 109:9296ab0bfc11 199 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 109:9296ab0bfc11 200
Kojto 109:9296ab0bfc11 201 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 202 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 203
Kojto 109:9296ab0bfc11 204 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto 109:9296ab0bfc11 205 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto 109:9296ab0bfc11 206
Kojto 109:9296ab0bfc11 207 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto 109:9296ab0bfc11 208 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto 109:9296ab0bfc11 209
Kojto 109:9296ab0bfc11 210 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto 109:9296ab0bfc11 211 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto 109:9296ab0bfc11 212 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 213 #endif /* STM32F301x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 214
Kojto 109:9296ab0bfc11 215 #if defined(STM32F302x8)
Kojto 109:9296ab0bfc11 216 typedef struct
Kojto 109:9296ab0bfc11 217 {
Kojto 109:9296ab0bfc11 218 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 219 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 220
Kojto 109:9296ab0bfc11 221 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 222 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 223
Kojto 109:9296ab0bfc11 224 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 225 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 226
Kojto 109:9296ab0bfc11 227 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 228 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 229
Kojto 109:9296ab0bfc11 230 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 231 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 232
Kojto 109:9296ab0bfc11 233 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 234 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 235
Kojto 109:9296ab0bfc11 236 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 237 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 238
Kojto 109:9296ab0bfc11 239 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto 109:9296ab0bfc11 240 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 109:9296ab0bfc11 241
Kojto 109:9296ab0bfc11 242 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto 109:9296ab0bfc11 243 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto 109:9296ab0bfc11 244
Kojto 109:9296ab0bfc11 245 uint32_t I2sClockSelection; /*!< I2S clock source
Kojto 109:9296ab0bfc11 246 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 109:9296ab0bfc11 247
Kojto 109:9296ab0bfc11 248 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 249 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 250
Kojto 109:9296ab0bfc11 251 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto 109:9296ab0bfc11 252 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto 109:9296ab0bfc11 253
Kojto 109:9296ab0bfc11 254 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto 109:9296ab0bfc11 255 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto 109:9296ab0bfc11 256
Kojto 109:9296ab0bfc11 257 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto 109:9296ab0bfc11 258 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto 109:9296ab0bfc11 259
Kojto 109:9296ab0bfc11 260 uint32_t USBClockSelection; /*!< USB clock source
Kojto 109:9296ab0bfc11 261 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 109:9296ab0bfc11 262
Kojto 109:9296ab0bfc11 263 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 264 #endif /* STM32F302x8 */
Kojto 109:9296ab0bfc11 265
Kojto 109:9296ab0bfc11 266 #if defined(STM32F302xC)
Kojto 109:9296ab0bfc11 267 typedef struct
Kojto 109:9296ab0bfc11 268 {
Kojto 109:9296ab0bfc11 269 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 270 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 271
Kojto 109:9296ab0bfc11 272 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 273 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 274
Kojto 109:9296ab0bfc11 275 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 276 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 277
Kojto 109:9296ab0bfc11 278 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 279 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 280
Kojto 109:9296ab0bfc11 281 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 282 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 283
Kojto 109:9296ab0bfc11 284 uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto 109:9296ab0bfc11 285 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 109:9296ab0bfc11 286
Kojto 109:9296ab0bfc11 287 uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto 109:9296ab0bfc11 288 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 109:9296ab0bfc11 289
Kojto 109:9296ab0bfc11 290 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 291 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 292
Kojto 109:9296ab0bfc11 293 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 294 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 295
Kojto 109:9296ab0bfc11 296 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto 109:9296ab0bfc11 297 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto 109:9296ab0bfc11 298
Kojto 109:9296ab0bfc11 299 uint32_t I2sClockSelection; /*!< I2S clock source
Kojto 109:9296ab0bfc11 300 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 109:9296ab0bfc11 301
Kojto 109:9296ab0bfc11 302 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 303 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 304
Kojto 109:9296ab0bfc11 305 uint32_t USBClockSelection; /*!< USB clock source
Kojto 109:9296ab0bfc11 306 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 109:9296ab0bfc11 307
Kojto 109:9296ab0bfc11 308 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 309 #endif /* STM32F302xC */
Kojto 109:9296ab0bfc11 310
Kojto 109:9296ab0bfc11 311 #if defined(STM32F303xC)
Kojto 109:9296ab0bfc11 312 typedef struct
Kojto 109:9296ab0bfc11 313 {
Kojto 109:9296ab0bfc11 314 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 315 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 316
Kojto 109:9296ab0bfc11 317 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 318 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 319
Kojto 109:9296ab0bfc11 320 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 321 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 322
Kojto 109:9296ab0bfc11 323 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 324 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 325
Kojto 109:9296ab0bfc11 326 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 327 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 328
Kojto 109:9296ab0bfc11 329 uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto 109:9296ab0bfc11 330 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 109:9296ab0bfc11 331
Kojto 109:9296ab0bfc11 332 uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto 109:9296ab0bfc11 333 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 109:9296ab0bfc11 334
Kojto 109:9296ab0bfc11 335 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 336 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 337
Kojto 109:9296ab0bfc11 338 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 339 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 340
Kojto 109:9296ab0bfc11 341 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto 109:9296ab0bfc11 342 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto 109:9296ab0bfc11 343
Kojto 109:9296ab0bfc11 344 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto 109:9296ab0bfc11 345 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto 109:9296ab0bfc11 346
Kojto 109:9296ab0bfc11 347 uint32_t I2sClockSelection; /*!< I2S clock source
Kojto 109:9296ab0bfc11 348 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 109:9296ab0bfc11 349
Kojto 109:9296ab0bfc11 350 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 351 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 352
Kojto 109:9296ab0bfc11 353 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto 109:9296ab0bfc11 354 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto 109:9296ab0bfc11 355
Kojto 109:9296ab0bfc11 356 uint32_t USBClockSelection; /*!< USB clock source
Kojto 109:9296ab0bfc11 357 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 109:9296ab0bfc11 358
Kojto 109:9296ab0bfc11 359 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 360 #endif /* STM32F303xC */
Kojto 109:9296ab0bfc11 361
Kojto 109:9296ab0bfc11 362 #if defined(STM32F302xE)
Kojto 109:9296ab0bfc11 363 typedef struct
Kojto 109:9296ab0bfc11 364 {
Kojto 109:9296ab0bfc11 365 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 366 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 367
Kojto 109:9296ab0bfc11 368 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 369 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 370
Kojto 109:9296ab0bfc11 371 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 372 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 373
Kojto 109:9296ab0bfc11 374 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 375 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 376
Kojto 109:9296ab0bfc11 377 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 378 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 379
Kojto 109:9296ab0bfc11 380 uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto 109:9296ab0bfc11 381 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 109:9296ab0bfc11 382
Kojto 109:9296ab0bfc11 383 uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto 109:9296ab0bfc11 384 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 109:9296ab0bfc11 385
Kojto 109:9296ab0bfc11 386 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 387 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 388
Kojto 109:9296ab0bfc11 389 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 390 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 391
Kojto 109:9296ab0bfc11 392 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto 109:9296ab0bfc11 393 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 109:9296ab0bfc11 394
Kojto 109:9296ab0bfc11 395 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto 109:9296ab0bfc11 396 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto 109:9296ab0bfc11 397
Kojto 109:9296ab0bfc11 398 uint32_t I2sClockSelection; /*!< I2S clock source
Kojto 109:9296ab0bfc11 399 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 109:9296ab0bfc11 400
Kojto 109:9296ab0bfc11 401 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 402 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 403
Kojto 109:9296ab0bfc11 404 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
Kojto 109:9296ab0bfc11 405 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
Kojto 109:9296ab0bfc11 406
Kojto 109:9296ab0bfc11 407 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
Kojto 109:9296ab0bfc11 408 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
Kojto 109:9296ab0bfc11 409
Kojto 109:9296ab0bfc11 410 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto 109:9296ab0bfc11 411 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto 109:9296ab0bfc11 412
Kojto 109:9296ab0bfc11 413 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto 109:9296ab0bfc11 414 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto 109:9296ab0bfc11 415
Kojto 109:9296ab0bfc11 416 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto 109:9296ab0bfc11 417 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto 109:9296ab0bfc11 418
Kojto 109:9296ab0bfc11 419 uint32_t USBClockSelection; /*!< USB clock source
Kojto 109:9296ab0bfc11 420 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 109:9296ab0bfc11 421
Kojto 109:9296ab0bfc11 422 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 423 #endif /* STM32F302xE */
Kojto 109:9296ab0bfc11 424
Kojto 109:9296ab0bfc11 425 #if defined(STM32F303xE)
Kojto 109:9296ab0bfc11 426 typedef struct
Kojto 109:9296ab0bfc11 427 {
Kojto 109:9296ab0bfc11 428 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 429 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 430
Kojto 109:9296ab0bfc11 431 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 432 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 433
Kojto 109:9296ab0bfc11 434 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 435 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 436
Kojto 109:9296ab0bfc11 437 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 438 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 439
Kojto 109:9296ab0bfc11 440 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 441 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 442
Kojto 109:9296ab0bfc11 443 uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto 109:9296ab0bfc11 444 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 109:9296ab0bfc11 445
Kojto 109:9296ab0bfc11 446 uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto 109:9296ab0bfc11 447 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 109:9296ab0bfc11 448
Kojto 109:9296ab0bfc11 449 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 450 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 451
Kojto 109:9296ab0bfc11 452 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 453 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 454
Kojto 109:9296ab0bfc11 455 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto 109:9296ab0bfc11 456 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 109:9296ab0bfc11 457
Kojto 109:9296ab0bfc11 458 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto 109:9296ab0bfc11 459 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto 109:9296ab0bfc11 460
Kojto 109:9296ab0bfc11 461 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto 109:9296ab0bfc11 462 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto 109:9296ab0bfc11 463
Kojto 109:9296ab0bfc11 464 uint32_t I2sClockSelection; /*!< I2S clock source
Kojto 109:9296ab0bfc11 465 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 109:9296ab0bfc11 466
Kojto 109:9296ab0bfc11 467 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 468 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 469
Kojto 109:9296ab0bfc11 470 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
Kojto 109:9296ab0bfc11 471 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
Kojto 109:9296ab0bfc11 472
Kojto 109:9296ab0bfc11 473 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
Kojto 109:9296ab0bfc11 474 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
Kojto 109:9296ab0bfc11 475
Kojto 109:9296ab0bfc11 476 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto 109:9296ab0bfc11 477 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto 109:9296ab0bfc11 478
Kojto 109:9296ab0bfc11 479 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto 109:9296ab0bfc11 480 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto 109:9296ab0bfc11 481
Kojto 109:9296ab0bfc11 482 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto 109:9296ab0bfc11 483 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto 109:9296ab0bfc11 484
Kojto 109:9296ab0bfc11 485 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto 109:9296ab0bfc11 486 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto 109:9296ab0bfc11 487
Kojto 109:9296ab0bfc11 488 uint32_t Tim20ClockSelection; /*!< TIM20 clock source
Kojto 109:9296ab0bfc11 489 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
Kojto 109:9296ab0bfc11 490
Kojto 109:9296ab0bfc11 491 uint32_t USBClockSelection; /*!< USB clock source
Kojto 109:9296ab0bfc11 492 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 109:9296ab0bfc11 493
Kojto 109:9296ab0bfc11 494 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 495 #endif /* STM32F303xE */
Kojto 109:9296ab0bfc11 496
Kojto 109:9296ab0bfc11 497 #if defined(STM32F398xx)
Kojto 109:9296ab0bfc11 498 typedef struct
Kojto 109:9296ab0bfc11 499 {
Kojto 109:9296ab0bfc11 500 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 501 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 502
Kojto 109:9296ab0bfc11 503 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 504 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 505
Kojto 109:9296ab0bfc11 506 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 507 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 508
Kojto 109:9296ab0bfc11 509 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 510 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 511
Kojto 109:9296ab0bfc11 512 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 513 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 514
Kojto 109:9296ab0bfc11 515 uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto 109:9296ab0bfc11 516 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 109:9296ab0bfc11 517
Kojto 109:9296ab0bfc11 518 uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto 109:9296ab0bfc11 519 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 109:9296ab0bfc11 520
Kojto 109:9296ab0bfc11 521 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 522 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 523
Kojto 109:9296ab0bfc11 524 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 525 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 526
Kojto 109:9296ab0bfc11 527 uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto 109:9296ab0bfc11 528 This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto 109:9296ab0bfc11 529
Kojto 109:9296ab0bfc11 530 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto 109:9296ab0bfc11 531 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto 109:9296ab0bfc11 532
Kojto 109:9296ab0bfc11 533 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto 109:9296ab0bfc11 534 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto 109:9296ab0bfc11 535
Kojto 109:9296ab0bfc11 536 uint32_t I2sClockSelection; /*!< I2S clock source
Kojto 109:9296ab0bfc11 537 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 109:9296ab0bfc11 538
Kojto 109:9296ab0bfc11 539 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 540 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 541
Kojto 109:9296ab0bfc11 542 uint32_t Tim2ClockSelection; /*!< TIM2 clock source
Kojto 109:9296ab0bfc11 543 This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
Kojto 109:9296ab0bfc11 544
Kojto 109:9296ab0bfc11 545 uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
Kojto 109:9296ab0bfc11 546 This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
Kojto 109:9296ab0bfc11 547
Kojto 109:9296ab0bfc11 548 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto 109:9296ab0bfc11 549 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto 109:9296ab0bfc11 550
Kojto 109:9296ab0bfc11 551 uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto 109:9296ab0bfc11 552 This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto 109:9296ab0bfc11 553
Kojto 109:9296ab0bfc11 554 uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto 109:9296ab0bfc11 555 This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto 109:9296ab0bfc11 556
Kojto 109:9296ab0bfc11 557 uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto 109:9296ab0bfc11 558 This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto 109:9296ab0bfc11 559
Kojto 109:9296ab0bfc11 560 uint32_t Tim20ClockSelection; /*!< TIM20 clock source
Kojto 109:9296ab0bfc11 561 This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
Kojto 109:9296ab0bfc11 562
Kojto 109:9296ab0bfc11 563 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 564 #endif /* STM32F398xx */
Kojto 109:9296ab0bfc11 565
Kojto 109:9296ab0bfc11 566 #if defined(STM32F358xx)
Kojto 109:9296ab0bfc11 567 typedef struct
Kojto 109:9296ab0bfc11 568 {
Kojto 109:9296ab0bfc11 569 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 570 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 571
Kojto 109:9296ab0bfc11 572 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 573 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 574
Kojto 109:9296ab0bfc11 575 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 576 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 577
Kojto 109:9296ab0bfc11 578 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 579 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 580
Kojto 109:9296ab0bfc11 581 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 582 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 583
Kojto 109:9296ab0bfc11 584 uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto 109:9296ab0bfc11 585 This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto 109:9296ab0bfc11 586
Kojto 109:9296ab0bfc11 587 uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto 109:9296ab0bfc11 588 This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto 109:9296ab0bfc11 589
Kojto 109:9296ab0bfc11 590 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 591 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 592
Kojto 109:9296ab0bfc11 593 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 594 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 595
Kojto 109:9296ab0bfc11 596 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto 109:9296ab0bfc11 597 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto 109:9296ab0bfc11 598
Kojto 109:9296ab0bfc11 599 uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto 109:9296ab0bfc11 600 This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto 109:9296ab0bfc11 601
Kojto 109:9296ab0bfc11 602 uint32_t I2sClockSelection; /*!< I2S clock source
Kojto 109:9296ab0bfc11 603 This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto 109:9296ab0bfc11 604
Kojto 109:9296ab0bfc11 605 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 606 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 607
Kojto 109:9296ab0bfc11 608 uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto 109:9296ab0bfc11 609 This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto 109:9296ab0bfc11 610
Kojto 109:9296ab0bfc11 611 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 612 #endif /* STM32F358xx */
Kojto 109:9296ab0bfc11 613
Kojto 109:9296ab0bfc11 614 #if defined(STM32F303x8)
Kojto 109:9296ab0bfc11 615 typedef struct
Kojto 109:9296ab0bfc11 616 {
Kojto 109:9296ab0bfc11 617 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 618 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 619
Kojto 109:9296ab0bfc11 620 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 621 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 622
Kojto 109:9296ab0bfc11 623 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 624 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 625
Kojto 109:9296ab0bfc11 626 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 627 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 628
Kojto 109:9296ab0bfc11 629 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 630 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 631
Kojto 109:9296ab0bfc11 632 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 633 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 634
Kojto 109:9296ab0bfc11 635 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto 109:9296ab0bfc11 636 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto 109:9296ab0bfc11 637
Kojto 109:9296ab0bfc11 638 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 639 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 640
Kojto 109:9296ab0bfc11 641 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 642 #endif /* STM32F303x8 */
Kojto 109:9296ab0bfc11 643
Kojto 109:9296ab0bfc11 644 #if defined(STM32F334x8)
Kojto 109:9296ab0bfc11 645 typedef struct
Kojto 109:9296ab0bfc11 646 {
Kojto 109:9296ab0bfc11 647 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 648 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 649
Kojto 109:9296ab0bfc11 650 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 651 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 652
Kojto 109:9296ab0bfc11 653 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 654 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 655
Kojto 109:9296ab0bfc11 656 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 657 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 658
Kojto 109:9296ab0bfc11 659 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 660 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 661
Kojto 109:9296ab0bfc11 662 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 663 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 664
Kojto 109:9296ab0bfc11 665 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto 109:9296ab0bfc11 666 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto 109:9296ab0bfc11 667
Kojto 109:9296ab0bfc11 668 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 669 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 670
Kojto 109:9296ab0bfc11 671 uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
Kojto 109:9296ab0bfc11 672 This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
Kojto 109:9296ab0bfc11 673
Kojto 109:9296ab0bfc11 674 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 675 #endif /* STM32F334x8 */
Kojto 109:9296ab0bfc11 676
Kojto 109:9296ab0bfc11 677 #if defined(STM32F328xx)
Kojto 109:9296ab0bfc11 678 typedef struct
Kojto 109:9296ab0bfc11 679 {
Kojto 109:9296ab0bfc11 680 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 681 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 682
Kojto 109:9296ab0bfc11 683 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 684 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 685
Kojto 109:9296ab0bfc11 686 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 687 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 688
Kojto 109:9296ab0bfc11 689 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 690 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 691
Kojto 109:9296ab0bfc11 692 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 693 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 694
Kojto 109:9296ab0bfc11 695 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 696 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 697
Kojto 109:9296ab0bfc11 698 uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto 109:9296ab0bfc11 699 This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto 109:9296ab0bfc11 700
Kojto 109:9296ab0bfc11 701 uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto 109:9296ab0bfc11 702 This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto 109:9296ab0bfc11 703
Kojto 109:9296ab0bfc11 704 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 705 #endif /* STM32F328xx */
Kojto 109:9296ab0bfc11 706
Kojto 109:9296ab0bfc11 707 #if defined(STM32F373xC)
Kojto 109:9296ab0bfc11 708 typedef struct
Kojto 109:9296ab0bfc11 709 {
Kojto 109:9296ab0bfc11 710 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 711 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 712
Kojto 109:9296ab0bfc11 713 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 714 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 715
Kojto 109:9296ab0bfc11 716 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 717 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 718
Kojto 109:9296ab0bfc11 719 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 720 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 721
Kojto 109:9296ab0bfc11 722 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 723 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 724
Kojto 109:9296ab0bfc11 725 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 726 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 727
Kojto 109:9296ab0bfc11 728 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 729 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 730
Kojto 109:9296ab0bfc11 731 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto 109:9296ab0bfc11 732 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto 109:9296ab0bfc11 733
Kojto 109:9296ab0bfc11 734 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
Kojto 109:9296ab0bfc11 735 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
Kojto 109:9296ab0bfc11 736
Kojto 109:9296ab0bfc11 737 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 109:9296ab0bfc11 738 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 109:9296ab0bfc11 739
Kojto 109:9296ab0bfc11 740 uint32_t USBClockSelection; /*!< USB clock source
Kojto 109:9296ab0bfc11 741 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 109:9296ab0bfc11 742
Kojto 109:9296ab0bfc11 743 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 744 #endif /* STM32F373xC */
Kojto 109:9296ab0bfc11 745
Kojto 109:9296ab0bfc11 746 #if defined(STM32F378xx)
Kojto 109:9296ab0bfc11 747 typedef struct
Kojto 109:9296ab0bfc11 748 {
Kojto 109:9296ab0bfc11 749 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 109:9296ab0bfc11 750 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 109:9296ab0bfc11 751
Kojto 109:9296ab0bfc11 752 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 109:9296ab0bfc11 753 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 109:9296ab0bfc11 754
Kojto 109:9296ab0bfc11 755 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 109:9296ab0bfc11 756 This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto 109:9296ab0bfc11 757
Kojto 109:9296ab0bfc11 758 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 109:9296ab0bfc11 759 This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto 109:9296ab0bfc11 760
Kojto 109:9296ab0bfc11 761 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 109:9296ab0bfc11 762 This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto 109:9296ab0bfc11 763
Kojto 109:9296ab0bfc11 764 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 109:9296ab0bfc11 765 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 109:9296ab0bfc11 766
Kojto 109:9296ab0bfc11 767 uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto 109:9296ab0bfc11 768 This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto 109:9296ab0bfc11 769
Kojto 109:9296ab0bfc11 770 uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto 109:9296ab0bfc11 771 This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto 109:9296ab0bfc11 772
Kojto 109:9296ab0bfc11 773 uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
Kojto 109:9296ab0bfc11 774 This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
Kojto 109:9296ab0bfc11 775
Kojto 109:9296ab0bfc11 776 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 109:9296ab0bfc11 777 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 109:9296ab0bfc11 778
Kojto 109:9296ab0bfc11 779 }RCC_PeriphCLKInitTypeDef;
Kojto 109:9296ab0bfc11 780 #endif /* STM32F378xx */
Kojto 109:9296ab0bfc11 781
Kojto 109:9296ab0bfc11 782 /**
Kojto 109:9296ab0bfc11 783 * @}
Kojto 109:9296ab0bfc11 784 */
Kojto 109:9296ab0bfc11 785
Kojto 109:9296ab0bfc11 786 /* Exported constants --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 787 /** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
Kojto 109:9296ab0bfc11 788 * @{
Kojto 109:9296ab0bfc11 789 */
Kojto 109:9296ab0bfc11 790 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 791 defined(STM32F334x8) || \
Kojto 109:9296ab0bfc11 792 defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 793 /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
Kojto 109:9296ab0bfc11 794 * @{
Kojto 109:9296ab0bfc11 795 */
Kojto 109:9296ab0bfc11 796 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
Kojto 109:9296ab0bfc11 797 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
Kojto 109:9296ab0bfc11 798 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
Kojto 109:9296ab0bfc11 799 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 109:9296ab0bfc11 800 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
Kojto 109:9296ab0bfc11 801 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
Kojto 109:9296ab0bfc11 802 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto 109:9296ab0bfc11 803
Kojto 109:9296ab0bfc11 804 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
Kojto 109:9296ab0bfc11 805 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
Kojto 109:9296ab0bfc11 806 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 807 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 808 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 809 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
Kojto 109:9296ab0bfc11 810 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
Kojto 109:9296ab0bfc11 811 /**
Kojto 109:9296ab0bfc11 812 * @}
Kojto 109:9296ab0bfc11 813 */
Kojto 109:9296ab0bfc11 814 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 815 /* STM32F334x8 */
Kojto 109:9296ab0bfc11 816 /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 817
Kojto 109:9296ab0bfc11 818 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 819 defined(STM32F303x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 820 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 821 /** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
Kojto 109:9296ab0bfc11 822 * @{
Kojto 109:9296ab0bfc11 823 */
Kojto 109:9296ab0bfc11 824 #define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
Kojto 109:9296ab0bfc11 825 #define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
Kojto 109:9296ab0bfc11 826 #define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
Kojto 109:9296ab0bfc11 827 #define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto 109:9296ab0bfc11 828 #define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
Kojto 109:9296ab0bfc11 829 #define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
Kojto 109:9296ab0bfc11 830 #define RCC_MCOSOURCE_PLLCLK_DIV1 (RCC_CFGR_PLLNODIV | RCC_CFGR_MCO_PLL)
Kojto 109:9296ab0bfc11 831 #define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto 109:9296ab0bfc11 832
Kojto 109:9296ab0bfc11 833 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
Kojto 109:9296ab0bfc11 834 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
Kojto 109:9296ab0bfc11 835 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 836 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 837 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 838 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
Kojto 109:9296ab0bfc11 839 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV1) || \
Kojto 109:9296ab0bfc11 840 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
Kojto 109:9296ab0bfc11 841 /**
Kojto 109:9296ab0bfc11 842 * @}
Kojto 109:9296ab0bfc11 843 */
Kojto 109:9296ab0bfc11 844 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 845 /* STM32F303x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 846 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 847
Kojto 109:9296ab0bfc11 848 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 849 /** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
Kojto 109:9296ab0bfc11 850 * @{
Kojto 109:9296ab0bfc11 851 */
Kojto 109:9296ab0bfc11 852 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto 109:9296ab0bfc11 853 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
Kojto 109:9296ab0bfc11 854
Kojto 109:9296ab0bfc11 855 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 856 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 109:9296ab0bfc11 857 /**
Kojto 109:9296ab0bfc11 858 * @}
Kojto 109:9296ab0bfc11 859 */
Kojto 109:9296ab0bfc11 860
Kojto 109:9296ab0bfc11 861 /** @defgroup RCCEx_PLL_Prediv_Factor RCC Extended PLL Prediv Factor
Kojto 109:9296ab0bfc11 862 * @{
Kojto 109:9296ab0bfc11 863 */
Kojto 109:9296ab0bfc11 864 #define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto 109:9296ab0bfc11 865 #define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto 109:9296ab0bfc11 866 #define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto 109:9296ab0bfc11 867 #define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto 109:9296ab0bfc11 868 #define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto 109:9296ab0bfc11 869 #define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto 109:9296ab0bfc11 870 #define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto 109:9296ab0bfc11 871 #define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto 109:9296ab0bfc11 872 #define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto 109:9296ab0bfc11 873 #define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto 109:9296ab0bfc11 874 #define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto 109:9296ab0bfc11 875 #define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto 109:9296ab0bfc11 876 #define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto 109:9296ab0bfc11 877 #define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto 109:9296ab0bfc11 878 #define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto 109:9296ab0bfc11 879 #define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto 109:9296ab0bfc11 880
Kojto 109:9296ab0bfc11 881 #define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) || ((PREDIV) == RCC_PREDIV_DIV2) || \
Kojto 109:9296ab0bfc11 882 ((PREDIV) == RCC_PREDIV_DIV3) || ((PREDIV) == RCC_PREDIV_DIV4) || \
Kojto 109:9296ab0bfc11 883 ((PREDIV) == RCC_PREDIV_DIV5) || ((PREDIV) == RCC_PREDIV_DIV6) || \
Kojto 109:9296ab0bfc11 884 ((PREDIV) == RCC_PREDIV_DIV7) || ((PREDIV) == RCC_PREDIV_DIV8) || \
Kojto 109:9296ab0bfc11 885 ((PREDIV) == RCC_PREDIV_DIV9) || ((PREDIV) == RCC_PREDIV_DIV10) || \
Kojto 109:9296ab0bfc11 886 ((PREDIV) == RCC_PREDIV_DIV11) || ((PREDIV) == RCC_PREDIV_DIV12) || \
Kojto 109:9296ab0bfc11 887 ((PREDIV) == RCC_PREDIV_DIV13) || ((PREDIV) == RCC_PREDIV_DIV14) || \
Kojto 109:9296ab0bfc11 888 ((PREDIV) == RCC_PREDIV_DIV15) || ((PREDIV) == RCC_PREDIV_DIV16))
Kojto 109:9296ab0bfc11 889 /**
Kojto 109:9296ab0bfc11 890 * @}
Kojto 109:9296ab0bfc11 891 */
Kojto 109:9296ab0bfc11 892 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 893
Kojto 109:9296ab0bfc11 894 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 895 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 896 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
Kojto 109:9296ab0bfc11 897 defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 898 /** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
Kojto 109:9296ab0bfc11 899 * @{
Kojto 109:9296ab0bfc11 900 */
Kojto 109:9296ab0bfc11 901 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto 109:9296ab0bfc11 902 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
Kojto 109:9296ab0bfc11 903
Kojto 109:9296ab0bfc11 904 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 905 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 109:9296ab0bfc11 906 /**
Kojto 109:9296ab0bfc11 907 * @}
Kojto 109:9296ab0bfc11 908 */
Kojto 109:9296ab0bfc11 909
Kojto 109:9296ab0bfc11 910 /** @defgroup RCCEx_HSE_Predivision_Factor RCC Extended HSE Predivision Factor
Kojto 109:9296ab0bfc11 911 * @{
Kojto 109:9296ab0bfc11 912 */
Kojto 109:9296ab0bfc11 913
Kojto 109:9296ab0bfc11 914 #define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto 109:9296ab0bfc11 915 #define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto 109:9296ab0bfc11 916 #define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto 109:9296ab0bfc11 917 #define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto 109:9296ab0bfc11 918 #define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto 109:9296ab0bfc11 919 #define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto 109:9296ab0bfc11 920 #define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto 109:9296ab0bfc11 921 #define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto 109:9296ab0bfc11 922 #define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto 109:9296ab0bfc11 923 #define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto 109:9296ab0bfc11 924 #define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto 109:9296ab0bfc11 925 #define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto 109:9296ab0bfc11 926 #define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto 109:9296ab0bfc11 927 #define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto 109:9296ab0bfc11 928 #define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto 109:9296ab0bfc11 929 #define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto 109:9296ab0bfc11 930
Kojto 109:9296ab0bfc11 931 #define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) || ((DIV) == RCC_HSE_PREDIV_DIV2) || \
Kojto 109:9296ab0bfc11 932 ((DIV) == RCC_HSE_PREDIV_DIV3) || ((DIV) == RCC_HSE_PREDIV_DIV4) || \
Kojto 109:9296ab0bfc11 933 ((DIV) == RCC_HSE_PREDIV_DIV5) || ((DIV) == RCC_HSE_PREDIV_DIV6) || \
Kojto 109:9296ab0bfc11 934 ((DIV) == RCC_HSE_PREDIV_DIV7) || ((DIV) == RCC_HSE_PREDIV_DIV8) || \
Kojto 109:9296ab0bfc11 935 ((DIV) == RCC_HSE_PREDIV_DIV9) || ((DIV) == RCC_HSE_PREDIV_DIV10) || \
Kojto 109:9296ab0bfc11 936 ((DIV) == RCC_HSE_PREDIV_DIV11) || ((DIV) == RCC_HSE_PREDIV_DIV12) || \
Kojto 109:9296ab0bfc11 937 ((DIV) == RCC_HSE_PREDIV_DIV13) || ((DIV) == RCC_HSE_PREDIV_DIV14) || \
Kojto 109:9296ab0bfc11 938 ((DIV) == RCC_HSE_PREDIV_DIV15) || ((DIV) == RCC_HSE_PREDIV_DIV16))
Kojto 109:9296ab0bfc11 939 /**
Kojto 109:9296ab0bfc11 940 * @}
Kojto 109:9296ab0bfc11 941 */
Kojto 109:9296ab0bfc11 942 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 943 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 944 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 945 /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 946
Kojto 109:9296ab0bfc11 947 /** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
Kojto 109:9296ab0bfc11 948 * @{
Kojto 109:9296ab0bfc11 949 */
Kojto 109:9296ab0bfc11 950 #if defined(STM32F301x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 951 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 952 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 953 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 954 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 955 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 956 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 957 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 958 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 959 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 960 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 961 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 962 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 963 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 964
Kojto 109:9296ab0bfc11 965 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 966 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 967 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
Kojto 109:9296ab0bfc11 968 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
Kojto 109:9296ab0bfc11 969 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
Kojto 109:9296ab0bfc11 970 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_RTC))
Kojto 109:9296ab0bfc11 971 #endif /* STM32F301x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 972
Kojto 109:9296ab0bfc11 973 #if defined(STM32F302x8)
Kojto 109:9296ab0bfc11 974 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 975 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 976 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 977 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 978 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 979 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 980 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 981 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 982 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 983 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 984 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 985 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 986 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 987 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 988
Kojto 109:9296ab0bfc11 989 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 990 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 991 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_I2S | \
Kojto 109:9296ab0bfc11 992 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM1 | \
Kojto 109:9296ab0bfc11 993 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB | \
Kojto 109:9296ab0bfc11 994 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
Kojto 109:9296ab0bfc11 995 RCC_PERIPHCLK_TIM17))
Kojto 109:9296ab0bfc11 996 #endif /* STM32F302x8 */
Kojto 109:9296ab0bfc11 997
Kojto 109:9296ab0bfc11 998 #if defined(STM32F302xC)
Kojto 109:9296ab0bfc11 999 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1000 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1001 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1002 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1003 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1004 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1005 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1006 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1007 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1008 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1009 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1010 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1011
Kojto 109:9296ab0bfc11 1012 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1013 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 109:9296ab0bfc11 1014 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 1015 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
Kojto 109:9296ab0bfc11 1016 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
Kojto 109:9296ab0bfc11 1017 RCC_PERIPHCLK_USB))
Kojto 109:9296ab0bfc11 1018 #endif /* STM32F302xC */
Kojto 109:9296ab0bfc11 1019
Kojto 109:9296ab0bfc11 1020 #if defined(STM32F303xC)
Kojto 109:9296ab0bfc11 1021 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1022 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1023 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1024 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1025 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1026 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1027 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1028 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1029 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1030 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1031 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1032 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1033 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1034 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1035
Kojto 109:9296ab0bfc11 1036 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1037 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 109:9296ab0bfc11 1038 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 1039 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
Kojto 109:9296ab0bfc11 1040 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
Kojto 109:9296ab0bfc11 1041 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
Kojto 109:9296ab0bfc11 1042 RCC_PERIPHCLK_USB))
Kojto 109:9296ab0bfc11 1043 #endif /* STM32F303xC */
Kojto 109:9296ab0bfc11 1044
Kojto 109:9296ab0bfc11 1045 #if defined(STM32F302xE)
Kojto 109:9296ab0bfc11 1046 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1047 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1048 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1049 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1050 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1051 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1052 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1053 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1054 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1055 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1056 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1057 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1058 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1059 #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1060 #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1061 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1062 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 1063 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 1064
Kojto 109:9296ab0bfc11 1065 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1066 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 109:9296ab0bfc11 1067 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 1068 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_I2S | \
Kojto 109:9296ab0bfc11 1069 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC | \
Kojto 109:9296ab0bfc11 1070 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
Kojto 109:9296ab0bfc11 1071 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
Kojto 109:9296ab0bfc11 1072 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
Kojto 109:9296ab0bfc11 1073 RCC_PERIPHCLK_TIM17))
Kojto 109:9296ab0bfc11 1074 #endif /* STM32F302xE */
Kojto 109:9296ab0bfc11 1075
Kojto 109:9296ab0bfc11 1076 #if defined(STM32F303xE)
Kojto 109:9296ab0bfc11 1077 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1078 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1079 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1080 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1081 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1082 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1083 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1084 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1085 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1086 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1087 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1088 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1089 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1090 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1091 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1092 #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1093 #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1094 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1095 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 1096 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 1097 #define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 1098
Kojto 109:9296ab0bfc11 1099 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1100 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 109:9296ab0bfc11 1101 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 1102 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
Kojto 109:9296ab0bfc11 1103 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
Kojto 109:9296ab0bfc11 1104 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
Kojto 109:9296ab0bfc11 1105 RCC_PERIPHCLK_USB | RCC_PERIPHCLK_I2C3 | \
Kojto 109:9296ab0bfc11 1106 RCC_PERIPHCLK_TIM2 | RCC_PERIPHCLK_TIM34 | \
Kojto 109:9296ab0bfc11 1107 RCC_PERIPHCLK_TIM15 | RCC_PERIPHCLK_TIM16 | \
Kojto 109:9296ab0bfc11 1108 RCC_PERIPHCLK_TIM17 | RCC_PERIPHCLK_TIM20))
Kojto 109:9296ab0bfc11 1109 #endif /* STM32F303xE */
Kojto 109:9296ab0bfc11 1110
Kojto 109:9296ab0bfc11 1111 #if defined(STM32F398xx)
Kojto 109:9296ab0bfc11 1112 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1113 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1114 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1115 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1116 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1117 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1118 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1119 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1120 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1121 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1122 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1123 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1124 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1125 #define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1126 #define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1127 #define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1128 #define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1129 #define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 1130 #define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 1131 #define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 1132
Kojto 109:9296ab0bfc11 1133 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1134 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 109:9296ab0bfc11 1135 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 1136 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
Kojto 109:9296ab0bfc11 1137 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
Kojto 109:9296ab0bfc11 1138 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC | \
Kojto 109:9296ab0bfc11 1139 RCC_PERIPHCLK_I2C3 | RCC_PERIPHCLK_TIM2 | \
Kojto 109:9296ab0bfc11 1140 RCC_PERIPHCLK_TIM34 | RCC_PERIPHCLK_TIM15 | \
Kojto 109:9296ab0bfc11 1141 RCC_PERIPHCLK_TIM16 | RCC_PERIPHCLK_TIM17 | \
Kojto 109:9296ab0bfc11 1142 RCC_PERIPHCLK_TIM20))
Kojto 109:9296ab0bfc11 1143 #endif /* STM32F398xx */
Kojto 109:9296ab0bfc11 1144
Kojto 109:9296ab0bfc11 1145 #if defined(STM32F358xx)
Kojto 109:9296ab0bfc11 1146 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1147 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1148 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1149 #define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1150 #define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1151 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1152 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1153 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1154 #define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1155 #define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1156 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1157 #define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1158 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1159
Kojto 109:9296ab0bfc11 1160 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1161 RCC_PERIPHCLK_UART4 | RCC_PERIPHCLK_UART5 | \
Kojto 109:9296ab0bfc11 1162 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 1163 RCC_PERIPHCLK_ADC12 | RCC_PERIPHCLK_ADC34 | \
Kojto 109:9296ab0bfc11 1164 RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_TIM1 | \
Kojto 109:9296ab0bfc11 1165 RCC_PERIPHCLK_TIM8 | RCC_PERIPHCLK_RTC))
Kojto 109:9296ab0bfc11 1166 #endif /* STM32F358xx */
Kojto 109:9296ab0bfc11 1167
Kojto 109:9296ab0bfc11 1168 #if defined(STM32F303x8)
Kojto 109:9296ab0bfc11 1169 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1170 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1171 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1172 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1173 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1174 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1175 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1176
Kojto 109:9296ab0bfc11 1177 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1178 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
Kojto 109:9296ab0bfc11 1179 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
Kojto 109:9296ab0bfc11 1180 #endif /* STM32F303x8 */
Kojto 109:9296ab0bfc11 1181
Kojto 109:9296ab0bfc11 1182 #if defined(STM32F334x8)
Kojto 109:9296ab0bfc11 1183 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1184 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1185 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1186 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1187 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1188 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1189 #define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1190 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1191
Kojto 109:9296ab0bfc11 1192 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1193 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
Kojto 109:9296ab0bfc11 1194 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_HRTIM1 | \
Kojto 109:9296ab0bfc11 1195 RCC_PERIPHCLK_RTC))
Kojto 109:9296ab0bfc11 1196 #endif /* STM32F334x8 */
Kojto 109:9296ab0bfc11 1197
Kojto 109:9296ab0bfc11 1198 #if defined(STM32F328xx)
Kojto 109:9296ab0bfc11 1199 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1200 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1201 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1202 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1203 #define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1204 #define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1205 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1206
Kojto 109:9296ab0bfc11 1207 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1208 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_ADC12 | \
Kojto 109:9296ab0bfc11 1209 RCC_PERIPHCLK_TIM1 | RCC_PERIPHCLK_RTC))
Kojto 109:9296ab0bfc11 1210 #endif /* STM32F328xx */
Kojto 109:9296ab0bfc11 1211
Kojto 109:9296ab0bfc11 1212 #if defined(STM32F373xC)
Kojto 109:9296ab0bfc11 1213 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1214 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1215 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1216 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1217 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1218 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1219 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1220 #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1221 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1222 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1223
Kojto 109:9296ab0bfc11 1224 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1225 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 1226 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
Kojto 109:9296ab0bfc11 1227 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
Kojto 109:9296ab0bfc11 1228 RCC_PERIPHCLK_USB))
Kojto 109:9296ab0bfc11 1229 #endif /* STM32F373xC */
Kojto 109:9296ab0bfc11 1230
Kojto 109:9296ab0bfc11 1231 #if defined(STM32F378xx)
Kojto 109:9296ab0bfc11 1232 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1233 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1234 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1235 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1236 #define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1237 #define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1238 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1239 #define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1240 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1241
Kojto 109:9296ab0bfc11 1242 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | RCC_PERIPHCLK_USART3 | \
Kojto 109:9296ab0bfc11 1243 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_I2C2 | \
Kojto 109:9296ab0bfc11 1244 RCC_PERIPHCLK_ADC1 | RCC_PERIPHCLK_SDADC | \
Kojto 109:9296ab0bfc11 1245 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
Kojto 109:9296ab0bfc11 1246 #endif /* STM32F378xx */
Kojto 109:9296ab0bfc11 1247 /**
Kojto 109:9296ab0bfc11 1248 * @}
Kojto 109:9296ab0bfc11 1249 */
Kojto 109:9296ab0bfc11 1250
Kojto 109:9296ab0bfc11 1251 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 1252
Kojto 109:9296ab0bfc11 1253 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto 109:9296ab0bfc11 1254 * @{
Kojto 109:9296ab0bfc11 1255 */
Kojto 109:9296ab0bfc11 1256 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto 109:9296ab0bfc11 1257 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto 109:9296ab0bfc11 1258 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto 109:9296ab0bfc11 1259 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto 109:9296ab0bfc11 1260
Kojto 109:9296ab0bfc11 1261 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 109:9296ab0bfc11 1262 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1263 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 1264 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 1265 /**
Kojto 109:9296ab0bfc11 1266 * @}
Kojto 109:9296ab0bfc11 1267 */
Kojto 109:9296ab0bfc11 1268
Kojto 109:9296ab0bfc11 1269 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto 109:9296ab0bfc11 1270 * @{
Kojto 109:9296ab0bfc11 1271 */
Kojto 109:9296ab0bfc11 1272 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto 109:9296ab0bfc11 1273 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto 109:9296ab0bfc11 1274
Kojto 109:9296ab0bfc11 1275 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 1276 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto 109:9296ab0bfc11 1277 /**
Kojto 109:9296ab0bfc11 1278 * @}
Kojto 109:9296ab0bfc11 1279 */
Kojto 109:9296ab0bfc11 1280
Kojto 109:9296ab0bfc11 1281 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
Kojto 109:9296ab0bfc11 1282 * @{
Kojto 109:9296ab0bfc11 1283 */
Kojto 109:9296ab0bfc11 1284 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
Kojto 109:9296ab0bfc11 1285 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
Kojto 109:9296ab0bfc11 1286
Kojto 109:9296ab0bfc11 1287 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 1288 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
Kojto 109:9296ab0bfc11 1289 /**
Kojto 109:9296ab0bfc11 1290 * @}
Kojto 109:9296ab0bfc11 1291 */
Kojto 109:9296ab0bfc11 1292
Kojto 109:9296ab0bfc11 1293 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
Kojto 109:9296ab0bfc11 1294 * @{
Kojto 109:9296ab0bfc11 1295 */
Kojto 109:9296ab0bfc11 1296 #define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
Kojto 109:9296ab0bfc11 1297 #define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
Kojto 109:9296ab0bfc11 1298 #define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
Kojto 109:9296ab0bfc11 1299 #define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
Kojto 109:9296ab0bfc11 1300 #define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
Kojto 109:9296ab0bfc11 1301 #define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
Kojto 109:9296ab0bfc11 1302 #define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
Kojto 109:9296ab0bfc11 1303 #define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
Kojto 109:9296ab0bfc11 1304 #define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
Kojto 109:9296ab0bfc11 1305 #define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
Kojto 109:9296ab0bfc11 1306 #define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
Kojto 109:9296ab0bfc11 1307 #define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
Kojto 109:9296ab0bfc11 1308 #define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
Kojto 109:9296ab0bfc11 1309
Kojto 109:9296ab0bfc11 1310 #define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) || \
Kojto 109:9296ab0bfc11 1311 ((ADCCLK) == RCC_ADC1PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) || \
Kojto 109:9296ab0bfc11 1312 ((ADCCLK) == RCC_ADC1PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) || \
Kojto 109:9296ab0bfc11 1313 ((ADCCLK) == RCC_ADC1PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) || \
Kojto 109:9296ab0bfc11 1314 ((ADCCLK) == RCC_ADC1PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) || \
Kojto 109:9296ab0bfc11 1315 ((ADCCLK) == RCC_ADC1PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) || \
Kojto 109:9296ab0bfc11 1316 ((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
Kojto 109:9296ab0bfc11 1317 /**
Kojto 109:9296ab0bfc11 1318 * @}
Kojto 109:9296ab0bfc11 1319 */
Kojto 109:9296ab0bfc11 1320
Kojto 109:9296ab0bfc11 1321 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
Kojto 109:9296ab0bfc11 1322 * @{
Kojto 109:9296ab0bfc11 1323 */
Kojto 109:9296ab0bfc11 1324 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
Kojto 109:9296ab0bfc11 1325 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
Kojto 109:9296ab0bfc11 1326
Kojto 109:9296ab0bfc11 1327 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1328 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto 109:9296ab0bfc11 1329 /**
Kojto 109:9296ab0bfc11 1330 * @}
Kojto 109:9296ab0bfc11 1331 */
Kojto 109:9296ab0bfc11 1332
Kojto 109:9296ab0bfc11 1333 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto 109:9296ab0bfc11 1334 * @{
Kojto 109:9296ab0bfc11 1335 */
Kojto 109:9296ab0bfc11 1336 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto 109:9296ab0bfc11 1337 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto 109:9296ab0bfc11 1338
Kojto 109:9296ab0bfc11 1339 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1340 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1341 /**
Kojto 109:9296ab0bfc11 1342 * @}
Kojto 109:9296ab0bfc11 1343 */
Kojto 109:9296ab0bfc11 1344
Kojto 109:9296ab0bfc11 1345 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
Kojto 109:9296ab0bfc11 1346 * @{
Kojto 109:9296ab0bfc11 1347 */
Kojto 109:9296ab0bfc11 1348 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
Kojto 109:9296ab0bfc11 1349 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
Kojto 109:9296ab0bfc11 1350
Kojto 109:9296ab0bfc11 1351 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1352 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1353 /**
Kojto 109:9296ab0bfc11 1354 * @}
Kojto 109:9296ab0bfc11 1355 */
Kojto 109:9296ab0bfc11 1356
Kojto 109:9296ab0bfc11 1357 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
Kojto 109:9296ab0bfc11 1358 * @{
Kojto 109:9296ab0bfc11 1359 */
Kojto 109:9296ab0bfc11 1360 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
Kojto 109:9296ab0bfc11 1361 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
Kojto 109:9296ab0bfc11 1362
Kojto 109:9296ab0bfc11 1363 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1364 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1365 /**
Kojto 109:9296ab0bfc11 1366 * @}
Kojto 109:9296ab0bfc11 1367 */
Kojto 109:9296ab0bfc11 1368
Kojto 109:9296ab0bfc11 1369 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
Kojto 109:9296ab0bfc11 1370 * @{
Kojto 109:9296ab0bfc11 1371 */
Kojto 109:9296ab0bfc11 1372 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
Kojto 109:9296ab0bfc11 1373 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
Kojto 109:9296ab0bfc11 1374
Kojto 109:9296ab0bfc11 1375 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1376 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1377 /**
Kojto 109:9296ab0bfc11 1378 * @}
Kojto 109:9296ab0bfc11 1379 */
Kojto 109:9296ab0bfc11 1380
Kojto 109:9296ab0bfc11 1381 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 1382
Kojto 109:9296ab0bfc11 1383 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 1384
Kojto 109:9296ab0bfc11 1385 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto 109:9296ab0bfc11 1386 * @{
Kojto 109:9296ab0bfc11 1387 */
Kojto 109:9296ab0bfc11 1388 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto 109:9296ab0bfc11 1389 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto 109:9296ab0bfc11 1390 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto 109:9296ab0bfc11 1391 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto 109:9296ab0bfc11 1392
Kojto 109:9296ab0bfc11 1393 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 109:9296ab0bfc11 1394 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1395 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 1396 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 1397 /**
Kojto 109:9296ab0bfc11 1398 * @}
Kojto 109:9296ab0bfc11 1399 */
Kojto 109:9296ab0bfc11 1400
Kojto 109:9296ab0bfc11 1401 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto 109:9296ab0bfc11 1402 * @{
Kojto 109:9296ab0bfc11 1403 */
Kojto 109:9296ab0bfc11 1404 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto 109:9296ab0bfc11 1405 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto 109:9296ab0bfc11 1406
Kojto 109:9296ab0bfc11 1407 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 1408 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto 109:9296ab0bfc11 1409 /**
Kojto 109:9296ab0bfc11 1410 * @}
Kojto 109:9296ab0bfc11 1411 */
Kojto 109:9296ab0bfc11 1412
Kojto 109:9296ab0bfc11 1413 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
Kojto 109:9296ab0bfc11 1414 * @{
Kojto 109:9296ab0bfc11 1415 */
Kojto 109:9296ab0bfc11 1416
Kojto 109:9296ab0bfc11 1417 /* ADC1 & ADC2 */
Kojto 109:9296ab0bfc11 1418 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
Kojto 109:9296ab0bfc11 1419 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
Kojto 109:9296ab0bfc11 1420 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
Kojto 109:9296ab0bfc11 1421 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
Kojto 109:9296ab0bfc11 1422 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
Kojto 109:9296ab0bfc11 1423 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
Kojto 109:9296ab0bfc11 1424 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
Kojto 109:9296ab0bfc11 1425 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
Kojto 109:9296ab0bfc11 1426 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
Kojto 109:9296ab0bfc11 1427 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
Kojto 109:9296ab0bfc11 1428 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
Kojto 109:9296ab0bfc11 1429 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
Kojto 109:9296ab0bfc11 1430 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
Kojto 109:9296ab0bfc11 1431
Kojto 109:9296ab0bfc11 1432 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
Kojto 109:9296ab0bfc11 1433 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
Kojto 109:9296ab0bfc11 1434 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
Kojto 109:9296ab0bfc11 1435 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
Kojto 109:9296ab0bfc11 1436 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
Kojto 109:9296ab0bfc11 1437 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
Kojto 109:9296ab0bfc11 1438 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto 109:9296ab0bfc11 1439 /**
Kojto 109:9296ab0bfc11 1440 * @}
Kojto 109:9296ab0bfc11 1441 */
Kojto 109:9296ab0bfc11 1442
Kojto 109:9296ab0bfc11 1443 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
Kojto 109:9296ab0bfc11 1444 * @{
Kojto 109:9296ab0bfc11 1445 */
Kojto 109:9296ab0bfc11 1446 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
Kojto 109:9296ab0bfc11 1447 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
Kojto 109:9296ab0bfc11 1448
Kojto 109:9296ab0bfc11 1449 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1450 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto 109:9296ab0bfc11 1451 /**
Kojto 109:9296ab0bfc11 1452 * @}
Kojto 109:9296ab0bfc11 1453 */
Kojto 109:9296ab0bfc11 1454 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto 109:9296ab0bfc11 1455 * @{
Kojto 109:9296ab0bfc11 1456 */
Kojto 109:9296ab0bfc11 1457 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto 109:9296ab0bfc11 1458 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto 109:9296ab0bfc11 1459
Kojto 109:9296ab0bfc11 1460 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1461 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1462 /**
Kojto 109:9296ab0bfc11 1463 * @}
Kojto 109:9296ab0bfc11 1464 */
Kojto 109:9296ab0bfc11 1465
Kojto 109:9296ab0bfc11 1466 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
Kojto 109:9296ab0bfc11 1467 * @{
Kojto 109:9296ab0bfc11 1468 */
Kojto 109:9296ab0bfc11 1469 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
Kojto 109:9296ab0bfc11 1470 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
Kojto 109:9296ab0bfc11 1471 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
Kojto 109:9296ab0bfc11 1472 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
Kojto 109:9296ab0bfc11 1473
Kojto 109:9296ab0bfc11 1474 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
Kojto 109:9296ab0bfc11 1475 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1476 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 1477 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 1478 /**
Kojto 109:9296ab0bfc11 1479 * @}
Kojto 109:9296ab0bfc11 1480 */
Kojto 109:9296ab0bfc11 1481
Kojto 109:9296ab0bfc11 1482 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
Kojto 109:9296ab0bfc11 1483 * @{
Kojto 109:9296ab0bfc11 1484 */
Kojto 109:9296ab0bfc11 1485 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
Kojto 109:9296ab0bfc11 1486 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
Kojto 109:9296ab0bfc11 1487 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
Kojto 109:9296ab0bfc11 1488 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
Kojto 109:9296ab0bfc11 1489
Kojto 109:9296ab0bfc11 1490 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
Kojto 109:9296ab0bfc11 1491 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1492 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 1493 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 1494 /**
Kojto 109:9296ab0bfc11 1495 * @}
Kojto 109:9296ab0bfc11 1496 */
Kojto 109:9296ab0bfc11 1497
Kojto 109:9296ab0bfc11 1498 #endif /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 1499
Kojto 109:9296ab0bfc11 1500 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 1501
Kojto 109:9296ab0bfc11 1502 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto 109:9296ab0bfc11 1503 * @{
Kojto 109:9296ab0bfc11 1504 */
Kojto 109:9296ab0bfc11 1505 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto 109:9296ab0bfc11 1506 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto 109:9296ab0bfc11 1507 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto 109:9296ab0bfc11 1508 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto 109:9296ab0bfc11 1509
Kojto 109:9296ab0bfc11 1510 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 109:9296ab0bfc11 1511 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1512 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 1513 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 1514 /**
Kojto 109:9296ab0bfc11 1515 * @}
Kojto 109:9296ab0bfc11 1516 */
Kojto 109:9296ab0bfc11 1517
Kojto 109:9296ab0bfc11 1518 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto 109:9296ab0bfc11 1519 * @{
Kojto 109:9296ab0bfc11 1520 */
Kojto 109:9296ab0bfc11 1521 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto 109:9296ab0bfc11 1522 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto 109:9296ab0bfc11 1523
Kojto 109:9296ab0bfc11 1524 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 1525 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto 109:9296ab0bfc11 1526 /**
Kojto 109:9296ab0bfc11 1527 * @}
Kojto 109:9296ab0bfc11 1528 */
Kojto 109:9296ab0bfc11 1529
Kojto 109:9296ab0bfc11 1530 /** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
Kojto 109:9296ab0bfc11 1531 * @{
Kojto 109:9296ab0bfc11 1532 */
Kojto 109:9296ab0bfc11 1533 #define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
Kojto 109:9296ab0bfc11 1534 #define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
Kojto 109:9296ab0bfc11 1535
Kojto 109:9296ab0bfc11 1536 #define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 1537 ((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
Kojto 109:9296ab0bfc11 1538 /**
Kojto 109:9296ab0bfc11 1539 * @}
Kojto 109:9296ab0bfc11 1540 */
Kojto 109:9296ab0bfc11 1541
Kojto 109:9296ab0bfc11 1542 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
Kojto 109:9296ab0bfc11 1543 * @{
Kojto 109:9296ab0bfc11 1544 */
Kojto 109:9296ab0bfc11 1545
Kojto 109:9296ab0bfc11 1546 /* ADC1 & ADC2 */
Kojto 109:9296ab0bfc11 1547 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
Kojto 109:9296ab0bfc11 1548 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
Kojto 109:9296ab0bfc11 1549 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
Kojto 109:9296ab0bfc11 1550 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
Kojto 109:9296ab0bfc11 1551 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
Kojto 109:9296ab0bfc11 1552 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
Kojto 109:9296ab0bfc11 1553 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
Kojto 109:9296ab0bfc11 1554 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
Kojto 109:9296ab0bfc11 1555 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
Kojto 109:9296ab0bfc11 1556 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
Kojto 109:9296ab0bfc11 1557 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
Kojto 109:9296ab0bfc11 1558 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
Kojto 109:9296ab0bfc11 1559 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
Kojto 109:9296ab0bfc11 1560
Kojto 109:9296ab0bfc11 1561 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
Kojto 109:9296ab0bfc11 1562 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
Kojto 109:9296ab0bfc11 1563 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
Kojto 109:9296ab0bfc11 1564 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
Kojto 109:9296ab0bfc11 1565 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
Kojto 109:9296ab0bfc11 1566 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
Kojto 109:9296ab0bfc11 1567 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto 109:9296ab0bfc11 1568 /**
Kojto 109:9296ab0bfc11 1569 * @}
Kojto 109:9296ab0bfc11 1570 */
Kojto 109:9296ab0bfc11 1571
Kojto 109:9296ab0bfc11 1572 /** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
Kojto 109:9296ab0bfc11 1573 * @{
Kojto 109:9296ab0bfc11 1574 */
Kojto 109:9296ab0bfc11 1575 #define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
Kojto 109:9296ab0bfc11 1576 #define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
Kojto 109:9296ab0bfc11 1577
Kojto 109:9296ab0bfc11 1578 #define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1579 ((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto 109:9296ab0bfc11 1580 /**
Kojto 109:9296ab0bfc11 1581 * @}
Kojto 109:9296ab0bfc11 1582 */
Kojto 109:9296ab0bfc11 1583
Kojto 109:9296ab0bfc11 1584 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto 109:9296ab0bfc11 1585 * @{
Kojto 109:9296ab0bfc11 1586 */
Kojto 109:9296ab0bfc11 1587 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto 109:9296ab0bfc11 1588 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto 109:9296ab0bfc11 1589
Kojto 109:9296ab0bfc11 1590 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1591 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1592 /**
Kojto 109:9296ab0bfc11 1593 * @}
Kojto 109:9296ab0bfc11 1594 */
Kojto 109:9296ab0bfc11 1595
Kojto 109:9296ab0bfc11 1596 /** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
Kojto 109:9296ab0bfc11 1597 * @{
Kojto 109:9296ab0bfc11 1598 */
Kojto 109:9296ab0bfc11 1599 #define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
Kojto 109:9296ab0bfc11 1600 #define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
Kojto 109:9296ab0bfc11 1601
Kojto 109:9296ab0bfc11 1602 #define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1603 ((SOURCE) == RCC_TIM2CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1604 /**
Kojto 109:9296ab0bfc11 1605 * @}
Kojto 109:9296ab0bfc11 1606 */
Kojto 109:9296ab0bfc11 1607
Kojto 109:9296ab0bfc11 1608 /** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
Kojto 109:9296ab0bfc11 1609 * @{
Kojto 109:9296ab0bfc11 1610 */
Kojto 109:9296ab0bfc11 1611 #define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
Kojto 109:9296ab0bfc11 1612 #define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
Kojto 109:9296ab0bfc11 1613
Kojto 109:9296ab0bfc11 1614 #define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1615 ((SOURCE) == RCC_TIM34CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1616 /**
Kojto 109:9296ab0bfc11 1617 * @}
Kojto 109:9296ab0bfc11 1618 */
Kojto 109:9296ab0bfc11 1619
Kojto 109:9296ab0bfc11 1620 /** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
Kojto 109:9296ab0bfc11 1621 * @{
Kojto 109:9296ab0bfc11 1622 */
Kojto 109:9296ab0bfc11 1623 #define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
Kojto 109:9296ab0bfc11 1624 #define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
Kojto 109:9296ab0bfc11 1625
Kojto 109:9296ab0bfc11 1626 #define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1627 ((SOURCE) == RCC_TIM15CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1628 /**
Kojto 109:9296ab0bfc11 1629 * @}
Kojto 109:9296ab0bfc11 1630 */
Kojto 109:9296ab0bfc11 1631
Kojto 109:9296ab0bfc11 1632 /** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
Kojto 109:9296ab0bfc11 1633 * @{
Kojto 109:9296ab0bfc11 1634 */
Kojto 109:9296ab0bfc11 1635 #define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
Kojto 109:9296ab0bfc11 1636 #define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
Kojto 109:9296ab0bfc11 1637
Kojto 109:9296ab0bfc11 1638 #define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1639 ((SOURCE) == RCC_TIM16CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1640 /**
Kojto 109:9296ab0bfc11 1641 * @}
Kojto 109:9296ab0bfc11 1642 */
Kojto 109:9296ab0bfc11 1643
Kojto 109:9296ab0bfc11 1644 /** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
Kojto 109:9296ab0bfc11 1645 * @{
Kojto 109:9296ab0bfc11 1646 */
Kojto 109:9296ab0bfc11 1647 #define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
Kojto 109:9296ab0bfc11 1648 #define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
Kojto 109:9296ab0bfc11 1649
Kojto 109:9296ab0bfc11 1650 #define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1651 ((SOURCE) == RCC_TIM17CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1652 /**
Kojto 109:9296ab0bfc11 1653 * @}
Kojto 109:9296ab0bfc11 1654 */
Kojto 109:9296ab0bfc11 1655
Kojto 109:9296ab0bfc11 1656 /** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
Kojto 109:9296ab0bfc11 1657 * @{
Kojto 109:9296ab0bfc11 1658 */
Kojto 109:9296ab0bfc11 1659 #define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
Kojto 109:9296ab0bfc11 1660 #define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
Kojto 109:9296ab0bfc11 1661 #define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
Kojto 109:9296ab0bfc11 1662 #define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
Kojto 109:9296ab0bfc11 1663
Kojto 109:9296ab0bfc11 1664 #define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) || \
Kojto 109:9296ab0bfc11 1665 ((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1666 ((SOURCE) == RCC_UART4CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 1667 ((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 1668 /**
Kojto 109:9296ab0bfc11 1669 * @}
Kojto 109:9296ab0bfc11 1670 */
Kojto 109:9296ab0bfc11 1671
Kojto 109:9296ab0bfc11 1672 /** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
Kojto 109:9296ab0bfc11 1673 * @{
Kojto 109:9296ab0bfc11 1674 */
Kojto 109:9296ab0bfc11 1675 #define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
Kojto 109:9296ab0bfc11 1676 #define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
Kojto 109:9296ab0bfc11 1677 #define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
Kojto 109:9296ab0bfc11 1678 #define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
Kojto 109:9296ab0bfc11 1679
Kojto 109:9296ab0bfc11 1680 #define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) || \
Kojto 109:9296ab0bfc11 1681 ((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1682 ((SOURCE) == RCC_UART5CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 1683 ((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 1684 /**
Kojto 109:9296ab0bfc11 1685 * @}
Kojto 109:9296ab0bfc11 1686 */
Kojto 109:9296ab0bfc11 1687
Kojto 109:9296ab0bfc11 1688 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 1689
Kojto 109:9296ab0bfc11 1690 #if defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 1691 /** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
Kojto 109:9296ab0bfc11 1692 * @{
Kojto 109:9296ab0bfc11 1693 */
Kojto 109:9296ab0bfc11 1694 #define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
Kojto 109:9296ab0bfc11 1695 #define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
Kojto 109:9296ab0bfc11 1696
Kojto 109:9296ab0bfc11 1697 #define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1698 ((SOURCE) == RCC_TIM20CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1699 /**
Kojto 109:9296ab0bfc11 1700 * @}
Kojto 109:9296ab0bfc11 1701 */
Kojto 109:9296ab0bfc11 1702 #endif /* STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 1703
Kojto 109:9296ab0bfc11 1704 #if defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 1705 defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 1706
Kojto 109:9296ab0bfc11 1707 /** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
Kojto 109:9296ab0bfc11 1708 * @{
Kojto 109:9296ab0bfc11 1709 */
Kojto 109:9296ab0bfc11 1710
Kojto 109:9296ab0bfc11 1711 /* ADC3 & ADC4 */
Kojto 109:9296ab0bfc11 1712 #define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
Kojto 109:9296ab0bfc11 1713 #define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
Kojto 109:9296ab0bfc11 1714 #define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
Kojto 109:9296ab0bfc11 1715 #define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
Kojto 109:9296ab0bfc11 1716 #define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
Kojto 109:9296ab0bfc11 1717 #define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
Kojto 109:9296ab0bfc11 1718 #define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
Kojto 109:9296ab0bfc11 1719 #define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
Kojto 109:9296ab0bfc11 1720 #define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
Kojto 109:9296ab0bfc11 1721 #define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
Kojto 109:9296ab0bfc11 1722 #define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
Kojto 109:9296ab0bfc11 1723 #define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
Kojto 109:9296ab0bfc11 1724 #define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
Kojto 109:9296ab0bfc11 1725
Kojto 109:9296ab0bfc11 1726 #define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) || \
Kojto 109:9296ab0bfc11 1727 ((ADCCLK) == RCC_ADC34PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) || \
Kojto 109:9296ab0bfc11 1728 ((ADCCLK) == RCC_ADC34PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) || \
Kojto 109:9296ab0bfc11 1729 ((ADCCLK) == RCC_ADC34PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) || \
Kojto 109:9296ab0bfc11 1730 ((ADCCLK) == RCC_ADC34PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) || \
Kojto 109:9296ab0bfc11 1731 ((ADCCLK) == RCC_ADC34PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) || \
Kojto 109:9296ab0bfc11 1732 ((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
Kojto 109:9296ab0bfc11 1733 /**
Kojto 109:9296ab0bfc11 1734 * @}
Kojto 109:9296ab0bfc11 1735 */
Kojto 109:9296ab0bfc11 1736
Kojto 109:9296ab0bfc11 1737 /** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
Kojto 109:9296ab0bfc11 1738 * @{
Kojto 109:9296ab0bfc11 1739 */
Kojto 109:9296ab0bfc11 1740 #define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
Kojto 109:9296ab0bfc11 1741 #define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
Kojto 109:9296ab0bfc11 1742
Kojto 109:9296ab0bfc11 1743 #define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1744 ((SOURCE) == RCC_TIM8CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1745 /**
Kojto 109:9296ab0bfc11 1746 * @}
Kojto 109:9296ab0bfc11 1747 */
Kojto 109:9296ab0bfc11 1748
Kojto 109:9296ab0bfc11 1749 #endif /* STM32F303xC || STM32F303xE || STM32F398xx || STM32F358xx */
Kojto 109:9296ab0bfc11 1750
Kojto 109:9296ab0bfc11 1751 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 109:9296ab0bfc11 1752
Kojto 109:9296ab0bfc11 1753 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto 109:9296ab0bfc11 1754 * @{
Kojto 109:9296ab0bfc11 1755 */
Kojto 109:9296ab0bfc11 1756 #define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
Kojto 109:9296ab0bfc11 1757 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto 109:9296ab0bfc11 1758 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto 109:9296ab0bfc11 1759 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto 109:9296ab0bfc11 1760
Kojto 109:9296ab0bfc11 1761 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) || \
Kojto 109:9296ab0bfc11 1762 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1763 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 1764 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 1765 /**
Kojto 109:9296ab0bfc11 1766 * @}
Kojto 109:9296ab0bfc11 1767 */
Kojto 109:9296ab0bfc11 1768
Kojto 109:9296ab0bfc11 1769 /** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
Kojto 109:9296ab0bfc11 1770 * @{
Kojto 109:9296ab0bfc11 1771 */
Kojto 109:9296ab0bfc11 1772 /* ADC1 & ADC2 */
Kojto 109:9296ab0bfc11 1773 #define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
Kojto 109:9296ab0bfc11 1774 #define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
Kojto 109:9296ab0bfc11 1775 #define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
Kojto 109:9296ab0bfc11 1776 #define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
Kojto 109:9296ab0bfc11 1777 #define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
Kojto 109:9296ab0bfc11 1778 #define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
Kojto 109:9296ab0bfc11 1779 #define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
Kojto 109:9296ab0bfc11 1780 #define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
Kojto 109:9296ab0bfc11 1781 #define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
Kojto 109:9296ab0bfc11 1782 #define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
Kojto 109:9296ab0bfc11 1783 #define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
Kojto 109:9296ab0bfc11 1784 #define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
Kojto 109:9296ab0bfc11 1785 #define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
Kojto 109:9296ab0bfc11 1786
Kojto 109:9296ab0bfc11 1787 #define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) || \
Kojto 109:9296ab0bfc11 1788 ((ADCCLK) == RCC_ADC12PLLCLK_DIV2) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) || \
Kojto 109:9296ab0bfc11 1789 ((ADCCLK) == RCC_ADC12PLLCLK_DIV6) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) || \
Kojto 109:9296ab0bfc11 1790 ((ADCCLK) == RCC_ADC12PLLCLK_DIV10) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) || \
Kojto 109:9296ab0bfc11 1791 ((ADCCLK) == RCC_ADC12PLLCLK_DIV16) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) || \
Kojto 109:9296ab0bfc11 1792 ((ADCCLK) == RCC_ADC12PLLCLK_DIV64) || ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) || \
Kojto 109:9296ab0bfc11 1793 ((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto 109:9296ab0bfc11 1794 /**
Kojto 109:9296ab0bfc11 1795 * @}
Kojto 109:9296ab0bfc11 1796 */
Kojto 109:9296ab0bfc11 1797
Kojto 109:9296ab0bfc11 1798 /** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto 109:9296ab0bfc11 1799 * @{
Kojto 109:9296ab0bfc11 1800 */
Kojto 109:9296ab0bfc11 1801 #define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto 109:9296ab0bfc11 1802 #define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto 109:9296ab0bfc11 1803
Kojto 109:9296ab0bfc11 1804 #define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1805 ((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1806 /**
Kojto 109:9296ab0bfc11 1807 * @}
Kojto 109:9296ab0bfc11 1808 */
Kojto 109:9296ab0bfc11 1809
Kojto 109:9296ab0bfc11 1810 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 109:9296ab0bfc11 1811
Kojto 109:9296ab0bfc11 1812 #if defined(STM32F334x8)
Kojto 109:9296ab0bfc11 1813
Kojto 109:9296ab0bfc11 1814 /** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
Kojto 109:9296ab0bfc11 1815 * @{
Kojto 109:9296ab0bfc11 1816 */
Kojto 109:9296ab0bfc11 1817 #define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
Kojto 109:9296ab0bfc11 1818 #define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
Kojto 109:9296ab0bfc11 1819
Kojto 109:9296ab0bfc11 1820 #define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) || \
Kojto 109:9296ab0bfc11 1821 ((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
Kojto 109:9296ab0bfc11 1822 /**
Kojto 109:9296ab0bfc11 1823 * @}
Kojto 109:9296ab0bfc11 1824 */
Kojto 109:9296ab0bfc11 1825
Kojto 109:9296ab0bfc11 1826 #endif /* STM32F334x8 */
Kojto 109:9296ab0bfc11 1827
Kojto 109:9296ab0bfc11 1828 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 1829
Kojto 109:9296ab0bfc11 1830 /** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto 109:9296ab0bfc11 1831 * @{
Kojto 109:9296ab0bfc11 1832 */
Kojto 109:9296ab0bfc11 1833 #define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto 109:9296ab0bfc11 1834 #define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto 109:9296ab0bfc11 1835 #define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto 109:9296ab0bfc11 1836 #define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto 109:9296ab0bfc11 1837
Kojto 109:9296ab0bfc11 1838 #define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) || \
Kojto 109:9296ab0bfc11 1839 ((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) || \
Kojto 109:9296ab0bfc11 1840 ((SOURCE) == RCC_USART1CLKSOURCE_LSE) || \
Kojto 109:9296ab0bfc11 1841 ((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto 109:9296ab0bfc11 1842 /**
Kojto 109:9296ab0bfc11 1843 * @}
Kojto 109:9296ab0bfc11 1844 */
Kojto 109:9296ab0bfc11 1845
Kojto 109:9296ab0bfc11 1846 /** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto 109:9296ab0bfc11 1847 * @{
Kojto 109:9296ab0bfc11 1848 */
Kojto 109:9296ab0bfc11 1849 #define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto 109:9296ab0bfc11 1850 #define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto 109:9296ab0bfc11 1851
Kojto 109:9296ab0bfc11 1852 #define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 1853 ((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto 109:9296ab0bfc11 1854 /**
Kojto 109:9296ab0bfc11 1855 * @}
Kojto 109:9296ab0bfc11 1856 */
Kojto 109:9296ab0bfc11 1857
Kojto 109:9296ab0bfc11 1858 /** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
Kojto 109:9296ab0bfc11 1859 * @{
Kojto 109:9296ab0bfc11 1860 */
Kojto 109:9296ab0bfc11 1861
Kojto 109:9296ab0bfc11 1862 /* ADC1 */
Kojto 109:9296ab0bfc11 1863 #define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
Kojto 109:9296ab0bfc11 1864 #define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
Kojto 109:9296ab0bfc11 1865 #define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
Kojto 109:9296ab0bfc11 1866 #define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
Kojto 109:9296ab0bfc11 1867
Kojto 109:9296ab0bfc11 1868 #define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) || ((ADCCLK) == RCC_ADC1PCLK2_DIV4) || \
Kojto 109:9296ab0bfc11 1869 ((ADCCLK) == RCC_ADC1PCLK2_DIV6) || ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
Kojto 109:9296ab0bfc11 1870 /**
Kojto 109:9296ab0bfc11 1871 * @}
Kojto 109:9296ab0bfc11 1872 */
Kojto 109:9296ab0bfc11 1873
Kojto 109:9296ab0bfc11 1874 /** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
Kojto 109:9296ab0bfc11 1875 * @{
Kojto 109:9296ab0bfc11 1876 */
Kojto 109:9296ab0bfc11 1877 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
Kojto 109:9296ab0bfc11 1878 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
Kojto 109:9296ab0bfc11 1879
Kojto 109:9296ab0bfc11 1880 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
Kojto 109:9296ab0bfc11 1881 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto 109:9296ab0bfc11 1882 /**
Kojto 109:9296ab0bfc11 1883 * @}
Kojto 109:9296ab0bfc11 1884 */
Kojto 109:9296ab0bfc11 1885
Kojto 109:9296ab0bfc11 1886 /** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
Kojto 109:9296ab0bfc11 1887 * @{
Kojto 109:9296ab0bfc11 1888 */
Kojto 109:9296ab0bfc11 1889 #define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
Kojto 109:9296ab0bfc11 1890 #define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
Kojto 109:9296ab0bfc11 1891 #define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
Kojto 109:9296ab0bfc11 1892 #define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
Kojto 109:9296ab0bfc11 1893 #define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
Kojto 109:9296ab0bfc11 1894 #define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
Kojto 109:9296ab0bfc11 1895 #define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
Kojto 109:9296ab0bfc11 1896 #define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
Kojto 109:9296ab0bfc11 1897 #define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
Kojto 109:9296ab0bfc11 1898 #define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
Kojto 109:9296ab0bfc11 1899 #define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
Kojto 109:9296ab0bfc11 1900 #define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
Kojto 109:9296ab0bfc11 1901 #define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
Kojto 109:9296ab0bfc11 1902 #define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
Kojto 109:9296ab0bfc11 1903 #define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
Kojto 109:9296ab0bfc11 1904 #define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
Kojto 109:9296ab0bfc11 1905 #define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
Kojto 109:9296ab0bfc11 1906
Kojto 109:9296ab0bfc11 1907 #define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) || ((DIV) == RCC_SDADCSYSCLK_DIV2) || \
Kojto 109:9296ab0bfc11 1908 ((DIV) == RCC_SDADCSYSCLK_DIV4) || ((DIV) == RCC_SDADCSYSCLK_DIV6) || \
Kojto 109:9296ab0bfc11 1909 ((DIV) == RCC_SDADCSYSCLK_DIV8) || ((DIV) == RCC_SDADCSYSCLK_DIV10) || \
Kojto 109:9296ab0bfc11 1910 ((DIV) == RCC_SDADCSYSCLK_DIV12) || ((DIV) == RCC_SDADCSYSCLK_DIV14) || \
Kojto 109:9296ab0bfc11 1911 ((DIV) == RCC_SDADCSYSCLK_DIV16) || ((DIV) == RCC_SDADCSYSCLK_DIV20) || \
Kojto 109:9296ab0bfc11 1912 ((DIV) == RCC_SDADCSYSCLK_DIV24) || ((DIV) == RCC_SDADCSYSCLK_DIV28) || \
Kojto 109:9296ab0bfc11 1913 ((DIV) == RCC_SDADCSYSCLK_DIV32) || ((DIV) == RCC_SDADCSYSCLK_DIV36) || \
Kojto 109:9296ab0bfc11 1914 ((DIV) == RCC_SDADCSYSCLK_DIV40) || ((DIV) == RCC_SDADCSYSCLK_DIV44) || \
Kojto 109:9296ab0bfc11 1915 ((DIV) == RCC_SDADCSYSCLK_DIV48))
Kojto 109:9296ab0bfc11 1916 /**
Kojto 109:9296ab0bfc11 1917 * @}
Kojto 109:9296ab0bfc11 1918 */
Kojto 109:9296ab0bfc11 1919
Kojto 109:9296ab0bfc11 1920 #endif /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 1921
Kojto 109:9296ab0bfc11 1922 #if defined(STM32F302xE) || defined(STM32F303xE) || \
Kojto 109:9296ab0bfc11 1923 defined(STM32F302xC) || defined(STM32F303xC) || \
Kojto 109:9296ab0bfc11 1924 defined(STM32F302x8) || \
Kojto 109:9296ab0bfc11 1925 defined(STM32F373xC)
Kojto 109:9296ab0bfc11 1926 /** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
Kojto 109:9296ab0bfc11 1927 * @{
Kojto 109:9296ab0bfc11 1928 */
Kojto 109:9296ab0bfc11 1929 #define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1
Kojto 109:9296ab0bfc11 1930 #define RCC_USBPLLCLK_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
Kojto 109:9296ab0bfc11 1931
Kojto 109:9296ab0bfc11 1932 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBPLLCLK_DIV1) || \
Kojto 109:9296ab0bfc11 1933 ((SOURCE) == RCC_USBPLLCLK_DIV1_5))
Kojto 109:9296ab0bfc11 1934 /**
Kojto 109:9296ab0bfc11 1935 * @}
Kojto 109:9296ab0bfc11 1936 */
Kojto 109:9296ab0bfc11 1937
Kojto 109:9296ab0bfc11 1938 #endif /* STM32F302xE || STM32F303xE || */
Kojto 109:9296ab0bfc11 1939 /* STM32F302xC || STM32F303xC || */
Kojto 109:9296ab0bfc11 1940 /* STM32F302x8 || */
Kojto 109:9296ab0bfc11 1941 /* STM32F373xC */
Kojto 109:9296ab0bfc11 1942
Kojto 109:9296ab0bfc11 1943 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 1944 defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 1945 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
Kojto 109:9296ab0bfc11 1946 * @{
Kojto 109:9296ab0bfc11 1947 */
Kojto 109:9296ab0bfc11 1948 #define RCC_MCO_NODIV ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 1949
Kojto 109:9296ab0bfc11 1950 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
Kojto 109:9296ab0bfc11 1951 /**
Kojto 109:9296ab0bfc11 1952 * @}
Kojto 109:9296ab0bfc11 1953 */
Kojto 109:9296ab0bfc11 1954 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 1955 /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 1956
Kojto 109:9296ab0bfc11 1957 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 1958 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 1959 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 1960
Kojto 109:9296ab0bfc11 1961 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
Kojto 109:9296ab0bfc11 1962 * @{
Kojto 109:9296ab0bfc11 1963 */
Kojto 109:9296ab0bfc11 1964 #define RCC_MCO_DIV1 ((uint32_t)0x00000000)
Kojto 109:9296ab0bfc11 1965 #define RCC_MCO_DIV2 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 1966 #define RCC_MCO_DIV4 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 1967 #define RCC_MCO_DIV8 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 1968 #define RCC_MCO_DIV16 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 1969 #define RCC_MCO_DIV32 ((uint32_t)0x50000000)
Kojto 109:9296ab0bfc11 1970 #define RCC_MCO_DIV64 ((uint32_t)0x60000000)
Kojto 109:9296ab0bfc11 1971 #define RCC_MCO_DIV128 ((uint32_t)0x70000000)
Kojto 109:9296ab0bfc11 1972
Kojto 109:9296ab0bfc11 1973 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
Kojto 109:9296ab0bfc11 1974 ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
Kojto 109:9296ab0bfc11 1975 ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
Kojto 109:9296ab0bfc11 1976 ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
Kojto 109:9296ab0bfc11 1977 /**
Kojto 109:9296ab0bfc11 1978 * @}
Kojto 109:9296ab0bfc11 1979 */
Kojto 109:9296ab0bfc11 1980
Kojto 109:9296ab0bfc11 1981 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 1982 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 1983 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 1984
Kojto 109:9296ab0bfc11 1985 /**
Kojto 109:9296ab0bfc11 1986 * @}
Kojto 109:9296ab0bfc11 1987 */
Kojto 109:9296ab0bfc11 1988
Kojto 109:9296ab0bfc11 1989 /* Exported macro ------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 1990 /** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
Kojto 109:9296ab0bfc11 1991 * @{
Kojto 109:9296ab0bfc11 1992 */
Kojto 109:9296ab0bfc11 1993
Kojto 109:9296ab0bfc11 1994 /** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
Kojto 109:9296ab0bfc11 1995 * @{
Kojto 109:9296ab0bfc11 1996 */
Kojto 109:9296ab0bfc11 1997 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 1998 /** @brief Macro to configure the PLL clock source, multiplication and division factors.
Kojto 109:9296ab0bfc11 1999 * @note This macro must be used only when the PLL is disabled.
Kojto 109:9296ab0bfc11 2000 *
Kojto 109:9296ab0bfc11 2001 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto 109:9296ab0bfc11 2002 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2003 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 109:9296ab0bfc11 2004 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 109:9296ab0bfc11 2005 * @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
Kojto 109:9296ab0bfc11 2006 * This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
Kojto 109:9296ab0bfc11 2007 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
Kojto 109:9296ab0bfc11 2008 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto 109:9296ab0bfc11 2009 *
Kojto 109:9296ab0bfc11 2010 */
Kojto 109:9296ab0bfc11 2011 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
Kojto 109:9296ab0bfc11 2012 do { \
Kojto 109:9296ab0bfc11 2013 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
Kojto 109:9296ab0bfc11 2014 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__))); \
Kojto 109:9296ab0bfc11 2015 } while(0)
Kojto 109:9296ab0bfc11 2016 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 2017
Kojto 109:9296ab0bfc11 2018 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 2019 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 2020 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
Kojto 109:9296ab0bfc11 2021 defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2022 /** @brief Macro to configure the PLL clock source and multiplication factor.
Kojto 109:9296ab0bfc11 2023 * @note This macro must be used only when the PLL is disabled.
Kojto 109:9296ab0bfc11 2024 *
Kojto 109:9296ab0bfc11 2025 * @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto 109:9296ab0bfc11 2026 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2027 * @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto 109:9296ab0bfc11 2028 * @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto 109:9296ab0bfc11 2029 * @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
Kojto 109:9296ab0bfc11 2030 * This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto 109:9296ab0bfc11 2031 *
Kojto 109:9296ab0bfc11 2032 */
Kojto 109:9296ab0bfc11 2033 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
Kojto 109:9296ab0bfc11 2034 MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL | RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)|(__RCC_PLLSource__)))
Kojto 109:9296ab0bfc11 2035 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 2036 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 2037 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 2038 /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2039 /**
Kojto 109:9296ab0bfc11 2040 * @}
Kojto 109:9296ab0bfc11 2041 */
Kojto 109:9296ab0bfc11 2042
Kojto 109:9296ab0bfc11 2043 #if defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 2044 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 2045 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || \
Kojto 109:9296ab0bfc11 2046 defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2047 /** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
Kojto 109:9296ab0bfc11 2048 * @{
Kojto 109:9296ab0bfc11 2049 */
Kojto 109:9296ab0bfc11 2050
Kojto 109:9296ab0bfc11 2051 /**
Kojto 109:9296ab0bfc11 2052 * @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
Kojto 109:9296ab0bfc11 2053 * @note Predivision factor can not be changed if PLL is used as system clock
Kojto 109:9296ab0bfc11 2054 * In this case, you have to select another source of the system clock, disable the PLL and
Kojto 109:9296ab0bfc11 2055 * then change the HSE predivision factor.
Kojto 109:9296ab0bfc11 2056 * @param __HSEPredivValue__: specifies the division value applied to HSE.
Kojto 109:9296ab0bfc11 2057 * This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
Kojto 109:9296ab0bfc11 2058 */
Kojto 109:9296ab0bfc11 2059 #define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
Kojto 109:9296ab0bfc11 2060 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
Kojto 109:9296ab0bfc11 2061 /**
Kojto 109:9296ab0bfc11 2062 * @}
Kojto 109:9296ab0bfc11 2063 */
Kojto 109:9296ab0bfc11 2064 #endif /* STM32F302xC || STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 2065 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 2066 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 2067 /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2068
Kojto 109:9296ab0bfc11 2069 /** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
Kojto 109:9296ab0bfc11 2070 * @brief Enable or disable the AHB peripheral clock.
Kojto 109:9296ab0bfc11 2071 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 2072 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 2073 * using it.
Kojto 109:9296ab0bfc11 2074 * @{
Kojto 109:9296ab0bfc11 2075 */
Kojto 109:9296ab0bfc11 2076 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 2077 #define __ADC1_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC1EN))
Kojto 109:9296ab0bfc11 2078
Kojto 109:9296ab0bfc11 2079 #define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
Kojto 109:9296ab0bfc11 2080 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 2081
Kojto 109:9296ab0bfc11 2082 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2083 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2084 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
Kojto 109:9296ab0bfc11 2085 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
Kojto 109:9296ab0bfc11 2086 #define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN))
Kojto 109:9296ab0bfc11 2087 /* Aliases for STM32 F3 compatibility */
Kojto 109:9296ab0bfc11 2088 #define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto 109:9296ab0bfc11 2089 #define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto 109:9296ab0bfc11 2090
Kojto 109:9296ab0bfc11 2091 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto 109:9296ab0bfc11 2092 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto 109:9296ab0bfc11 2093 #define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
Kojto 109:9296ab0bfc11 2094 /* Aliases for STM32 F3 compatibility */
Kojto 109:9296ab0bfc11 2095 #define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto 109:9296ab0bfc11 2096 #define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto 109:9296ab0bfc11 2097 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2098 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2099
Kojto 109:9296ab0bfc11 2100 #if defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2101 defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2102 #define __ADC34_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC34EN))
Kojto 109:9296ab0bfc11 2103
Kojto 109:9296ab0bfc11 2104 #define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
Kojto 109:9296ab0bfc11 2105 #endif /* STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2106 /* STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2107
Kojto 109:9296ab0bfc11 2108 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 109:9296ab0bfc11 2109 #define __ADC12_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_ADC12EN))
Kojto 109:9296ab0bfc11 2110 /* Aliases for STM32 F3 compatibility */
Kojto 109:9296ab0bfc11 2111 #define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto 109:9296ab0bfc11 2112 #define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto 109:9296ab0bfc11 2113
Kojto 109:9296ab0bfc11 2114 #define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
Kojto 109:9296ab0bfc11 2115 /* Aliases for STM32 F3 compatibility */
Kojto 109:9296ab0bfc11 2116 #define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto 109:9296ab0bfc11 2117 #define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto 109:9296ab0bfc11 2118 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 109:9296ab0bfc11 2119
Kojto 109:9296ab0bfc11 2120 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2121 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
Kojto 109:9296ab0bfc11 2122 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
Kojto 109:9296ab0bfc11 2123
Kojto 109:9296ab0bfc11 2124 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto 109:9296ab0bfc11 2125 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto 109:9296ab0bfc11 2126 #endif /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2127
Kojto 109:9296ab0bfc11 2128 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 2129 #define __FMC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_FMCEN))
Kojto 109:9296ab0bfc11 2130 #define __GPIOG_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN))
Kojto 109:9296ab0bfc11 2131 #define __GPIOH_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOHEN))
Kojto 109:9296ab0bfc11 2132
Kojto 109:9296ab0bfc11 2133 #define __FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
Kojto 109:9296ab0bfc11 2134 #define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
Kojto 109:9296ab0bfc11 2135 #define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
Kojto 109:9296ab0bfc11 2136 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 2137 /**
Kojto 109:9296ab0bfc11 2138 * @}
Kojto 109:9296ab0bfc11 2139 */
Kojto 109:9296ab0bfc11 2140
Kojto 109:9296ab0bfc11 2141 /** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
Kojto 109:9296ab0bfc11 2142 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 109:9296ab0bfc11 2143 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 2144 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 2145 * using it.
Kojto 109:9296ab0bfc11 2146 * @{
Kojto 109:9296ab0bfc11 2147 */
Kojto 109:9296ab0bfc11 2148 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 2149 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
Kojto 109:9296ab0bfc11 2150 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
Kojto 109:9296ab0bfc11 2151 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
Kojto 109:9296ab0bfc11 2152 #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
Kojto 109:9296ab0bfc11 2153
Kojto 109:9296ab0bfc11 2154 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 109:9296ab0bfc11 2155 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 109:9296ab0bfc11 2156 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 109:9296ab0bfc11 2157 #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto 109:9296ab0bfc11 2158 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 2159
Kojto 109:9296ab0bfc11 2160 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2161 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2162 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
Kojto 109:9296ab0bfc11 2163 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
Kojto 109:9296ab0bfc11 2164 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
Kojto 109:9296ab0bfc11 2165 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
Kojto 109:9296ab0bfc11 2166 #define __UART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
Kojto 109:9296ab0bfc11 2167 #define __UART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
Kojto 109:9296ab0bfc11 2168 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
Kojto 109:9296ab0bfc11 2169
Kojto 109:9296ab0bfc11 2170 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 109:9296ab0bfc11 2171 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 109:9296ab0bfc11 2172 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 109:9296ab0bfc11 2173 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 109:9296ab0bfc11 2174 #define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto 109:9296ab0bfc11 2175 #define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto 109:9296ab0bfc11 2176 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 109:9296ab0bfc11 2177 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2178 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2179
Kojto 109:9296ab0bfc11 2180 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 109:9296ab0bfc11 2181 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
Kojto 109:9296ab0bfc11 2182 #define __DAC2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC2EN))
Kojto 109:9296ab0bfc11 2183
Kojto 109:9296ab0bfc11 2184 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 109:9296ab0bfc11 2185 #define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
Kojto 109:9296ab0bfc11 2186 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 109:9296ab0bfc11 2187
Kojto 109:9296ab0bfc11 2188 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2189 #define __TIM3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
Kojto 109:9296ab0bfc11 2190 #define __TIM4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
Kojto 109:9296ab0bfc11 2191 #define __TIM5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
Kojto 109:9296ab0bfc11 2192 #define __TIM12_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM12EN))
Kojto 109:9296ab0bfc11 2193 #define __TIM13_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM13EN))
Kojto 109:9296ab0bfc11 2194 #define __TIM14_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM14EN))
Kojto 109:9296ab0bfc11 2195 #define __TIM18_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM18EN))
Kojto 109:9296ab0bfc11 2196 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
Kojto 109:9296ab0bfc11 2197 #define __SPI3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
Kojto 109:9296ab0bfc11 2198 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
Kojto 109:9296ab0bfc11 2199 #define __DAC2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DAC2EN))
Kojto 109:9296ab0bfc11 2200 #define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
Kojto 109:9296ab0bfc11 2201
Kojto 109:9296ab0bfc11 2202 #define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto 109:9296ab0bfc11 2203 #define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto 109:9296ab0bfc11 2204 #define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto 109:9296ab0bfc11 2205 #define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto 109:9296ab0bfc11 2206 #define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto 109:9296ab0bfc11 2207 #define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto 109:9296ab0bfc11 2208 #define __TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
Kojto 109:9296ab0bfc11 2209 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 109:9296ab0bfc11 2210 #define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto 109:9296ab0bfc11 2211 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 109:9296ab0bfc11 2212 #define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
Kojto 109:9296ab0bfc11 2213 #define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto 109:9296ab0bfc11 2214 #endif /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2215
Kojto 109:9296ab0bfc11 2216 #if defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2217 defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 2218 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 2219 defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2220 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
Kojto 109:9296ab0bfc11 2221
Kojto 109:9296ab0bfc11 2222 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 109:9296ab0bfc11 2223 #endif /* STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2224 /* STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 2225 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 2226 /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2227
Kojto 109:9296ab0bfc11 2228 #if defined(STM32F302xE) || defined(STM32F303xE) || \
Kojto 109:9296ab0bfc11 2229 defined(STM32F302xC) || defined(STM32F303xC) || \
Kojto 109:9296ab0bfc11 2230 defined(STM32F302x8) || \
Kojto 109:9296ab0bfc11 2231 defined(STM32F373xC)
Kojto 109:9296ab0bfc11 2232 #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
Kojto 109:9296ab0bfc11 2233
Kojto 109:9296ab0bfc11 2234 #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto 109:9296ab0bfc11 2235 #endif /* STM32F302xE || STM32F303xE || */
Kojto 109:9296ab0bfc11 2236 /* STM32F302xC || STM32F303xC || */
Kojto 109:9296ab0bfc11 2237 /* STM32F302x8 || */
Kojto 109:9296ab0bfc11 2238 /* STM32F373xC */
Kojto 109:9296ab0bfc11 2239
Kojto 109:9296ab0bfc11 2240 #if !defined(STM32F301x8)
Kojto 109:9296ab0bfc11 2241 #define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
Kojto 109:9296ab0bfc11 2242
Kojto 109:9296ab0bfc11 2243 #define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
Kojto 109:9296ab0bfc11 2244 #endif /* STM32F301x8*/
Kojto 109:9296ab0bfc11 2245
Kojto 109:9296ab0bfc11 2246 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 2247 #define __I2C3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C3EN))
Kojto 109:9296ab0bfc11 2248
Kojto 109:9296ab0bfc11 2249 #define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto 109:9296ab0bfc11 2250 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 2251 /**
Kojto 109:9296ab0bfc11 2252 * @}
Kojto 109:9296ab0bfc11 2253 */
Kojto 109:9296ab0bfc11 2254
Kojto 109:9296ab0bfc11 2255 /** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
Kojto 109:9296ab0bfc11 2256 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 109:9296ab0bfc11 2257 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 109:9296ab0bfc11 2258 * is disabled and the application software has to enable this clock before
Kojto 109:9296ab0bfc11 2259 * using it.
Kojto 109:9296ab0bfc11 2260 * @{
Kojto 109:9296ab0bfc11 2261 */
Kojto 109:9296ab0bfc11 2262 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2263 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2264 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
Kojto 109:9296ab0bfc11 2265
Kojto 109:9296ab0bfc11 2266 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 109:9296ab0bfc11 2267 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2268 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2269
Kojto 109:9296ab0bfc11 2270 #if defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2271 defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2272 #define __TIM8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM8EN))
Kojto 109:9296ab0bfc11 2273
Kojto 109:9296ab0bfc11 2274 #define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto 109:9296ab0bfc11 2275 #endif /* STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2276 /* STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2277
Kojto 109:9296ab0bfc11 2278 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 109:9296ab0bfc11 2279 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
Kojto 109:9296ab0bfc11 2280
Kojto 109:9296ab0bfc11 2281 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 109:9296ab0bfc11 2282 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 109:9296ab0bfc11 2283
Kojto 109:9296ab0bfc11 2284 #if defined(STM32F334x8)
Kojto 109:9296ab0bfc11 2285 #define __HRTIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_HRTIM1EN))
Kojto 109:9296ab0bfc11 2286
Kojto 109:9296ab0bfc11 2287 #define __HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
Kojto 109:9296ab0bfc11 2288 #endif /* STM32F334x8 */
Kojto 109:9296ab0bfc11 2289
Kojto 109:9296ab0bfc11 2290 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2291 #define __ADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
Kojto 109:9296ab0bfc11 2292 #define __SPI1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
Kojto 109:9296ab0bfc11 2293 #define __TIM19_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM19EN))
Kojto 109:9296ab0bfc11 2294 #define __SDADC1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC1EN))
Kojto 109:9296ab0bfc11 2295 #define __SDADC2_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC2EN))
Kojto 109:9296ab0bfc11 2296 #define __SDADC3_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SDADC3EN))
Kojto 109:9296ab0bfc11 2297
Kojto 109:9296ab0bfc11 2298 #define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto 109:9296ab0bfc11 2299 #define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto 109:9296ab0bfc11 2300 #define __TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
Kojto 109:9296ab0bfc11 2301 #define __SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
Kojto 109:9296ab0bfc11 2302 #define __SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
Kojto 109:9296ab0bfc11 2303 #define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
Kojto 109:9296ab0bfc11 2304 #endif /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2305
Kojto 109:9296ab0bfc11 2306 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2307 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 2308 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 2309 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 2310 #define __TIM1_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM1EN))
Kojto 109:9296ab0bfc11 2311
Kojto 109:9296ab0bfc11 2312 #define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto 109:9296ab0bfc11 2313 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2314 /* STM32F302xC || STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 2315 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 2316 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 2317
Kojto 109:9296ab0bfc11 2318 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 2319 #define __SPI4_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_SPI4EN))
Kojto 109:9296ab0bfc11 2320
Kojto 109:9296ab0bfc11 2321 #define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto 109:9296ab0bfc11 2322 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 2323
Kojto 109:9296ab0bfc11 2324 #if defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 2325 #define __TIM20_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM20EN))
Kojto 109:9296ab0bfc11 2326
Kojto 109:9296ab0bfc11 2327 #define __TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
Kojto 109:9296ab0bfc11 2328 #endif /* STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 2329
Kojto 109:9296ab0bfc11 2330 /**
Kojto 109:9296ab0bfc11 2331 * @}
Kojto 109:9296ab0bfc11 2332 */
Kojto 109:9296ab0bfc11 2333
Kojto 109:9296ab0bfc11 2334 /** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
Kojto 109:9296ab0bfc11 2335 * @brief Force or release AHB peripheral reset.
Kojto 109:9296ab0bfc11 2336 * @{
Kojto 109:9296ab0bfc11 2337 */
Kojto 109:9296ab0bfc11 2338 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 2339 #define __ADC1_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC1RST))
Kojto 109:9296ab0bfc11 2340
Kojto 109:9296ab0bfc11 2341 #define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
Kojto 109:9296ab0bfc11 2342 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 2343
Kojto 109:9296ab0bfc11 2344 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2345 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2346 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
Kojto 109:9296ab0bfc11 2347 #define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
Kojto 109:9296ab0bfc11 2348 /* Aliases for STM32 F3 compatibility */
Kojto 109:9296ab0bfc11 2349 #define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto 109:9296ab0bfc11 2350 #define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto 109:9296ab0bfc11 2351
Kojto 109:9296ab0bfc11 2352 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto 109:9296ab0bfc11 2353 #define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
Kojto 109:9296ab0bfc11 2354 /* Aliases for STM32 F3 compatibility */
Kojto 109:9296ab0bfc11 2355 #define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto 109:9296ab0bfc11 2356 #define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto 109:9296ab0bfc11 2357 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2358 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2359
Kojto 109:9296ab0bfc11 2360 #if defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2361 defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2362 #define __ADC34_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC34RST))
Kojto 109:9296ab0bfc11 2363
Kojto 109:9296ab0bfc11 2364 #define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
Kojto 109:9296ab0bfc11 2365 #endif /* STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2366 /* STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2367
Kojto 109:9296ab0bfc11 2368 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 109:9296ab0bfc11 2369 #define __ADC12_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_ADC12RST))
Kojto 109:9296ab0bfc11 2370 /* Aliases for STM32 F3 compatibility */
Kojto 109:9296ab0bfc11 2371 #define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto 109:9296ab0bfc11 2372 #define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto 109:9296ab0bfc11 2373
Kojto 109:9296ab0bfc11 2374 #define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
Kojto 109:9296ab0bfc11 2375 /* Aliases for STM32 F3 compatibility */
Kojto 109:9296ab0bfc11 2376 #define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto 109:9296ab0bfc11 2377 #define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto 109:9296ab0bfc11 2378 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 109:9296ab0bfc11 2379
Kojto 109:9296ab0bfc11 2380 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2381 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
Kojto 109:9296ab0bfc11 2382
Kojto 109:9296ab0bfc11 2383 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto 109:9296ab0bfc11 2384 #endif /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2385
Kojto 109:9296ab0bfc11 2386 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 2387 #define __FMC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_FMCRST))
Kojto 109:9296ab0bfc11 2388 #define __GPIOG_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
Kojto 109:9296ab0bfc11 2389 #define __GPIOH_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
Kojto 109:9296ab0bfc11 2390
Kojto 109:9296ab0bfc11 2391 #define __FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
Kojto 109:9296ab0bfc11 2392 #define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
Kojto 109:9296ab0bfc11 2393 #define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
Kojto 109:9296ab0bfc11 2394 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 2395 /**
Kojto 109:9296ab0bfc11 2396 * @}
Kojto 109:9296ab0bfc11 2397 */
Kojto 109:9296ab0bfc11 2398
Kojto 109:9296ab0bfc11 2399 /** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
Kojto 109:9296ab0bfc11 2400 * @brief Force or release APB1 peripheral reset.
Kojto 109:9296ab0bfc11 2401 * @{
Kojto 109:9296ab0bfc11 2402 */
Kojto 109:9296ab0bfc11 2403 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 2404 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 109:9296ab0bfc11 2405 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 109:9296ab0bfc11 2406 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 109:9296ab0bfc11 2407 #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 109:9296ab0bfc11 2408
Kojto 109:9296ab0bfc11 2409 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 109:9296ab0bfc11 2410 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 109:9296ab0bfc11 2411 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 109:9296ab0bfc11 2412 #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto 109:9296ab0bfc11 2413 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 2414
Kojto 109:9296ab0bfc11 2415 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2416 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2417 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 109:9296ab0bfc11 2418 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 109:9296ab0bfc11 2419 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 109:9296ab0bfc11 2420 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 109:9296ab0bfc11 2421 #define __UART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
Kojto 109:9296ab0bfc11 2422 #define __UART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
Kojto 109:9296ab0bfc11 2423 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 109:9296ab0bfc11 2424
Kojto 109:9296ab0bfc11 2425 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 109:9296ab0bfc11 2426 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 109:9296ab0bfc11 2427 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 109:9296ab0bfc11 2428 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 109:9296ab0bfc11 2429 #define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto 109:9296ab0bfc11 2430 #define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto 109:9296ab0bfc11 2431 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 109:9296ab0bfc11 2432 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2433 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2434
Kojto 109:9296ab0bfc11 2435 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 109:9296ab0bfc11 2436 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 109:9296ab0bfc11 2437 #define __DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
Kojto 109:9296ab0bfc11 2438
Kojto 109:9296ab0bfc11 2439 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 109:9296ab0bfc11 2440 #define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
Kojto 109:9296ab0bfc11 2441 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 109:9296ab0bfc11 2442
Kojto 109:9296ab0bfc11 2443 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2444 #define __TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
Kojto 109:9296ab0bfc11 2445 #define __TIM4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
Kojto 109:9296ab0bfc11 2446 #define __TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
Kojto 109:9296ab0bfc11 2447 #define __TIM12_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM12RST))
Kojto 109:9296ab0bfc11 2448 #define __TIM13_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM13RST))
Kojto 109:9296ab0bfc11 2449 #define __TIM14_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM14RST))
Kojto 109:9296ab0bfc11 2450 #define __TIM18_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM18RST))
Kojto 109:9296ab0bfc11 2451 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 109:9296ab0bfc11 2452 #define __SPI3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
Kojto 109:9296ab0bfc11 2453 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 109:9296ab0bfc11 2454 #define __DAC2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DAC2RST))
Kojto 109:9296ab0bfc11 2455 #define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
Kojto 109:9296ab0bfc11 2456
Kojto 109:9296ab0bfc11 2457 #define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto 109:9296ab0bfc11 2458 #define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto 109:9296ab0bfc11 2459 #define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto 109:9296ab0bfc11 2460 #define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto 109:9296ab0bfc11 2461 #define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto 109:9296ab0bfc11 2462 #define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto 109:9296ab0bfc11 2463 #define __TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
Kojto 109:9296ab0bfc11 2464 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 109:9296ab0bfc11 2465 #define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto 109:9296ab0bfc11 2466 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 109:9296ab0bfc11 2467 #define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
Kojto 109:9296ab0bfc11 2468 #define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto 109:9296ab0bfc11 2469 #endif /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2470
Kojto 109:9296ab0bfc11 2471 #if defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2472 defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 2473 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 2474 defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2475 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 109:9296ab0bfc11 2476
Kojto 109:9296ab0bfc11 2477 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 109:9296ab0bfc11 2478 #endif /* STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2479 /* STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 2480 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 2481 /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2482
Kojto 109:9296ab0bfc11 2483 #if defined(STM32F302xE) || defined(STM32F303xE) || \
Kojto 109:9296ab0bfc11 2484 defined(STM32F302xC) || defined(STM32F303xC) || \
Kojto 109:9296ab0bfc11 2485 defined(STM32F302x8) || \
Kojto 109:9296ab0bfc11 2486 defined(STM32F373xC)
Kojto 109:9296ab0bfc11 2487 #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
Kojto 109:9296ab0bfc11 2488
Kojto 109:9296ab0bfc11 2489 #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto 109:9296ab0bfc11 2490 #endif /* STM32F302xE || STM32F303xE || */
Kojto 109:9296ab0bfc11 2491 /* STM32F302xC || STM32F303xC || */
Kojto 109:9296ab0bfc11 2492 /* STM32F302x8 || */
Kojto 109:9296ab0bfc11 2493 /* STM32F373xC */
Kojto 109:9296ab0bfc11 2494
Kojto 109:9296ab0bfc11 2495 #if !defined(STM32F301x8)
Kojto 109:9296ab0bfc11 2496 #define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
Kojto 109:9296ab0bfc11 2497
Kojto 109:9296ab0bfc11 2498 #define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
Kojto 109:9296ab0bfc11 2499 #endif /* STM32F301x8*/
Kojto 109:9296ab0bfc11 2500
Kojto 109:9296ab0bfc11 2501 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 2502 #define __I2C3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C3RST))
Kojto 109:9296ab0bfc11 2503
Kojto 109:9296ab0bfc11 2504 #define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto 109:9296ab0bfc11 2505 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 2506 /**
Kojto 109:9296ab0bfc11 2507 * @}
Kojto 109:9296ab0bfc11 2508 */
Kojto 109:9296ab0bfc11 2509
Kojto 109:9296ab0bfc11 2510 /** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
Kojto 109:9296ab0bfc11 2511 * @brief Force or release APB2 peripheral reset.
Kojto 109:9296ab0bfc11 2512 * @{
Kojto 109:9296ab0bfc11 2513 */
Kojto 109:9296ab0bfc11 2514 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2515 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2516 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 109:9296ab0bfc11 2517
Kojto 109:9296ab0bfc11 2518 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 109:9296ab0bfc11 2519 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2520 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2521
Kojto 109:9296ab0bfc11 2522 #if defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2523 defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2524 #define __TIM8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM8RST))
Kojto 109:9296ab0bfc11 2525
Kojto 109:9296ab0bfc11 2526 #define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto 109:9296ab0bfc11 2527 #endif /* STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2528 /* STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2529
Kojto 109:9296ab0bfc11 2530 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 109:9296ab0bfc11 2531 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 109:9296ab0bfc11 2532
Kojto 109:9296ab0bfc11 2533 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 109:9296ab0bfc11 2534 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 109:9296ab0bfc11 2535
Kojto 109:9296ab0bfc11 2536 #if defined(STM32F334x8)
Kojto 109:9296ab0bfc11 2537 #define __HRTIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_HRTIM1RST))
Kojto 109:9296ab0bfc11 2538
Kojto 109:9296ab0bfc11 2539 #define __HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
Kojto 109:9296ab0bfc11 2540 #endif /* STM32F334x8 */
Kojto 109:9296ab0bfc11 2541
Kojto 109:9296ab0bfc11 2542 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 2543 #define __ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
Kojto 109:9296ab0bfc11 2544 #define __SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
Kojto 109:9296ab0bfc11 2545 #define __TIM19_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM19RST))
Kojto 109:9296ab0bfc11 2546 #define __SDADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC1RST))
Kojto 109:9296ab0bfc11 2547 #define __SDADC2_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC2RST))
Kojto 109:9296ab0bfc11 2548 #define __SDADC3_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SDADC3RST))
Kojto 109:9296ab0bfc11 2549
Kojto 109:9296ab0bfc11 2550 #define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto 109:9296ab0bfc11 2551 #define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto 109:9296ab0bfc11 2552 #define __TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
Kojto 109:9296ab0bfc11 2553 #define __SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
Kojto 109:9296ab0bfc11 2554 #define __SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
Kojto 109:9296ab0bfc11 2555 #define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
Kojto 109:9296ab0bfc11 2556 #endif /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 2557
Kojto 109:9296ab0bfc11 2558 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2559 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx) || \
Kojto 109:9296ab0bfc11 2560 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 2561 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 2562 #define __TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
Kojto 109:9296ab0bfc11 2563
Kojto 109:9296ab0bfc11 2564 #define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto 109:9296ab0bfc11 2565 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2566 /* STM32F302xC || STM32F303xC || STM32F358xx || */
Kojto 109:9296ab0bfc11 2567 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 2568 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 2569
Kojto 109:9296ab0bfc11 2570 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 2571 #define __SPI4_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI4RST))
Kojto 109:9296ab0bfc11 2572
Kojto 109:9296ab0bfc11 2573 #define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto 109:9296ab0bfc11 2574 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 2575
Kojto 109:9296ab0bfc11 2576 #if defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 2577 #define __TIM20_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM20RST))
Kojto 109:9296ab0bfc11 2578
Kojto 109:9296ab0bfc11 2579 #define __TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
Kojto 109:9296ab0bfc11 2580 #endif /* STM32F303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 2581
Kojto 109:9296ab0bfc11 2582 /**
Kojto 109:9296ab0bfc11 2583 * @}
Kojto 109:9296ab0bfc11 2584 */
Kojto 109:9296ab0bfc11 2585
Kojto 109:9296ab0bfc11 2586 #if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 2587 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto 109:9296ab0bfc11 2588 * @{
Kojto 109:9296ab0bfc11 2589 */
Kojto 109:9296ab0bfc11 2590
Kojto 109:9296ab0bfc11 2591 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 109:9296ab0bfc11 2592 * @param __I2C2CLKSource__: specifies the I2C2 clock source.
Kojto 109:9296ab0bfc11 2593 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2594 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 109:9296ab0bfc11 2595 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 109:9296ab0bfc11 2596 */
Kojto 109:9296ab0bfc11 2597 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
Kojto 109:9296ab0bfc11 2598 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Kojto 109:9296ab0bfc11 2599
Kojto 109:9296ab0bfc11 2600 /** @brief Macro to get the I2C2 clock source.
Kojto 109:9296ab0bfc11 2601 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2602 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 109:9296ab0bfc11 2603 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 109:9296ab0bfc11 2604 */
Kojto 109:9296ab0bfc11 2605 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Kojto 109:9296ab0bfc11 2606
Kojto 109:9296ab0bfc11 2607 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto 109:9296ab0bfc11 2608 * @param __I2C3CLKSource__: specifies the I2C3 clock source.
Kojto 109:9296ab0bfc11 2609 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2610 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 109:9296ab0bfc11 2611 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 109:9296ab0bfc11 2612 */
Kojto 109:9296ab0bfc11 2613 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
Kojto 109:9296ab0bfc11 2614 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
Kojto 109:9296ab0bfc11 2615
Kojto 109:9296ab0bfc11 2616 /** @brief Macro to get the I2C3 clock source.
Kojto 109:9296ab0bfc11 2617 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2618 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 109:9296ab0bfc11 2619 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 109:9296ab0bfc11 2620 */
Kojto 109:9296ab0bfc11 2621 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
Kojto 109:9296ab0bfc11 2622
Kojto 109:9296ab0bfc11 2623 /**
Kojto 109:9296ab0bfc11 2624 * @}
Kojto 109:9296ab0bfc11 2625 */
Kojto 109:9296ab0bfc11 2626
Kojto 109:9296ab0bfc11 2627 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto 109:9296ab0bfc11 2628 * @{
Kojto 109:9296ab0bfc11 2629 */
Kojto 109:9296ab0bfc11 2630 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto 109:9296ab0bfc11 2631 * @param __TIM1CLKSource__: specifies the TIM1 clock source.
Kojto 109:9296ab0bfc11 2632 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2633 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto 109:9296ab0bfc11 2634 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto 109:9296ab0bfc11 2635 */
Kojto 109:9296ab0bfc11 2636 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
Kojto 109:9296ab0bfc11 2637 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
Kojto 109:9296ab0bfc11 2638
Kojto 109:9296ab0bfc11 2639 /** @brief Macro to get the TIM1 clock (TIM1CLK).
Kojto 109:9296ab0bfc11 2640 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2641 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2642 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto 109:9296ab0bfc11 2643 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto 109:9296ab0bfc11 2644 */
Kojto 109:9296ab0bfc11 2645 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
Kojto 109:9296ab0bfc11 2646
Kojto 109:9296ab0bfc11 2647 /** @brief Macro to configure the TIM15 clock (TIM15CLK).
Kojto 109:9296ab0bfc11 2648 * @param __TIM15CLKSource__: specifies the TIM15 clock source.
Kojto 109:9296ab0bfc11 2649 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2650 * @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
Kojto 109:9296ab0bfc11 2651 * @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
Kojto 109:9296ab0bfc11 2652 */
Kojto 109:9296ab0bfc11 2653 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
Kojto 109:9296ab0bfc11 2654 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
Kojto 109:9296ab0bfc11 2655
Kojto 109:9296ab0bfc11 2656 /** @brief Macro to get the TIM15 clock (TIM15CLK).
Kojto 109:9296ab0bfc11 2657 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2658 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2659 * @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
Kojto 109:9296ab0bfc11 2660 * @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
Kojto 109:9296ab0bfc11 2661 */
Kojto 109:9296ab0bfc11 2662 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
Kojto 109:9296ab0bfc11 2663
Kojto 109:9296ab0bfc11 2664 /** @brief Macro to configure the TIM16 clock (TIM16CLK).
Kojto 109:9296ab0bfc11 2665 * @param __TIM16CLKSource__: specifies the TIM16 clock source.
Kojto 109:9296ab0bfc11 2666 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2667 * @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
Kojto 109:9296ab0bfc11 2668 * @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
Kojto 109:9296ab0bfc11 2669 */
Kojto 109:9296ab0bfc11 2670 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
Kojto 109:9296ab0bfc11 2671 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
Kojto 109:9296ab0bfc11 2672
Kojto 109:9296ab0bfc11 2673 /** @brief Macro to get the TIM16 clock (TIM16CLK).
Kojto 109:9296ab0bfc11 2674 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2675 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2676 * @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
Kojto 109:9296ab0bfc11 2677 * @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
Kojto 109:9296ab0bfc11 2678 */
Kojto 109:9296ab0bfc11 2679 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
Kojto 109:9296ab0bfc11 2680
Kojto 109:9296ab0bfc11 2681 /** @brief Macro to configure the TIM17 clock (TIM17CLK).
Kojto 109:9296ab0bfc11 2682 * @param __TIM17CLKSource__: specifies the TIM17 clock source.
Kojto 109:9296ab0bfc11 2683 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2684 * @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
Kojto 109:9296ab0bfc11 2685 * @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
Kojto 109:9296ab0bfc11 2686 */
Kojto 109:9296ab0bfc11 2687 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
Kojto 109:9296ab0bfc11 2688 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
Kojto 109:9296ab0bfc11 2689
Kojto 109:9296ab0bfc11 2690 /** @brief Macro to get the TIM17 clock (TIM17CLK).
Kojto 109:9296ab0bfc11 2691 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2692 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2693 * @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
Kojto 109:9296ab0bfc11 2694 * @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
Kojto 109:9296ab0bfc11 2695 */
Kojto 109:9296ab0bfc11 2696 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
Kojto 109:9296ab0bfc11 2697
Kojto 109:9296ab0bfc11 2698 /**
Kojto 109:9296ab0bfc11 2699 * @}
Kojto 109:9296ab0bfc11 2700 */
Kojto 109:9296ab0bfc11 2701
Kojto 109:9296ab0bfc11 2702 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
Kojto 109:9296ab0bfc11 2703 * @{
Kojto 109:9296ab0bfc11 2704 */
Kojto 109:9296ab0bfc11 2705 /** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto 109:9296ab0bfc11 2706 * @note This function must be called before enabling the I2S APB clock.
Kojto 109:9296ab0bfc11 2707 * @param __I2SCLKSource__: specifies the I2S clock source.
Kojto 109:9296ab0bfc11 2708 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2709 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto 109:9296ab0bfc11 2710 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto 109:9296ab0bfc11 2711 * used as I2S clock source
Kojto 109:9296ab0bfc11 2712 */
Kojto 109:9296ab0bfc11 2713 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
Kojto 109:9296ab0bfc11 2714 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
Kojto 109:9296ab0bfc11 2715
Kojto 109:9296ab0bfc11 2716 /** @brief Macro to get the I2S clock source (I2SCLK).
Kojto 109:9296ab0bfc11 2717 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2718 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto 109:9296ab0bfc11 2719 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto 109:9296ab0bfc11 2720 * used as I2S clock source
Kojto 109:9296ab0bfc11 2721 */
Kojto 109:9296ab0bfc11 2722 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
Kojto 109:9296ab0bfc11 2723 /**
Kojto 109:9296ab0bfc11 2724 * @}
Kojto 109:9296ab0bfc11 2725 */
Kojto 109:9296ab0bfc11 2726
Kojto 109:9296ab0bfc11 2727 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto 109:9296ab0bfc11 2728 * @{
Kojto 109:9296ab0bfc11 2729 */
Kojto 109:9296ab0bfc11 2730
Kojto 109:9296ab0bfc11 2731 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
Kojto 109:9296ab0bfc11 2732 * @param __ADC1CLKSource__: specifies the ADC1 clock source.
Kojto 109:9296ab0bfc11 2733 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2734 * @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
Kojto 109:9296ab0bfc11 2735 * @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2736 * @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2737 * @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2738 * @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2739 * @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2740 * @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2741 * @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2742 * @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2743 * @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2744 * @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2745 * @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2746 * @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2747 */
Kojto 109:9296ab0bfc11 2748 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
Kojto 109:9296ab0bfc11 2749 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
Kojto 109:9296ab0bfc11 2750
Kojto 109:9296ab0bfc11 2751 /** @brief Macro to get the ADC1 clock
Kojto 109:9296ab0bfc11 2752 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2753 * @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
Kojto 109:9296ab0bfc11 2754 * @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2755 * @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2756 * @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2757 * @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2758 * @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2759 * @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2760 * @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2761 * @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2762 * @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2763 * @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2764 * @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2765 * @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
Kojto 109:9296ab0bfc11 2766 */
Kojto 109:9296ab0bfc11 2767 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
Kojto 109:9296ab0bfc11 2768 /**
Kojto 109:9296ab0bfc11 2769 * @}
Kojto 109:9296ab0bfc11 2770 */
Kojto 109:9296ab0bfc11 2771
Kojto 109:9296ab0bfc11 2772 #endif /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 2773
Kojto 109:9296ab0bfc11 2774 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2775 defined(STM32F302xC) || defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2776 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto 109:9296ab0bfc11 2777 * @{
Kojto 109:9296ab0bfc11 2778 */
Kojto 109:9296ab0bfc11 2779
Kojto 109:9296ab0bfc11 2780 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 109:9296ab0bfc11 2781 * @param __I2C2CLKSource__: specifies the I2C2 clock source.
Kojto 109:9296ab0bfc11 2782 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2783 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 109:9296ab0bfc11 2784 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 109:9296ab0bfc11 2785 */
Kojto 109:9296ab0bfc11 2786 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
Kojto 109:9296ab0bfc11 2787 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Kojto 109:9296ab0bfc11 2788
Kojto 109:9296ab0bfc11 2789 /** @brief Macro to get the I2C2 clock source.
Kojto 109:9296ab0bfc11 2790 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2791 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 109:9296ab0bfc11 2792 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 109:9296ab0bfc11 2793 */
Kojto 109:9296ab0bfc11 2794 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Kojto 109:9296ab0bfc11 2795 /**
Kojto 109:9296ab0bfc11 2796 * @}
Kojto 109:9296ab0bfc11 2797 */
Kojto 109:9296ab0bfc11 2798
Kojto 109:9296ab0bfc11 2799 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto 109:9296ab0bfc11 2800 * @{
Kojto 109:9296ab0bfc11 2801 */
Kojto 109:9296ab0bfc11 2802
Kojto 109:9296ab0bfc11 2803 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
Kojto 109:9296ab0bfc11 2804 * @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
Kojto 109:9296ab0bfc11 2805 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2806 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto 109:9296ab0bfc11 2807 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2808 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2809 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2810 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2811 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2812 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2813 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2814 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2815 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2816 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2817 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2818 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2819 */
Kojto 109:9296ab0bfc11 2820 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
Kojto 109:9296ab0bfc11 2821 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
Kojto 109:9296ab0bfc11 2822
Kojto 109:9296ab0bfc11 2823 /** @brief Macro to get the ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2824 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2825 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto 109:9296ab0bfc11 2826 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2827 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2828 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2829 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2830 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2831 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2832 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2833 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2834 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2835 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2836 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2837 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 2838 */
Kojto 109:9296ab0bfc11 2839 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
Kojto 109:9296ab0bfc11 2840 /**
Kojto 109:9296ab0bfc11 2841 * @}
Kojto 109:9296ab0bfc11 2842 */
Kojto 109:9296ab0bfc11 2843
Kojto 109:9296ab0bfc11 2844 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto 109:9296ab0bfc11 2845 * @{
Kojto 109:9296ab0bfc11 2846 */
Kojto 109:9296ab0bfc11 2847
Kojto 109:9296ab0bfc11 2848 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto 109:9296ab0bfc11 2849 * @param __TIM1CLKSource__: specifies the TIM1 clock source.
Kojto 109:9296ab0bfc11 2850 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2851 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto 109:9296ab0bfc11 2852 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto 109:9296ab0bfc11 2853 */
Kojto 109:9296ab0bfc11 2854 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
Kojto 109:9296ab0bfc11 2855 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
Kojto 109:9296ab0bfc11 2856
Kojto 109:9296ab0bfc11 2857 /** @brief Macro to get the TIM1 clock (TIM1CLK).
Kojto 109:9296ab0bfc11 2858 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2859 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2860 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto 109:9296ab0bfc11 2861 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto 109:9296ab0bfc11 2862 */
Kojto 109:9296ab0bfc11 2863 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
Kojto 109:9296ab0bfc11 2864 /**
Kojto 109:9296ab0bfc11 2865 * @}
Kojto 109:9296ab0bfc11 2866 */
Kojto 109:9296ab0bfc11 2867
Kojto 109:9296ab0bfc11 2868 /** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
Kojto 109:9296ab0bfc11 2869 * @{
Kojto 109:9296ab0bfc11 2870 */
Kojto 109:9296ab0bfc11 2871
Kojto 109:9296ab0bfc11 2872 /** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto 109:9296ab0bfc11 2873 * @note This function must be called before enabling the I2S APB clock.
Kojto 109:9296ab0bfc11 2874 * @param __I2SCLKSource__: specifies the I2S clock source.
Kojto 109:9296ab0bfc11 2875 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2876 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto 109:9296ab0bfc11 2877 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto 109:9296ab0bfc11 2878 * used as I2S clock source
Kojto 109:9296ab0bfc11 2879 */
Kojto 109:9296ab0bfc11 2880 #define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
Kojto 109:9296ab0bfc11 2881 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
Kojto 109:9296ab0bfc11 2882
Kojto 109:9296ab0bfc11 2883 /** @brief Macro to get the I2S clock source (I2SCLK).
Kojto 109:9296ab0bfc11 2884 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2885 * @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto 109:9296ab0bfc11 2886 * @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto 109:9296ab0bfc11 2887 * used as I2S clock source
Kojto 109:9296ab0bfc11 2888 */
Kojto 109:9296ab0bfc11 2889 #define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
Kojto 109:9296ab0bfc11 2890 /**
Kojto 109:9296ab0bfc11 2891 * @}
Kojto 109:9296ab0bfc11 2892 */
Kojto 109:9296ab0bfc11 2893
Kojto 109:9296ab0bfc11 2894 /** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
Kojto 109:9296ab0bfc11 2895 * @{
Kojto 109:9296ab0bfc11 2896 */
Kojto 109:9296ab0bfc11 2897
Kojto 109:9296ab0bfc11 2898 /** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto 109:9296ab0bfc11 2899 * @param __UART4CLKSource__: specifies the UART4 clock source.
Kojto 109:9296ab0bfc11 2900 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2901 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto 109:9296ab0bfc11 2902 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto 109:9296ab0bfc11 2903 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto 109:9296ab0bfc11 2904 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto 109:9296ab0bfc11 2905 */
Kojto 109:9296ab0bfc11 2906 #define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
Kojto 109:9296ab0bfc11 2907 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
Kojto 109:9296ab0bfc11 2908
Kojto 109:9296ab0bfc11 2909 /** @brief Macro to get the UART4 clock source.
Kojto 109:9296ab0bfc11 2910 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2911 * @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto 109:9296ab0bfc11 2912 * @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto 109:9296ab0bfc11 2913 * @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto 109:9296ab0bfc11 2914 * @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto 109:9296ab0bfc11 2915 */
Kojto 109:9296ab0bfc11 2916 #define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
Kojto 109:9296ab0bfc11 2917
Kojto 109:9296ab0bfc11 2918 /** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto 109:9296ab0bfc11 2919 * @param __UART5CLKSource__: specifies the UART5 clock source.
Kojto 109:9296ab0bfc11 2920 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2921 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto 109:9296ab0bfc11 2922 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto 109:9296ab0bfc11 2923 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto 109:9296ab0bfc11 2924 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto 109:9296ab0bfc11 2925 */
Kojto 109:9296ab0bfc11 2926 #define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
Kojto 109:9296ab0bfc11 2927 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
Kojto 109:9296ab0bfc11 2928
Kojto 109:9296ab0bfc11 2929 /** @brief Macro to get the UART5 clock source.
Kojto 109:9296ab0bfc11 2930 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2931 * @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto 109:9296ab0bfc11 2932 * @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto 109:9296ab0bfc11 2933 * @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto 109:9296ab0bfc11 2934 * @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto 109:9296ab0bfc11 2935 */
Kojto 109:9296ab0bfc11 2936 #define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
Kojto 109:9296ab0bfc11 2937 /**
Kojto 109:9296ab0bfc11 2938 * @}
Kojto 109:9296ab0bfc11 2939 */
Kojto 109:9296ab0bfc11 2940 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 2941 /* STM32F302xC || STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 2942
Kojto 109:9296ab0bfc11 2943 #if defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 2944 defined(STM32F303xC) || defined(STM32F358xx)
Kojto 109:9296ab0bfc11 2945 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto 109:9296ab0bfc11 2946 * @{
Kojto 109:9296ab0bfc11 2947 */
Kojto 109:9296ab0bfc11 2948
Kojto 109:9296ab0bfc11 2949 /** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
Kojto 109:9296ab0bfc11 2950 * @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source.
Kojto 109:9296ab0bfc11 2951 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2952 * @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
Kojto 109:9296ab0bfc11 2953 * @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2954 * @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2955 * @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2956 * @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2957 * @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2958 * @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2959 * @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2960 * @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2961 * @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2962 * @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2963 * @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2964 * @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2965 */
Kojto 109:9296ab0bfc11 2966 #define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
Kojto 109:9296ab0bfc11 2967 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
Kojto 109:9296ab0bfc11 2968
Kojto 109:9296ab0bfc11 2969 /** @brief Macro to get the ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2970 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 2971 * @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
Kojto 109:9296ab0bfc11 2972 * @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2973 * @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2974 * @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2975 * @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2976 * @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2977 * @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2978 * @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2979 * @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2980 * @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2981 * @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2982 * @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2983 * @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
Kojto 109:9296ab0bfc11 2984 */
Kojto 109:9296ab0bfc11 2985 #define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
Kojto 109:9296ab0bfc11 2986 /**
Kojto 109:9296ab0bfc11 2987 * @}
Kojto 109:9296ab0bfc11 2988 */
Kojto 109:9296ab0bfc11 2989
Kojto 109:9296ab0bfc11 2990 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto 109:9296ab0bfc11 2991 * @{
Kojto 109:9296ab0bfc11 2992 */
Kojto 109:9296ab0bfc11 2993
Kojto 109:9296ab0bfc11 2994 /** @brief Macro to configure the TIM8 clock (TIM8CLK).
Kojto 109:9296ab0bfc11 2995 * @param __TIM8CLKSource__: specifies the TIM8 clock source.
Kojto 109:9296ab0bfc11 2996 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 2997 * @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
Kojto 109:9296ab0bfc11 2998 * @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
Kojto 109:9296ab0bfc11 2999 */
Kojto 109:9296ab0bfc11 3000 #define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
Kojto 109:9296ab0bfc11 3001 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
Kojto 109:9296ab0bfc11 3002
Kojto 109:9296ab0bfc11 3003 /** @brief Macro to get the TIM8 clock (TIM8CLK).
Kojto 109:9296ab0bfc11 3004 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3005 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3006 * @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
Kojto 109:9296ab0bfc11 3007 * @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
Kojto 109:9296ab0bfc11 3008 */
Kojto 109:9296ab0bfc11 3009 #define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
Kojto 109:9296ab0bfc11 3010
Kojto 109:9296ab0bfc11 3011 /**
Kojto 109:9296ab0bfc11 3012 * @}
Kojto 109:9296ab0bfc11 3013 */
Kojto 109:9296ab0bfc11 3014 #endif /* STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 3015 /* STM32F303xC || STM32F358xx */
Kojto 109:9296ab0bfc11 3016
Kojto 109:9296ab0bfc11 3017 #if defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
Kojto 109:9296ab0bfc11 3018 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto 109:9296ab0bfc11 3019 * @{
Kojto 109:9296ab0bfc11 3020 */
Kojto 109:9296ab0bfc11 3021
Kojto 109:9296ab0bfc11 3022 /** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
Kojto 109:9296ab0bfc11 3023 * @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
Kojto 109:9296ab0bfc11 3024 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3025 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto 109:9296ab0bfc11 3026 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3027 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3028 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3029 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3030 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3031 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3032 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3033 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3034 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3035 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3036 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3037 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3038 */
Kojto 109:9296ab0bfc11 3039 #define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
Kojto 109:9296ab0bfc11 3040 MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
Kojto 109:9296ab0bfc11 3041
Kojto 109:9296ab0bfc11 3042 /** @brief Macro to get the ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3043 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3044 * @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto 109:9296ab0bfc11 3045 * @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3046 * @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3047 * @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3048 * @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3049 * @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3050 * @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3051 * @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3052 * @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3053 * @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3054 * @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3055 * @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3056 * @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto 109:9296ab0bfc11 3057 */
Kojto 109:9296ab0bfc11 3058 #define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
Kojto 109:9296ab0bfc11 3059 /**
Kojto 109:9296ab0bfc11 3060 * @}
Kojto 109:9296ab0bfc11 3061 */
Kojto 109:9296ab0bfc11 3062
Kojto 109:9296ab0bfc11 3063 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto 109:9296ab0bfc11 3064 * @{
Kojto 109:9296ab0bfc11 3065 */
Kojto 109:9296ab0bfc11 3066 /** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto 109:9296ab0bfc11 3067 * @param __TIM1CLKSource__: specifies the TIM1 clock source.
Kojto 109:9296ab0bfc11 3068 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3069 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto 109:9296ab0bfc11 3070 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto 109:9296ab0bfc11 3071 */
Kojto 109:9296ab0bfc11 3072 #define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
Kojto 109:9296ab0bfc11 3073 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
Kojto 109:9296ab0bfc11 3074
Kojto 109:9296ab0bfc11 3075 /** @brief Macro to get the TIM1 clock (TIM1CLK).
Kojto 109:9296ab0bfc11 3076 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3077 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3078 * @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto 109:9296ab0bfc11 3079 * @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto 109:9296ab0bfc11 3080 */
Kojto 109:9296ab0bfc11 3081 #define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
Kojto 109:9296ab0bfc11 3082 /**
Kojto 109:9296ab0bfc11 3083 * @}
Kojto 109:9296ab0bfc11 3084 */
Kojto 109:9296ab0bfc11 3085 #endif /* STM32F303x8 || STM32F334x8 || STM32F328xx */
Kojto 109:9296ab0bfc11 3086
Kojto 109:9296ab0bfc11 3087 #if defined(STM32F334x8)
Kojto 109:9296ab0bfc11 3088 /** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
Kojto 109:9296ab0bfc11 3089 * @{
Kojto 109:9296ab0bfc11 3090 */
Kojto 109:9296ab0bfc11 3091 /** @brief Macro to configure the HRTIM1 clock.
Kojto 109:9296ab0bfc11 3092 * @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source.
Kojto 109:9296ab0bfc11 3093 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3094 * @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
Kojto 109:9296ab0bfc11 3095 * @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
Kojto 109:9296ab0bfc11 3096 */
Kojto 109:9296ab0bfc11 3097 #define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
Kojto 109:9296ab0bfc11 3098 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
Kojto 109:9296ab0bfc11 3099
Kojto 109:9296ab0bfc11 3100 /** @brief Macro to get the HRTIM1 clock source.
Kojto 109:9296ab0bfc11 3101 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3102 * @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
Kojto 109:9296ab0bfc11 3103 * @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
Kojto 109:9296ab0bfc11 3104 */
Kojto 109:9296ab0bfc11 3105 #define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
Kojto 109:9296ab0bfc11 3106 /**
Kojto 109:9296ab0bfc11 3107 * @}
Kojto 109:9296ab0bfc11 3108 */
Kojto 109:9296ab0bfc11 3109 #endif /* STM32F334x8 */
Kojto 109:9296ab0bfc11 3110
Kojto 109:9296ab0bfc11 3111 #if defined(STM32F373xC) || defined(STM32F378xx)
Kojto 109:9296ab0bfc11 3112 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto 109:9296ab0bfc11 3113 * @{
Kojto 109:9296ab0bfc11 3114 */
Kojto 109:9296ab0bfc11 3115 /** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto 109:9296ab0bfc11 3116 * @param __I2C2CLKSource__: specifies the I2C2 clock source.
Kojto 109:9296ab0bfc11 3117 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3118 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 109:9296ab0bfc11 3119 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 109:9296ab0bfc11 3120 */
Kojto 109:9296ab0bfc11 3121 #define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
Kojto 109:9296ab0bfc11 3122 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Kojto 109:9296ab0bfc11 3123
Kojto 109:9296ab0bfc11 3124 /** @brief Macro to get the I2C2 clock source.
Kojto 109:9296ab0bfc11 3125 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3126 * @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto 109:9296ab0bfc11 3127 * @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto 109:9296ab0bfc11 3128 */
Kojto 109:9296ab0bfc11 3129 #define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Kojto 109:9296ab0bfc11 3130 /**
Kojto 109:9296ab0bfc11 3131 * @}
Kojto 109:9296ab0bfc11 3132 */
Kojto 109:9296ab0bfc11 3133
Kojto 109:9296ab0bfc11 3134 /** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto 109:9296ab0bfc11 3135 * @{
Kojto 109:9296ab0bfc11 3136 */
Kojto 109:9296ab0bfc11 3137 /** @brief Macro to configure the ADC1 clock (ADC1CLK).
Kojto 109:9296ab0bfc11 3138 * @param __ADC1CLKSource__: specifies the ADC1 clock source.
Kojto 109:9296ab0bfc11 3139 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3140 * @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
Kojto 109:9296ab0bfc11 3141 * @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
Kojto 109:9296ab0bfc11 3142 * @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
Kojto 109:9296ab0bfc11 3143 * @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
Kojto 109:9296ab0bfc11 3144 */
Kojto 109:9296ab0bfc11 3145 #define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
Kojto 109:9296ab0bfc11 3146 MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
Kojto 109:9296ab0bfc11 3147
Kojto 109:9296ab0bfc11 3148 /** @brief Macro to get the ADC1 clock (ADC1CLK).
Kojto 109:9296ab0bfc11 3149 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3150 * @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
Kojto 109:9296ab0bfc11 3151 * @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
Kojto 109:9296ab0bfc11 3152 * @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
Kojto 109:9296ab0bfc11 3153 * @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
Kojto 109:9296ab0bfc11 3154 */
Kojto 109:9296ab0bfc11 3155 #define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
Kojto 109:9296ab0bfc11 3156 /**
Kojto 109:9296ab0bfc11 3157 * @}
Kojto 109:9296ab0bfc11 3158 */
Kojto 109:9296ab0bfc11 3159
Kojto 109:9296ab0bfc11 3160 /** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
Kojto 109:9296ab0bfc11 3161 * @{
Kojto 109:9296ab0bfc11 3162 */
Kojto 109:9296ab0bfc11 3163 /** @brief Macro to configure the SDADCx clock (SDADCxCLK).
Kojto 109:9296ab0bfc11 3164 * @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler.
Kojto 109:9296ab0bfc11 3165 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3166 * @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
Kojto 109:9296ab0bfc11 3167 * @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3168 * @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3169 * @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3170 * @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3171 * @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3172 * @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3173 * @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3174 * @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3175 * @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3176 * @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3177 * @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3178 * @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3179 * @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3180 * @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3181 * @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3182 * @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3183 */
Kojto 109:9296ab0bfc11 3184 #define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
Kojto 109:9296ab0bfc11 3185 MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
Kojto 109:9296ab0bfc11 3186
Kojto 109:9296ab0bfc11 3187 /** @brief Macro to get the SDADCx clock prescaler.
Kojto 109:9296ab0bfc11 3188 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3189 * @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
Kojto 109:9296ab0bfc11 3190 * @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3191 * @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3192 * @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3193 * @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3194 * @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3195 * @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3196 * @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3197 * @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3198 * @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3199 * @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3200 * @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3201 * @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3202 * @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3203 * @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3204 * @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3205 * @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
Kojto 109:9296ab0bfc11 3206 */
Kojto 109:9296ab0bfc11 3207 #define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
Kojto 109:9296ab0bfc11 3208 /**
Kojto 109:9296ab0bfc11 3209 * @}
Kojto 109:9296ab0bfc11 3210 */
Kojto 109:9296ab0bfc11 3211
Kojto 109:9296ab0bfc11 3212 /** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
Kojto 109:9296ab0bfc11 3213 * @{
Kojto 109:9296ab0bfc11 3214 */
Kojto 109:9296ab0bfc11 3215 /** @brief Macro to configure the CEC clock.
Kojto 109:9296ab0bfc11 3216 * @param __CECCLKSource__: specifies the CEC clock source.
Kojto 109:9296ab0bfc11 3217 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3218 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 109:9296ab0bfc11 3219 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 109:9296ab0bfc11 3220 */
Kojto 109:9296ab0bfc11 3221 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
Kojto 109:9296ab0bfc11 3222 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
Kojto 109:9296ab0bfc11 3223
Kojto 109:9296ab0bfc11 3224 /** @brief Macro to get the HDMI CEC clock source.
Kojto 109:9296ab0bfc11 3225 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3226 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 109:9296ab0bfc11 3227 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 109:9296ab0bfc11 3228 */
Kojto 109:9296ab0bfc11 3229 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
Kojto 109:9296ab0bfc11 3230 /**
Kojto 109:9296ab0bfc11 3231 * @}
Kojto 109:9296ab0bfc11 3232 */
Kojto 109:9296ab0bfc11 3233
Kojto 109:9296ab0bfc11 3234 #endif /* STM32F373xC || STM32F378xx */
Kojto 109:9296ab0bfc11 3235
Kojto 109:9296ab0bfc11 3236 #if defined(STM32F302xE) || defined(STM32F303xE) || \
Kojto 109:9296ab0bfc11 3237 defined(STM32F302xC) || defined(STM32F303xC) || \
Kojto 109:9296ab0bfc11 3238 defined(STM32F302x8) || \
Kojto 109:9296ab0bfc11 3239 defined(STM32F373xC)
Kojto 109:9296ab0bfc11 3240
Kojto 109:9296ab0bfc11 3241 /** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
Kojto 109:9296ab0bfc11 3242 * @{
Kojto 109:9296ab0bfc11 3243 */
Kojto 109:9296ab0bfc11 3244 /** @brief Macro to configure the USB clock (USBCLK).
Kojto 109:9296ab0bfc11 3245 * @param __USBCLKSource__: specifies the USB clock source.
Kojto 109:9296ab0bfc11 3246 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3247 * @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
Kojto 109:9296ab0bfc11 3248 * @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
Kojto 109:9296ab0bfc11 3249 */
Kojto 109:9296ab0bfc11 3250 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
Kojto 109:9296ab0bfc11 3251 MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
Kojto 109:9296ab0bfc11 3252
Kojto 109:9296ab0bfc11 3253 /** @brief Macro to get the USB clock source.
Kojto 109:9296ab0bfc11 3254 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3255 * @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
Kojto 109:9296ab0bfc11 3256 * @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
Kojto 109:9296ab0bfc11 3257 */
Kojto 109:9296ab0bfc11 3258 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
Kojto 109:9296ab0bfc11 3259 /**
Kojto 109:9296ab0bfc11 3260 * @}
Kojto 109:9296ab0bfc11 3261 */
Kojto 109:9296ab0bfc11 3262
Kojto 109:9296ab0bfc11 3263 #endif /* STM32F302xE || STM32F303xE || */
Kojto 109:9296ab0bfc11 3264 /* STM32F302xC || STM32F303xC || */
Kojto 109:9296ab0bfc11 3265 /* STM32F302x8 || */
Kojto 109:9296ab0bfc11 3266 /* STM32F373xC */
Kojto 109:9296ab0bfc11 3267
Kojto 109:9296ab0bfc11 3268 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx) || \
Kojto 109:9296ab0bfc11 3269 defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx) || \
Kojto 109:9296ab0bfc11 3270 defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
Kojto 109:9296ab0bfc11 3271
Kojto 109:9296ab0bfc11 3272 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto 109:9296ab0bfc11 3273 * @{
Kojto 109:9296ab0bfc11 3274 */
Kojto 109:9296ab0bfc11 3275 /** @brief macro to configure the MCO clock.
Kojto 109:9296ab0bfc11 3276 * @param __MCOCLKSource__: specifies the MCO clock source.
Kojto 109:9296ab0bfc11 3277 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3278 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto 109:9296ab0bfc11 3279 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto 109:9296ab0bfc11 3280 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto 109:9296ab0bfc11 3281 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto 109:9296ab0bfc11 3282 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto 109:9296ab0bfc11 3283 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto 109:9296ab0bfc11 3284 * @param __MCODiv__: specifies the MCO clock prescaler.
Kojto 109:9296ab0bfc11 3285 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3286 * @arg RCC_MCO_NODIV: No division applied on MCO clock source
Kojto 109:9296ab0bfc11 3287 */
Kojto 109:9296ab0bfc11 3288 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto 109:9296ab0bfc11 3289 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__)))
Kojto 109:9296ab0bfc11 3290 /**
Kojto 109:9296ab0bfc11 3291 * @}
Kojto 109:9296ab0bfc11 3292 */
Kojto 109:9296ab0bfc11 3293 #else
Kojto 109:9296ab0bfc11 3294 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto 109:9296ab0bfc11 3295 * @{
Kojto 109:9296ab0bfc11 3296 */
Kojto 109:9296ab0bfc11 3297
Kojto 109:9296ab0bfc11 3298 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto 109:9296ab0bfc11 3299 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__))
Kojto 109:9296ab0bfc11 3300 /**
Kojto 109:9296ab0bfc11 3301 * @}
Kojto 109:9296ab0bfc11 3302 */
Kojto 109:9296ab0bfc11 3303
Kojto 109:9296ab0bfc11 3304 #endif /* STM32F302xE || STM32F303xE || STM32F398xx || */
Kojto 109:9296ab0bfc11 3305 /* STM32F303x8 || STM32F334x8 || STM32F328xx || */
Kojto 109:9296ab0bfc11 3306 /* STM32F301x8 || STM32F302x8 || STM32F318xx */
Kojto 109:9296ab0bfc11 3307
Kojto 109:9296ab0bfc11 3308 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 3309
Kojto 109:9296ab0bfc11 3310 /** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto 109:9296ab0bfc11 3311 * @{
Kojto 109:9296ab0bfc11 3312 */
Kojto 109:9296ab0bfc11 3313 /** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto 109:9296ab0bfc11 3314 * @param __I2C3CLKSource__: specifies the I2C3 clock source.
Kojto 109:9296ab0bfc11 3315 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3316 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 109:9296ab0bfc11 3317 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 109:9296ab0bfc11 3318 */
Kojto 109:9296ab0bfc11 3319 #define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
Kojto 109:9296ab0bfc11 3320 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
Kojto 109:9296ab0bfc11 3321
Kojto 109:9296ab0bfc11 3322 /** @brief Macro to get the I2C3 clock source.
Kojto 109:9296ab0bfc11 3323 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3324 * @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto 109:9296ab0bfc11 3325 * @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto 109:9296ab0bfc11 3326 */
Kojto 109:9296ab0bfc11 3327 #define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
Kojto 109:9296ab0bfc11 3328 /**
Kojto 109:9296ab0bfc11 3329 * @}
Kojto 109:9296ab0bfc11 3330 */
Kojto 109:9296ab0bfc11 3331
Kojto 109:9296ab0bfc11 3332 /** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto 109:9296ab0bfc11 3333 * @{
Kojto 109:9296ab0bfc11 3334 */
Kojto 109:9296ab0bfc11 3335 /** @brief Macro to configure the TIM2 clock (TIM2CLK).
Kojto 109:9296ab0bfc11 3336 * @param __TIM2CLKSource__: specifies the TIM2 clock source.
Kojto 109:9296ab0bfc11 3337 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3338 * @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
Kojto 109:9296ab0bfc11 3339 * @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
Kojto 109:9296ab0bfc11 3340 */
Kojto 109:9296ab0bfc11 3341 #define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
Kojto 109:9296ab0bfc11 3342 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
Kojto 109:9296ab0bfc11 3343
Kojto 109:9296ab0bfc11 3344 /** @brief Macro to get the TIM2 clock (TIM2CLK).
Kojto 109:9296ab0bfc11 3345 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3346 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3347 * @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
Kojto 109:9296ab0bfc11 3348 * @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
Kojto 109:9296ab0bfc11 3349 */
Kojto 109:9296ab0bfc11 3350 #define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
Kojto 109:9296ab0bfc11 3351
Kojto 109:9296ab0bfc11 3352 /** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
Kojto 109:9296ab0bfc11 3353 * @param __TIM3CLKSource__: specifies the TIM3 & TIM4 clock source.
Kojto 109:9296ab0bfc11 3354 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3355 * @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
Kojto 109:9296ab0bfc11 3356 * @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
Kojto 109:9296ab0bfc11 3357 */
Kojto 109:9296ab0bfc11 3358 #define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
Kojto 109:9296ab0bfc11 3359 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
Kojto 109:9296ab0bfc11 3360
Kojto 109:9296ab0bfc11 3361 /** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
Kojto 109:9296ab0bfc11 3362 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3363 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3364 * @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
Kojto 109:9296ab0bfc11 3365 * @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
Kojto 109:9296ab0bfc11 3366 */
Kojto 109:9296ab0bfc11 3367 #define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
Kojto 109:9296ab0bfc11 3368
Kojto 109:9296ab0bfc11 3369 /** @brief Macro to configure the TIM15 clock (TIM15CLK).
Kojto 109:9296ab0bfc11 3370 * @param __TIM15CLKSource__: specifies the TIM15 clock source.
Kojto 109:9296ab0bfc11 3371 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3372 * @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
Kojto 109:9296ab0bfc11 3373 * @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
Kojto 109:9296ab0bfc11 3374 */
Kojto 109:9296ab0bfc11 3375 #define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
Kojto 109:9296ab0bfc11 3376 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
Kojto 109:9296ab0bfc11 3377
Kojto 109:9296ab0bfc11 3378 /** @brief Macro to get the TIM15 clock (TIM15CLK).
Kojto 109:9296ab0bfc11 3379 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3380 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3381 * @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
Kojto 109:9296ab0bfc11 3382 * @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
Kojto 109:9296ab0bfc11 3383 */
Kojto 109:9296ab0bfc11 3384 #define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
Kojto 109:9296ab0bfc11 3385
Kojto 109:9296ab0bfc11 3386 /** @brief Macro to configure the TIM16 clock (TIM16CLK).
Kojto 109:9296ab0bfc11 3387 * @param __TIM16CLKSource__: specifies the TIM16 clock source.
Kojto 109:9296ab0bfc11 3388 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3389 * @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
Kojto 109:9296ab0bfc11 3390 * @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
Kojto 109:9296ab0bfc11 3391 */
Kojto 109:9296ab0bfc11 3392 #define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
Kojto 109:9296ab0bfc11 3393 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
Kojto 109:9296ab0bfc11 3394
Kojto 109:9296ab0bfc11 3395 /** @brief Macro to get the TIM16 clock (TIM16CLK).
Kojto 109:9296ab0bfc11 3396 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3397 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3398 * @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
Kojto 109:9296ab0bfc11 3399 * @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
Kojto 109:9296ab0bfc11 3400 */
Kojto 109:9296ab0bfc11 3401 #define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
Kojto 109:9296ab0bfc11 3402
Kojto 109:9296ab0bfc11 3403 /** @brief Macro to configure the TIM17 clock (TIM17CLK).
Kojto 109:9296ab0bfc11 3404 * @param __TIM17CLKSource__: specifies the TIM17 clock source.
Kojto 109:9296ab0bfc11 3405 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3406 * @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
Kojto 109:9296ab0bfc11 3407 * @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
Kojto 109:9296ab0bfc11 3408 */
Kojto 109:9296ab0bfc11 3409 #define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
Kojto 109:9296ab0bfc11 3410 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
Kojto 109:9296ab0bfc11 3411
Kojto 109:9296ab0bfc11 3412 /** @brief Macro to get the TIM17 clock (TIM17CLK).
Kojto 109:9296ab0bfc11 3413 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3414 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3415 * @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
Kojto 109:9296ab0bfc11 3416 * @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
Kojto 109:9296ab0bfc11 3417 */
Kojto 109:9296ab0bfc11 3418 #define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
Kojto 109:9296ab0bfc11 3419
Kojto 109:9296ab0bfc11 3420 /**
Kojto 109:9296ab0bfc11 3421 * @}
Kojto 109:9296ab0bfc11 3422 */
Kojto 109:9296ab0bfc11 3423
Kojto 109:9296ab0bfc11 3424 #endif /* STM32f302xE || STM32f303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 3425
Kojto 109:9296ab0bfc11 3426 #if defined(STM32F303xE) || defined(STM32F398xx)
Kojto 109:9296ab0bfc11 3427 /** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto 109:9296ab0bfc11 3428 * @{
Kojto 109:9296ab0bfc11 3429 */
Kojto 109:9296ab0bfc11 3430 /** @brief Macro to configure the TIM20 clock (TIM20CLK).
Kojto 109:9296ab0bfc11 3431 * @param __TIM20CLKSource__: specifies the TIM20 clock source.
Kojto 109:9296ab0bfc11 3432 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3433 * @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
Kojto 109:9296ab0bfc11 3434 * @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
Kojto 109:9296ab0bfc11 3435 */
Kojto 109:9296ab0bfc11 3436 #define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
Kojto 109:9296ab0bfc11 3437 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
Kojto 109:9296ab0bfc11 3438
Kojto 109:9296ab0bfc11 3439 /** @brief Macro to get the TIM20 clock (TIM20CLK).
Kojto 109:9296ab0bfc11 3440 * @retval The clock source can be one of the following values:
Kojto 109:9296ab0bfc11 3441 * This parameter can be one of the following values:
Kojto 109:9296ab0bfc11 3442 * @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
Kojto 109:9296ab0bfc11 3443 * @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
Kojto 109:9296ab0bfc11 3444 */
Kojto 109:9296ab0bfc11 3445 #define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
Kojto 109:9296ab0bfc11 3446
Kojto 109:9296ab0bfc11 3447 /**
Kojto 109:9296ab0bfc11 3448 * @}
Kojto 109:9296ab0bfc11 3449 */
Kojto 109:9296ab0bfc11 3450 #endif /* STM32f303xE || STM32F398xx */
Kojto 109:9296ab0bfc11 3451
Kojto 109:9296ab0bfc11 3452
Kojto 109:9296ab0bfc11 3453 /**
Kojto 109:9296ab0bfc11 3454 * @}
Kojto 109:9296ab0bfc11 3455 */
Kojto 109:9296ab0bfc11 3456
Kojto 109:9296ab0bfc11 3457 /* Exported functions --------------------------------------------------------*/
Kojto 109:9296ab0bfc11 3458 /** @addtogroup RCCEx_Exported_Functions RCC Extended Exported Functions
Kojto 109:9296ab0bfc11 3459 * @{
Kojto 109:9296ab0bfc11 3460 */
Kojto 109:9296ab0bfc11 3461
Kojto 109:9296ab0bfc11 3462 /** @addtogroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
Kojto 109:9296ab0bfc11 3463 * @{
Kojto 109:9296ab0bfc11 3464 */
Kojto 109:9296ab0bfc11 3465 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 109:9296ab0bfc11 3466 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 109:9296ab0bfc11 3467 /**
Kojto 109:9296ab0bfc11 3468 * @}
Kojto 109:9296ab0bfc11 3469 */
Kojto 109:9296ab0bfc11 3470
Kojto 109:9296ab0bfc11 3471 /**
Kojto 109:9296ab0bfc11 3472 * @}
Kojto 109:9296ab0bfc11 3473 */
Kojto 109:9296ab0bfc11 3474
Kojto 109:9296ab0bfc11 3475 /**
Kojto 109:9296ab0bfc11 3476 * @}
Kojto 109:9296ab0bfc11 3477 */
Kojto 109:9296ab0bfc11 3478
Kojto 109:9296ab0bfc11 3479 /**
Kojto 109:9296ab0bfc11 3480 * @}
Kojto 109:9296ab0bfc11 3481 */
Kojto 109:9296ab0bfc11 3482 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 3483 }
Kojto 109:9296ab0bfc11 3484 #endif
Kojto 109:9296ab0bfc11 3485
Kojto 109:9296ab0bfc11 3486 #endif /* __STM32F3xx_HAL_RCC_EX_H */
Kojto 109:9296ab0bfc11 3487
Kojto 109:9296ab0bfc11 3488 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/