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TARGET_NUCLEO_F031K6/stm32f031x6.h@109:9296ab0bfc11, 2015-10-29 (annotated)

Committer:
Kojto
Date:
Thu Oct 29 08:40:18 2015 +0000
Revision:
109:9296ab0bfc11
Release 109  of the mbed library



Changes:

- new platforms - NUCLEO_F042K6, WIZNWIKI_W7500ECO

- MTS targets - bootloaders update to 0.1.1

- STM F7 - RTC enable fixes

- STM F4 - i2c pending stop before start fix

- STM all targets - analogout normalization fix

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 109:9296ab0bfc11 1 /**
Kojto 109:9296ab0bfc11 2 ******************************************************************************
Kojto 109:9296ab0bfc11 3 * @file stm32f031x6.h
Kojto 109:9296ab0bfc11 4 * @author MCD Application Team
Kojto 109:9296ab0bfc11 5 * @version V2.2.2
Kojto 109:9296ab0bfc11 6 * @date 26-June-2015
Kojto 109:9296ab0bfc11 7 * @brief CMSIS STM32F031x4/STM32F031x6 devices Peripheral Access Layer Header File.
Kojto 109:9296ab0bfc11 8 *
Kojto 109:9296ab0bfc11 9 * This file contains:
Kojto 109:9296ab0bfc11 10 * - Data structures and the address mapping for all peripherals
Kojto 109:9296ab0bfc11 11 * - Peripheral's registers declarations and bits definition
Kojto 109:9296ab0bfc11 12 * - Macros to access peripheral’s registers hardware
Kojto 109:9296ab0bfc11 13 *
Kojto 109:9296ab0bfc11 14 ******************************************************************************
Kojto 109:9296ab0bfc11 15 * @attention
Kojto 109:9296ab0bfc11 16 *
Kojto 109:9296ab0bfc11 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 109:9296ab0bfc11 18 *
Kojto 109:9296ab0bfc11 19 * Redistribution and use in source and binary forms, with or without modification,
Kojto 109:9296ab0bfc11 20 * are permitted provided that the following conditions are met:
Kojto 109:9296ab0bfc11 21 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 109:9296ab0bfc11 22 * this list of conditions and the following disclaimer.
Kojto 109:9296ab0bfc11 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 109:9296ab0bfc11 24 * this list of conditions and the following disclaimer in the documentation
Kojto 109:9296ab0bfc11 25 * and/or other materials provided with the distribution.
Kojto 109:9296ab0bfc11 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 109:9296ab0bfc11 27 * may be used to endorse or promote products derived from this software
Kojto 109:9296ab0bfc11 28 * without specific prior written permission.
Kojto 109:9296ab0bfc11 29 *
Kojto 109:9296ab0bfc11 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 109:9296ab0bfc11 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 109:9296ab0bfc11 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 109:9296ab0bfc11 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 109:9296ab0bfc11 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 109:9296ab0bfc11 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 109:9296ab0bfc11 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 109:9296ab0bfc11 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 109:9296ab0bfc11 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 109:9296ab0bfc11 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 109:9296ab0bfc11 40 *
Kojto 109:9296ab0bfc11 41 ******************************************************************************
Kojto 109:9296ab0bfc11 42 */
Kojto 109:9296ab0bfc11 43
Kojto 109:9296ab0bfc11 44 /** @addtogroup CMSIS_Device
Kojto 109:9296ab0bfc11 45 * @{
Kojto 109:9296ab0bfc11 46 */
Kojto 109:9296ab0bfc11 47
Kojto 109:9296ab0bfc11 48 /** @addtogroup stm32f031x6
Kojto 109:9296ab0bfc11 49 * @{
Kojto 109:9296ab0bfc11 50 */
Kojto 109:9296ab0bfc11 51
Kojto 109:9296ab0bfc11 52 #ifndef __STM32F031x6_H
Kojto 109:9296ab0bfc11 53 #define __STM32F031x6_H
Kojto 109:9296ab0bfc11 54
Kojto 109:9296ab0bfc11 55 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 56 extern "C" {
Kojto 109:9296ab0bfc11 57 #endif /* __cplusplus */
Kojto 109:9296ab0bfc11 58
Kojto 109:9296ab0bfc11 59 /** @addtogroup Configuration_section_for_CMSIS
Kojto 109:9296ab0bfc11 60 * @{
Kojto 109:9296ab0bfc11 61 */
Kojto 109:9296ab0bfc11 62 /**
Kojto 109:9296ab0bfc11 63 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
Kojto 109:9296ab0bfc11 64 */
Kojto 109:9296ab0bfc11 65 #define __CM0_REV 0 /*!< Core Revision r0p0 */
Kojto 109:9296ab0bfc11 66 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
Kojto 109:9296ab0bfc11 67 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
Kojto 109:9296ab0bfc11 68 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 109:9296ab0bfc11 69
Kojto 109:9296ab0bfc11 70 /**
Kojto 109:9296ab0bfc11 71 * @}
Kojto 109:9296ab0bfc11 72 */
Kojto 109:9296ab0bfc11 73
Kojto 109:9296ab0bfc11 74 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 109:9296ab0bfc11 75 * @{
Kojto 109:9296ab0bfc11 76 */
Kojto 109:9296ab0bfc11 77
Kojto 109:9296ab0bfc11 78 /**
Kojto 109:9296ab0bfc11 79 * @brief STM32F031x4/STM32F031x6 device Interrupt Number Definition
Kojto 109:9296ab0bfc11 80 */
Kojto 109:9296ab0bfc11 81 typedef enum
Kojto 109:9296ab0bfc11 82 {
Kojto 109:9296ab0bfc11 83 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
Kojto 109:9296ab0bfc11 84 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 109:9296ab0bfc11 85 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
Kojto 109:9296ab0bfc11 86 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
Kojto 109:9296ab0bfc11 87 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
Kojto 109:9296ab0bfc11 88 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
Kojto 109:9296ab0bfc11 89
Kojto 109:9296ab0bfc11 90 /****** STM32F031x4/STM32F031x6 specific Interrupt Numbers **************************************************/
Kojto 109:9296ab0bfc11 91 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 109:9296ab0bfc11 92 PVD_IRQn = 1, /*!< PVD Interrupts through EXTI Lines 16 */
Kojto 109:9296ab0bfc11 93 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
Kojto 109:9296ab0bfc11 94 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
Kojto 109:9296ab0bfc11 95 RCC_IRQn = 4, /*!< RCC global Interrupt */
Kojto 109:9296ab0bfc11 96 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
Kojto 109:9296ab0bfc11 97 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
Kojto 109:9296ab0bfc11 98 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
Kojto 109:9296ab0bfc11 99 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
Kojto 109:9296ab0bfc11 100 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
Kojto 109:9296ab0bfc11 101 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
Kojto 109:9296ab0bfc11 102 ADC1_IRQn = 12, /*!< ADC1 global Interrupt */
Kojto 109:9296ab0bfc11 103 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
Kojto 109:9296ab0bfc11 104 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
Kojto 109:9296ab0bfc11 105 TIM2_IRQn = 15, /*!< TIM2 global Interrupt */
Kojto 109:9296ab0bfc11 106 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
Kojto 109:9296ab0bfc11 107 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
Kojto 109:9296ab0bfc11 108 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
Kojto 109:9296ab0bfc11 109 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
Kojto 109:9296ab0bfc11 110 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt & EXTI Line23 Interrupt (I2C1 wakeup) */
Kojto 109:9296ab0bfc11 111 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
Kojto 109:9296ab0bfc11 112 USART1_IRQn = 27 /*!< USART1 global Interrupt & EXTI Line25 Interrupt (USART1 wakeup) */
Kojto 109:9296ab0bfc11 113 } IRQn_Type;
Kojto 109:9296ab0bfc11 114
Kojto 109:9296ab0bfc11 115 /**
Kojto 109:9296ab0bfc11 116 * @}
Kojto 109:9296ab0bfc11 117 */
Kojto 109:9296ab0bfc11 118
Kojto 109:9296ab0bfc11 119 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
Kojto 109:9296ab0bfc11 120 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
Kojto 109:9296ab0bfc11 121 #include <stdint.h>
Kojto 109:9296ab0bfc11 122
Kojto 109:9296ab0bfc11 123 /** @addtogroup Peripheral_registers_structures
Kojto 109:9296ab0bfc11 124 * @{
Kojto 109:9296ab0bfc11 125 */
Kojto 109:9296ab0bfc11 126
Kojto 109:9296ab0bfc11 127 /**
Kojto 109:9296ab0bfc11 128 * @brief Analog to Digital Converter
Kojto 109:9296ab0bfc11 129 */
Kojto 109:9296ab0bfc11 130
Kojto 109:9296ab0bfc11 131 typedef struct
Kojto 109:9296ab0bfc11 132 {
Kojto 109:9296ab0bfc11 133 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
Kojto 109:9296ab0bfc11 134 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
Kojto 109:9296ab0bfc11 135 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
Kojto 109:9296ab0bfc11 136 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
Kojto 109:9296ab0bfc11 137 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
Kojto 109:9296ab0bfc11 138 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
Kojto 109:9296ab0bfc11 139 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 109:9296ab0bfc11 140 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 109:9296ab0bfc11 141 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
Kojto 109:9296ab0bfc11 142 uint32_t RESERVED3; /*!< Reserved, 0x24 */
Kojto 109:9296ab0bfc11 143 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
Kojto 109:9296ab0bfc11 144 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
Kojto 109:9296ab0bfc11 145 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
Kojto 109:9296ab0bfc11 146 }ADC_TypeDef;
Kojto 109:9296ab0bfc11 147
Kojto 109:9296ab0bfc11 148 typedef struct
Kojto 109:9296ab0bfc11 149 {
Kojto 109:9296ab0bfc11 150 __IO uint32_t CCR;
Kojto 109:9296ab0bfc11 151 }ADC_Common_TypeDef;
Kojto 109:9296ab0bfc11 152
Kojto 109:9296ab0bfc11 153 /**
Kojto 109:9296ab0bfc11 154 * @brief CRC calculation unit
Kojto 109:9296ab0bfc11 155 */
Kojto 109:9296ab0bfc11 156
Kojto 109:9296ab0bfc11 157 typedef struct
Kojto 109:9296ab0bfc11 158 {
Kojto 109:9296ab0bfc11 159 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 160 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 161 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 109:9296ab0bfc11 162 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 109:9296ab0bfc11 163 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 164 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 109:9296ab0bfc11 165 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 166 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 167 }CRC_TypeDef;
Kojto 109:9296ab0bfc11 168
Kojto 109:9296ab0bfc11 169 /**
Kojto 109:9296ab0bfc11 170 * @brief Debug MCU
Kojto 109:9296ab0bfc11 171 */
Kojto 109:9296ab0bfc11 172
Kojto 109:9296ab0bfc11 173 typedef struct
Kojto 109:9296ab0bfc11 174 {
Kojto 109:9296ab0bfc11 175 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 176 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 177 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 178 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 179 }DBGMCU_TypeDef;
Kojto 109:9296ab0bfc11 180
Kojto 109:9296ab0bfc11 181 /**
Kojto 109:9296ab0bfc11 182 * @brief DMA Controller
Kojto 109:9296ab0bfc11 183 */
Kojto 109:9296ab0bfc11 184
Kojto 109:9296ab0bfc11 185 typedef struct
Kojto 109:9296ab0bfc11 186 {
Kojto 109:9296ab0bfc11 187 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 109:9296ab0bfc11 188 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 109:9296ab0bfc11 189 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 109:9296ab0bfc11 190 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 109:9296ab0bfc11 191 }DMA_Channel_TypeDef;
Kojto 109:9296ab0bfc11 192
Kojto 109:9296ab0bfc11 193 typedef struct
Kojto 109:9296ab0bfc11 194 {
Kojto 109:9296ab0bfc11 195 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 196 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 197 }DMA_TypeDef;
Kojto 109:9296ab0bfc11 198
Kojto 109:9296ab0bfc11 199 /**
Kojto 109:9296ab0bfc11 200 * @brief External Interrupt/Event Controller
Kojto 109:9296ab0bfc11 201 */
Kojto 109:9296ab0bfc11 202
Kojto 109:9296ab0bfc11 203 typedef struct
Kojto 109:9296ab0bfc11 204 {
Kojto 109:9296ab0bfc11 205 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 206 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 207 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Kojto 109:9296ab0bfc11 208 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 209 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 210 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 211 }EXTI_TypeDef;
Kojto 109:9296ab0bfc11 212
Kojto 109:9296ab0bfc11 213 /**
Kojto 109:9296ab0bfc11 214 * @brief FLASH Registers
Kojto 109:9296ab0bfc11 215 */
Kojto 109:9296ab0bfc11 216 typedef struct
Kojto 109:9296ab0bfc11 217 {
Kojto 109:9296ab0bfc11 218 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 219 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 220 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 221 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 222 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 223 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 224 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
Kojto 109:9296ab0bfc11 225 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 226 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 227 }FLASH_TypeDef;
Kojto 109:9296ab0bfc11 228
Kojto 109:9296ab0bfc11 229
Kojto 109:9296ab0bfc11 230 /**
Kojto 109:9296ab0bfc11 231 * @brief Option Bytes Registers
Kojto 109:9296ab0bfc11 232 */
Kojto 109:9296ab0bfc11 233 typedef struct
Kojto 109:9296ab0bfc11 234 {
Kojto 109:9296ab0bfc11 235 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 236 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
Kojto 109:9296ab0bfc11 237 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
Kojto 109:9296ab0bfc11 238 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
Kojto 109:9296ab0bfc11 239 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 240 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
Kojto 109:9296ab0bfc11 241 }OB_TypeDef;
Kojto 109:9296ab0bfc11 242
Kojto 109:9296ab0bfc11 243 /**
Kojto 109:9296ab0bfc11 244 * @brief General Purpose I/O
Kojto 109:9296ab0bfc11 245 */
Kojto 109:9296ab0bfc11 246
Kojto 109:9296ab0bfc11 247 typedef struct
Kojto 109:9296ab0bfc11 248 {
Kojto 109:9296ab0bfc11 249 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 250 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 251 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 252 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 253 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 254 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 255 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
Kojto 109:9296ab0bfc11 256 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 257 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
Kojto 109:9296ab0bfc11 258 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 259 }GPIO_TypeDef;
Kojto 109:9296ab0bfc11 260
Kojto 109:9296ab0bfc11 261 /**
Kojto 109:9296ab0bfc11 262 * @brief SysTem Configuration
Kojto 109:9296ab0bfc11 263 */
Kojto 109:9296ab0bfc11 264
Kojto 109:9296ab0bfc11 265 typedef struct
Kojto 109:9296ab0bfc11 266 {
Kojto 109:9296ab0bfc11 267 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 268 uint32_t RESERVED; /*!< Reserved, 0x04 */
Kojto 109:9296ab0bfc11 269 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
Kojto 109:9296ab0bfc11 270 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 271 }SYSCFG_TypeDef;
Kojto 109:9296ab0bfc11 272
Kojto 109:9296ab0bfc11 273 /**
Kojto 109:9296ab0bfc11 274 * @brief Inter-integrated Circuit Interface
Kojto 109:9296ab0bfc11 275 */
Kojto 109:9296ab0bfc11 276
Kojto 109:9296ab0bfc11 277 typedef struct
Kojto 109:9296ab0bfc11 278 {
Kojto 109:9296ab0bfc11 279 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 280 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 281 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 282 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 283 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 284 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 285 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 286 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 287 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 288 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 289 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 290 }I2C_TypeDef;
Kojto 109:9296ab0bfc11 291
Kojto 109:9296ab0bfc11 292 /**
Kojto 109:9296ab0bfc11 293 * @brief Independent WATCHDOG
Kojto 109:9296ab0bfc11 294 */
Kojto 109:9296ab0bfc11 295
Kojto 109:9296ab0bfc11 296 typedef struct
Kojto 109:9296ab0bfc11 297 {
Kojto 109:9296ab0bfc11 298 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 299 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 300 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 301 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 302 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 303 }IWDG_TypeDef;
Kojto 109:9296ab0bfc11 304
Kojto 109:9296ab0bfc11 305 /**
Kojto 109:9296ab0bfc11 306 * @brief Power Control
Kojto 109:9296ab0bfc11 307 */
Kojto 109:9296ab0bfc11 308
Kojto 109:9296ab0bfc11 309 typedef struct
Kojto 109:9296ab0bfc11 310 {
Kojto 109:9296ab0bfc11 311 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 312 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 313 }PWR_TypeDef;
Kojto 109:9296ab0bfc11 314
Kojto 109:9296ab0bfc11 315 /**
Kojto 109:9296ab0bfc11 316 * @brief Reset and Clock Control
Kojto 109:9296ab0bfc11 317 */
Kojto 109:9296ab0bfc11 318
Kojto 109:9296ab0bfc11 319 typedef struct
Kojto 109:9296ab0bfc11 320 {
Kojto 109:9296ab0bfc11 321 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 322 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 323 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 324 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 325 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 326 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 327 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 328 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 329 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 330 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 331 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 332 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 333 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 334 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 335 }RCC_TypeDef;
Kojto 109:9296ab0bfc11 336
Kojto 109:9296ab0bfc11 337 /**
Kojto 109:9296ab0bfc11 338 * @brief Real-Time Clock
Kojto 109:9296ab0bfc11 339 */
Kojto 109:9296ab0bfc11 340 typedef struct
Kojto 109:9296ab0bfc11 341 {
Kojto 109:9296ab0bfc11 342 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 343 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 344 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 345 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 346 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 347 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 348 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 349 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 350 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 351 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 352 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 353 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 354 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 355 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 356 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 109:9296ab0bfc11 357 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 109:9296ab0bfc11 358 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
Kojto 109:9296ab0bfc11 359 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 109:9296ab0bfc11 360 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x48 */
Kojto 109:9296ab0bfc11 361 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x4C */
Kojto 109:9296ab0bfc11 362 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 109:9296ab0bfc11 363 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 109:9296ab0bfc11 364 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 109:9296ab0bfc11 365 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 109:9296ab0bfc11 366 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 109:9296ab0bfc11 367 }RTC_TypeDef;
Kojto 109:9296ab0bfc11 368
Kojto 109:9296ab0bfc11 369 /**
Kojto 109:9296ab0bfc11 370 * @brief Serial Peripheral Interface
Kojto 109:9296ab0bfc11 371 */
Kojto 109:9296ab0bfc11 372
Kojto 109:9296ab0bfc11 373 typedef struct
Kojto 109:9296ab0bfc11 374 {
Kojto 109:9296ab0bfc11 375 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 109:9296ab0bfc11 376 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 377 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 378 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 379 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 109:9296ab0bfc11 380 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 109:9296ab0bfc11 381 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 109:9296ab0bfc11 382 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 383 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 384 }SPI_TypeDef;
Kojto 109:9296ab0bfc11 385
Kojto 109:9296ab0bfc11 386 /**
Kojto 109:9296ab0bfc11 387 * @brief TIM
Kojto 109:9296ab0bfc11 388 */
Kojto 109:9296ab0bfc11 389 typedef struct
Kojto 109:9296ab0bfc11 390 {
Kojto 109:9296ab0bfc11 391 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 392 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 393 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 394 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 395 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 396 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 397 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 398 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 399 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 400 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 401 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 402 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 109:9296ab0bfc11 403 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
Kojto 109:9296ab0bfc11 404 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 109:9296ab0bfc11 405 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 109:9296ab0bfc11 406 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 109:9296ab0bfc11 407 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 109:9296ab0bfc11 408 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
Kojto 109:9296ab0bfc11 409 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 109:9296ab0bfc11 410 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Kojto 109:9296ab0bfc11 411 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 109:9296ab0bfc11 412 }TIM_TypeDef;
Kojto 109:9296ab0bfc11 413
Kojto 109:9296ab0bfc11 414 /**
Kojto 109:9296ab0bfc11 415 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 109:9296ab0bfc11 416 */
Kojto 109:9296ab0bfc11 417
Kojto 109:9296ab0bfc11 418 typedef struct
Kojto 109:9296ab0bfc11 419 {
Kojto 109:9296ab0bfc11 420 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 421 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 422 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 423 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 109:9296ab0bfc11 424 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 109:9296ab0bfc11 425 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 109:9296ab0bfc11 426 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 109:9296ab0bfc11 427 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 109:9296ab0bfc11 428 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 109:9296ab0bfc11 429 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 109:9296ab0bfc11 430 uint16_t RESERVED1; /*!< Reserved, 0x26 */
Kojto 109:9296ab0bfc11 431 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 109:9296ab0bfc11 432 uint16_t RESERVED2; /*!< Reserved, 0x2A */
Kojto 109:9296ab0bfc11 433 }USART_TypeDef;
Kojto 109:9296ab0bfc11 434
Kojto 109:9296ab0bfc11 435 /**
Kojto 109:9296ab0bfc11 436 * @brief Window WATCHDOG
Kojto 109:9296ab0bfc11 437 */
Kojto 109:9296ab0bfc11 438 typedef struct
Kojto 109:9296ab0bfc11 439 {
Kojto 109:9296ab0bfc11 440 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 109:9296ab0bfc11 441 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 109:9296ab0bfc11 442 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 109:9296ab0bfc11 443 }WWDG_TypeDef;
Kojto 109:9296ab0bfc11 444
Kojto 109:9296ab0bfc11 445 /**
Kojto 109:9296ab0bfc11 446 * @}
Kojto 109:9296ab0bfc11 447 */
Kojto 109:9296ab0bfc11 448
Kojto 109:9296ab0bfc11 449 /** @addtogroup Peripheral_memory_map
Kojto 109:9296ab0bfc11 450 * @{
Kojto 109:9296ab0bfc11 451 */
Kojto 109:9296ab0bfc11 452
Kojto 109:9296ab0bfc11 453 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
Kojto 109:9296ab0bfc11 454 #define FLASH_BANK1_END ((uint32_t)0x08007FFF) /*!< FLASH END address of bank1 */
Kojto 109:9296ab0bfc11 455 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
Kojto 109:9296ab0bfc11 456 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
Kojto 109:9296ab0bfc11 457
Kojto 109:9296ab0bfc11 458 /*!< Peripheral memory map */
Kojto 109:9296ab0bfc11 459 #define APBPERIPH_BASE PERIPH_BASE
Kojto 109:9296ab0bfc11 460 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 109:9296ab0bfc11 461 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
Kojto 109:9296ab0bfc11 462
Kojto 109:9296ab0bfc11 463 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 464 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
Kojto 109:9296ab0bfc11 465 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
Kojto 109:9296ab0bfc11 466 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Kojto 109:9296ab0bfc11 467 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Kojto 109:9296ab0bfc11 468 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Kojto 109:9296ab0bfc11 469 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Kojto 109:9296ab0bfc11 470 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Kojto 109:9296ab0bfc11 471 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Kojto 109:9296ab0bfc11 472 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Kojto 109:9296ab0bfc11 473 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Kojto 109:9296ab0bfc11 474 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Kojto 109:9296ab0bfc11 475 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
Kojto 109:9296ab0bfc11 476 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Kojto 109:9296ab0bfc11 477 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Kojto 109:9296ab0bfc11 478 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
Kojto 109:9296ab0bfc11 479 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
Kojto 109:9296ab0bfc11 480 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Kojto 109:9296ab0bfc11 481
Kojto 109:9296ab0bfc11 482 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 483 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Kojto 109:9296ab0bfc11 484 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Kojto 109:9296ab0bfc11 485 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Kojto 109:9296ab0bfc11 486 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Kojto 109:9296ab0bfc11 487 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Kojto 109:9296ab0bfc11 488
Kojto 109:9296ab0bfc11 489 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Kojto 109:9296ab0bfc11 490 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
Kojto 109:9296ab0bfc11 491 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
Kojto 109:9296ab0bfc11 492 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Kojto 109:9296ab0bfc11 493
Kojto 109:9296ab0bfc11 494 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
Kojto 109:9296ab0bfc11 495 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
Kojto 109:9296ab0bfc11 496 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
Kojto 109:9296ab0bfc11 497 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
Kojto 109:9296ab0bfc11 498
Kojto 109:9296ab0bfc11 499 /**
Kojto 109:9296ab0bfc11 500 * @}
Kojto 109:9296ab0bfc11 501 */
Kojto 109:9296ab0bfc11 502
Kojto 109:9296ab0bfc11 503 /** @addtogroup Peripheral_declaration
Kojto 109:9296ab0bfc11 504 * @{
Kojto 109:9296ab0bfc11 505 */
Kojto 109:9296ab0bfc11 506
Kojto 109:9296ab0bfc11 507 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 109:9296ab0bfc11 508 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto 109:9296ab0bfc11 509 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto 109:9296ab0bfc11 510 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 109:9296ab0bfc11 511 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 109:9296ab0bfc11 512 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 109:9296ab0bfc11 513 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 109:9296ab0bfc11 514 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 109:9296ab0bfc11 515 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 109:9296ab0bfc11 516 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 109:9296ab0bfc11 517 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 109:9296ab0bfc11 518 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 109:9296ab0bfc11 519 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto 109:9296ab0bfc11 520 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 109:9296ab0bfc11 521 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 109:9296ab0bfc11 522 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
Kojto 109:9296ab0bfc11 523 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
Kojto 109:9296ab0bfc11 524 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 109:9296ab0bfc11 525 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 109:9296ab0bfc11 526 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 109:9296ab0bfc11 527 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 109:9296ab0bfc11 528 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 109:9296ab0bfc11 529 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 109:9296ab0bfc11 530 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 109:9296ab0bfc11 531 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 109:9296ab0bfc11 532 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 109:9296ab0bfc11 533 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 109:9296ab0bfc11 534 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 109:9296ab0bfc11 535 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 109:9296ab0bfc11 536 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 109:9296ab0bfc11 537 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 109:9296ab0bfc11 538 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto 109:9296ab0bfc11 539 /**
Kojto 109:9296ab0bfc11 540 * @}
Kojto 109:9296ab0bfc11 541 */
Kojto 109:9296ab0bfc11 542
Kojto 109:9296ab0bfc11 543 /** @addtogroup Exported_constants
Kojto 109:9296ab0bfc11 544 * @{
Kojto 109:9296ab0bfc11 545 */
Kojto 109:9296ab0bfc11 546
Kojto 109:9296ab0bfc11 547 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 109:9296ab0bfc11 548 * @{
Kojto 109:9296ab0bfc11 549 */
Kojto 109:9296ab0bfc11 550
Kojto 109:9296ab0bfc11 551 /******************************************************************************/
Kojto 109:9296ab0bfc11 552 /* Peripheral Registers Bits Definition */
Kojto 109:9296ab0bfc11 553 /******************************************************************************/
Kojto 109:9296ab0bfc11 554 /******************************************************************************/
Kojto 109:9296ab0bfc11 555 /* */
Kojto 109:9296ab0bfc11 556 /* Analog to Digital Converter (ADC) */
Kojto 109:9296ab0bfc11 557 /* */
Kojto 109:9296ab0bfc11 558 /******************************************************************************/
Kojto 109:9296ab0bfc11 559 /******************** Bits definition for ADC_ISR register ******************/
Kojto 109:9296ab0bfc11 560 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
Kojto 109:9296ab0bfc11 561 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
Kojto 109:9296ab0bfc11 562 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
Kojto 109:9296ab0bfc11 563 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
Kojto 109:9296ab0bfc11 564 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
Kojto 109:9296ab0bfc11 565 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
Kojto 109:9296ab0bfc11 566
Kojto 109:9296ab0bfc11 567 /* Old EOSEQ bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 568 #define ADC_ISR_EOS ADC_ISR_EOSEQ
Kojto 109:9296ab0bfc11 569
Kojto 109:9296ab0bfc11 570 /******************** Bits definition for ADC_IER register ******************/
Kojto 109:9296ab0bfc11 571 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
Kojto 109:9296ab0bfc11 572 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
Kojto 109:9296ab0bfc11 573 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
Kojto 109:9296ab0bfc11 574 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
Kojto 109:9296ab0bfc11 575 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
Kojto 109:9296ab0bfc11 576 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
Kojto 109:9296ab0bfc11 577
Kojto 109:9296ab0bfc11 578 /* Old EOSEQIE bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 579 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
Kojto 109:9296ab0bfc11 580
Kojto 109:9296ab0bfc11 581 /******************** Bits definition for ADC_CR register *******************/
Kojto 109:9296ab0bfc11 582 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
Kojto 109:9296ab0bfc11 583 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
Kojto 109:9296ab0bfc11 584 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
Kojto 109:9296ab0bfc11 585 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
Kojto 109:9296ab0bfc11 586 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
Kojto 109:9296ab0bfc11 587
Kojto 109:9296ab0bfc11 588 /******************* Bits definition for ADC_CFGR1 register *****************/
Kojto 109:9296ab0bfc11 589 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 109:9296ab0bfc11 590 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 591 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 592 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 593 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 594 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 595 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
Kojto 109:9296ab0bfc11 596 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
Kojto 109:9296ab0bfc11 597 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
Kojto 109:9296ab0bfc11 598 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
Kojto 109:9296ab0bfc11 599 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
Kojto 109:9296ab0bfc11 600 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
Kojto 109:9296ab0bfc11 601 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
Kojto 109:9296ab0bfc11 602 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
Kojto 109:9296ab0bfc11 603 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 604 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 605 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
Kojto 109:9296ab0bfc11 606 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 607 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 608 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 609 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
Kojto 109:9296ab0bfc11 610 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
Kojto 109:9296ab0bfc11 611 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 612 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 613 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
Kojto 109:9296ab0bfc11 614 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
Kojto 109:9296ab0bfc11 615 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
Kojto 109:9296ab0bfc11 616
Kojto 109:9296ab0bfc11 617 /* Old WAIT bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 618 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
Kojto 109:9296ab0bfc11 619
Kojto 109:9296ab0bfc11 620 /******************* Bits definition for ADC_CFGR2 register *****************/
Kojto 109:9296ab0bfc11 621 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
Kojto 109:9296ab0bfc11 622 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
Kojto 109:9296ab0bfc11 623 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
Kojto 109:9296ab0bfc11 624
Kojto 109:9296ab0bfc11 625 /* Old bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 626 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
Kojto 109:9296ab0bfc11 627 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
Kojto 109:9296ab0bfc11 628
Kojto 109:9296ab0bfc11 629 /****************** Bit definition for ADC_SMPR register ********************/
Kojto 109:9296ab0bfc11 630 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 109:9296ab0bfc11 631 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 632 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 633 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 634
Kojto 109:9296ab0bfc11 635 /* Old bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 636 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
Kojto 109:9296ab0bfc11 637 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
Kojto 109:9296ab0bfc11 638 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
Kojto 109:9296ab0bfc11 639 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
Kojto 109:9296ab0bfc11 640
Kojto 109:9296ab0bfc11 641 /******************* Bit definition for ADC_TR register ********************/
Kojto 109:9296ab0bfc11 642 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
Kojto 109:9296ab0bfc11 643 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
Kojto 109:9296ab0bfc11 644
Kojto 109:9296ab0bfc11 645 /* Old bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 646 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
Kojto 109:9296ab0bfc11 647 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
Kojto 109:9296ab0bfc11 648
Kojto 109:9296ab0bfc11 649 /****************** Bit definition for ADC_CHSELR register ******************/
Kojto 109:9296ab0bfc11 650 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
Kojto 109:9296ab0bfc11 651 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
Kojto 109:9296ab0bfc11 652 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
Kojto 109:9296ab0bfc11 653 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
Kojto 109:9296ab0bfc11 654 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
Kojto 109:9296ab0bfc11 655 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
Kojto 109:9296ab0bfc11 656 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
Kojto 109:9296ab0bfc11 657 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
Kojto 109:9296ab0bfc11 658 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
Kojto 109:9296ab0bfc11 659 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
Kojto 109:9296ab0bfc11 660 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
Kojto 109:9296ab0bfc11 661 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
Kojto 109:9296ab0bfc11 662 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
Kojto 109:9296ab0bfc11 663 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
Kojto 109:9296ab0bfc11 664 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
Kojto 109:9296ab0bfc11 665 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
Kojto 109:9296ab0bfc11 666 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
Kojto 109:9296ab0bfc11 667 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
Kojto 109:9296ab0bfc11 668 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
Kojto 109:9296ab0bfc11 669
Kojto 109:9296ab0bfc11 670 /******************** Bit definition for ADC_DR register ********************/
Kojto 109:9296ab0bfc11 671 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
Kojto 109:9296ab0bfc11 672
Kojto 109:9296ab0bfc11 673 /******************* Bit definition for ADC_CCR register ********************/
Kojto 109:9296ab0bfc11 674 #define ADC_CCR_VBATEN ((uint32_t)0x01000000) /*!< Voltage battery enable */
Kojto 109:9296ab0bfc11 675 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
Kojto 109:9296ab0bfc11 676 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
Kojto 109:9296ab0bfc11 677
Kojto 109:9296ab0bfc11 678 /******************************************************************************/
Kojto 109:9296ab0bfc11 679 /* */
Kojto 109:9296ab0bfc11 680 /* CRC calculation unit (CRC) */
Kojto 109:9296ab0bfc11 681 /* */
Kojto 109:9296ab0bfc11 682 /******************************************************************************/
Kojto 109:9296ab0bfc11 683 /******************* Bit definition for CRC_DR register *********************/
Kojto 109:9296ab0bfc11 684 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
Kojto 109:9296ab0bfc11 685
Kojto 109:9296ab0bfc11 686 /******************* Bit definition for CRC_IDR register ********************/
Kojto 109:9296ab0bfc11 687 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
Kojto 109:9296ab0bfc11 688
Kojto 109:9296ab0bfc11 689 /******************** Bit definition for CRC_CR register ********************/
Kojto 109:9296ab0bfc11 690 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
Kojto 109:9296ab0bfc11 691 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
Kojto 109:9296ab0bfc11 692 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
Kojto 109:9296ab0bfc11 693 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
Kojto 109:9296ab0bfc11 694 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
Kojto 109:9296ab0bfc11 695
Kojto 109:9296ab0bfc11 696 /******************* Bit definition for CRC_INIT register *******************/
Kojto 109:9296ab0bfc11 697 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
Kojto 109:9296ab0bfc11 698
Kojto 109:9296ab0bfc11 699 /******************************************************************************/
Kojto 109:9296ab0bfc11 700 /* */
Kojto 109:9296ab0bfc11 701 /* Debug MCU (DBGMCU) */
Kojto 109:9296ab0bfc11 702 /* */
Kojto 109:9296ab0bfc11 703 /******************************************************************************/
Kojto 109:9296ab0bfc11 704
Kojto 109:9296ab0bfc11 705 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Kojto 109:9296ab0bfc11 706 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
Kojto 109:9296ab0bfc11 707
Kojto 109:9296ab0bfc11 708 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
Kojto 109:9296ab0bfc11 709 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 710 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 711 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 712 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 713 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 714 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
Kojto 109:9296ab0bfc11 715 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
Kojto 109:9296ab0bfc11 716 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
Kojto 109:9296ab0bfc11 717 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
Kojto 109:9296ab0bfc11 718 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
Kojto 109:9296ab0bfc11 719 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
Kojto 109:9296ab0bfc11 720 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
Kojto 109:9296ab0bfc11 721 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
Kojto 109:9296ab0bfc11 722 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
Kojto 109:9296ab0bfc11 723 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
Kojto 109:9296ab0bfc11 724 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
Kojto 109:9296ab0bfc11 725
Kojto 109:9296ab0bfc11 726 /****************** Bit definition for DBGMCU_CR register *******************/
Kojto 109:9296ab0bfc11 727 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
Kojto 109:9296ab0bfc11 728 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
Kojto 109:9296ab0bfc11 729
Kojto 109:9296ab0bfc11 730 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
Kojto 109:9296ab0bfc11 731 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 732 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 733 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 734 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
Kojto 109:9296ab0bfc11 735 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
Kojto 109:9296ab0bfc11 736 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
Kojto 109:9296ab0bfc11 737 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
Kojto 109:9296ab0bfc11 738
Kojto 109:9296ab0bfc11 739 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
Kojto 109:9296ab0bfc11 740 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 741 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 742 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
Kojto 109:9296ab0bfc11 743
Kojto 109:9296ab0bfc11 744 /******************************************************************************/
Kojto 109:9296ab0bfc11 745 /* */
Kojto 109:9296ab0bfc11 746 /* DMA Controller (DMA) */
Kojto 109:9296ab0bfc11 747 /* */
Kojto 109:9296ab0bfc11 748 /******************************************************************************/
Kojto 109:9296ab0bfc11 749 /******************* Bit definition for DMA_ISR register ********************/
Kojto 109:9296ab0bfc11 750 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
Kojto 109:9296ab0bfc11 751 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
Kojto 109:9296ab0bfc11 752 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
Kojto 109:9296ab0bfc11 753 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
Kojto 109:9296ab0bfc11 754 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
Kojto 109:9296ab0bfc11 755 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
Kojto 109:9296ab0bfc11 756 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
Kojto 109:9296ab0bfc11 757 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
Kojto 109:9296ab0bfc11 758 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
Kojto 109:9296ab0bfc11 759 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
Kojto 109:9296ab0bfc11 760 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
Kojto 109:9296ab0bfc11 761 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
Kojto 109:9296ab0bfc11 762 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
Kojto 109:9296ab0bfc11 763 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
Kojto 109:9296ab0bfc11 764 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
Kojto 109:9296ab0bfc11 765 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
Kojto 109:9296ab0bfc11 766 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
Kojto 109:9296ab0bfc11 767 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
Kojto 109:9296ab0bfc11 768 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
Kojto 109:9296ab0bfc11 769 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
Kojto 109:9296ab0bfc11 770
Kojto 109:9296ab0bfc11 771 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 109:9296ab0bfc11 772 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
Kojto 109:9296ab0bfc11 773 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
Kojto 109:9296ab0bfc11 774 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
Kojto 109:9296ab0bfc11 775 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
Kojto 109:9296ab0bfc11 776 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
Kojto 109:9296ab0bfc11 777 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
Kojto 109:9296ab0bfc11 778 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
Kojto 109:9296ab0bfc11 779 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
Kojto 109:9296ab0bfc11 780 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
Kojto 109:9296ab0bfc11 781 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
Kojto 109:9296ab0bfc11 782 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
Kojto 109:9296ab0bfc11 783 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
Kojto 109:9296ab0bfc11 784 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
Kojto 109:9296ab0bfc11 785 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
Kojto 109:9296ab0bfc11 786 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
Kojto 109:9296ab0bfc11 787 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
Kojto 109:9296ab0bfc11 788 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
Kojto 109:9296ab0bfc11 789 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
Kojto 109:9296ab0bfc11 790 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
Kojto 109:9296ab0bfc11 791 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
Kojto 109:9296ab0bfc11 792
Kojto 109:9296ab0bfc11 793 /******************* Bit definition for DMA_CCR register ********************/
Kojto 109:9296ab0bfc11 794 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
Kojto 109:9296ab0bfc11 795 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
Kojto 109:9296ab0bfc11 796 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
Kojto 109:9296ab0bfc11 797 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
Kojto 109:9296ab0bfc11 798 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
Kojto 109:9296ab0bfc11 799 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
Kojto 109:9296ab0bfc11 800 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
Kojto 109:9296ab0bfc11 801 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
Kojto 109:9296ab0bfc11 802
Kojto 109:9296ab0bfc11 803 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 109:9296ab0bfc11 804 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 805 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 806
Kojto 109:9296ab0bfc11 807 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
Kojto 109:9296ab0bfc11 808 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 809 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 810
Kojto 109:9296ab0bfc11 811 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 109:9296ab0bfc11 812 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 813 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 814
Kojto 109:9296ab0bfc11 815 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
Kojto 109:9296ab0bfc11 816
Kojto 109:9296ab0bfc11 817 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 109:9296ab0bfc11 818 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
Kojto 109:9296ab0bfc11 819
Kojto 109:9296ab0bfc11 820 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 109:9296ab0bfc11 821 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
Kojto 109:9296ab0bfc11 822
Kojto 109:9296ab0bfc11 823 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 109:9296ab0bfc11 824 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
Kojto 109:9296ab0bfc11 825
Kojto 109:9296ab0bfc11 826 /******************************************************************************/
Kojto 109:9296ab0bfc11 827 /* */
Kojto 109:9296ab0bfc11 828 /* External Interrupt/Event Controller (EXTI) */
Kojto 109:9296ab0bfc11 829 /* */
Kojto 109:9296ab0bfc11 830 /******************************************************************************/
Kojto 109:9296ab0bfc11 831 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 109:9296ab0bfc11 832 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
Kojto 109:9296ab0bfc11 833 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
Kojto 109:9296ab0bfc11 834 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
Kojto 109:9296ab0bfc11 835 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
Kojto 109:9296ab0bfc11 836 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
Kojto 109:9296ab0bfc11 837 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
Kojto 109:9296ab0bfc11 838 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
Kojto 109:9296ab0bfc11 839 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
Kojto 109:9296ab0bfc11 840 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
Kojto 109:9296ab0bfc11 841 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
Kojto 109:9296ab0bfc11 842 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
Kojto 109:9296ab0bfc11 843 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
Kojto 109:9296ab0bfc11 844 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
Kojto 109:9296ab0bfc11 845 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
Kojto 109:9296ab0bfc11 846 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
Kojto 109:9296ab0bfc11 847 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
Kojto 109:9296ab0bfc11 848 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
Kojto 109:9296ab0bfc11 849 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
Kojto 109:9296ab0bfc11 850 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
Kojto 109:9296ab0bfc11 851 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
Kojto 109:9296ab0bfc11 852 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
Kojto 109:9296ab0bfc11 853 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
Kojto 109:9296ab0bfc11 854 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
Kojto 109:9296ab0bfc11 855 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
Kojto 109:9296ab0bfc11 856
Kojto 109:9296ab0bfc11 857 /****************** Bit definition for EXTI_EMR register ********************/
Kojto 109:9296ab0bfc11 858 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
Kojto 109:9296ab0bfc11 859 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
Kojto 109:9296ab0bfc11 860 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
Kojto 109:9296ab0bfc11 861 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
Kojto 109:9296ab0bfc11 862 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
Kojto 109:9296ab0bfc11 863 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
Kojto 109:9296ab0bfc11 864 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
Kojto 109:9296ab0bfc11 865 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
Kojto 109:9296ab0bfc11 866 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
Kojto 109:9296ab0bfc11 867 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
Kojto 109:9296ab0bfc11 868 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
Kojto 109:9296ab0bfc11 869 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
Kojto 109:9296ab0bfc11 870 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
Kojto 109:9296ab0bfc11 871 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
Kojto 109:9296ab0bfc11 872 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
Kojto 109:9296ab0bfc11 873 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
Kojto 109:9296ab0bfc11 874 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
Kojto 109:9296ab0bfc11 875 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
Kojto 109:9296ab0bfc11 876 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
Kojto 109:9296ab0bfc11 877 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
Kojto 109:9296ab0bfc11 878 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
Kojto 109:9296ab0bfc11 879 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
Kojto 109:9296ab0bfc11 880 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
Kojto 109:9296ab0bfc11 881 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
Kojto 109:9296ab0bfc11 882
Kojto 109:9296ab0bfc11 883 /******************* Bit definition for EXTI_RTSR register ******************/
Kojto 109:9296ab0bfc11 884 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
Kojto 109:9296ab0bfc11 885 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
Kojto 109:9296ab0bfc11 886 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
Kojto 109:9296ab0bfc11 887 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
Kojto 109:9296ab0bfc11 888 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
Kojto 109:9296ab0bfc11 889 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
Kojto 109:9296ab0bfc11 890 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
Kojto 109:9296ab0bfc11 891 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
Kojto 109:9296ab0bfc11 892 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
Kojto 109:9296ab0bfc11 893 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
Kojto 109:9296ab0bfc11 894 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
Kojto 109:9296ab0bfc11 895 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
Kojto 109:9296ab0bfc11 896 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
Kojto 109:9296ab0bfc11 897 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
Kojto 109:9296ab0bfc11 898 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
Kojto 109:9296ab0bfc11 899 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
Kojto 109:9296ab0bfc11 900 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
Kojto 109:9296ab0bfc11 901 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
Kojto 109:9296ab0bfc11 902 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
Kojto 109:9296ab0bfc11 903
Kojto 109:9296ab0bfc11 904 /******************* Bit definition for EXTI_FTSR register *******************/
Kojto 109:9296ab0bfc11 905 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
Kojto 109:9296ab0bfc11 906 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
Kojto 109:9296ab0bfc11 907 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
Kojto 109:9296ab0bfc11 908 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
Kojto 109:9296ab0bfc11 909 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
Kojto 109:9296ab0bfc11 910 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
Kojto 109:9296ab0bfc11 911 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
Kojto 109:9296ab0bfc11 912 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
Kojto 109:9296ab0bfc11 913 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
Kojto 109:9296ab0bfc11 914 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
Kojto 109:9296ab0bfc11 915 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
Kojto 109:9296ab0bfc11 916 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
Kojto 109:9296ab0bfc11 917 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
Kojto 109:9296ab0bfc11 918 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
Kojto 109:9296ab0bfc11 919 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
Kojto 109:9296ab0bfc11 920 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
Kojto 109:9296ab0bfc11 921 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
Kojto 109:9296ab0bfc11 922 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
Kojto 109:9296ab0bfc11 923 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
Kojto 109:9296ab0bfc11 924
Kojto 109:9296ab0bfc11 925 /******************* Bit definition for EXTI_SWIER register *******************/
Kojto 109:9296ab0bfc11 926 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
Kojto 109:9296ab0bfc11 927 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
Kojto 109:9296ab0bfc11 928 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
Kojto 109:9296ab0bfc11 929 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
Kojto 109:9296ab0bfc11 930 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
Kojto 109:9296ab0bfc11 931 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
Kojto 109:9296ab0bfc11 932 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
Kojto 109:9296ab0bfc11 933 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
Kojto 109:9296ab0bfc11 934 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
Kojto 109:9296ab0bfc11 935 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
Kojto 109:9296ab0bfc11 936 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
Kojto 109:9296ab0bfc11 937 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
Kojto 109:9296ab0bfc11 938 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
Kojto 109:9296ab0bfc11 939 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
Kojto 109:9296ab0bfc11 940 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
Kojto 109:9296ab0bfc11 941 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
Kojto 109:9296ab0bfc11 942 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
Kojto 109:9296ab0bfc11 943 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
Kojto 109:9296ab0bfc11 944 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
Kojto 109:9296ab0bfc11 945
Kojto 109:9296ab0bfc11 946 /****************** Bit definition for EXTI_PR register *********************/
Kojto 109:9296ab0bfc11 947 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
Kojto 109:9296ab0bfc11 948 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
Kojto 109:9296ab0bfc11 949 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
Kojto 109:9296ab0bfc11 950 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
Kojto 109:9296ab0bfc11 951 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
Kojto 109:9296ab0bfc11 952 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
Kojto 109:9296ab0bfc11 953 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
Kojto 109:9296ab0bfc11 954 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
Kojto 109:9296ab0bfc11 955 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
Kojto 109:9296ab0bfc11 956 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
Kojto 109:9296ab0bfc11 957 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
Kojto 109:9296ab0bfc11 958 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
Kojto 109:9296ab0bfc11 959 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
Kojto 109:9296ab0bfc11 960 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
Kojto 109:9296ab0bfc11 961 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
Kojto 109:9296ab0bfc11 962 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
Kojto 109:9296ab0bfc11 963 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
Kojto 109:9296ab0bfc11 964 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
Kojto 109:9296ab0bfc11 965 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
Kojto 109:9296ab0bfc11 966
Kojto 109:9296ab0bfc11 967 /******************************************************************************/
Kojto 109:9296ab0bfc11 968 /* */
Kojto 109:9296ab0bfc11 969 /* FLASH and Option Bytes Registers */
Kojto 109:9296ab0bfc11 970 /* */
Kojto 109:9296ab0bfc11 971 /******************************************************************************/
Kojto 109:9296ab0bfc11 972
Kojto 109:9296ab0bfc11 973 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 109:9296ab0bfc11 974 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
Kojto 109:9296ab0bfc11 975
Kojto 109:9296ab0bfc11 976 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
Kojto 109:9296ab0bfc11 977 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
Kojto 109:9296ab0bfc11 978
Kojto 109:9296ab0bfc11 979 /****************** Bit definition for FLASH_KEYR register ******************/
Kojto 109:9296ab0bfc11 980 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
Kojto 109:9296ab0bfc11 981
Kojto 109:9296ab0bfc11 982 /***************** Bit definition for FLASH_OPTKEYR register ****************/
Kojto 109:9296ab0bfc11 983 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
Kojto 109:9296ab0bfc11 984
Kojto 109:9296ab0bfc11 985 /****************** FLASH Keys **********************************************/
Kojto 109:9296ab0bfc11 986 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
Kojto 109:9296ab0bfc11 987 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
Kojto 109:9296ab0bfc11 988 to unlock the write access to the FPEC. */
Kojto 109:9296ab0bfc11 989
Kojto 109:9296ab0bfc11 990 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
Kojto 109:9296ab0bfc11 991 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
Kojto 109:9296ab0bfc11 992 unlock the write access to the option byte block */
Kojto 109:9296ab0bfc11 993
Kojto 109:9296ab0bfc11 994 /****************** Bit definition for FLASH_SR register *******************/
Kojto 109:9296ab0bfc11 995 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
Kojto 109:9296ab0bfc11 996 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
Kojto 109:9296ab0bfc11 997 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
Kojto 109:9296ab0bfc11 998 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
Kojto 109:9296ab0bfc11 999 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
Kojto 109:9296ab0bfc11 1000
Kojto 109:9296ab0bfc11 1001 /******************* Bit definition for FLASH_CR register *******************/
Kojto 109:9296ab0bfc11 1002 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
Kojto 109:9296ab0bfc11 1003 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
Kojto 109:9296ab0bfc11 1004 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
Kojto 109:9296ab0bfc11 1005 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
Kojto 109:9296ab0bfc11 1006 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
Kojto 109:9296ab0bfc11 1007 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
Kojto 109:9296ab0bfc11 1008 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
Kojto 109:9296ab0bfc11 1009 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
Kojto 109:9296ab0bfc11 1010 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
Kojto 109:9296ab0bfc11 1011 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
Kojto 109:9296ab0bfc11 1012 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
Kojto 109:9296ab0bfc11 1013
Kojto 109:9296ab0bfc11 1014 /******************* Bit definition for FLASH_AR register *******************/
Kojto 109:9296ab0bfc11 1015 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
Kojto 109:9296ab0bfc11 1016
Kojto 109:9296ab0bfc11 1017 /****************** Bit definition for FLASH_OBR register *******************/
Kojto 109:9296ab0bfc11 1018 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
Kojto 109:9296ab0bfc11 1019 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
Kojto 109:9296ab0bfc11 1020 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
Kojto 109:9296ab0bfc11 1021
Kojto 109:9296ab0bfc11 1022 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
Kojto 109:9296ab0bfc11 1023 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
Kojto 109:9296ab0bfc11 1024 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
Kojto 109:9296ab0bfc11 1025 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
Kojto 109:9296ab0bfc11 1026 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
Kojto 109:9296ab0bfc11 1027 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
Kojto 109:9296ab0bfc11 1028 #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
Kojto 109:9296ab0bfc11 1029
Kojto 109:9296ab0bfc11 1030 /* Old BOOT1 bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 1031 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
Kojto 109:9296ab0bfc11 1032
Kojto 109:9296ab0bfc11 1033 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
Kojto 109:9296ab0bfc11 1034 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
Kojto 109:9296ab0bfc11 1035
Kojto 109:9296ab0bfc11 1036 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 109:9296ab0bfc11 1037 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
Kojto 109:9296ab0bfc11 1038
Kojto 109:9296ab0bfc11 1039 /*----------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 1040
Kojto 109:9296ab0bfc11 1041 /****************** Bit definition for OB_RDP register **********************/
Kojto 109:9296ab0bfc11 1042 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
Kojto 109:9296ab0bfc11 1043 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
Kojto 109:9296ab0bfc11 1044
Kojto 109:9296ab0bfc11 1045 /****************** Bit definition for OB_USER register *********************/
Kojto 109:9296ab0bfc11 1046 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
Kojto 109:9296ab0bfc11 1047 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
Kojto 109:9296ab0bfc11 1048
Kojto 109:9296ab0bfc11 1049 /****************** Bit definition for OB_WRP0 register *********************/
Kojto 109:9296ab0bfc11 1050 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
Kojto 109:9296ab0bfc11 1051 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
Kojto 109:9296ab0bfc11 1052
Kojto 109:9296ab0bfc11 1053 /******************************************************************************/
Kojto 109:9296ab0bfc11 1054 /* */
Kojto 109:9296ab0bfc11 1055 /* General Purpose IOs (GPIO) */
Kojto 109:9296ab0bfc11 1056 /* */
Kojto 109:9296ab0bfc11 1057 /******************************************************************************/
Kojto 109:9296ab0bfc11 1058 /******************* Bit definition for GPIO_MODER register *****************/
Kojto 109:9296ab0bfc11 1059 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
Kojto 109:9296ab0bfc11 1060 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1061 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1062 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
Kojto 109:9296ab0bfc11 1063 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1064 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1065 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 1066 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1067 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1068 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 1069 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1070 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1071 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
Kojto 109:9296ab0bfc11 1072 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1073 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1074 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
Kojto 109:9296ab0bfc11 1075 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1076 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1077 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
Kojto 109:9296ab0bfc11 1078 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1079 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1080 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
Kojto 109:9296ab0bfc11 1081 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1082 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1083 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
Kojto 109:9296ab0bfc11 1084 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1085 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1086 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
Kojto 109:9296ab0bfc11 1087 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1088 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 1089 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 1090 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1091 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1092 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
Kojto 109:9296ab0bfc11 1093 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1094 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 1095 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
Kojto 109:9296ab0bfc11 1096 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 1097 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 1098 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
Kojto 109:9296ab0bfc11 1099 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 1100 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 1101 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 1102 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 1103 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 1104 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
Kojto 109:9296ab0bfc11 1105 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 1106 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 1107
Kojto 109:9296ab0bfc11 1108 /****************** Bit definition for GPIO_OTYPER register *****************/
Kojto 109:9296ab0bfc11 1109 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1110 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1111 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1112 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1113 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1114 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1115 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1116 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1117 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1118 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1119 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1120 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1121 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1122 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1123 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1124 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1125
Kojto 109:9296ab0bfc11 1126 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Kojto 109:9296ab0bfc11 1127 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
Kojto 109:9296ab0bfc11 1128 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1129 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1130 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
Kojto 109:9296ab0bfc11 1131 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1132 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1133 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 1134 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1135 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1136 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 1137 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1138 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1139 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
Kojto 109:9296ab0bfc11 1140 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1141 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1142 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
Kojto 109:9296ab0bfc11 1143 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1144 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1145 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
Kojto 109:9296ab0bfc11 1146 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1147 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1148 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
Kojto 109:9296ab0bfc11 1149 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1150 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1151 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
Kojto 109:9296ab0bfc11 1152 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1153 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1154 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
Kojto 109:9296ab0bfc11 1155 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1156 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 1157 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 1158 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1159 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1160 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
Kojto 109:9296ab0bfc11 1161 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1162 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 1163 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
Kojto 109:9296ab0bfc11 1164 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 1165 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 1166 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
Kojto 109:9296ab0bfc11 1167 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 1168 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 1169 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 1170 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 1171 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 1172 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
Kojto 109:9296ab0bfc11 1173 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 1174 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 1175
Kojto 109:9296ab0bfc11 1176 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
Kojto 109:9296ab0bfc11 1177 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
Kojto 109:9296ab0bfc11 1178 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
Kojto 109:9296ab0bfc11 1179 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
Kojto 109:9296ab0bfc11 1180 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
Kojto 109:9296ab0bfc11 1181 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
Kojto 109:9296ab0bfc11 1182 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
Kojto 109:9296ab0bfc11 1183 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
Kojto 109:9296ab0bfc11 1184 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
Kojto 109:9296ab0bfc11 1185 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
Kojto 109:9296ab0bfc11 1186 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
Kojto 109:9296ab0bfc11 1187 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
Kojto 109:9296ab0bfc11 1188 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
Kojto 109:9296ab0bfc11 1189 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
Kojto 109:9296ab0bfc11 1190 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
Kojto 109:9296ab0bfc11 1191 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
Kojto 109:9296ab0bfc11 1192 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
Kojto 109:9296ab0bfc11 1193 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
Kojto 109:9296ab0bfc11 1194 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
Kojto 109:9296ab0bfc11 1195 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
Kojto 109:9296ab0bfc11 1196 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
Kojto 109:9296ab0bfc11 1197 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
Kojto 109:9296ab0bfc11 1198 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
Kojto 109:9296ab0bfc11 1199 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
Kojto 109:9296ab0bfc11 1200 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
Kojto 109:9296ab0bfc11 1201 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
Kojto 109:9296ab0bfc11 1202 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
Kojto 109:9296ab0bfc11 1203 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
Kojto 109:9296ab0bfc11 1204 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
Kojto 109:9296ab0bfc11 1205 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
Kojto 109:9296ab0bfc11 1206 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
Kojto 109:9296ab0bfc11 1207 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
Kojto 109:9296ab0bfc11 1208 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
Kojto 109:9296ab0bfc11 1209 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
Kojto 109:9296ab0bfc11 1210 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
Kojto 109:9296ab0bfc11 1211 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
Kojto 109:9296ab0bfc11 1212 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
Kojto 109:9296ab0bfc11 1213 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
Kojto 109:9296ab0bfc11 1214 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
Kojto 109:9296ab0bfc11 1215 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
Kojto 109:9296ab0bfc11 1216 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
Kojto 109:9296ab0bfc11 1217 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
Kojto 109:9296ab0bfc11 1218 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
Kojto 109:9296ab0bfc11 1219 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
Kojto 109:9296ab0bfc11 1220 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
Kojto 109:9296ab0bfc11 1221 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
Kojto 109:9296ab0bfc11 1222 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
Kojto 109:9296ab0bfc11 1223 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
Kojto 109:9296ab0bfc11 1224 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
Kojto 109:9296ab0bfc11 1225
Kojto 109:9296ab0bfc11 1226 /******************* Bit definition for GPIO_PUPDR register ******************/
Kojto 109:9296ab0bfc11 1227 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
Kojto 109:9296ab0bfc11 1228 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1229 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1230 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
Kojto 109:9296ab0bfc11 1231 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1232 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1233 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 1234 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1235 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1236 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
Kojto 109:9296ab0bfc11 1237 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1238 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1239 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
Kojto 109:9296ab0bfc11 1240 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1241 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1242 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
Kojto 109:9296ab0bfc11 1243 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1244 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1245 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
Kojto 109:9296ab0bfc11 1246 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1247 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1248 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
Kojto 109:9296ab0bfc11 1249 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1250 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1251 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
Kojto 109:9296ab0bfc11 1252 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1253 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1254 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
Kojto 109:9296ab0bfc11 1255 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1256 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 1257 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 1258 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1259 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1260 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
Kojto 109:9296ab0bfc11 1261 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1262 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 1263 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
Kojto 109:9296ab0bfc11 1264 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 1265 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 1266 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
Kojto 109:9296ab0bfc11 1267 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 1268 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 1269 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 1270 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 1271 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 1272 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
Kojto 109:9296ab0bfc11 1273 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 1274 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 1275
Kojto 109:9296ab0bfc11 1276 /******************* Bit definition for GPIO_IDR register *******************/
Kojto 109:9296ab0bfc11 1277 #define GPIO_IDR_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1278 #define GPIO_IDR_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1279 #define GPIO_IDR_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1280 #define GPIO_IDR_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1281 #define GPIO_IDR_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1282 #define GPIO_IDR_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1283 #define GPIO_IDR_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1284 #define GPIO_IDR_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1285 #define GPIO_IDR_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1286 #define GPIO_IDR_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1287 #define GPIO_IDR_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1288 #define GPIO_IDR_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1289 #define GPIO_IDR_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1290 #define GPIO_IDR_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1291 #define GPIO_IDR_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1292 #define GPIO_IDR_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1293
Kojto 109:9296ab0bfc11 1294 /****************** Bit definition for GPIO_ODR register ********************/
Kojto 109:9296ab0bfc11 1295 #define GPIO_ODR_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1296 #define GPIO_ODR_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1297 #define GPIO_ODR_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1298 #define GPIO_ODR_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1299 #define GPIO_ODR_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1300 #define GPIO_ODR_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1301 #define GPIO_ODR_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1302 #define GPIO_ODR_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1303 #define GPIO_ODR_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1304 #define GPIO_ODR_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1305 #define GPIO_ODR_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1306 #define GPIO_ODR_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1307 #define GPIO_ODR_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1308 #define GPIO_ODR_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1309 #define GPIO_ODR_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1310 #define GPIO_ODR_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1311
Kojto 109:9296ab0bfc11 1312 /****************** Bit definition for GPIO_BSRR register ********************/
Kojto 109:9296ab0bfc11 1313 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1314 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1315 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1316 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1317 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1318 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1319 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1320 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1321 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1322 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1323 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1324 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1325 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1326 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1327 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1328 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1329 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1330 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1331 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1332 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 1333 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1334 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1335 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1336 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 1337 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 1338 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 1339 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 1340 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 1341 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 1342 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 1343 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 1344 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 1345
Kojto 109:9296ab0bfc11 1346 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 109:9296ab0bfc11 1347 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1348 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1349 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1350 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1351 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1352 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1353 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1354 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1355 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1356 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1357 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1358 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1359 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1360 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1361 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1362 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1363 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1364
Kojto 109:9296ab0bfc11 1365 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 109:9296ab0bfc11 1366 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 1367 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
Kojto 109:9296ab0bfc11 1368 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 1369 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
Kojto 109:9296ab0bfc11 1370 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 1371 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
Kojto 109:9296ab0bfc11 1372 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 1373 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
Kojto 109:9296ab0bfc11 1374
Kojto 109:9296ab0bfc11 1375 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 109:9296ab0bfc11 1376 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 1377 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
Kojto 109:9296ab0bfc11 1378 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 1379 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
Kojto 109:9296ab0bfc11 1380 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 1381 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
Kojto 109:9296ab0bfc11 1382 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 1383 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
Kojto 109:9296ab0bfc11 1384
Kojto 109:9296ab0bfc11 1385 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 109:9296ab0bfc11 1386 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1387 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1388 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1389 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1390 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1391 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1392 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1393 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1394 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1395 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1396 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1397 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1398 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1399 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1400 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1401 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1402
Kojto 109:9296ab0bfc11 1403 /******************************************************************************/
Kojto 109:9296ab0bfc11 1404 /* */
Kojto 109:9296ab0bfc11 1405 /* Inter-integrated Circuit Interface (I2C) */
Kojto 109:9296ab0bfc11 1406 /* */
Kojto 109:9296ab0bfc11 1407 /******************************************************************************/
Kojto 109:9296ab0bfc11 1408
Kojto 109:9296ab0bfc11 1409 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 109:9296ab0bfc11 1410 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
Kojto 109:9296ab0bfc11 1411 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
Kojto 109:9296ab0bfc11 1412 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
Kojto 109:9296ab0bfc11 1413 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
Kojto 109:9296ab0bfc11 1414 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
Kojto 109:9296ab0bfc11 1415 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
Kojto 109:9296ab0bfc11 1416 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
Kojto 109:9296ab0bfc11 1417 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
Kojto 109:9296ab0bfc11 1418 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
Kojto 109:9296ab0bfc11 1419 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
Kojto 109:9296ab0bfc11 1420 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
Kojto 109:9296ab0bfc11 1421 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
Kojto 109:9296ab0bfc11 1422 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
Kojto 109:9296ab0bfc11 1423 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
Kojto 109:9296ab0bfc11 1424 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
Kojto 109:9296ab0bfc11 1425 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
Kojto 109:9296ab0bfc11 1426 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
Kojto 109:9296ab0bfc11 1427 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
Kojto 109:9296ab0bfc11 1428 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
Kojto 109:9296ab0bfc11 1429 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
Kojto 109:9296ab0bfc11 1430 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
Kojto 109:9296ab0bfc11 1431
Kojto 109:9296ab0bfc11 1432 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 109:9296ab0bfc11 1433 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
Kojto 109:9296ab0bfc11 1434 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
Kojto 109:9296ab0bfc11 1435 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
Kojto 109:9296ab0bfc11 1436 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
Kojto 109:9296ab0bfc11 1437 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
Kojto 109:9296ab0bfc11 1438 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
Kojto 109:9296ab0bfc11 1439 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
Kojto 109:9296ab0bfc11 1440 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
Kojto 109:9296ab0bfc11 1441 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
Kojto 109:9296ab0bfc11 1442 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
Kojto 109:9296ab0bfc11 1443 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
Kojto 109:9296ab0bfc11 1444
Kojto 109:9296ab0bfc11 1445 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 109:9296ab0bfc11 1446 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
Kojto 109:9296ab0bfc11 1447 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
Kojto 109:9296ab0bfc11 1448 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
Kojto 109:9296ab0bfc11 1449
Kojto 109:9296ab0bfc11 1450 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 109:9296ab0bfc11 1451 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
Kojto 109:9296ab0bfc11 1452 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
Kojto 109:9296ab0bfc11 1453 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
Kojto 109:9296ab0bfc11 1454
Kojto 109:9296ab0bfc11 1455 /******************* Bit definition for I2C_TIMINGR register ****************/
Kojto 109:9296ab0bfc11 1456 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
Kojto 109:9296ab0bfc11 1457 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
Kojto 109:9296ab0bfc11 1458 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
Kojto 109:9296ab0bfc11 1459 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
Kojto 109:9296ab0bfc11 1460 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
Kojto 109:9296ab0bfc11 1461
Kojto 109:9296ab0bfc11 1462 /******************* Bit definition for I2C_TIMEOUTR register ****************/
Kojto 109:9296ab0bfc11 1463 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
Kojto 109:9296ab0bfc11 1464 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
Kojto 109:9296ab0bfc11 1465 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
Kojto 109:9296ab0bfc11 1466 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
Kojto 109:9296ab0bfc11 1467 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
Kojto 109:9296ab0bfc11 1468
Kojto 109:9296ab0bfc11 1469 /****************** Bit definition for I2C_ISR register ********************/
Kojto 109:9296ab0bfc11 1470 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
Kojto 109:9296ab0bfc11 1471 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
Kojto 109:9296ab0bfc11 1472 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
Kojto 109:9296ab0bfc11 1473 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
Kojto 109:9296ab0bfc11 1474 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
Kojto 109:9296ab0bfc11 1475 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
Kojto 109:9296ab0bfc11 1476 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
Kojto 109:9296ab0bfc11 1477 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
Kojto 109:9296ab0bfc11 1478 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
Kojto 109:9296ab0bfc11 1479 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
Kojto 109:9296ab0bfc11 1480 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
Kojto 109:9296ab0bfc11 1481 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
Kojto 109:9296ab0bfc11 1482 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
Kojto 109:9296ab0bfc11 1483 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
Kojto 109:9296ab0bfc11 1484 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
Kojto 109:9296ab0bfc11 1485 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
Kojto 109:9296ab0bfc11 1486 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
Kojto 109:9296ab0bfc11 1487
Kojto 109:9296ab0bfc11 1488 /****************** Bit definition for I2C_ICR register ********************/
Kojto 109:9296ab0bfc11 1489 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
Kojto 109:9296ab0bfc11 1490 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
Kojto 109:9296ab0bfc11 1491 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
Kojto 109:9296ab0bfc11 1492 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
Kojto 109:9296ab0bfc11 1493 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
Kojto 109:9296ab0bfc11 1494 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
Kojto 109:9296ab0bfc11 1495 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
Kojto 109:9296ab0bfc11 1496 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
Kojto 109:9296ab0bfc11 1497 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
Kojto 109:9296ab0bfc11 1498
Kojto 109:9296ab0bfc11 1499 /****************** Bit definition for I2C_PECR register *******************/
Kojto 109:9296ab0bfc11 1500 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
Kojto 109:9296ab0bfc11 1501
Kojto 109:9296ab0bfc11 1502 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 109:9296ab0bfc11 1503 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
Kojto 109:9296ab0bfc11 1504
Kojto 109:9296ab0bfc11 1505 /****************** Bit definition for I2C_TXDR register *******************/
Kojto 109:9296ab0bfc11 1506 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
Kojto 109:9296ab0bfc11 1507
Kojto 109:9296ab0bfc11 1508 /*****************************************************************************/
Kojto 109:9296ab0bfc11 1509 /* */
Kojto 109:9296ab0bfc11 1510 /* Independent WATCHDOG (IWDG) */
Kojto 109:9296ab0bfc11 1511 /* */
Kojto 109:9296ab0bfc11 1512 /*****************************************************************************/
Kojto 109:9296ab0bfc11 1513 /******************* Bit definition for IWDG_KR register *******************/
Kojto 109:9296ab0bfc11 1514 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
Kojto 109:9296ab0bfc11 1515
Kojto 109:9296ab0bfc11 1516 /******************* Bit definition for IWDG_PR register *******************/
Kojto 109:9296ab0bfc11 1517 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
Kojto 109:9296ab0bfc11 1518 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1519 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1520 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 1521
Kojto 109:9296ab0bfc11 1522 /******************* Bit definition for IWDG_RLR register ******************/
Kojto 109:9296ab0bfc11 1523 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
Kojto 109:9296ab0bfc11 1524
Kojto 109:9296ab0bfc11 1525 /******************* Bit definition for IWDG_SR register *******************/
Kojto 109:9296ab0bfc11 1526 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
Kojto 109:9296ab0bfc11 1527 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
Kojto 109:9296ab0bfc11 1528 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
Kojto 109:9296ab0bfc11 1529
Kojto 109:9296ab0bfc11 1530 /******************* Bit definition for IWDG_KR register *******************/
Kojto 109:9296ab0bfc11 1531 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
Kojto 109:9296ab0bfc11 1532
Kojto 109:9296ab0bfc11 1533 /*****************************************************************************/
Kojto 109:9296ab0bfc11 1534 /* */
Kojto 109:9296ab0bfc11 1535 /* Power Control (PWR) */
Kojto 109:9296ab0bfc11 1536 /* */
Kojto 109:9296ab0bfc11 1537 /*****************************************************************************/
Kojto 109:9296ab0bfc11 1538
Kojto 109:9296ab0bfc11 1539 /******************** Bit definition for PWR_CR register *******************/
Kojto 109:9296ab0bfc11 1540 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
Kojto 109:9296ab0bfc11 1541 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
Kojto 109:9296ab0bfc11 1542 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
Kojto 109:9296ab0bfc11 1543 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
Kojto 109:9296ab0bfc11 1544 #define PWR_CR_PVDE ((uint32_t)0x00000010) /*!< Power Voltage Detector Enable */
Kojto 109:9296ab0bfc11 1545
Kojto 109:9296ab0bfc11 1546 #define PWR_CR_PLS ((uint32_t)0x000000E0) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 109:9296ab0bfc11 1547 #define PWR_CR_PLS_0 ((uint32_t)0x00000020) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1548 #define PWR_CR_PLS_1 ((uint32_t)0x00000040) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1549 #define PWR_CR_PLS_2 ((uint32_t)0x00000080) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 1550
Kojto 109:9296ab0bfc11 1551 /*!< PVD level configuration */
Kojto 109:9296ab0bfc11 1552 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000) /*!< PVD level 0 */
Kojto 109:9296ab0bfc11 1553 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020) /*!< PVD level 1 */
Kojto 109:9296ab0bfc11 1554 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040) /*!< PVD level 2 */
Kojto 109:9296ab0bfc11 1555 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060) /*!< PVD level 3 */
Kojto 109:9296ab0bfc11 1556 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080) /*!< PVD level 4 */
Kojto 109:9296ab0bfc11 1557 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0) /*!< PVD level 5 */
Kojto 109:9296ab0bfc11 1558 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0) /*!< PVD level 6 */
Kojto 109:9296ab0bfc11 1559 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0) /*!< PVD level 7 */
Kojto 109:9296ab0bfc11 1560
Kojto 109:9296ab0bfc11 1561 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
Kojto 109:9296ab0bfc11 1562
Kojto 109:9296ab0bfc11 1563 /******************* Bit definition for PWR_CSR register *******************/
Kojto 109:9296ab0bfc11 1564 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
Kojto 109:9296ab0bfc11 1565 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
Kojto 109:9296ab0bfc11 1566 #define PWR_CSR_PVDO ((uint32_t)0x00000004) /*!< PVD Output */
Kojto 109:9296ab0bfc11 1567 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008) /*!< Internal voltage reference (VREFINT) ready flag */
Kojto 109:9296ab0bfc11 1568
Kojto 109:9296ab0bfc11 1569 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
Kojto 109:9296ab0bfc11 1570 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
Kojto 109:9296ab0bfc11 1571
Kojto 109:9296ab0bfc11 1572 /*****************************************************************************/
Kojto 109:9296ab0bfc11 1573 /* */
Kojto 109:9296ab0bfc11 1574 /* Reset and Clock Control */
Kojto 109:9296ab0bfc11 1575 /* */
Kojto 109:9296ab0bfc11 1576 /*****************************************************************************/
Kojto 109:9296ab0bfc11 1577
Kojto 109:9296ab0bfc11 1578 /******************** Bit definition for RCC_CR register *******************/
Kojto 109:9296ab0bfc11 1579 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
Kojto 109:9296ab0bfc11 1580 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
Kojto 109:9296ab0bfc11 1581
Kojto 109:9296ab0bfc11 1582 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
Kojto 109:9296ab0bfc11 1583 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 1584 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 1585 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 1586 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 1587 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 1588
Kojto 109:9296ab0bfc11 1589 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
Kojto 109:9296ab0bfc11 1590 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 1591 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 1592 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 1593 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 1594 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 1595 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 1596 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 1597 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
Kojto 109:9296ab0bfc11 1598
Kojto 109:9296ab0bfc11 1599 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
Kojto 109:9296ab0bfc11 1600 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
Kojto 109:9296ab0bfc11 1601 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
Kojto 109:9296ab0bfc11 1602 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
Kojto 109:9296ab0bfc11 1603 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
Kojto 109:9296ab0bfc11 1604 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
Kojto 109:9296ab0bfc11 1605
Kojto 109:9296ab0bfc11 1606 /******************** Bit definition for RCC_CFGR register *****************/
Kojto 109:9296ab0bfc11 1607 /*!< SW configuration */
Kojto 109:9296ab0bfc11 1608 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
Kojto 109:9296ab0bfc11 1609 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1610 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1611
Kojto 109:9296ab0bfc11 1612 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
Kojto 109:9296ab0bfc11 1613 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
Kojto 109:9296ab0bfc11 1614 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
Kojto 109:9296ab0bfc11 1615
Kojto 109:9296ab0bfc11 1616 /*!< SWS configuration */
Kojto 109:9296ab0bfc11 1617 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 109:9296ab0bfc11 1618 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1619 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1620
Kojto 109:9296ab0bfc11 1621 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
Kojto 109:9296ab0bfc11 1622 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
Kojto 109:9296ab0bfc11 1623 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
Kojto 109:9296ab0bfc11 1624
Kojto 109:9296ab0bfc11 1625 /*!< HPRE configuration */
Kojto 109:9296ab0bfc11 1626 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 109:9296ab0bfc11 1627 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1628 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1629 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 1630 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 1631
Kojto 109:9296ab0bfc11 1632 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
Kojto 109:9296ab0bfc11 1633 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
Kojto 109:9296ab0bfc11 1634 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
Kojto 109:9296ab0bfc11 1635 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
Kojto 109:9296ab0bfc11 1636 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
Kojto 109:9296ab0bfc11 1637 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
Kojto 109:9296ab0bfc11 1638 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
Kojto 109:9296ab0bfc11 1639 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
Kojto 109:9296ab0bfc11 1640 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
Kojto 109:9296ab0bfc11 1641
Kojto 109:9296ab0bfc11 1642 /*!< PPRE configuration */
Kojto 109:9296ab0bfc11 1643 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
Kojto 109:9296ab0bfc11 1644 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1645 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1646 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 1647
Kojto 109:9296ab0bfc11 1648 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
Kojto 109:9296ab0bfc11 1649 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
Kojto 109:9296ab0bfc11 1650 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
Kojto 109:9296ab0bfc11 1651 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
Kojto 109:9296ab0bfc11 1652 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
Kojto 109:9296ab0bfc11 1653
Kojto 109:9296ab0bfc11 1654 /*!< ADCPPRE configuration */
Kojto 109:9296ab0bfc11 1655 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
Kojto 109:9296ab0bfc11 1656
Kojto 109:9296ab0bfc11 1657 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
Kojto 109:9296ab0bfc11 1658 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
Kojto 109:9296ab0bfc11 1659
Kojto 109:9296ab0bfc11 1660 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
Kojto 109:9296ab0bfc11 1661 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
Kojto 109:9296ab0bfc11 1662 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
Kojto 109:9296ab0bfc11 1663
Kojto 109:9296ab0bfc11 1664 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
Kojto 109:9296ab0bfc11 1665 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
Kojto 109:9296ab0bfc11 1666 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
Kojto 109:9296ab0bfc11 1667
Kojto 109:9296ab0bfc11 1668 /*!< PLLMUL configuration */
Kojto 109:9296ab0bfc11 1669 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 109:9296ab0bfc11 1670 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1671 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1672 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 1673 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 1674
Kojto 109:9296ab0bfc11 1675 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
Kojto 109:9296ab0bfc11 1676 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
Kojto 109:9296ab0bfc11 1677 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
Kojto 109:9296ab0bfc11 1678 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
Kojto 109:9296ab0bfc11 1679 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
Kojto 109:9296ab0bfc11 1680 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
Kojto 109:9296ab0bfc11 1681 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
Kojto 109:9296ab0bfc11 1682 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
Kojto 109:9296ab0bfc11 1683 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
Kojto 109:9296ab0bfc11 1684 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
Kojto 109:9296ab0bfc11 1685 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
Kojto 109:9296ab0bfc11 1686 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
Kojto 109:9296ab0bfc11 1687 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
Kojto 109:9296ab0bfc11 1688 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
Kojto 109:9296ab0bfc11 1689 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
Kojto 109:9296ab0bfc11 1690
Kojto 109:9296ab0bfc11 1691 /*!< MCO configuration */
Kojto 109:9296ab0bfc11 1692 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
Kojto 109:9296ab0bfc11 1693 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1694 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1695 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 1696 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 1697
Kojto 109:9296ab0bfc11 1698 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 109:9296ab0bfc11 1699 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
Kojto 109:9296ab0bfc11 1700 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
Kojto 109:9296ab0bfc11 1701 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
Kojto 109:9296ab0bfc11 1702 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
Kojto 109:9296ab0bfc11 1703 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
Kojto 109:9296ab0bfc11 1704 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
Kojto 109:9296ab0bfc11 1705 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
Kojto 109:9296ab0bfc11 1706
Kojto 109:9296ab0bfc11 1707 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCO prescaler */
Kojto 109:9296ab0bfc11 1708 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
Kojto 109:9296ab0bfc11 1709 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
Kojto 109:9296ab0bfc11 1710 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
Kojto 109:9296ab0bfc11 1711 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
Kojto 109:9296ab0bfc11 1712 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
Kojto 109:9296ab0bfc11 1713 #define RCC_CFGR_MCOPRE_DIV32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
Kojto 109:9296ab0bfc11 1714 #define RCC_CFGR_MCOPRE_DIV64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
Kojto 109:9296ab0bfc11 1715 #define RCC_CFGR_MCOPRE_DIV128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
Kojto 109:9296ab0bfc11 1716
Kojto 109:9296ab0bfc11 1717 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
Kojto 109:9296ab0bfc11 1718
Kojto 109:9296ab0bfc11 1719 /*!<****************** Bit definition for RCC_CIR register *****************/
Kojto 109:9296ab0bfc11 1720 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
Kojto 109:9296ab0bfc11 1721 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
Kojto 109:9296ab0bfc11 1722 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
Kojto 109:9296ab0bfc11 1723 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
Kojto 109:9296ab0bfc11 1724 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
Kojto 109:9296ab0bfc11 1725 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
Kojto 109:9296ab0bfc11 1726 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
Kojto 109:9296ab0bfc11 1727 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 1728 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 1729 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 1730 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 1731 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 1732 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
Kojto 109:9296ab0bfc11 1733 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 1734 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 1735 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 1736 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 1737 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 1738 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
Kojto 109:9296ab0bfc11 1739 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
Kojto 109:9296ab0bfc11 1740
Kojto 109:9296ab0bfc11 1741 /***************** Bit definition for RCC_APB2RSTR register ****************/
Kojto 109:9296ab0bfc11 1742 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
Kojto 109:9296ab0bfc11 1743 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
Kojto 109:9296ab0bfc11 1744 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
Kojto 109:9296ab0bfc11 1745 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
Kojto 109:9296ab0bfc11 1746 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
Kojto 109:9296ab0bfc11 1747 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
Kojto 109:9296ab0bfc11 1748 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
Kojto 109:9296ab0bfc11 1749 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
Kojto 109:9296ab0bfc11 1750
Kojto 109:9296ab0bfc11 1751 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
Kojto 109:9296ab0bfc11 1752 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
Kojto 109:9296ab0bfc11 1753
Kojto 109:9296ab0bfc11 1754 /***************** Bit definition for RCC_APB1RSTR register ****************/
Kojto 109:9296ab0bfc11 1755 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 clock reset */
Kojto 109:9296ab0bfc11 1756 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
Kojto 109:9296ab0bfc11 1757 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
Kojto 109:9296ab0bfc11 1758 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
Kojto 109:9296ab0bfc11 1759 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
Kojto 109:9296ab0bfc11 1760 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
Kojto 109:9296ab0bfc11 1761
Kojto 109:9296ab0bfc11 1762 /****************** Bit definition for RCC_AHBENR register *****************/
Kojto 109:9296ab0bfc11 1763 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
Kojto 109:9296ab0bfc11 1764 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
Kojto 109:9296ab0bfc11 1765 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
Kojto 109:9296ab0bfc11 1766 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
Kojto 109:9296ab0bfc11 1767 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
Kojto 109:9296ab0bfc11 1768 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
Kojto 109:9296ab0bfc11 1769 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
Kojto 109:9296ab0bfc11 1770 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
Kojto 109:9296ab0bfc11 1771 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
Kojto 109:9296ab0bfc11 1772
Kojto 109:9296ab0bfc11 1773 /* Old Bit definition maintained for legacy purpose */
Kojto 109:9296ab0bfc11 1774 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
Kojto 109:9296ab0bfc11 1775 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
Kojto 109:9296ab0bfc11 1776
Kojto 109:9296ab0bfc11 1777 /***************** Bit definition for RCC_APB2ENR register *****************/
Kojto 109:9296ab0bfc11 1778 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
Kojto 109:9296ab0bfc11 1779 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
Kojto 109:9296ab0bfc11 1780 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
Kojto 109:9296ab0bfc11 1781 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
Kojto 109:9296ab0bfc11 1782 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
Kojto 109:9296ab0bfc11 1783 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
Kojto 109:9296ab0bfc11 1784 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
Kojto 109:9296ab0bfc11 1785 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
Kojto 109:9296ab0bfc11 1786
Kojto 109:9296ab0bfc11 1787 /* Old Bit definition maintained for legacy purpose */
Kojto 109:9296ab0bfc11 1788 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
Kojto 109:9296ab0bfc11 1789 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
Kojto 109:9296ab0bfc11 1790
Kojto 109:9296ab0bfc11 1791 /***************** Bit definition for RCC_APB1ENR register *****************/
Kojto 109:9296ab0bfc11 1792 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
Kojto 109:9296ab0bfc11 1793 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
Kojto 109:9296ab0bfc11 1794 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
Kojto 109:9296ab0bfc11 1795 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
Kojto 109:9296ab0bfc11 1796 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
Kojto 109:9296ab0bfc11 1797 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
Kojto 109:9296ab0bfc11 1798
Kojto 109:9296ab0bfc11 1799 /******************* Bit definition for RCC_BDCR register ******************/
Kojto 109:9296ab0bfc11 1800 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
Kojto 109:9296ab0bfc11 1801 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
Kojto 109:9296ab0bfc11 1802 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
Kojto 109:9296ab0bfc11 1803
Kojto 109:9296ab0bfc11 1804 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Kojto 109:9296ab0bfc11 1805 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1806 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1807
Kojto 109:9296ab0bfc11 1808 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 109:9296ab0bfc11 1809 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1810 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1811
Kojto 109:9296ab0bfc11 1812 /*!< RTC configuration */
Kojto 109:9296ab0bfc11 1813 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
Kojto 109:9296ab0bfc11 1814 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
Kojto 109:9296ab0bfc11 1815 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
Kojto 109:9296ab0bfc11 1816 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
Kojto 109:9296ab0bfc11 1817
Kojto 109:9296ab0bfc11 1818 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
Kojto 109:9296ab0bfc11 1819 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
Kojto 109:9296ab0bfc11 1820
Kojto 109:9296ab0bfc11 1821 /******************* Bit definition for RCC_CSR register *******************/
Kojto 109:9296ab0bfc11 1822 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
Kojto 109:9296ab0bfc11 1823 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
Kojto 109:9296ab0bfc11 1824 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
Kojto 109:9296ab0bfc11 1825 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
Kojto 109:9296ab0bfc11 1826 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
Kojto 109:9296ab0bfc11 1827 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
Kojto 109:9296ab0bfc11 1828 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
Kojto 109:9296ab0bfc11 1829 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
Kojto 109:9296ab0bfc11 1830 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
Kojto 109:9296ab0bfc11 1831 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
Kojto 109:9296ab0bfc11 1832 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
Kojto 109:9296ab0bfc11 1833
Kojto 109:9296ab0bfc11 1834 /* Old Bit definition maintained for legacy purpose */
Kojto 109:9296ab0bfc11 1835 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
Kojto 109:9296ab0bfc11 1836
Kojto 109:9296ab0bfc11 1837 /******************* Bit definition for RCC_AHBRSTR register ***************/
Kojto 109:9296ab0bfc11 1838 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
Kojto 109:9296ab0bfc11 1839 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
Kojto 109:9296ab0bfc11 1840 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
Kojto 109:9296ab0bfc11 1841 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
Kojto 109:9296ab0bfc11 1842 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
Kojto 109:9296ab0bfc11 1843
Kojto 109:9296ab0bfc11 1844 /******************* Bit definition for RCC_CFGR2 register *****************/
Kojto 109:9296ab0bfc11 1845 /*!< PREDIV configuration */
Kojto 109:9296ab0bfc11 1846 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
Kojto 109:9296ab0bfc11 1847 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1848 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1849 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 1850 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 1851
Kojto 109:9296ab0bfc11 1852 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
Kojto 109:9296ab0bfc11 1853 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
Kojto 109:9296ab0bfc11 1854 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
Kojto 109:9296ab0bfc11 1855 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
Kojto 109:9296ab0bfc11 1856 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
Kojto 109:9296ab0bfc11 1857 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
Kojto 109:9296ab0bfc11 1858 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
Kojto 109:9296ab0bfc11 1859 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
Kojto 109:9296ab0bfc11 1860 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
Kojto 109:9296ab0bfc11 1861 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
Kojto 109:9296ab0bfc11 1862 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
Kojto 109:9296ab0bfc11 1863 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
Kojto 109:9296ab0bfc11 1864 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
Kojto 109:9296ab0bfc11 1865 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
Kojto 109:9296ab0bfc11 1866 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
Kojto 109:9296ab0bfc11 1867 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
Kojto 109:9296ab0bfc11 1868
Kojto 109:9296ab0bfc11 1869 /******************* Bit definition for RCC_CFGR3 register *****************/
Kojto 109:9296ab0bfc11 1870 /*!< USART1 Clock source selection */
Kojto 109:9296ab0bfc11 1871 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
Kojto 109:9296ab0bfc11 1872 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 1873 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 1874
Kojto 109:9296ab0bfc11 1875 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
Kojto 109:9296ab0bfc11 1876 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
Kojto 109:9296ab0bfc11 1877 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
Kojto 109:9296ab0bfc11 1878 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
Kojto 109:9296ab0bfc11 1879
Kojto 109:9296ab0bfc11 1880 /*!< I2C1 Clock source selection */
Kojto 109:9296ab0bfc11 1881 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
Kojto 109:9296ab0bfc11 1882
Kojto 109:9296ab0bfc11 1883 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
Kojto 109:9296ab0bfc11 1884 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
Kojto 109:9296ab0bfc11 1885
Kojto 109:9296ab0bfc11 1886 /******************* Bit definition for RCC_CR2 register *******************/
Kojto 109:9296ab0bfc11 1887 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
Kojto 109:9296ab0bfc11 1888 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
Kojto 109:9296ab0bfc11 1889 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
Kojto 109:9296ab0bfc11 1890 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
Kojto 109:9296ab0bfc11 1891 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
Kojto 109:9296ab0bfc11 1892
Kojto 109:9296ab0bfc11 1893 /*****************************************************************************/
Kojto 109:9296ab0bfc11 1894 /* */
Kojto 109:9296ab0bfc11 1895 /* Real-Time Clock (RTC) */
Kojto 109:9296ab0bfc11 1896 /* */
Kojto 109:9296ab0bfc11 1897 /*****************************************************************************/
Kojto 109:9296ab0bfc11 1898 /******************** Bits definition for RTC_TR register ******************/
Kojto 109:9296ab0bfc11 1899 #define RTC_TR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1900 #define RTC_TR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 1901 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1902 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1903 #define RTC_TR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 1904 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1905 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1906 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1907 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 1908 #define RTC_TR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 1909 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1910 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1911 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1912 #define RTC_TR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 1913 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1914 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1915 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1916 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1917 #define RTC_TR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 1918 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1919 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1920 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1921 #define RTC_TR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 1922 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1923 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1924 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1925 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1926
Kojto 109:9296ab0bfc11 1927 /******************** Bits definition for RTC_DR register ******************/
Kojto 109:9296ab0bfc11 1928 #define RTC_DR_YT ((uint32_t)0x00F00000)
Kojto 109:9296ab0bfc11 1929 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1930 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1931 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1932 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 1933 #define RTC_DR_YU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 1934 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1935 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1936 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1937 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 1938 #define RTC_DR_WDU ((uint32_t)0x0000E000)
Kojto 109:9296ab0bfc11 1939 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1940 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1941 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1942 #define RTC_DR_MT ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1943 #define RTC_DR_MU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 1944 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1945 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 1946 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 1947 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1948 #define RTC_DR_DT ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 1949 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1950 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1951 #define RTC_DR_DU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 1952 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1953 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 1954 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 1955 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1956
Kojto 109:9296ab0bfc11 1957 /******************** Bits definition for RTC_CR register ******************/
Kojto 109:9296ab0bfc11 1958 #define RTC_CR_COE ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 1959 #define RTC_CR_OSEL ((uint32_t)0x00600000)
Kojto 109:9296ab0bfc11 1960 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 1961 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 1962 #define RTC_CR_POL ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 1963 #define RTC_CR_COSEL ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 1964 #define RTC_CR_BCK ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 1965 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 1966 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1967 #define RTC_CR_TSIE ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 1968 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1969 #define RTC_CR_TSE ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1970 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1971 #define RTC_CR_FMT ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1972 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1973 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1974 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1975
Kojto 109:9296ab0bfc11 1976 /******************** Bits definition for RTC_ISR register *****************/
Kojto 109:9296ab0bfc11 1977 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 1978 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 1979 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 1980 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 1981 #define RTC_ISR_TSF ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 1982 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 1983 #define RTC_ISR_INIT ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 1984 #define RTC_ISR_INITF ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 1985 #define RTC_ISR_RSF ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 1986 #define RTC_ISR_INITS ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 1987 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 1988 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 1989
Kojto 109:9296ab0bfc11 1990 /******************** Bits definition for RTC_PRER register ****************/
Kojto 109:9296ab0bfc11 1991 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
Kojto 109:9296ab0bfc11 1992 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 1993
Kojto 109:9296ab0bfc11 1994 /******************** Bits definition for RTC_ALRMAR register **************/
Kojto 109:9296ab0bfc11 1995 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 1996 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
Kojto 109:9296ab0bfc11 1997 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
Kojto 109:9296ab0bfc11 1998 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
Kojto 109:9296ab0bfc11 1999 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
Kojto 109:9296ab0bfc11 2000 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 2001 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 2002 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 2003 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 2004 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 2005 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
Kojto 109:9296ab0bfc11 2006 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 2007 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 2008 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 2009 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 2010 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 2011 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 2012 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 2013 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 2014 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 2015 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2016 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 2017 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2018 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2019 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2020 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 2021 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2022 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2023 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2024 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2025 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2026 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 2027 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2028 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2029 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2030 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 2031 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2032 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2033 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2034 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2035
Kojto 109:9296ab0bfc11 2036 /******************** Bits definition for RTC_WPR register *****************/
Kojto 109:9296ab0bfc11 2037 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
Kojto 109:9296ab0bfc11 2038
Kojto 109:9296ab0bfc11 2039 /******************** Bits definition for RTC_SSR register *****************/
Kojto 109:9296ab0bfc11 2040 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
Kojto 109:9296ab0bfc11 2041
Kojto 109:9296ab0bfc11 2042 /******************** Bits definition for RTC_SHIFTR register **************/
Kojto 109:9296ab0bfc11 2043 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 2044 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
Kojto 109:9296ab0bfc11 2045
Kojto 109:9296ab0bfc11 2046 /******************** Bits definition for RTC_TSTR register ****************/
Kojto 109:9296ab0bfc11 2047 #define RTC_TSTR_PM ((uint32_t)0x00400000)
Kojto 109:9296ab0bfc11 2048 #define RTC_TSTR_HT ((uint32_t)0x00300000)
Kojto 109:9296ab0bfc11 2049 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
Kojto 109:9296ab0bfc11 2050 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
Kojto 109:9296ab0bfc11 2051 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
Kojto 109:9296ab0bfc11 2052 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
Kojto 109:9296ab0bfc11 2053 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
Kojto 109:9296ab0bfc11 2054 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 2055 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
Kojto 109:9296ab0bfc11 2056 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
Kojto 109:9296ab0bfc11 2057 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2058 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2059 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2060 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 2061 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2062 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2063 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2064 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2065 #define RTC_TSTR_ST ((uint32_t)0x00000070)
Kojto 109:9296ab0bfc11 2066 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2067 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2068 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2069 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 2070 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2071 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2072 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2073 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2074
Kojto 109:9296ab0bfc11 2075 /******************** Bits definition for RTC_TSDR register ****************/
Kojto 109:9296ab0bfc11 2076 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
Kojto 109:9296ab0bfc11 2077 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2078 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2079 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2080 #define RTC_TSDR_MT ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2081 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
Kojto 109:9296ab0bfc11 2082 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2083 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2084 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2085 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2086 #define RTC_TSDR_DT ((uint32_t)0x00000030)
Kojto 109:9296ab0bfc11 2087 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2088 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2089 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
Kojto 109:9296ab0bfc11 2090 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2091 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2092 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2093 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2094
Kojto 109:9296ab0bfc11 2095 /******************** Bits definition for RTC_TSSSR register ***************/
Kojto 109:9296ab0bfc11 2096 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
Kojto 109:9296ab0bfc11 2097
Kojto 109:9296ab0bfc11 2098 /******************** Bits definition for RTC_CALR register ****************/
Kojto 109:9296ab0bfc11 2099 #define RTC_CALR_CALP ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2100 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2101 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2102 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
Kojto 109:9296ab0bfc11 2103 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2104 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2105 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2106 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2107 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2108 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
Kojto 109:9296ab0bfc11 2109 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
Kojto 109:9296ab0bfc11 2110 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2111 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2112
Kojto 109:9296ab0bfc11 2113 /******************** Bits definition for RTC_TAFCR register ***************/
Kojto 109:9296ab0bfc11 2114 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
Kojto 109:9296ab0bfc11 2115 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
Kojto 109:9296ab0bfc11 2116 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
Kojto 109:9296ab0bfc11 2117 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
Kojto 109:9296ab0bfc11 2118 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
Kojto 109:9296ab0bfc11 2119 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
Kojto 109:9296ab0bfc11 2120 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
Kojto 109:9296ab0bfc11 2121 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
Kojto 109:9296ab0bfc11 2122 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
Kojto 109:9296ab0bfc11 2123 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
Kojto 109:9296ab0bfc11 2124 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
Kojto 109:9296ab0bfc11 2125 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
Kojto 109:9296ab0bfc11 2126 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
Kojto 109:9296ab0bfc11 2127 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
Kojto 109:9296ab0bfc11 2128 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
Kojto 109:9296ab0bfc11 2129 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
Kojto 109:9296ab0bfc11 2130 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
Kojto 109:9296ab0bfc11 2131 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
Kojto 109:9296ab0bfc11 2132
Kojto 109:9296ab0bfc11 2133 /******************** Bits definition for RTC_ALRMASSR register ************/
Kojto 109:9296ab0bfc11 2134 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
Kojto 109:9296ab0bfc11 2135 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
Kojto 109:9296ab0bfc11 2136 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
Kojto 109:9296ab0bfc11 2137 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
Kojto 109:9296ab0bfc11 2138 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
Kojto 109:9296ab0bfc11 2139 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
Kojto 109:9296ab0bfc11 2140
Kojto 109:9296ab0bfc11 2141 /******************** Bits definition for RTC_BKP0R register ***************/
Kojto 109:9296ab0bfc11 2142 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 2143
Kojto 109:9296ab0bfc11 2144 /******************** Bits definition for RTC_BKP1R register ***************/
Kojto 109:9296ab0bfc11 2145 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 2146
Kojto 109:9296ab0bfc11 2147 /******************** Bits definition for RTC_BKP2R register ***************/
Kojto 109:9296ab0bfc11 2148 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 2149
Kojto 109:9296ab0bfc11 2150 /******************** Bits definition for RTC_BKP3R register ***************/
Kojto 109:9296ab0bfc11 2151 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 2152
Kojto 109:9296ab0bfc11 2153 /******************** Bits definition for RTC_BKP4R register ***************/
Kojto 109:9296ab0bfc11 2154 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
Kojto 109:9296ab0bfc11 2155
Kojto 109:9296ab0bfc11 2156 /******************** Number of backup registers ******************************/
Kojto 109:9296ab0bfc11 2157 #define RTC_BKP_NUMBER ((uint32_t)0x00000005)
Kojto 109:9296ab0bfc11 2158
Kojto 109:9296ab0bfc11 2159 /*****************************************************************************/
Kojto 109:9296ab0bfc11 2160 /* */
Kojto 109:9296ab0bfc11 2161 /* Serial Peripheral Interface (SPI) */
Kojto 109:9296ab0bfc11 2162 /* */
Kojto 109:9296ab0bfc11 2163 /*****************************************************************************/
Kojto 109:9296ab0bfc11 2164 /******************* Bit definition for SPI_CR1 register *******************/
Kojto 109:9296ab0bfc11 2165 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
Kojto 109:9296ab0bfc11 2166 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
Kojto 109:9296ab0bfc11 2167 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
Kojto 109:9296ab0bfc11 2168 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 109:9296ab0bfc11 2169 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2170 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2171 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 2172 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
Kojto 109:9296ab0bfc11 2173 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
Kojto 109:9296ab0bfc11 2174 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
Kojto 109:9296ab0bfc11 2175 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
Kojto 109:9296ab0bfc11 2176 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
Kojto 109:9296ab0bfc11 2177 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
Kojto 109:9296ab0bfc11 2178 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
Kojto 109:9296ab0bfc11 2179 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
Kojto 109:9296ab0bfc11 2180 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
Kojto 109:9296ab0bfc11 2181 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
Kojto 109:9296ab0bfc11 2182
Kojto 109:9296ab0bfc11 2183 /******************* Bit definition for SPI_CR2 register *******************/
Kojto 109:9296ab0bfc11 2184 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
Kojto 109:9296ab0bfc11 2185 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
Kojto 109:9296ab0bfc11 2186 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
Kojto 109:9296ab0bfc11 2187 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
Kojto 109:9296ab0bfc11 2188 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
Kojto 109:9296ab0bfc11 2189 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
Kojto 109:9296ab0bfc11 2190 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
Kojto 109:9296ab0bfc11 2191 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
Kojto 109:9296ab0bfc11 2192 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
Kojto 109:9296ab0bfc11 2193 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2194 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2195 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 2196 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 2197 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
Kojto 109:9296ab0bfc11 2198 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
Kojto 109:9296ab0bfc11 2199 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
Kojto 109:9296ab0bfc11 2200
Kojto 109:9296ab0bfc11 2201 /******************** Bit definition for SPI_SR register *******************/
Kojto 109:9296ab0bfc11 2202 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
Kojto 109:9296ab0bfc11 2203 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
Kojto 109:9296ab0bfc11 2204 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
Kojto 109:9296ab0bfc11 2205 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
Kojto 109:9296ab0bfc11 2206 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
Kojto 109:9296ab0bfc11 2207 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
Kojto 109:9296ab0bfc11 2208 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
Kojto 109:9296ab0bfc11 2209 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
Kojto 109:9296ab0bfc11 2210 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
Kojto 109:9296ab0bfc11 2211 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
Kojto 109:9296ab0bfc11 2212 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2213 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2214 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
Kojto 109:9296ab0bfc11 2215 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2216 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2217
Kojto 109:9296ab0bfc11 2218 /******************** Bit definition for SPI_DR register *******************/
Kojto 109:9296ab0bfc11 2219 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
Kojto 109:9296ab0bfc11 2220
Kojto 109:9296ab0bfc11 2221 /******************* Bit definition for SPI_CRCPR register *****************/
Kojto 109:9296ab0bfc11 2222 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
Kojto 109:9296ab0bfc11 2223
Kojto 109:9296ab0bfc11 2224 /****************** Bit definition for SPI_RXCRCR register *****************/
Kojto 109:9296ab0bfc11 2225 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
Kojto 109:9296ab0bfc11 2226
Kojto 109:9296ab0bfc11 2227 /****************** Bit definition for SPI_TXCRCR register *****************/
Kojto 109:9296ab0bfc11 2228 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
Kojto 109:9296ab0bfc11 2229
Kojto 109:9296ab0bfc11 2230 /****************** Bit definition for SPI_I2SCFGR register ****************/
Kojto 109:9296ab0bfc11 2231 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
Kojto 109:9296ab0bfc11 2232 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 109:9296ab0bfc11 2233 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2234 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2235 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
Kojto 109:9296ab0bfc11 2236 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 109:9296ab0bfc11 2237 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2238 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2239 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
Kojto 109:9296ab0bfc11 2240 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 109:9296ab0bfc11 2241 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2242 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2243 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
Kojto 109:9296ab0bfc11 2244 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
Kojto 109:9296ab0bfc11 2245
Kojto 109:9296ab0bfc11 2246 /****************** Bit definition for SPI_I2SPR register ******************/
Kojto 109:9296ab0bfc11 2247 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
Kojto 109:9296ab0bfc11 2248 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
Kojto 109:9296ab0bfc11 2249 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
Kojto 109:9296ab0bfc11 2250
Kojto 109:9296ab0bfc11 2251 /*****************************************************************************/
Kojto 109:9296ab0bfc11 2252 /* */
Kojto 109:9296ab0bfc11 2253 /* System Configuration (SYSCFG) */
Kojto 109:9296ab0bfc11 2254 /* */
Kojto 109:9296ab0bfc11 2255 /*****************************************************************************/
Kojto 109:9296ab0bfc11 2256 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
Kojto 109:9296ab0bfc11 2257 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
Kojto 109:9296ab0bfc11 2258 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
Kojto 109:9296ab0bfc11 2259 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
Kojto 109:9296ab0bfc11 2260
Kojto 109:9296ab0bfc11 2261
Kojto 109:9296ab0bfc11 2262 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
Kojto 109:9296ab0bfc11 2263 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
Kojto 109:9296ab0bfc11 2264 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
Kojto 109:9296ab0bfc11 2265 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
Kojto 109:9296ab0bfc11 2266 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
Kojto 109:9296ab0bfc11 2267 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
Kojto 109:9296ab0bfc11 2268
Kojto 109:9296ab0bfc11 2269 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
Kojto 109:9296ab0bfc11 2270 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
Kojto 109:9296ab0bfc11 2271 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
Kojto 109:9296ab0bfc11 2272 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
Kojto 109:9296ab0bfc11 2273 #define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7 */
Kojto 109:9296ab0bfc11 2274 #define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 */
Kojto 109:9296ab0bfc11 2275 #define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10 */
Kojto 109:9296ab0bfc11 2276
Kojto 109:9296ab0bfc11 2277
Kojto 109:9296ab0bfc11 2278 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
Kojto 109:9296ab0bfc11 2279 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
Kojto 109:9296ab0bfc11 2280 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
Kojto 109:9296ab0bfc11 2281 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
Kojto 109:9296ab0bfc11 2282 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
Kojto 109:9296ab0bfc11 2283
Kojto 109:9296ab0bfc11 2284 /**
Kojto 109:9296ab0bfc11 2285 * @brief EXTI0 configuration
Kojto 109:9296ab0bfc11 2286 */
Kojto 109:9296ab0bfc11 2287 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
Kojto 109:9296ab0bfc11 2288 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
Kojto 109:9296ab0bfc11 2289 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
Kojto 109:9296ab0bfc11 2290 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
Kojto 109:9296ab0bfc11 2291 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
Kojto 109:9296ab0bfc11 2292
Kojto 109:9296ab0bfc11 2293 /**
Kojto 109:9296ab0bfc11 2294 * @brief EXTI1 configuration
Kojto 109:9296ab0bfc11 2295 */
Kojto 109:9296ab0bfc11 2296 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
Kojto 109:9296ab0bfc11 2297 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
Kojto 109:9296ab0bfc11 2298 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
Kojto 109:9296ab0bfc11 2299 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
Kojto 109:9296ab0bfc11 2300 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
Kojto 109:9296ab0bfc11 2301
Kojto 109:9296ab0bfc11 2302 /**
Kojto 109:9296ab0bfc11 2303 * @brief EXTI2 configuration
Kojto 109:9296ab0bfc11 2304 */
Kojto 109:9296ab0bfc11 2305 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
Kojto 109:9296ab0bfc11 2306 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
Kojto 109:9296ab0bfc11 2307 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
Kojto 109:9296ab0bfc11 2308 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
Kojto 109:9296ab0bfc11 2309 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
Kojto 109:9296ab0bfc11 2310
Kojto 109:9296ab0bfc11 2311 /**
Kojto 109:9296ab0bfc11 2312 * @brief EXTI3 configuration
Kojto 109:9296ab0bfc11 2313 */
Kojto 109:9296ab0bfc11 2314 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
Kojto 109:9296ab0bfc11 2315 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
Kojto 109:9296ab0bfc11 2316 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
Kojto 109:9296ab0bfc11 2317 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
Kojto 109:9296ab0bfc11 2318 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
Kojto 109:9296ab0bfc11 2319
Kojto 109:9296ab0bfc11 2320 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
Kojto 109:9296ab0bfc11 2321 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
Kojto 109:9296ab0bfc11 2322 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
Kojto 109:9296ab0bfc11 2323 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
Kojto 109:9296ab0bfc11 2324 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
Kojto 109:9296ab0bfc11 2325
Kojto 109:9296ab0bfc11 2326 /**
Kojto 109:9296ab0bfc11 2327 * @brief EXTI4 configuration
Kojto 109:9296ab0bfc11 2328 */
Kojto 109:9296ab0bfc11 2329 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
Kojto 109:9296ab0bfc11 2330 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
Kojto 109:9296ab0bfc11 2331 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
Kojto 109:9296ab0bfc11 2332 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
Kojto 109:9296ab0bfc11 2333 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
Kojto 109:9296ab0bfc11 2334
Kojto 109:9296ab0bfc11 2335 /**
Kojto 109:9296ab0bfc11 2336 * @brief EXTI5 configuration
Kojto 109:9296ab0bfc11 2337 */
Kojto 109:9296ab0bfc11 2338 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
Kojto 109:9296ab0bfc11 2339 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
Kojto 109:9296ab0bfc11 2340 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
Kojto 109:9296ab0bfc11 2341 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
Kojto 109:9296ab0bfc11 2342 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
Kojto 109:9296ab0bfc11 2343
Kojto 109:9296ab0bfc11 2344 /**
Kojto 109:9296ab0bfc11 2345 * @brief EXTI6 configuration
Kojto 109:9296ab0bfc11 2346 */
Kojto 109:9296ab0bfc11 2347 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
Kojto 109:9296ab0bfc11 2348 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
Kojto 109:9296ab0bfc11 2349 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
Kojto 109:9296ab0bfc11 2350 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
Kojto 109:9296ab0bfc11 2351 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
Kojto 109:9296ab0bfc11 2352
Kojto 109:9296ab0bfc11 2353 /**
Kojto 109:9296ab0bfc11 2354 * @brief EXTI7 configuration
Kojto 109:9296ab0bfc11 2355 */
Kojto 109:9296ab0bfc11 2356 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
Kojto 109:9296ab0bfc11 2357 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
Kojto 109:9296ab0bfc11 2358 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
Kojto 109:9296ab0bfc11 2359 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
Kojto 109:9296ab0bfc11 2360 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
Kojto 109:9296ab0bfc11 2361
Kojto 109:9296ab0bfc11 2362 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
Kojto 109:9296ab0bfc11 2363 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
Kojto 109:9296ab0bfc11 2364 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
Kojto 109:9296ab0bfc11 2365 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
Kojto 109:9296ab0bfc11 2366 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
Kojto 109:9296ab0bfc11 2367
Kojto 109:9296ab0bfc11 2368 /**
Kojto 109:9296ab0bfc11 2369 * @brief EXTI8 configuration
Kojto 109:9296ab0bfc11 2370 */
Kojto 109:9296ab0bfc11 2371 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
Kojto 109:9296ab0bfc11 2372 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
Kojto 109:9296ab0bfc11 2373 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
Kojto 109:9296ab0bfc11 2374 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
Kojto 109:9296ab0bfc11 2375 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
Kojto 109:9296ab0bfc11 2376
Kojto 109:9296ab0bfc11 2377 /**
Kojto 109:9296ab0bfc11 2378 * @brief EXTI9 configuration
Kojto 109:9296ab0bfc11 2379 */
Kojto 109:9296ab0bfc11 2380 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
Kojto 109:9296ab0bfc11 2381 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
Kojto 109:9296ab0bfc11 2382 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
Kojto 109:9296ab0bfc11 2383 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
Kojto 109:9296ab0bfc11 2384 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
Kojto 109:9296ab0bfc11 2385
Kojto 109:9296ab0bfc11 2386 /**
Kojto 109:9296ab0bfc11 2387 * @brief EXTI10 configuration
Kojto 109:9296ab0bfc11 2388 */
Kojto 109:9296ab0bfc11 2389 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
Kojto 109:9296ab0bfc11 2390 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
Kojto 109:9296ab0bfc11 2391 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
Kojto 109:9296ab0bfc11 2392 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
Kojto 109:9296ab0bfc11 2393 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
Kojto 109:9296ab0bfc11 2394
Kojto 109:9296ab0bfc11 2395 /**
Kojto 109:9296ab0bfc11 2396 * @brief EXTI11 configuration
Kojto 109:9296ab0bfc11 2397 */
Kojto 109:9296ab0bfc11 2398 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
Kojto 109:9296ab0bfc11 2399 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
Kojto 109:9296ab0bfc11 2400 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
Kojto 109:9296ab0bfc11 2401 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
Kojto 109:9296ab0bfc11 2402 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
Kojto 109:9296ab0bfc11 2403
Kojto 109:9296ab0bfc11 2404 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
Kojto 109:9296ab0bfc11 2405 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
Kojto 109:9296ab0bfc11 2406 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
Kojto 109:9296ab0bfc11 2407 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
Kojto 109:9296ab0bfc11 2408 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
Kojto 109:9296ab0bfc11 2409
Kojto 109:9296ab0bfc11 2410 /**
Kojto 109:9296ab0bfc11 2411 * @brief EXTI12 configuration
Kojto 109:9296ab0bfc11 2412 */
Kojto 109:9296ab0bfc11 2413 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
Kojto 109:9296ab0bfc11 2414 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
Kojto 109:9296ab0bfc11 2415 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
Kojto 109:9296ab0bfc11 2416 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
Kojto 109:9296ab0bfc11 2417 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
Kojto 109:9296ab0bfc11 2418
Kojto 109:9296ab0bfc11 2419 /**
Kojto 109:9296ab0bfc11 2420 * @brief EXTI13 configuration
Kojto 109:9296ab0bfc11 2421 */
Kojto 109:9296ab0bfc11 2422 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
Kojto 109:9296ab0bfc11 2423 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
Kojto 109:9296ab0bfc11 2424 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
Kojto 109:9296ab0bfc11 2425 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
Kojto 109:9296ab0bfc11 2426 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
Kojto 109:9296ab0bfc11 2427
Kojto 109:9296ab0bfc11 2428 /**
Kojto 109:9296ab0bfc11 2429 * @brief EXTI14 configuration
Kojto 109:9296ab0bfc11 2430 */
Kojto 109:9296ab0bfc11 2431 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
Kojto 109:9296ab0bfc11 2432 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
Kojto 109:9296ab0bfc11 2433 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
Kojto 109:9296ab0bfc11 2434 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
Kojto 109:9296ab0bfc11 2435 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
Kojto 109:9296ab0bfc11 2436
Kojto 109:9296ab0bfc11 2437 /**
Kojto 109:9296ab0bfc11 2438 * @brief EXTI15 configuration
Kojto 109:9296ab0bfc11 2439 */
Kojto 109:9296ab0bfc11 2440 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
Kojto 109:9296ab0bfc11 2441 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
Kojto 109:9296ab0bfc11 2442 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
Kojto 109:9296ab0bfc11 2443 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
Kojto 109:9296ab0bfc11 2444 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
Kojto 109:9296ab0bfc11 2445
Kojto 109:9296ab0bfc11 2446 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
Kojto 109:9296ab0bfc11 2447 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
Kojto 109:9296ab0bfc11 2448 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
Kojto 109:9296ab0bfc11 2449 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
Kojto 109:9296ab0bfc11 2450 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
Kojto 109:9296ab0bfc11 2451 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
Kojto 109:9296ab0bfc11 2452
Kojto 109:9296ab0bfc11 2453 /*****************************************************************************/
Kojto 109:9296ab0bfc11 2454 /* */
Kojto 109:9296ab0bfc11 2455 /* Timers (TIM) */
Kojto 109:9296ab0bfc11 2456 /* */
Kojto 109:9296ab0bfc11 2457 /*****************************************************************************/
Kojto 109:9296ab0bfc11 2458 /******************* Bit definition for TIM_CR1 register *******************/
Kojto 109:9296ab0bfc11 2459 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
Kojto 109:9296ab0bfc11 2460 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
Kojto 109:9296ab0bfc11 2461 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
Kojto 109:9296ab0bfc11 2462 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
Kojto 109:9296ab0bfc11 2463 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
Kojto 109:9296ab0bfc11 2464
Kojto 109:9296ab0bfc11 2465 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 109:9296ab0bfc11 2466 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2467 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2468
Kojto 109:9296ab0bfc11 2469 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
Kojto 109:9296ab0bfc11 2470
Kojto 109:9296ab0bfc11 2471 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
Kojto 109:9296ab0bfc11 2472 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2473 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2474
Kojto 109:9296ab0bfc11 2475 /******************* Bit definition for TIM_CR2 register *******************/
Kojto 109:9296ab0bfc11 2476 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
Kojto 109:9296ab0bfc11 2477 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
Kojto 109:9296ab0bfc11 2478 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
Kojto 109:9296ab0bfc11 2479
Kojto 109:9296ab0bfc11 2480 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 109:9296ab0bfc11 2481 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2482 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2483 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2484
Kojto 109:9296ab0bfc11 2485 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
Kojto 109:9296ab0bfc11 2486 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
Kojto 109:9296ab0bfc11 2487 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
Kojto 109:9296ab0bfc11 2488 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
Kojto 109:9296ab0bfc11 2489 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
Kojto 109:9296ab0bfc11 2490 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
Kojto 109:9296ab0bfc11 2491 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
Kojto 109:9296ab0bfc11 2492 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
Kojto 109:9296ab0bfc11 2493
Kojto 109:9296ab0bfc11 2494 /******************* Bit definition for TIM_SMCR register ******************/
Kojto 109:9296ab0bfc11 2495 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 109:9296ab0bfc11 2496 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2497 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2498 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2499
Kojto 109:9296ab0bfc11 2500 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
Kojto 109:9296ab0bfc11 2501
Kojto 109:9296ab0bfc11 2502 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
Kojto 109:9296ab0bfc11 2503 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2504 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2505 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2506
Kojto 109:9296ab0bfc11 2507 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
Kojto 109:9296ab0bfc11 2508
Kojto 109:9296ab0bfc11 2509 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 109:9296ab0bfc11 2510 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2511 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2512 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2513 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2514
Kojto 109:9296ab0bfc11 2515 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 109:9296ab0bfc11 2516 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2517 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2518
Kojto 109:9296ab0bfc11 2519 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
Kojto 109:9296ab0bfc11 2520 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
Kojto 109:9296ab0bfc11 2521
Kojto 109:9296ab0bfc11 2522 /******************* Bit definition for TIM_DIER register ******************/
Kojto 109:9296ab0bfc11 2523 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
Kojto 109:9296ab0bfc11 2524 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
Kojto 109:9296ab0bfc11 2525 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
Kojto 109:9296ab0bfc11 2526 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
Kojto 109:9296ab0bfc11 2527 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
Kojto 109:9296ab0bfc11 2528 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
Kojto 109:9296ab0bfc11 2529 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
Kojto 109:9296ab0bfc11 2530 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
Kojto 109:9296ab0bfc11 2531 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
Kojto 109:9296ab0bfc11 2532 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
Kojto 109:9296ab0bfc11 2533 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
Kojto 109:9296ab0bfc11 2534 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
Kojto 109:9296ab0bfc11 2535 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
Kojto 109:9296ab0bfc11 2536 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
Kojto 109:9296ab0bfc11 2537 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
Kojto 109:9296ab0bfc11 2538
Kojto 109:9296ab0bfc11 2539 /******************** Bit definition for TIM_SR register *******************/
Kojto 109:9296ab0bfc11 2540 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
Kojto 109:9296ab0bfc11 2541 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
Kojto 109:9296ab0bfc11 2542 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
Kojto 109:9296ab0bfc11 2543 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
Kojto 109:9296ab0bfc11 2544 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
Kojto 109:9296ab0bfc11 2545 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
Kojto 109:9296ab0bfc11 2546 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
Kojto 109:9296ab0bfc11 2547 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
Kojto 109:9296ab0bfc11 2548 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 109:9296ab0bfc11 2549 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 109:9296ab0bfc11 2550 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 109:9296ab0bfc11 2551 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 109:9296ab0bfc11 2552
Kojto 109:9296ab0bfc11 2553 /******************* Bit definition for TIM_EGR register *******************/
Kojto 109:9296ab0bfc11 2554 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
Kojto 109:9296ab0bfc11 2555 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
Kojto 109:9296ab0bfc11 2556 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
Kojto 109:9296ab0bfc11 2557 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
Kojto 109:9296ab0bfc11 2558 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
Kojto 109:9296ab0bfc11 2559 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
Kojto 109:9296ab0bfc11 2560 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
Kojto 109:9296ab0bfc11 2561 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
Kojto 109:9296ab0bfc11 2562
Kojto 109:9296ab0bfc11 2563 /****************** Bit definition for TIM_CCMR1 register ******************/
Kojto 109:9296ab0bfc11 2564 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 109:9296ab0bfc11 2565 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2566 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2567
Kojto 109:9296ab0bfc11 2568 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
Kojto 109:9296ab0bfc11 2569 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
Kojto 109:9296ab0bfc11 2570
Kojto 109:9296ab0bfc11 2571 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 109:9296ab0bfc11 2572 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2573 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2574 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2575
Kojto 109:9296ab0bfc11 2576 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
Kojto 109:9296ab0bfc11 2577
Kojto 109:9296ab0bfc11 2578 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 109:9296ab0bfc11 2579 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2580 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2581
Kojto 109:9296ab0bfc11 2582 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
Kojto 109:9296ab0bfc11 2583 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
Kojto 109:9296ab0bfc11 2584
Kojto 109:9296ab0bfc11 2585 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 109:9296ab0bfc11 2586 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2587 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2588 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2589
Kojto 109:9296ab0bfc11 2590 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
Kojto 109:9296ab0bfc11 2591
Kojto 109:9296ab0bfc11 2592 /*---------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 2593
Kojto 109:9296ab0bfc11 2594 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 109:9296ab0bfc11 2595 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2596 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2597
Kojto 109:9296ab0bfc11 2598 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 109:9296ab0bfc11 2599 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2600 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2601 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2602 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2603
Kojto 109:9296ab0bfc11 2604 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 109:9296ab0bfc11 2605 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2606 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2607
Kojto 109:9296ab0bfc11 2608 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 109:9296ab0bfc11 2609 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2610 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2611 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2612 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2613
Kojto 109:9296ab0bfc11 2614 /****************** Bit definition for TIM_CCMR2 register ******************/
Kojto 109:9296ab0bfc11 2615 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 109:9296ab0bfc11 2616 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2617 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2618
Kojto 109:9296ab0bfc11 2619 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
Kojto 109:9296ab0bfc11 2620 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
Kojto 109:9296ab0bfc11 2621
Kojto 109:9296ab0bfc11 2622 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 109:9296ab0bfc11 2623 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2624 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2625 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2626
Kojto 109:9296ab0bfc11 2627 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
Kojto 109:9296ab0bfc11 2628
Kojto 109:9296ab0bfc11 2629 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 109:9296ab0bfc11 2630 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2631 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2632
Kojto 109:9296ab0bfc11 2633 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
Kojto 109:9296ab0bfc11 2634 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
Kojto 109:9296ab0bfc11 2635
Kojto 109:9296ab0bfc11 2636 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 109:9296ab0bfc11 2637 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2638 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2639 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2640
Kojto 109:9296ab0bfc11 2641 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
Kojto 109:9296ab0bfc11 2642
Kojto 109:9296ab0bfc11 2643 /*---------------------------------------------------------------------------*/
Kojto 109:9296ab0bfc11 2644
Kojto 109:9296ab0bfc11 2645 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 109:9296ab0bfc11 2646 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2647 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2648
Kojto 109:9296ab0bfc11 2649 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 109:9296ab0bfc11 2650 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2651 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2652 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2653 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2654
Kojto 109:9296ab0bfc11 2655 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 109:9296ab0bfc11 2656 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2657 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2658
Kojto 109:9296ab0bfc11 2659 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 109:9296ab0bfc11 2660 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2661 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2662 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2663 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2664
Kojto 109:9296ab0bfc11 2665 /******************* Bit definition for TIM_CCER register ******************/
Kojto 109:9296ab0bfc11 2666 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
Kojto 109:9296ab0bfc11 2667 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
Kojto 109:9296ab0bfc11 2668 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
Kojto 109:9296ab0bfc11 2669 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 109:9296ab0bfc11 2670 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
Kojto 109:9296ab0bfc11 2671 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
Kojto 109:9296ab0bfc11 2672 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
Kojto 109:9296ab0bfc11 2673 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 109:9296ab0bfc11 2674 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
Kojto 109:9296ab0bfc11 2675 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
Kojto 109:9296ab0bfc11 2676 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
Kojto 109:9296ab0bfc11 2677 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 109:9296ab0bfc11 2678 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
Kojto 109:9296ab0bfc11 2679 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
Kojto 109:9296ab0bfc11 2680 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 109:9296ab0bfc11 2681
Kojto 109:9296ab0bfc11 2682 /******************* Bit definition for TIM_CNT register *******************/
Kojto 109:9296ab0bfc11 2683 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
Kojto 109:9296ab0bfc11 2684
Kojto 109:9296ab0bfc11 2685 /******************* Bit definition for TIM_PSC register *******************/
Kojto 109:9296ab0bfc11 2686 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
Kojto 109:9296ab0bfc11 2687
Kojto 109:9296ab0bfc11 2688 /******************* Bit definition for TIM_ARR register *******************/
Kojto 109:9296ab0bfc11 2689 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
Kojto 109:9296ab0bfc11 2690
Kojto 109:9296ab0bfc11 2691 /******************* Bit definition for TIM_RCR register *******************/
Kojto 109:9296ab0bfc11 2692 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
Kojto 109:9296ab0bfc11 2693
Kojto 109:9296ab0bfc11 2694 /******************* Bit definition for TIM_CCR1 register ******************/
Kojto 109:9296ab0bfc11 2695 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
Kojto 109:9296ab0bfc11 2696
Kojto 109:9296ab0bfc11 2697 /******************* Bit definition for TIM_CCR2 register ******************/
Kojto 109:9296ab0bfc11 2698 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
Kojto 109:9296ab0bfc11 2699
Kojto 109:9296ab0bfc11 2700 /******************* Bit definition for TIM_CCR3 register ******************/
Kojto 109:9296ab0bfc11 2701 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
Kojto 109:9296ab0bfc11 2702
Kojto 109:9296ab0bfc11 2703 /******************* Bit definition for TIM_CCR4 register ******************/
Kojto 109:9296ab0bfc11 2704 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
Kojto 109:9296ab0bfc11 2705
Kojto 109:9296ab0bfc11 2706 /******************* Bit definition for TIM_BDTR register ******************/
Kojto 109:9296ab0bfc11 2707 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
Kojto 109:9296ab0bfc11 2708 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2709 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2710 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2711 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2712 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 2713 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 2714 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 2715 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
Kojto 109:9296ab0bfc11 2716
Kojto 109:9296ab0bfc11 2717 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
Kojto 109:9296ab0bfc11 2718 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2719 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2720
Kojto 109:9296ab0bfc11 2721 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
Kojto 109:9296ab0bfc11 2722 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
Kojto 109:9296ab0bfc11 2723 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
Kojto 109:9296ab0bfc11 2724 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
Kojto 109:9296ab0bfc11 2725 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
Kojto 109:9296ab0bfc11 2726 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
Kojto 109:9296ab0bfc11 2727
Kojto 109:9296ab0bfc11 2728 /******************* Bit definition for TIM_DCR register *******************/
Kojto 109:9296ab0bfc11 2729 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 109:9296ab0bfc11 2730 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2731 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2732 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2733 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2734 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 2735
Kojto 109:9296ab0bfc11 2736 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 109:9296ab0bfc11 2737 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2738 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2739 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2740 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2741 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 2742
Kojto 109:9296ab0bfc11 2743 /******************* Bit definition for TIM_DMAR register ******************/
Kojto 109:9296ab0bfc11 2744 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
Kojto 109:9296ab0bfc11 2745
Kojto 109:9296ab0bfc11 2746 /******************* Bit definition for TIM14_OR register ********************/
Kojto 109:9296ab0bfc11 2747 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
Kojto 109:9296ab0bfc11 2748 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2749 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2750
Kojto 109:9296ab0bfc11 2751 /******************************************************************************/
Kojto 109:9296ab0bfc11 2752 /* */
Kojto 109:9296ab0bfc11 2753 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 109:9296ab0bfc11 2754 /* */
Kojto 109:9296ab0bfc11 2755 /******************************************************************************/
Kojto 109:9296ab0bfc11 2756 /****************** Bit definition for USART_CR1 register *******************/
Kojto 109:9296ab0bfc11 2757 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
Kojto 109:9296ab0bfc11 2758 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
Kojto 109:9296ab0bfc11 2759 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
Kojto 109:9296ab0bfc11 2760 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
Kojto 109:9296ab0bfc11 2761 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
Kojto 109:9296ab0bfc11 2762 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
Kojto 109:9296ab0bfc11 2763 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
Kojto 109:9296ab0bfc11 2764 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
Kojto 109:9296ab0bfc11 2765 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
Kojto 109:9296ab0bfc11 2766 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
Kojto 109:9296ab0bfc11 2767 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
Kojto 109:9296ab0bfc11 2768 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
Kojto 109:9296ab0bfc11 2769 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
Kojto 109:9296ab0bfc11 2770 #define USART_CR1_M ((uint32_t)0x00001000) /*!< SmartCard Length */
Kojto 109:9296ab0bfc11 2771 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
Kojto 109:9296ab0bfc11 2772 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
Kojto 109:9296ab0bfc11 2773 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 109:9296ab0bfc11 2774 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 109:9296ab0bfc11 2775 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2776 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2777 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 2778 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 2779 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 2780 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 109:9296ab0bfc11 2781 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2782 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2783 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 2784 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
Kojto 109:9296ab0bfc11 2785 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
Kojto 109:9296ab0bfc11 2786 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
Kojto 109:9296ab0bfc11 2787 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
Kojto 109:9296ab0bfc11 2788
Kojto 109:9296ab0bfc11 2789 /****************** Bit definition for USART_CR2 register *******************/
Kojto 109:9296ab0bfc11 2790 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
Kojto 109:9296ab0bfc11 2791 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
Kojto 109:9296ab0bfc11 2792 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
Kojto 109:9296ab0bfc11 2793 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
Kojto 109:9296ab0bfc11 2794 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
Kojto 109:9296ab0bfc11 2795 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
Kojto 109:9296ab0bfc11 2796 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
Kojto 109:9296ab0bfc11 2797 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
Kojto 109:9296ab0bfc11 2798 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2799 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2800 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
Kojto 109:9296ab0bfc11 2801 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
Kojto 109:9296ab0bfc11 2802 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
Kojto 109:9296ab0bfc11 2803 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
Kojto 109:9296ab0bfc11 2804 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
Kojto 109:9296ab0bfc11 2805 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
Kojto 109:9296ab0bfc11 2806 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
Kojto 109:9296ab0bfc11 2807 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 109:9296ab0bfc11 2808 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2809 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2810 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
Kojto 109:9296ab0bfc11 2811 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
Kojto 109:9296ab0bfc11 2812
Kojto 109:9296ab0bfc11 2813 /****************** Bit definition for USART_CR3 register *******************/
Kojto 109:9296ab0bfc11 2814 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
Kojto 109:9296ab0bfc11 2815 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
Kojto 109:9296ab0bfc11 2816 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
Kojto 109:9296ab0bfc11 2817 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
Kojto 109:9296ab0bfc11 2818 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
Kojto 109:9296ab0bfc11 2819 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
Kojto 109:9296ab0bfc11 2820 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
Kojto 109:9296ab0bfc11 2821 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
Kojto 109:9296ab0bfc11 2822 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
Kojto 109:9296ab0bfc11 2823 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
Kojto 109:9296ab0bfc11 2824 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
Kojto 109:9296ab0bfc11 2825 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
Kojto 109:9296ab0bfc11 2826 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
Kojto 109:9296ab0bfc11 2827 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
Kojto 109:9296ab0bfc11 2828 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
Kojto 109:9296ab0bfc11 2829 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
Kojto 109:9296ab0bfc11 2830 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 109:9296ab0bfc11 2831 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2832 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2833 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
Kojto 109:9296ab0bfc11 2834 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
Kojto 109:9296ab0bfc11 2835 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
Kojto 109:9296ab0bfc11 2836 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
Kojto 109:9296ab0bfc11 2837 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
Kojto 109:9296ab0bfc11 2838
Kojto 109:9296ab0bfc11 2839 /****************** Bit definition for USART_BRR register *******************/
Kojto 109:9296ab0bfc11 2840 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
Kojto 109:9296ab0bfc11 2841 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
Kojto 109:9296ab0bfc11 2842
Kojto 109:9296ab0bfc11 2843 /****************** Bit definition for USART_GTPR register ******************/
Kojto 109:9296ab0bfc11 2844 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
Kojto 109:9296ab0bfc11 2845 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
Kojto 109:9296ab0bfc11 2846
Kojto 109:9296ab0bfc11 2847
Kojto 109:9296ab0bfc11 2848 /******************* Bit definition for USART_RTOR register *****************/
Kojto 109:9296ab0bfc11 2849 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
Kojto 109:9296ab0bfc11 2850 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
Kojto 109:9296ab0bfc11 2851
Kojto 109:9296ab0bfc11 2852 /******************* Bit definition for USART_RQR register ******************/
Kojto 109:9296ab0bfc11 2853 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
Kojto 109:9296ab0bfc11 2854 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
Kojto 109:9296ab0bfc11 2855 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
Kojto 109:9296ab0bfc11 2856 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
Kojto 109:9296ab0bfc11 2857 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
Kojto 109:9296ab0bfc11 2858
Kojto 109:9296ab0bfc11 2859 /******************* Bit definition for USART_ISR register ******************/
Kojto 109:9296ab0bfc11 2860 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
Kojto 109:9296ab0bfc11 2861 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
Kojto 109:9296ab0bfc11 2862 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
Kojto 109:9296ab0bfc11 2863 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
Kojto 109:9296ab0bfc11 2864 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
Kojto 109:9296ab0bfc11 2865 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
Kojto 109:9296ab0bfc11 2866 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
Kojto 109:9296ab0bfc11 2867 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
Kojto 109:9296ab0bfc11 2868 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
Kojto 109:9296ab0bfc11 2869 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
Kojto 109:9296ab0bfc11 2870 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
Kojto 109:9296ab0bfc11 2871 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
Kojto 109:9296ab0bfc11 2872 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
Kojto 109:9296ab0bfc11 2873 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
Kojto 109:9296ab0bfc11 2874 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
Kojto 109:9296ab0bfc11 2875 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
Kojto 109:9296ab0bfc11 2876 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
Kojto 109:9296ab0bfc11 2877 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
Kojto 109:9296ab0bfc11 2878 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
Kojto 109:9296ab0bfc11 2879 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
Kojto 109:9296ab0bfc11 2880 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
Kojto 109:9296ab0bfc11 2881 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
Kojto 109:9296ab0bfc11 2882
Kojto 109:9296ab0bfc11 2883 /******************* Bit definition for USART_ICR register ******************/
Kojto 109:9296ab0bfc11 2884 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
Kojto 109:9296ab0bfc11 2885 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
Kojto 109:9296ab0bfc11 2886 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
Kojto 109:9296ab0bfc11 2887 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
Kojto 109:9296ab0bfc11 2888 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
Kojto 109:9296ab0bfc11 2889 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
Kojto 109:9296ab0bfc11 2890 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
Kojto 109:9296ab0bfc11 2891 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
Kojto 109:9296ab0bfc11 2892 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
Kojto 109:9296ab0bfc11 2893 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
Kojto 109:9296ab0bfc11 2894 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
Kojto 109:9296ab0bfc11 2895 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
Kojto 109:9296ab0bfc11 2896
Kojto 109:9296ab0bfc11 2897 /******************* Bit definition for USART_RDR register ******************/
Kojto 109:9296ab0bfc11 2898 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
Kojto 109:9296ab0bfc11 2899
Kojto 109:9296ab0bfc11 2900 /******************* Bit definition for USART_TDR register ******************/
Kojto 109:9296ab0bfc11 2901 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 109:9296ab0bfc11 2902
Kojto 109:9296ab0bfc11 2903 /******************************************************************************/
Kojto 109:9296ab0bfc11 2904 /* */
Kojto 109:9296ab0bfc11 2905 /* Window WATCHDOG (WWDG) */
Kojto 109:9296ab0bfc11 2906 /* */
Kojto 109:9296ab0bfc11 2907 /******************************************************************************/
Kojto 109:9296ab0bfc11 2908 /******************* Bit definition for WWDG_CR register ********************/
Kojto 109:9296ab0bfc11 2909 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 109:9296ab0bfc11 2910 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2911 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2912 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2913 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2914 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 2915 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 2916 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 2917
Kojto 109:9296ab0bfc11 2918 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
Kojto 109:9296ab0bfc11 2919
Kojto 109:9296ab0bfc11 2920 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 109:9296ab0bfc11 2921 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
Kojto 109:9296ab0bfc11 2922 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2923 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2924 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
Kojto 109:9296ab0bfc11 2925 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
Kojto 109:9296ab0bfc11 2926 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
Kojto 109:9296ab0bfc11 2927 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
Kojto 109:9296ab0bfc11 2928 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
Kojto 109:9296ab0bfc11 2929
Kojto 109:9296ab0bfc11 2930 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
Kojto 109:9296ab0bfc11 2931 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
Kojto 109:9296ab0bfc11 2932 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
Kojto 109:9296ab0bfc11 2933
Kojto 109:9296ab0bfc11 2934 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
Kojto 109:9296ab0bfc11 2935
Kojto 109:9296ab0bfc11 2936 /******************* Bit definition for WWDG_SR register ********************/
Kojto 109:9296ab0bfc11 2937 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
Kojto 109:9296ab0bfc11 2938
Kojto 109:9296ab0bfc11 2939 /**
Kojto 109:9296ab0bfc11 2940 * @}
Kojto 109:9296ab0bfc11 2941 */
Kojto 109:9296ab0bfc11 2942
Kojto 109:9296ab0bfc11 2943 /**
Kojto 109:9296ab0bfc11 2944 * @}
Kojto 109:9296ab0bfc11 2945 */
Kojto 109:9296ab0bfc11 2946
Kojto 109:9296ab0bfc11 2947
Kojto 109:9296ab0bfc11 2948 /** @addtogroup Exported_macro
Kojto 109:9296ab0bfc11 2949 * @{
Kojto 109:9296ab0bfc11 2950 */
Kojto 109:9296ab0bfc11 2951
Kojto 109:9296ab0bfc11 2952 /****************************** ADC Instances *********************************/
Kojto 109:9296ab0bfc11 2953 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 109:9296ab0bfc11 2954
Kojto 109:9296ab0bfc11 2955 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
Kojto 109:9296ab0bfc11 2956
Kojto 109:9296ab0bfc11 2957 /****************************** CRC Instances *********************************/
Kojto 109:9296ab0bfc11 2958 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 109:9296ab0bfc11 2959
Kojto 109:9296ab0bfc11 2960 /******************************* DMA Instances ******************************/
Kojto 109:9296ab0bfc11 2961 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
Kojto 109:9296ab0bfc11 2962 ((INSTANCE) == DMA1_Channel2) || \
Kojto 109:9296ab0bfc11 2963 ((INSTANCE) == DMA1_Channel3) || \
Kojto 109:9296ab0bfc11 2964 ((INSTANCE) == DMA1_Channel4) || \
Kojto 109:9296ab0bfc11 2965 ((INSTANCE) == DMA1_Channel5))
Kojto 109:9296ab0bfc11 2966
Kojto 109:9296ab0bfc11 2967 /****************************** GPIO Instances ********************************/
Kojto 109:9296ab0bfc11 2968 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 109:9296ab0bfc11 2969 ((INSTANCE) == GPIOB) || \
Kojto 109:9296ab0bfc11 2970 ((INSTANCE) == GPIOC) || \
Kojto 109:9296ab0bfc11 2971 ((INSTANCE) == GPIOF))
Kojto 109:9296ab0bfc11 2972
Kojto 109:9296ab0bfc11 2973 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 109:9296ab0bfc11 2974 ((INSTANCE) == GPIOB))
Kojto 109:9296ab0bfc11 2975
Kojto 109:9296ab0bfc11 2976 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 109:9296ab0bfc11 2977 ((INSTANCE) == GPIOB))
Kojto 109:9296ab0bfc11 2978
Kojto 109:9296ab0bfc11 2979 /****************************** I2C Instances *********************************/
Kojto 109:9296ab0bfc11 2980 #define IS_I2C_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 109:9296ab0bfc11 2981
Kojto 109:9296ab0bfc11 2982 /****************************** I2S Instances *********************************/
Kojto 109:9296ab0bfc11 2983 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
Kojto 109:9296ab0bfc11 2984
Kojto 109:9296ab0bfc11 2985 /****************************** IWDG Instances ********************************/
Kojto 109:9296ab0bfc11 2986 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 109:9296ab0bfc11 2987
Kojto 109:9296ab0bfc11 2988 /****************************** RTC Instances *********************************/
Kojto 109:9296ab0bfc11 2989 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 109:9296ab0bfc11 2990
Kojto 109:9296ab0bfc11 2991 /****************************** SMBUS Instances *********************************/
Kojto 109:9296ab0bfc11 2992 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 109:9296ab0bfc11 2993
Kojto 109:9296ab0bfc11 2994 /****************************** SPI Instances *********************************/
Kojto 109:9296ab0bfc11 2995 #define IS_SPI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI1)
Kojto 109:9296ab0bfc11 2996
Kojto 109:9296ab0bfc11 2997 /****************************** TIM Instances *********************************/
Kojto 109:9296ab0bfc11 2998 #define IS_TIM_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 2999 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3000 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3001 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 3002 ((INSTANCE) == TIM14) || \
Kojto 109:9296ab0bfc11 3003 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 3004 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 3005
Kojto 109:9296ab0bfc11 3006 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3007 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3008 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3009 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 3010 ((INSTANCE) == TIM14) || \
Kojto 109:9296ab0bfc11 3011 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 3012 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 3013
Kojto 109:9296ab0bfc11 3014 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3015 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3016 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3017 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3018
Kojto 109:9296ab0bfc11 3019 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3020 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3021 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3022 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3023
Kojto 109:9296ab0bfc11 3024 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3025 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3026 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3027 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3028
Kojto 109:9296ab0bfc11 3029
Kojto 109:9296ab0bfc11 3030 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3031 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3032 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3033 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3034
Kojto 109:9296ab0bfc11 3035 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3036 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3037 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3038 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3039
Kojto 109:9296ab0bfc11 3040 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3041 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3042 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3043 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3044
Kojto 109:9296ab0bfc11 3045 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3046 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3047 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3048 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3049
Kojto 109:9296ab0bfc11 3050 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3051 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3052 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3053 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3054
Kojto 109:9296ab0bfc11 3055 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3056 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3057 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3058 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3059
Kojto 109:9296ab0bfc11 3060 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3061 (((INSTANCE) == TIM1))
Kojto 109:9296ab0bfc11 3062
Kojto 109:9296ab0bfc11 3063 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3064 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3065 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3066 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3067
Kojto 109:9296ab0bfc11 3068 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3069 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3070 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3071 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3072
Kojto 109:9296ab0bfc11 3073 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3074 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3075 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3076 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3077
Kojto 109:9296ab0bfc11 3078 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3079 ((INSTANCE) == TIM2)
Kojto 109:9296ab0bfc11 3080
Kojto 109:9296ab0bfc11 3081 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3082 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3083 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3084 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 3085 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 3086 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 3087
Kojto 109:9296ab0bfc11 3088 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3089 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3090 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 3091 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 3092
Kojto 109:9296ab0bfc11 3093 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 109:9296ab0bfc11 3094 ((((INSTANCE) == TIM1) && \
Kojto 109:9296ab0bfc11 3095 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 3096 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 3097 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 109:9296ab0bfc11 3098 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 109:9296ab0bfc11 3099 || \
Kojto 109:9296ab0bfc11 3100 (((INSTANCE) == TIM2) && \
Kojto 109:9296ab0bfc11 3101 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 3102 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 3103 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 109:9296ab0bfc11 3104 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 109:9296ab0bfc11 3105 || \
Kojto 109:9296ab0bfc11 3106 (((INSTANCE) == TIM3) && \
Kojto 109:9296ab0bfc11 3107 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 3108 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 3109 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 109:9296ab0bfc11 3110 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 109:9296ab0bfc11 3111 || \
Kojto 109:9296ab0bfc11 3112 (((INSTANCE) == TIM14) && \
Kojto 109:9296ab0bfc11 3113 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 109:9296ab0bfc11 3114 || \
Kojto 109:9296ab0bfc11 3115 (((INSTANCE) == TIM16) && \
Kojto 109:9296ab0bfc11 3116 (((CHANNEL) == TIM_CHANNEL_1))) \
Kojto 109:9296ab0bfc11 3117 || \
Kojto 109:9296ab0bfc11 3118 (((INSTANCE) == TIM17) && \
Kojto 109:9296ab0bfc11 3119 (((CHANNEL) == TIM_CHANNEL_1))))
Kojto 109:9296ab0bfc11 3120
Kojto 109:9296ab0bfc11 3121 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
Kojto 109:9296ab0bfc11 3122 ((((INSTANCE) == TIM1) && \
Kojto 109:9296ab0bfc11 3123 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 109:9296ab0bfc11 3124 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 109:9296ab0bfc11 3125 ((CHANNEL) == TIM_CHANNEL_3))) \
Kojto 109:9296ab0bfc11 3126 || \
Kojto 109:9296ab0bfc11 3127 (((INSTANCE) == TIM16) && \
Kojto 109:9296ab0bfc11 3128 ((CHANNEL) == TIM_CHANNEL_1)) \
Kojto 109:9296ab0bfc11 3129 || \
Kojto 109:9296ab0bfc11 3130 (((INSTANCE) == TIM17) && \
Kojto 109:9296ab0bfc11 3131 ((CHANNEL) == TIM_CHANNEL_1)))
Kojto 109:9296ab0bfc11 3132
Kojto 109:9296ab0bfc11 3133 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3134 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3135 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3136 ((INSTANCE) == TIM3))
Kojto 109:9296ab0bfc11 3137
Kojto 109:9296ab0bfc11 3138 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3139 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3140 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 3141 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 3142
Kojto 109:9296ab0bfc11 3143 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3144 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3145 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3146 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 3147 ((INSTANCE) == TIM14) || \
Kojto 109:9296ab0bfc11 3148 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 3149 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 3150
Kojto 109:9296ab0bfc11 3151 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3152 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3153 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3154 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 3155 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 3156 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 3157
Kojto 109:9296ab0bfc11 3158 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3159 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3160 ((INSTANCE) == TIM2) || \
Kojto 109:9296ab0bfc11 3161 ((INSTANCE) == TIM3) || \
Kojto 109:9296ab0bfc11 3162 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 3163 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 3164
Kojto 109:9296ab0bfc11 3165 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3166 (((INSTANCE) == TIM1) || \
Kojto 109:9296ab0bfc11 3167 ((INSTANCE) == TIM16) || \
Kojto 109:9296ab0bfc11 3168 ((INSTANCE) == TIM17))
Kojto 109:9296ab0bfc11 3169
Kojto 109:9296ab0bfc11 3170 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
Kojto 109:9296ab0bfc11 3171 ((INSTANCE) == TIM14)
Kojto 109:9296ab0bfc11 3172
Kojto 109:9296ab0bfc11 3173 /*********************** UART Instances : IRDA mode ***************************/
Kojto 109:9296ab0bfc11 3174 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
Kojto 109:9296ab0bfc11 3175
Kojto 109:9296ab0bfc11 3176 /********************* UART Instances : Smard card mode ***********************/
Kojto 109:9296ab0bfc11 3177 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
Kojto 109:9296ab0bfc11 3178
Kojto 109:9296ab0bfc11 3179 /******************** USART Instances : Synchronous mode **********************/
Kojto 109:9296ab0bfc11 3180 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
Kojto 109:9296ab0bfc11 3181
Kojto 109:9296ab0bfc11 3182 /******************** USART Instances : auto Baud rate detection **************/
Kojto 109:9296ab0bfc11 3183 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
Kojto 109:9296ab0bfc11 3184
Kojto 109:9296ab0bfc11 3185 /******************** UART Instances : Asynchronous mode **********************/
Kojto 109:9296ab0bfc11 3186 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
Kojto 109:9296ab0bfc11 3187
Kojto 109:9296ab0bfc11 3188 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 109:9296ab0bfc11 3189 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 3190
Kojto 109:9296ab0bfc11 3191 /****************** UART Instances : Hardware Flow control ********************/
Kojto 109:9296ab0bfc11 3192 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
Kojto 109:9296ab0bfc11 3193
Kojto 109:9296ab0bfc11 3194 /****************** UART Instances : LIN mode ********************/
Kojto 109:9296ab0bfc11 3195 #define IS_UART_LIN_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 3196
Kojto 109:9296ab0bfc11 3197 /****************** UART Instances : wakeup from stop mode ********************/
Kojto 109:9296ab0bfc11 3198 #define IS_UART_WAKEUP_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
Kojto 109:9296ab0bfc11 3199
Kojto 109:9296ab0bfc11 3200 /****************** UART Instances : Auto Baud Rate detection ********************/
Kojto 109:9296ab0bfc11 3201 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
Kojto 109:9296ab0bfc11 3202
Kojto 109:9296ab0bfc11 3203 /****************** UART Instances : Driver enable detection ********************/
Kojto 109:9296ab0bfc11 3204 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1))
Kojto 109:9296ab0bfc11 3205
Kojto 109:9296ab0bfc11 3206 /****************************** WWDG Instances ********************************/
Kojto 109:9296ab0bfc11 3207 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 109:9296ab0bfc11 3208
Kojto 109:9296ab0bfc11 3209 /**
Kojto 109:9296ab0bfc11 3210 * @}
Kojto 109:9296ab0bfc11 3211 */
Kojto 109:9296ab0bfc11 3212
Kojto 109:9296ab0bfc11 3213
Kojto 109:9296ab0bfc11 3214 /******************************************************************************/
Kojto 109:9296ab0bfc11 3215 /* For a painless codes migration between the STM32F0xx device product */
Kojto 109:9296ab0bfc11 3216 /* lines, the aliases defined below are put in place to overcome the */
Kojto 109:9296ab0bfc11 3217 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 109:9296ab0bfc11 3218 /* No need to update developed interrupt code when moving across */
Kojto 109:9296ab0bfc11 3219 /* product lines within the same STM32F0 Family */
Kojto 109:9296ab0bfc11 3220 /******************************************************************************/
Kojto 109:9296ab0bfc11 3221
Kojto 109:9296ab0bfc11 3222 /* Aliases for __IRQn */
Kojto 109:9296ab0bfc11 3223 #define PVD_VDDIO2_IRQn PVD_IRQn
Kojto 109:9296ab0bfc11 3224 #define RCC_CRS_IRQn RCC_IRQn
Kojto 109:9296ab0bfc11 3225 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
Kojto 109:9296ab0bfc11 3226 #define ADC1_COMP_IRQn ADC1_IRQn
Kojto 109:9296ab0bfc11 3227
Kojto 109:9296ab0bfc11 3228 /* Aliases for __IRQHandler */
Kojto 109:9296ab0bfc11 3229 #define PVD_VDDIO2_IRQHandler PVD_IRQHandler
Kojto 109:9296ab0bfc11 3230 #define RCC_CRS_IRQHandler RCC_IRQHandler
Kojto 109:9296ab0bfc11 3231 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
Kojto 109:9296ab0bfc11 3232 #define ADC1_COMP_IRQHandler ADC1_IRQHandler
Kojto 109:9296ab0bfc11 3233
Kojto 109:9296ab0bfc11 3234 #ifdef __cplusplus
Kojto 109:9296ab0bfc11 3235 }
Kojto 109:9296ab0bfc11 3236 #endif /* __cplusplus */
Kojto 109:9296ab0bfc11 3237
Kojto 109:9296ab0bfc11 3238 #endif /* __STM32F031x6_H */
Kojto 109:9296ab0bfc11 3239
Kojto 109:9296ab0bfc11 3240 /**
Kojto 109:9296ab0bfc11 3241 * @}
Kojto 109:9296ab0bfc11 3242 */
Kojto 109:9296ab0bfc11 3243
Kojto 109:9296ab0bfc11 3244 /**
Kojto 109:9296ab0bfc11 3245 * @}
Kojto 109:9296ab0bfc11 3246 */
Kojto 109:9296ab0bfc11 3247
Kojto 109:9296ab0bfc11 3248 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/