Ricardo Benitez / mbed

meh

Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32f4xx_hal_adc_ex.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:
emilmont
Date:
Fri Feb 14 14:36:43 2014 +0000
Revision:
77:869cf507173a
Child:
81:7d30d6019079
Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_adc.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.0.0RC2
emilmont 77:869cf507173a 6 * @date 04-February-2014
emilmont 77:869cf507173a 7 * @brief Header file of ADC HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_ADC_EX_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_ADC_EX_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup ADCEx
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58
emilmont 77:869cf507173a 59 /**
emilmont 77:869cf507173a 60 * @brief ADC Configuration injected Channel structure definition
emilmont 77:869cf507173a 61 */
emilmont 77:869cf507173a 62 typedef struct
emilmont 77:869cf507173a 63 {
emilmont 77:869cf507173a 64 uint32_t InjectedChannel; /*!< Configure the ADC injected channel
emilmont 77:869cf507173a 65 This parameter can be a value of @ref ADC_channels. */
emilmont 77:869cf507173a 66 uint32_t InjectedRank; /*!< The rank in the injected group sequencer
emilmont 77:869cf507173a 67 This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
emilmont 77:869cf507173a 68 uint32_t InjectedSamplingTime; /*!< The sample time value to be set for the selected channel.
emilmont 77:869cf507173a 69 This parameter can be a value of @ref ADC_sampling_times */
emilmont 77:869cf507173a 70 uint32_t InjectedOffset; /*!< Defines the offset to be subtracted from the raw converted data when convert injected channels.
emilmont 77:869cf507173a 71 This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
emilmont 77:869cf507173a 72 uint32_t InjectedNbrOfConversion; /*!< Specifies the number of ADC conversions that will be done using the sequencer for
emilmont 77:869cf507173a 73 injected channel group.
emilmont 77:869cf507173a 74 This parameter must be a number between Min_Data = 1 and Max_Data = 4. */
emilmont 77:869cf507173a 75 uint32_t AutoInjectedConv; /*!< Enables or disables the selected ADC automatic injected group
emilmont 77:869cf507173a 76 conversion after regular one */
emilmont 77:869cf507173a 77 uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversion is performed in Discontinuous mode or not for injected channels.
emilmont 77:869cf507173a 78 This parameter can be set to ENABLE or DISABLE. */
emilmont 77:869cf507173a 79 uint32_t ExternalTrigInjecConvEdge; /*!< Select the external trigger edge and enable the trigger of an injected channels.
emilmont 77:869cf507173a 80 This parameter can be a value of @ref ADC_External_trigger_Source_Injected. */
emilmont 77:869cf507173a 81 uint32_t ExternalTrigInjecConv; /*!< Select the external event used to trigger the start of conversion of a injected channels.
emilmont 77:869cf507173a 82 This parameter can be a value of @ref ADC_External_trigger_Source_Injected */
emilmont 77:869cf507173a 83 }ADC_InjectionConfTypeDef;
emilmont 77:869cf507173a 84
emilmont 77:869cf507173a 85 /**
emilmont 77:869cf507173a 86 * @brief ADC Configuration multi-mode structure definition
emilmont 77:869cf507173a 87 */
emilmont 77:869cf507173a 88 typedef struct
emilmont 77:869cf507173a 89 {
emilmont 77:869cf507173a 90 uint32_t Mode; /*!< Configures the ADC to operate in independent or multi mode.
emilmont 77:869cf507173a 91 This parameter can be a value of @ref ADC_Common_mode */
emilmont 77:869cf507173a 92 uint32_t DMAAccessMode; /*!< Configures the Direct memory access mode for multi ADC mode.
emilmont 77:869cf507173a 93 This parameter can be a value of @ref ADC_Direct_memory_access_mode_for_multi_mode */
emilmont 77:869cf507173a 94 uint32_t TwoSamplingDelay; /*!< Configures the Delay between 2 sampling phases.
emilmont 77:869cf507173a 95 This parameter can be a value of @ref ADC_delay_between_2_sampling_phases */
emilmont 77:869cf507173a 96 }ADC_MultiModeTypeDef;
emilmont 77:869cf507173a 97
emilmont 77:869cf507173a 98 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 99
emilmont 77:869cf507173a 100 /** @defgroup ADCEx_Exported_Constants
emilmont 77:869cf507173a 101 * @{
emilmont 77:869cf507173a 102 */
emilmont 77:869cf507173a 103
emilmont 77:869cf507173a 104
emilmont 77:869cf507173a 105 /** @defgroup ADCEx_Common_mode
emilmont 77:869cf507173a 106 * @{
emilmont 77:869cf507173a 107 */
emilmont 77:869cf507173a 108 #define ADC_MODE_INDEPENDENT ((uint32_t)0x00000000)
emilmont 77:869cf507173a 109 #define ADC_DUALMODE_REGSIMULT_INJECSIMULT ((uint32_t)ADC_CCR_MULTI_0)
emilmont 77:869cf507173a 110 #define ADC_DUALMODE_REGSIMULT_ALTERTRIG ((uint32_t)ADC_CCR_MULTI_1)
emilmont 77:869cf507173a 111 #define ADC_DUALMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
emilmont 77:869cf507173a 112 #define ADC_DUALMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
emilmont 77:869cf507173a 113 #define ADC_DUALMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
emilmont 77:869cf507173a 114 #define ADC_DUALMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
emilmont 77:869cf507173a 115 #define ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_0))
emilmont 77:869cf507173a 116 #define ADC_TRIPLEMODE_REGSIMULT_AlterTrig ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_1))
emilmont 77:869cf507173a 117 #define ADC_TRIPLEMODE_INJECSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_0))
emilmont 77:869cf507173a 118 #define ADC_TRIPLEMODE_REGSIMULT ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1))
emilmont 77:869cf507173a 119 #define ADC_TRIPLEMODE_INTERL ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_2 | ADC_CCR_MULTI_1 | ADC_CCR_MULTI_0))
emilmont 77:869cf507173a 120 #define ADC_TRIPLEMODE_ALTERTRIG ((uint32_t)(ADC_CCR_MULTI_4 | ADC_CCR_MULTI_3 | ADC_CCR_MULTI_0))
emilmont 77:869cf507173a 121
emilmont 77:869cf507173a 122 #define IS_ADC_MODE(MODE) (((MODE) == ADC_MODE_INDEPENDENT) || \
emilmont 77:869cf507173a 123 ((MODE) == ADC_DUALMODE_REGSIMULT_INJECSIMULT) || \
emilmont 77:869cf507173a 124 ((MODE) == ADC_DUALMODE_REGSIMULT_ALTERTRIG) || \
emilmont 77:869cf507173a 125 ((MODE) == ADC_DUALMODE_INJECSIMULT) || \
emilmont 77:869cf507173a 126 ((MODE) == ADC_DUALMODE_REGSIMULT) || \
emilmont 77:869cf507173a 127 ((MODE) == ADC_DUALMODE_INTERL) || \
emilmont 77:869cf507173a 128 ((MODE) == ADC_DUALMODE_ALTERTRIG) || \
emilmont 77:869cf507173a 129 ((MODE) == ADC_TRIPLEMODE_REGSIMULT_INJECSIMULT) || \
emilmont 77:869cf507173a 130 ((MODE) == ADC_TRIPLEMODE_REGSIMULT_AlterTrig) || \
emilmont 77:869cf507173a 131 ((MODE) == ADC_TRIPLEMODE_INJECSIMULT) || \
emilmont 77:869cf507173a 132 ((MODE) == ADC_TRIPLEMODE_REGSIMULT) || \
emilmont 77:869cf507173a 133 ((MODE) == ADC_TRIPLEMODE_INTERL) || \
emilmont 77:869cf507173a 134 ((MODE) == ADC_TRIPLEMODE_ALTERTRIG))
emilmont 77:869cf507173a 135 /**
emilmont 77:869cf507173a 136 * @}
emilmont 77:869cf507173a 137 */
emilmont 77:869cf507173a 138
emilmont 77:869cf507173a 139 /** @defgroup ADCEx_Direct_memory_access_mode_for_multi_mode
emilmont 77:869cf507173a 140 * @{
emilmont 77:869cf507173a 141 */
emilmont 77:869cf507173a 142 #define ADC_DMAACCESSMODE_DISABLED ((uint32_t)0x00000000) /*!< DMA mode disabled */
emilmont 77:869cf507173a 143 #define ADC_DMAACCESSMODE_1 ((uint32_t)ADC_CCR_DMA_0) /*!< DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
emilmont 77:869cf507173a 144 #define ADC_DMAACCESSMODE_2 ((uint32_t)ADC_CCR_DMA_1) /*!< DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
emilmont 77:869cf507173a 145 #define ADC_DMAACCESSMODE_3 ((uint32_t)ADC_CCR_DMA) /*!< DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
emilmont 77:869cf507173a 146
emilmont 77:869cf507173a 147 #define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAACCESSMODE_DISABLED) || \
emilmont 77:869cf507173a 148 ((MODE) == ADC_DMAACCESSMODE_1) || \
emilmont 77:869cf507173a 149 ((MODE) == ADC_DMAACCESSMODE_2) || \
emilmont 77:869cf507173a 150 ((MODE) == ADC_DMAACCESSMODE_3))
emilmont 77:869cf507173a 151 /**
emilmont 77:869cf507173a 152 * @}
emilmont 77:869cf507173a 153 */
emilmont 77:869cf507173a 154
emilmont 77:869cf507173a 155 /** @defgroup ADCEx_External_trigger_edge_Injected
emilmont 77:869cf507173a 156 * @{
emilmont 77:869cf507173a 157 */
emilmont 77:869cf507173a 158 #define ADC_EXTERNALTRIGINJECCONVEDGE_NONE ((uint32_t)0x00000000)
emilmont 77:869cf507173a 159 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISING ((uint32_t)ADC_CR2_JEXTEN_0)
emilmont 77:869cf507173a 160 #define ADC_EXTERNALTRIGINJECCONVEDGE_FALLING ((uint32_t)ADC_CR2_JEXTEN_1)
emilmont 77:869cf507173a 161 #define ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_JEXTEN)
emilmont 77:869cf507173a 162
emilmont 77:869cf507173a 163 #define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_NONE) || \
emilmont 77:869cf507173a 164 ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISING) || \
emilmont 77:869cf507173a 165 ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_FALLING) || \
emilmont 77:869cf507173a 166 ((EDGE) == ADC_EXTERNALTRIGINJECCONVEDGE_RISINGFALLING))
emilmont 77:869cf507173a 167 /**
emilmont 77:869cf507173a 168 * @}
emilmont 77:869cf507173a 169 */
emilmont 77:869cf507173a 170
emilmont 77:869cf507173a 171 /** @defgroup ADCEx_External_trigger_Source_Injected
emilmont 77:869cf507173a 172 * @{
emilmont 77:869cf507173a 173 */
emilmont 77:869cf507173a 174 #define ADC_EXTERNALTRIGINJECCONV_T1_CC4 ((uint32_t)0x00000000)
emilmont 77:869cf507173a 175 #define ADC_EXTERNALTRIGINJECCONV_T1_TRGO ((uint32_t)ADC_CR2_JEXTSEL_0)
emilmont 77:869cf507173a 176 #define ADC_EXTERNALTRIGINJECCONV_T2_CC1 ((uint32_t)ADC_CR2_JEXTSEL_1)
emilmont 77:869cf507173a 177 #define ADC_EXTERNALTRIGINJECCONV_T2_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
emilmont 77:869cf507173a 178 #define ADC_EXTERNALTRIGINJECCONV_T3_CC2 ((uint32_t)ADC_CR2_JEXTSEL_2)
emilmont 77:869cf507173a 179 #define ADC_EXTERNALTRIGINJECCONV_T3_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
emilmont 77:869cf507173a 180 #define ADC_EXTERNALTRIGINJECCONV_T4_CC1 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
emilmont 77:869cf507173a 181 #define ADC_EXTERNALTRIGINJECCONV_T4_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
emilmont 77:869cf507173a 182 #define ADC_EXTERNALTRIGINJECCONV_T4_CC3 ((uint32_t)ADC_CR2_JEXTSEL_3)
emilmont 77:869cf507173a 183 #define ADC_EXTERNALTRIGINJECCONV_T4_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_0))
emilmont 77:869cf507173a 184 #define ADC_EXTERNALTRIGINJECCONV_T5_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1))
emilmont 77:869cf507173a 185 #define ADC_EXTERNALTRIGINJECCONV_T5_TRGO ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
emilmont 77:869cf507173a 186 #define ADC_EXTERNALTRIGINJECCONV_T8_CC2 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2))
emilmont 77:869cf507173a 187 #define ADC_EXTERNALTRIGINJECCONV_T8_CC3 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_0))
emilmont 77:869cf507173a 188 #define ADC_EXTERNALTRIGINJECCONV_T8_CC4 ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1))
emilmont 77:869cf507173a 189 #define ADC_EXTERNALTRIGINJECCONV_EXT_IT15 ((uint32_t)ADC_CR2_JEXTSEL)
emilmont 77:869cf507173a 190
emilmont 77:869cf507173a 191 #define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_CC4) || \
emilmont 77:869cf507173a 192 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T1_TRGO) || \
emilmont 77:869cf507173a 193 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1) || \
emilmont 77:869cf507173a 194 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO) || \
emilmont 77:869cf507173a 195 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC2) || \
emilmont 77:869cf507173a 196 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4) || \
emilmont 77:869cf507173a 197 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1) || \
emilmont 77:869cf507173a 198 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2) || \
emilmont 77:869cf507173a 199 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3) || \
emilmont 77:869cf507173a 200 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO) || \
emilmont 77:869cf507173a 201 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_CC4) || \
emilmont 77:869cf507173a 202 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T5_TRGO) || \
emilmont 77:869cf507173a 203 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC2) || \
emilmont 77:869cf507173a 204 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC3) || \
emilmont 77:869cf507173a 205 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_T8_CC4) || \
emilmont 77:869cf507173a 206 ((INJTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15))
emilmont 77:869cf507173a 207 /**
emilmont 77:869cf507173a 208 * @}
emilmont 77:869cf507173a 209 */
emilmont 77:869cf507173a 210
emilmont 77:869cf507173a 211 /** @defgroup ADCEx_injected_channel_selection
emilmont 77:869cf507173a 212 * @{
emilmont 77:869cf507173a 213 */
emilmont 77:869cf507173a 214 #define ADC_INJECTED_RANK_1 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 215 #define ADC_INJECTED_RANK_2 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 216 #define ADC_INJECTED_RANK_3 ((uint32_t)0x00000003)
emilmont 77:869cf507173a 217 #define ADC_INJECTED_RANK_4 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 218
emilmont 77:869cf507173a 219 /**
emilmont 77:869cf507173a 220 * @}
emilmont 77:869cf507173a 221 */
emilmont 77:869cf507173a 222
emilmont 77:869cf507173a 223 /** @defgroup ADCEx_injected_length
emilmont 77:869cf507173a 224 * @{
emilmont 77:869cf507173a 225 */
emilmont 77:869cf507173a 226 #define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
emilmont 77:869cf507173a 227 /**
emilmont 77:869cf507173a 228 * @}
emilmont 77:869cf507173a 229 */
emilmont 77:869cf507173a 230
emilmont 77:869cf507173a 231 /** @defgroup ADCEx_injected_rank
emilmont 77:869cf507173a 232 * @{
emilmont 77:869cf507173a 233 */
emilmont 77:869cf507173a 234 #define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= ((uint32_t)1)) && ((RANK) <= ((uint32_t)4)))
emilmont 77:869cf507173a 235 /**
emilmont 77:869cf507173a 236 * @}
emilmont 77:869cf507173a 237 */
emilmont 77:869cf507173a 238
emilmont 77:869cf507173a 239 /**
emilmont 77:869cf507173a 240 * @}
emilmont 77:869cf507173a 241 */
emilmont 77:869cf507173a 242
emilmont 77:869cf507173a 243 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 244
emilmont 77:869cf507173a 245 /**
emilmont 77:869cf507173a 246 * @brief Set the selected injected Channel rank.
emilmont 77:869cf507173a 247 * @param _CHANNELNB_: Channel number.
emilmont 77:869cf507173a 248 * @param _RANKNB_: Rank number.
emilmont 77:869cf507173a 249 * @param _JSQR_JL_: Sequence length.
emilmont 77:869cf507173a 250 * @retval None
emilmont 77:869cf507173a 251 */
emilmont 77:869cf507173a 252 #define __HAL_ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) \
emilmont 77:869cf507173a 253 ((_CHANNELNB_) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
emilmont 77:869cf507173a 254
emilmont 77:869cf507173a 255 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 256
emilmont 77:869cf507173a 257 /* I/O operation functions ******************************************************/
emilmont 77:869cf507173a 258 HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
emilmont 77:869cf507173a 259 HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
emilmont 77:869cf507173a 260 HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
emilmont 77:869cf507173a 261 HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
emilmont 77:869cf507173a 262 HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
emilmont 77:869cf507173a 263 uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
emilmont 77:869cf507173a 264 HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
emilmont 77:869cf507173a 265 HAL_StatusTypeDef HAL_ADCEx_MultiModeStop_DMA(ADC_HandleTypeDef* hadc);
emilmont 77:869cf507173a 266 uint32_t HAL_ADCEx_MultiModeGetValue(ADC_HandleTypeDef* hadc);
emilmont 77:869cf507173a 267 __weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
emilmont 77:869cf507173a 268
emilmont 77:869cf507173a 269 /* Peripheral Control functions *************************************************/
emilmont 77:869cf507173a 270 HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
emilmont 77:869cf507173a 271 HAL_StatusTypeDef HAL_ADCEx_MultiModeConfigChannel(ADC_HandleTypeDef* hadc, ADC_MultiModeTypeDef* multimode);
emilmont 77:869cf507173a 272
emilmont 77:869cf507173a 273 /**
emilmont 77:869cf507173a 274 * @}
emilmont 77:869cf507173a 275 */
emilmont 77:869cf507173a 276
emilmont 77:869cf507173a 277 /**
emilmont 77:869cf507173a 278 * @}
emilmont 77:869cf507173a 279 */
emilmont 77:869cf507173a 280
emilmont 77:869cf507173a 281 #ifdef __cplusplus
emilmont 77:869cf507173a 282 }
emilmont 77:869cf507173a 283 #endif
emilmont 77:869cf507173a 284
emilmont 77:869cf507173a 285 #endif /*__STM32F4xx_ADC_EX_H */
emilmont 77:869cf507173a 286
emilmont 77:869cf507173a 287
emilmont 77:869cf507173a 288 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/