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TARGET_RZ_A1H/ssif_iodefine.h@92:4fc01daae5a5, 2014-11-27 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Nov 27 13:33:22 2014 +0000
- Revision:
- 92:4fc01daae5a5
Release 92 of the mbed libray
Main changes:
- nRF51822: fixed pin assignment issues
- ST targets moving to the STM32Cube driver
- LPC1439: fixed serial interrupt issue
- first Cortex-A platform supported in mbed (RZ_A1H)
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 92:4fc01daae5a5 | 1 | /******************************************************************************* |
bogdanm | 92:4fc01daae5a5 | 2 | * DISCLAIMER |
bogdanm | 92:4fc01daae5a5 | 3 | * This software is supplied by Renesas Electronics Corporation and is only |
bogdanm | 92:4fc01daae5a5 | 4 | * intended for use with Renesas products. No other uses are authorized. This |
bogdanm | 92:4fc01daae5a5 | 5 | * software is owned by Renesas Electronics Corporation and is protected under |
bogdanm | 92:4fc01daae5a5 | 6 | * all applicable laws, including copyright laws. |
bogdanm | 92:4fc01daae5a5 | 7 | * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING |
bogdanm | 92:4fc01daae5a5 | 8 | * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT |
bogdanm | 92:4fc01daae5a5 | 9 | * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE |
bogdanm | 92:4fc01daae5a5 | 10 | * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. |
bogdanm | 92:4fc01daae5a5 | 11 | * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS |
bogdanm | 92:4fc01daae5a5 | 12 | * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE |
bogdanm | 92:4fc01daae5a5 | 13 | * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR |
bogdanm | 92:4fc01daae5a5 | 14 | * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE |
bogdanm | 92:4fc01daae5a5 | 15 | * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. |
bogdanm | 92:4fc01daae5a5 | 16 | * Renesas reserves the right, without notice, to make changes to this software |
bogdanm | 92:4fc01daae5a5 | 17 | * and to discontinue the availability of this software. By using this software, |
bogdanm | 92:4fc01daae5a5 | 18 | * you agree to the additional terms and conditions found by accessing the |
bogdanm | 92:4fc01daae5a5 | 19 | * following link: |
bogdanm | 92:4fc01daae5a5 | 20 | * http://www.renesas.com/disclaimer* |
bogdanm | 92:4fc01daae5a5 | 21 | * Copyright (C) 2013-2014 Renesas Electronics Corporation. All rights reserved. |
bogdanm | 92:4fc01daae5a5 | 22 | *******************************************************************************/ |
bogdanm | 92:4fc01daae5a5 | 23 | /******************************************************************************* |
bogdanm | 92:4fc01daae5a5 | 24 | * File Name : ssif_iodefine.h |
bogdanm | 92:4fc01daae5a5 | 25 | * $Rev: $ |
bogdanm | 92:4fc01daae5a5 | 26 | * $Date:: $ |
bogdanm | 92:4fc01daae5a5 | 27 | * Description : Definition of I/O Register (V1.00a) |
bogdanm | 92:4fc01daae5a5 | 28 | ******************************************************************************/ |
bogdanm | 92:4fc01daae5a5 | 29 | #ifndef SSIF_IODEFINE_H |
bogdanm | 92:4fc01daae5a5 | 30 | #define SSIF_IODEFINE_H |
bogdanm | 92:4fc01daae5a5 | 31 | /* ->SEC M1.10.1 : Not magic number */ |
bogdanm | 92:4fc01daae5a5 | 32 | |
bogdanm | 92:4fc01daae5a5 | 33 | struct st_ssif |
bogdanm | 92:4fc01daae5a5 | 34 | { /* SSIF */ |
bogdanm | 92:4fc01daae5a5 | 35 | volatile uint32_t SSICR; /* SSICR */ |
bogdanm | 92:4fc01daae5a5 | 36 | volatile uint32_t SSISR; /* SSISR */ |
bogdanm | 92:4fc01daae5a5 | 37 | volatile uint8_t dummy1[8]; /* */ |
bogdanm | 92:4fc01daae5a5 | 38 | volatile uint32_t SSIFCR; /* SSIFCR */ |
bogdanm | 92:4fc01daae5a5 | 39 | volatile uint32_t SSIFSR; /* SSIFSR */ |
bogdanm | 92:4fc01daae5a5 | 40 | volatile uint32_t SSIFTDR; /* SSIFTDR */ |
bogdanm | 92:4fc01daae5a5 | 41 | volatile uint32_t SSIFRDR; /* SSIFRDR */ |
bogdanm | 92:4fc01daae5a5 | 42 | volatile uint32_t SSITDMR; /* SSITDMR */ |
bogdanm | 92:4fc01daae5a5 | 43 | volatile uint32_t SSIFCCR; /* SSIFCCR */ |
bogdanm | 92:4fc01daae5a5 | 44 | volatile uint32_t SSIFCMR; /* SSIFCMR */ |
bogdanm | 92:4fc01daae5a5 | 45 | volatile uint32_t SSIFCSR; /* SSIFCSR */ |
bogdanm | 92:4fc01daae5a5 | 46 | }; |
bogdanm | 92:4fc01daae5a5 | 47 | |
bogdanm | 92:4fc01daae5a5 | 48 | |
bogdanm | 92:4fc01daae5a5 | 49 | #define SSIF0 (*(struct st_ssif *)0xE820B000uL) /* SSIF0 */ |
bogdanm | 92:4fc01daae5a5 | 50 | #define SSIF1 (*(struct st_ssif *)0xE820B800uL) /* SSIF1 */ |
bogdanm | 92:4fc01daae5a5 | 51 | #define SSIF2 (*(struct st_ssif *)0xE820C000uL) /* SSIF2 */ |
bogdanm | 92:4fc01daae5a5 | 52 | #define SSIF3 (*(struct st_ssif *)0xE820C800uL) /* SSIF3 */ |
bogdanm | 92:4fc01daae5a5 | 53 | #define SSIF4 (*(struct st_ssif *)0xE820D000uL) /* SSIF4 */ |
bogdanm | 92:4fc01daae5a5 | 54 | #define SSIF5 (*(struct st_ssif *)0xE820D800uL) /* SSIF5 */ |
bogdanm | 92:4fc01daae5a5 | 55 | |
bogdanm | 92:4fc01daae5a5 | 56 | |
bogdanm | 92:4fc01daae5a5 | 57 | /* Start of channnel array defines of SSIF */ |
bogdanm | 92:4fc01daae5a5 | 58 | |
bogdanm | 92:4fc01daae5a5 | 59 | /* Channnel array defines of SSIF */ |
bogdanm | 92:4fc01daae5a5 | 60 | /*(Sample) value = SSIF[ channel ]->SSICR; */ |
bogdanm | 92:4fc01daae5a5 | 61 | #define SSIF_COUNT 6 |
bogdanm | 92:4fc01daae5a5 | 62 | #define SSIF_ADDRESS_LIST \ |
bogdanm | 92:4fc01daae5a5 | 63 | { /* ->MISRA 11.3 */ /* ->SEC R2.7.1 */ \ |
bogdanm | 92:4fc01daae5a5 | 64 | &SSIF0, &SSIF1, &SSIF2, &SSIF3, &SSIF4, &SSIF5 \ |
bogdanm | 92:4fc01daae5a5 | 65 | } /* <-MISRA 11.3 */ /* <-SEC R2.7.1 */ /* { } is for MISRA 19.4 */ |
bogdanm | 92:4fc01daae5a5 | 66 | |
bogdanm | 92:4fc01daae5a5 | 67 | /* End of channnel array defines of SSIF */ |
bogdanm | 92:4fc01daae5a5 | 68 | |
bogdanm | 92:4fc01daae5a5 | 69 | |
bogdanm | 92:4fc01daae5a5 | 70 | #define SSICR_0 SSIF0.SSICR |
bogdanm | 92:4fc01daae5a5 | 71 | #define SSISR_0 SSIF0.SSISR |
bogdanm | 92:4fc01daae5a5 | 72 | #define SSIFCR_0 SSIF0.SSIFCR |
bogdanm | 92:4fc01daae5a5 | 73 | #define SSIFSR_0 SSIF0.SSIFSR |
bogdanm | 92:4fc01daae5a5 | 74 | #define SSIFTDR_0 SSIF0.SSIFTDR |
bogdanm | 92:4fc01daae5a5 | 75 | #define SSIFRDR_0 SSIF0.SSIFRDR |
bogdanm | 92:4fc01daae5a5 | 76 | #define SSITDMR_0 SSIF0.SSITDMR |
bogdanm | 92:4fc01daae5a5 | 77 | #define SSIFCCR_0 SSIF0.SSIFCCR |
bogdanm | 92:4fc01daae5a5 | 78 | #define SSIFCMR_0 SSIF0.SSIFCMR |
bogdanm | 92:4fc01daae5a5 | 79 | #define SSIFCSR_0 SSIF0.SSIFCSR |
bogdanm | 92:4fc01daae5a5 | 80 | #define SSICR_1 SSIF1.SSICR |
bogdanm | 92:4fc01daae5a5 | 81 | #define SSISR_1 SSIF1.SSISR |
bogdanm | 92:4fc01daae5a5 | 82 | #define SSIFCR_1 SSIF1.SSIFCR |
bogdanm | 92:4fc01daae5a5 | 83 | #define SSIFSR_1 SSIF1.SSIFSR |
bogdanm | 92:4fc01daae5a5 | 84 | #define SSIFTDR_1 SSIF1.SSIFTDR |
bogdanm | 92:4fc01daae5a5 | 85 | #define SSIFRDR_1 SSIF1.SSIFRDR |
bogdanm | 92:4fc01daae5a5 | 86 | #define SSITDMR_1 SSIF1.SSITDMR |
bogdanm | 92:4fc01daae5a5 | 87 | #define SSIFCCR_1 SSIF1.SSIFCCR |
bogdanm | 92:4fc01daae5a5 | 88 | #define SSIFCMR_1 SSIF1.SSIFCMR |
bogdanm | 92:4fc01daae5a5 | 89 | #define SSIFCSR_1 SSIF1.SSIFCSR |
bogdanm | 92:4fc01daae5a5 | 90 | #define SSICR_2 SSIF2.SSICR |
bogdanm | 92:4fc01daae5a5 | 91 | #define SSISR_2 SSIF2.SSISR |
bogdanm | 92:4fc01daae5a5 | 92 | #define SSIFCR_2 SSIF2.SSIFCR |
bogdanm | 92:4fc01daae5a5 | 93 | #define SSIFSR_2 SSIF2.SSIFSR |
bogdanm | 92:4fc01daae5a5 | 94 | #define SSIFTDR_2 SSIF2.SSIFTDR |
bogdanm | 92:4fc01daae5a5 | 95 | #define SSIFRDR_2 SSIF2.SSIFRDR |
bogdanm | 92:4fc01daae5a5 | 96 | #define SSITDMR_2 SSIF2.SSITDMR |
bogdanm | 92:4fc01daae5a5 | 97 | #define SSIFCCR_2 SSIF2.SSIFCCR |
bogdanm | 92:4fc01daae5a5 | 98 | #define SSIFCMR_2 SSIF2.SSIFCMR |
bogdanm | 92:4fc01daae5a5 | 99 | #define SSIFCSR_2 SSIF2.SSIFCSR |
bogdanm | 92:4fc01daae5a5 | 100 | #define SSICR_3 SSIF3.SSICR |
bogdanm | 92:4fc01daae5a5 | 101 | #define SSISR_3 SSIF3.SSISR |
bogdanm | 92:4fc01daae5a5 | 102 | #define SSIFCR_3 SSIF3.SSIFCR |
bogdanm | 92:4fc01daae5a5 | 103 | #define SSIFSR_3 SSIF3.SSIFSR |
bogdanm | 92:4fc01daae5a5 | 104 | #define SSIFTDR_3 SSIF3.SSIFTDR |
bogdanm | 92:4fc01daae5a5 | 105 | #define SSIFRDR_3 SSIF3.SSIFRDR |
bogdanm | 92:4fc01daae5a5 | 106 | #define SSITDMR_3 SSIF3.SSITDMR |
bogdanm | 92:4fc01daae5a5 | 107 | #define SSIFCCR_3 SSIF3.SSIFCCR |
bogdanm | 92:4fc01daae5a5 | 108 | #define SSIFCMR_3 SSIF3.SSIFCMR |
bogdanm | 92:4fc01daae5a5 | 109 | #define SSIFCSR_3 SSIF3.SSIFCSR |
bogdanm | 92:4fc01daae5a5 | 110 | #define SSICR_4 SSIF4.SSICR |
bogdanm | 92:4fc01daae5a5 | 111 | #define SSISR_4 SSIF4.SSISR |
bogdanm | 92:4fc01daae5a5 | 112 | #define SSIFCR_4 SSIF4.SSIFCR |
bogdanm | 92:4fc01daae5a5 | 113 | #define SSIFSR_4 SSIF4.SSIFSR |
bogdanm | 92:4fc01daae5a5 | 114 | #define SSIFTDR_4 SSIF4.SSIFTDR |
bogdanm | 92:4fc01daae5a5 | 115 | #define SSIFRDR_4 SSIF4.SSIFRDR |
bogdanm | 92:4fc01daae5a5 | 116 | #define SSITDMR_4 SSIF4.SSITDMR |
bogdanm | 92:4fc01daae5a5 | 117 | #define SSIFCCR_4 SSIF4.SSIFCCR |
bogdanm | 92:4fc01daae5a5 | 118 | #define SSIFCMR_4 SSIF4.SSIFCMR |
bogdanm | 92:4fc01daae5a5 | 119 | #define SSIFCSR_4 SSIF4.SSIFCSR |
bogdanm | 92:4fc01daae5a5 | 120 | #define SSICR_5 SSIF5.SSICR |
bogdanm | 92:4fc01daae5a5 | 121 | #define SSISR_5 SSIF5.SSISR |
bogdanm | 92:4fc01daae5a5 | 122 | #define SSIFCR_5 SSIF5.SSIFCR |
bogdanm | 92:4fc01daae5a5 | 123 | #define SSIFSR_5 SSIF5.SSIFSR |
bogdanm | 92:4fc01daae5a5 | 124 | #define SSIFTDR_5 SSIF5.SSIFTDR |
bogdanm | 92:4fc01daae5a5 | 125 | #define SSIFRDR_5 SSIF5.SSIFRDR |
bogdanm | 92:4fc01daae5a5 | 126 | #define SSITDMR_5 SSIF5.SSITDMR |
bogdanm | 92:4fc01daae5a5 | 127 | #define SSIFCCR_5 SSIF5.SSIFCCR |
bogdanm | 92:4fc01daae5a5 | 128 | #define SSIFCMR_5 SSIF5.SSIFCMR |
bogdanm | 92:4fc01daae5a5 | 129 | #define SSIFCSR_5 SSIF5.SSIFCSR |
bogdanm | 92:4fc01daae5a5 | 130 | /* <-SEC M1.10.1 */ |
bogdanm | 92:4fc01daae5a5 | 131 | #endif |