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TARGET_NUCLEO_L053R8/stm32l0xx_hal_tim_ex.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Parent:
84:0b3ab51c8877
Child:
96:487b796308b0
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_tim_ex.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 18-June-2014
bogdanm 84:0b3ab51c8877 7 * @brief Header file of TIM HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
bogdanm 84:0b3ab51c8877 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_TIM_EX_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_TIM_EX_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
bogdanm 84:0b3ab51c8877 53 /** @addtogroup TIMEx
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 58
bogdanm 84:0b3ab51c8877 59 /**
bogdanm 84:0b3ab51c8877 60 * @brief TIM Master configuration Structure definition
bogdanm 84:0b3ab51c8877 61 */
bogdanm 84:0b3ab51c8877 62 typedef struct {
bogdanm 84:0b3ab51c8877 63 uint32_t MasterOutputTrigger; /*!< Trigger output (TRGO) selection
bogdanm 84:0b3ab51c8877 64 This parameter can be a value of @ref TIMEx_Master_Mode_Selection */
bogdanm 84:0b3ab51c8877 65 uint32_t MasterSlaveMode; /*!< Master/slave mode selection
bogdanm 92:4fc01daae5a5 66 This parameter can be a value of @ref TIM_Master_Slave_Mode */
bogdanm 84:0b3ab51c8877 67 }TIM_MasterConfigTypeDef;
bogdanm 84:0b3ab51c8877 68
bogdanm 84:0b3ab51c8877 69
bogdanm 84:0b3ab51c8877 70 /* Exported constants --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 71 /** @defgroup TIMEx_Exported_Constants
bogdanm 84:0b3ab51c8877 72 * @{
bogdanm 84:0b3ab51c8877 73 */
bogdanm 84:0b3ab51c8877 74
bogdanm 84:0b3ab51c8877 75 /** @defgroup TIMEx_Master_Mode_Selection
bogdanm 84:0b3ab51c8877 76 * @{
bogdanm 84:0b3ab51c8877 77 */
bogdanm 84:0b3ab51c8877 78 #define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm 84:0b3ab51c8877 79 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm 84:0b3ab51c8877 80 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm 84:0b3ab51c8877 81 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 84:0b3ab51c8877 82 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm 84:0b3ab51c8877 83 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
bogdanm 84:0b3ab51c8877 84 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
bogdanm 84:0b3ab51c8877 85 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
bogdanm 84:0b3ab51c8877 86
bogdanm 84:0b3ab51c8877 87 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
bogdanm 84:0b3ab51c8877 88 ((SOURCE) == TIM_TRGO_ENABLE) || \
bogdanm 84:0b3ab51c8877 89 ((SOURCE) == TIM_TRGO_UPDATE) || \
bogdanm 84:0b3ab51c8877 90 ((SOURCE) == TIM_TRGO_OC1) || \
bogdanm 84:0b3ab51c8877 91 ((SOURCE) == TIM_TRGO_OC1REF) || \
bogdanm 84:0b3ab51c8877 92 ((SOURCE) == TIM_TRGO_OC2REF) || \
bogdanm 84:0b3ab51c8877 93 ((SOURCE) == TIM_TRGO_OC3REF) || \
bogdanm 84:0b3ab51c8877 94 ((SOURCE) == TIM_TRGO_OC4REF))
bogdanm 84:0b3ab51c8877 95
bogdanm 84:0b3ab51c8877 96 /**
bogdanm 84:0b3ab51c8877 97 * @}
bogdanm 84:0b3ab51c8877 98 */
bogdanm 84:0b3ab51c8877 99
bogdanm 92:4fc01daae5a5 100 /** @defgroup TIMEx_Remap
bogdanm 84:0b3ab51c8877 101 * @{
bogdanm 84:0b3ab51c8877 102 */
bogdanm 84:0b3ab51c8877 103
bogdanm 84:0b3ab51c8877 104 #define TIM2_ETR_GPIO ((uint32_t)0xFFF80000)
bogdanm 84:0b3ab51c8877 105 #define TIM2_ETR_HSI48 ((uint32_t)0xFFF80004)
bogdanm 84:0b3ab51c8877 106 #define TIM2_ETR_LSE ((uint32_t)0xFFF80005)
bogdanm 84:0b3ab51c8877 107 #define TIM2_ETR_COMP2_OUT ((uint32_t)0xFFF80006)
bogdanm 84:0b3ab51c8877 108 #define TIM2_ETR_COMP1_OUT ((uint32_t)0xFFF80007)
bogdanm 84:0b3ab51c8877 109 #define TIM2_TI4_GPIO1 ((uint32_t)0xFFE70000)
bogdanm 84:0b3ab51c8877 110 #define TIM2_TI4_COMP2 ((uint32_t)0xFFE70008)
bogdanm 84:0b3ab51c8877 111 #define TIM2_TI4_COMP1 ((uint32_t)0xFFE70010)
bogdanm 84:0b3ab51c8877 112 #define TIM2_TI4_GPIO2 ((uint32_t)0xFFE70018)
bogdanm 84:0b3ab51c8877 113 #define TIM21_ETR_GPIO ((uint32_t)0xFFF40000)
bogdanm 84:0b3ab51c8877 114 #define TIM21_ETR_COMP2_OUT ((uint32_t)0xFFF40001)
bogdanm 84:0b3ab51c8877 115 #define TIM21_ETR_COMP1_OUT ((uint32_t)0xFFF40002)
bogdanm 84:0b3ab51c8877 116 #define TIM21_ETR_LSE ((uint32_t)0xFFF40003)
bogdanm 84:0b3ab51c8877 117 #define TIM21_TI1_MCO ((uint32_t)0xFFE3001C)
bogdanm 84:0b3ab51c8877 118 #define TIM21_TI1_RTC_WKUT_IT ((uint32_t)0xFFE30004)
bogdanm 84:0b3ab51c8877 119 #define TIM21_TI1_HSE_RTC ((uint32_t)0xFFE30008)
bogdanm 84:0b3ab51c8877 120 #define TIM21_TI1_MSI ((uint32_t)0xFFE3000C)
bogdanm 84:0b3ab51c8877 121 #define TIM21_TI1_LSE ((uint32_t)0xFFE30010)
bogdanm 84:0b3ab51c8877 122 #define TIM21_TI1_LSI ((uint32_t)0xFFE30014)
bogdanm 84:0b3ab51c8877 123 #define TIM21_TI1_COMP1_OUT ((uint32_t)0xFFE30018)
bogdanm 84:0b3ab51c8877 124 #define TIM21_TI1_GPIO ((uint32_t)0xFFE30000)
bogdanm 84:0b3ab51c8877 125 #define TIM21_TI2_GPIO ((uint32_t)0xFFDF0000)
bogdanm 84:0b3ab51c8877 126 #define TIM21_TI2_COMP2_OUT ((uint32_t)0xFFDF0020)
bogdanm 84:0b3ab51c8877 127 #define TIM22_ETR_LSE ((uint32_t)0xFFFC0000)
bogdanm 84:0b3ab51c8877 128 #define TIM22_ETR_COMP2_OUT ((uint32_t)0xFFFC0001)
bogdanm 84:0b3ab51c8877 129 #define TIM22_ETR_COMP1_OUT ((uint32_t)0xFFFC0002)
bogdanm 84:0b3ab51c8877 130 #define TIM22_ETR_GPIO ((uint32_t)0xFFFC0003)
bogdanm 84:0b3ab51c8877 131 #define TIM22_TI1_GPIO1 ((uint32_t)0xFFF70000)
bogdanm 84:0b3ab51c8877 132 #define TIM22_TI1_COMP2_OUT ((uint32_t)0xFFF70004)
bogdanm 84:0b3ab51c8877 133 #define TIM22_TI1_COMP1_OUT ((uint32_t)0xFFF70008)
bogdanm 84:0b3ab51c8877 134 #define TIM22_TI1_GPIO2 ((uint32_t)0xFFF7000C)
bogdanm 84:0b3ab51c8877 135
bogdanm 84:0b3ab51c8877 136
bogdanm 84:0b3ab51c8877 137 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM2_ETR_GPIO )|| \
bogdanm 84:0b3ab51c8877 138 ((TIM_REMAP) == TIM2_ETR_HSI48 )|| \
bogdanm 84:0b3ab51c8877 139 ((TIM_REMAP) == TIM2_ETR_LSE )|| \
bogdanm 84:0b3ab51c8877 140 ((TIM_REMAP) == TIM2_ETR_COMP2_OUT )|| \
bogdanm 84:0b3ab51c8877 141 ((TIM_REMAP) == TIM2_ETR_COMP1_OUT )|| \
bogdanm 84:0b3ab51c8877 142 ((TIM_REMAP) == TIM2_TI4_GPIO1 )|| \
bogdanm 84:0b3ab51c8877 143 ((TIM_REMAP) == TIM2_TI4_COMP1 )|| \
bogdanm 84:0b3ab51c8877 144 ((TIM_REMAP) == TIM2_TI4_COMP2 )|| \
bogdanm 84:0b3ab51c8877 145 ((TIM_REMAP) == TIM2_TI4_GPIO2 )|| \
bogdanm 84:0b3ab51c8877 146 ((TIM_REMAP) == TIM21_ETR_GPIO )|| \
bogdanm 84:0b3ab51c8877 147 ((TIM_REMAP) == TIM21_ETR_COMP2_OUT )|| \
bogdanm 84:0b3ab51c8877 148 ((TIM_REMAP) == TIM21_ETR_COMP1_OUT )|| \
bogdanm 84:0b3ab51c8877 149 ((TIM_REMAP) == TIM21_ETR_LSE )|| \
bogdanm 84:0b3ab51c8877 150 ((TIM_REMAP) == TIM21_TI1_MCO )|| \
bogdanm 84:0b3ab51c8877 151 ((TIM_REMAP) == TIM21_TI1_RTC_WKUT_IT )|| \
bogdanm 84:0b3ab51c8877 152 ((TIM_REMAP) == TIM21_TI1_HSE_RTC )|| \
bogdanm 84:0b3ab51c8877 153 ((TIM_REMAP) == TIM21_TI1_MSI )|| \
bogdanm 84:0b3ab51c8877 154 ((TIM_REMAP) == TIM21_TI1_LSE )|| \
bogdanm 84:0b3ab51c8877 155 ((TIM_REMAP) == TIM21_TI1_LSI )|| \
bogdanm 84:0b3ab51c8877 156 ((TIM_REMAP) == TIM21_TI1_COMP1_OUT )|| \
bogdanm 84:0b3ab51c8877 157 ((TIM_REMAP) == TIM21_TI1_GPIO )|| \
bogdanm 84:0b3ab51c8877 158 ((TIM_REMAP) == TIM21_TI2_GPIO )|| \
bogdanm 84:0b3ab51c8877 159 ((TIM_REMAP) == TIM21_TI2_COMP2_OUT )|| \
bogdanm 84:0b3ab51c8877 160 ((TIM_REMAP) == TIM22_ETR_LSE )|| \
bogdanm 84:0b3ab51c8877 161 ((TIM_REMAP) == TIM22_ETR_COMP2_OUT )|| \
bogdanm 84:0b3ab51c8877 162 ((TIM_REMAP) == TIM22_ETR_COMP1_OUT )|| \
bogdanm 84:0b3ab51c8877 163 ((TIM_REMAP) == TIM22_ETR_GPIO )|| \
bogdanm 84:0b3ab51c8877 164 ((TIM_REMAP) == TIM22_TI1_GPIO1 )|| \
bogdanm 84:0b3ab51c8877 165 ((TIM_REMAP) == TIM22_TI1_COMP2_OUT )|| \
bogdanm 84:0b3ab51c8877 166 ((TIM_REMAP) == TIM22_TI1_COMP1_OUT )|| \
bogdanm 84:0b3ab51c8877 167 ((TIM_REMAP) == TIM22_TI1_GPIO2 ))
bogdanm 84:0b3ab51c8877 168
bogdanm 84:0b3ab51c8877 169
bogdanm 84:0b3ab51c8877 170 /**
bogdanm 84:0b3ab51c8877 171 * @}
bogdanm 84:0b3ab51c8877 172 */
bogdanm 84:0b3ab51c8877 173
bogdanm 84:0b3ab51c8877 174 /**
bogdanm 84:0b3ab51c8877 175 * @}
bogdanm 84:0b3ab51c8877 176 */
bogdanm 84:0b3ab51c8877 177
bogdanm 84:0b3ab51c8877 178 /* Exported macro ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 179 /* Exported functions --------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 180 /* Control functions ***********************************************************/
bogdanm 84:0b3ab51c8877 181 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
bogdanm 84:0b3ab51c8877 182 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
bogdanm 84:0b3ab51c8877 183 /**
bogdanm 84:0b3ab51c8877 184 * @}
bogdanm 84:0b3ab51c8877 185 */
bogdanm 84:0b3ab51c8877 186
bogdanm 84:0b3ab51c8877 187 /**
bogdanm 84:0b3ab51c8877 188 * @}
bogdanm 84:0b3ab51c8877 189 */
bogdanm 84:0b3ab51c8877 190
bogdanm 84:0b3ab51c8877 191 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 192 }
bogdanm 84:0b3ab51c8877 193 #endif
bogdanm 84:0b3ab51c8877 194
bogdanm 84:0b3ab51c8877 195 #endif /* __STM32L0xx_HAL_TIM_EX_H */
bogdanm 84:0b3ab51c8877 196
bogdanm 84:0b3ab51c8877 197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/