Ricardo Benitez / mbed

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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_iwdg.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:
bogdanm
Date:
Thu Nov 27 13:33:22 2014 +0000
Revision:
92:4fc01daae5a5
Child:
99:dbbf35b96557
Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_iwdg.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of IWDG HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_IWDG_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_IWDG_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup IWDG
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /**
bogdanm 92:4fc01daae5a5 60 * @brief IWDG HAL State Structure definition
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62 typedef enum
bogdanm 92:4fc01daae5a5 63 {
bogdanm 92:4fc01daae5a5 64 HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 65 HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
bogdanm 92:4fc01daae5a5 66 HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
bogdanm 92:4fc01daae5a5 67 HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
bogdanm 92:4fc01daae5a5 68 HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 }HAL_IWDG_StateTypeDef;
bogdanm 92:4fc01daae5a5 71
bogdanm 92:4fc01daae5a5 72 /**
bogdanm 92:4fc01daae5a5 73 * @brief IWDG Init structure definition
bogdanm 92:4fc01daae5a5 74 */
bogdanm 92:4fc01daae5a5 75 typedef struct
bogdanm 92:4fc01daae5a5 76 {
bogdanm 92:4fc01daae5a5 77 uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
bogdanm 92:4fc01daae5a5 78 This parameter can be a value of @ref IWDG_Prescaler */
bogdanm 92:4fc01daae5a5 79
bogdanm 92:4fc01daae5a5 80 uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
bogdanm 92:4fc01daae5a5 81 This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
bogdanm 92:4fc01daae5a5 82
bogdanm 92:4fc01daae5a5 83 }IWDG_InitTypeDef;
bogdanm 92:4fc01daae5a5 84
bogdanm 92:4fc01daae5a5 85 /**
bogdanm 92:4fc01daae5a5 86 * @brief IWDG handle Structure definition
bogdanm 92:4fc01daae5a5 87 */
bogdanm 92:4fc01daae5a5 88 typedef struct
bogdanm 92:4fc01daae5a5 89 {
bogdanm 92:4fc01daae5a5 90 IWDG_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 91
bogdanm 92:4fc01daae5a5 92 IWDG_InitTypeDef Init; /*!< IWDG required parameters */
bogdanm 92:4fc01daae5a5 93
bogdanm 92:4fc01daae5a5 94 HAL_LockTypeDef Lock; /*!< IWDG locking object */
bogdanm 92:4fc01daae5a5 95
bogdanm 92:4fc01daae5a5 96 __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
bogdanm 92:4fc01daae5a5 97
bogdanm 92:4fc01daae5a5 98 }IWDG_HandleTypeDef;
bogdanm 92:4fc01daae5a5 99
bogdanm 92:4fc01daae5a5 100 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 101 /** @defgroup IWDG_Exported_Constants
bogdanm 92:4fc01daae5a5 102 * @{
bogdanm 92:4fc01daae5a5 103 */
bogdanm 92:4fc01daae5a5 104
bogdanm 92:4fc01daae5a5 105 /** @defgroup IWDG_Registers_BitMask
bogdanm 92:4fc01daae5a5 106 * @{
bogdanm 92:4fc01daae5a5 107 */
bogdanm 92:4fc01daae5a5 108 /* --- KR Register ---*/
bogdanm 92:4fc01daae5a5 109 /* KR register bit mask */
bogdanm 92:4fc01daae5a5 110 #define KR_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG reload counter enable */
bogdanm 92:4fc01daae5a5 111 #define KR_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG peripheral enable */
bogdanm 92:4fc01daae5a5 112 #define KR_KEY_EWA ((uint32_t)0x5555) /*!< IWDG KR write Access enable */
bogdanm 92:4fc01daae5a5 113 #define KR_KEY_DWA ((uint32_t)0x0000) /*!< IWDG KR write Access disable */
bogdanm 92:4fc01daae5a5 114
bogdanm 92:4fc01daae5a5 115 #define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \
bogdanm 92:4fc01daae5a5 116 ((__KR__) == KR_KEY_ENABLE))|| \
bogdanm 92:4fc01daae5a5 117 ((__KR__) == KR_KEY_EWA)) || \
bogdanm 92:4fc01daae5a5 118 ((__KR__) == KR_KEY_DWA))
bogdanm 92:4fc01daae5a5 119 /**
bogdanm 92:4fc01daae5a5 120 * @}
bogdanm 92:4fc01daae5a5 121 */
bogdanm 92:4fc01daae5a5 122
bogdanm 92:4fc01daae5a5 123 /** @defgroup IWDG_Flag_definition
bogdanm 92:4fc01daae5a5 124 * @{
bogdanm 92:4fc01daae5a5 125 */
bogdanm 92:4fc01daae5a5 126 #define IWDG_FLAG_PVU ((uint32_t)0x0001) /*!< Watchdog counter prescaler value update flag */
bogdanm 92:4fc01daae5a5 127 #define IWDG_FLAG_RVU ((uint32_t)0x0002) /*!< Watchdog counter reload value update flag */
bogdanm 92:4fc01daae5a5 128
bogdanm 92:4fc01daae5a5 129 #define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || \
bogdanm 92:4fc01daae5a5 130 ((FLAG) == IWDG_FLAG_RVU))
bogdanm 92:4fc01daae5a5 131
bogdanm 92:4fc01daae5a5 132 /**
bogdanm 92:4fc01daae5a5 133 * @}
bogdanm 92:4fc01daae5a5 134 */
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136 /** @defgroup IWDG_Prescaler
bogdanm 92:4fc01daae5a5 137 * @{
bogdanm 92:4fc01daae5a5 138 */
bogdanm 92:4fc01daae5a5 139 #define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
bogdanm 92:4fc01daae5a5 140 #define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
bogdanm 92:4fc01daae5a5 141 #define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
bogdanm 92:4fc01daae5a5 142 #define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
bogdanm 92:4fc01daae5a5 143 #define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
bogdanm 92:4fc01daae5a5 144 #define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
bogdanm 92:4fc01daae5a5 145 #define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147
bogdanm 92:4fc01daae5a5 148 #define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_PRESCALER_4) || \
bogdanm 92:4fc01daae5a5 149 ((PRESCALER) == IWDG_PRESCALER_8) || \
bogdanm 92:4fc01daae5a5 150 ((PRESCALER) == IWDG_PRESCALER_16) || \
bogdanm 92:4fc01daae5a5 151 ((PRESCALER) == IWDG_PRESCALER_32) || \
bogdanm 92:4fc01daae5a5 152 ((PRESCALER) == IWDG_PRESCALER_64) || \
bogdanm 92:4fc01daae5a5 153 ((PRESCALER) == IWDG_PRESCALER_128)|| \
bogdanm 92:4fc01daae5a5 154 ((PRESCALER) == IWDG_PRESCALER_256))
bogdanm 92:4fc01daae5a5 155
bogdanm 92:4fc01daae5a5 156 /**
bogdanm 92:4fc01daae5a5 157 * @}
bogdanm 92:4fc01daae5a5 158 */
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 /** @defgroup IWDG_Reload_Value
bogdanm 92:4fc01daae5a5 161 * @{
bogdanm 92:4fc01daae5a5 162 */
bogdanm 92:4fc01daae5a5 163 #define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
bogdanm 92:4fc01daae5a5 164
bogdanm 92:4fc01daae5a5 165 /**
bogdanm 92:4fc01daae5a5 166 * @}
bogdanm 92:4fc01daae5a5 167 */
bogdanm 92:4fc01daae5a5 168
bogdanm 92:4fc01daae5a5 169 /**
bogdanm 92:4fc01daae5a5 170 * @}
bogdanm 92:4fc01daae5a5 171 */
bogdanm 92:4fc01daae5a5 172
bogdanm 92:4fc01daae5a5 173 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 174
bogdanm 92:4fc01daae5a5 175 /** @brief Reset IWDG handle state
bogdanm 92:4fc01daae5a5 176 * @param __HANDLE__: IWDG handle
bogdanm 92:4fc01daae5a5 177 * @retval None
bogdanm 92:4fc01daae5a5 178 */
bogdanm 92:4fc01daae5a5 179 #define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
bogdanm 92:4fc01daae5a5 180
bogdanm 92:4fc01daae5a5 181 /**
bogdanm 92:4fc01daae5a5 182 * @brief Enables the IWDG peripheral.
bogdanm 92:4fc01daae5a5 183 * @param __HANDLE__: IWDG handle
bogdanm 92:4fc01daae5a5 184 * @retval None
bogdanm 92:4fc01daae5a5 185 */
bogdanm 92:4fc01daae5a5 186 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE)
bogdanm 92:4fc01daae5a5 187
bogdanm 92:4fc01daae5a5 188 /**
bogdanm 92:4fc01daae5a5 189 * @brief Reloads IWDG counter with value defined in the reload register
bogdanm 92:4fc01daae5a5 190 * (write access to IWDG_PR and IWDG_RLR registers disabled).
bogdanm 92:4fc01daae5a5 191 * @param __HANDLE__: IWDG handle
bogdanm 92:4fc01daae5a5 192 * @retval None
bogdanm 92:4fc01daae5a5 193 */
bogdanm 92:4fc01daae5a5 194 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD)
bogdanm 92:4fc01daae5a5 195
bogdanm 92:4fc01daae5a5 196 /**
bogdanm 92:4fc01daae5a5 197 * @brief Enables write access to IWDG_PR and IWDG_RLR registers.
bogdanm 92:4fc01daae5a5 198 * @param __HANDLE__: IWDG handle
bogdanm 92:4fc01daae5a5 199 * @retval None
bogdanm 92:4fc01daae5a5 200 */
bogdanm 92:4fc01daae5a5 201 #define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA)
bogdanm 92:4fc01daae5a5 202
bogdanm 92:4fc01daae5a5 203 /**
bogdanm 92:4fc01daae5a5 204 * @brief Disables write access to IWDG_PR and IWDG_RLR registers.
bogdanm 92:4fc01daae5a5 205 * @param __HANDLE__: IWDG handle
bogdanm 92:4fc01daae5a5 206 * @retval None
bogdanm 92:4fc01daae5a5 207 */
bogdanm 92:4fc01daae5a5 208 #define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA)
bogdanm 92:4fc01daae5a5 209
bogdanm 92:4fc01daae5a5 210 /**
bogdanm 92:4fc01daae5a5 211 * @brief Gets the selected IWDG's flag status.
bogdanm 92:4fc01daae5a5 212 * @param __HANDLE__: IWDG handle
bogdanm 92:4fc01daae5a5 213 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 214 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 215 * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
bogdanm 92:4fc01daae5a5 216 * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
bogdanm 92:4fc01daae5a5 217 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 218 */
bogdanm 92:4fc01daae5a5 219 #define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 220
bogdanm 92:4fc01daae5a5 221 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 222
bogdanm 92:4fc01daae5a5 223 /* Initialization/de-initialization functions ********************************/
bogdanm 92:4fc01daae5a5 224 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
bogdanm 92:4fc01daae5a5 225 void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
bogdanm 92:4fc01daae5a5 226
bogdanm 92:4fc01daae5a5 227 /* I/O operation functions ****************************************************/
bogdanm 92:4fc01daae5a5 228 HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
bogdanm 92:4fc01daae5a5 229 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
bogdanm 92:4fc01daae5a5 230
bogdanm 92:4fc01daae5a5 231 /* Peripheral State functions ************************************************/
bogdanm 92:4fc01daae5a5 232 HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
bogdanm 92:4fc01daae5a5 233
bogdanm 92:4fc01daae5a5 234 /**
bogdanm 92:4fc01daae5a5 235 * @}
bogdanm 92:4fc01daae5a5 236 */
bogdanm 92:4fc01daae5a5 237
bogdanm 92:4fc01daae5a5 238 /**
bogdanm 92:4fc01daae5a5 239 * @}
bogdanm 92:4fc01daae5a5 240 */
bogdanm 92:4fc01daae5a5 241
bogdanm 92:4fc01daae5a5 242 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 243 }
bogdanm 92:4fc01daae5a5 244 #endif
bogdanm 92:4fc01daae5a5 245
bogdanm 92:4fc01daae5a5 246 #endif /* __STM32F4xx_HAL_IWDG_H */
bogdanm 92:4fc01daae5a5 247
bogdanm 92:4fc01daae5a5 248 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/