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TARGET_NRF51822/nrf51_bitfields.h@97:433970e64889, 2015-04-14 (annotated)

Committer:: Kojto
Date:: Tue Apr 14 10:58:58 2015 +0200
Revision:: 97:433970e64889
Parent:: 80:8e73be2a2ac1

Release 97 of the mbed library



Changes:

- NRF51 - Update Softdevice, fix us ticker

- MTS Dragonfly - bugfixes, IAR support

- MTS mdot - bootloader support

- RZ_A1 - nvic wrapper

- STM F3xx, F4xx - hal reorganization

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	97:433970e64889	1	/* Copyright (c) 2013, Nordic Semiconductor ASA
Kojto	97:433970e64889	2	* All rights reserved.
Kojto	97:433970e64889	3	*
Kojto	97:433970e64889	4	* Redistribution and use in source and binary forms, with or without
Kojto	97:433970e64889	5	* modification, are permitted provided that the following conditions are met:
Kojto	97:433970e64889	6	*
Kojto	97:433970e64889	7	* * Redistributions of source code must retain the above copyright notice, this
Kojto	97:433970e64889	8	* list of conditions and the following disclaimer.
Kojto	97:433970e64889	9	*
Kojto	97:433970e64889	10	* * Redistributions in binary form must reproduce the above copyright notice,
Kojto	97:433970e64889	11	* this list of conditions and the following disclaimer in the documentation
Kojto	97:433970e64889	12	* and/or other materials provided with the distribution.
emilmont	80:8e73be2a2ac1	13	*
Kojto	97:433970e64889	14	* * Neither the name of Nordic Semiconductor ASA nor the names of its
Kojto	97:433970e64889	15	* contributors may be used to endorse or promote products derived from
Kojto	97:433970e64889	16	* this software without specific prior written permission.
emilmont	80:8e73be2a2ac1	17	*
Kojto	97:433970e64889	18	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	97:433970e64889	19	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	97:433970e64889	20	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	97:433970e64889	21	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	97:433970e64889	22	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	97:433970e64889	23	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	97:433970e64889	24	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	97:433970e64889	25	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	97:433970e64889	26	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	97:433970e64889	27	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	80:8e73be2a2ac1	28	*
emilmont	80:8e73be2a2ac1	29	*/
emilmont	80:8e73be2a2ac1	30	#ifndef __NRF51_BITS_H
emilmont	80:8e73be2a2ac1	31	#define __NRF51_BITS_H
emilmont	80:8e73be2a2ac1	32
emilmont	80:8e73be2a2ac1	33	/lint ++flb "Enter library region /
emilmont	80:8e73be2a2ac1	34
Kojto	97:433970e64889	35	#include <core_cm0.h>
emilmont	80:8e73be2a2ac1	36
emilmont	80:8e73be2a2ac1	37	/* Peripheral: AAR */
emilmont	80:8e73be2a2ac1	38	/* Description: Accelerated Address Resolver. */
emilmont	80:8e73be2a2ac1	39
emilmont	80:8e73be2a2ac1	40	/* Register: AAR_INTENSET */
emilmont	80:8e73be2a2ac1	41	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	42
emilmont	80:8e73be2a2ac1	43	/* Bit 2 : Enable interrupt on NOTRESOLVED event. */
emilmont	80:8e73be2a2ac1	44	#define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
emilmont	80:8e73be2a2ac1	45	#define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
emilmont	80:8e73be2a2ac1	46	#define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	47	#define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	48	#define AAR_INTENSET_NOTRESOLVED_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	49
emilmont	80:8e73be2a2ac1	50	/* Bit 1 : Enable interrupt on RESOLVED event. */
emilmont	80:8e73be2a2ac1	51	#define AAR_INTENSET_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
emilmont	80:8e73be2a2ac1	52	#define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
emilmont	80:8e73be2a2ac1	53	#define AAR_INTENSET_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	54	#define AAR_INTENSET_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	55	#define AAR_INTENSET_RESOLVED_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	56
emilmont	80:8e73be2a2ac1	57	/* Bit 0 : Enable interrupt on END event. */
emilmont	80:8e73be2a2ac1	58	#define AAR_INTENSET_END_Pos (0UL) /!< Position of END field. /
emilmont	80:8e73be2a2ac1	59	#define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /!< Bit mask of END field. /
emilmont	80:8e73be2a2ac1	60	#define AAR_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	61	#define AAR_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	62	#define AAR_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	63
emilmont	80:8e73be2a2ac1	64	/* Register: AAR_INTENCLR */
emilmont	80:8e73be2a2ac1	65	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	66
emilmont	80:8e73be2a2ac1	67	/* Bit 2 : Disable interrupt on NOTRESOLVED event. */
emilmont	80:8e73be2a2ac1	68	#define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /!< Position of NOTRESOLVED field. /
emilmont	80:8e73be2a2ac1	69	#define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /!< Bit mask of NOTRESOLVED field. /
emilmont	80:8e73be2a2ac1	70	#define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	71	#define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	72	#define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	73
emilmont	80:8e73be2a2ac1	74	/* Bit 1 : Disable interrupt on RESOLVED event. */
emilmont	80:8e73be2a2ac1	75	#define AAR_INTENCLR_RESOLVED_Pos (1UL) /!< Position of RESOLVED field. /
emilmont	80:8e73be2a2ac1	76	#define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /!< Bit mask of RESOLVED field. /
emilmont	80:8e73be2a2ac1	77	#define AAR_INTENCLR_RESOLVED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	78	#define AAR_INTENCLR_RESOLVED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	79	#define AAR_INTENCLR_RESOLVED_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	80
emilmont	80:8e73be2a2ac1	81	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
emilmont	80:8e73be2a2ac1	82	#define AAR_INTENCLR_END_Pos (0UL) /!< Position of END field. /
emilmont	80:8e73be2a2ac1	83	#define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /!< Bit mask of END field. /
emilmont	80:8e73be2a2ac1	84	#define AAR_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	85	#define AAR_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	86	#define AAR_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	87
emilmont	80:8e73be2a2ac1	88	/* Register: AAR_STATUS */
emilmont	80:8e73be2a2ac1	89	/* Description: Resolution status. */
emilmont	80:8e73be2a2ac1	90
emilmont	80:8e73be2a2ac1	91	/* Bits 3..0 : The IRK used last time an address was resolved. */
emilmont	80:8e73be2a2ac1	92	#define AAR_STATUS_STATUS_Pos (0UL) /!< Position of STATUS field. /
emilmont	80:8e73be2a2ac1	93	#define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /!< Bit mask of STATUS field. /
emilmont	80:8e73be2a2ac1	94
emilmont	80:8e73be2a2ac1	95	/* Register: AAR_ENABLE */
emilmont	80:8e73be2a2ac1	96	/* Description: Enable AAR. */
emilmont	80:8e73be2a2ac1	97
emilmont	80:8e73be2a2ac1	98	/* Bits 1..0 : Enable AAR. */
emilmont	80:8e73be2a2ac1	99	#define AAR_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	100	#define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	101	#define AAR_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled AAR. /
emilmont	80:8e73be2a2ac1	102	#define AAR_ENABLE_ENABLE_Enabled (0x03UL) /!< Enable AAR. /
emilmont	80:8e73be2a2ac1	103
emilmont	80:8e73be2a2ac1	104	/* Register: AAR_NIRK */
emilmont	80:8e73be2a2ac1	105	/* Description: Number of Identity root Keys in the IRK data structure. */
emilmont	80:8e73be2a2ac1	106
emilmont	80:8e73be2a2ac1	107	/* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
emilmont	80:8e73be2a2ac1	108	#define AAR_NIRK_NIRK_Pos (0UL) /!< Position of NIRK field. /
emilmont	80:8e73be2a2ac1	109	#define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /!< Bit mask of NIRK field. /
emilmont	80:8e73be2a2ac1	110
emilmont	80:8e73be2a2ac1	111	/* Register: AAR_POWER */
emilmont	80:8e73be2a2ac1	112	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	113
emilmont	80:8e73be2a2ac1	114	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	115	#define AAR_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	116	#define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	117	#define AAR_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	118	#define AAR_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	119
emilmont	80:8e73be2a2ac1	120
emilmont	80:8e73be2a2ac1	121	/* Peripheral: ADC */
emilmont	80:8e73be2a2ac1	122	/* Description: Analog to digital converter. */
emilmont	80:8e73be2a2ac1	123
emilmont	80:8e73be2a2ac1	124	/* Register: ADC_INTENSET */
emilmont	80:8e73be2a2ac1	125	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	126
emilmont	80:8e73be2a2ac1	127	/* Bit 0 : Enable interrupt on END event. */
emilmont	80:8e73be2a2ac1	128	#define ADC_INTENSET_END_Pos (0UL) /!< Position of END field. /
emilmont	80:8e73be2a2ac1	129	#define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /!< Bit mask of END field. /
emilmont	80:8e73be2a2ac1	130	#define ADC_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	131	#define ADC_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	132	#define ADC_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	133
emilmont	80:8e73be2a2ac1	134	/* Register: ADC_INTENCLR */
emilmont	80:8e73be2a2ac1	135	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	136
emilmont	80:8e73be2a2ac1	137	/* Bit 0 : Disable interrupt on END event. */
emilmont	80:8e73be2a2ac1	138	#define ADC_INTENCLR_END_Pos (0UL) /!< Position of END field. /
emilmont	80:8e73be2a2ac1	139	#define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /!< Bit mask of END field. /
emilmont	80:8e73be2a2ac1	140	#define ADC_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	141	#define ADC_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	142	#define ADC_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	143
emilmont	80:8e73be2a2ac1	144	/* Register: ADC_BUSY */
emilmont	80:8e73be2a2ac1	145	/* Description: ADC busy register. */
emilmont	80:8e73be2a2ac1	146
emilmont	80:8e73be2a2ac1	147	/* Bit 0 : ADC busy register. */
emilmont	80:8e73be2a2ac1	148	#define ADC_BUSY_BUSY_Pos (0UL) /!< Position of BUSY field. /
emilmont	80:8e73be2a2ac1	149	#define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /!< Bit mask of BUSY field. /
emilmont	80:8e73be2a2ac1	150	#define ADC_BUSY_BUSY_Ready (0UL) /!< No ongoing ADC conversion is taking place. ADC is ready. /
emilmont	80:8e73be2a2ac1	151	#define ADC_BUSY_BUSY_Busy (1UL) /!< An ADC conversion is taking place. ADC is busy. /
emilmont	80:8e73be2a2ac1	152
emilmont	80:8e73be2a2ac1	153	/* Register: ADC_ENABLE */
emilmont	80:8e73be2a2ac1	154	/* Description: ADC enable. */
emilmont	80:8e73be2a2ac1	155
emilmont	80:8e73be2a2ac1	156	/* Bits 1..0 : ADC enable. */
emilmont	80:8e73be2a2ac1	157	#define ADC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	158	#define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	159	#define ADC_ENABLE_ENABLE_Disabled (0x00UL) /!< ADC is disabled. /
emilmont	80:8e73be2a2ac1	160	#define ADC_ENABLE_ENABLE_Enabled (0x01UL) /!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. /
emilmont	80:8e73be2a2ac1	161
emilmont	80:8e73be2a2ac1	162	/* Register: ADC_CONFIG */
emilmont	80:8e73be2a2ac1	163	/* Description: ADC configuration register. */
emilmont	80:8e73be2a2ac1	164
emilmont	80:8e73be2a2ac1	165	/* Bits 17..16 : ADC external reference pin selection. */
emilmont	80:8e73be2a2ac1	166	#define ADC_CONFIG_EXTREFSEL_Pos (16UL) /!< Position of EXTREFSEL field. /
emilmont	80:8e73be2a2ac1	167	#define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
emilmont	80:8e73be2a2ac1	168	#define ADC_CONFIG_EXTREFSEL_None (0UL) /!< Analog external reference inputs disabled. /
emilmont	80:8e73be2a2ac1	169	#define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /!< Use analog reference 0 as reference. /
emilmont	80:8e73be2a2ac1	170	#define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /!< Use analog reference 1 as reference. /
emilmont	80:8e73be2a2ac1	171
emilmont	80:8e73be2a2ac1	172	/* Bits 15..8 : ADC analog pin selection. */
emilmont	80:8e73be2a2ac1	173	#define ADC_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
emilmont	80:8e73be2a2ac1	174	#define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
emilmont	80:8e73be2a2ac1	175	#define ADC_CONFIG_PSEL_Disabled (0UL) /!< Analog input pins disabled. /
emilmont	80:8e73be2a2ac1	176	#define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /!< Use analog input 0 as analog input. /
emilmont	80:8e73be2a2ac1	177	#define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /!< Use analog input 1 as analog input. /
emilmont	80:8e73be2a2ac1	178	#define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /!< Use analog input 2 as analog input. /
emilmont	80:8e73be2a2ac1	179	#define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /!< Use analog input 3 as analog input. /
emilmont	80:8e73be2a2ac1	180	#define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /!< Use analog input 4 as analog input. /
emilmont	80:8e73be2a2ac1	181	#define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /!< Use analog input 5 as analog input. /
emilmont	80:8e73be2a2ac1	182	#define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /!< Use analog input 6 as analog input. /
emilmont	80:8e73be2a2ac1	183	#define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /!< Use analog input 7 as analog input. /
emilmont	80:8e73be2a2ac1	184
emilmont	80:8e73be2a2ac1	185	/* Bits 6..5 : ADC reference selection. */
emilmont	80:8e73be2a2ac1	186	#define ADC_CONFIG_REFSEL_Pos (5UL) /!< Position of REFSEL field. /
emilmont	80:8e73be2a2ac1	187	#define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /!< Bit mask of REFSEL field. /
emilmont	80:8e73be2a2ac1	188	#define ADC_CONFIG_REFSEL_VBG (0x00UL) /!< Use internal 1.2V bandgap voltage as reference for conversion. /
emilmont	80:8e73be2a2ac1	189	#define ADC_CONFIG_REFSEL_External (0x01UL) /!< Use external source configured by EXTREFSEL as reference for conversion. /
emilmont	80:8e73be2a2ac1	190	#define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. /
emilmont	80:8e73be2a2ac1	191	#define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. /
emilmont	80:8e73be2a2ac1	192
emilmont	80:8e73be2a2ac1	193	/* Bits 4..2 : ADC input selection. */
emilmont	80:8e73be2a2ac1	194	#define ADC_CONFIG_INPSEL_Pos (2UL) /!< Position of INPSEL field. /
emilmont	80:8e73be2a2ac1	195	#define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /!< Bit mask of INPSEL field. /
emilmont	80:8e73be2a2ac1	196	#define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /!< Analog input specified by PSEL with no prescaling used as input for the conversion. /
emilmont	80:8e73be2a2ac1	197	#define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. /
emilmont	80:8e73be2a2ac1	198	#define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. /
emilmont	80:8e73be2a2ac1	199	#define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /!< Supply voltage with 2/3 prescaling used as input for the conversion. /
emilmont	80:8e73be2a2ac1	200	#define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /!< Supply voltage with 1/3 prescaling used as input for the conversion. /
emilmont	80:8e73be2a2ac1	201
emilmont	80:8e73be2a2ac1	202	/* Bits 1..0 : ADC resolution. */
emilmont	80:8e73be2a2ac1	203	#define ADC_CONFIG_RES_Pos (0UL) /!< Position of RES field. /
emilmont	80:8e73be2a2ac1	204	#define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /!< Bit mask of RES field. /
emilmont	80:8e73be2a2ac1	205	#define ADC_CONFIG_RES_8bit (0x00UL) /!< 8bit ADC resolution. /
emilmont	80:8e73be2a2ac1	206	#define ADC_CONFIG_RES_9bit (0x01UL) /!< 9bit ADC resolution. /
emilmont	80:8e73be2a2ac1	207	#define ADC_CONFIG_RES_10bit (0x02UL) /!< 10bit ADC resolution. /
emilmont	80:8e73be2a2ac1	208
emilmont	80:8e73be2a2ac1	209	/* Register: ADC_RESULT */
emilmont	80:8e73be2a2ac1	210	/* Description: Result of ADC conversion. */
emilmont	80:8e73be2a2ac1	211
emilmont	80:8e73be2a2ac1	212	/* Bits 9..0 : Result of ADC conversion. */
emilmont	80:8e73be2a2ac1	213	#define ADC_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
emilmont	80:8e73be2a2ac1	214	#define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
emilmont	80:8e73be2a2ac1	215
emilmont	80:8e73be2a2ac1	216	/* Register: ADC_POWER */
emilmont	80:8e73be2a2ac1	217	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	218
emilmont	80:8e73be2a2ac1	219	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	220	#define ADC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	221	#define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	222	#define ADC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	223	#define ADC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	224
emilmont	80:8e73be2a2ac1	225
emilmont	80:8e73be2a2ac1	226	/* Peripheral: AMLI */
emilmont	80:8e73be2a2ac1	227	/* Description: AHB Multi-Layer Interface. */
emilmont	80:8e73be2a2ac1	228
emilmont	80:8e73be2a2ac1	229	/* Register: AMLI_RAMPRI_CPU0 */
emilmont	80:8e73be2a2ac1	230	/* Description: Configurable priority configuration register for CPU0. */
emilmont	80:8e73be2a2ac1	231
Kojto	97:433970e64889	232	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	233	#define AMLI_RAMPRI_CPU0_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	234	#define AMLI_RAMPRI_CPU0_RAM7_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	235	#define AMLI_RAMPRI_CPU0_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	236	#define AMLI_RAMPRI_CPU0_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	237	#define AMLI_RAMPRI_CPU0_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	238	#define AMLI_RAMPRI_CPU0_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	239	#define AMLI_RAMPRI_CPU0_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	240	#define AMLI_RAMPRI_CPU0_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	241	#define AMLI_RAMPRI_CPU0_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	242	#define AMLI_RAMPRI_CPU0_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	243
Kojto	97:433970e64889	244	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	245	#define AMLI_RAMPRI_CPU0_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	246	#define AMLI_RAMPRI_CPU0_RAM6_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	247	#define AMLI_RAMPRI_CPU0_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	248	#define AMLI_RAMPRI_CPU0_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	249	#define AMLI_RAMPRI_CPU0_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	250	#define AMLI_RAMPRI_CPU0_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	251	#define AMLI_RAMPRI_CPU0_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	252	#define AMLI_RAMPRI_CPU0_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	253	#define AMLI_RAMPRI_CPU0_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	254	#define AMLI_RAMPRI_CPU0_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	255
Kojto	97:433970e64889	256	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	257	#define AMLI_RAMPRI_CPU0_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	258	#define AMLI_RAMPRI_CPU0_RAM5_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	259	#define AMLI_RAMPRI_CPU0_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	260	#define AMLI_RAMPRI_CPU0_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	261	#define AMLI_RAMPRI_CPU0_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	262	#define AMLI_RAMPRI_CPU0_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	263	#define AMLI_RAMPRI_CPU0_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	264	#define AMLI_RAMPRI_CPU0_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	265	#define AMLI_RAMPRI_CPU0_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	266	#define AMLI_RAMPRI_CPU0_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	267
Kojto	97:433970e64889	268	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	269	#define AMLI_RAMPRI_CPU0_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	270	#define AMLI_RAMPRI_CPU0_RAM4_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	271	#define AMLI_RAMPRI_CPU0_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	272	#define AMLI_RAMPRI_CPU0_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	273	#define AMLI_RAMPRI_CPU0_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	274	#define AMLI_RAMPRI_CPU0_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	275	#define AMLI_RAMPRI_CPU0_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	276	#define AMLI_RAMPRI_CPU0_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	277	#define AMLI_RAMPRI_CPU0_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	278	#define AMLI_RAMPRI_CPU0_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	279
emilmont	80:8e73be2a2ac1	280	/* Bits 15..12 : Configuration field for RAM block 3. */
emilmont	80:8e73be2a2ac1	281	#define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /!< Position of RAM3 field. /
emilmont	80:8e73be2a2ac1	282	#define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	283	#define AMLI_RAMPRI_CPU0_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	284	#define AMLI_RAMPRI_CPU0_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	285	#define AMLI_RAMPRI_CPU0_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	286	#define AMLI_RAMPRI_CPU0_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	287	#define AMLI_RAMPRI_CPU0_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	288	#define AMLI_RAMPRI_CPU0_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	289	#define AMLI_RAMPRI_CPU0_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	290	#define AMLI_RAMPRI_CPU0_RAM3_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	291
emilmont	80:8e73be2a2ac1	292	/* Bits 11..8 : Configuration field for RAM block 2. */
emilmont	80:8e73be2a2ac1	293	#define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /!< Position of RAM2 field. /
emilmont	80:8e73be2a2ac1	294	#define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	295	#define AMLI_RAMPRI_CPU0_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	296	#define AMLI_RAMPRI_CPU0_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	297	#define AMLI_RAMPRI_CPU0_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	298	#define AMLI_RAMPRI_CPU0_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	299	#define AMLI_RAMPRI_CPU0_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	300	#define AMLI_RAMPRI_CPU0_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	301	#define AMLI_RAMPRI_CPU0_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	302	#define AMLI_RAMPRI_CPU0_RAM2_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	303
emilmont	80:8e73be2a2ac1	304	/* Bits 7..4 : Configuration field for RAM block 1. */
emilmont	80:8e73be2a2ac1	305	#define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /!< Position of RAM1 field. /
emilmont	80:8e73be2a2ac1	306	#define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	307	#define AMLI_RAMPRI_CPU0_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	308	#define AMLI_RAMPRI_CPU0_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	309	#define AMLI_RAMPRI_CPU0_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	310	#define AMLI_RAMPRI_CPU0_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	311	#define AMLI_RAMPRI_CPU0_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	312	#define AMLI_RAMPRI_CPU0_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	313	#define AMLI_RAMPRI_CPU0_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	314	#define AMLI_RAMPRI_CPU0_RAM1_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	315
emilmont	80:8e73be2a2ac1	316	/* Bits 3..0 : Configuration field for RAM block 0. */
emilmont	80:8e73be2a2ac1	317	#define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /!< Position of RAM0 field. /
emilmont	80:8e73be2a2ac1	318	#define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	319	#define AMLI_RAMPRI_CPU0_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	320	#define AMLI_RAMPRI_CPU0_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	321	#define AMLI_RAMPRI_CPU0_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	322	#define AMLI_RAMPRI_CPU0_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	323	#define AMLI_RAMPRI_CPU0_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	324	#define AMLI_RAMPRI_CPU0_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	325	#define AMLI_RAMPRI_CPU0_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	326	#define AMLI_RAMPRI_CPU0_RAM0_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	327
emilmont	80:8e73be2a2ac1	328	/* Register: AMLI_RAMPRI_SPIS1 */
emilmont	80:8e73be2a2ac1	329	/* Description: Configurable priority configuration register for SPIS1. */
emilmont	80:8e73be2a2ac1	330
Kojto	97:433970e64889	331	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	332	#define AMLI_RAMPRI_SPIS1_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	333	#define AMLI_RAMPRI_SPIS1_RAM7_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	334	#define AMLI_RAMPRI_SPIS1_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	335	#define AMLI_RAMPRI_SPIS1_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	336	#define AMLI_RAMPRI_SPIS1_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	337	#define AMLI_RAMPRI_SPIS1_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	338	#define AMLI_RAMPRI_SPIS1_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	339	#define AMLI_RAMPRI_SPIS1_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	340	#define AMLI_RAMPRI_SPIS1_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	341	#define AMLI_RAMPRI_SPIS1_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	342
Kojto	97:433970e64889	343	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	344	#define AMLI_RAMPRI_SPIS1_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	345	#define AMLI_RAMPRI_SPIS1_RAM6_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	346	#define AMLI_RAMPRI_SPIS1_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	347	#define AMLI_RAMPRI_SPIS1_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	348	#define AMLI_RAMPRI_SPIS1_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	349	#define AMLI_RAMPRI_SPIS1_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	350	#define AMLI_RAMPRI_SPIS1_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	351	#define AMLI_RAMPRI_SPIS1_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	352	#define AMLI_RAMPRI_SPIS1_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	353	#define AMLI_RAMPRI_SPIS1_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	354
Kojto	97:433970e64889	355	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	356	#define AMLI_RAMPRI_SPIS1_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	357	#define AMLI_RAMPRI_SPIS1_RAM5_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	358	#define AMLI_RAMPRI_SPIS1_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	359	#define AMLI_RAMPRI_SPIS1_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	360	#define AMLI_RAMPRI_SPIS1_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	361	#define AMLI_RAMPRI_SPIS1_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	362	#define AMLI_RAMPRI_SPIS1_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	363	#define AMLI_RAMPRI_SPIS1_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	364	#define AMLI_RAMPRI_SPIS1_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	365	#define AMLI_RAMPRI_SPIS1_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	366
Kojto	97:433970e64889	367	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	368	#define AMLI_RAMPRI_SPIS1_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	369	#define AMLI_RAMPRI_SPIS1_RAM4_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	370	#define AMLI_RAMPRI_SPIS1_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	371	#define AMLI_RAMPRI_SPIS1_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	372	#define AMLI_RAMPRI_SPIS1_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	373	#define AMLI_RAMPRI_SPIS1_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	374	#define AMLI_RAMPRI_SPIS1_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	375	#define AMLI_RAMPRI_SPIS1_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	376	#define AMLI_RAMPRI_SPIS1_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	377	#define AMLI_RAMPRI_SPIS1_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	378
emilmont	80:8e73be2a2ac1	379	/* Bits 15..12 : Configuration field for RAM block 3. */
emilmont	80:8e73be2a2ac1	380	#define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /!< Position of RAM3 field. /
emilmont	80:8e73be2a2ac1	381	#define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	382	#define AMLI_RAMPRI_SPIS1_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	383	#define AMLI_RAMPRI_SPIS1_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	384	#define AMLI_RAMPRI_SPIS1_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	385	#define AMLI_RAMPRI_SPIS1_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	386	#define AMLI_RAMPRI_SPIS1_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	387	#define AMLI_RAMPRI_SPIS1_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	388	#define AMLI_RAMPRI_SPIS1_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	389	#define AMLI_RAMPRI_SPIS1_RAM3_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	390
emilmont	80:8e73be2a2ac1	391	/* Bits 11..8 : Configuration field for RAM block 2. */
emilmont	80:8e73be2a2ac1	392	#define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /!< Position of RAM2 field. /
emilmont	80:8e73be2a2ac1	393	#define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	394	#define AMLI_RAMPRI_SPIS1_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	395	#define AMLI_RAMPRI_SPIS1_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	396	#define AMLI_RAMPRI_SPIS1_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	397	#define AMLI_RAMPRI_SPIS1_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	398	#define AMLI_RAMPRI_SPIS1_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	399	#define AMLI_RAMPRI_SPIS1_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	400	#define AMLI_RAMPRI_SPIS1_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	401	#define AMLI_RAMPRI_SPIS1_RAM2_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	402
emilmont	80:8e73be2a2ac1	403	/* Bits 7..4 : Configuration field for RAM block 1. */
emilmont	80:8e73be2a2ac1	404	#define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /!< Position of RAM1 field. /
emilmont	80:8e73be2a2ac1	405	#define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	406	#define AMLI_RAMPRI_SPIS1_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	407	#define AMLI_RAMPRI_SPIS1_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	408	#define AMLI_RAMPRI_SPIS1_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	409	#define AMLI_RAMPRI_SPIS1_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	410	#define AMLI_RAMPRI_SPIS1_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	411	#define AMLI_RAMPRI_SPIS1_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	412	#define AMLI_RAMPRI_SPIS1_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	413	#define AMLI_RAMPRI_SPIS1_RAM1_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	414
emilmont	80:8e73be2a2ac1	415	/* Bits 3..0 : Configuration field for RAM block 0. */
emilmont	80:8e73be2a2ac1	416	#define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /!< Position of RAM0 field. /
emilmont	80:8e73be2a2ac1	417	#define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	418	#define AMLI_RAMPRI_SPIS1_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	419	#define AMLI_RAMPRI_SPIS1_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	420	#define AMLI_RAMPRI_SPIS1_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	421	#define AMLI_RAMPRI_SPIS1_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	422	#define AMLI_RAMPRI_SPIS1_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	423	#define AMLI_RAMPRI_SPIS1_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	424	#define AMLI_RAMPRI_SPIS1_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	425	#define AMLI_RAMPRI_SPIS1_RAM0_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	426
emilmont	80:8e73be2a2ac1	427	/* Register: AMLI_RAMPRI_RADIO */
emilmont	80:8e73be2a2ac1	428	/* Description: Configurable priority configuration register for RADIO. */
emilmont	80:8e73be2a2ac1	429
Kojto	97:433970e64889	430	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	431	#define AMLI_RAMPRI_RADIO_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	432	#define AMLI_RAMPRI_RADIO_RAM7_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	433	#define AMLI_RAMPRI_RADIO_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	434	#define AMLI_RAMPRI_RADIO_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	435	#define AMLI_RAMPRI_RADIO_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	436	#define AMLI_RAMPRI_RADIO_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	437	#define AMLI_RAMPRI_RADIO_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	438	#define AMLI_RAMPRI_RADIO_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	439	#define AMLI_RAMPRI_RADIO_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	440	#define AMLI_RAMPRI_RADIO_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	441
Kojto	97:433970e64889	442	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	443	#define AMLI_RAMPRI_RADIO_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	444	#define AMLI_RAMPRI_RADIO_RAM6_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	445	#define AMLI_RAMPRI_RADIO_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	446	#define AMLI_RAMPRI_RADIO_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	447	#define AMLI_RAMPRI_RADIO_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	448	#define AMLI_RAMPRI_RADIO_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	449	#define AMLI_RAMPRI_RADIO_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	450	#define AMLI_RAMPRI_RADIO_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	451	#define AMLI_RAMPRI_RADIO_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	452	#define AMLI_RAMPRI_RADIO_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	453
Kojto	97:433970e64889	454	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	455	#define AMLI_RAMPRI_RADIO_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	456	#define AMLI_RAMPRI_RADIO_RAM5_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	457	#define AMLI_RAMPRI_RADIO_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	458	#define AMLI_RAMPRI_RADIO_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	459	#define AMLI_RAMPRI_RADIO_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	460	#define AMLI_RAMPRI_RADIO_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	461	#define AMLI_RAMPRI_RADIO_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	462	#define AMLI_RAMPRI_RADIO_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	463	#define AMLI_RAMPRI_RADIO_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	464	#define AMLI_RAMPRI_RADIO_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	465
Kojto	97:433970e64889	466	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	467	#define AMLI_RAMPRI_RADIO_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	468	#define AMLI_RAMPRI_RADIO_RAM4_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	469	#define AMLI_RAMPRI_RADIO_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	470	#define AMLI_RAMPRI_RADIO_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	471	#define AMLI_RAMPRI_RADIO_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	472	#define AMLI_RAMPRI_RADIO_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	473	#define AMLI_RAMPRI_RADIO_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	474	#define AMLI_RAMPRI_RADIO_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	475	#define AMLI_RAMPRI_RADIO_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	476	#define AMLI_RAMPRI_RADIO_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	477
emilmont	80:8e73be2a2ac1	478	/* Bits 15..12 : Configuration field for RAM block 3. */
emilmont	80:8e73be2a2ac1	479	#define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /!< Position of RAM3 field. /
emilmont	80:8e73be2a2ac1	480	#define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	481	#define AMLI_RAMPRI_RADIO_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	482	#define AMLI_RAMPRI_RADIO_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	483	#define AMLI_RAMPRI_RADIO_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	484	#define AMLI_RAMPRI_RADIO_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	485	#define AMLI_RAMPRI_RADIO_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	486	#define AMLI_RAMPRI_RADIO_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	487	#define AMLI_RAMPRI_RADIO_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	488	#define AMLI_RAMPRI_RADIO_RAM3_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	489
emilmont	80:8e73be2a2ac1	490	/* Bits 11..8 : Configuration field for RAM block 2. */
emilmont	80:8e73be2a2ac1	491	#define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /!< Position of RAM2 field. /
emilmont	80:8e73be2a2ac1	492	#define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	493	#define AMLI_RAMPRI_RADIO_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	494	#define AMLI_RAMPRI_RADIO_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	495	#define AMLI_RAMPRI_RADIO_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	496	#define AMLI_RAMPRI_RADIO_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	497	#define AMLI_RAMPRI_RADIO_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	498	#define AMLI_RAMPRI_RADIO_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	499	#define AMLI_RAMPRI_RADIO_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	500	#define AMLI_RAMPRI_RADIO_RAM2_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	501
emilmont	80:8e73be2a2ac1	502	/* Bits 7..4 : Configuration field for RAM block 1. */
emilmont	80:8e73be2a2ac1	503	#define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /!< Position of RAM1 field. /
emilmont	80:8e73be2a2ac1	504	#define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	505	#define AMLI_RAMPRI_RADIO_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	506	#define AMLI_RAMPRI_RADIO_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	507	#define AMLI_RAMPRI_RADIO_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	508	#define AMLI_RAMPRI_RADIO_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	509	#define AMLI_RAMPRI_RADIO_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	510	#define AMLI_RAMPRI_RADIO_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	511	#define AMLI_RAMPRI_RADIO_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	512	#define AMLI_RAMPRI_RADIO_RAM1_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	513
emilmont	80:8e73be2a2ac1	514	/* Bits 3..0 : Configuration field for RAM block 0. */
emilmont	80:8e73be2a2ac1	515	#define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /!< Position of RAM0 field. /
emilmont	80:8e73be2a2ac1	516	#define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	517	#define AMLI_RAMPRI_RADIO_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	518	#define AMLI_RAMPRI_RADIO_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	519	#define AMLI_RAMPRI_RADIO_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	520	#define AMLI_RAMPRI_RADIO_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	521	#define AMLI_RAMPRI_RADIO_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	522	#define AMLI_RAMPRI_RADIO_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	523	#define AMLI_RAMPRI_RADIO_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	524	#define AMLI_RAMPRI_RADIO_RAM0_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	525
emilmont	80:8e73be2a2ac1	526	/* Register: AMLI_RAMPRI_ECB */
emilmont	80:8e73be2a2ac1	527	/* Description: Configurable priority configuration register for ECB. */
emilmont	80:8e73be2a2ac1	528
Kojto	97:433970e64889	529	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	530	#define AMLI_RAMPRI_ECB_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	531	#define AMLI_RAMPRI_ECB_RAM7_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	532	#define AMLI_RAMPRI_ECB_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	533	#define AMLI_RAMPRI_ECB_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	534	#define AMLI_RAMPRI_ECB_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	535	#define AMLI_RAMPRI_ECB_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	536	#define AMLI_RAMPRI_ECB_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	537	#define AMLI_RAMPRI_ECB_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	538	#define AMLI_RAMPRI_ECB_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	539	#define AMLI_RAMPRI_ECB_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	540
Kojto	97:433970e64889	541	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	542	#define AMLI_RAMPRI_ECB_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	543	#define AMLI_RAMPRI_ECB_RAM6_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	544	#define AMLI_RAMPRI_ECB_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	545	#define AMLI_RAMPRI_ECB_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	546	#define AMLI_RAMPRI_ECB_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	547	#define AMLI_RAMPRI_ECB_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	548	#define AMLI_RAMPRI_ECB_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	549	#define AMLI_RAMPRI_ECB_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	550	#define AMLI_RAMPRI_ECB_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	551	#define AMLI_RAMPRI_ECB_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	552
Kojto	97:433970e64889	553	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	554	#define AMLI_RAMPRI_ECB_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	555	#define AMLI_RAMPRI_ECB_RAM5_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	556	#define AMLI_RAMPRI_ECB_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	557	#define AMLI_RAMPRI_ECB_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	558	#define AMLI_RAMPRI_ECB_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	559	#define AMLI_RAMPRI_ECB_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	560	#define AMLI_RAMPRI_ECB_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	561	#define AMLI_RAMPRI_ECB_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	562	#define AMLI_RAMPRI_ECB_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	563	#define AMLI_RAMPRI_ECB_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	564
Kojto	97:433970e64889	565	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	566	#define AMLI_RAMPRI_ECB_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	567	#define AMLI_RAMPRI_ECB_RAM4_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	568	#define AMLI_RAMPRI_ECB_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	569	#define AMLI_RAMPRI_ECB_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	570	#define AMLI_RAMPRI_ECB_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	571	#define AMLI_RAMPRI_ECB_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	572	#define AMLI_RAMPRI_ECB_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	573	#define AMLI_RAMPRI_ECB_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	574	#define AMLI_RAMPRI_ECB_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	575	#define AMLI_RAMPRI_ECB_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	576
emilmont	80:8e73be2a2ac1	577	/* Bits 15..12 : Configuration field for RAM block 3. */
emilmont	80:8e73be2a2ac1	578	#define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /!< Position of RAM3 field. /
emilmont	80:8e73be2a2ac1	579	#define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	580	#define AMLI_RAMPRI_ECB_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	581	#define AMLI_RAMPRI_ECB_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	582	#define AMLI_RAMPRI_ECB_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	583	#define AMLI_RAMPRI_ECB_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	584	#define AMLI_RAMPRI_ECB_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	585	#define AMLI_RAMPRI_ECB_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	586	#define AMLI_RAMPRI_ECB_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	587	#define AMLI_RAMPRI_ECB_RAM3_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	588
emilmont	80:8e73be2a2ac1	589	/* Bits 11..8 : Configuration field for RAM block 2. */
emilmont	80:8e73be2a2ac1	590	#define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /!< Position of RAM2 field. /
emilmont	80:8e73be2a2ac1	591	#define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	592	#define AMLI_RAMPRI_ECB_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	593	#define AMLI_RAMPRI_ECB_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	594	#define AMLI_RAMPRI_ECB_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	595	#define AMLI_RAMPRI_ECB_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	596	#define AMLI_RAMPRI_ECB_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	597	#define AMLI_RAMPRI_ECB_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	598	#define AMLI_RAMPRI_ECB_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	599	#define AMLI_RAMPRI_ECB_RAM2_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	600
emilmont	80:8e73be2a2ac1	601	/* Bits 7..4 : Configuration field for RAM block 1. */
emilmont	80:8e73be2a2ac1	602	#define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /!< Position of RAM1 field. /
emilmont	80:8e73be2a2ac1	603	#define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	604	#define AMLI_RAMPRI_ECB_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	605	#define AMLI_RAMPRI_ECB_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	606	#define AMLI_RAMPRI_ECB_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	607	#define AMLI_RAMPRI_ECB_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	608	#define AMLI_RAMPRI_ECB_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	609	#define AMLI_RAMPRI_ECB_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	610	#define AMLI_RAMPRI_ECB_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	611	#define AMLI_RAMPRI_ECB_RAM1_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	612
emilmont	80:8e73be2a2ac1	613	/* Bits 3..0 : Configuration field for RAM block 0. */
emilmont	80:8e73be2a2ac1	614	#define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /!< Position of RAM0 field. /
emilmont	80:8e73be2a2ac1	615	#define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	616	#define AMLI_RAMPRI_ECB_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	617	#define AMLI_RAMPRI_ECB_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	618	#define AMLI_RAMPRI_ECB_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	619	#define AMLI_RAMPRI_ECB_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	620	#define AMLI_RAMPRI_ECB_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	621	#define AMLI_RAMPRI_ECB_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	622	#define AMLI_RAMPRI_ECB_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	623	#define AMLI_RAMPRI_ECB_RAM0_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	624
emilmont	80:8e73be2a2ac1	625	/* Register: AMLI_RAMPRI_CCM */
emilmont	80:8e73be2a2ac1	626	/* Description: Configurable priority configuration register for CCM. */
emilmont	80:8e73be2a2ac1	627
Kojto	97:433970e64889	628	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	629	#define AMLI_RAMPRI_CCM_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	630	#define AMLI_RAMPRI_CCM_RAM7_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	631	#define AMLI_RAMPRI_CCM_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	632	#define AMLI_RAMPRI_CCM_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	633	#define AMLI_RAMPRI_CCM_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	634	#define AMLI_RAMPRI_CCM_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	635	#define AMLI_RAMPRI_CCM_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	636	#define AMLI_RAMPRI_CCM_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	637	#define AMLI_RAMPRI_CCM_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	638	#define AMLI_RAMPRI_CCM_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	639
Kojto	97:433970e64889	640	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	641	#define AMLI_RAMPRI_CCM_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	642	#define AMLI_RAMPRI_CCM_RAM6_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	643	#define AMLI_RAMPRI_CCM_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	644	#define AMLI_RAMPRI_CCM_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	645	#define AMLI_RAMPRI_CCM_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	646	#define AMLI_RAMPRI_CCM_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	647	#define AMLI_RAMPRI_CCM_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	648	#define AMLI_RAMPRI_CCM_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	649	#define AMLI_RAMPRI_CCM_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	650	#define AMLI_RAMPRI_CCM_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	651
Kojto	97:433970e64889	652	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	653	#define AMLI_RAMPRI_CCM_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	654	#define AMLI_RAMPRI_CCM_RAM5_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	655	#define AMLI_RAMPRI_CCM_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	656	#define AMLI_RAMPRI_CCM_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	657	#define AMLI_RAMPRI_CCM_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	658	#define AMLI_RAMPRI_CCM_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	659	#define AMLI_RAMPRI_CCM_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	660	#define AMLI_RAMPRI_CCM_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	661	#define AMLI_RAMPRI_CCM_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	662	#define AMLI_RAMPRI_CCM_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	663
Kojto	97:433970e64889	664	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	665	#define AMLI_RAMPRI_CCM_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	666	#define AMLI_RAMPRI_CCM_RAM4_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	667	#define AMLI_RAMPRI_CCM_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	668	#define AMLI_RAMPRI_CCM_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	669	#define AMLI_RAMPRI_CCM_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	670	#define AMLI_RAMPRI_CCM_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	671	#define AMLI_RAMPRI_CCM_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	672	#define AMLI_RAMPRI_CCM_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	673	#define AMLI_RAMPRI_CCM_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	674	#define AMLI_RAMPRI_CCM_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	675
emilmont	80:8e73be2a2ac1	676	/* Bits 15..12 : Configuration field for RAM block 3. */
emilmont	80:8e73be2a2ac1	677	#define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /!< Position of RAM3 field. /
emilmont	80:8e73be2a2ac1	678	#define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	679	#define AMLI_RAMPRI_CCM_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	680	#define AMLI_RAMPRI_CCM_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	681	#define AMLI_RAMPRI_CCM_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	682	#define AMLI_RAMPRI_CCM_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	683	#define AMLI_RAMPRI_CCM_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	684	#define AMLI_RAMPRI_CCM_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	685	#define AMLI_RAMPRI_CCM_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	686	#define AMLI_RAMPRI_CCM_RAM3_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	687
emilmont	80:8e73be2a2ac1	688	/* Bits 11..8 : Configuration field for RAM block 2. */
emilmont	80:8e73be2a2ac1	689	#define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /!< Position of RAM2 field. /
emilmont	80:8e73be2a2ac1	690	#define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	691	#define AMLI_RAMPRI_CCM_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	692	#define AMLI_RAMPRI_CCM_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	693	#define AMLI_RAMPRI_CCM_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	694	#define AMLI_RAMPRI_CCM_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	695	#define AMLI_RAMPRI_CCM_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	696	#define AMLI_RAMPRI_CCM_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	697	#define AMLI_RAMPRI_CCM_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	698	#define AMLI_RAMPRI_CCM_RAM2_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	699
emilmont	80:8e73be2a2ac1	700	/* Bits 7..4 : Configuration field for RAM block 1. */
emilmont	80:8e73be2a2ac1	701	#define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /!< Position of RAM1 field. /
emilmont	80:8e73be2a2ac1	702	#define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	703	#define AMLI_RAMPRI_CCM_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	704	#define AMLI_RAMPRI_CCM_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	705	#define AMLI_RAMPRI_CCM_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	706	#define AMLI_RAMPRI_CCM_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	707	#define AMLI_RAMPRI_CCM_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	708	#define AMLI_RAMPRI_CCM_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	709	#define AMLI_RAMPRI_CCM_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	710	#define AMLI_RAMPRI_CCM_RAM1_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	711
emilmont	80:8e73be2a2ac1	712	/* Bits 3..0 : Configuration field for RAM block 0. */
emilmont	80:8e73be2a2ac1	713	#define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /!< Position of RAM0 field. /
emilmont	80:8e73be2a2ac1	714	#define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	715	#define AMLI_RAMPRI_CCM_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	716	#define AMLI_RAMPRI_CCM_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	717	#define AMLI_RAMPRI_CCM_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	718	#define AMLI_RAMPRI_CCM_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	719	#define AMLI_RAMPRI_CCM_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	720	#define AMLI_RAMPRI_CCM_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	721	#define AMLI_RAMPRI_CCM_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	722	#define AMLI_RAMPRI_CCM_RAM0_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	723
emilmont	80:8e73be2a2ac1	724	/* Register: AMLI_RAMPRI_AAR */
emilmont	80:8e73be2a2ac1	725	/* Description: Configurable priority configuration register for AAR. */
emilmont	80:8e73be2a2ac1	726
Kojto	97:433970e64889	727	/* Bits 31..28 : Configuration field for RAM block 7. */
Kojto	97:433970e64889	728	#define AMLI_RAMPRI_AAR_RAM7_Pos (28UL) /!< Position of RAM7 field. /
Kojto	97:433970e64889	729	#define AMLI_RAMPRI_AAR_RAM7_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM7_Pos) /!< Bit mask of RAM7 field. /
Kojto	97:433970e64889	730	#define AMLI_RAMPRI_AAR_RAM7_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	731	#define AMLI_RAMPRI_AAR_RAM7_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	732	#define AMLI_RAMPRI_AAR_RAM7_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	733	#define AMLI_RAMPRI_AAR_RAM7_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	734	#define AMLI_RAMPRI_AAR_RAM7_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	735	#define AMLI_RAMPRI_AAR_RAM7_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	736	#define AMLI_RAMPRI_AAR_RAM7_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	737	#define AMLI_RAMPRI_AAR_RAM7_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	738
Kojto	97:433970e64889	739	/* Bits 27..24 : Configuration field for RAM block 6. */
Kojto	97:433970e64889	740	#define AMLI_RAMPRI_AAR_RAM6_Pos (24UL) /!< Position of RAM6 field. /
Kojto	97:433970e64889	741	#define AMLI_RAMPRI_AAR_RAM6_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM6_Pos) /!< Bit mask of RAM6 field. /
Kojto	97:433970e64889	742	#define AMLI_RAMPRI_AAR_RAM6_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	743	#define AMLI_RAMPRI_AAR_RAM6_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	744	#define AMLI_RAMPRI_AAR_RAM6_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	745	#define AMLI_RAMPRI_AAR_RAM6_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	746	#define AMLI_RAMPRI_AAR_RAM6_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	747	#define AMLI_RAMPRI_AAR_RAM6_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	748	#define AMLI_RAMPRI_AAR_RAM6_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	749	#define AMLI_RAMPRI_AAR_RAM6_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	750
Kojto	97:433970e64889	751	/* Bits 23..20 : Configuration field for RAM block 5. */
Kojto	97:433970e64889	752	#define AMLI_RAMPRI_AAR_RAM5_Pos (20UL) /!< Position of RAM5 field. /
Kojto	97:433970e64889	753	#define AMLI_RAMPRI_AAR_RAM5_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM5_Pos) /!< Bit mask of RAM5 field. /
Kojto	97:433970e64889	754	#define AMLI_RAMPRI_AAR_RAM5_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	755	#define AMLI_RAMPRI_AAR_RAM5_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	756	#define AMLI_RAMPRI_AAR_RAM5_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	757	#define AMLI_RAMPRI_AAR_RAM5_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	758	#define AMLI_RAMPRI_AAR_RAM5_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	759	#define AMLI_RAMPRI_AAR_RAM5_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	760	#define AMLI_RAMPRI_AAR_RAM5_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	761	#define AMLI_RAMPRI_AAR_RAM5_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	762
Kojto	97:433970e64889	763	/* Bits 19..16 : Configuration field for RAM block 4. */
Kojto	97:433970e64889	764	#define AMLI_RAMPRI_AAR_RAM4_Pos (16UL) /!< Position of RAM4 field. /
Kojto	97:433970e64889	765	#define AMLI_RAMPRI_AAR_RAM4_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM4_Pos) /!< Bit mask of RAM4 field. /
Kojto	97:433970e64889	766	#define AMLI_RAMPRI_AAR_RAM4_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	767	#define AMLI_RAMPRI_AAR_RAM4_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	768	#define AMLI_RAMPRI_AAR_RAM4_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	769	#define AMLI_RAMPRI_AAR_RAM4_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	770	#define AMLI_RAMPRI_AAR_RAM4_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	771	#define AMLI_RAMPRI_AAR_RAM4_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	772	#define AMLI_RAMPRI_AAR_RAM4_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	773	#define AMLI_RAMPRI_AAR_RAM4_Pri14 (0xEUL) /!< Priority 14. /
Kojto	97:433970e64889	774
emilmont	80:8e73be2a2ac1	775	/* Bits 15..12 : Configuration field for RAM block 3. */
emilmont	80:8e73be2a2ac1	776	#define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /!< Position of RAM3 field. /
emilmont	80:8e73be2a2ac1	777	#define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /!< Bit mask of RAM3 field. /
Kojto	97:433970e64889	778	#define AMLI_RAMPRI_AAR_RAM3_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	779	#define AMLI_RAMPRI_AAR_RAM3_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	780	#define AMLI_RAMPRI_AAR_RAM3_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	781	#define AMLI_RAMPRI_AAR_RAM3_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	782	#define AMLI_RAMPRI_AAR_RAM3_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	783	#define AMLI_RAMPRI_AAR_RAM3_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	784	#define AMLI_RAMPRI_AAR_RAM3_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	785	#define AMLI_RAMPRI_AAR_RAM3_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	786
emilmont	80:8e73be2a2ac1	787	/* Bits 11..8 : Configuration field for RAM block 2. */
emilmont	80:8e73be2a2ac1	788	#define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /!< Position of RAM2 field. /
emilmont	80:8e73be2a2ac1	789	#define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /!< Bit mask of RAM2 field. /
Kojto	97:433970e64889	790	#define AMLI_RAMPRI_AAR_RAM2_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	791	#define AMLI_RAMPRI_AAR_RAM2_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	792	#define AMLI_RAMPRI_AAR_RAM2_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	793	#define AMLI_RAMPRI_AAR_RAM2_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	794	#define AMLI_RAMPRI_AAR_RAM2_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	795	#define AMLI_RAMPRI_AAR_RAM2_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	796	#define AMLI_RAMPRI_AAR_RAM2_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	797	#define AMLI_RAMPRI_AAR_RAM2_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	798
emilmont	80:8e73be2a2ac1	799	/* Bits 7..4 : Configuration field for RAM block 1. */
emilmont	80:8e73be2a2ac1	800	#define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /!< Position of RAM1 field. /
emilmont	80:8e73be2a2ac1	801	#define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /!< Bit mask of RAM1 field. /
Kojto	97:433970e64889	802	#define AMLI_RAMPRI_AAR_RAM1_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	803	#define AMLI_RAMPRI_AAR_RAM1_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	804	#define AMLI_RAMPRI_AAR_RAM1_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	805	#define AMLI_RAMPRI_AAR_RAM1_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	806	#define AMLI_RAMPRI_AAR_RAM1_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	807	#define AMLI_RAMPRI_AAR_RAM1_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	808	#define AMLI_RAMPRI_AAR_RAM1_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	809	#define AMLI_RAMPRI_AAR_RAM1_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	810
emilmont	80:8e73be2a2ac1	811	/* Bits 3..0 : Configuration field for RAM block 0. */
emilmont	80:8e73be2a2ac1	812	#define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /!< Position of RAM0 field. /
emilmont	80:8e73be2a2ac1	813	#define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /!< Bit mask of RAM0 field. /
Kojto	97:433970e64889	814	#define AMLI_RAMPRI_AAR_RAM0_Pri0 (0x0UL) /!< Priority 0. /
Kojto	97:433970e64889	815	#define AMLI_RAMPRI_AAR_RAM0_Pri2 (0x2UL) /!< Priority 2. /
Kojto	97:433970e64889	816	#define AMLI_RAMPRI_AAR_RAM0_Pri4 (0x4UL) /!< Priority 4. /
Kojto	97:433970e64889	817	#define AMLI_RAMPRI_AAR_RAM0_Pri6 (0x6UL) /!< Priority 6. /
Kojto	97:433970e64889	818	#define AMLI_RAMPRI_AAR_RAM0_Pri8 (0x8UL) /!< Priority 8. /
Kojto	97:433970e64889	819	#define AMLI_RAMPRI_AAR_RAM0_Pri10 (0xAUL) /!< Priority 10. /
Kojto	97:433970e64889	820	#define AMLI_RAMPRI_AAR_RAM0_Pri12 (0xCUL) /!< Priority 12. /
Kojto	97:433970e64889	821	#define AMLI_RAMPRI_AAR_RAM0_Pri14 (0xEUL) /!< Priority 14. /
emilmont	80:8e73be2a2ac1	822
emilmont	80:8e73be2a2ac1	823	/* Peripheral: CCM */
emilmont	80:8e73be2a2ac1	824	/* Description: AES CCM Mode Encryption. */
emilmont	80:8e73be2a2ac1	825
emilmont	80:8e73be2a2ac1	826	/* Register: CCM_SHORTS */
Kojto	97:433970e64889	827	/* Description: Shortcuts for the CCM. */
Kojto	97:433970e64889	828
Kojto	97:433970e64889	829	/* Bit 0 : Shortcut between ENDKSGEN event and CRYPT task. */
emilmont	80:8e73be2a2ac1	830	#define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /!< Position of ENDKSGEN_CRYPT field. /
emilmont	80:8e73be2a2ac1	831	#define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /!< Bit mask of ENDKSGEN_CRYPT field. /
emilmont	80:8e73be2a2ac1	832	#define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	833	#define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	834
emilmont	80:8e73be2a2ac1	835	/* Register: CCM_INTENSET */
emilmont	80:8e73be2a2ac1	836	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	837
emilmont	80:8e73be2a2ac1	838	/* Bit 2 : Enable interrupt on ERROR event. */
emilmont	80:8e73be2a2ac1	839	#define CCM_INTENSET_ERROR_Pos (2UL) /!< Position of ERROR field. /
emilmont	80:8e73be2a2ac1	840	#define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
emilmont	80:8e73be2a2ac1	841	#define CCM_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	842	#define CCM_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	843	#define CCM_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	844
emilmont	80:8e73be2a2ac1	845	/* Bit 1 : Enable interrupt on ENDCRYPT event. */
emilmont	80:8e73be2a2ac1	846	#define CCM_INTENSET_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
emilmont	80:8e73be2a2ac1	847	#define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
emilmont	80:8e73be2a2ac1	848	#define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	849	#define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	850	#define CCM_INTENSET_ENDCRYPT_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	851
emilmont	80:8e73be2a2ac1	852	/* Bit 0 : Enable interrupt on ENDKSGEN event. */
emilmont	80:8e73be2a2ac1	853	#define CCM_INTENSET_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
emilmont	80:8e73be2a2ac1	854	#define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
emilmont	80:8e73be2a2ac1	855	#define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	856	#define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	857	#define CCM_INTENSET_ENDKSGEN_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	858
emilmont	80:8e73be2a2ac1	859	/* Register: CCM_INTENCLR */
emilmont	80:8e73be2a2ac1	860	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	861
emilmont	80:8e73be2a2ac1	862	/* Bit 2 : Disable interrupt on ERROR event. */
emilmont	80:8e73be2a2ac1	863	#define CCM_INTENCLR_ERROR_Pos (2UL) /!< Position of ERROR field. /
emilmont	80:8e73be2a2ac1	864	#define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
emilmont	80:8e73be2a2ac1	865	#define CCM_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	866	#define CCM_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	867	#define CCM_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	868
emilmont	80:8e73be2a2ac1	869	/* Bit 1 : Disable interrupt on ENDCRYPT event. */
emilmont	80:8e73be2a2ac1	870	#define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /!< Position of ENDCRYPT field. /
emilmont	80:8e73be2a2ac1	871	#define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /!< Bit mask of ENDCRYPT field. /
emilmont	80:8e73be2a2ac1	872	#define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	873	#define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	874	#define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	875
emilmont	80:8e73be2a2ac1	876	/* Bit 0 : Disable interrupt on ENDKSGEN event. */
emilmont	80:8e73be2a2ac1	877	#define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /!< Position of ENDKSGEN field. /
emilmont	80:8e73be2a2ac1	878	#define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /!< Bit mask of ENDKSGEN field. /
emilmont	80:8e73be2a2ac1	879	#define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	880	#define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	881	#define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	882
emilmont	80:8e73be2a2ac1	883	/* Register: CCM_MICSTATUS */
emilmont	80:8e73be2a2ac1	884	/* Description: CCM RX MIC check result. */
emilmont	80:8e73be2a2ac1	885
emilmont	80:8e73be2a2ac1	886	/* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
emilmont	80:8e73be2a2ac1	887	#define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /!< Position of MICSTATUS field. /
emilmont	80:8e73be2a2ac1	888	#define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /!< Bit mask of MICSTATUS field. /
emilmont	80:8e73be2a2ac1	889	#define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /!< MIC check failed. /
emilmont	80:8e73be2a2ac1	890	#define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /!< MIC check passed. /
emilmont	80:8e73be2a2ac1	891
emilmont	80:8e73be2a2ac1	892	/* Register: CCM_ENABLE */
emilmont	80:8e73be2a2ac1	893	/* Description: CCM enable. */
emilmont	80:8e73be2a2ac1	894
emilmont	80:8e73be2a2ac1	895	/* Bits 1..0 : CCM enable. */
emilmont	80:8e73be2a2ac1	896	#define CCM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	897	#define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	898	#define CCM_ENABLE_ENABLE_Disabled (0x00UL) /!< CCM is disabled. /
emilmont	80:8e73be2a2ac1	899	#define CCM_ENABLE_ENABLE_Enabled (0x02UL) /!< CCM is enabled. /
emilmont	80:8e73be2a2ac1	900
emilmont	80:8e73be2a2ac1	901	/* Register: CCM_MODE */
emilmont	80:8e73be2a2ac1	902	/* Description: Operation mode. */
emilmont	80:8e73be2a2ac1	903
emilmont	80:8e73be2a2ac1	904	/* Bit 0 : CCM mode operation. */
emilmont	80:8e73be2a2ac1	905	#define CCM_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
emilmont	80:8e73be2a2ac1	906	#define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /!< Bit mask of MODE field. /
emilmont	80:8e73be2a2ac1	907	#define CCM_MODE_MODE_Encryption (0UL) /!< CCM mode TX /
emilmont	80:8e73be2a2ac1	908	#define CCM_MODE_MODE_Decryption (1UL) /!< CCM mode TX /
emilmont	80:8e73be2a2ac1	909
emilmont	80:8e73be2a2ac1	910	/* Register: CCM_POWER */
emilmont	80:8e73be2a2ac1	911	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	912
emilmont	80:8e73be2a2ac1	913	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	914	#define CCM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	915	#define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	916	#define CCM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	917	#define CCM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	918
emilmont	80:8e73be2a2ac1	919
emilmont	80:8e73be2a2ac1	920	/* Peripheral: CLOCK */
emilmont	80:8e73be2a2ac1	921	/* Description: Clock control. */
emilmont	80:8e73be2a2ac1	922
emilmont	80:8e73be2a2ac1	923	/* Register: CLOCK_INTENSET */
emilmont	80:8e73be2a2ac1	924	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	925
emilmont	80:8e73be2a2ac1	926	/* Bit 4 : Enable interrupt on CTTO event. */
emilmont	80:8e73be2a2ac1	927	#define CLOCK_INTENSET_CTTO_Pos (4UL) /!< Position of CTTO field. /
emilmont	80:8e73be2a2ac1	928	#define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /!< Bit mask of CTTO field. /
emilmont	80:8e73be2a2ac1	929	#define CLOCK_INTENSET_CTTO_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	930	#define CLOCK_INTENSET_CTTO_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	931	#define CLOCK_INTENSET_CTTO_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	932
emilmont	80:8e73be2a2ac1	933	/* Bit 3 : Enable interrupt on DONE event. */
emilmont	80:8e73be2a2ac1	934	#define CLOCK_INTENSET_DONE_Pos (3UL) /!< Position of DONE field. /
emilmont	80:8e73be2a2ac1	935	#define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /!< Bit mask of DONE field. /
emilmont	80:8e73be2a2ac1	936	#define CLOCK_INTENSET_DONE_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	937	#define CLOCK_INTENSET_DONE_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	938	#define CLOCK_INTENSET_DONE_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	939
emilmont	80:8e73be2a2ac1	940	/* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
emilmont	80:8e73be2a2ac1	941	#define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
emilmont	80:8e73be2a2ac1	942	#define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
emilmont	80:8e73be2a2ac1	943	#define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	944	#define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	945	#define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	946
emilmont	80:8e73be2a2ac1	947	/* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
emilmont	80:8e73be2a2ac1	948	#define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
emilmont	80:8e73be2a2ac1	949	#define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
emilmont	80:8e73be2a2ac1	950	#define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	951	#define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	952	#define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	953
emilmont	80:8e73be2a2ac1	954	/* Register: CLOCK_INTENCLR */
emilmont	80:8e73be2a2ac1	955	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	956
emilmont	80:8e73be2a2ac1	957	/* Bit 4 : Disable interrupt on CTTO event. */
emilmont	80:8e73be2a2ac1	958	#define CLOCK_INTENCLR_CTTO_Pos (4UL) /!< Position of CTTO field. /
emilmont	80:8e73be2a2ac1	959	#define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /!< Bit mask of CTTO field. /
emilmont	80:8e73be2a2ac1	960	#define CLOCK_INTENCLR_CTTO_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	961	#define CLOCK_INTENCLR_CTTO_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	962	#define CLOCK_INTENCLR_CTTO_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	963
emilmont	80:8e73be2a2ac1	964	/* Bit 3 : Disable interrupt on DONE event. */
emilmont	80:8e73be2a2ac1	965	#define CLOCK_INTENCLR_DONE_Pos (3UL) /!< Position of DONE field. /
emilmont	80:8e73be2a2ac1	966	#define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /!< Bit mask of DONE field. /
emilmont	80:8e73be2a2ac1	967	#define CLOCK_INTENCLR_DONE_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	968	#define CLOCK_INTENCLR_DONE_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	969	#define CLOCK_INTENCLR_DONE_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	970
emilmont	80:8e73be2a2ac1	971	/* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
emilmont	80:8e73be2a2ac1	972	#define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /!< Position of LFCLKSTARTED field. /
emilmont	80:8e73be2a2ac1	973	#define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /!< Bit mask of LFCLKSTARTED field. /
emilmont	80:8e73be2a2ac1	974	#define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	975	#define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	976	#define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	977
emilmont	80:8e73be2a2ac1	978	/* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
emilmont	80:8e73be2a2ac1	979	#define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /!< Position of HFCLKSTARTED field. /
emilmont	80:8e73be2a2ac1	980	#define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /!< Bit mask of HFCLKSTARTED field. /
emilmont	80:8e73be2a2ac1	981	#define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	982	#define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	983	#define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	984
Kojto	97:433970e64889	985	/* Register: CLOCK_HFCLKRUN */
Kojto	97:433970e64889	986	/* Description: Task HFCLKSTART trigger status. */
Kojto	97:433970e64889	987
Kojto	97:433970e64889	988	/* Bit 0 : Task HFCLKSTART trigger status. */
Kojto	97:433970e64889	989	#define CLOCK_HFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	97:433970e64889	990	#define CLOCK_HFCLKRUN_STATUS_Msk (0x1UL << CLOCK_HFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	97:433970e64889	991	#define CLOCK_HFCLKRUN_STATUS_NotTriggered (0UL) /!< Task HFCLKSTART has not been triggered. /
Kojto	97:433970e64889	992	#define CLOCK_HFCLKRUN_STATUS_Triggered (1UL) /!< Task HFCLKSTART has been triggered. /
Kojto	97:433970e64889	993
emilmont	80:8e73be2a2ac1	994	/* Register: CLOCK_HFCLKSTAT */
emilmont	80:8e73be2a2ac1	995	/* Description: High frequency clock status. */
emilmont	80:8e73be2a2ac1	996
emilmont	80:8e73be2a2ac1	997	/* Bit 16 : State for the HFCLK. */
emilmont	80:8e73be2a2ac1	998	#define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
emilmont	80:8e73be2a2ac1	999	#define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
emilmont	80:8e73be2a2ac1	1000	#define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /!< HFCLK clock not running. /
emilmont	80:8e73be2a2ac1	1001	#define CLOCK_HFCLKSTAT_STATE_Running (1UL) /!< HFCLK clock running. /
emilmont	80:8e73be2a2ac1	1002
emilmont	80:8e73be2a2ac1	1003	/* Bit 0 : Active clock source for the HF clock. */
emilmont	80:8e73be2a2ac1	1004	#define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
emilmont	80:8e73be2a2ac1	1005	#define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
emilmont	80:8e73be2a2ac1	1006	#define CLOCK_HFCLKSTAT_SRC_RC (0UL) /!< Internal 16MHz RC oscillator running and generating the HFCLK clock. /
emilmont	80:8e73be2a2ac1	1007	#define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. /
emilmont	80:8e73be2a2ac1	1008
Kojto	97:433970e64889	1009	/* Register: CLOCK_LFCLKRUN */
Kojto	97:433970e64889	1010	/* Description: Task LFCLKSTART triggered status. */
Kojto	97:433970e64889	1011
Kojto	97:433970e64889	1012	/* Bit 0 : Task LFCLKSTART triggered status. */
Kojto	97:433970e64889	1013	#define CLOCK_LFCLKRUN_STATUS_Pos (0UL) /!< Position of STATUS field. /
Kojto	97:433970e64889	1014	#define CLOCK_LFCLKRUN_STATUS_Msk (0x1UL << CLOCK_LFCLKRUN_STATUS_Pos) /!< Bit mask of STATUS field. /
Kojto	97:433970e64889	1015	#define CLOCK_LFCLKRUN_STATUS_NotTriggered (0UL) /!< Task LFCLKSTART has not been triggered. /
Kojto	97:433970e64889	1016	#define CLOCK_LFCLKRUN_STATUS_Triggered (1UL) /!< Task LFCLKSTART has been triggered. /
Kojto	97:433970e64889	1017
emilmont	80:8e73be2a2ac1	1018	/* Register: CLOCK_LFCLKSTAT */
emilmont	80:8e73be2a2ac1	1019	/* Description: Low frequency clock status. */
emilmont	80:8e73be2a2ac1	1020
emilmont	80:8e73be2a2ac1	1021	/* Bit 16 : State for the LF clock. */
emilmont	80:8e73be2a2ac1	1022	#define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /!< Position of STATE field. /
emilmont	80:8e73be2a2ac1	1023	#define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /!< Bit mask of STATE field. /
emilmont	80:8e73be2a2ac1	1024	#define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /!< LFCLK clock not running. /
emilmont	80:8e73be2a2ac1	1025	#define CLOCK_LFCLKSTAT_STATE_Running (1UL) /!< LFCLK clock running. /
emilmont	80:8e73be2a2ac1	1026
emilmont	80:8e73be2a2ac1	1027	/* Bits 1..0 : Active clock source for the LF clock. */
emilmont	80:8e73be2a2ac1	1028	#define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /!< Position of SRC field. /
emilmont	80:8e73be2a2ac1	1029	#define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /!< Bit mask of SRC field. /
emilmont	80:8e73be2a2ac1	1030	#define CLOCK_LFCLKSTAT_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. /
emilmont	80:8e73be2a2ac1	1031	#define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /!< External 32KiHz crystal oscillator running and generating the LFCLK clock. /
emilmont	80:8e73be2a2ac1	1032	#define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. /
emilmont	80:8e73be2a2ac1	1033
Kojto	97:433970e64889	1034	/* Register: CLOCK_LFCLKSRCCOPY */
Kojto	97:433970e64889	1035	/* Description: Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto	97:433970e64889	1036
Kojto	97:433970e64889	1037	/* Bits 1..0 : Clock source for the LFCLK clock, set when task LKCLKSTART is triggered. */
Kojto	97:433970e64889	1038	#define CLOCK_LFCLKSRCCOPY_SRC_Pos (0UL) /!< Position of SRC field. /
Kojto	97:433970e64889	1039	#define CLOCK_LFCLKSRCCOPY_SRC_Msk (0x3UL << CLOCK_LFCLKSRCCOPY_SRC_Pos) /!< Bit mask of SRC field. /
Kojto	97:433970e64889	1040	#define CLOCK_LFCLKSRCCOPY_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
Kojto	97:433970e64889	1041	#define CLOCK_LFCLKSRCCOPY_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
Kojto	97:433970e64889	1042	#define CLOCK_LFCLKSRCCOPY_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
Kojto	97:433970e64889	1043
emilmont	80:8e73be2a2ac1	1044	/* Register: CLOCK_LFCLKSRC */
emilmont	80:8e73be2a2ac1	1045	/* Description: Clock source for the LFCLK clock. */
emilmont	80:8e73be2a2ac1	1046
emilmont	80:8e73be2a2ac1	1047	/* Bits 1..0 : Clock source. */
emilmont	80:8e73be2a2ac1	1048	#define CLOCK_LFCLKSRC_SRC_Pos (0UL) /!< Position of SRC field. /
emilmont	80:8e73be2a2ac1	1049	#define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /!< Bit mask of SRC field. /
emilmont	80:8e73be2a2ac1	1050	#define CLOCK_LFCLKSRC_SRC_RC (0UL) /!< Internal 32KiHz RC oscillator. /
emilmont	80:8e73be2a2ac1	1051	#define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /!< External 32KiHz crystal. /
emilmont	80:8e73be2a2ac1	1052	#define CLOCK_LFCLKSRC_SRC_Synth (2UL) /!< Internal 32KiHz synthesizer from HFCLK system clock. /
emilmont	80:8e73be2a2ac1	1053
emilmont	80:8e73be2a2ac1	1054	/* Register: CLOCK_CTIV */
emilmont	80:8e73be2a2ac1	1055	/* Description: Calibration timer interval. */
emilmont	80:8e73be2a2ac1	1056
emilmont	80:8e73be2a2ac1	1057	/* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
emilmont	80:8e73be2a2ac1	1058	#define CLOCK_CTIV_CTIV_Pos (0UL) /!< Position of CTIV field. /
emilmont	80:8e73be2a2ac1	1059	#define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /!< Bit mask of CTIV field. /
emilmont	80:8e73be2a2ac1	1060
emilmont	80:8e73be2a2ac1	1061	/* Register: CLOCK_XTALFREQ */
emilmont	80:8e73be2a2ac1	1062	/* Description: Crystal frequency. */
emilmont	80:8e73be2a2ac1	1063
emilmont	80:8e73be2a2ac1	1064	/* Bits 7..0 : External Xtal frequency selection. */
emilmont	80:8e73be2a2ac1	1065	#define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
emilmont	80:8e73be2a2ac1	1066	#define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
Kojto	97:433970e64889	1067	#define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz xtal is used as source for the HFCLK oscillator. /
Kojto	97:433970e64889	1068	#define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz xtal is used as source for the HFCLK oscillator. /
emilmont	80:8e73be2a2ac1	1069
emilmont	80:8e73be2a2ac1	1070
emilmont	80:8e73be2a2ac1	1071	/* Peripheral: ECB */
emilmont	80:8e73be2a2ac1	1072	/* Description: AES ECB Mode Encryption. */
emilmont	80:8e73be2a2ac1	1073
emilmont	80:8e73be2a2ac1	1074	/* Register: ECB_INTENSET */
emilmont	80:8e73be2a2ac1	1075	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	1076
emilmont	80:8e73be2a2ac1	1077	/* Bit 1 : Enable interrupt on ERRORECB event. */
emilmont	80:8e73be2a2ac1	1078	#define ECB_INTENSET_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
emilmont	80:8e73be2a2ac1	1079	#define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
emilmont	80:8e73be2a2ac1	1080	#define ECB_INTENSET_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	1081	#define ECB_INTENSET_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	1082	#define ECB_INTENSET_ERRORECB_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	1083
emilmont	80:8e73be2a2ac1	1084	/* Bit 0 : Enable interrupt on ENDECB event. */
emilmont	80:8e73be2a2ac1	1085	#define ECB_INTENSET_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
emilmont	80:8e73be2a2ac1	1086	#define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /!< Bit mask of ENDECB field. /
emilmont	80:8e73be2a2ac1	1087	#define ECB_INTENSET_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	1088	#define ECB_INTENSET_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	1089	#define ECB_INTENSET_ENDECB_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	1090
emilmont	80:8e73be2a2ac1	1091	/* Register: ECB_INTENCLR */
emilmont	80:8e73be2a2ac1	1092	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	1093
emilmont	80:8e73be2a2ac1	1094	/* Bit 1 : Disable interrupt on ERRORECB event. */
emilmont	80:8e73be2a2ac1	1095	#define ECB_INTENCLR_ERRORECB_Pos (1UL) /!< Position of ERRORECB field. /
emilmont	80:8e73be2a2ac1	1096	#define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /!< Bit mask of ERRORECB field. /
emilmont	80:8e73be2a2ac1	1097	#define ECB_INTENCLR_ERRORECB_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	1098	#define ECB_INTENCLR_ERRORECB_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	1099	#define ECB_INTENCLR_ERRORECB_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	1100
emilmont	80:8e73be2a2ac1	1101	/* Bit 0 : Disable interrupt on ENDECB event. */
emilmont	80:8e73be2a2ac1	1102	#define ECB_INTENCLR_ENDECB_Pos (0UL) /!< Position of ENDECB field. /
emilmont	80:8e73be2a2ac1	1103	#define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /!< Bit mask of ENDECB field. /
emilmont	80:8e73be2a2ac1	1104	#define ECB_INTENCLR_ENDECB_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	1105	#define ECB_INTENCLR_ENDECB_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	1106	#define ECB_INTENCLR_ENDECB_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	1107
emilmont	80:8e73be2a2ac1	1108	/* Register: ECB_POWER */
emilmont	80:8e73be2a2ac1	1109	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	1110
emilmont	80:8e73be2a2ac1	1111	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	1112	#define ECB_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	1113	#define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	1114	#define ECB_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	1115	#define ECB_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	1116
emilmont	80:8e73be2a2ac1	1117
emilmont	80:8e73be2a2ac1	1118	/* Peripheral: FICR */
emilmont	80:8e73be2a2ac1	1119	/* Description: Factory Information Configuration. */
emilmont	80:8e73be2a2ac1	1120
emilmont	80:8e73be2a2ac1	1121	/* Register: FICR_PPFC */
emilmont	80:8e73be2a2ac1	1122	/* Description: Pre-programmed factory code present. */
emilmont	80:8e73be2a2ac1	1123
emilmont	80:8e73be2a2ac1	1124	/* Bits 7..0 : Pre-programmed factory code present. */
emilmont	80:8e73be2a2ac1	1125	#define FICR_PPFC_PPFC_Pos (0UL) /!< Position of PPFC field. /
emilmont	80:8e73be2a2ac1	1126	#define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /!< Bit mask of PPFC field. /
emilmont	80:8e73be2a2ac1	1127	#define FICR_PPFC_PPFC_NotPresent (0xFFUL) /!< Not present. /
emilmont	80:8e73be2a2ac1	1128	#define FICR_PPFC_PPFC_Present (0x00UL) /!< Present. /
emilmont	80:8e73be2a2ac1	1129
emilmont	80:8e73be2a2ac1	1130	/* Register: FICR_CONFIGID */
emilmont	80:8e73be2a2ac1	1131	/* Description: Configuration identifier. */
emilmont	80:8e73be2a2ac1	1132
emilmont	80:8e73be2a2ac1	1133	/* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
emilmont	80:8e73be2a2ac1	1134	#define FICR_CONFIGID_FWID_Pos (16UL) /!< Position of FWID field. /
emilmont	80:8e73be2a2ac1	1135	#define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /!< Bit mask of FWID field. /
emilmont	80:8e73be2a2ac1	1136
emilmont	80:8e73be2a2ac1	1137	/* Bits 15..0 : Hardware Identification Number. */
emilmont	80:8e73be2a2ac1	1138	#define FICR_CONFIGID_HWID_Pos (0UL) /!< Position of HWID field. /
emilmont	80:8e73be2a2ac1	1139	#define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /!< Bit mask of HWID field. /
emilmont	80:8e73be2a2ac1	1140
emilmont	80:8e73be2a2ac1	1141	/* Register: FICR_DEVICEADDRTYPE */
emilmont	80:8e73be2a2ac1	1142	/* Description: Device address type. */
emilmont	80:8e73be2a2ac1	1143
emilmont	80:8e73be2a2ac1	1144	/* Bit 0 : Device address type. */
emilmont	80:8e73be2a2ac1	1145	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /!< Position of DEVICEADDRTYPE field. /
emilmont	80:8e73be2a2ac1	1146	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /!< Bit mask of DEVICEADDRTYPE field. /
emilmont	80:8e73be2a2ac1	1147	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /!< Public address. /
emilmont	80:8e73be2a2ac1	1148	#define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /!< Random address. /
emilmont	80:8e73be2a2ac1	1149
emilmont	80:8e73be2a2ac1	1150	/* Register: FICR_OVERRIDEEN */
emilmont	80:8e73be2a2ac1	1151	/* Description: Radio calibration override enable. */
emilmont	80:8e73be2a2ac1	1152
emilmont	80:8e73be2a2ac1	1153	/* Bit 3 : Override default values for BLE_1Mbit mode. */
emilmont	80:8e73be2a2ac1	1154	#define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /!< Position of BLE_1MBIT field. /
emilmont	80:8e73be2a2ac1	1155	#define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /!< Bit mask of BLE_1MBIT field. /
emilmont	80:8e73be2a2ac1	1156	#define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /!< Override the default values for BLE_1Mbit mode. /
emilmont	80:8e73be2a2ac1	1157	#define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /!< Do not override the default values for BLE_1Mbit mode. /
emilmont	80:8e73be2a2ac1	1158
Kojto	97:433970e64889	1159	/* Bit 0 : Override default values for NRF_1Mbit mode. */
Kojto	97:433970e64889	1160	#define FICR_OVERRIDEEN_NRF_1MBIT_Pos (0UL) /!< Position of NRF_1MBIT field. /
Kojto	97:433970e64889	1161	#define FICR_OVERRIDEEN_NRF_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_NRF_1MBIT_Pos) /!< Bit mask of NRF_1MBIT field. /
Kojto	97:433970e64889	1162	#define FICR_OVERRIDEEN_NRF_1MBIT_Override (0UL) /!< Override the default values for NRF_1Mbit mode. /
Kojto	97:433970e64889	1163	#define FICR_OVERRIDEEN_NRF_1MBIT_NotOverride (1UL) /!< Do not override the default values for NRF_1Mbit mode. /
Kojto	97:433970e64889	1164
Kojto	97:433970e64889	1165	/* Register: FICR_INFO_PART */
Kojto	97:433970e64889	1166	/* Description: Part code */
Kojto	97:433970e64889	1167
Kojto	97:433970e64889	1168	/* Bits 31..0 : Part code */
Kojto	97:433970e64889	1169	#define FICR_INFO_PART_PART_Pos (0UL) /!< Position of PART field. /
Kojto	97:433970e64889	1170	#define FICR_INFO_PART_PART_Msk (0xFFFFFFFFUL << FICR_INFO_PART_PART_Pos) /!< Bit mask of PART field. /
Kojto	97:433970e64889	1171	#define FICR_INFO_PART_PART_N51822 (0x51822UL) /!< nRF51822 /
Kojto	97:433970e64889	1172	#define FICR_INFO_PART_PART_N51422 (0x51422UL) /!< nRF51422 /
Kojto	97:433970e64889	1173	#define FICR_INFO_PART_PART_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1174
Kojto	97:433970e64889	1175	/* Register: FICR_INFO_VARIANT */
Kojto	97:433970e64889	1176	/* Description: Part variant */
Kojto	97:433970e64889	1177
Kojto	97:433970e64889	1178	/* Bits 31..0 : Part variant */
Kojto	97:433970e64889	1179	#define FICR_INFO_VARIANT_VARIANT_Pos (0UL) /!< Position of VARIANT field. /
Kojto	97:433970e64889	1180	#define FICR_INFO_VARIANT_VARIANT_Msk (0xFFFFFFFFUL << FICR_INFO_VARIANT_VARIANT_Pos) /!< Bit mask of VARIANT field. /
Kojto	97:433970e64889	1181	#define FICR_INFO_VARIANT_VARIANT_nRF51C (0x1002UL) /!< nRF51-C (XLR3) /
Kojto	97:433970e64889	1182	#define FICR_INFO_VARIANT_VARIANT_nRF51D (0x1003UL) /!< nRF51-D (L3) /
Kojto	97:433970e64889	1183	#define FICR_INFO_VARIANT_VARIANT_nRF51E (0x1004UL) /!< nRF51-E (XLR3P) /
Kojto	97:433970e64889	1184	#define FICR_INFO_VARIANT_VARIANT_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1185
Kojto	97:433970e64889	1186	/* Register: FICR_INFO_PACKAGE */
Kojto	97:433970e64889	1187	/* Description: Package option */
Kojto	97:433970e64889	1188
Kojto	97:433970e64889	1189	/* Bits 31..0 : Package option */
Kojto	97:433970e64889	1190	#define FICR_INFO_PACKAGE_PACKAGE_Pos (0UL) /!< Position of PACKAGE field. /
Kojto	97:433970e64889	1191	#define FICR_INFO_PACKAGE_PACKAGE_Msk (0xFFFFFFFFUL << FICR_INFO_PACKAGE_PACKAGE_Pos) /!< Bit mask of PACKAGE field. /
Kojto	97:433970e64889	1192	#define FICR_INFO_PACKAGE_PACKAGE_QFN48 (0x0000UL) /!< 48-pin QFN with 31 GPIO /
Kojto	97:433970e64889	1193	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP56A (0x1000UL) /!< nRF51x22 CDxx - WLCSP 56 balls /
Kojto	97:433970e64889	1194	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62A (0x1001UL) /!< nRF51x22 CExx - WLCSP 62 balls /
Kojto	97:433970e64889	1195	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62B (0x1002UL) /!< nRF51x22 CFxx - WLCSP 62 balls /
Kojto	97:433970e64889	1196	#define FICR_INFO_PACKAGE_PACKAGE_nRF51CSP62C (0x1003UL) /!< nRF51x22 CTxx - WLCSP 62 balls /
Kojto	97:433970e64889	1197	#define FICR_INFO_PACKAGE_PACKAGE_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1198
Kojto	97:433970e64889	1199	/* Register: FICR_INFO_RAM */
Kojto	97:433970e64889	1200	/* Description: RAM variant */
Kojto	97:433970e64889	1201
Kojto	97:433970e64889	1202	/* Bits 31..0 : RAM variant */
Kojto	97:433970e64889	1203	#define FICR_INFO_RAM_RAM_Pos (0UL) /!< Position of RAM field. /
Kojto	97:433970e64889	1204	#define FICR_INFO_RAM_RAM_Msk (0xFFFFFFFFUL << FICR_INFO_RAM_RAM_Pos) /!< Bit mask of RAM field. /
Kojto	97:433970e64889	1205	#define FICR_INFO_RAM_RAM_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1206	#define FICR_INFO_RAM_RAM_K16 (16UL) /!< 16 kByte RAM. /
Kojto	97:433970e64889	1207	#define FICR_INFO_RAM_RAM_K32 (32UL) /!< 32 kByte RAM. /
Kojto	97:433970e64889	1208
Kojto	97:433970e64889	1209	/* Register: FICR_INFO_FLASH */
Kojto	97:433970e64889	1210	/* Description: Flash variant */
Kojto	97:433970e64889	1211
Kojto	97:433970e64889	1212	/* Bits 31..0 : Flash variant */
Kojto	97:433970e64889	1213	#define FICR_INFO_FLASH_FLASH_Pos (0UL) /!< Position of FLASH field. /
Kojto	97:433970e64889	1214	#define FICR_INFO_FLASH_FLASH_Msk (0xFFFFFFFFUL << FICR_INFO_FLASH_FLASH_Pos) /!< Bit mask of FLASH field. /
Kojto	97:433970e64889	1215	#define FICR_INFO_FLASH_FLASH_Unspecified (0xFFFFFFFFUL) /!< Unspecified /
Kojto	97:433970e64889	1216	#define FICR_INFO_FLASH_FLASH_K128 (128UL) /!< 128 kByte FLASH. /
Kojto	97:433970e64889	1217	#define FICR_INFO_FLASH_FLASH_K256 (256UL) /!< 256 kByte FLASH. /
Kojto	97:433970e64889	1218
emilmont	80:8e73be2a2ac1	1219
emilmont	80:8e73be2a2ac1	1220	/* Peripheral: GPIO */
emilmont	80:8e73be2a2ac1	1221	/* Description: General purpose input and output. */
emilmont	80:8e73be2a2ac1	1222
emilmont	80:8e73be2a2ac1	1223	/* Register: GPIO_OUT */
emilmont	80:8e73be2a2ac1	1224	/* Description: Write GPIO port. */
emilmont	80:8e73be2a2ac1	1225
emilmont	80:8e73be2a2ac1	1226	/* Bit 31 : Pin 31. */
emilmont	80:8e73be2a2ac1	1227	#define GPIO_OUT_PIN31_Pos (31UL) /!< Position of PIN31 field. /
emilmont	80:8e73be2a2ac1	1228	#define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /!< Bit mask of PIN31 field. /
emilmont	80:8e73be2a2ac1	1229	#define GPIO_OUT_PIN31_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1230	#define GPIO_OUT_PIN31_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1231
emilmont	80:8e73be2a2ac1	1232	/* Bit 30 : Pin 30. */
emilmont	80:8e73be2a2ac1	1233	#define GPIO_OUT_PIN30_Pos (30UL) /!< Position of PIN30 field. /
emilmont	80:8e73be2a2ac1	1234	#define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /!< Bit mask of PIN30 field. /
emilmont	80:8e73be2a2ac1	1235	#define GPIO_OUT_PIN30_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1236	#define GPIO_OUT_PIN30_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1237
emilmont	80:8e73be2a2ac1	1238	/* Bit 29 : Pin 29. */
emilmont	80:8e73be2a2ac1	1239	#define GPIO_OUT_PIN29_Pos (29UL) /!< Position of PIN29 field. /
emilmont	80:8e73be2a2ac1	1240	#define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /!< Bit mask of PIN29 field. /
emilmont	80:8e73be2a2ac1	1241	#define GPIO_OUT_PIN29_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1242	#define GPIO_OUT_PIN29_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1243
emilmont	80:8e73be2a2ac1	1244	/* Bit 28 : Pin 28. */
emilmont	80:8e73be2a2ac1	1245	#define GPIO_OUT_PIN28_Pos (28UL) /!< Position of PIN28 field. /
emilmont	80:8e73be2a2ac1	1246	#define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /!< Bit mask of PIN28 field. /
emilmont	80:8e73be2a2ac1	1247	#define GPIO_OUT_PIN28_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1248	#define GPIO_OUT_PIN28_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1249
emilmont	80:8e73be2a2ac1	1250	/* Bit 27 : Pin 27. */
emilmont	80:8e73be2a2ac1	1251	#define GPIO_OUT_PIN27_Pos (27UL) /!< Position of PIN27 field. /
emilmont	80:8e73be2a2ac1	1252	#define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /!< Bit mask of PIN27 field. /
emilmont	80:8e73be2a2ac1	1253	#define GPIO_OUT_PIN27_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1254	#define GPIO_OUT_PIN27_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1255
emilmont	80:8e73be2a2ac1	1256	/* Bit 26 : Pin 26. */
emilmont	80:8e73be2a2ac1	1257	#define GPIO_OUT_PIN26_Pos (26UL) /!< Position of PIN26 field. /
emilmont	80:8e73be2a2ac1	1258	#define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /!< Bit mask of PIN26 field. /
emilmont	80:8e73be2a2ac1	1259	#define GPIO_OUT_PIN26_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1260	#define GPIO_OUT_PIN26_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1261
emilmont	80:8e73be2a2ac1	1262	/* Bit 25 : Pin 25. */
emilmont	80:8e73be2a2ac1	1263	#define GPIO_OUT_PIN25_Pos (25UL) /!< Position of PIN25 field. /
emilmont	80:8e73be2a2ac1	1264	#define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /!< Bit mask of PIN25 field. /
emilmont	80:8e73be2a2ac1	1265	#define GPIO_OUT_PIN25_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1266	#define GPIO_OUT_PIN25_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1267
emilmont	80:8e73be2a2ac1	1268	/* Bit 24 : Pin 24. */
emilmont	80:8e73be2a2ac1	1269	#define GPIO_OUT_PIN24_Pos (24UL) /!< Position of PIN24 field. /
emilmont	80:8e73be2a2ac1	1270	#define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /!< Bit mask of PIN24 field. /
emilmont	80:8e73be2a2ac1	1271	#define GPIO_OUT_PIN24_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1272	#define GPIO_OUT_PIN24_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1273
emilmont	80:8e73be2a2ac1	1274	/* Bit 23 : Pin 23. */
emilmont	80:8e73be2a2ac1	1275	#define GPIO_OUT_PIN23_Pos (23UL) /!< Position of PIN23 field. /
emilmont	80:8e73be2a2ac1	1276	#define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /!< Bit mask of PIN23 field. /
emilmont	80:8e73be2a2ac1	1277	#define GPIO_OUT_PIN23_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1278	#define GPIO_OUT_PIN23_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1279
emilmont	80:8e73be2a2ac1	1280	/* Bit 22 : Pin 22. */
emilmont	80:8e73be2a2ac1	1281	#define GPIO_OUT_PIN22_Pos (22UL) /!< Position of PIN22 field. /
emilmont	80:8e73be2a2ac1	1282	#define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /!< Bit mask of PIN22 field. /
emilmont	80:8e73be2a2ac1	1283	#define GPIO_OUT_PIN22_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1284	#define GPIO_OUT_PIN22_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1285
emilmont	80:8e73be2a2ac1	1286	/* Bit 21 : Pin 21. */
emilmont	80:8e73be2a2ac1	1287	#define GPIO_OUT_PIN21_Pos (21UL) /!< Position of PIN21 field. /
emilmont	80:8e73be2a2ac1	1288	#define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /!< Bit mask of PIN21 field. /
emilmont	80:8e73be2a2ac1	1289	#define GPIO_OUT_PIN21_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1290	#define GPIO_OUT_PIN21_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1291
emilmont	80:8e73be2a2ac1	1292	/* Bit 20 : Pin 20. */
emilmont	80:8e73be2a2ac1	1293	#define GPIO_OUT_PIN20_Pos (20UL) /!< Position of PIN20 field. /
emilmont	80:8e73be2a2ac1	1294	#define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /!< Bit mask of PIN20 field. /
emilmont	80:8e73be2a2ac1	1295	#define GPIO_OUT_PIN20_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1296	#define GPIO_OUT_PIN20_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1297
emilmont	80:8e73be2a2ac1	1298	/* Bit 19 : Pin 19. */
emilmont	80:8e73be2a2ac1	1299	#define GPIO_OUT_PIN19_Pos (19UL) /!< Position of PIN19 field. /
emilmont	80:8e73be2a2ac1	1300	#define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /!< Bit mask of PIN19 field. /
emilmont	80:8e73be2a2ac1	1301	#define GPIO_OUT_PIN19_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1302	#define GPIO_OUT_PIN19_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1303
emilmont	80:8e73be2a2ac1	1304	/* Bit 18 : Pin 18. */
emilmont	80:8e73be2a2ac1	1305	#define GPIO_OUT_PIN18_Pos (18UL) /!< Position of PIN18 field. /
emilmont	80:8e73be2a2ac1	1306	#define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /!< Bit mask of PIN18 field. /
emilmont	80:8e73be2a2ac1	1307	#define GPIO_OUT_PIN18_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1308	#define GPIO_OUT_PIN18_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1309
emilmont	80:8e73be2a2ac1	1310	/* Bit 17 : Pin 17. */
emilmont	80:8e73be2a2ac1	1311	#define GPIO_OUT_PIN17_Pos (17UL) /!< Position of PIN17 field. /
emilmont	80:8e73be2a2ac1	1312	#define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /!< Bit mask of PIN17 field. /
emilmont	80:8e73be2a2ac1	1313	#define GPIO_OUT_PIN17_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1314	#define GPIO_OUT_PIN17_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1315
emilmont	80:8e73be2a2ac1	1316	/* Bit 16 : Pin 16. */
emilmont	80:8e73be2a2ac1	1317	#define GPIO_OUT_PIN16_Pos (16UL) /!< Position of PIN16 field. /
emilmont	80:8e73be2a2ac1	1318	#define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /!< Bit mask of PIN16 field. /
emilmont	80:8e73be2a2ac1	1319	#define GPIO_OUT_PIN16_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1320	#define GPIO_OUT_PIN16_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1321
emilmont	80:8e73be2a2ac1	1322	/* Bit 15 : Pin 15. */
emilmont	80:8e73be2a2ac1	1323	#define GPIO_OUT_PIN15_Pos (15UL) /!< Position of PIN15 field. /
emilmont	80:8e73be2a2ac1	1324	#define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /!< Bit mask of PIN15 field. /
emilmont	80:8e73be2a2ac1	1325	#define GPIO_OUT_PIN15_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1326	#define GPIO_OUT_PIN15_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1327
emilmont	80:8e73be2a2ac1	1328	/* Bit 14 : Pin 14. */
emilmont	80:8e73be2a2ac1	1329	#define GPIO_OUT_PIN14_Pos (14UL) /!< Position of PIN14 field. /
emilmont	80:8e73be2a2ac1	1330	#define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /!< Bit mask of PIN14 field. /
emilmont	80:8e73be2a2ac1	1331	#define GPIO_OUT_PIN14_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1332	#define GPIO_OUT_PIN14_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1333
emilmont	80:8e73be2a2ac1	1334	/* Bit 13 : Pin 13. */
emilmont	80:8e73be2a2ac1	1335	#define GPIO_OUT_PIN13_Pos (13UL) /!< Position of PIN13 field. /
emilmont	80:8e73be2a2ac1	1336	#define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /!< Bit mask of PIN13 field. /
emilmont	80:8e73be2a2ac1	1337	#define GPIO_OUT_PIN13_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1338	#define GPIO_OUT_PIN13_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1339
emilmont	80:8e73be2a2ac1	1340	/* Bit 12 : Pin 12. */
emilmont	80:8e73be2a2ac1	1341	#define GPIO_OUT_PIN12_Pos (12UL) /!< Position of PIN12 field. /
emilmont	80:8e73be2a2ac1	1342	#define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /!< Bit mask of PIN12 field. /
emilmont	80:8e73be2a2ac1	1343	#define GPIO_OUT_PIN12_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1344	#define GPIO_OUT_PIN12_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1345
emilmont	80:8e73be2a2ac1	1346	/* Bit 11 : Pin 11. */
emilmont	80:8e73be2a2ac1	1347	#define GPIO_OUT_PIN11_Pos (11UL) /!< Position of PIN11 field. /
emilmont	80:8e73be2a2ac1	1348	#define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /!< Bit mask of PIN11 field. /
emilmont	80:8e73be2a2ac1	1349	#define GPIO_OUT_PIN11_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1350	#define GPIO_OUT_PIN11_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1351
emilmont	80:8e73be2a2ac1	1352	/* Bit 10 : Pin 10. */
emilmont	80:8e73be2a2ac1	1353	#define GPIO_OUT_PIN10_Pos (10UL) /!< Position of PIN10 field. /
emilmont	80:8e73be2a2ac1	1354	#define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /!< Bit mask of PIN10 field. /
emilmont	80:8e73be2a2ac1	1355	#define GPIO_OUT_PIN10_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1356	#define GPIO_OUT_PIN10_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1357
emilmont	80:8e73be2a2ac1	1358	/* Bit 9 : Pin 9. */
emilmont	80:8e73be2a2ac1	1359	#define GPIO_OUT_PIN9_Pos (9UL) /!< Position of PIN9 field. /
emilmont	80:8e73be2a2ac1	1360	#define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /!< Bit mask of PIN9 field. /
emilmont	80:8e73be2a2ac1	1361	#define GPIO_OUT_PIN9_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1362	#define GPIO_OUT_PIN9_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1363
emilmont	80:8e73be2a2ac1	1364	/* Bit 8 : Pin 8. */
emilmont	80:8e73be2a2ac1	1365	#define GPIO_OUT_PIN8_Pos (8UL) /!< Position of PIN8 field. /
emilmont	80:8e73be2a2ac1	1366	#define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /!< Bit mask of PIN8 field. /
emilmont	80:8e73be2a2ac1	1367	#define GPIO_OUT_PIN8_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1368	#define GPIO_OUT_PIN8_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1369
emilmont	80:8e73be2a2ac1	1370	/* Bit 7 : Pin 7. */
emilmont	80:8e73be2a2ac1	1371	#define GPIO_OUT_PIN7_Pos (7UL) /!< Position of PIN7 field. /
emilmont	80:8e73be2a2ac1	1372	#define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /!< Bit mask of PIN7 field. /
emilmont	80:8e73be2a2ac1	1373	#define GPIO_OUT_PIN7_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1374	#define GPIO_OUT_PIN7_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1375
emilmont	80:8e73be2a2ac1	1376	/* Bit 6 : Pin 6. */
emilmont	80:8e73be2a2ac1	1377	#define GPIO_OUT_PIN6_Pos (6UL) /!< Position of PIN6 field. /
emilmont	80:8e73be2a2ac1	1378	#define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /!< Bit mask of PIN6 field. /
emilmont	80:8e73be2a2ac1	1379	#define GPIO_OUT_PIN6_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1380	#define GPIO_OUT_PIN6_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1381
emilmont	80:8e73be2a2ac1	1382	/* Bit 5 : Pin 5. */
emilmont	80:8e73be2a2ac1	1383	#define GPIO_OUT_PIN5_Pos (5UL) /!< Position of PIN5 field. /
emilmont	80:8e73be2a2ac1	1384	#define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /!< Bit mask of PIN5 field. /
emilmont	80:8e73be2a2ac1	1385	#define GPIO_OUT_PIN5_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1386	#define GPIO_OUT_PIN5_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1387
emilmont	80:8e73be2a2ac1	1388	/* Bit 4 : Pin 4. */
emilmont	80:8e73be2a2ac1	1389	#define GPIO_OUT_PIN4_Pos (4UL) /!< Position of PIN4 field. /
emilmont	80:8e73be2a2ac1	1390	#define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /!< Bit mask of PIN4 field. /
emilmont	80:8e73be2a2ac1	1391	#define GPIO_OUT_PIN4_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1392	#define GPIO_OUT_PIN4_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1393
emilmont	80:8e73be2a2ac1	1394	/* Bit 3 : Pin 3. */
emilmont	80:8e73be2a2ac1	1395	#define GPIO_OUT_PIN3_Pos (3UL) /!< Position of PIN3 field. /
emilmont	80:8e73be2a2ac1	1396	#define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /!< Bit mask of PIN3 field. /
emilmont	80:8e73be2a2ac1	1397	#define GPIO_OUT_PIN3_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1398	#define GPIO_OUT_PIN3_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1399
emilmont	80:8e73be2a2ac1	1400	/* Bit 2 : Pin 2. */
emilmont	80:8e73be2a2ac1	1401	#define GPIO_OUT_PIN2_Pos (2UL) /!< Position of PIN2 field. /
emilmont	80:8e73be2a2ac1	1402	#define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /!< Bit mask of PIN2 field. /
emilmont	80:8e73be2a2ac1	1403	#define GPIO_OUT_PIN2_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1404	#define GPIO_OUT_PIN2_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1405
emilmont	80:8e73be2a2ac1	1406	/* Bit 1 : Pin 1. */
emilmont	80:8e73be2a2ac1	1407	#define GPIO_OUT_PIN1_Pos (1UL) /!< Position of PIN1 field. /
emilmont	80:8e73be2a2ac1	1408	#define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /!< Bit mask of PIN1 field. /
emilmont	80:8e73be2a2ac1	1409	#define GPIO_OUT_PIN1_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1410	#define GPIO_OUT_PIN1_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1411
emilmont	80:8e73be2a2ac1	1412	/* Bit 0 : Pin 0. */
emilmont	80:8e73be2a2ac1	1413	#define GPIO_OUT_PIN0_Pos (0UL) /!< Position of PIN0 field. /
emilmont	80:8e73be2a2ac1	1414	#define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /!< Bit mask of PIN0 field. /
emilmont	80:8e73be2a2ac1	1415	#define GPIO_OUT_PIN0_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1416	#define GPIO_OUT_PIN0_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1417
emilmont	80:8e73be2a2ac1	1418	/* Register: GPIO_OUTSET */
emilmont	80:8e73be2a2ac1	1419	/* Description: Set individual bits in GPIO port. */
emilmont	80:8e73be2a2ac1	1420
emilmont	80:8e73be2a2ac1	1421	/* Bit 31 : Pin 31. */
emilmont	80:8e73be2a2ac1	1422	#define GPIO_OUTSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
emilmont	80:8e73be2a2ac1	1423	#define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
emilmont	80:8e73be2a2ac1	1424	#define GPIO_OUTSET_PIN31_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1425	#define GPIO_OUTSET_PIN31_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1426	#define GPIO_OUTSET_PIN31_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1427
emilmont	80:8e73be2a2ac1	1428	/* Bit 30 : Pin 30. */
emilmont	80:8e73be2a2ac1	1429	#define GPIO_OUTSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
emilmont	80:8e73be2a2ac1	1430	#define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
emilmont	80:8e73be2a2ac1	1431	#define GPIO_OUTSET_PIN30_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1432	#define GPIO_OUTSET_PIN30_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1433	#define GPIO_OUTSET_PIN30_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1434
emilmont	80:8e73be2a2ac1	1435	/* Bit 29 : Pin 29. */
emilmont	80:8e73be2a2ac1	1436	#define GPIO_OUTSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
emilmont	80:8e73be2a2ac1	1437	#define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
emilmont	80:8e73be2a2ac1	1438	#define GPIO_OUTSET_PIN29_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1439	#define GPIO_OUTSET_PIN29_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1440	#define GPIO_OUTSET_PIN29_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1441
emilmont	80:8e73be2a2ac1	1442	/* Bit 28 : Pin 28. */
emilmont	80:8e73be2a2ac1	1443	#define GPIO_OUTSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
emilmont	80:8e73be2a2ac1	1444	#define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
emilmont	80:8e73be2a2ac1	1445	#define GPIO_OUTSET_PIN28_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1446	#define GPIO_OUTSET_PIN28_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1447	#define GPIO_OUTSET_PIN28_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1448
emilmont	80:8e73be2a2ac1	1449	/* Bit 27 : Pin 27. */
emilmont	80:8e73be2a2ac1	1450	#define GPIO_OUTSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
emilmont	80:8e73be2a2ac1	1451	#define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
emilmont	80:8e73be2a2ac1	1452	#define GPIO_OUTSET_PIN27_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1453	#define GPIO_OUTSET_PIN27_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1454	#define GPIO_OUTSET_PIN27_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1455
emilmont	80:8e73be2a2ac1	1456	/* Bit 26 : Pin 26. */
emilmont	80:8e73be2a2ac1	1457	#define GPIO_OUTSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
emilmont	80:8e73be2a2ac1	1458	#define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
emilmont	80:8e73be2a2ac1	1459	#define GPIO_OUTSET_PIN26_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1460	#define GPIO_OUTSET_PIN26_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1461	#define GPIO_OUTSET_PIN26_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1462
emilmont	80:8e73be2a2ac1	1463	/* Bit 25 : Pin 25. */
emilmont	80:8e73be2a2ac1	1464	#define GPIO_OUTSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
emilmont	80:8e73be2a2ac1	1465	#define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
emilmont	80:8e73be2a2ac1	1466	#define GPIO_OUTSET_PIN25_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1467	#define GPIO_OUTSET_PIN25_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1468	#define GPIO_OUTSET_PIN25_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1469
emilmont	80:8e73be2a2ac1	1470	/* Bit 24 : Pin 24. */
emilmont	80:8e73be2a2ac1	1471	#define GPIO_OUTSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
emilmont	80:8e73be2a2ac1	1472	#define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
emilmont	80:8e73be2a2ac1	1473	#define GPIO_OUTSET_PIN24_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1474	#define GPIO_OUTSET_PIN24_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1475	#define GPIO_OUTSET_PIN24_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1476
emilmont	80:8e73be2a2ac1	1477	/* Bit 23 : Pin 23. */
emilmont	80:8e73be2a2ac1	1478	#define GPIO_OUTSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
emilmont	80:8e73be2a2ac1	1479	#define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
emilmont	80:8e73be2a2ac1	1480	#define GPIO_OUTSET_PIN23_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1481	#define GPIO_OUTSET_PIN23_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1482	#define GPIO_OUTSET_PIN23_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1483
emilmont	80:8e73be2a2ac1	1484	/* Bit 22 : Pin 22. */
emilmont	80:8e73be2a2ac1	1485	#define GPIO_OUTSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
emilmont	80:8e73be2a2ac1	1486	#define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
emilmont	80:8e73be2a2ac1	1487	#define GPIO_OUTSET_PIN22_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1488	#define GPIO_OUTSET_PIN22_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1489	#define GPIO_OUTSET_PIN22_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1490
emilmont	80:8e73be2a2ac1	1491	/* Bit 21 : Pin 21. */
emilmont	80:8e73be2a2ac1	1492	#define GPIO_OUTSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
emilmont	80:8e73be2a2ac1	1493	#define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
emilmont	80:8e73be2a2ac1	1494	#define GPIO_OUTSET_PIN21_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1495	#define GPIO_OUTSET_PIN21_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1496	#define GPIO_OUTSET_PIN21_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1497
emilmont	80:8e73be2a2ac1	1498	/* Bit 20 : Pin 20. */
emilmont	80:8e73be2a2ac1	1499	#define GPIO_OUTSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
emilmont	80:8e73be2a2ac1	1500	#define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
emilmont	80:8e73be2a2ac1	1501	#define GPIO_OUTSET_PIN20_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1502	#define GPIO_OUTSET_PIN20_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1503	#define GPIO_OUTSET_PIN20_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1504
emilmont	80:8e73be2a2ac1	1505	/* Bit 19 : Pin 19. */
emilmont	80:8e73be2a2ac1	1506	#define GPIO_OUTSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
emilmont	80:8e73be2a2ac1	1507	#define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
emilmont	80:8e73be2a2ac1	1508	#define GPIO_OUTSET_PIN19_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1509	#define GPIO_OUTSET_PIN19_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1510	#define GPIO_OUTSET_PIN19_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1511
emilmont	80:8e73be2a2ac1	1512	/* Bit 18 : Pin 18. */
emilmont	80:8e73be2a2ac1	1513	#define GPIO_OUTSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
emilmont	80:8e73be2a2ac1	1514	#define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
emilmont	80:8e73be2a2ac1	1515	#define GPIO_OUTSET_PIN18_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1516	#define GPIO_OUTSET_PIN18_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1517	#define GPIO_OUTSET_PIN18_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1518
emilmont	80:8e73be2a2ac1	1519	/* Bit 17 : Pin 17. */
emilmont	80:8e73be2a2ac1	1520	#define GPIO_OUTSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
emilmont	80:8e73be2a2ac1	1521	#define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
emilmont	80:8e73be2a2ac1	1522	#define GPIO_OUTSET_PIN17_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1523	#define GPIO_OUTSET_PIN17_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1524	#define GPIO_OUTSET_PIN17_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1525
emilmont	80:8e73be2a2ac1	1526	/* Bit 16 : Pin 16. */
emilmont	80:8e73be2a2ac1	1527	#define GPIO_OUTSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
emilmont	80:8e73be2a2ac1	1528	#define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
emilmont	80:8e73be2a2ac1	1529	#define GPIO_OUTSET_PIN16_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1530	#define GPIO_OUTSET_PIN16_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1531	#define GPIO_OUTSET_PIN16_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1532
emilmont	80:8e73be2a2ac1	1533	/* Bit 15 : Pin 15. */
emilmont	80:8e73be2a2ac1	1534	#define GPIO_OUTSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
emilmont	80:8e73be2a2ac1	1535	#define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
emilmont	80:8e73be2a2ac1	1536	#define GPIO_OUTSET_PIN15_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1537	#define GPIO_OUTSET_PIN15_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1538	#define GPIO_OUTSET_PIN15_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1539
emilmont	80:8e73be2a2ac1	1540	/* Bit 14 : Pin 14. */
emilmont	80:8e73be2a2ac1	1541	#define GPIO_OUTSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
emilmont	80:8e73be2a2ac1	1542	#define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
emilmont	80:8e73be2a2ac1	1543	#define GPIO_OUTSET_PIN14_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1544	#define GPIO_OUTSET_PIN14_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1545	#define GPIO_OUTSET_PIN14_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1546
emilmont	80:8e73be2a2ac1	1547	/* Bit 13 : Pin 13. */
emilmont	80:8e73be2a2ac1	1548	#define GPIO_OUTSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
emilmont	80:8e73be2a2ac1	1549	#define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
emilmont	80:8e73be2a2ac1	1550	#define GPIO_OUTSET_PIN13_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1551	#define GPIO_OUTSET_PIN13_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1552	#define GPIO_OUTSET_PIN13_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1553
emilmont	80:8e73be2a2ac1	1554	/* Bit 12 : Pin 12. */
emilmont	80:8e73be2a2ac1	1555	#define GPIO_OUTSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
emilmont	80:8e73be2a2ac1	1556	#define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
emilmont	80:8e73be2a2ac1	1557	#define GPIO_OUTSET_PIN12_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1558	#define GPIO_OUTSET_PIN12_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1559	#define GPIO_OUTSET_PIN12_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1560
emilmont	80:8e73be2a2ac1	1561	/* Bit 11 : Pin 11. */
emilmont	80:8e73be2a2ac1	1562	#define GPIO_OUTSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
emilmont	80:8e73be2a2ac1	1563	#define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
emilmont	80:8e73be2a2ac1	1564	#define GPIO_OUTSET_PIN11_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1565	#define GPIO_OUTSET_PIN11_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1566	#define GPIO_OUTSET_PIN11_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1567
emilmont	80:8e73be2a2ac1	1568	/* Bit 10 : Pin 10. */
emilmont	80:8e73be2a2ac1	1569	#define GPIO_OUTSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
emilmont	80:8e73be2a2ac1	1570	#define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
emilmont	80:8e73be2a2ac1	1571	#define GPIO_OUTSET_PIN10_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1572	#define GPIO_OUTSET_PIN10_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1573	#define GPIO_OUTSET_PIN10_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1574
emilmont	80:8e73be2a2ac1	1575	/* Bit 9 : Pin 9. */
emilmont	80:8e73be2a2ac1	1576	#define GPIO_OUTSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
emilmont	80:8e73be2a2ac1	1577	#define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
emilmont	80:8e73be2a2ac1	1578	#define GPIO_OUTSET_PIN9_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1579	#define GPIO_OUTSET_PIN9_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1580	#define GPIO_OUTSET_PIN9_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1581
emilmont	80:8e73be2a2ac1	1582	/* Bit 8 : Pin 8. */
emilmont	80:8e73be2a2ac1	1583	#define GPIO_OUTSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
emilmont	80:8e73be2a2ac1	1584	#define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
emilmont	80:8e73be2a2ac1	1585	#define GPIO_OUTSET_PIN8_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1586	#define GPIO_OUTSET_PIN8_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1587	#define GPIO_OUTSET_PIN8_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1588
emilmont	80:8e73be2a2ac1	1589	/* Bit 7 : Pin 7. */
emilmont	80:8e73be2a2ac1	1590	#define GPIO_OUTSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
emilmont	80:8e73be2a2ac1	1591	#define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
emilmont	80:8e73be2a2ac1	1592	#define GPIO_OUTSET_PIN7_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1593	#define GPIO_OUTSET_PIN7_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1594	#define GPIO_OUTSET_PIN7_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1595
emilmont	80:8e73be2a2ac1	1596	/* Bit 6 : Pin 6. */
emilmont	80:8e73be2a2ac1	1597	#define GPIO_OUTSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
emilmont	80:8e73be2a2ac1	1598	#define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
emilmont	80:8e73be2a2ac1	1599	#define GPIO_OUTSET_PIN6_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1600	#define GPIO_OUTSET_PIN6_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1601	#define GPIO_OUTSET_PIN6_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1602
emilmont	80:8e73be2a2ac1	1603	/* Bit 5 : Pin 5. */
emilmont	80:8e73be2a2ac1	1604	#define GPIO_OUTSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
emilmont	80:8e73be2a2ac1	1605	#define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
emilmont	80:8e73be2a2ac1	1606	#define GPIO_OUTSET_PIN5_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1607	#define GPIO_OUTSET_PIN5_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1608	#define GPIO_OUTSET_PIN5_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1609
emilmont	80:8e73be2a2ac1	1610	/* Bit 4 : Pin 4. */
emilmont	80:8e73be2a2ac1	1611	#define GPIO_OUTSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
emilmont	80:8e73be2a2ac1	1612	#define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
emilmont	80:8e73be2a2ac1	1613	#define GPIO_OUTSET_PIN4_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1614	#define GPIO_OUTSET_PIN4_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1615	#define GPIO_OUTSET_PIN4_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1616
emilmont	80:8e73be2a2ac1	1617	/* Bit 3 : Pin 3. */
emilmont	80:8e73be2a2ac1	1618	#define GPIO_OUTSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
emilmont	80:8e73be2a2ac1	1619	#define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
emilmont	80:8e73be2a2ac1	1620	#define GPIO_OUTSET_PIN3_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1621	#define GPIO_OUTSET_PIN3_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1622	#define GPIO_OUTSET_PIN3_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1623
emilmont	80:8e73be2a2ac1	1624	/* Bit 2 : Pin 2. */
emilmont	80:8e73be2a2ac1	1625	#define GPIO_OUTSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
emilmont	80:8e73be2a2ac1	1626	#define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
emilmont	80:8e73be2a2ac1	1627	#define GPIO_OUTSET_PIN2_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1628	#define GPIO_OUTSET_PIN2_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1629	#define GPIO_OUTSET_PIN2_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1630
emilmont	80:8e73be2a2ac1	1631	/* Bit 1 : Pin 1. */
emilmont	80:8e73be2a2ac1	1632	#define GPIO_OUTSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
emilmont	80:8e73be2a2ac1	1633	#define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
emilmont	80:8e73be2a2ac1	1634	#define GPIO_OUTSET_PIN1_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1635	#define GPIO_OUTSET_PIN1_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1636	#define GPIO_OUTSET_PIN1_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1637
emilmont	80:8e73be2a2ac1	1638	/* Bit 0 : Pin 0. */
emilmont	80:8e73be2a2ac1	1639	#define GPIO_OUTSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
emilmont	80:8e73be2a2ac1	1640	#define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
emilmont	80:8e73be2a2ac1	1641	#define GPIO_OUTSET_PIN0_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1642	#define GPIO_OUTSET_PIN0_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1643	#define GPIO_OUTSET_PIN0_Set (1UL) /!< Set pin driver high. /
emilmont	80:8e73be2a2ac1	1644
emilmont	80:8e73be2a2ac1	1645	/* Register: GPIO_OUTCLR */
emilmont	80:8e73be2a2ac1	1646	/* Description: Clear individual bits in GPIO port. */
emilmont	80:8e73be2a2ac1	1647
emilmont	80:8e73be2a2ac1	1648	/* Bit 31 : Pin 31. */
emilmont	80:8e73be2a2ac1	1649	#define GPIO_OUTCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
emilmont	80:8e73be2a2ac1	1650	#define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
emilmont	80:8e73be2a2ac1	1651	#define GPIO_OUTCLR_PIN31_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1652	#define GPIO_OUTCLR_PIN31_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1653	#define GPIO_OUTCLR_PIN31_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1654
emilmont	80:8e73be2a2ac1	1655	/* Bit 30 : Pin 30. */
emilmont	80:8e73be2a2ac1	1656	#define GPIO_OUTCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
emilmont	80:8e73be2a2ac1	1657	#define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
emilmont	80:8e73be2a2ac1	1658	#define GPIO_OUTCLR_PIN30_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1659	#define GPIO_OUTCLR_PIN30_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1660	#define GPIO_OUTCLR_PIN30_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1661
emilmont	80:8e73be2a2ac1	1662	/* Bit 29 : Pin 29. */
emilmont	80:8e73be2a2ac1	1663	#define GPIO_OUTCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
emilmont	80:8e73be2a2ac1	1664	#define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
emilmont	80:8e73be2a2ac1	1665	#define GPIO_OUTCLR_PIN29_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1666	#define GPIO_OUTCLR_PIN29_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1667	#define GPIO_OUTCLR_PIN29_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1668
emilmont	80:8e73be2a2ac1	1669	/* Bit 28 : Pin 28. */
emilmont	80:8e73be2a2ac1	1670	#define GPIO_OUTCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
emilmont	80:8e73be2a2ac1	1671	#define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
emilmont	80:8e73be2a2ac1	1672	#define GPIO_OUTCLR_PIN28_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1673	#define GPIO_OUTCLR_PIN28_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1674	#define GPIO_OUTCLR_PIN28_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1675
emilmont	80:8e73be2a2ac1	1676	/* Bit 27 : Pin 27. */
emilmont	80:8e73be2a2ac1	1677	#define GPIO_OUTCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
emilmont	80:8e73be2a2ac1	1678	#define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
emilmont	80:8e73be2a2ac1	1679	#define GPIO_OUTCLR_PIN27_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1680	#define GPIO_OUTCLR_PIN27_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1681	#define GPIO_OUTCLR_PIN27_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1682
emilmont	80:8e73be2a2ac1	1683	/* Bit 26 : Pin 26. */
emilmont	80:8e73be2a2ac1	1684	#define GPIO_OUTCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
emilmont	80:8e73be2a2ac1	1685	#define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
emilmont	80:8e73be2a2ac1	1686	#define GPIO_OUTCLR_PIN26_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1687	#define GPIO_OUTCLR_PIN26_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1688	#define GPIO_OUTCLR_PIN26_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1689
emilmont	80:8e73be2a2ac1	1690	/* Bit 25 : Pin 25. */
emilmont	80:8e73be2a2ac1	1691	#define GPIO_OUTCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
emilmont	80:8e73be2a2ac1	1692	#define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
emilmont	80:8e73be2a2ac1	1693	#define GPIO_OUTCLR_PIN25_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1694	#define GPIO_OUTCLR_PIN25_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1695	#define GPIO_OUTCLR_PIN25_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1696
emilmont	80:8e73be2a2ac1	1697	/* Bit 24 : Pin 24. */
emilmont	80:8e73be2a2ac1	1698	#define GPIO_OUTCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
emilmont	80:8e73be2a2ac1	1699	#define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
emilmont	80:8e73be2a2ac1	1700	#define GPIO_OUTCLR_PIN24_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1701	#define GPIO_OUTCLR_PIN24_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1702	#define GPIO_OUTCLR_PIN24_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1703
emilmont	80:8e73be2a2ac1	1704	/* Bit 23 : Pin 23. */
emilmont	80:8e73be2a2ac1	1705	#define GPIO_OUTCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
emilmont	80:8e73be2a2ac1	1706	#define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
emilmont	80:8e73be2a2ac1	1707	#define GPIO_OUTCLR_PIN23_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1708	#define GPIO_OUTCLR_PIN23_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1709	#define GPIO_OUTCLR_PIN23_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1710
emilmont	80:8e73be2a2ac1	1711	/* Bit 22 : Pin 22. */
emilmont	80:8e73be2a2ac1	1712	#define GPIO_OUTCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
emilmont	80:8e73be2a2ac1	1713	#define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
emilmont	80:8e73be2a2ac1	1714	#define GPIO_OUTCLR_PIN22_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1715	#define GPIO_OUTCLR_PIN22_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1716	#define GPIO_OUTCLR_PIN22_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1717
emilmont	80:8e73be2a2ac1	1718	/* Bit 21 : Pin 21. */
emilmont	80:8e73be2a2ac1	1719	#define GPIO_OUTCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
emilmont	80:8e73be2a2ac1	1720	#define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
emilmont	80:8e73be2a2ac1	1721	#define GPIO_OUTCLR_PIN21_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1722	#define GPIO_OUTCLR_PIN21_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1723	#define GPIO_OUTCLR_PIN21_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1724
emilmont	80:8e73be2a2ac1	1725	/* Bit 20 : Pin 20. */
emilmont	80:8e73be2a2ac1	1726	#define GPIO_OUTCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
emilmont	80:8e73be2a2ac1	1727	#define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
emilmont	80:8e73be2a2ac1	1728	#define GPIO_OUTCLR_PIN20_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1729	#define GPIO_OUTCLR_PIN20_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1730	#define GPIO_OUTCLR_PIN20_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1731
emilmont	80:8e73be2a2ac1	1732	/* Bit 19 : Pin 19. */
emilmont	80:8e73be2a2ac1	1733	#define GPIO_OUTCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
emilmont	80:8e73be2a2ac1	1734	#define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
emilmont	80:8e73be2a2ac1	1735	#define GPIO_OUTCLR_PIN19_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1736	#define GPIO_OUTCLR_PIN19_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1737	#define GPIO_OUTCLR_PIN19_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1738
emilmont	80:8e73be2a2ac1	1739	/* Bit 18 : Pin 18. */
emilmont	80:8e73be2a2ac1	1740	#define GPIO_OUTCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
emilmont	80:8e73be2a2ac1	1741	#define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
emilmont	80:8e73be2a2ac1	1742	#define GPIO_OUTCLR_PIN18_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1743	#define GPIO_OUTCLR_PIN18_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1744	#define GPIO_OUTCLR_PIN18_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1745
emilmont	80:8e73be2a2ac1	1746	/* Bit 17 : Pin 17. */
emilmont	80:8e73be2a2ac1	1747	#define GPIO_OUTCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
emilmont	80:8e73be2a2ac1	1748	#define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
emilmont	80:8e73be2a2ac1	1749	#define GPIO_OUTCLR_PIN17_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1750	#define GPIO_OUTCLR_PIN17_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1751	#define GPIO_OUTCLR_PIN17_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1752
emilmont	80:8e73be2a2ac1	1753	/* Bit 16 : Pin 16. */
emilmont	80:8e73be2a2ac1	1754	#define GPIO_OUTCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
emilmont	80:8e73be2a2ac1	1755	#define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
emilmont	80:8e73be2a2ac1	1756	#define GPIO_OUTCLR_PIN16_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1757	#define GPIO_OUTCLR_PIN16_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1758	#define GPIO_OUTCLR_PIN16_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1759
emilmont	80:8e73be2a2ac1	1760	/* Bit 15 : Pin 15. */
emilmont	80:8e73be2a2ac1	1761	#define GPIO_OUTCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
emilmont	80:8e73be2a2ac1	1762	#define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
emilmont	80:8e73be2a2ac1	1763	#define GPIO_OUTCLR_PIN15_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1764	#define GPIO_OUTCLR_PIN15_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1765	#define GPIO_OUTCLR_PIN15_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1766
emilmont	80:8e73be2a2ac1	1767	/* Bit 14 : Pin 14. */
emilmont	80:8e73be2a2ac1	1768	#define GPIO_OUTCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
emilmont	80:8e73be2a2ac1	1769	#define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
emilmont	80:8e73be2a2ac1	1770	#define GPIO_OUTCLR_PIN14_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1771	#define GPIO_OUTCLR_PIN14_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1772	#define GPIO_OUTCLR_PIN14_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1773
emilmont	80:8e73be2a2ac1	1774	/* Bit 13 : Pin 13. */
emilmont	80:8e73be2a2ac1	1775	#define GPIO_OUTCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
emilmont	80:8e73be2a2ac1	1776	#define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
emilmont	80:8e73be2a2ac1	1777	#define GPIO_OUTCLR_PIN13_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1778	#define GPIO_OUTCLR_PIN13_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1779	#define GPIO_OUTCLR_PIN13_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1780
emilmont	80:8e73be2a2ac1	1781	/* Bit 12 : Pin 12. */
emilmont	80:8e73be2a2ac1	1782	#define GPIO_OUTCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
emilmont	80:8e73be2a2ac1	1783	#define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
emilmont	80:8e73be2a2ac1	1784	#define GPIO_OUTCLR_PIN12_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1785	#define GPIO_OUTCLR_PIN12_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1786	#define GPIO_OUTCLR_PIN12_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1787
emilmont	80:8e73be2a2ac1	1788	/* Bit 11 : Pin 11. */
emilmont	80:8e73be2a2ac1	1789	#define GPIO_OUTCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
emilmont	80:8e73be2a2ac1	1790	#define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
emilmont	80:8e73be2a2ac1	1791	#define GPIO_OUTCLR_PIN11_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1792	#define GPIO_OUTCLR_PIN11_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1793	#define GPIO_OUTCLR_PIN11_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1794
emilmont	80:8e73be2a2ac1	1795	/* Bit 10 : Pin 10. */
emilmont	80:8e73be2a2ac1	1796	#define GPIO_OUTCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
emilmont	80:8e73be2a2ac1	1797	#define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
emilmont	80:8e73be2a2ac1	1798	#define GPIO_OUTCLR_PIN10_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1799	#define GPIO_OUTCLR_PIN10_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1800	#define GPIO_OUTCLR_PIN10_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1801
emilmont	80:8e73be2a2ac1	1802	/* Bit 9 : Pin 9. */
emilmont	80:8e73be2a2ac1	1803	#define GPIO_OUTCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
emilmont	80:8e73be2a2ac1	1804	#define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
emilmont	80:8e73be2a2ac1	1805	#define GPIO_OUTCLR_PIN9_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1806	#define GPIO_OUTCLR_PIN9_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1807	#define GPIO_OUTCLR_PIN9_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1808
emilmont	80:8e73be2a2ac1	1809	/* Bit 8 : Pin 8. */
emilmont	80:8e73be2a2ac1	1810	#define GPIO_OUTCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
emilmont	80:8e73be2a2ac1	1811	#define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
emilmont	80:8e73be2a2ac1	1812	#define GPIO_OUTCLR_PIN8_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1813	#define GPIO_OUTCLR_PIN8_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1814	#define GPIO_OUTCLR_PIN8_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1815
emilmont	80:8e73be2a2ac1	1816	/* Bit 7 : Pin 7. */
emilmont	80:8e73be2a2ac1	1817	#define GPIO_OUTCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
emilmont	80:8e73be2a2ac1	1818	#define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
emilmont	80:8e73be2a2ac1	1819	#define GPIO_OUTCLR_PIN7_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1820	#define GPIO_OUTCLR_PIN7_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1821	#define GPIO_OUTCLR_PIN7_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1822
emilmont	80:8e73be2a2ac1	1823	/* Bit 6 : Pin 6. */
emilmont	80:8e73be2a2ac1	1824	#define GPIO_OUTCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
emilmont	80:8e73be2a2ac1	1825	#define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
emilmont	80:8e73be2a2ac1	1826	#define GPIO_OUTCLR_PIN6_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1827	#define GPIO_OUTCLR_PIN6_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1828	#define GPIO_OUTCLR_PIN6_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1829
emilmont	80:8e73be2a2ac1	1830	/* Bit 5 : Pin 5. */
emilmont	80:8e73be2a2ac1	1831	#define GPIO_OUTCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
emilmont	80:8e73be2a2ac1	1832	#define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
emilmont	80:8e73be2a2ac1	1833	#define GPIO_OUTCLR_PIN5_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1834	#define GPIO_OUTCLR_PIN5_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1835	#define GPIO_OUTCLR_PIN5_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1836
emilmont	80:8e73be2a2ac1	1837	/* Bit 4 : Pin 4. */
emilmont	80:8e73be2a2ac1	1838	#define GPIO_OUTCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
emilmont	80:8e73be2a2ac1	1839	#define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
emilmont	80:8e73be2a2ac1	1840	#define GPIO_OUTCLR_PIN4_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1841	#define GPIO_OUTCLR_PIN4_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1842	#define GPIO_OUTCLR_PIN4_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1843
emilmont	80:8e73be2a2ac1	1844	/* Bit 3 : Pin 3. */
emilmont	80:8e73be2a2ac1	1845	#define GPIO_OUTCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
emilmont	80:8e73be2a2ac1	1846	#define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
emilmont	80:8e73be2a2ac1	1847	#define GPIO_OUTCLR_PIN3_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1848	#define GPIO_OUTCLR_PIN3_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1849	#define GPIO_OUTCLR_PIN3_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1850
emilmont	80:8e73be2a2ac1	1851	/* Bit 2 : Pin 2. */
emilmont	80:8e73be2a2ac1	1852	#define GPIO_OUTCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
emilmont	80:8e73be2a2ac1	1853	#define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
emilmont	80:8e73be2a2ac1	1854	#define GPIO_OUTCLR_PIN2_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1855	#define GPIO_OUTCLR_PIN2_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1856	#define GPIO_OUTCLR_PIN2_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1857
emilmont	80:8e73be2a2ac1	1858	/* Bit 1 : Pin 1. */
emilmont	80:8e73be2a2ac1	1859	#define GPIO_OUTCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
emilmont	80:8e73be2a2ac1	1860	#define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
emilmont	80:8e73be2a2ac1	1861	#define GPIO_OUTCLR_PIN1_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1862	#define GPIO_OUTCLR_PIN1_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1863	#define GPIO_OUTCLR_PIN1_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1864
emilmont	80:8e73be2a2ac1	1865	/* Bit 0 : Pin 0. */
emilmont	80:8e73be2a2ac1	1866	#define GPIO_OUTCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
emilmont	80:8e73be2a2ac1	1867	#define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
emilmont	80:8e73be2a2ac1	1868	#define GPIO_OUTCLR_PIN0_Low (0UL) /!< Pin driver is low. /
emilmont	80:8e73be2a2ac1	1869	#define GPIO_OUTCLR_PIN0_High (1UL) /!< Pin driver is high. /
emilmont	80:8e73be2a2ac1	1870	#define GPIO_OUTCLR_PIN0_Clear (1UL) /!< Set pin driver low. /
emilmont	80:8e73be2a2ac1	1871
emilmont	80:8e73be2a2ac1	1872	/* Register: GPIO_IN */
emilmont	80:8e73be2a2ac1	1873	/* Description: Read GPIO port. */
emilmont	80:8e73be2a2ac1	1874
emilmont	80:8e73be2a2ac1	1875	/* Bit 31 : Pin 31. */
emilmont	80:8e73be2a2ac1	1876	#define GPIO_IN_PIN31_Pos (31UL) /!< Position of PIN31 field. /
emilmont	80:8e73be2a2ac1	1877	#define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /!< Bit mask of PIN31 field. /
emilmont	80:8e73be2a2ac1	1878	#define GPIO_IN_PIN31_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1879	#define GPIO_IN_PIN31_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1880
emilmont	80:8e73be2a2ac1	1881	/* Bit 30 : Pin 30. */
emilmont	80:8e73be2a2ac1	1882	#define GPIO_IN_PIN30_Pos (30UL) /!< Position of PIN30 field. /
emilmont	80:8e73be2a2ac1	1883	#define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /!< Bit mask of PIN30 field. /
emilmont	80:8e73be2a2ac1	1884	#define GPIO_IN_PIN30_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1885	#define GPIO_IN_PIN30_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1886
emilmont	80:8e73be2a2ac1	1887	/* Bit 29 : Pin 29. */
emilmont	80:8e73be2a2ac1	1888	#define GPIO_IN_PIN29_Pos (29UL) /!< Position of PIN29 field. /
emilmont	80:8e73be2a2ac1	1889	#define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /!< Bit mask of PIN29 field. /
emilmont	80:8e73be2a2ac1	1890	#define GPIO_IN_PIN29_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1891	#define GPIO_IN_PIN29_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1892
emilmont	80:8e73be2a2ac1	1893	/* Bit 28 : Pin 28. */
emilmont	80:8e73be2a2ac1	1894	#define GPIO_IN_PIN28_Pos (28UL) /!< Position of PIN28 field. /
emilmont	80:8e73be2a2ac1	1895	#define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /!< Bit mask of PIN28 field. /
emilmont	80:8e73be2a2ac1	1896	#define GPIO_IN_PIN28_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1897	#define GPIO_IN_PIN28_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1898
emilmont	80:8e73be2a2ac1	1899	/* Bit 27 : Pin 27. */
emilmont	80:8e73be2a2ac1	1900	#define GPIO_IN_PIN27_Pos (27UL) /!< Position of PIN27 field. /
emilmont	80:8e73be2a2ac1	1901	#define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /!< Bit mask of PIN27 field. /
emilmont	80:8e73be2a2ac1	1902	#define GPIO_IN_PIN27_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1903	#define GPIO_IN_PIN27_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1904
emilmont	80:8e73be2a2ac1	1905	/* Bit 26 : Pin 26. */
emilmont	80:8e73be2a2ac1	1906	#define GPIO_IN_PIN26_Pos (26UL) /!< Position of PIN26 field. /
emilmont	80:8e73be2a2ac1	1907	#define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /!< Bit mask of PIN26 field. /
emilmont	80:8e73be2a2ac1	1908	#define GPIO_IN_PIN26_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1909	#define GPIO_IN_PIN26_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1910
emilmont	80:8e73be2a2ac1	1911	/* Bit 25 : Pin 25. */
emilmont	80:8e73be2a2ac1	1912	#define GPIO_IN_PIN25_Pos (25UL) /!< Position of PIN25 field. /
emilmont	80:8e73be2a2ac1	1913	#define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /!< Bit mask of PIN25 field. /
emilmont	80:8e73be2a2ac1	1914	#define GPIO_IN_PIN25_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1915	#define GPIO_IN_PIN25_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1916
emilmont	80:8e73be2a2ac1	1917	/* Bit 24 : Pin 24. */
emilmont	80:8e73be2a2ac1	1918	#define GPIO_IN_PIN24_Pos (24UL) /!< Position of PIN24 field. /
emilmont	80:8e73be2a2ac1	1919	#define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /!< Bit mask of PIN24 field. /
emilmont	80:8e73be2a2ac1	1920	#define GPIO_IN_PIN24_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1921	#define GPIO_IN_PIN24_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1922
emilmont	80:8e73be2a2ac1	1923	/* Bit 23 : Pin 23. */
emilmont	80:8e73be2a2ac1	1924	#define GPIO_IN_PIN23_Pos (23UL) /!< Position of PIN23 field. /
emilmont	80:8e73be2a2ac1	1925	#define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /!< Bit mask of PIN23 field. /
emilmont	80:8e73be2a2ac1	1926	#define GPIO_IN_PIN23_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1927	#define GPIO_IN_PIN23_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1928
emilmont	80:8e73be2a2ac1	1929	/* Bit 22 : Pin 22. */
emilmont	80:8e73be2a2ac1	1930	#define GPIO_IN_PIN22_Pos (22UL) /!< Position of PIN22 field. /
emilmont	80:8e73be2a2ac1	1931	#define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /!< Bit mask of PIN22 field. /
emilmont	80:8e73be2a2ac1	1932	#define GPIO_IN_PIN22_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1933	#define GPIO_IN_PIN22_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1934
emilmont	80:8e73be2a2ac1	1935	/* Bit 21 : Pin 21. */
emilmont	80:8e73be2a2ac1	1936	#define GPIO_IN_PIN21_Pos (21UL) /!< Position of PIN21 field. /
emilmont	80:8e73be2a2ac1	1937	#define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /!< Bit mask of PIN21 field. /
emilmont	80:8e73be2a2ac1	1938	#define GPIO_IN_PIN21_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1939	#define GPIO_IN_PIN21_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1940
emilmont	80:8e73be2a2ac1	1941	/* Bit 20 : Pin 20. */
emilmont	80:8e73be2a2ac1	1942	#define GPIO_IN_PIN20_Pos (20UL) /!< Position of PIN20 field. /
emilmont	80:8e73be2a2ac1	1943	#define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /!< Bit mask of PIN20 field. /
emilmont	80:8e73be2a2ac1	1944	#define GPIO_IN_PIN20_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1945	#define GPIO_IN_PIN20_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1946
emilmont	80:8e73be2a2ac1	1947	/* Bit 19 : Pin 19. */
emilmont	80:8e73be2a2ac1	1948	#define GPIO_IN_PIN19_Pos (19UL) /!< Position of PIN19 field. /
emilmont	80:8e73be2a2ac1	1949	#define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /!< Bit mask of PIN19 field. /
emilmont	80:8e73be2a2ac1	1950	#define GPIO_IN_PIN19_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1951	#define GPIO_IN_PIN19_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1952
emilmont	80:8e73be2a2ac1	1953	/* Bit 18 : Pin 18. */
emilmont	80:8e73be2a2ac1	1954	#define GPIO_IN_PIN18_Pos (18UL) /!< Position of PIN18 field. /
emilmont	80:8e73be2a2ac1	1955	#define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /!< Bit mask of PIN18 field. /
emilmont	80:8e73be2a2ac1	1956	#define GPIO_IN_PIN18_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1957	#define GPIO_IN_PIN18_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1958
emilmont	80:8e73be2a2ac1	1959	/* Bit 17 : Pin 17. */
emilmont	80:8e73be2a2ac1	1960	#define GPIO_IN_PIN17_Pos (17UL) /!< Position of PIN17 field. /
emilmont	80:8e73be2a2ac1	1961	#define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /!< Bit mask of PIN17 field. /
emilmont	80:8e73be2a2ac1	1962	#define GPIO_IN_PIN17_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1963	#define GPIO_IN_PIN17_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1964
emilmont	80:8e73be2a2ac1	1965	/* Bit 16 : Pin 16. */
emilmont	80:8e73be2a2ac1	1966	#define GPIO_IN_PIN16_Pos (16UL) /!< Position of PIN16 field. /
emilmont	80:8e73be2a2ac1	1967	#define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /!< Bit mask of PIN16 field. /
emilmont	80:8e73be2a2ac1	1968	#define GPIO_IN_PIN16_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1969	#define GPIO_IN_PIN16_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1970
emilmont	80:8e73be2a2ac1	1971	/* Bit 15 : Pin 15. */
emilmont	80:8e73be2a2ac1	1972	#define GPIO_IN_PIN15_Pos (15UL) /!< Position of PIN15 field. /
emilmont	80:8e73be2a2ac1	1973	#define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /!< Bit mask of PIN15 field. /
emilmont	80:8e73be2a2ac1	1974	#define GPIO_IN_PIN15_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1975	#define GPIO_IN_PIN15_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1976
emilmont	80:8e73be2a2ac1	1977	/* Bit 14 : Pin 14. */
emilmont	80:8e73be2a2ac1	1978	#define GPIO_IN_PIN14_Pos (14UL) /!< Position of PIN14 field. /
emilmont	80:8e73be2a2ac1	1979	#define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /!< Bit mask of PIN14 field. /
emilmont	80:8e73be2a2ac1	1980	#define GPIO_IN_PIN14_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1981	#define GPIO_IN_PIN14_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1982
emilmont	80:8e73be2a2ac1	1983	/* Bit 13 : Pin 13. */
emilmont	80:8e73be2a2ac1	1984	#define GPIO_IN_PIN13_Pos (13UL) /!< Position of PIN13 field. /
emilmont	80:8e73be2a2ac1	1985	#define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /!< Bit mask of PIN13 field. /
emilmont	80:8e73be2a2ac1	1986	#define GPIO_IN_PIN13_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1987	#define GPIO_IN_PIN13_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1988
emilmont	80:8e73be2a2ac1	1989	/* Bit 12 : Pin 12. */
emilmont	80:8e73be2a2ac1	1990	#define GPIO_IN_PIN12_Pos (12UL) /!< Position of PIN12 field. /
emilmont	80:8e73be2a2ac1	1991	#define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /!< Bit mask of PIN12 field. /
emilmont	80:8e73be2a2ac1	1992	#define GPIO_IN_PIN12_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1993	#define GPIO_IN_PIN12_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	1994
emilmont	80:8e73be2a2ac1	1995	/* Bit 11 : Pin 11. */
emilmont	80:8e73be2a2ac1	1996	#define GPIO_IN_PIN11_Pos (11UL) /!< Position of PIN11 field. /
emilmont	80:8e73be2a2ac1	1997	#define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /!< Bit mask of PIN11 field. /
emilmont	80:8e73be2a2ac1	1998	#define GPIO_IN_PIN11_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	1999	#define GPIO_IN_PIN11_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2000
emilmont	80:8e73be2a2ac1	2001	/* Bit 10 : Pin 10. */
emilmont	80:8e73be2a2ac1	2002	#define GPIO_IN_PIN10_Pos (10UL) /!< Position of PIN10 field. /
emilmont	80:8e73be2a2ac1	2003	#define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /!< Bit mask of PIN10 field. /
emilmont	80:8e73be2a2ac1	2004	#define GPIO_IN_PIN10_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2005	#define GPIO_IN_PIN10_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2006
emilmont	80:8e73be2a2ac1	2007	/* Bit 9 : Pin 9. */
emilmont	80:8e73be2a2ac1	2008	#define GPIO_IN_PIN9_Pos (9UL) /!< Position of PIN9 field. /
emilmont	80:8e73be2a2ac1	2009	#define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /!< Bit mask of PIN9 field. /
emilmont	80:8e73be2a2ac1	2010	#define GPIO_IN_PIN9_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2011	#define GPIO_IN_PIN9_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2012
emilmont	80:8e73be2a2ac1	2013	/* Bit 8 : Pin 8. */
emilmont	80:8e73be2a2ac1	2014	#define GPIO_IN_PIN8_Pos (8UL) /!< Position of PIN8 field. /
emilmont	80:8e73be2a2ac1	2015	#define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /!< Bit mask of PIN8 field. /
emilmont	80:8e73be2a2ac1	2016	#define GPIO_IN_PIN8_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2017	#define GPIO_IN_PIN8_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2018
emilmont	80:8e73be2a2ac1	2019	/* Bit 7 : Pin 7. */
emilmont	80:8e73be2a2ac1	2020	#define GPIO_IN_PIN7_Pos (7UL) /!< Position of PIN7 field. /
emilmont	80:8e73be2a2ac1	2021	#define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /!< Bit mask of PIN7 field. /
emilmont	80:8e73be2a2ac1	2022	#define GPIO_IN_PIN7_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2023	#define GPIO_IN_PIN7_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2024
emilmont	80:8e73be2a2ac1	2025	/* Bit 6 : Pin 6. */
emilmont	80:8e73be2a2ac1	2026	#define GPIO_IN_PIN6_Pos (6UL) /!< Position of PIN6 field. /
emilmont	80:8e73be2a2ac1	2027	#define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /!< Bit mask of PIN6 field. /
emilmont	80:8e73be2a2ac1	2028	#define GPIO_IN_PIN6_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2029	#define GPIO_IN_PIN6_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2030
emilmont	80:8e73be2a2ac1	2031	/* Bit 5 : Pin 5. */
emilmont	80:8e73be2a2ac1	2032	#define GPIO_IN_PIN5_Pos (5UL) /!< Position of PIN5 field. /
emilmont	80:8e73be2a2ac1	2033	#define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /!< Bit mask of PIN5 field. /
emilmont	80:8e73be2a2ac1	2034	#define GPIO_IN_PIN5_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2035	#define GPIO_IN_PIN5_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2036
emilmont	80:8e73be2a2ac1	2037	/* Bit 4 : Pin 4. */
emilmont	80:8e73be2a2ac1	2038	#define GPIO_IN_PIN4_Pos (4UL) /!< Position of PIN4 field. /
emilmont	80:8e73be2a2ac1	2039	#define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /!< Bit mask of PIN4 field. /
emilmont	80:8e73be2a2ac1	2040	#define GPIO_IN_PIN4_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2041	#define GPIO_IN_PIN4_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2042
emilmont	80:8e73be2a2ac1	2043	/* Bit 3 : Pin 3. */
emilmont	80:8e73be2a2ac1	2044	#define GPIO_IN_PIN3_Pos (3UL) /!< Position of PIN3 field. /
emilmont	80:8e73be2a2ac1	2045	#define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /!< Bit mask of PIN3 field. /
emilmont	80:8e73be2a2ac1	2046	#define GPIO_IN_PIN3_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2047	#define GPIO_IN_PIN3_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2048
emilmont	80:8e73be2a2ac1	2049	/* Bit 2 : Pin 2. */
emilmont	80:8e73be2a2ac1	2050	#define GPIO_IN_PIN2_Pos (2UL) /!< Position of PIN2 field. /
emilmont	80:8e73be2a2ac1	2051	#define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /!< Bit mask of PIN2 field. /
emilmont	80:8e73be2a2ac1	2052	#define GPIO_IN_PIN2_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2053	#define GPIO_IN_PIN2_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2054
emilmont	80:8e73be2a2ac1	2055	/* Bit 1 : Pin 1. */
emilmont	80:8e73be2a2ac1	2056	#define GPIO_IN_PIN1_Pos (1UL) /!< Position of PIN1 field. /
emilmont	80:8e73be2a2ac1	2057	#define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /!< Bit mask of PIN1 field. /
emilmont	80:8e73be2a2ac1	2058	#define GPIO_IN_PIN1_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2059	#define GPIO_IN_PIN1_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2060
emilmont	80:8e73be2a2ac1	2061	/* Bit 0 : Pin 0. */
emilmont	80:8e73be2a2ac1	2062	#define GPIO_IN_PIN0_Pos (0UL) /!< Position of PIN0 field. /
emilmont	80:8e73be2a2ac1	2063	#define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /!< Bit mask of PIN0 field. /
emilmont	80:8e73be2a2ac1	2064	#define GPIO_IN_PIN0_Low (0UL) /!< Pin input is low. /
emilmont	80:8e73be2a2ac1	2065	#define GPIO_IN_PIN0_High (1UL) /!< Pin input is high. /
emilmont	80:8e73be2a2ac1	2066
emilmont	80:8e73be2a2ac1	2067	/* Register: GPIO_DIR */
emilmont	80:8e73be2a2ac1	2068	/* Description: Direction of GPIO pins. */
emilmont	80:8e73be2a2ac1	2069
emilmont	80:8e73be2a2ac1	2070	/* Bit 31 : Pin 31. */
emilmont	80:8e73be2a2ac1	2071	#define GPIO_DIR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
emilmont	80:8e73be2a2ac1	2072	#define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /!< Bit mask of PIN31 field. /
emilmont	80:8e73be2a2ac1	2073	#define GPIO_DIR_PIN31_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2074	#define GPIO_DIR_PIN31_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2075
emilmont	80:8e73be2a2ac1	2076	/* Bit 30 : Pin 30. */
emilmont	80:8e73be2a2ac1	2077	#define GPIO_DIR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
emilmont	80:8e73be2a2ac1	2078	#define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /!< Bit mask of PIN30 field. /
emilmont	80:8e73be2a2ac1	2079	#define GPIO_DIR_PIN30_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2080	#define GPIO_DIR_PIN30_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2081
emilmont	80:8e73be2a2ac1	2082	/* Bit 29 : Pin 29. */
emilmont	80:8e73be2a2ac1	2083	#define GPIO_DIR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
emilmont	80:8e73be2a2ac1	2084	#define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /!< Bit mask of PIN29 field. /
emilmont	80:8e73be2a2ac1	2085	#define GPIO_DIR_PIN29_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2086	#define GPIO_DIR_PIN29_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2087
emilmont	80:8e73be2a2ac1	2088	/* Bit 28 : Pin 28. */
emilmont	80:8e73be2a2ac1	2089	#define GPIO_DIR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
emilmont	80:8e73be2a2ac1	2090	#define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /!< Bit mask of PIN28 field. /
emilmont	80:8e73be2a2ac1	2091	#define GPIO_DIR_PIN28_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2092	#define GPIO_DIR_PIN28_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2093
emilmont	80:8e73be2a2ac1	2094	/* Bit 27 : Pin 27. */
emilmont	80:8e73be2a2ac1	2095	#define GPIO_DIR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
emilmont	80:8e73be2a2ac1	2096	#define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /!< Bit mask of PIN27 field. /
emilmont	80:8e73be2a2ac1	2097	#define GPIO_DIR_PIN27_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2098	#define GPIO_DIR_PIN27_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2099
emilmont	80:8e73be2a2ac1	2100	/* Bit 26 : Pin 26. */
emilmont	80:8e73be2a2ac1	2101	#define GPIO_DIR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
emilmont	80:8e73be2a2ac1	2102	#define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /!< Bit mask of PIN26 field. /
emilmont	80:8e73be2a2ac1	2103	#define GPIO_DIR_PIN26_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2104	#define GPIO_DIR_PIN26_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2105
emilmont	80:8e73be2a2ac1	2106	/* Bit 25 : Pin 25. */
emilmont	80:8e73be2a2ac1	2107	#define GPIO_DIR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
emilmont	80:8e73be2a2ac1	2108	#define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /!< Bit mask of PIN25 field. /
emilmont	80:8e73be2a2ac1	2109	#define GPIO_DIR_PIN25_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2110	#define GPIO_DIR_PIN25_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2111
emilmont	80:8e73be2a2ac1	2112	/* Bit 24 : Pin 24. */
emilmont	80:8e73be2a2ac1	2113	#define GPIO_DIR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
emilmont	80:8e73be2a2ac1	2114	#define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /!< Bit mask of PIN24 field. /
emilmont	80:8e73be2a2ac1	2115	#define GPIO_DIR_PIN24_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2116	#define GPIO_DIR_PIN24_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2117
emilmont	80:8e73be2a2ac1	2118	/* Bit 23 : Pin 23. */
emilmont	80:8e73be2a2ac1	2119	#define GPIO_DIR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
emilmont	80:8e73be2a2ac1	2120	#define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /!< Bit mask of PIN23 field. /
emilmont	80:8e73be2a2ac1	2121	#define GPIO_DIR_PIN23_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2122	#define GPIO_DIR_PIN23_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2123
emilmont	80:8e73be2a2ac1	2124	/* Bit 22 : Pin 22. */
emilmont	80:8e73be2a2ac1	2125	#define GPIO_DIR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
emilmont	80:8e73be2a2ac1	2126	#define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /!< Bit mask of PIN22 field. /
emilmont	80:8e73be2a2ac1	2127	#define GPIO_DIR_PIN22_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2128	#define GPIO_DIR_PIN22_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2129
emilmont	80:8e73be2a2ac1	2130	/* Bit 21 : Pin 21. */
emilmont	80:8e73be2a2ac1	2131	#define GPIO_DIR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
emilmont	80:8e73be2a2ac1	2132	#define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /!< Bit mask of PIN21 field. /
emilmont	80:8e73be2a2ac1	2133	#define GPIO_DIR_PIN21_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2134	#define GPIO_DIR_PIN21_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2135
emilmont	80:8e73be2a2ac1	2136	/* Bit 20 : Pin 20. */
emilmont	80:8e73be2a2ac1	2137	#define GPIO_DIR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
emilmont	80:8e73be2a2ac1	2138	#define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /!< Bit mask of PIN20 field. /
emilmont	80:8e73be2a2ac1	2139	#define GPIO_DIR_PIN20_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2140	#define GPIO_DIR_PIN20_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2141
emilmont	80:8e73be2a2ac1	2142	/* Bit 19 : Pin 19. */
emilmont	80:8e73be2a2ac1	2143	#define GPIO_DIR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
emilmont	80:8e73be2a2ac1	2144	#define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /!< Bit mask of PIN19 field. /
emilmont	80:8e73be2a2ac1	2145	#define GPIO_DIR_PIN19_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2146	#define GPIO_DIR_PIN19_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2147
emilmont	80:8e73be2a2ac1	2148	/* Bit 18 : Pin 18. */
emilmont	80:8e73be2a2ac1	2149	#define GPIO_DIR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
emilmont	80:8e73be2a2ac1	2150	#define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /!< Bit mask of PIN18 field. /
emilmont	80:8e73be2a2ac1	2151	#define GPIO_DIR_PIN18_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2152	#define GPIO_DIR_PIN18_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2153
emilmont	80:8e73be2a2ac1	2154	/* Bit 17 : Pin 17. */
emilmont	80:8e73be2a2ac1	2155	#define GPIO_DIR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
emilmont	80:8e73be2a2ac1	2156	#define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /!< Bit mask of PIN17 field. /
emilmont	80:8e73be2a2ac1	2157	#define GPIO_DIR_PIN17_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2158	#define GPIO_DIR_PIN17_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2159
emilmont	80:8e73be2a2ac1	2160	/* Bit 16 : Pin 16. */
emilmont	80:8e73be2a2ac1	2161	#define GPIO_DIR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
emilmont	80:8e73be2a2ac1	2162	#define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /!< Bit mask of PIN16 field. /
emilmont	80:8e73be2a2ac1	2163	#define GPIO_DIR_PIN16_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2164	#define GPIO_DIR_PIN16_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2165
emilmont	80:8e73be2a2ac1	2166	/* Bit 15 : Pin 15. */
emilmont	80:8e73be2a2ac1	2167	#define GPIO_DIR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
emilmont	80:8e73be2a2ac1	2168	#define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /!< Bit mask of PIN15 field. /
emilmont	80:8e73be2a2ac1	2169	#define GPIO_DIR_PIN15_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2170	#define GPIO_DIR_PIN15_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2171
emilmont	80:8e73be2a2ac1	2172	/* Bit 14 : Pin 14. */
emilmont	80:8e73be2a2ac1	2173	#define GPIO_DIR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
emilmont	80:8e73be2a2ac1	2174	#define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /!< Bit mask of PIN14 field. /
emilmont	80:8e73be2a2ac1	2175	#define GPIO_DIR_PIN14_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2176	#define GPIO_DIR_PIN14_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2177
emilmont	80:8e73be2a2ac1	2178	/* Bit 13 : Pin 13. */
emilmont	80:8e73be2a2ac1	2179	#define GPIO_DIR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
emilmont	80:8e73be2a2ac1	2180	#define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /!< Bit mask of PIN13 field. /
emilmont	80:8e73be2a2ac1	2181	#define GPIO_DIR_PIN13_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2182	#define GPIO_DIR_PIN13_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2183
emilmont	80:8e73be2a2ac1	2184	/* Bit 12 : Pin 12. */
emilmont	80:8e73be2a2ac1	2185	#define GPIO_DIR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
emilmont	80:8e73be2a2ac1	2186	#define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /!< Bit mask of PIN12 field. /
emilmont	80:8e73be2a2ac1	2187	#define GPIO_DIR_PIN12_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2188	#define GPIO_DIR_PIN12_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2189
emilmont	80:8e73be2a2ac1	2190	/* Bit 11 : Pin 11. */
emilmont	80:8e73be2a2ac1	2191	#define GPIO_DIR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
emilmont	80:8e73be2a2ac1	2192	#define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /!< Bit mask of PIN11 field. /
emilmont	80:8e73be2a2ac1	2193	#define GPIO_DIR_PIN11_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2194	#define GPIO_DIR_PIN11_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2195
emilmont	80:8e73be2a2ac1	2196	/* Bit 10 : Pin 10. */
emilmont	80:8e73be2a2ac1	2197	#define GPIO_DIR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
emilmont	80:8e73be2a2ac1	2198	#define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /!< Bit mask of PIN10 field. /
emilmont	80:8e73be2a2ac1	2199	#define GPIO_DIR_PIN10_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2200	#define GPIO_DIR_PIN10_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2201
emilmont	80:8e73be2a2ac1	2202	/* Bit 9 : Pin 9. */
emilmont	80:8e73be2a2ac1	2203	#define GPIO_DIR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
emilmont	80:8e73be2a2ac1	2204	#define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /!< Bit mask of PIN9 field. /
emilmont	80:8e73be2a2ac1	2205	#define GPIO_DIR_PIN9_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2206	#define GPIO_DIR_PIN9_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2207
emilmont	80:8e73be2a2ac1	2208	/* Bit 8 : Pin 8. */
emilmont	80:8e73be2a2ac1	2209	#define GPIO_DIR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
emilmont	80:8e73be2a2ac1	2210	#define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /!< Bit mask of PIN8 field. /
emilmont	80:8e73be2a2ac1	2211	#define GPIO_DIR_PIN8_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2212	#define GPIO_DIR_PIN8_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2213
emilmont	80:8e73be2a2ac1	2214	/* Bit 7 : Pin 7. */
emilmont	80:8e73be2a2ac1	2215	#define GPIO_DIR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
emilmont	80:8e73be2a2ac1	2216	#define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /!< Bit mask of PIN7 field. /
emilmont	80:8e73be2a2ac1	2217	#define GPIO_DIR_PIN7_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2218	#define GPIO_DIR_PIN7_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2219
emilmont	80:8e73be2a2ac1	2220	/* Bit 6 : Pin 6. */
emilmont	80:8e73be2a2ac1	2221	#define GPIO_DIR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
emilmont	80:8e73be2a2ac1	2222	#define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /!< Bit mask of PIN6 field. /
emilmont	80:8e73be2a2ac1	2223	#define GPIO_DIR_PIN6_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2224	#define GPIO_DIR_PIN6_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2225
emilmont	80:8e73be2a2ac1	2226	/* Bit 5 : Pin 5. */
emilmont	80:8e73be2a2ac1	2227	#define GPIO_DIR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
emilmont	80:8e73be2a2ac1	2228	#define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /!< Bit mask of PIN5 field. /
emilmont	80:8e73be2a2ac1	2229	#define GPIO_DIR_PIN5_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2230	#define GPIO_DIR_PIN5_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2231
emilmont	80:8e73be2a2ac1	2232	/* Bit 4 : Pin 4. */
emilmont	80:8e73be2a2ac1	2233	#define GPIO_DIR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
emilmont	80:8e73be2a2ac1	2234	#define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /!< Bit mask of PIN4 field. /
emilmont	80:8e73be2a2ac1	2235	#define GPIO_DIR_PIN4_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2236	#define GPIO_DIR_PIN4_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2237
emilmont	80:8e73be2a2ac1	2238	/* Bit 3 : Pin 3. */
emilmont	80:8e73be2a2ac1	2239	#define GPIO_DIR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
emilmont	80:8e73be2a2ac1	2240	#define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /!< Bit mask of PIN3 field. /
emilmont	80:8e73be2a2ac1	2241	#define GPIO_DIR_PIN3_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2242	#define GPIO_DIR_PIN3_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2243
emilmont	80:8e73be2a2ac1	2244	/* Bit 2 : Pin 2. */
emilmont	80:8e73be2a2ac1	2245	#define GPIO_DIR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
emilmont	80:8e73be2a2ac1	2246	#define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /!< Bit mask of PIN2 field. /
emilmont	80:8e73be2a2ac1	2247	#define GPIO_DIR_PIN2_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2248	#define GPIO_DIR_PIN2_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2249
emilmont	80:8e73be2a2ac1	2250	/* Bit 1 : Pin 1. */
emilmont	80:8e73be2a2ac1	2251	#define GPIO_DIR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
emilmont	80:8e73be2a2ac1	2252	#define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /!< Bit mask of PIN1 field. /
emilmont	80:8e73be2a2ac1	2253	#define GPIO_DIR_PIN1_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2254	#define GPIO_DIR_PIN1_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2255
emilmont	80:8e73be2a2ac1	2256	/* Bit 0 : Pin 0. */
emilmont	80:8e73be2a2ac1	2257	#define GPIO_DIR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
emilmont	80:8e73be2a2ac1	2258	#define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /!< Bit mask of PIN0 field. /
emilmont	80:8e73be2a2ac1	2259	#define GPIO_DIR_PIN0_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2260	#define GPIO_DIR_PIN0_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2261
emilmont	80:8e73be2a2ac1	2262	/* Register: GPIO_DIRSET */
emilmont	80:8e73be2a2ac1	2263	/* Description: DIR set register. */
emilmont	80:8e73be2a2ac1	2264
emilmont	80:8e73be2a2ac1	2265	/* Bit 31 : Set as output pin 31. */
emilmont	80:8e73be2a2ac1	2266	#define GPIO_DIRSET_PIN31_Pos (31UL) /!< Position of PIN31 field. /
emilmont	80:8e73be2a2ac1	2267	#define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /!< Bit mask of PIN31 field. /
emilmont	80:8e73be2a2ac1	2268	#define GPIO_DIRSET_PIN31_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2269	#define GPIO_DIRSET_PIN31_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2270	#define GPIO_DIRSET_PIN31_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2271
emilmont	80:8e73be2a2ac1	2272	/* Bit 30 : Set as output pin 30. */
emilmont	80:8e73be2a2ac1	2273	#define GPIO_DIRSET_PIN30_Pos (30UL) /!< Position of PIN30 field. /
emilmont	80:8e73be2a2ac1	2274	#define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /!< Bit mask of PIN30 field. /
emilmont	80:8e73be2a2ac1	2275	#define GPIO_DIRSET_PIN30_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2276	#define GPIO_DIRSET_PIN30_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2277	#define GPIO_DIRSET_PIN30_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2278
emilmont	80:8e73be2a2ac1	2279	/* Bit 29 : Set as output pin 29. */
emilmont	80:8e73be2a2ac1	2280	#define GPIO_DIRSET_PIN29_Pos (29UL) /!< Position of PIN29 field. /
emilmont	80:8e73be2a2ac1	2281	#define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /!< Bit mask of PIN29 field. /
emilmont	80:8e73be2a2ac1	2282	#define GPIO_DIRSET_PIN29_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2283	#define GPIO_DIRSET_PIN29_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2284	#define GPIO_DIRSET_PIN29_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2285
emilmont	80:8e73be2a2ac1	2286	/* Bit 28 : Set as output pin 28. */
emilmont	80:8e73be2a2ac1	2287	#define GPIO_DIRSET_PIN28_Pos (28UL) /!< Position of PIN28 field. /
emilmont	80:8e73be2a2ac1	2288	#define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /!< Bit mask of PIN28 field. /
emilmont	80:8e73be2a2ac1	2289	#define GPIO_DIRSET_PIN28_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2290	#define GPIO_DIRSET_PIN28_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2291	#define GPIO_DIRSET_PIN28_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2292
emilmont	80:8e73be2a2ac1	2293	/* Bit 27 : Set as output pin 27. */
emilmont	80:8e73be2a2ac1	2294	#define GPIO_DIRSET_PIN27_Pos (27UL) /!< Position of PIN27 field. /
emilmont	80:8e73be2a2ac1	2295	#define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /!< Bit mask of PIN27 field. /
emilmont	80:8e73be2a2ac1	2296	#define GPIO_DIRSET_PIN27_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2297	#define GPIO_DIRSET_PIN27_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2298	#define GPIO_DIRSET_PIN27_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2299
emilmont	80:8e73be2a2ac1	2300	/* Bit 26 : Set as output pin 26. */
emilmont	80:8e73be2a2ac1	2301	#define GPIO_DIRSET_PIN26_Pos (26UL) /!< Position of PIN26 field. /
emilmont	80:8e73be2a2ac1	2302	#define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /!< Bit mask of PIN26 field. /
emilmont	80:8e73be2a2ac1	2303	#define GPIO_DIRSET_PIN26_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2304	#define GPIO_DIRSET_PIN26_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2305	#define GPIO_DIRSET_PIN26_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2306
emilmont	80:8e73be2a2ac1	2307	/* Bit 25 : Set as output pin 25. */
emilmont	80:8e73be2a2ac1	2308	#define GPIO_DIRSET_PIN25_Pos (25UL) /!< Position of PIN25 field. /
emilmont	80:8e73be2a2ac1	2309	#define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /!< Bit mask of PIN25 field. /
emilmont	80:8e73be2a2ac1	2310	#define GPIO_DIRSET_PIN25_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2311	#define GPIO_DIRSET_PIN25_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2312	#define GPIO_DIRSET_PIN25_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2313
emilmont	80:8e73be2a2ac1	2314	/* Bit 24 : Set as output pin 24. */
emilmont	80:8e73be2a2ac1	2315	#define GPIO_DIRSET_PIN24_Pos (24UL) /!< Position of PIN24 field. /
emilmont	80:8e73be2a2ac1	2316	#define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /!< Bit mask of PIN24 field. /
emilmont	80:8e73be2a2ac1	2317	#define GPIO_DIRSET_PIN24_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2318	#define GPIO_DIRSET_PIN24_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2319	#define GPIO_DIRSET_PIN24_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2320
emilmont	80:8e73be2a2ac1	2321	/* Bit 23 : Set as output pin 23. */
emilmont	80:8e73be2a2ac1	2322	#define GPIO_DIRSET_PIN23_Pos (23UL) /!< Position of PIN23 field. /
emilmont	80:8e73be2a2ac1	2323	#define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /!< Bit mask of PIN23 field. /
emilmont	80:8e73be2a2ac1	2324	#define GPIO_DIRSET_PIN23_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2325	#define GPIO_DIRSET_PIN23_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2326	#define GPIO_DIRSET_PIN23_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2327
emilmont	80:8e73be2a2ac1	2328	/* Bit 22 : Set as output pin 22. */
emilmont	80:8e73be2a2ac1	2329	#define GPIO_DIRSET_PIN22_Pos (22UL) /!< Position of PIN22 field. /
emilmont	80:8e73be2a2ac1	2330	#define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /!< Bit mask of PIN22 field. /
emilmont	80:8e73be2a2ac1	2331	#define GPIO_DIRSET_PIN22_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2332	#define GPIO_DIRSET_PIN22_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2333	#define GPIO_DIRSET_PIN22_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2334
emilmont	80:8e73be2a2ac1	2335	/* Bit 21 : Set as output pin 21. */
emilmont	80:8e73be2a2ac1	2336	#define GPIO_DIRSET_PIN21_Pos (21UL) /!< Position of PIN21 field. /
emilmont	80:8e73be2a2ac1	2337	#define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /!< Bit mask of PIN21 field. /
emilmont	80:8e73be2a2ac1	2338	#define GPIO_DIRSET_PIN21_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2339	#define GPIO_DIRSET_PIN21_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2340	#define GPIO_DIRSET_PIN21_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2341
emilmont	80:8e73be2a2ac1	2342	/* Bit 20 : Set as output pin 20. */
emilmont	80:8e73be2a2ac1	2343	#define GPIO_DIRSET_PIN20_Pos (20UL) /!< Position of PIN20 field. /
emilmont	80:8e73be2a2ac1	2344	#define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /!< Bit mask of PIN20 field. /
emilmont	80:8e73be2a2ac1	2345	#define GPIO_DIRSET_PIN20_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2346	#define GPIO_DIRSET_PIN20_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2347	#define GPIO_DIRSET_PIN20_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2348
emilmont	80:8e73be2a2ac1	2349	/* Bit 19 : Set as output pin 19. */
emilmont	80:8e73be2a2ac1	2350	#define GPIO_DIRSET_PIN19_Pos (19UL) /!< Position of PIN19 field. /
emilmont	80:8e73be2a2ac1	2351	#define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /!< Bit mask of PIN19 field. /
emilmont	80:8e73be2a2ac1	2352	#define GPIO_DIRSET_PIN19_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2353	#define GPIO_DIRSET_PIN19_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2354	#define GPIO_DIRSET_PIN19_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2355
emilmont	80:8e73be2a2ac1	2356	/* Bit 18 : Set as output pin 18. */
emilmont	80:8e73be2a2ac1	2357	#define GPIO_DIRSET_PIN18_Pos (18UL) /!< Position of PIN18 field. /
emilmont	80:8e73be2a2ac1	2358	#define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /!< Bit mask of PIN18 field. /
emilmont	80:8e73be2a2ac1	2359	#define GPIO_DIRSET_PIN18_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2360	#define GPIO_DIRSET_PIN18_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2361	#define GPIO_DIRSET_PIN18_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2362
emilmont	80:8e73be2a2ac1	2363	/* Bit 17 : Set as output pin 17. */
emilmont	80:8e73be2a2ac1	2364	#define GPIO_DIRSET_PIN17_Pos (17UL) /!< Position of PIN17 field. /
emilmont	80:8e73be2a2ac1	2365	#define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /!< Bit mask of PIN17 field. /
emilmont	80:8e73be2a2ac1	2366	#define GPIO_DIRSET_PIN17_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2367	#define GPIO_DIRSET_PIN17_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2368	#define GPIO_DIRSET_PIN17_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2369
emilmont	80:8e73be2a2ac1	2370	/* Bit 16 : Set as output pin 16. */
emilmont	80:8e73be2a2ac1	2371	#define GPIO_DIRSET_PIN16_Pos (16UL) /!< Position of PIN16 field. /
emilmont	80:8e73be2a2ac1	2372	#define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /!< Bit mask of PIN16 field. /
emilmont	80:8e73be2a2ac1	2373	#define GPIO_DIRSET_PIN16_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2374	#define GPIO_DIRSET_PIN16_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2375	#define GPIO_DIRSET_PIN16_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2376
emilmont	80:8e73be2a2ac1	2377	/* Bit 15 : Set as output pin 15. */
emilmont	80:8e73be2a2ac1	2378	#define GPIO_DIRSET_PIN15_Pos (15UL) /!< Position of PIN15 field. /
emilmont	80:8e73be2a2ac1	2379	#define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /!< Bit mask of PIN15 field. /
emilmont	80:8e73be2a2ac1	2380	#define GPIO_DIRSET_PIN15_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2381	#define GPIO_DIRSET_PIN15_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2382	#define GPIO_DIRSET_PIN15_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2383
emilmont	80:8e73be2a2ac1	2384	/* Bit 14 : Set as output pin 14. */
emilmont	80:8e73be2a2ac1	2385	#define GPIO_DIRSET_PIN14_Pos (14UL) /!< Position of PIN14 field. /
emilmont	80:8e73be2a2ac1	2386	#define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /!< Bit mask of PIN14 field. /
emilmont	80:8e73be2a2ac1	2387	#define GPIO_DIRSET_PIN14_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2388	#define GPIO_DIRSET_PIN14_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2389	#define GPIO_DIRSET_PIN14_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2390
emilmont	80:8e73be2a2ac1	2391	/* Bit 13 : Set as output pin 13. */
emilmont	80:8e73be2a2ac1	2392	#define GPIO_DIRSET_PIN13_Pos (13UL) /!< Position of PIN13 field. /
emilmont	80:8e73be2a2ac1	2393	#define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /!< Bit mask of PIN13 field. /
emilmont	80:8e73be2a2ac1	2394	#define GPIO_DIRSET_PIN13_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2395	#define GPIO_DIRSET_PIN13_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2396	#define GPIO_DIRSET_PIN13_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2397
emilmont	80:8e73be2a2ac1	2398	/* Bit 12 : Set as output pin 12. */
emilmont	80:8e73be2a2ac1	2399	#define GPIO_DIRSET_PIN12_Pos (12UL) /!< Position of PIN12 field. /
emilmont	80:8e73be2a2ac1	2400	#define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /!< Bit mask of PIN12 field. /
emilmont	80:8e73be2a2ac1	2401	#define GPIO_DIRSET_PIN12_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2402	#define GPIO_DIRSET_PIN12_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2403	#define GPIO_DIRSET_PIN12_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2404
emilmont	80:8e73be2a2ac1	2405	/* Bit 11 : Set as output pin 11. */
emilmont	80:8e73be2a2ac1	2406	#define GPIO_DIRSET_PIN11_Pos (11UL) /!< Position of PIN11 field. /
emilmont	80:8e73be2a2ac1	2407	#define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /!< Bit mask of PIN11 field. /
emilmont	80:8e73be2a2ac1	2408	#define GPIO_DIRSET_PIN11_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2409	#define GPIO_DIRSET_PIN11_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2410	#define GPIO_DIRSET_PIN11_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2411
emilmont	80:8e73be2a2ac1	2412	/* Bit 10 : Set as output pin 10. */
emilmont	80:8e73be2a2ac1	2413	#define GPIO_DIRSET_PIN10_Pos (10UL) /!< Position of PIN10 field. /
emilmont	80:8e73be2a2ac1	2414	#define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /!< Bit mask of PIN10 field. /
emilmont	80:8e73be2a2ac1	2415	#define GPIO_DIRSET_PIN10_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2416	#define GPIO_DIRSET_PIN10_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2417	#define GPIO_DIRSET_PIN10_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2418
emilmont	80:8e73be2a2ac1	2419	/* Bit 9 : Set as output pin 9. */
emilmont	80:8e73be2a2ac1	2420	#define GPIO_DIRSET_PIN9_Pos (9UL) /!< Position of PIN9 field. /
emilmont	80:8e73be2a2ac1	2421	#define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /!< Bit mask of PIN9 field. /
emilmont	80:8e73be2a2ac1	2422	#define GPIO_DIRSET_PIN9_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2423	#define GPIO_DIRSET_PIN9_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2424	#define GPIO_DIRSET_PIN9_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2425
emilmont	80:8e73be2a2ac1	2426	/* Bit 8 : Set as output pin 8. */
emilmont	80:8e73be2a2ac1	2427	#define GPIO_DIRSET_PIN8_Pos (8UL) /!< Position of PIN8 field. /
emilmont	80:8e73be2a2ac1	2428	#define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /!< Bit mask of PIN8 field. /
emilmont	80:8e73be2a2ac1	2429	#define GPIO_DIRSET_PIN8_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2430	#define GPIO_DIRSET_PIN8_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2431	#define GPIO_DIRSET_PIN8_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2432
emilmont	80:8e73be2a2ac1	2433	/* Bit 7 : Set as output pin 7. */
emilmont	80:8e73be2a2ac1	2434	#define GPIO_DIRSET_PIN7_Pos (7UL) /!< Position of PIN7 field. /
emilmont	80:8e73be2a2ac1	2435	#define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /!< Bit mask of PIN7 field. /
emilmont	80:8e73be2a2ac1	2436	#define GPIO_DIRSET_PIN7_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2437	#define GPIO_DIRSET_PIN7_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2438	#define GPIO_DIRSET_PIN7_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2439
emilmont	80:8e73be2a2ac1	2440	/* Bit 6 : Set as output pin 6. */
emilmont	80:8e73be2a2ac1	2441	#define GPIO_DIRSET_PIN6_Pos (6UL) /!< Position of PIN6 field. /
emilmont	80:8e73be2a2ac1	2442	#define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /!< Bit mask of PIN6 field. /
emilmont	80:8e73be2a2ac1	2443	#define GPIO_DIRSET_PIN6_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2444	#define GPIO_DIRSET_PIN6_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2445	#define GPIO_DIRSET_PIN6_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2446
emilmont	80:8e73be2a2ac1	2447	/* Bit 5 : Set as output pin 5. */
emilmont	80:8e73be2a2ac1	2448	#define GPIO_DIRSET_PIN5_Pos (5UL) /!< Position of PIN5 field. /
emilmont	80:8e73be2a2ac1	2449	#define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /!< Bit mask of PIN5 field. /
emilmont	80:8e73be2a2ac1	2450	#define GPIO_DIRSET_PIN5_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2451	#define GPIO_DIRSET_PIN5_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2452	#define GPIO_DIRSET_PIN5_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2453
emilmont	80:8e73be2a2ac1	2454	/* Bit 4 : Set as output pin 4. */
emilmont	80:8e73be2a2ac1	2455	#define GPIO_DIRSET_PIN4_Pos (4UL) /!< Position of PIN4 field. /
emilmont	80:8e73be2a2ac1	2456	#define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /!< Bit mask of PIN4 field. /
emilmont	80:8e73be2a2ac1	2457	#define GPIO_DIRSET_PIN4_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2458	#define GPIO_DIRSET_PIN4_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2459	#define GPIO_DIRSET_PIN4_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2460
emilmont	80:8e73be2a2ac1	2461	/* Bit 3 : Set as output pin 3. */
emilmont	80:8e73be2a2ac1	2462	#define GPIO_DIRSET_PIN3_Pos (3UL) /!< Position of PIN3 field. /
emilmont	80:8e73be2a2ac1	2463	#define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /!< Bit mask of PIN3 field. /
emilmont	80:8e73be2a2ac1	2464	#define GPIO_DIRSET_PIN3_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2465	#define GPIO_DIRSET_PIN3_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2466	#define GPIO_DIRSET_PIN3_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2467
emilmont	80:8e73be2a2ac1	2468	/* Bit 2 : Set as output pin 2. */
emilmont	80:8e73be2a2ac1	2469	#define GPIO_DIRSET_PIN2_Pos (2UL) /!< Position of PIN2 field. /
emilmont	80:8e73be2a2ac1	2470	#define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /!< Bit mask of PIN2 field. /
emilmont	80:8e73be2a2ac1	2471	#define GPIO_DIRSET_PIN2_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2472	#define GPIO_DIRSET_PIN2_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2473	#define GPIO_DIRSET_PIN2_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2474
emilmont	80:8e73be2a2ac1	2475	/* Bit 1 : Set as output pin 1. */
emilmont	80:8e73be2a2ac1	2476	#define GPIO_DIRSET_PIN1_Pos (1UL) /!< Position of PIN1 field. /
emilmont	80:8e73be2a2ac1	2477	#define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /!< Bit mask of PIN1 field. /
emilmont	80:8e73be2a2ac1	2478	#define GPIO_DIRSET_PIN1_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2479	#define GPIO_DIRSET_PIN1_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2480	#define GPIO_DIRSET_PIN1_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2481
emilmont	80:8e73be2a2ac1	2482	/* Bit 0 : Set as output pin 0. */
emilmont	80:8e73be2a2ac1	2483	#define GPIO_DIRSET_PIN0_Pos (0UL) /!< Position of PIN0 field. /
emilmont	80:8e73be2a2ac1	2484	#define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /!< Bit mask of PIN0 field. /
emilmont	80:8e73be2a2ac1	2485	#define GPIO_DIRSET_PIN0_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2486	#define GPIO_DIRSET_PIN0_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2487	#define GPIO_DIRSET_PIN0_Set (1UL) /!< Set pin as output. /
emilmont	80:8e73be2a2ac1	2488
emilmont	80:8e73be2a2ac1	2489	/* Register: GPIO_DIRCLR */
emilmont	80:8e73be2a2ac1	2490	/* Description: DIR clear register. */
emilmont	80:8e73be2a2ac1	2491
emilmont	80:8e73be2a2ac1	2492	/* Bit 31 : Set as input pin 31. */
emilmont	80:8e73be2a2ac1	2493	#define GPIO_DIRCLR_PIN31_Pos (31UL) /!< Position of PIN31 field. /
emilmont	80:8e73be2a2ac1	2494	#define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /!< Bit mask of PIN31 field. /
emilmont	80:8e73be2a2ac1	2495	#define GPIO_DIRCLR_PIN31_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2496	#define GPIO_DIRCLR_PIN31_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2497	#define GPIO_DIRCLR_PIN31_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2498
emilmont	80:8e73be2a2ac1	2499	/* Bit 30 : Set as input pin 30. */
emilmont	80:8e73be2a2ac1	2500	#define GPIO_DIRCLR_PIN30_Pos (30UL) /!< Position of PIN30 field. /
emilmont	80:8e73be2a2ac1	2501	#define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /!< Bit mask of PIN30 field. /
emilmont	80:8e73be2a2ac1	2502	#define GPIO_DIRCLR_PIN30_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2503	#define GPIO_DIRCLR_PIN30_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2504	#define GPIO_DIRCLR_PIN30_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2505
emilmont	80:8e73be2a2ac1	2506	/* Bit 29 : Set as input pin 29. */
emilmont	80:8e73be2a2ac1	2507	#define GPIO_DIRCLR_PIN29_Pos (29UL) /!< Position of PIN29 field. /
emilmont	80:8e73be2a2ac1	2508	#define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /!< Bit mask of PIN29 field. /
emilmont	80:8e73be2a2ac1	2509	#define GPIO_DIRCLR_PIN29_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2510	#define GPIO_DIRCLR_PIN29_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2511	#define GPIO_DIRCLR_PIN29_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2512
emilmont	80:8e73be2a2ac1	2513	/* Bit 28 : Set as input pin 28. */
emilmont	80:8e73be2a2ac1	2514	#define GPIO_DIRCLR_PIN28_Pos (28UL) /!< Position of PIN28 field. /
emilmont	80:8e73be2a2ac1	2515	#define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /!< Bit mask of PIN28 field. /
emilmont	80:8e73be2a2ac1	2516	#define GPIO_DIRCLR_PIN28_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2517	#define GPIO_DIRCLR_PIN28_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2518	#define GPIO_DIRCLR_PIN28_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2519
emilmont	80:8e73be2a2ac1	2520	/* Bit 27 : Set as input pin 27. */
emilmont	80:8e73be2a2ac1	2521	#define GPIO_DIRCLR_PIN27_Pos (27UL) /!< Position of PIN27 field. /
emilmont	80:8e73be2a2ac1	2522	#define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /!< Bit mask of PIN27 field. /
emilmont	80:8e73be2a2ac1	2523	#define GPIO_DIRCLR_PIN27_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2524	#define GPIO_DIRCLR_PIN27_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2525	#define GPIO_DIRCLR_PIN27_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2526
emilmont	80:8e73be2a2ac1	2527	/* Bit 26 : Set as input pin 26. */
emilmont	80:8e73be2a2ac1	2528	#define GPIO_DIRCLR_PIN26_Pos (26UL) /!< Position of PIN26 field. /
emilmont	80:8e73be2a2ac1	2529	#define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /!< Bit mask of PIN26 field. /
emilmont	80:8e73be2a2ac1	2530	#define GPIO_DIRCLR_PIN26_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2531	#define GPIO_DIRCLR_PIN26_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2532	#define GPIO_DIRCLR_PIN26_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2533
emilmont	80:8e73be2a2ac1	2534	/* Bit 25 : Set as input pin 25. */
emilmont	80:8e73be2a2ac1	2535	#define GPIO_DIRCLR_PIN25_Pos (25UL) /!< Position of PIN25 field. /
emilmont	80:8e73be2a2ac1	2536	#define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /!< Bit mask of PIN25 field. /
emilmont	80:8e73be2a2ac1	2537	#define GPIO_DIRCLR_PIN25_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2538	#define GPIO_DIRCLR_PIN25_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2539	#define GPIO_DIRCLR_PIN25_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2540
emilmont	80:8e73be2a2ac1	2541	/* Bit 24 : Set as input pin 24. */
emilmont	80:8e73be2a2ac1	2542	#define GPIO_DIRCLR_PIN24_Pos (24UL) /!< Position of PIN24 field. /
emilmont	80:8e73be2a2ac1	2543	#define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /!< Bit mask of PIN24 field. /
emilmont	80:8e73be2a2ac1	2544	#define GPIO_DIRCLR_PIN24_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2545	#define GPIO_DIRCLR_PIN24_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2546	#define GPIO_DIRCLR_PIN24_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2547
emilmont	80:8e73be2a2ac1	2548	/* Bit 23 : Set as input pin 23. */
emilmont	80:8e73be2a2ac1	2549	#define GPIO_DIRCLR_PIN23_Pos (23UL) /!< Position of PIN23 field. /
emilmont	80:8e73be2a2ac1	2550	#define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /!< Bit mask of PIN23 field. /
emilmont	80:8e73be2a2ac1	2551	#define GPIO_DIRCLR_PIN23_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2552	#define GPIO_DIRCLR_PIN23_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2553	#define GPIO_DIRCLR_PIN23_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2554
emilmont	80:8e73be2a2ac1	2555	/* Bit 22 : Set as input pin 22. */
emilmont	80:8e73be2a2ac1	2556	#define GPIO_DIRCLR_PIN22_Pos (22UL) /!< Position of PIN22 field. /
emilmont	80:8e73be2a2ac1	2557	#define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /!< Bit mask of PIN22 field. /
emilmont	80:8e73be2a2ac1	2558	#define GPIO_DIRCLR_PIN22_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2559	#define GPIO_DIRCLR_PIN22_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2560	#define GPIO_DIRCLR_PIN22_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2561
emilmont	80:8e73be2a2ac1	2562	/* Bit 21 : Set as input pin 21. */
emilmont	80:8e73be2a2ac1	2563	#define GPIO_DIRCLR_PIN21_Pos (21UL) /!< Position of PIN21 field. /
emilmont	80:8e73be2a2ac1	2564	#define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /!< Bit mask of PIN21 field. /
emilmont	80:8e73be2a2ac1	2565	#define GPIO_DIRCLR_PIN21_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2566	#define GPIO_DIRCLR_PIN21_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2567	#define GPIO_DIRCLR_PIN21_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2568
emilmont	80:8e73be2a2ac1	2569	/* Bit 20 : Set as input pin 20. */
emilmont	80:8e73be2a2ac1	2570	#define GPIO_DIRCLR_PIN20_Pos (20UL) /!< Position of PIN20 field. /
emilmont	80:8e73be2a2ac1	2571	#define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /!< Bit mask of PIN20 field. /
emilmont	80:8e73be2a2ac1	2572	#define GPIO_DIRCLR_PIN20_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2573	#define GPIO_DIRCLR_PIN20_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2574	#define GPIO_DIRCLR_PIN20_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2575
emilmont	80:8e73be2a2ac1	2576	/* Bit 19 : Set as input pin 19. */
emilmont	80:8e73be2a2ac1	2577	#define GPIO_DIRCLR_PIN19_Pos (19UL) /!< Position of PIN19 field. /
emilmont	80:8e73be2a2ac1	2578	#define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /!< Bit mask of PIN19 field. /
emilmont	80:8e73be2a2ac1	2579	#define GPIO_DIRCLR_PIN19_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2580	#define GPIO_DIRCLR_PIN19_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2581	#define GPIO_DIRCLR_PIN19_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2582
emilmont	80:8e73be2a2ac1	2583	/* Bit 18 : Set as input pin 18. */
emilmont	80:8e73be2a2ac1	2584	#define GPIO_DIRCLR_PIN18_Pos (18UL) /!< Position of PIN18 field. /
emilmont	80:8e73be2a2ac1	2585	#define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /!< Bit mask of PIN18 field. /
emilmont	80:8e73be2a2ac1	2586	#define GPIO_DIRCLR_PIN18_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2587	#define GPIO_DIRCLR_PIN18_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2588	#define GPIO_DIRCLR_PIN18_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2589
emilmont	80:8e73be2a2ac1	2590	/* Bit 17 : Set as input pin 17. */
emilmont	80:8e73be2a2ac1	2591	#define GPIO_DIRCLR_PIN17_Pos (17UL) /!< Position of PIN17 field. /
emilmont	80:8e73be2a2ac1	2592	#define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /!< Bit mask of PIN17 field. /
emilmont	80:8e73be2a2ac1	2593	#define GPIO_DIRCLR_PIN17_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2594	#define GPIO_DIRCLR_PIN17_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2595	#define GPIO_DIRCLR_PIN17_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2596
emilmont	80:8e73be2a2ac1	2597	/* Bit 16 : Set as input pin 16. */
emilmont	80:8e73be2a2ac1	2598	#define GPIO_DIRCLR_PIN16_Pos (16UL) /!< Position of PIN16 field. /
emilmont	80:8e73be2a2ac1	2599	#define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /!< Bit mask of PIN16 field. /
emilmont	80:8e73be2a2ac1	2600	#define GPIO_DIRCLR_PIN16_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2601	#define GPIO_DIRCLR_PIN16_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2602	#define GPIO_DIRCLR_PIN16_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2603
emilmont	80:8e73be2a2ac1	2604	/* Bit 15 : Set as input pin 15. */
emilmont	80:8e73be2a2ac1	2605	#define GPIO_DIRCLR_PIN15_Pos (15UL) /!< Position of PIN15 field. /
emilmont	80:8e73be2a2ac1	2606	#define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /!< Bit mask of PIN15 field. /
emilmont	80:8e73be2a2ac1	2607	#define GPIO_DIRCLR_PIN15_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2608	#define GPIO_DIRCLR_PIN15_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2609	#define GPIO_DIRCLR_PIN15_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2610
emilmont	80:8e73be2a2ac1	2611	/* Bit 14 : Set as input pin 14. */
emilmont	80:8e73be2a2ac1	2612	#define GPIO_DIRCLR_PIN14_Pos (14UL) /!< Position of PIN14 field. /
emilmont	80:8e73be2a2ac1	2613	#define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /!< Bit mask of PIN14 field. /
emilmont	80:8e73be2a2ac1	2614	#define GPIO_DIRCLR_PIN14_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2615	#define GPIO_DIRCLR_PIN14_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2616	#define GPIO_DIRCLR_PIN14_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2617
emilmont	80:8e73be2a2ac1	2618	/* Bit 13 : Set as input pin 13. */
emilmont	80:8e73be2a2ac1	2619	#define GPIO_DIRCLR_PIN13_Pos (13UL) /!< Position of PIN13 field. /
emilmont	80:8e73be2a2ac1	2620	#define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /!< Bit mask of PIN13 field. /
emilmont	80:8e73be2a2ac1	2621	#define GPIO_DIRCLR_PIN13_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2622	#define GPIO_DIRCLR_PIN13_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2623	#define GPIO_DIRCLR_PIN13_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2624
emilmont	80:8e73be2a2ac1	2625	/* Bit 12 : Set as input pin 12. */
emilmont	80:8e73be2a2ac1	2626	#define GPIO_DIRCLR_PIN12_Pos (12UL) /!< Position of PIN12 field. /
emilmont	80:8e73be2a2ac1	2627	#define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /!< Bit mask of PIN12 field. /
emilmont	80:8e73be2a2ac1	2628	#define GPIO_DIRCLR_PIN12_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2629	#define GPIO_DIRCLR_PIN12_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2630	#define GPIO_DIRCLR_PIN12_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2631
emilmont	80:8e73be2a2ac1	2632	/* Bit 11 : Set as input pin 11. */
emilmont	80:8e73be2a2ac1	2633	#define GPIO_DIRCLR_PIN11_Pos (11UL) /!< Position of PIN11 field. /
emilmont	80:8e73be2a2ac1	2634	#define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /!< Bit mask of PIN11 field. /
emilmont	80:8e73be2a2ac1	2635	#define GPIO_DIRCLR_PIN11_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2636	#define GPIO_DIRCLR_PIN11_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2637	#define GPIO_DIRCLR_PIN11_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2638
emilmont	80:8e73be2a2ac1	2639	/* Bit 10 : Set as input pin 10. */
emilmont	80:8e73be2a2ac1	2640	#define GPIO_DIRCLR_PIN10_Pos (10UL) /!< Position of PIN10 field. /
emilmont	80:8e73be2a2ac1	2641	#define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /!< Bit mask of PIN10 field. /
emilmont	80:8e73be2a2ac1	2642	#define GPIO_DIRCLR_PIN10_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2643	#define GPIO_DIRCLR_PIN10_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2644	#define GPIO_DIRCLR_PIN10_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2645
emilmont	80:8e73be2a2ac1	2646	/* Bit 9 : Set as input pin 9. */
emilmont	80:8e73be2a2ac1	2647	#define GPIO_DIRCLR_PIN9_Pos (9UL) /!< Position of PIN9 field. /
emilmont	80:8e73be2a2ac1	2648	#define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /!< Bit mask of PIN9 field. /
emilmont	80:8e73be2a2ac1	2649	#define GPIO_DIRCLR_PIN9_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2650	#define GPIO_DIRCLR_PIN9_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2651	#define GPIO_DIRCLR_PIN9_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2652
emilmont	80:8e73be2a2ac1	2653	/* Bit 8 : Set as input pin 8. */
emilmont	80:8e73be2a2ac1	2654	#define GPIO_DIRCLR_PIN8_Pos (8UL) /!< Position of PIN8 field. /
emilmont	80:8e73be2a2ac1	2655	#define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /!< Bit mask of PIN8 field. /
emilmont	80:8e73be2a2ac1	2656	#define GPIO_DIRCLR_PIN8_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2657	#define GPIO_DIRCLR_PIN8_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2658	#define GPIO_DIRCLR_PIN8_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2659
emilmont	80:8e73be2a2ac1	2660	/* Bit 7 : Set as input pin 7. */
emilmont	80:8e73be2a2ac1	2661	#define GPIO_DIRCLR_PIN7_Pos (7UL) /!< Position of PIN7 field. /
emilmont	80:8e73be2a2ac1	2662	#define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /!< Bit mask of PIN7 field. /
emilmont	80:8e73be2a2ac1	2663	#define GPIO_DIRCLR_PIN7_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2664	#define GPIO_DIRCLR_PIN7_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2665	#define GPIO_DIRCLR_PIN7_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2666
emilmont	80:8e73be2a2ac1	2667	/* Bit 6 : Set as input pin 6. */
emilmont	80:8e73be2a2ac1	2668	#define GPIO_DIRCLR_PIN6_Pos (6UL) /!< Position of PIN6 field. /
emilmont	80:8e73be2a2ac1	2669	#define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /!< Bit mask of PIN6 field. /
emilmont	80:8e73be2a2ac1	2670	#define GPIO_DIRCLR_PIN6_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2671	#define GPIO_DIRCLR_PIN6_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2672	#define GPIO_DIRCLR_PIN6_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2673
emilmont	80:8e73be2a2ac1	2674	/* Bit 5 : Set as input pin 5. */
emilmont	80:8e73be2a2ac1	2675	#define GPIO_DIRCLR_PIN5_Pos (5UL) /!< Position of PIN5 field. /
emilmont	80:8e73be2a2ac1	2676	#define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /!< Bit mask of PIN5 field. /
emilmont	80:8e73be2a2ac1	2677	#define GPIO_DIRCLR_PIN5_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2678	#define GPIO_DIRCLR_PIN5_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2679	#define GPIO_DIRCLR_PIN5_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2680
emilmont	80:8e73be2a2ac1	2681	/* Bit 4 : Set as input pin 4. */
emilmont	80:8e73be2a2ac1	2682	#define GPIO_DIRCLR_PIN4_Pos (4UL) /!< Position of PIN4 field. /
emilmont	80:8e73be2a2ac1	2683	#define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /!< Bit mask of PIN4 field. /
emilmont	80:8e73be2a2ac1	2684	#define GPIO_DIRCLR_PIN4_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2685	#define GPIO_DIRCLR_PIN4_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2686	#define GPIO_DIRCLR_PIN4_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2687
emilmont	80:8e73be2a2ac1	2688	/* Bit 3 : Set as input pin 3. */
emilmont	80:8e73be2a2ac1	2689	#define GPIO_DIRCLR_PIN3_Pos (3UL) /!< Position of PIN3 field. /
emilmont	80:8e73be2a2ac1	2690	#define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /!< Bit mask of PIN3 field. /
emilmont	80:8e73be2a2ac1	2691	#define GPIO_DIRCLR_PIN3_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2692	#define GPIO_DIRCLR_PIN3_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2693	#define GPIO_DIRCLR_PIN3_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2694
emilmont	80:8e73be2a2ac1	2695	/* Bit 2 : Set as input pin 2. */
emilmont	80:8e73be2a2ac1	2696	#define GPIO_DIRCLR_PIN2_Pos (2UL) /!< Position of PIN2 field. /
emilmont	80:8e73be2a2ac1	2697	#define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /!< Bit mask of PIN2 field. /
emilmont	80:8e73be2a2ac1	2698	#define GPIO_DIRCLR_PIN2_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2699	#define GPIO_DIRCLR_PIN2_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2700	#define GPIO_DIRCLR_PIN2_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2701
emilmont	80:8e73be2a2ac1	2702	/* Bit 1 : Set as input pin 1. */
emilmont	80:8e73be2a2ac1	2703	#define GPIO_DIRCLR_PIN1_Pos (1UL) /!< Position of PIN1 field. /
emilmont	80:8e73be2a2ac1	2704	#define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /!< Bit mask of PIN1 field. /
emilmont	80:8e73be2a2ac1	2705	#define GPIO_DIRCLR_PIN1_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2706	#define GPIO_DIRCLR_PIN1_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2707	#define GPIO_DIRCLR_PIN1_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2708
emilmont	80:8e73be2a2ac1	2709	/* Bit 0 : Set as input pin 0. */
emilmont	80:8e73be2a2ac1	2710	#define GPIO_DIRCLR_PIN0_Pos (0UL) /!< Position of PIN0 field. /
emilmont	80:8e73be2a2ac1	2711	#define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /!< Bit mask of PIN0 field. /
emilmont	80:8e73be2a2ac1	2712	#define GPIO_DIRCLR_PIN0_Input (0UL) /!< Pin set as input. /
emilmont	80:8e73be2a2ac1	2713	#define GPIO_DIRCLR_PIN0_Output (1UL) /!< Pin set as output. /
emilmont	80:8e73be2a2ac1	2714	#define GPIO_DIRCLR_PIN0_Clear (1UL) /!< Set pin as input. /
emilmont	80:8e73be2a2ac1	2715
emilmont	80:8e73be2a2ac1	2716	/* Register: GPIO_PIN_CNF */
emilmont	80:8e73be2a2ac1	2717	/* Description: Configuration of GPIO pins. */
emilmont	80:8e73be2a2ac1	2718
emilmont	80:8e73be2a2ac1	2719	/* Bits 17..16 : Pin sensing mechanism. */
emilmont	80:8e73be2a2ac1	2720	#define GPIO_PIN_CNF_SENSE_Pos (16UL) /!< Position of SENSE field. /
emilmont	80:8e73be2a2ac1	2721	#define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /!< Bit mask of SENSE field. /
emilmont	80:8e73be2a2ac1	2722	#define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	2723	#define GPIO_PIN_CNF_SENSE_High (0x02UL) /!< Wakeup on high level. /
emilmont	80:8e73be2a2ac1	2724	#define GPIO_PIN_CNF_SENSE_Low (0x03UL) /!< Wakeup on low level. /
emilmont	80:8e73be2a2ac1	2725
emilmont	80:8e73be2a2ac1	2726	/* Bits 10..8 : Drive configuration. */
emilmont	80:8e73be2a2ac1	2727	#define GPIO_PIN_CNF_DRIVE_Pos (8UL) /!< Position of DRIVE field. /
emilmont	80:8e73be2a2ac1	2728	#define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /!< Bit mask of DRIVE field. /
emilmont	80:8e73be2a2ac1	2729	#define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /!< Standard '0', Standard '1'. /
emilmont	80:8e73be2a2ac1	2730	#define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /!< High '0', Standard '1'. /
emilmont	80:8e73be2a2ac1	2731	#define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /!< Standard '0', High '1'. /
emilmont	80:8e73be2a2ac1	2732	#define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /!< High '0', High '1'. /
emilmont	80:8e73be2a2ac1	2733	#define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /!< Disconnected '0', Standard '1'. /
emilmont	80:8e73be2a2ac1	2734	#define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /!< Disconnected '0', High '1'. /
emilmont	80:8e73be2a2ac1	2735	#define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /!< Standard '0', Disconnected '1'. /
emilmont	80:8e73be2a2ac1	2736	#define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /!< High '0', Disconnected '1'. /
emilmont	80:8e73be2a2ac1	2737
emilmont	80:8e73be2a2ac1	2738	/* Bits 3..2 : Pull-up or -down configuration. */
emilmont	80:8e73be2a2ac1	2739	#define GPIO_PIN_CNF_PULL_Pos (2UL) /!< Position of PULL field. /
emilmont	80:8e73be2a2ac1	2740	#define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /!< Bit mask of PULL field. /
emilmont	80:8e73be2a2ac1	2741	#define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /!< No pull. /
emilmont	80:8e73be2a2ac1	2742	#define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /!< Pulldown on pin. /
emilmont	80:8e73be2a2ac1	2743	#define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /!< Pullup on pin. /
emilmont	80:8e73be2a2ac1	2744
emilmont	80:8e73be2a2ac1	2745	/* Bit 1 : Connect or disconnect input path. */
emilmont	80:8e73be2a2ac1	2746	#define GPIO_PIN_CNF_INPUT_Pos (1UL) /!< Position of INPUT field. /
emilmont	80:8e73be2a2ac1	2747	#define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /!< Bit mask of INPUT field. /
emilmont	80:8e73be2a2ac1	2748	#define GPIO_PIN_CNF_INPUT_Connect (0UL) /!< Connect input pin. /
emilmont	80:8e73be2a2ac1	2749	#define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /!< Disconnect input pin. /
emilmont	80:8e73be2a2ac1	2750
emilmont	80:8e73be2a2ac1	2751	/* Bit 0 : Pin direction. */
emilmont	80:8e73be2a2ac1	2752	#define GPIO_PIN_CNF_DIR_Pos (0UL) /!< Position of DIR field. /
emilmont	80:8e73be2a2ac1	2753	#define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /!< Bit mask of DIR field. /
emilmont	80:8e73be2a2ac1	2754	#define GPIO_PIN_CNF_DIR_Input (0UL) /!< Configure pin as an input pin. /
emilmont	80:8e73be2a2ac1	2755	#define GPIO_PIN_CNF_DIR_Output (1UL) /!< Configure pin as an output pin. /
emilmont	80:8e73be2a2ac1	2756
emilmont	80:8e73be2a2ac1	2757
emilmont	80:8e73be2a2ac1	2758	/* Peripheral: GPIOTE */
emilmont	80:8e73be2a2ac1	2759	/* Description: GPIO tasks and events. */
emilmont	80:8e73be2a2ac1	2760
emilmont	80:8e73be2a2ac1	2761	/* Register: GPIOTE_INTENSET */
emilmont	80:8e73be2a2ac1	2762	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	2763
emilmont	80:8e73be2a2ac1	2764	/* Bit 31 : Enable interrupt on PORT event. */
emilmont	80:8e73be2a2ac1	2765	#define GPIOTE_INTENSET_PORT_Pos (31UL) /!< Position of PORT field. /
emilmont	80:8e73be2a2ac1	2766	#define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /!< Bit mask of PORT field. /
emilmont	80:8e73be2a2ac1	2767	#define GPIOTE_INTENSET_PORT_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2768	#define GPIOTE_INTENSET_PORT_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2769	#define GPIOTE_INTENSET_PORT_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	2770
emilmont	80:8e73be2a2ac1	2771	/* Bit 3 : Enable interrupt on IN[3] event. */
emilmont	80:8e73be2a2ac1	2772	#define GPIOTE_INTENSET_IN3_Pos (3UL) /!< Position of IN3 field. /
emilmont	80:8e73be2a2ac1	2773	#define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /!< Bit mask of IN3 field. /
emilmont	80:8e73be2a2ac1	2774	#define GPIOTE_INTENSET_IN3_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2775	#define GPIOTE_INTENSET_IN3_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2776	#define GPIOTE_INTENSET_IN3_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	2777
emilmont	80:8e73be2a2ac1	2778	/* Bit 2 : Enable interrupt on IN[2] event. */
emilmont	80:8e73be2a2ac1	2779	#define GPIOTE_INTENSET_IN2_Pos (2UL) /!< Position of IN2 field. /
emilmont	80:8e73be2a2ac1	2780	#define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /!< Bit mask of IN2 field. /
emilmont	80:8e73be2a2ac1	2781	#define GPIOTE_INTENSET_IN2_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2782	#define GPIOTE_INTENSET_IN2_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2783	#define GPIOTE_INTENSET_IN2_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	2784
emilmont	80:8e73be2a2ac1	2785	/* Bit 1 : Enable interrupt on IN[1] event. */
emilmont	80:8e73be2a2ac1	2786	#define GPIOTE_INTENSET_IN1_Pos (1UL) /!< Position of IN1 field. /
emilmont	80:8e73be2a2ac1	2787	#define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /!< Bit mask of IN1 field. /
emilmont	80:8e73be2a2ac1	2788	#define GPIOTE_INTENSET_IN1_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2789	#define GPIOTE_INTENSET_IN1_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2790	#define GPIOTE_INTENSET_IN1_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	2791
emilmont	80:8e73be2a2ac1	2792	/* Bit 0 : Enable interrupt on IN[0] event. */
emilmont	80:8e73be2a2ac1	2793	#define GPIOTE_INTENSET_IN0_Pos (0UL) /!< Position of IN0 field. /
emilmont	80:8e73be2a2ac1	2794	#define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /!< Bit mask of IN0 field. /
emilmont	80:8e73be2a2ac1	2795	#define GPIOTE_INTENSET_IN0_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2796	#define GPIOTE_INTENSET_IN0_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2797	#define GPIOTE_INTENSET_IN0_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	2798
emilmont	80:8e73be2a2ac1	2799	/* Register: GPIOTE_INTENCLR */
emilmont	80:8e73be2a2ac1	2800	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	2801
emilmont	80:8e73be2a2ac1	2802	/* Bit 31 : Disable interrupt on PORT event. */
emilmont	80:8e73be2a2ac1	2803	#define GPIOTE_INTENCLR_PORT_Pos (31UL) /!< Position of PORT field. /
emilmont	80:8e73be2a2ac1	2804	#define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /!< Bit mask of PORT field. /
emilmont	80:8e73be2a2ac1	2805	#define GPIOTE_INTENCLR_PORT_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2806	#define GPIOTE_INTENCLR_PORT_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2807	#define GPIOTE_INTENCLR_PORT_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	2808
emilmont	80:8e73be2a2ac1	2809	/* Bit 3 : Disable interrupt on IN[3] event. */
emilmont	80:8e73be2a2ac1	2810	#define GPIOTE_INTENCLR_IN3_Pos (3UL) /!< Position of IN3 field. /
emilmont	80:8e73be2a2ac1	2811	#define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /!< Bit mask of IN3 field. /
emilmont	80:8e73be2a2ac1	2812	#define GPIOTE_INTENCLR_IN3_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2813	#define GPIOTE_INTENCLR_IN3_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2814	#define GPIOTE_INTENCLR_IN3_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	2815
emilmont	80:8e73be2a2ac1	2816	/* Bit 2 : Disable interrupt on IN[2] event. */
emilmont	80:8e73be2a2ac1	2817	#define GPIOTE_INTENCLR_IN2_Pos (2UL) /!< Position of IN2 field. /
emilmont	80:8e73be2a2ac1	2818	#define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /!< Bit mask of IN2 field. /
emilmont	80:8e73be2a2ac1	2819	#define GPIOTE_INTENCLR_IN2_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2820	#define GPIOTE_INTENCLR_IN2_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2821	#define GPIOTE_INTENCLR_IN2_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	2822
emilmont	80:8e73be2a2ac1	2823	/* Bit 1 : Disable interrupt on IN[1] event. */
emilmont	80:8e73be2a2ac1	2824	#define GPIOTE_INTENCLR_IN1_Pos (1UL) /!< Position of IN1 field. /
emilmont	80:8e73be2a2ac1	2825	#define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /!< Bit mask of IN1 field. /
emilmont	80:8e73be2a2ac1	2826	#define GPIOTE_INTENCLR_IN1_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2827	#define GPIOTE_INTENCLR_IN1_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2828	#define GPIOTE_INTENCLR_IN1_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	2829
emilmont	80:8e73be2a2ac1	2830	/* Bit 0 : Disable interrupt on IN[0] event. */
emilmont	80:8e73be2a2ac1	2831	#define GPIOTE_INTENCLR_IN0_Pos (0UL) /!< Position of IN0 field. /
emilmont	80:8e73be2a2ac1	2832	#define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /!< Bit mask of IN0 field. /
emilmont	80:8e73be2a2ac1	2833	#define GPIOTE_INTENCLR_IN0_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2834	#define GPIOTE_INTENCLR_IN0_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2835	#define GPIOTE_INTENCLR_IN0_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	2836
emilmont	80:8e73be2a2ac1	2837	/* Register: GPIOTE_CONFIG */
emilmont	80:8e73be2a2ac1	2838	/* Description: Channel configuration registers. */
emilmont	80:8e73be2a2ac1	2839
emilmont	80:8e73be2a2ac1	2840	/* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
emilmont	80:8e73be2a2ac1	2841	#define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /!< Position of OUTINIT field. /
emilmont	80:8e73be2a2ac1	2842	#define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /!< Bit mask of OUTINIT field. /
emilmont	80:8e73be2a2ac1	2843	#define GPIOTE_CONFIG_OUTINIT_Low (0UL) /!< Initial low output when in task mode. /
emilmont	80:8e73be2a2ac1	2844	#define GPIOTE_CONFIG_OUTINIT_High (1UL) /!< Initial high output when in task mode. /
emilmont	80:8e73be2a2ac1	2845
emilmont	80:8e73be2a2ac1	2846	/* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
emilmont	80:8e73be2a2ac1	2847	#define GPIOTE_CONFIG_POLARITY_Pos (16UL) /!< Position of POLARITY field. /
emilmont	80:8e73be2a2ac1	2848	#define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /!< Bit mask of POLARITY field. /
emilmont	80:8e73be2a2ac1	2849	#define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /!< Low to high. /
emilmont	80:8e73be2a2ac1	2850	#define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /!< High to low. /
emilmont	80:8e73be2a2ac1	2851	#define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /!< Toggle. /
emilmont	80:8e73be2a2ac1	2852
emilmont	80:8e73be2a2ac1	2853	/* Bits 12..8 : Pin select. */
emilmont	80:8e73be2a2ac1	2854	#define GPIOTE_CONFIG_PSEL_Pos (8UL) /!< Position of PSEL field. /
emilmont	80:8e73be2a2ac1	2855	#define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /!< Bit mask of PSEL field. /
emilmont	80:8e73be2a2ac1	2856
emilmont	80:8e73be2a2ac1	2857	/* Bits 1..0 : Mode */
emilmont	80:8e73be2a2ac1	2858	#define GPIOTE_CONFIG_MODE_Pos (0UL) /!< Position of MODE field. /
emilmont	80:8e73be2a2ac1	2859	#define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /!< Bit mask of MODE field. /
emilmont	80:8e73be2a2ac1	2860	#define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	2861	#define GPIOTE_CONFIG_MODE_Event (0x01UL) /!< Channel configure in event mode. /
emilmont	80:8e73be2a2ac1	2862	#define GPIOTE_CONFIG_MODE_Task (0x03UL) /!< Channel configure in task mode. /
emilmont	80:8e73be2a2ac1	2863
emilmont	80:8e73be2a2ac1	2864	/* Register: GPIOTE_POWER */
emilmont	80:8e73be2a2ac1	2865	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	2866
emilmont	80:8e73be2a2ac1	2867	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	2868	#define GPIOTE_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	2869	#define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	2870	#define GPIOTE_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	2871	#define GPIOTE_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	2872
emilmont	80:8e73be2a2ac1	2873
emilmont	80:8e73be2a2ac1	2874	/* Peripheral: LPCOMP */
Kojto	97:433970e64889	2875	/* Description: Low power comparator. */
emilmont	80:8e73be2a2ac1	2876
emilmont	80:8e73be2a2ac1	2877	/* Register: LPCOMP_SHORTS */
Kojto	97:433970e64889	2878	/* Description: Shortcuts for the LPCOMP. */
Kojto	97:433970e64889	2879
Kojto	97:433970e64889	2880	/* Bit 4 : Shortcut between CROSS event and STOP task. */
emilmont	80:8e73be2a2ac1	2881	#define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /!< Position of CROSS_STOP field. /
emilmont	80:8e73be2a2ac1	2882	#define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /!< Bit mask of CROSS_STOP field. /
emilmont	80:8e73be2a2ac1	2883	#define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	2884	#define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	2885
Kojto	97:433970e64889	2886	/* Bit 3 : Shortcut between UP event and STOP task. */
emilmont	80:8e73be2a2ac1	2887	#define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /!< Position of UP_STOP field. /
emilmont	80:8e73be2a2ac1	2888	#define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /!< Bit mask of UP_STOP field. /
emilmont	80:8e73be2a2ac1	2889	#define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	2890	#define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	2891
Kojto	97:433970e64889	2892	/* Bit 2 : Shortcut between DOWN event and STOP task. */
emilmont	80:8e73be2a2ac1	2893	#define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /!< Position of DOWN_STOP field. /
emilmont	80:8e73be2a2ac1	2894	#define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /!< Bit mask of DOWN_STOP field. /
emilmont	80:8e73be2a2ac1	2895	#define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	2896	#define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	2897
Kojto	97:433970e64889	2898	/* Bit 1 : Shortcut between RADY event and STOP task. */
emilmont	80:8e73be2a2ac1	2899	#define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /!< Position of READY_STOP field. /
emilmont	80:8e73be2a2ac1	2900	#define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /!< Bit mask of READY_STOP field. /
emilmont	80:8e73be2a2ac1	2901	#define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	2902	#define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	2903
Kojto	97:433970e64889	2904	/* Bit 0 : Shortcut between READY event and SAMPLE task. */
emilmont	80:8e73be2a2ac1	2905	#define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /!< Position of READY_SAMPLE field. /
emilmont	80:8e73be2a2ac1	2906	#define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /!< Bit mask of READY_SAMPLE field. /
emilmont	80:8e73be2a2ac1	2907	#define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	2908	#define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	2909
emilmont	80:8e73be2a2ac1	2910	/* Register: LPCOMP_INTENSET */
emilmont	80:8e73be2a2ac1	2911	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	2912
emilmont	80:8e73be2a2ac1	2913	/* Bit 3 : Enable interrupt on CROSS event. */
emilmont	80:8e73be2a2ac1	2914	#define LPCOMP_INTENSET_CROSS_Pos (3UL) /!< Position of CROSS field. /
emilmont	80:8e73be2a2ac1	2915	#define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /!< Bit mask of CROSS field. /
emilmont	80:8e73be2a2ac1	2916	#define LPCOMP_INTENSET_CROSS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2917	#define LPCOMP_INTENSET_CROSS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2918	#define LPCOMP_INTENSET_CROSS_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	2919
emilmont	80:8e73be2a2ac1	2920	/* Bit 2 : Enable interrupt on UP event. */
emilmont	80:8e73be2a2ac1	2921	#define LPCOMP_INTENSET_UP_Pos (2UL) /!< Position of UP field. /
emilmont	80:8e73be2a2ac1	2922	#define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /!< Bit mask of UP field. /
emilmont	80:8e73be2a2ac1	2923	#define LPCOMP_INTENSET_UP_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2924	#define LPCOMP_INTENSET_UP_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2925	#define LPCOMP_INTENSET_UP_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	2926
emilmont	80:8e73be2a2ac1	2927	/* Bit 1 : Enable interrupt on DOWN event. */
emilmont	80:8e73be2a2ac1	2928	#define LPCOMP_INTENSET_DOWN_Pos (1UL) /!< Position of DOWN field. /
emilmont	80:8e73be2a2ac1	2929	#define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /!< Bit mask of DOWN field. /
emilmont	80:8e73be2a2ac1	2930	#define LPCOMP_INTENSET_DOWN_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2931	#define LPCOMP_INTENSET_DOWN_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2932	#define LPCOMP_INTENSET_DOWN_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	2933
emilmont	80:8e73be2a2ac1	2934	/* Bit 0 : Enable interrupt on READY event. */
emilmont	80:8e73be2a2ac1	2935	#define LPCOMP_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
emilmont	80:8e73be2a2ac1	2936	#define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /!< Bit mask of READY field. /
emilmont	80:8e73be2a2ac1	2937	#define LPCOMP_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2938	#define LPCOMP_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2939	#define LPCOMP_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	2940
emilmont	80:8e73be2a2ac1	2941	/* Register: LPCOMP_INTENCLR */
emilmont	80:8e73be2a2ac1	2942	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	2943
emilmont	80:8e73be2a2ac1	2944	/* Bit 3 : Disable interrupt on CROSS event. */
emilmont	80:8e73be2a2ac1	2945	#define LPCOMP_INTENCLR_CROSS_Pos (3UL) /!< Position of CROSS field. /
emilmont	80:8e73be2a2ac1	2946	#define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /!< Bit mask of CROSS field. /
emilmont	80:8e73be2a2ac1	2947	#define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2948	#define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2949	#define LPCOMP_INTENCLR_CROSS_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	2950
emilmont	80:8e73be2a2ac1	2951	/* Bit 2 : Disable interrupt on UP event. */
emilmont	80:8e73be2a2ac1	2952	#define LPCOMP_INTENCLR_UP_Pos (2UL) /!< Position of UP field. /
emilmont	80:8e73be2a2ac1	2953	#define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /!< Bit mask of UP field. /
emilmont	80:8e73be2a2ac1	2954	#define LPCOMP_INTENCLR_UP_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2955	#define LPCOMP_INTENCLR_UP_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2956	#define LPCOMP_INTENCLR_UP_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	2957
emilmont	80:8e73be2a2ac1	2958	/* Bit 1 : Disable interrupt on DOWN event. */
emilmont	80:8e73be2a2ac1	2959	#define LPCOMP_INTENCLR_DOWN_Pos (1UL) /!< Position of DOWN field. /
emilmont	80:8e73be2a2ac1	2960	#define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /!< Bit mask of DOWN field. /
emilmont	80:8e73be2a2ac1	2961	#define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2962	#define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2963	#define LPCOMP_INTENCLR_DOWN_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	2964
emilmont	80:8e73be2a2ac1	2965	/* Bit 0 : Disable interrupt on READY event. */
emilmont	80:8e73be2a2ac1	2966	#define LPCOMP_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
emilmont	80:8e73be2a2ac1	2967	#define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
emilmont	80:8e73be2a2ac1	2968	#define LPCOMP_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	2969	#define LPCOMP_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	2970	#define LPCOMP_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	2971
emilmont	80:8e73be2a2ac1	2972	/* Register: LPCOMP_RESULT */
emilmont	80:8e73be2a2ac1	2973	/* Description: Result of last compare. */
emilmont	80:8e73be2a2ac1	2974
emilmont	80:8e73be2a2ac1	2975	/* Bit 0 : Result of last compare. Decision point SAMPLE task. */
emilmont	80:8e73be2a2ac1	2976	#define LPCOMP_RESULT_RESULT_Pos (0UL) /!< Position of RESULT field. /
emilmont	80:8e73be2a2ac1	2977	#define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /!< Bit mask of RESULT field. /
emilmont	80:8e73be2a2ac1	2978	#define LPCOMP_RESULT_RESULT_Bellow (0UL) /!< Input voltage is bellow the reference threshold. /
emilmont	80:8e73be2a2ac1	2979	#define LPCOMP_RESULT_RESULT_Above (1UL) /!< Input voltage is above the reference threshold. /
emilmont	80:8e73be2a2ac1	2980
emilmont	80:8e73be2a2ac1	2981	/* Register: LPCOMP_ENABLE */
emilmont	80:8e73be2a2ac1	2982	/* Description: Enable the LPCOMP. */
emilmont	80:8e73be2a2ac1	2983
emilmont	80:8e73be2a2ac1	2984	/* Bits 1..0 : Enable or disable LPCOMP. */
emilmont	80:8e73be2a2ac1	2985	#define LPCOMP_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	2986	#define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	2987	#define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled LPCOMP. /
emilmont	80:8e73be2a2ac1	2988	#define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable LPCOMP. /
emilmont	80:8e73be2a2ac1	2989
emilmont	80:8e73be2a2ac1	2990	/* Register: LPCOMP_PSEL */
emilmont	80:8e73be2a2ac1	2991	/* Description: Input pin select. */
emilmont	80:8e73be2a2ac1	2992
emilmont	80:8e73be2a2ac1	2993	/* Bits 2..0 : Analog input pin select. */
emilmont	80:8e73be2a2ac1	2994	#define LPCOMP_PSEL_PSEL_Pos (0UL) /!< Position of PSEL field. /
emilmont	80:8e73be2a2ac1	2995	#define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /!< Bit mask of PSEL field. /
emilmont	80:8e73be2a2ac1	2996	#define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /!< Use analog input 0 as analog input. /
emilmont	80:8e73be2a2ac1	2997	#define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /!< Use analog input 1 as analog input. /
emilmont	80:8e73be2a2ac1	2998	#define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /!< Use analog input 2 as analog input. /
emilmont	80:8e73be2a2ac1	2999	#define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /!< Use analog input 3 as analog input. /
emilmont	80:8e73be2a2ac1	3000	#define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /!< Use analog input 4 as analog input. /
emilmont	80:8e73be2a2ac1	3001	#define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /!< Use analog input 5 as analog input. /
emilmont	80:8e73be2a2ac1	3002	#define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /!< Use analog input 6 as analog input. /
emilmont	80:8e73be2a2ac1	3003	#define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /!< Use analog input 7 as analog input. /
emilmont	80:8e73be2a2ac1	3004
emilmont	80:8e73be2a2ac1	3005	/* Register: LPCOMP_REFSEL */
emilmont	80:8e73be2a2ac1	3006	/* Description: Reference select. */
emilmont	80:8e73be2a2ac1	3007
emilmont	80:8e73be2a2ac1	3008	/* Bits 2..0 : Reference select. */
emilmont	80:8e73be2a2ac1	3009	#define LPCOMP_REFSEL_REFSEL_Pos (0UL) /!< Position of REFSEL field. /
emilmont	80:8e73be2a2ac1	3010	#define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /!< Bit mask of REFSEL field. /
Kojto	97:433970e64889	3011	#define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /!< Use supply with a 1/8 prescaler as reference. /
Kojto	97:433970e64889	3012	#define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /!< Use supply with a 2/8 prescaler as reference. /
Kojto	97:433970e64889	3013	#define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /!< Use supply with a 3/8 prescaler as reference. /
Kojto	97:433970e64889	3014	#define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /!< Use supply with a 4/8 prescaler as reference. /
Kojto	97:433970e64889	3015	#define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /!< Use supply with a 5/8 prescaler as reference. /
Kojto	97:433970e64889	3016	#define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /!< Use supply with a 6/8 prescaler as reference. /
Kojto	97:433970e64889	3017	#define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /!< Use supply with a 7/8 prescaler as reference. /
emilmont	80:8e73be2a2ac1	3018	#define LPCOMP_REFSEL_REFSEL_ARef (7UL) /!< Use external analog reference as reference. /
emilmont	80:8e73be2a2ac1	3019
emilmont	80:8e73be2a2ac1	3020	/* Register: LPCOMP_EXTREFSEL */
emilmont	80:8e73be2a2ac1	3021	/* Description: External reference select. */
emilmont	80:8e73be2a2ac1	3022
emilmont	80:8e73be2a2ac1	3023	/* Bit 0 : External analog reference pin selection. */
emilmont	80:8e73be2a2ac1	3024	#define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /!< Position of EXTREFSEL field. /
emilmont	80:8e73be2a2ac1	3025	#define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /!< Bit mask of EXTREFSEL field. /
emilmont	80:8e73be2a2ac1	3026	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /!< Use analog reference 0 as reference. /
emilmont	80:8e73be2a2ac1	3027	#define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /!< Use analog reference 1 as reference. /
emilmont	80:8e73be2a2ac1	3028
emilmont	80:8e73be2a2ac1	3029	/* Register: LPCOMP_ANADETECT */
emilmont	80:8e73be2a2ac1	3030	/* Description: Analog detect configuration. */
emilmont	80:8e73be2a2ac1	3031
emilmont	80:8e73be2a2ac1	3032	/* Bits 1..0 : Analog detect configuration. */
emilmont	80:8e73be2a2ac1	3033	#define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /!< Position of ANADETECT field. /
emilmont	80:8e73be2a2ac1	3034	#define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /!< Bit mask of ANADETECT field. /
emilmont	80:8e73be2a2ac1	3035	#define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /!< Generate ANADETEC on crossing, both upwards and downwards crossing. /
emilmont	80:8e73be2a2ac1	3036	#define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /!< Generate ANADETEC on upwards crossing only. /
emilmont	80:8e73be2a2ac1	3037	#define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /!< Generate ANADETEC on downwards crossing only. /
emilmont	80:8e73be2a2ac1	3038
emilmont	80:8e73be2a2ac1	3039	/* Register: LPCOMP_POWER */
emilmont	80:8e73be2a2ac1	3040	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	3041
emilmont	80:8e73be2a2ac1	3042	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	3043	#define LPCOMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	3044	#define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	3045	#define LPCOMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	3046	#define LPCOMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	3047
emilmont	80:8e73be2a2ac1	3048
emilmont	80:8e73be2a2ac1	3049	/* Peripheral: MPU */
emilmont	80:8e73be2a2ac1	3050	/* Description: Memory Protection Unit. */
emilmont	80:8e73be2a2ac1	3051
emilmont	80:8e73be2a2ac1	3052	/* Register: MPU_PERR0 */
emilmont	80:8e73be2a2ac1	3053	/* Description: Configuration of peripherals in mpu regions. */
emilmont	80:8e73be2a2ac1	3054
emilmont	80:8e73be2a2ac1	3055	/* Bit 31 : PPI region configuration. */
emilmont	80:8e73be2a2ac1	3056	#define MPU_PERR0_PPI_Pos (31UL) /!< Position of PPI field. /
emilmont	80:8e73be2a2ac1	3057	#define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /!< Bit mask of PPI field. /
emilmont	80:8e73be2a2ac1	3058	#define MPU_PERR0_PPI_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3059	#define MPU_PERR0_PPI_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3060
emilmont	80:8e73be2a2ac1	3061	/* Bit 30 : NVMC region configuration. */
emilmont	80:8e73be2a2ac1	3062	#define MPU_PERR0_NVMC_Pos (30UL) /!< Position of NVMC field. /
emilmont	80:8e73be2a2ac1	3063	#define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /!< Bit mask of NVMC field. /
emilmont	80:8e73be2a2ac1	3064	#define MPU_PERR0_NVMC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3065	#define MPU_PERR0_NVMC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3066
Kojto	97:433970e64889	3067	/* Bit 19 : LPCOMP region configuration. */
Kojto	97:433970e64889	3068	#define MPU_PERR0_LPCOMP_Pos (19UL) /!< Position of LPCOMP field. /
Kojto	97:433970e64889	3069	#define MPU_PERR0_LPCOMP_Msk (0x1UL << MPU_PERR0_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
Kojto	97:433970e64889	3070	#define MPU_PERR0_LPCOMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
Kojto	97:433970e64889	3071	#define MPU_PERR0_LPCOMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3072
emilmont	80:8e73be2a2ac1	3073	/* Bit 18 : QDEC region configuration. */
emilmont	80:8e73be2a2ac1	3074	#define MPU_PERR0_QDEC_Pos (18UL) /!< Position of QDEC field. /
emilmont	80:8e73be2a2ac1	3075	#define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /!< Bit mask of QDEC field. /
emilmont	80:8e73be2a2ac1	3076	#define MPU_PERR0_QDEC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3077	#define MPU_PERR0_QDEC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3078
emilmont	80:8e73be2a2ac1	3079	/* Bit 17 : RTC1 region configuration. */
emilmont	80:8e73be2a2ac1	3080	#define MPU_PERR0_RTC1_Pos (17UL) /!< Position of RTC1 field. /
emilmont	80:8e73be2a2ac1	3081	#define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /!< Bit mask of RTC1 field. /
emilmont	80:8e73be2a2ac1	3082	#define MPU_PERR0_RTC1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3083	#define MPU_PERR0_RTC1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3084
emilmont	80:8e73be2a2ac1	3085	/* Bit 16 : WDT region configuration. */
emilmont	80:8e73be2a2ac1	3086	#define MPU_PERR0_WDT_Pos (16UL) /!< Position of WDT field. /
emilmont	80:8e73be2a2ac1	3087	#define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /!< Bit mask of WDT field. /
emilmont	80:8e73be2a2ac1	3088	#define MPU_PERR0_WDT_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3089	#define MPU_PERR0_WDT_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3090
emilmont	80:8e73be2a2ac1	3091	/* Bit 15 : CCM and AAR region configuration. */
emilmont	80:8e73be2a2ac1	3092	#define MPU_PERR0_CCM_AAR_Pos (15UL) /!< Position of CCM_AAR field. /
emilmont	80:8e73be2a2ac1	3093	#define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /!< Bit mask of CCM_AAR field. /
emilmont	80:8e73be2a2ac1	3094	#define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3095	#define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3096
emilmont	80:8e73be2a2ac1	3097	/* Bit 14 : ECB region configuration. */
emilmont	80:8e73be2a2ac1	3098	#define MPU_PERR0_ECB_Pos (14UL) /!< Position of ECB field. /
emilmont	80:8e73be2a2ac1	3099	#define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /!< Bit mask of ECB field. /
emilmont	80:8e73be2a2ac1	3100	#define MPU_PERR0_ECB_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3101	#define MPU_PERR0_ECB_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3102
emilmont	80:8e73be2a2ac1	3103	/* Bit 13 : RNG region configuration. */
emilmont	80:8e73be2a2ac1	3104	#define MPU_PERR0_RNG_Pos (13UL) /!< Position of RNG field. /
emilmont	80:8e73be2a2ac1	3105	#define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /!< Bit mask of RNG field. /
emilmont	80:8e73be2a2ac1	3106	#define MPU_PERR0_RNG_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3107	#define MPU_PERR0_RNG_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3108
emilmont	80:8e73be2a2ac1	3109	/* Bit 12 : TEMP region configuration. */
emilmont	80:8e73be2a2ac1	3110	#define MPU_PERR0_TEMP_Pos (12UL) /!< Position of TEMP field. /
emilmont	80:8e73be2a2ac1	3111	#define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /!< Bit mask of TEMP field. /
emilmont	80:8e73be2a2ac1	3112	#define MPU_PERR0_TEMP_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3113	#define MPU_PERR0_TEMP_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3114
emilmont	80:8e73be2a2ac1	3115	/* Bit 11 : RTC0 region configuration. */
emilmont	80:8e73be2a2ac1	3116	#define MPU_PERR0_RTC0_Pos (11UL) /!< Position of RTC0 field. /
emilmont	80:8e73be2a2ac1	3117	#define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /!< Bit mask of RTC0 field. /
emilmont	80:8e73be2a2ac1	3118	#define MPU_PERR0_RTC0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3119	#define MPU_PERR0_RTC0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3120
emilmont	80:8e73be2a2ac1	3121	/* Bit 10 : TIMER2 region configuration. */
emilmont	80:8e73be2a2ac1	3122	#define MPU_PERR0_TIMER2_Pos (10UL) /!< Position of TIMER2 field. /
emilmont	80:8e73be2a2ac1	3123	#define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /!< Bit mask of TIMER2 field. /
emilmont	80:8e73be2a2ac1	3124	#define MPU_PERR0_TIMER2_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3125	#define MPU_PERR0_TIMER2_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3126
emilmont	80:8e73be2a2ac1	3127	/* Bit 9 : TIMER1 region configuration. */
emilmont	80:8e73be2a2ac1	3128	#define MPU_PERR0_TIMER1_Pos (9UL) /!< Position of TIMER1 field. /
emilmont	80:8e73be2a2ac1	3129	#define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /!< Bit mask of TIMER1 field. /
emilmont	80:8e73be2a2ac1	3130	#define MPU_PERR0_TIMER1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3131	#define MPU_PERR0_TIMER1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3132
emilmont	80:8e73be2a2ac1	3133	/* Bit 8 : TIMER0 region configuration. */
emilmont	80:8e73be2a2ac1	3134	#define MPU_PERR0_TIMER0_Pos (8UL) /!< Position of TIMER0 field. /
emilmont	80:8e73be2a2ac1	3135	#define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /!< Bit mask of TIMER0 field. /
emilmont	80:8e73be2a2ac1	3136	#define MPU_PERR0_TIMER0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3137	#define MPU_PERR0_TIMER0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3138
emilmont	80:8e73be2a2ac1	3139	/* Bit 7 : ADC region configuration. */
emilmont	80:8e73be2a2ac1	3140	#define MPU_PERR0_ADC_Pos (7UL) /!< Position of ADC field. /
emilmont	80:8e73be2a2ac1	3141	#define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /!< Bit mask of ADC field. /
emilmont	80:8e73be2a2ac1	3142	#define MPU_PERR0_ADC_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3143	#define MPU_PERR0_ADC_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3144
emilmont	80:8e73be2a2ac1	3145	/* Bit 6 : GPIOTE region configuration. */
emilmont	80:8e73be2a2ac1	3146	#define MPU_PERR0_GPIOTE_Pos (6UL) /!< Position of GPIOTE field. /
emilmont	80:8e73be2a2ac1	3147	#define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /!< Bit mask of GPIOTE field. /
emilmont	80:8e73be2a2ac1	3148	#define MPU_PERR0_GPIOTE_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3149	#define MPU_PERR0_GPIOTE_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3150
emilmont	80:8e73be2a2ac1	3151	/* Bit 4 : SPI1 and TWI1 region configuration. */
emilmont	80:8e73be2a2ac1	3152	#define MPU_PERR0_SPI1_TWI1_Pos (4UL) /!< Position of SPI1_TWI1 field. /
emilmont	80:8e73be2a2ac1	3153	#define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /!< Bit mask of SPI1_TWI1 field. /
emilmont	80:8e73be2a2ac1	3154	#define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3155	#define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3156
emilmont	80:8e73be2a2ac1	3157	/* Bit 3 : SPI0 and TWI0 region configuration. */
emilmont	80:8e73be2a2ac1	3158	#define MPU_PERR0_SPI0_TWI0_Pos (3UL) /!< Position of SPI0_TWI0 field. /
emilmont	80:8e73be2a2ac1	3159	#define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /!< Bit mask of SPI0_TWI0 field. /
emilmont	80:8e73be2a2ac1	3160	#define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3161	#define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3162
emilmont	80:8e73be2a2ac1	3163	/* Bit 2 : UART0 region configuration. */
emilmont	80:8e73be2a2ac1	3164	#define MPU_PERR0_UART0_Pos (2UL) /!< Position of UART0 field. /
emilmont	80:8e73be2a2ac1	3165	#define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /!< Bit mask of UART0 field. /
emilmont	80:8e73be2a2ac1	3166	#define MPU_PERR0_UART0_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3167	#define MPU_PERR0_UART0_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3168
emilmont	80:8e73be2a2ac1	3169	/* Bit 1 : RADIO region configuration. */
emilmont	80:8e73be2a2ac1	3170	#define MPU_PERR0_RADIO_Pos (1UL) /!< Position of RADIO field. /
emilmont	80:8e73be2a2ac1	3171	#define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /!< Bit mask of RADIO field. /
emilmont	80:8e73be2a2ac1	3172	#define MPU_PERR0_RADIO_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3173	#define MPU_PERR0_RADIO_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3174
emilmont	80:8e73be2a2ac1	3175	/* Bit 0 : POWER_CLOCK region configuration. */
emilmont	80:8e73be2a2ac1	3176	#define MPU_PERR0_POWER_CLOCK_Pos (0UL) /!< Position of POWER_CLOCK field. /
emilmont	80:8e73be2a2ac1	3177	#define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /!< Bit mask of POWER_CLOCK field. /
emilmont	80:8e73be2a2ac1	3178	#define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /!< Peripheral configured in region 1. /
emilmont	80:8e73be2a2ac1	3179	#define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /!< Peripheral configured in region 0. /
emilmont	80:8e73be2a2ac1	3180
emilmont	80:8e73be2a2ac1	3181	/* Register: MPU_PROTENSET0 */
Kojto	97:433970e64889	3182	/* Description: Erase and write protection bit enable set register. */
emilmont	80:8e73be2a2ac1	3183
emilmont	80:8e73be2a2ac1	3184	/* Bit 31 : Protection enable for region 31. */
emilmont	80:8e73be2a2ac1	3185	#define MPU_PROTENSET0_PROTREG31_Pos (31UL) /!< Position of PROTREG31 field. /
emilmont	80:8e73be2a2ac1	3186	#define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /!< Bit mask of PROTREG31 field. /
emilmont	80:8e73be2a2ac1	3187	#define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3188	#define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3189	#define MPU_PROTENSET0_PROTREG31_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3190
emilmont	80:8e73be2a2ac1	3191	/* Bit 30 : Protection enable for region 30. */
emilmont	80:8e73be2a2ac1	3192	#define MPU_PROTENSET0_PROTREG30_Pos (30UL) /!< Position of PROTREG30 field. /
emilmont	80:8e73be2a2ac1	3193	#define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /!< Bit mask of PROTREG30 field. /
emilmont	80:8e73be2a2ac1	3194	#define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3195	#define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3196	#define MPU_PROTENSET0_PROTREG30_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3197
emilmont	80:8e73be2a2ac1	3198	/* Bit 29 : Protection enable for region 29. */
emilmont	80:8e73be2a2ac1	3199	#define MPU_PROTENSET0_PROTREG29_Pos (29UL) /!< Position of PROTREG29 field. /
emilmont	80:8e73be2a2ac1	3200	#define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /!< Bit mask of PROTREG29 field. /
emilmont	80:8e73be2a2ac1	3201	#define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3202	#define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3203	#define MPU_PROTENSET0_PROTREG29_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3204
emilmont	80:8e73be2a2ac1	3205	/* Bit 28 : Protection enable for region 28. */
emilmont	80:8e73be2a2ac1	3206	#define MPU_PROTENSET0_PROTREG28_Pos (28UL) /!< Position of PROTREG28 field. /
emilmont	80:8e73be2a2ac1	3207	#define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /!< Bit mask of PROTREG28 field. /
emilmont	80:8e73be2a2ac1	3208	#define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3209	#define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3210	#define MPU_PROTENSET0_PROTREG28_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3211
emilmont	80:8e73be2a2ac1	3212	/* Bit 27 : Protection enable for region 27. */
emilmont	80:8e73be2a2ac1	3213	#define MPU_PROTENSET0_PROTREG27_Pos (27UL) /!< Position of PROTREG27 field. /
emilmont	80:8e73be2a2ac1	3214	#define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /!< Bit mask of PROTREG27 field. /
emilmont	80:8e73be2a2ac1	3215	#define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3216	#define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3217	#define MPU_PROTENSET0_PROTREG27_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3218
emilmont	80:8e73be2a2ac1	3219	/* Bit 26 : Protection enable for region 26. */
emilmont	80:8e73be2a2ac1	3220	#define MPU_PROTENSET0_PROTREG26_Pos (26UL) /!< Position of PROTREG26 field. /
emilmont	80:8e73be2a2ac1	3221	#define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /!< Bit mask of PROTREG26 field. /
emilmont	80:8e73be2a2ac1	3222	#define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3223	#define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3224	#define MPU_PROTENSET0_PROTREG26_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3225
emilmont	80:8e73be2a2ac1	3226	/* Bit 25 : Protection enable for region 25. */
emilmont	80:8e73be2a2ac1	3227	#define MPU_PROTENSET0_PROTREG25_Pos (25UL) /!< Position of PROTREG25 field. /
emilmont	80:8e73be2a2ac1	3228	#define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /!< Bit mask of PROTREG25 field. /
emilmont	80:8e73be2a2ac1	3229	#define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3230	#define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3231	#define MPU_PROTENSET0_PROTREG25_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3232
emilmont	80:8e73be2a2ac1	3233	/* Bit 24 : Protection enable for region 24. */
emilmont	80:8e73be2a2ac1	3234	#define MPU_PROTENSET0_PROTREG24_Pos (24UL) /!< Position of PROTREG24 field. /
emilmont	80:8e73be2a2ac1	3235	#define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /!< Bit mask of PROTREG24 field. /
emilmont	80:8e73be2a2ac1	3236	#define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3237	#define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3238	#define MPU_PROTENSET0_PROTREG24_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3239
emilmont	80:8e73be2a2ac1	3240	/* Bit 23 : Protection enable for region 23. */
emilmont	80:8e73be2a2ac1	3241	#define MPU_PROTENSET0_PROTREG23_Pos (23UL) /!< Position of PROTREG23 field. /
emilmont	80:8e73be2a2ac1	3242	#define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /!< Bit mask of PROTREG23 field. /
emilmont	80:8e73be2a2ac1	3243	#define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3244	#define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3245	#define MPU_PROTENSET0_PROTREG23_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3246
emilmont	80:8e73be2a2ac1	3247	/* Bit 22 : Protection enable for region 22. */
emilmont	80:8e73be2a2ac1	3248	#define MPU_PROTENSET0_PROTREG22_Pos (22UL) /!< Position of PROTREG22 field. /
emilmont	80:8e73be2a2ac1	3249	#define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /!< Bit mask of PROTREG22 field. /
emilmont	80:8e73be2a2ac1	3250	#define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3251	#define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3252	#define MPU_PROTENSET0_PROTREG22_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3253
emilmont	80:8e73be2a2ac1	3254	/* Bit 21 : Protection enable for region 21. */
emilmont	80:8e73be2a2ac1	3255	#define MPU_PROTENSET0_PROTREG21_Pos (21UL) /!< Position of PROTREG21 field. /
emilmont	80:8e73be2a2ac1	3256	#define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /!< Bit mask of PROTREG21 field. /
emilmont	80:8e73be2a2ac1	3257	#define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3258	#define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3259	#define MPU_PROTENSET0_PROTREG21_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3260
emilmont	80:8e73be2a2ac1	3261	/* Bit 20 : Protection enable for region 20. */
emilmont	80:8e73be2a2ac1	3262	#define MPU_PROTENSET0_PROTREG20_Pos (20UL) /!< Position of PROTREG20 field. /
emilmont	80:8e73be2a2ac1	3263	#define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /!< Bit mask of PROTREG20 field. /
emilmont	80:8e73be2a2ac1	3264	#define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3265	#define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3266	#define MPU_PROTENSET0_PROTREG20_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3267
emilmont	80:8e73be2a2ac1	3268	/* Bit 19 : Protection enable for region 19. */
emilmont	80:8e73be2a2ac1	3269	#define MPU_PROTENSET0_PROTREG19_Pos (19UL) /!< Position of PROTREG19 field. /
emilmont	80:8e73be2a2ac1	3270	#define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /!< Bit mask of PROTREG19 field. /
emilmont	80:8e73be2a2ac1	3271	#define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3272	#define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3273	#define MPU_PROTENSET0_PROTREG19_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3274
emilmont	80:8e73be2a2ac1	3275	/* Bit 18 : Protection enable for region 18. */
emilmont	80:8e73be2a2ac1	3276	#define MPU_PROTENSET0_PROTREG18_Pos (18UL) /!< Position of PROTREG18 field. /
emilmont	80:8e73be2a2ac1	3277	#define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /!< Bit mask of PROTREG18 field. /
emilmont	80:8e73be2a2ac1	3278	#define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3279	#define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3280	#define MPU_PROTENSET0_PROTREG18_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3281
emilmont	80:8e73be2a2ac1	3282	/* Bit 17 : Protection enable for region 17. */
emilmont	80:8e73be2a2ac1	3283	#define MPU_PROTENSET0_PROTREG17_Pos (17UL) /!< Position of PROTREG17 field. /
emilmont	80:8e73be2a2ac1	3284	#define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /!< Bit mask of PROTREG17 field. /
emilmont	80:8e73be2a2ac1	3285	#define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3286	#define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3287	#define MPU_PROTENSET0_PROTREG17_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3288
emilmont	80:8e73be2a2ac1	3289	/* Bit 16 : Protection enable for region 16. */
emilmont	80:8e73be2a2ac1	3290	#define MPU_PROTENSET0_PROTREG16_Pos (16UL) /!< Position of PROTREG16 field. /
emilmont	80:8e73be2a2ac1	3291	#define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /!< Bit mask of PROTREG16 field. /
emilmont	80:8e73be2a2ac1	3292	#define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3293	#define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3294	#define MPU_PROTENSET0_PROTREG16_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3295
emilmont	80:8e73be2a2ac1	3296	/* Bit 15 : Protection enable for region 15. */
emilmont	80:8e73be2a2ac1	3297	#define MPU_PROTENSET0_PROTREG15_Pos (15UL) /!< Position of PROTREG15 field. /
emilmont	80:8e73be2a2ac1	3298	#define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /!< Bit mask of PROTREG15 field. /
emilmont	80:8e73be2a2ac1	3299	#define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3300	#define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3301	#define MPU_PROTENSET0_PROTREG15_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3302
emilmont	80:8e73be2a2ac1	3303	/* Bit 14 : Protection enable for region 14. */
emilmont	80:8e73be2a2ac1	3304	#define MPU_PROTENSET0_PROTREG14_Pos (14UL) /!< Position of PROTREG14 field. /
emilmont	80:8e73be2a2ac1	3305	#define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /!< Bit mask of PROTREG14 field. /
emilmont	80:8e73be2a2ac1	3306	#define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3307	#define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3308	#define MPU_PROTENSET0_PROTREG14_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3309
emilmont	80:8e73be2a2ac1	3310	/* Bit 13 : Protection enable for region 13. */
emilmont	80:8e73be2a2ac1	3311	#define MPU_PROTENSET0_PROTREG13_Pos (13UL) /!< Position of PROTREG13 field. /
emilmont	80:8e73be2a2ac1	3312	#define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /!< Bit mask of PROTREG13 field. /
emilmont	80:8e73be2a2ac1	3313	#define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3314	#define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3315	#define MPU_PROTENSET0_PROTREG13_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3316
emilmont	80:8e73be2a2ac1	3317	/* Bit 12 : Protection enable for region 12. */
emilmont	80:8e73be2a2ac1	3318	#define MPU_PROTENSET0_PROTREG12_Pos (12UL) /!< Position of PROTREG12 field. /
emilmont	80:8e73be2a2ac1	3319	#define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /!< Bit mask of PROTREG12 field. /
emilmont	80:8e73be2a2ac1	3320	#define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3321	#define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3322	#define MPU_PROTENSET0_PROTREG12_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3323
emilmont	80:8e73be2a2ac1	3324	/* Bit 11 : Protection enable for region 11. */
emilmont	80:8e73be2a2ac1	3325	#define MPU_PROTENSET0_PROTREG11_Pos (11UL) /!< Position of PROTREG11 field. /
emilmont	80:8e73be2a2ac1	3326	#define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /!< Bit mask of PROTREG11 field. /
emilmont	80:8e73be2a2ac1	3327	#define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3328	#define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3329	#define MPU_PROTENSET0_PROTREG11_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3330
emilmont	80:8e73be2a2ac1	3331	/* Bit 10 : Protection enable for region 10. */
emilmont	80:8e73be2a2ac1	3332	#define MPU_PROTENSET0_PROTREG10_Pos (10UL) /!< Position of PROTREG10 field. /
emilmont	80:8e73be2a2ac1	3333	#define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /!< Bit mask of PROTREG10 field. /
emilmont	80:8e73be2a2ac1	3334	#define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3335	#define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3336	#define MPU_PROTENSET0_PROTREG10_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3337
emilmont	80:8e73be2a2ac1	3338	/* Bit 9 : Protection enable for region 9. */
emilmont	80:8e73be2a2ac1	3339	#define MPU_PROTENSET0_PROTREG9_Pos (9UL) /!< Position of PROTREG9 field. /
emilmont	80:8e73be2a2ac1	3340	#define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /!< Bit mask of PROTREG9 field. /
emilmont	80:8e73be2a2ac1	3341	#define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3342	#define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3343	#define MPU_PROTENSET0_PROTREG9_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3344
emilmont	80:8e73be2a2ac1	3345	/* Bit 8 : Protection enable for region 8. */
emilmont	80:8e73be2a2ac1	3346	#define MPU_PROTENSET0_PROTREG8_Pos (8UL) /!< Position of PROTREG8 field. /
emilmont	80:8e73be2a2ac1	3347	#define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /!< Bit mask of PROTREG8 field. /
emilmont	80:8e73be2a2ac1	3348	#define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3349	#define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3350	#define MPU_PROTENSET0_PROTREG8_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3351
emilmont	80:8e73be2a2ac1	3352	/* Bit 7 : Protection enable for region 7. */
emilmont	80:8e73be2a2ac1	3353	#define MPU_PROTENSET0_PROTREG7_Pos (7UL) /!< Position of PROTREG7 field. /
emilmont	80:8e73be2a2ac1	3354	#define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /!< Bit mask of PROTREG7 field. /
emilmont	80:8e73be2a2ac1	3355	#define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3356	#define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3357	#define MPU_PROTENSET0_PROTREG7_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3358
emilmont	80:8e73be2a2ac1	3359	/* Bit 6 : Protection enable for region 6. */
emilmont	80:8e73be2a2ac1	3360	#define MPU_PROTENSET0_PROTREG6_Pos (6UL) /!< Position of PROTREG6 field. /
emilmont	80:8e73be2a2ac1	3361	#define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /!< Bit mask of PROTREG6 field. /
emilmont	80:8e73be2a2ac1	3362	#define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3363	#define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3364	#define MPU_PROTENSET0_PROTREG6_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3365
emilmont	80:8e73be2a2ac1	3366	/* Bit 5 : Protection enable for region 5. */
emilmont	80:8e73be2a2ac1	3367	#define MPU_PROTENSET0_PROTREG5_Pos (5UL) /!< Position of PROTREG5 field. /
emilmont	80:8e73be2a2ac1	3368	#define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /!< Bit mask of PROTREG5 field. /
emilmont	80:8e73be2a2ac1	3369	#define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3370	#define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3371	#define MPU_PROTENSET0_PROTREG5_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3372
emilmont	80:8e73be2a2ac1	3373	/* Bit 4 : Protection enable for region 4. */
emilmont	80:8e73be2a2ac1	3374	#define MPU_PROTENSET0_PROTREG4_Pos (4UL) /!< Position of PROTREG4 field. /
emilmont	80:8e73be2a2ac1	3375	#define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /!< Bit mask of PROTREG4 field. /
emilmont	80:8e73be2a2ac1	3376	#define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3377	#define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3378	#define MPU_PROTENSET0_PROTREG4_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3379
emilmont	80:8e73be2a2ac1	3380	/* Bit 3 : Protection enable for region 3. */
emilmont	80:8e73be2a2ac1	3381	#define MPU_PROTENSET0_PROTREG3_Pos (3UL) /!< Position of PROTREG3 field. /
emilmont	80:8e73be2a2ac1	3382	#define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /!< Bit mask of PROTREG3 field. /
emilmont	80:8e73be2a2ac1	3383	#define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3384	#define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3385	#define MPU_PROTENSET0_PROTREG3_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3386
emilmont	80:8e73be2a2ac1	3387	/* Bit 2 : Protection enable for region 2. */
emilmont	80:8e73be2a2ac1	3388	#define MPU_PROTENSET0_PROTREG2_Pos (2UL) /!< Position of PROTREG2 field. /
emilmont	80:8e73be2a2ac1	3389	#define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /!< Bit mask of PROTREG2 field. /
emilmont	80:8e73be2a2ac1	3390	#define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3391	#define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3392	#define MPU_PROTENSET0_PROTREG2_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3393
emilmont	80:8e73be2a2ac1	3394	/* Bit 1 : Protection enable for region 1. */
emilmont	80:8e73be2a2ac1	3395	#define MPU_PROTENSET0_PROTREG1_Pos (1UL) /!< Position of PROTREG1 field. /
emilmont	80:8e73be2a2ac1	3396	#define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /!< Bit mask of PROTREG1 field. /
emilmont	80:8e73be2a2ac1	3397	#define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3398	#define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3399	#define MPU_PROTENSET0_PROTREG1_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3400
emilmont	80:8e73be2a2ac1	3401	/* Bit 0 : Protection enable for region 0. */
emilmont	80:8e73be2a2ac1	3402	#define MPU_PROTENSET0_PROTREG0_Pos (0UL) /!< Position of PROTREG0 field. /
emilmont	80:8e73be2a2ac1	3403	#define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /!< Bit mask of PROTREG0 field. /
emilmont	80:8e73be2a2ac1	3404	#define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3405	#define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3406	#define MPU_PROTENSET0_PROTREG0_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3407
emilmont	80:8e73be2a2ac1	3408	/* Register: MPU_PROTENSET1 */
Kojto	97:433970e64889	3409	/* Description: Erase and write protection bit enable set register. */
emilmont	80:8e73be2a2ac1	3410
emilmont	80:8e73be2a2ac1	3411	/* Bit 31 : Protection enable for region 63. */
emilmont	80:8e73be2a2ac1	3412	#define MPU_PROTENSET1_PROTREG63_Pos (31UL) /!< Position of PROTREG63 field. /
emilmont	80:8e73be2a2ac1	3413	#define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /!< Bit mask of PROTREG63 field. /
emilmont	80:8e73be2a2ac1	3414	#define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3415	#define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3416	#define MPU_PROTENSET1_PROTREG63_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3417
emilmont	80:8e73be2a2ac1	3418	/* Bit 30 : Protection enable for region 62. */
emilmont	80:8e73be2a2ac1	3419	#define MPU_PROTENSET1_PROTREG62_Pos (30UL) /!< Position of PROTREG62 field. /
emilmont	80:8e73be2a2ac1	3420	#define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /!< Bit mask of PROTREG62 field. /
emilmont	80:8e73be2a2ac1	3421	#define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3422	#define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3423	#define MPU_PROTENSET1_PROTREG62_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3424
emilmont	80:8e73be2a2ac1	3425	/* Bit 29 : Protection enable for region 61. */
emilmont	80:8e73be2a2ac1	3426	#define MPU_PROTENSET1_PROTREG61_Pos (29UL) /!< Position of PROTREG61 field. /
emilmont	80:8e73be2a2ac1	3427	#define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /!< Bit mask of PROTREG61 field. /
emilmont	80:8e73be2a2ac1	3428	#define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3429	#define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3430	#define MPU_PROTENSET1_PROTREG61_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3431
emilmont	80:8e73be2a2ac1	3432	/* Bit 28 : Protection enable for region 60. */
emilmont	80:8e73be2a2ac1	3433	#define MPU_PROTENSET1_PROTREG60_Pos (28UL) /!< Position of PROTREG60 field. /
emilmont	80:8e73be2a2ac1	3434	#define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /!< Bit mask of PROTREG60 field. /
emilmont	80:8e73be2a2ac1	3435	#define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3436	#define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3437	#define MPU_PROTENSET1_PROTREG60_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3438
emilmont	80:8e73be2a2ac1	3439	/* Bit 27 : Protection enable for region 59. */
emilmont	80:8e73be2a2ac1	3440	#define MPU_PROTENSET1_PROTREG59_Pos (27UL) /!< Position of PROTREG59 field. /
emilmont	80:8e73be2a2ac1	3441	#define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /!< Bit mask of PROTREG59 field. /
emilmont	80:8e73be2a2ac1	3442	#define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3443	#define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3444	#define MPU_PROTENSET1_PROTREG59_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3445
emilmont	80:8e73be2a2ac1	3446	/* Bit 26 : Protection enable for region 58. */
emilmont	80:8e73be2a2ac1	3447	#define MPU_PROTENSET1_PROTREG58_Pos (26UL) /!< Position of PROTREG58 field. /
emilmont	80:8e73be2a2ac1	3448	#define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /!< Bit mask of PROTREG58 field. /
emilmont	80:8e73be2a2ac1	3449	#define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3450	#define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3451	#define MPU_PROTENSET1_PROTREG58_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3452
emilmont	80:8e73be2a2ac1	3453	/* Bit 25 : Protection enable for region 57. */
emilmont	80:8e73be2a2ac1	3454	#define MPU_PROTENSET1_PROTREG57_Pos (25UL) /!< Position of PROTREG57 field. /
emilmont	80:8e73be2a2ac1	3455	#define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /!< Bit mask of PROTREG57 field. /
emilmont	80:8e73be2a2ac1	3456	#define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3457	#define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3458	#define MPU_PROTENSET1_PROTREG57_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3459
emilmont	80:8e73be2a2ac1	3460	/* Bit 24 : Protection enable for region 56. */
emilmont	80:8e73be2a2ac1	3461	#define MPU_PROTENSET1_PROTREG56_Pos (24UL) /!< Position of PROTREG56 field. /
emilmont	80:8e73be2a2ac1	3462	#define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /!< Bit mask of PROTREG56 field. /
emilmont	80:8e73be2a2ac1	3463	#define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3464	#define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3465	#define MPU_PROTENSET1_PROTREG56_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3466
emilmont	80:8e73be2a2ac1	3467	/* Bit 23 : Protection enable for region 55. */
emilmont	80:8e73be2a2ac1	3468	#define MPU_PROTENSET1_PROTREG55_Pos (23UL) /!< Position of PROTREG55 field. /
emilmont	80:8e73be2a2ac1	3469	#define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /!< Bit mask of PROTREG55 field. /
emilmont	80:8e73be2a2ac1	3470	#define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3471	#define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3472	#define MPU_PROTENSET1_PROTREG55_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3473
emilmont	80:8e73be2a2ac1	3474	/* Bit 22 : Protection enable for region 54. */
emilmont	80:8e73be2a2ac1	3475	#define MPU_PROTENSET1_PROTREG54_Pos (22UL) /!< Position of PROTREG54 field. /
emilmont	80:8e73be2a2ac1	3476	#define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /!< Bit mask of PROTREG54 field. /
emilmont	80:8e73be2a2ac1	3477	#define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3478	#define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3479	#define MPU_PROTENSET1_PROTREG54_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3480
emilmont	80:8e73be2a2ac1	3481	/* Bit 21 : Protection enable for region 53. */
emilmont	80:8e73be2a2ac1	3482	#define MPU_PROTENSET1_PROTREG53_Pos (21UL) /!< Position of PROTREG53 field. /
emilmont	80:8e73be2a2ac1	3483	#define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /!< Bit mask of PROTREG53 field. /
emilmont	80:8e73be2a2ac1	3484	#define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3485	#define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3486	#define MPU_PROTENSET1_PROTREG53_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3487
emilmont	80:8e73be2a2ac1	3488	/* Bit 20 : Protection enable for region 52. */
emilmont	80:8e73be2a2ac1	3489	#define MPU_PROTENSET1_PROTREG52_Pos (20UL) /!< Position of PROTREG52 field. /
emilmont	80:8e73be2a2ac1	3490	#define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /!< Bit mask of PROTREG52 field. /
emilmont	80:8e73be2a2ac1	3491	#define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3492	#define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3493	#define MPU_PROTENSET1_PROTREG52_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3494
emilmont	80:8e73be2a2ac1	3495	/* Bit 19 : Protection enable for region 51. */
emilmont	80:8e73be2a2ac1	3496	#define MPU_PROTENSET1_PROTREG51_Pos (19UL) /!< Position of PROTREG51 field. /
emilmont	80:8e73be2a2ac1	3497	#define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /!< Bit mask of PROTREG51 field. /
emilmont	80:8e73be2a2ac1	3498	#define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3499	#define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3500	#define MPU_PROTENSET1_PROTREG51_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3501
emilmont	80:8e73be2a2ac1	3502	/* Bit 18 : Protection enable for region 50. */
emilmont	80:8e73be2a2ac1	3503	#define MPU_PROTENSET1_PROTREG50_Pos (18UL) /!< Position of PROTREG50 field. /
emilmont	80:8e73be2a2ac1	3504	#define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /!< Bit mask of PROTREG50 field. /
emilmont	80:8e73be2a2ac1	3505	#define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3506	#define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3507	#define MPU_PROTENSET1_PROTREG50_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3508
emilmont	80:8e73be2a2ac1	3509	/* Bit 17 : Protection enable for region 49. */
emilmont	80:8e73be2a2ac1	3510	#define MPU_PROTENSET1_PROTREG49_Pos (17UL) /!< Position of PROTREG49 field. /
emilmont	80:8e73be2a2ac1	3511	#define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /!< Bit mask of PROTREG49 field. /
emilmont	80:8e73be2a2ac1	3512	#define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3513	#define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3514	#define MPU_PROTENSET1_PROTREG49_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3515
emilmont	80:8e73be2a2ac1	3516	/* Bit 16 : Protection enable for region 48. */
emilmont	80:8e73be2a2ac1	3517	#define MPU_PROTENSET1_PROTREG48_Pos (16UL) /!< Position of PROTREG48 field. /
emilmont	80:8e73be2a2ac1	3518	#define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /!< Bit mask of PROTREG48 field. /
emilmont	80:8e73be2a2ac1	3519	#define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3520	#define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3521	#define MPU_PROTENSET1_PROTREG48_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3522
emilmont	80:8e73be2a2ac1	3523	/* Bit 15 : Protection enable for region 47. */
emilmont	80:8e73be2a2ac1	3524	#define MPU_PROTENSET1_PROTREG47_Pos (15UL) /!< Position of PROTREG47 field. /
emilmont	80:8e73be2a2ac1	3525	#define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /!< Bit mask of PROTREG47 field. /
emilmont	80:8e73be2a2ac1	3526	#define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3527	#define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3528	#define MPU_PROTENSET1_PROTREG47_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3529
emilmont	80:8e73be2a2ac1	3530	/* Bit 14 : Protection enable for region 46. */
emilmont	80:8e73be2a2ac1	3531	#define MPU_PROTENSET1_PROTREG46_Pos (14UL) /!< Position of PROTREG46 field. /
emilmont	80:8e73be2a2ac1	3532	#define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /!< Bit mask of PROTREG46 field. /
emilmont	80:8e73be2a2ac1	3533	#define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3534	#define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3535	#define MPU_PROTENSET1_PROTREG46_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3536
emilmont	80:8e73be2a2ac1	3537	/* Bit 13 : Protection enable for region 45. */
emilmont	80:8e73be2a2ac1	3538	#define MPU_PROTENSET1_PROTREG45_Pos (13UL) /!< Position of PROTREG45 field. /
emilmont	80:8e73be2a2ac1	3539	#define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /!< Bit mask of PROTREG45 field. /
emilmont	80:8e73be2a2ac1	3540	#define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3541	#define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3542	#define MPU_PROTENSET1_PROTREG45_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3543
emilmont	80:8e73be2a2ac1	3544	/* Bit 12 : Protection enable for region 44. */
emilmont	80:8e73be2a2ac1	3545	#define MPU_PROTENSET1_PROTREG44_Pos (12UL) /!< Position of PROTREG44 field. /
emilmont	80:8e73be2a2ac1	3546	#define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /!< Bit mask of PROTREG44 field. /
emilmont	80:8e73be2a2ac1	3547	#define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3548	#define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3549	#define MPU_PROTENSET1_PROTREG44_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3550
emilmont	80:8e73be2a2ac1	3551	/* Bit 11 : Protection enable for region 43. */
emilmont	80:8e73be2a2ac1	3552	#define MPU_PROTENSET1_PROTREG43_Pos (11UL) /!< Position of PROTREG43 field. /
emilmont	80:8e73be2a2ac1	3553	#define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /!< Bit mask of PROTREG43 field. /
emilmont	80:8e73be2a2ac1	3554	#define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3555	#define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3556	#define MPU_PROTENSET1_PROTREG43_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3557
emilmont	80:8e73be2a2ac1	3558	/* Bit 10 : Protection enable for region 42. */
emilmont	80:8e73be2a2ac1	3559	#define MPU_PROTENSET1_PROTREG42_Pos (10UL) /!< Position of PROTREG42 field. /
emilmont	80:8e73be2a2ac1	3560	#define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /!< Bit mask of PROTREG42 field. /
emilmont	80:8e73be2a2ac1	3561	#define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3562	#define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3563	#define MPU_PROTENSET1_PROTREG42_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3564
emilmont	80:8e73be2a2ac1	3565	/* Bit 9 : Protection enable for region 41. */
emilmont	80:8e73be2a2ac1	3566	#define MPU_PROTENSET1_PROTREG41_Pos (9UL) /!< Position of PROTREG41 field. /
emilmont	80:8e73be2a2ac1	3567	#define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /!< Bit mask of PROTREG41 field. /
emilmont	80:8e73be2a2ac1	3568	#define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3569	#define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3570	#define MPU_PROTENSET1_PROTREG41_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3571
emilmont	80:8e73be2a2ac1	3572	/* Bit 8 : Protection enable for region 40. */
emilmont	80:8e73be2a2ac1	3573	#define MPU_PROTENSET1_PROTREG40_Pos (8UL) /!< Position of PROTREG40 field. /
emilmont	80:8e73be2a2ac1	3574	#define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /!< Bit mask of PROTREG40 field. /
emilmont	80:8e73be2a2ac1	3575	#define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3576	#define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3577	#define MPU_PROTENSET1_PROTREG40_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3578
emilmont	80:8e73be2a2ac1	3579	/* Bit 7 : Protection enable for region 39. */
emilmont	80:8e73be2a2ac1	3580	#define MPU_PROTENSET1_PROTREG39_Pos (7UL) /!< Position of PROTREG39 field. /
emilmont	80:8e73be2a2ac1	3581	#define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /!< Bit mask of PROTREG39 field. /
emilmont	80:8e73be2a2ac1	3582	#define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3583	#define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3584	#define MPU_PROTENSET1_PROTREG39_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3585
emilmont	80:8e73be2a2ac1	3586	/* Bit 6 : Protection enable for region 38. */
emilmont	80:8e73be2a2ac1	3587	#define MPU_PROTENSET1_PROTREG38_Pos (6UL) /!< Position of PROTREG38 field. /
emilmont	80:8e73be2a2ac1	3588	#define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /!< Bit mask of PROTREG38 field. /
emilmont	80:8e73be2a2ac1	3589	#define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3590	#define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3591	#define MPU_PROTENSET1_PROTREG38_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3592
emilmont	80:8e73be2a2ac1	3593	/* Bit 5 : Protection enable for region 37. */
emilmont	80:8e73be2a2ac1	3594	#define MPU_PROTENSET1_PROTREG37_Pos (5UL) /!< Position of PROTREG37 field. /
emilmont	80:8e73be2a2ac1	3595	#define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /!< Bit mask of PROTREG37 field. /
emilmont	80:8e73be2a2ac1	3596	#define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3597	#define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3598	#define MPU_PROTENSET1_PROTREG37_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3599
emilmont	80:8e73be2a2ac1	3600	/* Bit 4 : Protection enable for region 36. */
emilmont	80:8e73be2a2ac1	3601	#define MPU_PROTENSET1_PROTREG36_Pos (4UL) /!< Position of PROTREG36 field. /
emilmont	80:8e73be2a2ac1	3602	#define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /!< Bit mask of PROTREG36 field. /
emilmont	80:8e73be2a2ac1	3603	#define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3604	#define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3605	#define MPU_PROTENSET1_PROTREG36_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3606
emilmont	80:8e73be2a2ac1	3607	/* Bit 3 : Protection enable for region 35. */
emilmont	80:8e73be2a2ac1	3608	#define MPU_PROTENSET1_PROTREG35_Pos (3UL) /!< Position of PROTREG35 field. /
emilmont	80:8e73be2a2ac1	3609	#define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /!< Bit mask of PROTREG35 field. /
emilmont	80:8e73be2a2ac1	3610	#define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3611	#define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3612	#define MPU_PROTENSET1_PROTREG35_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3613
emilmont	80:8e73be2a2ac1	3614	/* Bit 2 : Protection enable for region 34. */
emilmont	80:8e73be2a2ac1	3615	#define MPU_PROTENSET1_PROTREG34_Pos (2UL) /!< Position of PROTREG34 field. /
emilmont	80:8e73be2a2ac1	3616	#define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /!< Bit mask of PROTREG34 field. /
emilmont	80:8e73be2a2ac1	3617	#define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3618	#define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3619	#define MPU_PROTENSET1_PROTREG34_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3620
emilmont	80:8e73be2a2ac1	3621	/* Bit 1 : Protection enable for region 33. */
emilmont	80:8e73be2a2ac1	3622	#define MPU_PROTENSET1_PROTREG33_Pos (1UL) /!< Position of PROTREG33 field. /
emilmont	80:8e73be2a2ac1	3623	#define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /!< Bit mask of PROTREG33 field. /
emilmont	80:8e73be2a2ac1	3624	#define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3625	#define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3626	#define MPU_PROTENSET1_PROTREG33_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3627
emilmont	80:8e73be2a2ac1	3628	/* Bit 0 : Protection enable for region 32. */
emilmont	80:8e73be2a2ac1	3629	#define MPU_PROTENSET1_PROTREG32_Pos (0UL) /!< Position of PROTREG32 field. /
emilmont	80:8e73be2a2ac1	3630	#define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /!< Bit mask of PROTREG32 field. /
emilmont	80:8e73be2a2ac1	3631	#define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3632	#define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3633	#define MPU_PROTENSET1_PROTREG32_Set (1UL) /!< Enable protection on write. /
emilmont	80:8e73be2a2ac1	3634
emilmont	80:8e73be2a2ac1	3635	/* Register: MPU_DISABLEINDEBUG */
Kojto	97:433970e64889	3636	/* Description: Disable erase and write protection mechanism in debug mode. */
emilmont	80:8e73be2a2ac1	3637
emilmont	80:8e73be2a2ac1	3638	/* Bit 0 : Disable protection mechanism in debug mode. */
emilmont	80:8e73be2a2ac1	3639	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /!< Position of DISABLEINDEBUG field. /
emilmont	80:8e73be2a2ac1	3640	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /!< Bit mask of DISABLEINDEBUG field. /
emilmont	80:8e73be2a2ac1	3641	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /!< Protection enabled. /
emilmont	80:8e73be2a2ac1	3642	#define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /!< Protection disabled. /
emilmont	80:8e73be2a2ac1	3643
Kojto	97:433970e64889	3644	/* Register: MPU_PROTBLOCKSIZE */
Kojto	97:433970e64889	3645	/* Description: Erase and write protection block size. */
Kojto	97:433970e64889	3646
Kojto	97:433970e64889	3647	/* Bits 1..0 : Erase and write protection block size. */
Kojto	97:433970e64889	3648	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos (0UL) /!< Position of PROTBLOCKSIZE field. /
Kojto	97:433970e64889	3649	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Msk (0x3UL << MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_Pos) /!< Bit mask of PROTBLOCKSIZE field. /
Kojto	97:433970e64889	3650	#define MPU_PROTBLOCKSIZE_PROTBLOCKSIZE_4k (0UL) /!< Erase and write protection block size is 4k. /
Kojto	97:433970e64889	3651
emilmont	80:8e73be2a2ac1	3652
emilmont	80:8e73be2a2ac1	3653	/* Peripheral: NVMC */
emilmont	80:8e73be2a2ac1	3654	/* Description: Non Volatile Memory Controller. */
emilmont	80:8e73be2a2ac1	3655
emilmont	80:8e73be2a2ac1	3656	/* Register: NVMC_READY */
emilmont	80:8e73be2a2ac1	3657	/* Description: Ready flag. */
emilmont	80:8e73be2a2ac1	3658
emilmont	80:8e73be2a2ac1	3659	/* Bit 0 : NVMC ready. */
emilmont	80:8e73be2a2ac1	3660	#define NVMC_READY_READY_Pos (0UL) /!< Position of READY field. /
emilmont	80:8e73be2a2ac1	3661	#define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /!< Bit mask of READY field. /
emilmont	80:8e73be2a2ac1	3662	#define NVMC_READY_READY_Busy (0UL) /!< NVMC is busy (on-going write or erase operation). /
emilmont	80:8e73be2a2ac1	3663	#define NVMC_READY_READY_Ready (1UL) /!< NVMC is ready. /
emilmont	80:8e73be2a2ac1	3664
emilmont	80:8e73be2a2ac1	3665	/* Register: NVMC_CONFIG */
emilmont	80:8e73be2a2ac1	3666	/* Description: Configuration register. */
emilmont	80:8e73be2a2ac1	3667
emilmont	80:8e73be2a2ac1	3668	/* Bits 1..0 : Program write enable. */
emilmont	80:8e73be2a2ac1	3669	#define NVMC_CONFIG_WEN_Pos (0UL) /!< Position of WEN field. /
emilmont	80:8e73be2a2ac1	3670	#define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /!< Bit mask of WEN field. /
emilmont	80:8e73be2a2ac1	3671	#define NVMC_CONFIG_WEN_Ren (0x00UL) /!< Read only access. /
emilmont	80:8e73be2a2ac1	3672	#define NVMC_CONFIG_WEN_Wen (0x01UL) /!< Write enabled. /
emilmont	80:8e73be2a2ac1	3673	#define NVMC_CONFIG_WEN_Een (0x02UL) /!< Erase enabled. /
emilmont	80:8e73be2a2ac1	3674
emilmont	80:8e73be2a2ac1	3675	/* Register: NVMC_ERASEALL */
emilmont	80:8e73be2a2ac1	3676	/* Description: Register for erasing all non-volatile user memory. */
emilmont	80:8e73be2a2ac1	3677
emilmont	80:8e73be2a2ac1	3678	/* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
emilmont	80:8e73be2a2ac1	3679	#define NVMC_ERASEALL_ERASEALL_Pos (0UL) /!< Position of ERASEALL field. /
emilmont	80:8e73be2a2ac1	3680	#define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /!< Bit mask of ERASEALL field. /
emilmont	80:8e73be2a2ac1	3681	#define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /!< No operation. /
emilmont	80:8e73be2a2ac1	3682	#define NVMC_ERASEALL_ERASEALL_Erase (1UL) /!< Start chip erase. /
emilmont	80:8e73be2a2ac1	3683
emilmont	80:8e73be2a2ac1	3684	/* Register: NVMC_ERASEUICR */
emilmont	80:8e73be2a2ac1	3685	/* Description: Register for start erasing User Information Congfiguration Registers. */
emilmont	80:8e73be2a2ac1	3686
emilmont	80:8e73be2a2ac1	3687	/* Bit 0 : It can only be used when all contents of code region 1 are erased. */
emilmont	80:8e73be2a2ac1	3688	#define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /!< Position of ERASEUICR field. /
emilmont	80:8e73be2a2ac1	3689	#define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /!< Bit mask of ERASEUICR field. /
emilmont	80:8e73be2a2ac1	3690	#define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /!< No operation. /
emilmont	80:8e73be2a2ac1	3691	#define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /!< Start UICR erase. /
emilmont	80:8e73be2a2ac1	3692
emilmont	80:8e73be2a2ac1	3693
emilmont	80:8e73be2a2ac1	3694	/* Peripheral: POWER */
emilmont	80:8e73be2a2ac1	3695	/* Description: Power Control. */
emilmont	80:8e73be2a2ac1	3696
emilmont	80:8e73be2a2ac1	3697	/* Register: POWER_INTENSET */
emilmont	80:8e73be2a2ac1	3698	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	3699
emilmont	80:8e73be2a2ac1	3700	/* Bit 2 : Enable interrupt on POFWARN event. */
emilmont	80:8e73be2a2ac1	3701	#define POWER_INTENSET_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
emilmont	80:8e73be2a2ac1	3702	#define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /!< Bit mask of POFWARN field. /
emilmont	80:8e73be2a2ac1	3703	#define POWER_INTENSET_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	3704	#define POWER_INTENSET_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	3705	#define POWER_INTENSET_POFWARN_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	3706
emilmont	80:8e73be2a2ac1	3707	/* Register: POWER_INTENCLR */
emilmont	80:8e73be2a2ac1	3708	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	3709
emilmont	80:8e73be2a2ac1	3710	/* Bit 2 : Disable interrupt on POFWARN event. */
emilmont	80:8e73be2a2ac1	3711	#define POWER_INTENCLR_POFWARN_Pos (2UL) /!< Position of POFWARN field. /
emilmont	80:8e73be2a2ac1	3712	#define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /!< Bit mask of POFWARN field. /
emilmont	80:8e73be2a2ac1	3713	#define POWER_INTENCLR_POFWARN_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	3714	#define POWER_INTENCLR_POFWARN_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	3715	#define POWER_INTENCLR_POFWARN_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	3716
emilmont	80:8e73be2a2ac1	3717	/* Register: POWER_RESETREAS */
emilmont	80:8e73be2a2ac1	3718	/* Description: Reset reason. */
emilmont	80:8e73be2a2ac1	3719
emilmont	80:8e73be2a2ac1	3720	/* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
emilmont	80:8e73be2a2ac1	3721	#define POWER_RESETREAS_DIF_Pos (18UL) /!< Position of DIF field. /
emilmont	80:8e73be2a2ac1	3722	#define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /!< Bit mask of DIF field. /
emilmont	80:8e73be2a2ac1	3723
emilmont	80:8e73be2a2ac1	3724	/* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
emilmont	80:8e73be2a2ac1	3725	#define POWER_RESETREAS_LPCOMP_Pos (17UL) /!< Position of LPCOMP field. /
emilmont	80:8e73be2a2ac1	3726	#define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /!< Bit mask of LPCOMP field. /
emilmont	80:8e73be2a2ac1	3727
emilmont	80:8e73be2a2ac1	3728	/* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
emilmont	80:8e73be2a2ac1	3729	#define POWER_RESETREAS_OFF_Pos (16UL) /!< Position of OFF field. /
emilmont	80:8e73be2a2ac1	3730	#define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /!< Bit mask of OFF field. /
emilmont	80:8e73be2a2ac1	3731
emilmont	80:8e73be2a2ac1	3732	/* Bit 3 : Reset from CPU lock-up detected. */
emilmont	80:8e73be2a2ac1	3733	#define POWER_RESETREAS_LOCKUP_Pos (3UL) /!< Position of LOCKUP field. /
emilmont	80:8e73be2a2ac1	3734	#define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /!< Bit mask of LOCKUP field. /
emilmont	80:8e73be2a2ac1	3735
emilmont	80:8e73be2a2ac1	3736	/* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
emilmont	80:8e73be2a2ac1	3737	#define POWER_RESETREAS_SREQ_Pos (2UL) /!< Position of SREQ field. /
emilmont	80:8e73be2a2ac1	3738	#define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /!< Bit mask of SREQ field. /
emilmont	80:8e73be2a2ac1	3739
emilmont	80:8e73be2a2ac1	3740	/* Bit 1 : Reset from watchdog detected. */
emilmont	80:8e73be2a2ac1	3741	#define POWER_RESETREAS_DOG_Pos (1UL) /!< Position of DOG field. /
emilmont	80:8e73be2a2ac1	3742	#define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /!< Bit mask of DOG field. /
emilmont	80:8e73be2a2ac1	3743
emilmont	80:8e73be2a2ac1	3744	/* Bit 0 : Reset from pin-reset detected. */
emilmont	80:8e73be2a2ac1	3745	#define POWER_RESETREAS_RESETPIN_Pos (0UL) /!< Position of RESETPIN field. /
emilmont	80:8e73be2a2ac1	3746	#define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /!< Bit mask of RESETPIN field. /
emilmont	80:8e73be2a2ac1	3747
Kojto	97:433970e64889	3748	/* Register: POWER_RAMSTATUS */
Kojto	97:433970e64889	3749	/* Description: Ram status register. */
Kojto	97:433970e64889	3750
Kojto	97:433970e64889	3751	/* Bit 3 : RAM block 3 status. */
Kojto	97:433970e64889	3752	#define POWER_RAMSTATUS_RAMBLOCK3_Pos (3UL) /!< Position of RAMBLOCK3 field. /
Kojto	97:433970e64889	3753	#define POWER_RAMSTATUS_RAMBLOCK3_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK3_Pos) /!< Bit mask of RAMBLOCK3 field. /
Kojto	97:433970e64889	3754	#define POWER_RAMSTATUS_RAMBLOCK3_Off (0UL) /!< RAM block 3 is off or powering up. /
Kojto	97:433970e64889	3755	#define POWER_RAMSTATUS_RAMBLOCK3_On (1UL) /!< RAM block 3 is on. /
Kojto	97:433970e64889	3756
Kojto	97:433970e64889	3757	/* Bit 2 : RAM block 2 status. */
Kojto	97:433970e64889	3758	#define POWER_RAMSTATUS_RAMBLOCK2_Pos (2UL) /!< Position of RAMBLOCK2 field. /
Kojto	97:433970e64889	3759	#define POWER_RAMSTATUS_RAMBLOCK2_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK2_Pos) /!< Bit mask of RAMBLOCK2 field. /
Kojto	97:433970e64889	3760	#define POWER_RAMSTATUS_RAMBLOCK2_Off (0UL) /!< RAM block 2 is off or powering up. /
Kojto	97:433970e64889	3761	#define POWER_RAMSTATUS_RAMBLOCK2_On (1UL) /!< RAM block 2 is on. /
Kojto	97:433970e64889	3762
Kojto	97:433970e64889	3763	/* Bit 1 : RAM block 1 status. */
Kojto	97:433970e64889	3764	#define POWER_RAMSTATUS_RAMBLOCK1_Pos (1UL) /!< Position of RAMBLOCK1 field. /
Kojto	97:433970e64889	3765	#define POWER_RAMSTATUS_RAMBLOCK1_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK1_Pos) /!< Bit mask of RAMBLOCK1 field. /
Kojto	97:433970e64889	3766	#define POWER_RAMSTATUS_RAMBLOCK1_Off (0UL) /!< RAM block 1 is off or powering up. /
Kojto	97:433970e64889	3767	#define POWER_RAMSTATUS_RAMBLOCK1_On (1UL) /!< RAM block 1 is on. /
Kojto	97:433970e64889	3768
Kojto	97:433970e64889	3769	/* Bit 0 : RAM block 0 status. */
Kojto	97:433970e64889	3770	#define POWER_RAMSTATUS_RAMBLOCK0_Pos (0UL) /!< Position of RAMBLOCK0 field. /
Kojto	97:433970e64889	3771	#define POWER_RAMSTATUS_RAMBLOCK0_Msk (0x1UL << POWER_RAMSTATUS_RAMBLOCK0_Pos) /!< Bit mask of RAMBLOCK0 field. /
Kojto	97:433970e64889	3772	#define POWER_RAMSTATUS_RAMBLOCK0_Off (0UL) /!< RAM block 0 is off or powering up. /
Kojto	97:433970e64889	3773	#define POWER_RAMSTATUS_RAMBLOCK0_On (1UL) /!< RAM block 0 is on. /
Kojto	97:433970e64889	3774
emilmont	80:8e73be2a2ac1	3775	/* Register: POWER_SYSTEMOFF */
emilmont	80:8e73be2a2ac1	3776	/* Description: System off register. */
emilmont	80:8e73be2a2ac1	3777
emilmont	80:8e73be2a2ac1	3778	/* Bit 0 : Enter system off mode. */
emilmont	80:8e73be2a2ac1	3779	#define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /!< Position of SYSTEMOFF field. /
emilmont	80:8e73be2a2ac1	3780	#define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /!< Bit mask of SYSTEMOFF field. /
emilmont	80:8e73be2a2ac1	3781	#define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /!< Enter system off mode. /
emilmont	80:8e73be2a2ac1	3782
emilmont	80:8e73be2a2ac1	3783	/* Register: POWER_POFCON */
emilmont	80:8e73be2a2ac1	3784	/* Description: Power failure configuration. */
emilmont	80:8e73be2a2ac1	3785
emilmont	80:8e73be2a2ac1	3786	/* Bits 2..1 : Set threshold level. */
emilmont	80:8e73be2a2ac1	3787	#define POWER_POFCON_THRESHOLD_Pos (1UL) /!< Position of THRESHOLD field. /
emilmont	80:8e73be2a2ac1	3788	#define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /!< Bit mask of THRESHOLD field. /
emilmont	80:8e73be2a2ac1	3789	#define POWER_POFCON_THRESHOLD_V21 (0x00UL) /!< Set threshold to 2.1Volts. /
emilmont	80:8e73be2a2ac1	3790	#define POWER_POFCON_THRESHOLD_V23 (0x01UL) /!< Set threshold to 2.3Volts. /
emilmont	80:8e73be2a2ac1	3791	#define POWER_POFCON_THRESHOLD_V25 (0x02UL) /!< Set threshold to 2.5Volts. /
emilmont	80:8e73be2a2ac1	3792	#define POWER_POFCON_THRESHOLD_V27 (0x03UL) /!< Set threshold to 2.7Volts. /
emilmont	80:8e73be2a2ac1	3793
emilmont	80:8e73be2a2ac1	3794	/* Bit 0 : Power failure comparator enable. */
emilmont	80:8e73be2a2ac1	3795	#define POWER_POFCON_POF_Pos (0UL) /!< Position of POF field. /
emilmont	80:8e73be2a2ac1	3796	#define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /!< Bit mask of POF field. /
emilmont	80:8e73be2a2ac1	3797	#define POWER_POFCON_POF_Disabled (0UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	3798	#define POWER_POFCON_POF_Enabled (1UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	3799
emilmont	80:8e73be2a2ac1	3800	/* Register: POWER_GPREGRET */
emilmont	80:8e73be2a2ac1	3801	/* Description: General purpose retention register. This register is a retained register. */
emilmont	80:8e73be2a2ac1	3802
emilmont	80:8e73be2a2ac1	3803	/* Bits 7..0 : General purpose retention register. */
emilmont	80:8e73be2a2ac1	3804	#define POWER_GPREGRET_GPREGRET_Pos (0UL) /!< Position of GPREGRET field. /
emilmont	80:8e73be2a2ac1	3805	#define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /!< Bit mask of GPREGRET field. /
emilmont	80:8e73be2a2ac1	3806
emilmont	80:8e73be2a2ac1	3807	/* Register: POWER_RAMON */
emilmont	80:8e73be2a2ac1	3808	/* Description: Ram on/off. */
emilmont	80:8e73be2a2ac1	3809
emilmont	80:8e73be2a2ac1	3810	/* Bit 17 : RAM block 1 behaviour in OFF mode. */
emilmont	80:8e73be2a2ac1	3811	#define POWER_RAMON_OFFRAM1_Pos (17UL) /!< Position of OFFRAM1 field. /
emilmont	80:8e73be2a2ac1	3812	#define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /!< Bit mask of OFFRAM1 field. /
emilmont	80:8e73be2a2ac1	3813	#define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in OFF mode. /
emilmont	80:8e73be2a2ac1	3814	#define POWER_RAMON_OFFRAM1_RAM1On (1UL) /!< RAM block 1 ON in OFF mode. /
emilmont	80:8e73be2a2ac1	3815
emilmont	80:8e73be2a2ac1	3816	/* Bit 16 : RAM block 0 behaviour in OFF mode. */
emilmont	80:8e73be2a2ac1	3817	#define POWER_RAMON_OFFRAM0_Pos (16UL) /!< Position of OFFRAM0 field. /
emilmont	80:8e73be2a2ac1	3818	#define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /!< Bit mask of OFFRAM0 field. /
emilmont	80:8e73be2a2ac1	3819	#define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in OFF mode. /
emilmont	80:8e73be2a2ac1	3820	#define POWER_RAMON_OFFRAM0_RAM0On (1UL) /!< RAM block 0 ON in OFF mode. /
emilmont	80:8e73be2a2ac1	3821
emilmont	80:8e73be2a2ac1	3822	/* Bit 1 : RAM block 1 behaviour in ON mode. */
emilmont	80:8e73be2a2ac1	3823	#define POWER_RAMON_ONRAM1_Pos (1UL) /!< Position of ONRAM1 field. /
emilmont	80:8e73be2a2ac1	3824	#define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /!< Bit mask of ONRAM1 field. /
emilmont	80:8e73be2a2ac1	3825	#define POWER_RAMON_ONRAM1_RAM1Off (0UL) /!< RAM block 1 OFF in ON mode. /
emilmont	80:8e73be2a2ac1	3826	#define POWER_RAMON_ONRAM1_RAM1On (1UL) /!< RAM block 1 ON in ON mode. /
emilmont	80:8e73be2a2ac1	3827
emilmont	80:8e73be2a2ac1	3828	/* Bit 0 : RAM block 0 behaviour in ON mode. */
emilmont	80:8e73be2a2ac1	3829	#define POWER_RAMON_ONRAM0_Pos (0UL) /!< Position of ONRAM0 field. /
emilmont	80:8e73be2a2ac1	3830	#define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /!< Bit mask of ONRAM0 field. /
emilmont	80:8e73be2a2ac1	3831	#define POWER_RAMON_ONRAM0_RAM0Off (0UL) /!< RAM block 0 OFF in ON mode. /
emilmont	80:8e73be2a2ac1	3832	#define POWER_RAMON_ONRAM0_RAM0On (1UL) /!< RAM block 0 ON in ON mode. /
emilmont	80:8e73be2a2ac1	3833
emilmont	80:8e73be2a2ac1	3834	/* Register: POWER_RESET */
emilmont	80:8e73be2a2ac1	3835	/* Description: Pin reset functionality configuration register. This register is a retained register. */
emilmont	80:8e73be2a2ac1	3836
Kojto	97:433970e64889	3837	/* Bit 0 : Enable or disable pin reset in debug interface mode. */
emilmont	80:8e73be2a2ac1	3838	#define POWER_RESET_RESET_Pos (0UL) /!< Position of RESET field. /
emilmont	80:8e73be2a2ac1	3839	#define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /!< Bit mask of RESET field. /
emilmont	80:8e73be2a2ac1	3840	#define POWER_RESET_RESET_Disabled (0UL) /!< Pin reset in debug interface mode disabled. /
emilmont	80:8e73be2a2ac1	3841	#define POWER_RESET_RESET_Enabled (1UL) /!< Pin reset in debug interface mode enabled. /
emilmont	80:8e73be2a2ac1	3842
Kojto	97:433970e64889	3843	/* Register: POWER_RAMONB */
Kojto	97:433970e64889	3844	/* Description: Ram on/off. */
Kojto	97:433970e64889	3845
Kojto	97:433970e64889	3846	/* Bit 17 : RAM block 3 behaviour in OFF mode. */
Kojto	97:433970e64889	3847	#define POWER_RAMONB_OFFRAM3_Pos (17UL) /!< Position of OFFRAM3 field. /
Kojto	97:433970e64889	3848	#define POWER_RAMONB_OFFRAM3_Msk (0x1UL << POWER_RAMONB_OFFRAM3_Pos) /!< Bit mask of OFFRAM3 field. /
Kojto	97:433970e64889	3849	#define POWER_RAMONB_OFFRAM3_RAM3Off (0UL) /!< RAM block 3 OFF in OFF mode. /
Kojto	97:433970e64889	3850	#define POWER_RAMONB_OFFRAM3_RAM3On (1UL) /!< RAM block 3 ON in OFF mode. /
Kojto	97:433970e64889	3851
Kojto	97:433970e64889	3852	/* Bit 16 : RAM block 2 behaviour in OFF mode. */
Kojto	97:433970e64889	3853	#define POWER_RAMONB_OFFRAM2_Pos (16UL) /!< Position of OFFRAM2 field. /
Kojto	97:433970e64889	3854	#define POWER_RAMONB_OFFRAM2_Msk (0x1UL << POWER_RAMONB_OFFRAM2_Pos) /!< Bit mask of OFFRAM2 field. /
Kojto	97:433970e64889	3855	#define POWER_RAMONB_OFFRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in OFF mode. /
Kojto	97:433970e64889	3856	#define POWER_RAMONB_OFFRAM2_RAM2On (1UL) /!< RAM block 2 ON in OFF mode. /
Kojto	97:433970e64889	3857
Kojto	97:433970e64889	3858	/* Bit 1 : RAM block 3 behaviour in ON mode. */
Kojto	97:433970e64889	3859	#define POWER_RAMONB_ONRAM3_Pos (1UL) /!< Position of ONRAM3 field. /
Kojto	97:433970e64889	3860	#define POWER_RAMONB_ONRAM3_Msk (0x1UL << POWER_RAMONB_ONRAM3_Pos) /!< Bit mask of ONRAM3 field. /
Kojto	97:433970e64889	3861	#define POWER_RAMONB_ONRAM3_RAM3Off (0UL) /!< RAM block 33 OFF in ON mode. /
Kojto	97:433970e64889	3862	#define POWER_RAMONB_ONRAM3_RAM3On (1UL) /!< RAM block 3 ON in ON mode. /
Kojto	97:433970e64889	3863
Kojto	97:433970e64889	3864	/* Bit 0 : RAM block 2 behaviour in ON mode. */
Kojto	97:433970e64889	3865	#define POWER_RAMONB_ONRAM2_Pos (0UL) /!< Position of ONRAM2 field. /
Kojto	97:433970e64889	3866	#define POWER_RAMONB_ONRAM2_Msk (0x1UL << POWER_RAMONB_ONRAM2_Pos) /!< Bit mask of ONRAM2 field. /
Kojto	97:433970e64889	3867	#define POWER_RAMONB_ONRAM2_RAM2Off (0UL) /!< RAM block 2 OFF in ON mode. /
Kojto	97:433970e64889	3868	#define POWER_RAMONB_ONRAM2_RAM2On (1UL) /!< RAM block 2 ON in ON mode. /
Kojto	97:433970e64889	3869
emilmont	80:8e73be2a2ac1	3870	/* Register: POWER_DCDCEN */
emilmont	80:8e73be2a2ac1	3871	/* Description: DCDC converter enable configuration register. */
emilmont	80:8e73be2a2ac1	3872
emilmont	80:8e73be2a2ac1	3873	/* Bit 0 : Enable DCDC converter. */
emilmont	80:8e73be2a2ac1	3874	#define POWER_DCDCEN_DCDCEN_Pos (0UL) /!< Position of DCDCEN field. /
emilmont	80:8e73be2a2ac1	3875	#define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /!< Bit mask of DCDCEN field. /
emilmont	80:8e73be2a2ac1	3876	#define POWER_DCDCEN_DCDCEN_Disabled (0UL) /!< DCDC converter disabled. /
emilmont	80:8e73be2a2ac1	3877	#define POWER_DCDCEN_DCDCEN_Enabled (1UL) /!< DCDC converter enabled. /
emilmont	80:8e73be2a2ac1	3878
Kojto	97:433970e64889	3879	/* Register: POWER_DCDCFORCE */
Kojto	97:433970e64889	3880	/* Description: DCDC power-up force register. */
Kojto	97:433970e64889	3881
Kojto	97:433970e64889	3882	/* Bit 1 : DCDC power-up force on. */
Kojto	97:433970e64889	3883	#define POWER_DCDCFORCE_FORCEON_Pos (1UL) /!< Position of FORCEON field. /
Kojto	97:433970e64889	3884	#define POWER_DCDCFORCE_FORCEON_Msk (0x1UL << POWER_DCDCFORCE_FORCEON_Pos) /!< Bit mask of FORCEON field. /
Kojto	97:433970e64889	3885	#define POWER_DCDCFORCE_FORCEON_NoForce (0UL) /!< No force. /
Kojto	97:433970e64889	3886	#define POWER_DCDCFORCE_FORCEON_Force (1UL) /!< Force. /
Kojto	97:433970e64889	3887
Kojto	97:433970e64889	3888	/* Bit 0 : DCDC power-up force off. */
Kojto	97:433970e64889	3889	#define POWER_DCDCFORCE_FORCEOFF_Pos (0UL) /!< Position of FORCEOFF field. /
Kojto	97:433970e64889	3890	#define POWER_DCDCFORCE_FORCEOFF_Msk (0x1UL << POWER_DCDCFORCE_FORCEOFF_Pos) /!< Bit mask of FORCEOFF field. /
Kojto	97:433970e64889	3891	#define POWER_DCDCFORCE_FORCEOFF_NoForce (0UL) /!< No force. /
Kojto	97:433970e64889	3892	#define POWER_DCDCFORCE_FORCEOFF_Force (1UL) /!< Force. /
Kojto	97:433970e64889	3893
emilmont	80:8e73be2a2ac1	3894
emilmont	80:8e73be2a2ac1	3895	/* Peripheral: PPI */
emilmont	80:8e73be2a2ac1	3896	/* Description: PPI controller. */
emilmont	80:8e73be2a2ac1	3897
emilmont	80:8e73be2a2ac1	3898	/* Register: PPI_CHEN */
emilmont	80:8e73be2a2ac1	3899	/* Description: Channel enable. */
emilmont	80:8e73be2a2ac1	3900
emilmont	80:8e73be2a2ac1	3901	/* Bit 31 : Enable PPI channel 31. */
emilmont	80:8e73be2a2ac1	3902	#define PPI_CHEN_CH31_Pos (31UL) /!< Position of CH31 field. /
emilmont	80:8e73be2a2ac1	3903	#define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /!< Bit mask of CH31 field. /
emilmont	80:8e73be2a2ac1	3904	#define PPI_CHEN_CH31_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3905	#define PPI_CHEN_CH31_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3906
emilmont	80:8e73be2a2ac1	3907	/* Bit 30 : Enable PPI channel 30. */
emilmont	80:8e73be2a2ac1	3908	#define PPI_CHEN_CH30_Pos (30UL) /!< Position of CH30 field. /
emilmont	80:8e73be2a2ac1	3909	#define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /!< Bit mask of CH30 field. /
emilmont	80:8e73be2a2ac1	3910	#define PPI_CHEN_CH30_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3911	#define PPI_CHEN_CH30_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3912
emilmont	80:8e73be2a2ac1	3913	/* Bit 29 : Enable PPI channel 29. */
emilmont	80:8e73be2a2ac1	3914	#define PPI_CHEN_CH29_Pos (29UL) /!< Position of CH29 field. /
emilmont	80:8e73be2a2ac1	3915	#define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /!< Bit mask of CH29 field. /
emilmont	80:8e73be2a2ac1	3916	#define PPI_CHEN_CH29_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3917	#define PPI_CHEN_CH29_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3918
emilmont	80:8e73be2a2ac1	3919	/* Bit 28 : Enable PPI channel 28. */
emilmont	80:8e73be2a2ac1	3920	#define PPI_CHEN_CH28_Pos (28UL) /!< Position of CH28 field. /
emilmont	80:8e73be2a2ac1	3921	#define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /!< Bit mask of CH28 field. /
emilmont	80:8e73be2a2ac1	3922	#define PPI_CHEN_CH28_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3923	#define PPI_CHEN_CH28_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3924
emilmont	80:8e73be2a2ac1	3925	/* Bit 27 : Enable PPI channel 27. */
emilmont	80:8e73be2a2ac1	3926	#define PPI_CHEN_CH27_Pos (27UL) /!< Position of CH27 field. /
emilmont	80:8e73be2a2ac1	3927	#define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /!< Bit mask of CH27 field. /
emilmont	80:8e73be2a2ac1	3928	#define PPI_CHEN_CH27_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3929	#define PPI_CHEN_CH27_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3930
emilmont	80:8e73be2a2ac1	3931	/* Bit 26 : Enable PPI channel 26. */
emilmont	80:8e73be2a2ac1	3932	#define PPI_CHEN_CH26_Pos (26UL) /!< Position of CH26 field. /
emilmont	80:8e73be2a2ac1	3933	#define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /!< Bit mask of CH26 field. /
emilmont	80:8e73be2a2ac1	3934	#define PPI_CHEN_CH26_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3935	#define PPI_CHEN_CH26_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3936
emilmont	80:8e73be2a2ac1	3937	/* Bit 25 : Enable PPI channel 25. */
emilmont	80:8e73be2a2ac1	3938	#define PPI_CHEN_CH25_Pos (25UL) /!< Position of CH25 field. /
emilmont	80:8e73be2a2ac1	3939	#define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /!< Bit mask of CH25 field. /
emilmont	80:8e73be2a2ac1	3940	#define PPI_CHEN_CH25_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3941	#define PPI_CHEN_CH25_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3942
emilmont	80:8e73be2a2ac1	3943	/* Bit 24 : Enable PPI channel 24. */
emilmont	80:8e73be2a2ac1	3944	#define PPI_CHEN_CH24_Pos (24UL) /!< Position of CH24 field. /
emilmont	80:8e73be2a2ac1	3945	#define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /!< Bit mask of CH24 field. /
emilmont	80:8e73be2a2ac1	3946	#define PPI_CHEN_CH24_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3947	#define PPI_CHEN_CH24_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3948
emilmont	80:8e73be2a2ac1	3949	/* Bit 23 : Enable PPI channel 23. */
emilmont	80:8e73be2a2ac1	3950	#define PPI_CHEN_CH23_Pos (23UL) /!< Position of CH23 field. /
emilmont	80:8e73be2a2ac1	3951	#define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /!< Bit mask of CH23 field. /
emilmont	80:8e73be2a2ac1	3952	#define PPI_CHEN_CH23_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3953	#define PPI_CHEN_CH23_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3954
emilmont	80:8e73be2a2ac1	3955	/* Bit 22 : Enable PPI channel 22. */
emilmont	80:8e73be2a2ac1	3956	#define PPI_CHEN_CH22_Pos (22UL) /!< Position of CH22 field. /
emilmont	80:8e73be2a2ac1	3957	#define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /!< Bit mask of CH22 field. /
emilmont	80:8e73be2a2ac1	3958	#define PPI_CHEN_CH22_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3959	#define PPI_CHEN_CH22_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3960
emilmont	80:8e73be2a2ac1	3961	/* Bit 21 : Enable PPI channel 21. */
emilmont	80:8e73be2a2ac1	3962	#define PPI_CHEN_CH21_Pos (21UL) /!< Position of CH21 field. /
emilmont	80:8e73be2a2ac1	3963	#define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /!< Bit mask of CH21 field. /
emilmont	80:8e73be2a2ac1	3964	#define PPI_CHEN_CH21_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3965	#define PPI_CHEN_CH21_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3966
emilmont	80:8e73be2a2ac1	3967	/* Bit 20 : Enable PPI channel 20. */
emilmont	80:8e73be2a2ac1	3968	#define PPI_CHEN_CH20_Pos (20UL) /!< Position of CH20 field. /
emilmont	80:8e73be2a2ac1	3969	#define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /!< Bit mask of CH20 field. /
emilmont	80:8e73be2a2ac1	3970	#define PPI_CHEN_CH20_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3971	#define PPI_CHEN_CH20_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3972
emilmont	80:8e73be2a2ac1	3973	/* Bit 15 : Enable PPI channel 15. */
emilmont	80:8e73be2a2ac1	3974	#define PPI_CHEN_CH15_Pos (15UL) /!< Position of CH15 field. /
emilmont	80:8e73be2a2ac1	3975	#define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /!< Bit mask of CH15 field. /
emilmont	80:8e73be2a2ac1	3976	#define PPI_CHEN_CH15_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3977	#define PPI_CHEN_CH15_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3978
emilmont	80:8e73be2a2ac1	3979	/* Bit 14 : Enable PPI channel 14. */
emilmont	80:8e73be2a2ac1	3980	#define PPI_CHEN_CH14_Pos (14UL) /!< Position of CH14 field. /
emilmont	80:8e73be2a2ac1	3981	#define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /!< Bit mask of CH14 field. /
emilmont	80:8e73be2a2ac1	3982	#define PPI_CHEN_CH14_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3983	#define PPI_CHEN_CH14_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3984
emilmont	80:8e73be2a2ac1	3985	/* Bit 13 : Enable PPI channel 13. */
emilmont	80:8e73be2a2ac1	3986	#define PPI_CHEN_CH13_Pos (13UL) /!< Position of CH13 field. /
emilmont	80:8e73be2a2ac1	3987	#define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /!< Bit mask of CH13 field. /
emilmont	80:8e73be2a2ac1	3988	#define PPI_CHEN_CH13_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3989	#define PPI_CHEN_CH13_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3990
emilmont	80:8e73be2a2ac1	3991	/* Bit 12 : Enable PPI channel 12. */
emilmont	80:8e73be2a2ac1	3992	#define PPI_CHEN_CH12_Pos (12UL) /!< Position of CH12 field. /
emilmont	80:8e73be2a2ac1	3993	#define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /!< Bit mask of CH12 field. /
emilmont	80:8e73be2a2ac1	3994	#define PPI_CHEN_CH12_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	3995	#define PPI_CHEN_CH12_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	3996
emilmont	80:8e73be2a2ac1	3997	/* Bit 11 : Enable PPI channel 11. */
emilmont	80:8e73be2a2ac1	3998	#define PPI_CHEN_CH11_Pos (11UL) /!< Position of CH11 field. /
emilmont	80:8e73be2a2ac1	3999	#define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /!< Bit mask of CH11 field. /
emilmont	80:8e73be2a2ac1	4000	#define PPI_CHEN_CH11_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4001	#define PPI_CHEN_CH11_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4002
emilmont	80:8e73be2a2ac1	4003	/* Bit 10 : Enable PPI channel 10. */
emilmont	80:8e73be2a2ac1	4004	#define PPI_CHEN_CH10_Pos (10UL) /!< Position of CH10 field. /
emilmont	80:8e73be2a2ac1	4005	#define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /!< Bit mask of CH10 field. /
emilmont	80:8e73be2a2ac1	4006	#define PPI_CHEN_CH10_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4007	#define PPI_CHEN_CH10_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4008
emilmont	80:8e73be2a2ac1	4009	/* Bit 9 : Enable PPI channel 9. */
emilmont	80:8e73be2a2ac1	4010	#define PPI_CHEN_CH9_Pos (9UL) /!< Position of CH9 field. /
emilmont	80:8e73be2a2ac1	4011	#define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /!< Bit mask of CH9 field. /
emilmont	80:8e73be2a2ac1	4012	#define PPI_CHEN_CH9_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4013	#define PPI_CHEN_CH9_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4014
emilmont	80:8e73be2a2ac1	4015	/* Bit 8 : Enable PPI channel 8. */
emilmont	80:8e73be2a2ac1	4016	#define PPI_CHEN_CH8_Pos (8UL) /!< Position of CH8 field. /
emilmont	80:8e73be2a2ac1	4017	#define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /!< Bit mask of CH8 field. /
emilmont	80:8e73be2a2ac1	4018	#define PPI_CHEN_CH8_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4019	#define PPI_CHEN_CH8_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4020
emilmont	80:8e73be2a2ac1	4021	/* Bit 7 : Enable PPI channel 7. */
emilmont	80:8e73be2a2ac1	4022	#define PPI_CHEN_CH7_Pos (7UL) /!< Position of CH7 field. /
emilmont	80:8e73be2a2ac1	4023	#define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /!< Bit mask of CH7 field. /
emilmont	80:8e73be2a2ac1	4024	#define PPI_CHEN_CH7_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4025	#define PPI_CHEN_CH7_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4026
emilmont	80:8e73be2a2ac1	4027	/* Bit 6 : Enable PPI channel 6. */
emilmont	80:8e73be2a2ac1	4028	#define PPI_CHEN_CH6_Pos (6UL) /!< Position of CH6 field. /
emilmont	80:8e73be2a2ac1	4029	#define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /!< Bit mask of CH6 field. /
emilmont	80:8e73be2a2ac1	4030	#define PPI_CHEN_CH6_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4031	#define PPI_CHEN_CH6_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4032
emilmont	80:8e73be2a2ac1	4033	/* Bit 5 : Enable PPI channel 5. */
emilmont	80:8e73be2a2ac1	4034	#define PPI_CHEN_CH5_Pos (5UL) /!< Position of CH5 field. /
emilmont	80:8e73be2a2ac1	4035	#define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /!< Bit mask of CH5 field. /
emilmont	80:8e73be2a2ac1	4036	#define PPI_CHEN_CH5_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4037	#define PPI_CHEN_CH5_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4038
emilmont	80:8e73be2a2ac1	4039	/* Bit 4 : Enable PPI channel 4. */
emilmont	80:8e73be2a2ac1	4040	#define PPI_CHEN_CH4_Pos (4UL) /!< Position of CH4 field. /
emilmont	80:8e73be2a2ac1	4041	#define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /!< Bit mask of CH4 field. /
emilmont	80:8e73be2a2ac1	4042	#define PPI_CHEN_CH4_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4043	#define PPI_CHEN_CH4_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4044
emilmont	80:8e73be2a2ac1	4045	/* Bit 3 : Enable PPI channel 3. */
emilmont	80:8e73be2a2ac1	4046	#define PPI_CHEN_CH3_Pos (3UL) /!< Position of CH3 field. /
emilmont	80:8e73be2a2ac1	4047	#define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /!< Bit mask of CH3 field. /
emilmont	80:8e73be2a2ac1	4048	#define PPI_CHEN_CH3_Disabled (0UL) /!< Channel disabled /
emilmont	80:8e73be2a2ac1	4049	#define PPI_CHEN_CH3_Enabled (1UL) /!< Channel enabled /
emilmont	80:8e73be2a2ac1	4050
emilmont	80:8e73be2a2ac1	4051	/* Bit 2 : Enable PPI channel 2. */
emilmont	80:8e73be2a2ac1	4052	#define PPI_CHEN_CH2_Pos (2UL) /!< Position of CH2 field. /
emilmont	80:8e73be2a2ac1	4053	#define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /!< Bit mask of CH2 field. /
emilmont	80:8e73be2a2ac1	4054	#define PPI_CHEN_CH2_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4055	#define PPI_CHEN_CH2_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4056
emilmont	80:8e73be2a2ac1	4057	/* Bit 1 : Enable PPI channel 1. */
emilmont	80:8e73be2a2ac1	4058	#define PPI_CHEN_CH1_Pos (1UL) /!< Position of CH1 field. /
emilmont	80:8e73be2a2ac1	4059	#define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /!< Bit mask of CH1 field. /
emilmont	80:8e73be2a2ac1	4060	#define PPI_CHEN_CH1_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4061	#define PPI_CHEN_CH1_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4062
emilmont	80:8e73be2a2ac1	4063	/* Bit 0 : Enable PPI channel 0. */
emilmont	80:8e73be2a2ac1	4064	#define PPI_CHEN_CH0_Pos (0UL) /!< Position of CH0 field. /
emilmont	80:8e73be2a2ac1	4065	#define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /!< Bit mask of CH0 field. /
emilmont	80:8e73be2a2ac1	4066	#define PPI_CHEN_CH0_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4067	#define PPI_CHEN_CH0_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4068
emilmont	80:8e73be2a2ac1	4069	/* Register: PPI_CHENSET */
emilmont	80:8e73be2a2ac1	4070	/* Description: Channel enable set. */
emilmont	80:8e73be2a2ac1	4071
emilmont	80:8e73be2a2ac1	4072	/* Bit 31 : Enable PPI channel 31. */
emilmont	80:8e73be2a2ac1	4073	#define PPI_CHENSET_CH31_Pos (31UL) /!< Position of CH31 field. /
emilmont	80:8e73be2a2ac1	4074	#define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /!< Bit mask of CH31 field. /
emilmont	80:8e73be2a2ac1	4075	#define PPI_CHENSET_CH31_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4076	#define PPI_CHENSET_CH31_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4077	#define PPI_CHENSET_CH31_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4078
emilmont	80:8e73be2a2ac1	4079	/* Bit 30 : Enable PPI channel 30. */
emilmont	80:8e73be2a2ac1	4080	#define PPI_CHENSET_CH30_Pos (30UL) /!< Position of CH30 field. /
emilmont	80:8e73be2a2ac1	4081	#define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /!< Bit mask of CH30 field. /
emilmont	80:8e73be2a2ac1	4082	#define PPI_CHENSET_CH30_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4083	#define PPI_CHENSET_CH30_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4084	#define PPI_CHENSET_CH30_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4085
emilmont	80:8e73be2a2ac1	4086	/* Bit 29 : Enable PPI channel 29. */
emilmont	80:8e73be2a2ac1	4087	#define PPI_CHENSET_CH29_Pos (29UL) /!< Position of CH29 field. /
emilmont	80:8e73be2a2ac1	4088	#define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /!< Bit mask of CH29 field. /
emilmont	80:8e73be2a2ac1	4089	#define PPI_CHENSET_CH29_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4090	#define PPI_CHENSET_CH29_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4091	#define PPI_CHENSET_CH29_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4092
emilmont	80:8e73be2a2ac1	4093	/* Bit 28 : Enable PPI channel 28. */
emilmont	80:8e73be2a2ac1	4094	#define PPI_CHENSET_CH28_Pos (28UL) /!< Position of CH28 field. /
emilmont	80:8e73be2a2ac1	4095	#define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /!< Bit mask of CH28 field. /
emilmont	80:8e73be2a2ac1	4096	#define PPI_CHENSET_CH28_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4097	#define PPI_CHENSET_CH28_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4098	#define PPI_CHENSET_CH28_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4099
emilmont	80:8e73be2a2ac1	4100	/* Bit 27 : Enable PPI channel 27. */
emilmont	80:8e73be2a2ac1	4101	#define PPI_CHENSET_CH27_Pos (27UL) /!< Position of CH27 field. /
emilmont	80:8e73be2a2ac1	4102	#define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /!< Bit mask of CH27 field. /
emilmont	80:8e73be2a2ac1	4103	#define PPI_CHENSET_CH27_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4104	#define PPI_CHENSET_CH27_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4105	#define PPI_CHENSET_CH27_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4106
emilmont	80:8e73be2a2ac1	4107	/* Bit 26 : Enable PPI channel 26. */
emilmont	80:8e73be2a2ac1	4108	#define PPI_CHENSET_CH26_Pos (26UL) /!< Position of CH26 field. /
emilmont	80:8e73be2a2ac1	4109	#define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /!< Bit mask of CH26 field. /
emilmont	80:8e73be2a2ac1	4110	#define PPI_CHENSET_CH26_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4111	#define PPI_CHENSET_CH26_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4112	#define PPI_CHENSET_CH26_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4113
emilmont	80:8e73be2a2ac1	4114	/* Bit 25 : Enable PPI channel 25. */
emilmont	80:8e73be2a2ac1	4115	#define PPI_CHENSET_CH25_Pos (25UL) /!< Position of CH25 field. /
emilmont	80:8e73be2a2ac1	4116	#define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /!< Bit mask of CH25 field. /
emilmont	80:8e73be2a2ac1	4117	#define PPI_CHENSET_CH25_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4118	#define PPI_CHENSET_CH25_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4119	#define PPI_CHENSET_CH25_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4120
emilmont	80:8e73be2a2ac1	4121	/* Bit 24 : Enable PPI channel 24. */
emilmont	80:8e73be2a2ac1	4122	#define PPI_CHENSET_CH24_Pos (24UL) /!< Position of CH24 field. /
emilmont	80:8e73be2a2ac1	4123	#define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /!< Bit mask of CH24 field. /
emilmont	80:8e73be2a2ac1	4124	#define PPI_CHENSET_CH24_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4125	#define PPI_CHENSET_CH24_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4126	#define PPI_CHENSET_CH24_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4127
emilmont	80:8e73be2a2ac1	4128	/* Bit 23 : Enable PPI channel 23. */
emilmont	80:8e73be2a2ac1	4129	#define PPI_CHENSET_CH23_Pos (23UL) /!< Position of CH23 field. /
emilmont	80:8e73be2a2ac1	4130	#define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /!< Bit mask of CH23 field. /
emilmont	80:8e73be2a2ac1	4131	#define PPI_CHENSET_CH23_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4132	#define PPI_CHENSET_CH23_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4133	#define PPI_CHENSET_CH23_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4134
emilmont	80:8e73be2a2ac1	4135	/* Bit 22 : Enable PPI channel 22. */
emilmont	80:8e73be2a2ac1	4136	#define PPI_CHENSET_CH22_Pos (22UL) /!< Position of CH22 field. /
emilmont	80:8e73be2a2ac1	4137	#define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /!< Bit mask of CH22 field. /
emilmont	80:8e73be2a2ac1	4138	#define PPI_CHENSET_CH22_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4139	#define PPI_CHENSET_CH22_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4140	#define PPI_CHENSET_CH22_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4141
emilmont	80:8e73be2a2ac1	4142	/* Bit 21 : Enable PPI channel 21. */
emilmont	80:8e73be2a2ac1	4143	#define PPI_CHENSET_CH21_Pos (21UL) /!< Position of CH21 field. /
emilmont	80:8e73be2a2ac1	4144	#define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /!< Bit mask of CH21 field. /
emilmont	80:8e73be2a2ac1	4145	#define PPI_CHENSET_CH21_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4146	#define PPI_CHENSET_CH21_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4147	#define PPI_CHENSET_CH21_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4148
emilmont	80:8e73be2a2ac1	4149	/* Bit 20 : Enable PPI channel 20. */
emilmont	80:8e73be2a2ac1	4150	#define PPI_CHENSET_CH20_Pos (20UL) /!< Position of CH20 field. /
emilmont	80:8e73be2a2ac1	4151	#define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /!< Bit mask of CH20 field. /
emilmont	80:8e73be2a2ac1	4152	#define PPI_CHENSET_CH20_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4153	#define PPI_CHENSET_CH20_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4154	#define PPI_CHENSET_CH20_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4155
emilmont	80:8e73be2a2ac1	4156	/* Bit 15 : Enable PPI channel 15. */
emilmont	80:8e73be2a2ac1	4157	#define PPI_CHENSET_CH15_Pos (15UL) /!< Position of CH15 field. /
emilmont	80:8e73be2a2ac1	4158	#define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /!< Bit mask of CH15 field. /
emilmont	80:8e73be2a2ac1	4159	#define PPI_CHENSET_CH15_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4160	#define PPI_CHENSET_CH15_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4161	#define PPI_CHENSET_CH15_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4162
emilmont	80:8e73be2a2ac1	4163	/* Bit 14 : Enable PPI channel 14. */
emilmont	80:8e73be2a2ac1	4164	#define PPI_CHENSET_CH14_Pos (14UL) /!< Position of CH14 field. /
emilmont	80:8e73be2a2ac1	4165	#define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /!< Bit mask of CH14 field. /
emilmont	80:8e73be2a2ac1	4166	#define PPI_CHENSET_CH14_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4167	#define PPI_CHENSET_CH14_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4168	#define PPI_CHENSET_CH14_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4169
emilmont	80:8e73be2a2ac1	4170	/* Bit 13 : Enable PPI channel 13. */
emilmont	80:8e73be2a2ac1	4171	#define PPI_CHENSET_CH13_Pos (13UL) /!< Position of CH13 field. /
emilmont	80:8e73be2a2ac1	4172	#define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /!< Bit mask of CH13 field. /
emilmont	80:8e73be2a2ac1	4173	#define PPI_CHENSET_CH13_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4174	#define PPI_CHENSET_CH13_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4175	#define PPI_CHENSET_CH13_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4176
emilmont	80:8e73be2a2ac1	4177	/* Bit 12 : Enable PPI channel 12. */
emilmont	80:8e73be2a2ac1	4178	#define PPI_CHENSET_CH12_Pos (12UL) /!< Position of CH12 field. /
emilmont	80:8e73be2a2ac1	4179	#define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /!< Bit mask of CH12 field. /
emilmont	80:8e73be2a2ac1	4180	#define PPI_CHENSET_CH12_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4181	#define PPI_CHENSET_CH12_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4182	#define PPI_CHENSET_CH12_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4183
emilmont	80:8e73be2a2ac1	4184	/* Bit 11 : Enable PPI channel 11. */
emilmont	80:8e73be2a2ac1	4185	#define PPI_CHENSET_CH11_Pos (11UL) /!< Position of CH11 field. /
emilmont	80:8e73be2a2ac1	4186	#define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /!< Bit mask of CH11 field. /
emilmont	80:8e73be2a2ac1	4187	#define PPI_CHENSET_CH11_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4188	#define PPI_CHENSET_CH11_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4189	#define PPI_CHENSET_CH11_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4190
emilmont	80:8e73be2a2ac1	4191	/* Bit 10 : Enable PPI channel 10. */
emilmont	80:8e73be2a2ac1	4192	#define PPI_CHENSET_CH10_Pos (10UL) /!< Position of CH10 field. /
emilmont	80:8e73be2a2ac1	4193	#define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /!< Bit mask of CH10 field. /
emilmont	80:8e73be2a2ac1	4194	#define PPI_CHENSET_CH10_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4195	#define PPI_CHENSET_CH10_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4196	#define PPI_CHENSET_CH10_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4197
emilmont	80:8e73be2a2ac1	4198	/* Bit 9 : Enable PPI channel 9. */
emilmont	80:8e73be2a2ac1	4199	#define PPI_CHENSET_CH9_Pos (9UL) /!< Position of CH9 field. /
emilmont	80:8e73be2a2ac1	4200	#define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /!< Bit mask of CH9 field. /
emilmont	80:8e73be2a2ac1	4201	#define PPI_CHENSET_CH9_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4202	#define PPI_CHENSET_CH9_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4203	#define PPI_CHENSET_CH9_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4204
emilmont	80:8e73be2a2ac1	4205	/* Bit 8 : Enable PPI channel 8. */
emilmont	80:8e73be2a2ac1	4206	#define PPI_CHENSET_CH8_Pos (8UL) /!< Position of CH8 field. /
emilmont	80:8e73be2a2ac1	4207	#define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /!< Bit mask of CH8 field. /
emilmont	80:8e73be2a2ac1	4208	#define PPI_CHENSET_CH8_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4209	#define PPI_CHENSET_CH8_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4210	#define PPI_CHENSET_CH8_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4211
emilmont	80:8e73be2a2ac1	4212	/* Bit 7 : Enable PPI channel 7. */
emilmont	80:8e73be2a2ac1	4213	#define PPI_CHENSET_CH7_Pos (7UL) /!< Position of CH7 field. /
emilmont	80:8e73be2a2ac1	4214	#define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /!< Bit mask of CH7 field. /
emilmont	80:8e73be2a2ac1	4215	#define PPI_CHENSET_CH7_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4216	#define PPI_CHENSET_CH7_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4217	#define PPI_CHENSET_CH7_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4218
emilmont	80:8e73be2a2ac1	4219	/* Bit 6 : Enable PPI channel 6. */
emilmont	80:8e73be2a2ac1	4220	#define PPI_CHENSET_CH6_Pos (6UL) /!< Position of CH6 field. /
emilmont	80:8e73be2a2ac1	4221	#define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /!< Bit mask of CH6 field. /
emilmont	80:8e73be2a2ac1	4222	#define PPI_CHENSET_CH6_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4223	#define PPI_CHENSET_CH6_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4224	#define PPI_CHENSET_CH6_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4225
emilmont	80:8e73be2a2ac1	4226	/* Bit 5 : Enable PPI channel 5. */
emilmont	80:8e73be2a2ac1	4227	#define PPI_CHENSET_CH5_Pos (5UL) /!< Position of CH5 field. /
emilmont	80:8e73be2a2ac1	4228	#define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /!< Bit mask of CH5 field. /
emilmont	80:8e73be2a2ac1	4229	#define PPI_CHENSET_CH5_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4230	#define PPI_CHENSET_CH5_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4231	#define PPI_CHENSET_CH5_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4232
emilmont	80:8e73be2a2ac1	4233	/* Bit 4 : Enable PPI channel 4. */
emilmont	80:8e73be2a2ac1	4234	#define PPI_CHENSET_CH4_Pos (4UL) /!< Position of CH4 field. /
emilmont	80:8e73be2a2ac1	4235	#define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /!< Bit mask of CH4 field. /
emilmont	80:8e73be2a2ac1	4236	#define PPI_CHENSET_CH4_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4237	#define PPI_CHENSET_CH4_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4238	#define PPI_CHENSET_CH4_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4239
emilmont	80:8e73be2a2ac1	4240	/* Bit 3 : Enable PPI channel 3. */
emilmont	80:8e73be2a2ac1	4241	#define PPI_CHENSET_CH3_Pos (3UL) /!< Position of CH3 field. /
emilmont	80:8e73be2a2ac1	4242	#define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /!< Bit mask of CH3 field. /
emilmont	80:8e73be2a2ac1	4243	#define PPI_CHENSET_CH3_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4244	#define PPI_CHENSET_CH3_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4245	#define PPI_CHENSET_CH3_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4246
emilmont	80:8e73be2a2ac1	4247	/* Bit 2 : Enable PPI channel 2. */
emilmont	80:8e73be2a2ac1	4248	#define PPI_CHENSET_CH2_Pos (2UL) /!< Position of CH2 field. /
emilmont	80:8e73be2a2ac1	4249	#define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /!< Bit mask of CH2 field. /
emilmont	80:8e73be2a2ac1	4250	#define PPI_CHENSET_CH2_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4251	#define PPI_CHENSET_CH2_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4252	#define PPI_CHENSET_CH2_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4253
emilmont	80:8e73be2a2ac1	4254	/* Bit 1 : Enable PPI channel 1. */
emilmont	80:8e73be2a2ac1	4255	#define PPI_CHENSET_CH1_Pos (1UL) /!< Position of CH1 field. /
emilmont	80:8e73be2a2ac1	4256	#define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /!< Bit mask of CH1 field. /
emilmont	80:8e73be2a2ac1	4257	#define PPI_CHENSET_CH1_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4258	#define PPI_CHENSET_CH1_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4259	#define PPI_CHENSET_CH1_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4260
emilmont	80:8e73be2a2ac1	4261	/* Bit 0 : Enable PPI channel 0. */
emilmont	80:8e73be2a2ac1	4262	#define PPI_CHENSET_CH0_Pos (0UL) /!< Position of CH0 field. /
emilmont	80:8e73be2a2ac1	4263	#define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /!< Bit mask of CH0 field. /
emilmont	80:8e73be2a2ac1	4264	#define PPI_CHENSET_CH0_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4265	#define PPI_CHENSET_CH0_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4266	#define PPI_CHENSET_CH0_Set (1UL) /!< Enable channel on write. /
emilmont	80:8e73be2a2ac1	4267
emilmont	80:8e73be2a2ac1	4268	/* Register: PPI_CHENCLR */
emilmont	80:8e73be2a2ac1	4269	/* Description: Channel enable clear. */
emilmont	80:8e73be2a2ac1	4270
emilmont	80:8e73be2a2ac1	4271	/* Bit 31 : Disable PPI channel 31. */
emilmont	80:8e73be2a2ac1	4272	#define PPI_CHENCLR_CH31_Pos (31UL) /!< Position of CH31 field. /
emilmont	80:8e73be2a2ac1	4273	#define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /!< Bit mask of CH31 field. /
emilmont	80:8e73be2a2ac1	4274	#define PPI_CHENCLR_CH31_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4275	#define PPI_CHENCLR_CH31_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4276	#define PPI_CHENCLR_CH31_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4277
emilmont	80:8e73be2a2ac1	4278	/* Bit 30 : Disable PPI channel 30. */
emilmont	80:8e73be2a2ac1	4279	#define PPI_CHENCLR_CH30_Pos (30UL) /!< Position of CH30 field. /
emilmont	80:8e73be2a2ac1	4280	#define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /!< Bit mask of CH30 field. /
emilmont	80:8e73be2a2ac1	4281	#define PPI_CHENCLR_CH30_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4282	#define PPI_CHENCLR_CH30_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4283	#define PPI_CHENCLR_CH30_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4284
emilmont	80:8e73be2a2ac1	4285	/* Bit 29 : Disable PPI channel 29. */
emilmont	80:8e73be2a2ac1	4286	#define PPI_CHENCLR_CH29_Pos (29UL) /!< Position of CH29 field. /
emilmont	80:8e73be2a2ac1	4287	#define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /!< Bit mask of CH29 field. /
emilmont	80:8e73be2a2ac1	4288	#define PPI_CHENCLR_CH29_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4289	#define PPI_CHENCLR_CH29_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4290	#define PPI_CHENCLR_CH29_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4291
emilmont	80:8e73be2a2ac1	4292	/* Bit 28 : Disable PPI channel 28. */
emilmont	80:8e73be2a2ac1	4293	#define PPI_CHENCLR_CH28_Pos (28UL) /!< Position of CH28 field. /
emilmont	80:8e73be2a2ac1	4294	#define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /!< Bit mask of CH28 field. /
emilmont	80:8e73be2a2ac1	4295	#define PPI_CHENCLR_CH28_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4296	#define PPI_CHENCLR_CH28_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4297	#define PPI_CHENCLR_CH28_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4298
emilmont	80:8e73be2a2ac1	4299	/* Bit 27 : Disable PPI channel 27. */
emilmont	80:8e73be2a2ac1	4300	#define PPI_CHENCLR_CH27_Pos (27UL) /!< Position of CH27 field. /
emilmont	80:8e73be2a2ac1	4301	#define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /!< Bit mask of CH27 field. /
emilmont	80:8e73be2a2ac1	4302	#define PPI_CHENCLR_CH27_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4303	#define PPI_CHENCLR_CH27_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4304	#define PPI_CHENCLR_CH27_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4305
emilmont	80:8e73be2a2ac1	4306	/* Bit 26 : Disable PPI channel 26. */
emilmont	80:8e73be2a2ac1	4307	#define PPI_CHENCLR_CH26_Pos (26UL) /!< Position of CH26 field. /
emilmont	80:8e73be2a2ac1	4308	#define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /!< Bit mask of CH26 field. /
emilmont	80:8e73be2a2ac1	4309	#define PPI_CHENCLR_CH26_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4310	#define PPI_CHENCLR_CH26_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4311	#define PPI_CHENCLR_CH26_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4312
emilmont	80:8e73be2a2ac1	4313	/* Bit 25 : Disable PPI channel 25. */
emilmont	80:8e73be2a2ac1	4314	#define PPI_CHENCLR_CH25_Pos (25UL) /!< Position of CH25 field. /
emilmont	80:8e73be2a2ac1	4315	#define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /!< Bit mask of CH25 field. /
emilmont	80:8e73be2a2ac1	4316	#define PPI_CHENCLR_CH25_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4317	#define PPI_CHENCLR_CH25_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4318	#define PPI_CHENCLR_CH25_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4319
emilmont	80:8e73be2a2ac1	4320	/* Bit 24 : Disable PPI channel 24. */
emilmont	80:8e73be2a2ac1	4321	#define PPI_CHENCLR_CH24_Pos (24UL) /!< Position of CH24 field. /
emilmont	80:8e73be2a2ac1	4322	#define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /!< Bit mask of CH24 field. /
emilmont	80:8e73be2a2ac1	4323	#define PPI_CHENCLR_CH24_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4324	#define PPI_CHENCLR_CH24_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4325	#define PPI_CHENCLR_CH24_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4326
emilmont	80:8e73be2a2ac1	4327	/* Bit 23 : Disable PPI channel 23. */
emilmont	80:8e73be2a2ac1	4328	#define PPI_CHENCLR_CH23_Pos (23UL) /!< Position of CH23 field. /
emilmont	80:8e73be2a2ac1	4329	#define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /!< Bit mask of CH23 field. /
emilmont	80:8e73be2a2ac1	4330	#define PPI_CHENCLR_CH23_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4331	#define PPI_CHENCLR_CH23_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4332	#define PPI_CHENCLR_CH23_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4333
emilmont	80:8e73be2a2ac1	4334	/* Bit 22 : Disable PPI channel 22. */
emilmont	80:8e73be2a2ac1	4335	#define PPI_CHENCLR_CH22_Pos (22UL) /!< Position of CH22 field. /
emilmont	80:8e73be2a2ac1	4336	#define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /!< Bit mask of CH22 field. /
emilmont	80:8e73be2a2ac1	4337	#define PPI_CHENCLR_CH22_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4338	#define PPI_CHENCLR_CH22_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4339	#define PPI_CHENCLR_CH22_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4340
emilmont	80:8e73be2a2ac1	4341	/* Bit 21 : Disable PPI channel 21. */
emilmont	80:8e73be2a2ac1	4342	#define PPI_CHENCLR_CH21_Pos (21UL) /!< Position of CH21 field. /
emilmont	80:8e73be2a2ac1	4343	#define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /!< Bit mask of CH21 field. /
emilmont	80:8e73be2a2ac1	4344	#define PPI_CHENCLR_CH21_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4345	#define PPI_CHENCLR_CH21_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4346	#define PPI_CHENCLR_CH21_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4347
emilmont	80:8e73be2a2ac1	4348	/* Bit 20 : Disable PPI channel 20. */
emilmont	80:8e73be2a2ac1	4349	#define PPI_CHENCLR_CH20_Pos (20UL) /!< Position of CH20 field. /
emilmont	80:8e73be2a2ac1	4350	#define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /!< Bit mask of CH20 field. /
emilmont	80:8e73be2a2ac1	4351	#define PPI_CHENCLR_CH20_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4352	#define PPI_CHENCLR_CH20_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4353	#define PPI_CHENCLR_CH20_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4354
emilmont	80:8e73be2a2ac1	4355	/* Bit 15 : Disable PPI channel 15. */
emilmont	80:8e73be2a2ac1	4356	#define PPI_CHENCLR_CH15_Pos (15UL) /!< Position of CH15 field. /
emilmont	80:8e73be2a2ac1	4357	#define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /!< Bit mask of CH15 field. /
emilmont	80:8e73be2a2ac1	4358	#define PPI_CHENCLR_CH15_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4359	#define PPI_CHENCLR_CH15_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4360	#define PPI_CHENCLR_CH15_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4361
emilmont	80:8e73be2a2ac1	4362	/* Bit 14 : Disable PPI channel 14. */
emilmont	80:8e73be2a2ac1	4363	#define PPI_CHENCLR_CH14_Pos (14UL) /!< Position of CH14 field. /
emilmont	80:8e73be2a2ac1	4364	#define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /!< Bit mask of CH14 field. /
emilmont	80:8e73be2a2ac1	4365	#define PPI_CHENCLR_CH14_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4366	#define PPI_CHENCLR_CH14_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4367	#define PPI_CHENCLR_CH14_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4368
emilmont	80:8e73be2a2ac1	4369	/* Bit 13 : Disable PPI channel 13. */
emilmont	80:8e73be2a2ac1	4370	#define PPI_CHENCLR_CH13_Pos (13UL) /!< Position of CH13 field. /
emilmont	80:8e73be2a2ac1	4371	#define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /!< Bit mask of CH13 field. /
emilmont	80:8e73be2a2ac1	4372	#define PPI_CHENCLR_CH13_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4373	#define PPI_CHENCLR_CH13_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4374	#define PPI_CHENCLR_CH13_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4375
emilmont	80:8e73be2a2ac1	4376	/* Bit 12 : Disable PPI channel 12. */
emilmont	80:8e73be2a2ac1	4377	#define PPI_CHENCLR_CH12_Pos (12UL) /!< Position of CH12 field. /
emilmont	80:8e73be2a2ac1	4378	#define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /!< Bit mask of CH12 field. /
emilmont	80:8e73be2a2ac1	4379	#define PPI_CHENCLR_CH12_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4380	#define PPI_CHENCLR_CH12_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4381	#define PPI_CHENCLR_CH12_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4382
emilmont	80:8e73be2a2ac1	4383	/* Bit 11 : Disable PPI channel 11. */
emilmont	80:8e73be2a2ac1	4384	#define PPI_CHENCLR_CH11_Pos (11UL) /!< Position of CH11 field. /
emilmont	80:8e73be2a2ac1	4385	#define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /!< Bit mask of CH11 field. /
emilmont	80:8e73be2a2ac1	4386	#define PPI_CHENCLR_CH11_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4387	#define PPI_CHENCLR_CH11_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4388	#define PPI_CHENCLR_CH11_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4389
emilmont	80:8e73be2a2ac1	4390	/* Bit 10 : Disable PPI channel 10. */
emilmont	80:8e73be2a2ac1	4391	#define PPI_CHENCLR_CH10_Pos (10UL) /!< Position of CH10 field. /
emilmont	80:8e73be2a2ac1	4392	#define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /!< Bit mask of CH10 field. /
emilmont	80:8e73be2a2ac1	4393	#define PPI_CHENCLR_CH10_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4394	#define PPI_CHENCLR_CH10_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4395	#define PPI_CHENCLR_CH10_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4396
emilmont	80:8e73be2a2ac1	4397	/* Bit 9 : Disable PPI channel 9. */
emilmont	80:8e73be2a2ac1	4398	#define PPI_CHENCLR_CH9_Pos (9UL) /!< Position of CH9 field. /
emilmont	80:8e73be2a2ac1	4399	#define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /!< Bit mask of CH9 field. /
emilmont	80:8e73be2a2ac1	4400	#define PPI_CHENCLR_CH9_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4401	#define PPI_CHENCLR_CH9_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4402	#define PPI_CHENCLR_CH9_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4403
emilmont	80:8e73be2a2ac1	4404	/* Bit 8 : Disable PPI channel 8. */
emilmont	80:8e73be2a2ac1	4405	#define PPI_CHENCLR_CH8_Pos (8UL) /!< Position of CH8 field. /
emilmont	80:8e73be2a2ac1	4406	#define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /!< Bit mask of CH8 field. /
emilmont	80:8e73be2a2ac1	4407	#define PPI_CHENCLR_CH8_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4408	#define PPI_CHENCLR_CH8_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4409	#define PPI_CHENCLR_CH8_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4410
emilmont	80:8e73be2a2ac1	4411	/* Bit 7 : Disable PPI channel 7. */
emilmont	80:8e73be2a2ac1	4412	#define PPI_CHENCLR_CH7_Pos (7UL) /!< Position of CH7 field. /
emilmont	80:8e73be2a2ac1	4413	#define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /!< Bit mask of CH7 field. /
emilmont	80:8e73be2a2ac1	4414	#define PPI_CHENCLR_CH7_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4415	#define PPI_CHENCLR_CH7_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4416	#define PPI_CHENCLR_CH7_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4417
emilmont	80:8e73be2a2ac1	4418	/* Bit 6 : Disable PPI channel 6. */
emilmont	80:8e73be2a2ac1	4419	#define PPI_CHENCLR_CH6_Pos (6UL) /!< Position of CH6 field. /
emilmont	80:8e73be2a2ac1	4420	#define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /!< Bit mask of CH6 field. /
emilmont	80:8e73be2a2ac1	4421	#define PPI_CHENCLR_CH6_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4422	#define PPI_CHENCLR_CH6_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4423	#define PPI_CHENCLR_CH6_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4424
emilmont	80:8e73be2a2ac1	4425	/* Bit 5 : Disable PPI channel 5. */
emilmont	80:8e73be2a2ac1	4426	#define PPI_CHENCLR_CH5_Pos (5UL) /!< Position of CH5 field. /
emilmont	80:8e73be2a2ac1	4427	#define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /!< Bit mask of CH5 field. /
emilmont	80:8e73be2a2ac1	4428	#define PPI_CHENCLR_CH5_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4429	#define PPI_CHENCLR_CH5_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4430	#define PPI_CHENCLR_CH5_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4431
emilmont	80:8e73be2a2ac1	4432	/* Bit 4 : Disable PPI channel 4. */
emilmont	80:8e73be2a2ac1	4433	#define PPI_CHENCLR_CH4_Pos (4UL) /!< Position of CH4 field. /
emilmont	80:8e73be2a2ac1	4434	#define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /!< Bit mask of CH4 field. /
emilmont	80:8e73be2a2ac1	4435	#define PPI_CHENCLR_CH4_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4436	#define PPI_CHENCLR_CH4_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4437	#define PPI_CHENCLR_CH4_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4438
emilmont	80:8e73be2a2ac1	4439	/* Bit 3 : Disable PPI channel 3. */
emilmont	80:8e73be2a2ac1	4440	#define PPI_CHENCLR_CH3_Pos (3UL) /!< Position of CH3 field. /
emilmont	80:8e73be2a2ac1	4441	#define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /!< Bit mask of CH3 field. /
emilmont	80:8e73be2a2ac1	4442	#define PPI_CHENCLR_CH3_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4443	#define PPI_CHENCLR_CH3_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4444	#define PPI_CHENCLR_CH3_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4445
emilmont	80:8e73be2a2ac1	4446	/* Bit 2 : Disable PPI channel 2. */
emilmont	80:8e73be2a2ac1	4447	#define PPI_CHENCLR_CH2_Pos (2UL) /!< Position of CH2 field. /
emilmont	80:8e73be2a2ac1	4448	#define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /!< Bit mask of CH2 field. /
emilmont	80:8e73be2a2ac1	4449	#define PPI_CHENCLR_CH2_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4450	#define PPI_CHENCLR_CH2_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4451	#define PPI_CHENCLR_CH2_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4452
emilmont	80:8e73be2a2ac1	4453	/* Bit 1 : Disable PPI channel 1. */
emilmont	80:8e73be2a2ac1	4454	#define PPI_CHENCLR_CH1_Pos (1UL) /!< Position of CH1 field. /
emilmont	80:8e73be2a2ac1	4455	#define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /!< Bit mask of CH1 field. /
emilmont	80:8e73be2a2ac1	4456	#define PPI_CHENCLR_CH1_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4457	#define PPI_CHENCLR_CH1_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4458	#define PPI_CHENCLR_CH1_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4459
emilmont	80:8e73be2a2ac1	4460	/* Bit 0 : Disable PPI channel 0. */
emilmont	80:8e73be2a2ac1	4461	#define PPI_CHENCLR_CH0_Pos (0UL) /!< Position of CH0 field. /
emilmont	80:8e73be2a2ac1	4462	#define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /!< Bit mask of CH0 field. /
emilmont	80:8e73be2a2ac1	4463	#define PPI_CHENCLR_CH0_Disabled (0UL) /!< Channel disabled. /
emilmont	80:8e73be2a2ac1	4464	#define PPI_CHENCLR_CH0_Enabled (1UL) /!< Channel enabled. /
emilmont	80:8e73be2a2ac1	4465	#define PPI_CHENCLR_CH0_Clear (1UL) /!< Disable channel on write. /
emilmont	80:8e73be2a2ac1	4466
emilmont	80:8e73be2a2ac1	4467	/* Register: PPI_CHG */
emilmont	80:8e73be2a2ac1	4468	/* Description: Channel group configuration. */
emilmont	80:8e73be2a2ac1	4469
emilmont	80:8e73be2a2ac1	4470	/* Bit 31 : Include CH31 in channel group. */
emilmont	80:8e73be2a2ac1	4471	#define PPI_CHG_CH31_Pos (31UL) /!< Position of CH31 field. /
emilmont	80:8e73be2a2ac1	4472	#define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /!< Bit mask of CH31 field. /
emilmont	80:8e73be2a2ac1	4473	#define PPI_CHG_CH31_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4474	#define PPI_CHG_CH31_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4475
emilmont	80:8e73be2a2ac1	4476	/* Bit 30 : Include CH30 in channel group. */
emilmont	80:8e73be2a2ac1	4477	#define PPI_CHG_CH30_Pos (30UL) /!< Position of CH30 field. /
emilmont	80:8e73be2a2ac1	4478	#define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /!< Bit mask of CH30 field. /
emilmont	80:8e73be2a2ac1	4479	#define PPI_CHG_CH30_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4480	#define PPI_CHG_CH30_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4481
emilmont	80:8e73be2a2ac1	4482	/* Bit 29 : Include CH29 in channel group. */
emilmont	80:8e73be2a2ac1	4483	#define PPI_CHG_CH29_Pos (29UL) /!< Position of CH29 field. /
emilmont	80:8e73be2a2ac1	4484	#define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /!< Bit mask of CH29 field. /
emilmont	80:8e73be2a2ac1	4485	#define PPI_CHG_CH29_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4486	#define PPI_CHG_CH29_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4487
emilmont	80:8e73be2a2ac1	4488	/* Bit 28 : Include CH28 in channel group. */
emilmont	80:8e73be2a2ac1	4489	#define PPI_CHG_CH28_Pos (28UL) /!< Position of CH28 field. /
emilmont	80:8e73be2a2ac1	4490	#define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /!< Bit mask of CH28 field. /
emilmont	80:8e73be2a2ac1	4491	#define PPI_CHG_CH28_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4492	#define PPI_CHG_CH28_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4493
emilmont	80:8e73be2a2ac1	4494	/* Bit 27 : Include CH27 in channel group. */
emilmont	80:8e73be2a2ac1	4495	#define PPI_CHG_CH27_Pos (27UL) /!< Position of CH27 field. /
emilmont	80:8e73be2a2ac1	4496	#define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /!< Bit mask of CH27 field. /
emilmont	80:8e73be2a2ac1	4497	#define PPI_CHG_CH27_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4498	#define PPI_CHG_CH27_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4499
emilmont	80:8e73be2a2ac1	4500	/* Bit 26 : Include CH26 in channel group. */
emilmont	80:8e73be2a2ac1	4501	#define PPI_CHG_CH26_Pos (26UL) /!< Position of CH26 field. /
emilmont	80:8e73be2a2ac1	4502	#define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /!< Bit mask of CH26 field. /
emilmont	80:8e73be2a2ac1	4503	#define PPI_CHG_CH26_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4504	#define PPI_CHG_CH26_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4505
emilmont	80:8e73be2a2ac1	4506	/* Bit 25 : Include CH25 in channel group. */
emilmont	80:8e73be2a2ac1	4507	#define PPI_CHG_CH25_Pos (25UL) /!< Position of CH25 field. /
emilmont	80:8e73be2a2ac1	4508	#define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /!< Bit mask of CH25 field. /
emilmont	80:8e73be2a2ac1	4509	#define PPI_CHG_CH25_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4510	#define PPI_CHG_CH25_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4511
emilmont	80:8e73be2a2ac1	4512	/* Bit 24 : Include CH24 in channel group. */
emilmont	80:8e73be2a2ac1	4513	#define PPI_CHG_CH24_Pos (24UL) /!< Position of CH24 field. /
emilmont	80:8e73be2a2ac1	4514	#define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /!< Bit mask of CH24 field. /
emilmont	80:8e73be2a2ac1	4515	#define PPI_CHG_CH24_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4516	#define PPI_CHG_CH24_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4517
emilmont	80:8e73be2a2ac1	4518	/* Bit 23 : Include CH23 in channel group. */
emilmont	80:8e73be2a2ac1	4519	#define PPI_CHG_CH23_Pos (23UL) /!< Position of CH23 field. /
emilmont	80:8e73be2a2ac1	4520	#define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /!< Bit mask of CH23 field. /
emilmont	80:8e73be2a2ac1	4521	#define PPI_CHG_CH23_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4522	#define PPI_CHG_CH23_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4523
emilmont	80:8e73be2a2ac1	4524	/* Bit 22 : Include CH22 in channel group. */
emilmont	80:8e73be2a2ac1	4525	#define PPI_CHG_CH22_Pos (22UL) /!< Position of CH22 field. /
emilmont	80:8e73be2a2ac1	4526	#define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /!< Bit mask of CH22 field. /
emilmont	80:8e73be2a2ac1	4527	#define PPI_CHG_CH22_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4528	#define PPI_CHG_CH22_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4529
emilmont	80:8e73be2a2ac1	4530	/* Bit 21 : Include CH21 in channel group. */
emilmont	80:8e73be2a2ac1	4531	#define PPI_CHG_CH21_Pos (21UL) /!< Position of CH21 field. /
emilmont	80:8e73be2a2ac1	4532	#define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /!< Bit mask of CH21 field. /
emilmont	80:8e73be2a2ac1	4533	#define PPI_CHG_CH21_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4534	#define PPI_CHG_CH21_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4535
emilmont	80:8e73be2a2ac1	4536	/* Bit 20 : Include CH20 in channel group. */
emilmont	80:8e73be2a2ac1	4537	#define PPI_CHG_CH20_Pos (20UL) /!< Position of CH20 field. /
emilmont	80:8e73be2a2ac1	4538	#define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /!< Bit mask of CH20 field. /
emilmont	80:8e73be2a2ac1	4539	#define PPI_CHG_CH20_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4540	#define PPI_CHG_CH20_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4541
emilmont	80:8e73be2a2ac1	4542	/* Bit 15 : Include CH15 in channel group. */
emilmont	80:8e73be2a2ac1	4543	#define PPI_CHG_CH15_Pos (15UL) /!< Position of CH15 field. /
emilmont	80:8e73be2a2ac1	4544	#define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /!< Bit mask of CH15 field. /
emilmont	80:8e73be2a2ac1	4545	#define PPI_CHG_CH15_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4546	#define PPI_CHG_CH15_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4547
emilmont	80:8e73be2a2ac1	4548	/* Bit 14 : Include CH14 in channel group. */
emilmont	80:8e73be2a2ac1	4549	#define PPI_CHG_CH14_Pos (14UL) /!< Position of CH14 field. /
emilmont	80:8e73be2a2ac1	4550	#define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /!< Bit mask of CH14 field. /
emilmont	80:8e73be2a2ac1	4551	#define PPI_CHG_CH14_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4552	#define PPI_CHG_CH14_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4553
emilmont	80:8e73be2a2ac1	4554	/* Bit 13 : Include CH13 in channel group. */
emilmont	80:8e73be2a2ac1	4555	#define PPI_CHG_CH13_Pos (13UL) /!< Position of CH13 field. /
emilmont	80:8e73be2a2ac1	4556	#define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /!< Bit mask of CH13 field. /
emilmont	80:8e73be2a2ac1	4557	#define PPI_CHG_CH13_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4558	#define PPI_CHG_CH13_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4559
emilmont	80:8e73be2a2ac1	4560	/* Bit 12 : Include CH12 in channel group. */
emilmont	80:8e73be2a2ac1	4561	#define PPI_CHG_CH12_Pos (12UL) /!< Position of CH12 field. /
emilmont	80:8e73be2a2ac1	4562	#define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /!< Bit mask of CH12 field. /
emilmont	80:8e73be2a2ac1	4563	#define PPI_CHG_CH12_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4564	#define PPI_CHG_CH12_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4565
emilmont	80:8e73be2a2ac1	4566	/* Bit 11 : Include CH11 in channel group. */
emilmont	80:8e73be2a2ac1	4567	#define PPI_CHG_CH11_Pos (11UL) /!< Position of CH11 field. /
emilmont	80:8e73be2a2ac1	4568	#define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /!< Bit mask of CH11 field. /
emilmont	80:8e73be2a2ac1	4569	#define PPI_CHG_CH11_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4570	#define PPI_CHG_CH11_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4571
emilmont	80:8e73be2a2ac1	4572	/* Bit 10 : Include CH10 in channel group. */
emilmont	80:8e73be2a2ac1	4573	#define PPI_CHG_CH10_Pos (10UL) /!< Position of CH10 field. /
emilmont	80:8e73be2a2ac1	4574	#define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /!< Bit mask of CH10 field. /
emilmont	80:8e73be2a2ac1	4575	#define PPI_CHG_CH10_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4576	#define PPI_CHG_CH10_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4577
emilmont	80:8e73be2a2ac1	4578	/* Bit 9 : Include CH9 in channel group. */
emilmont	80:8e73be2a2ac1	4579	#define PPI_CHG_CH9_Pos (9UL) /!< Position of CH9 field. /
emilmont	80:8e73be2a2ac1	4580	#define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /!< Bit mask of CH9 field. /
emilmont	80:8e73be2a2ac1	4581	#define PPI_CHG_CH9_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4582	#define PPI_CHG_CH9_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4583
emilmont	80:8e73be2a2ac1	4584	/* Bit 8 : Include CH8 in channel group. */
emilmont	80:8e73be2a2ac1	4585	#define PPI_CHG_CH8_Pos (8UL) /!< Position of CH8 field. /
emilmont	80:8e73be2a2ac1	4586	#define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /!< Bit mask of CH8 field. /
emilmont	80:8e73be2a2ac1	4587	#define PPI_CHG_CH8_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4588	#define PPI_CHG_CH8_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4589
emilmont	80:8e73be2a2ac1	4590	/* Bit 7 : Include CH7 in channel group. */
emilmont	80:8e73be2a2ac1	4591	#define PPI_CHG_CH7_Pos (7UL) /!< Position of CH7 field. /
emilmont	80:8e73be2a2ac1	4592	#define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /!< Bit mask of CH7 field. /
emilmont	80:8e73be2a2ac1	4593	#define PPI_CHG_CH7_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4594	#define PPI_CHG_CH7_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4595
emilmont	80:8e73be2a2ac1	4596	/* Bit 6 : Include CH6 in channel group. */
emilmont	80:8e73be2a2ac1	4597	#define PPI_CHG_CH6_Pos (6UL) /!< Position of CH6 field. /
emilmont	80:8e73be2a2ac1	4598	#define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /!< Bit mask of CH6 field. /
emilmont	80:8e73be2a2ac1	4599	#define PPI_CHG_CH6_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4600	#define PPI_CHG_CH6_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4601
emilmont	80:8e73be2a2ac1	4602	/* Bit 5 : Include CH5 in channel group. */
emilmont	80:8e73be2a2ac1	4603	#define PPI_CHG_CH5_Pos (5UL) /!< Position of CH5 field. /
emilmont	80:8e73be2a2ac1	4604	#define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /!< Bit mask of CH5 field. /
emilmont	80:8e73be2a2ac1	4605	#define PPI_CHG_CH5_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4606	#define PPI_CHG_CH5_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4607
emilmont	80:8e73be2a2ac1	4608	/* Bit 4 : Include CH4 in channel group. */
emilmont	80:8e73be2a2ac1	4609	#define PPI_CHG_CH4_Pos (4UL) /!< Position of CH4 field. /
emilmont	80:8e73be2a2ac1	4610	#define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /!< Bit mask of CH4 field. /
emilmont	80:8e73be2a2ac1	4611	#define PPI_CHG_CH4_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4612	#define PPI_CHG_CH4_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4613
emilmont	80:8e73be2a2ac1	4614	/* Bit 3 : Include CH3 in channel group. */
emilmont	80:8e73be2a2ac1	4615	#define PPI_CHG_CH3_Pos (3UL) /!< Position of CH3 field. /
emilmont	80:8e73be2a2ac1	4616	#define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /!< Bit mask of CH3 field. /
emilmont	80:8e73be2a2ac1	4617	#define PPI_CHG_CH3_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4618	#define PPI_CHG_CH3_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4619
emilmont	80:8e73be2a2ac1	4620	/* Bit 2 : Include CH2 in channel group. */
emilmont	80:8e73be2a2ac1	4621	#define PPI_CHG_CH2_Pos (2UL) /!< Position of CH2 field. /
emilmont	80:8e73be2a2ac1	4622	#define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /!< Bit mask of CH2 field. /
emilmont	80:8e73be2a2ac1	4623	#define PPI_CHG_CH2_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4624	#define PPI_CHG_CH2_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4625
emilmont	80:8e73be2a2ac1	4626	/* Bit 1 : Include CH1 in channel group. */
emilmont	80:8e73be2a2ac1	4627	#define PPI_CHG_CH1_Pos (1UL) /!< Position of CH1 field. /
emilmont	80:8e73be2a2ac1	4628	#define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /!< Bit mask of CH1 field. /
emilmont	80:8e73be2a2ac1	4629	#define PPI_CHG_CH1_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4630	#define PPI_CHG_CH1_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4631
emilmont	80:8e73be2a2ac1	4632	/* Bit 0 : Include CH0 in channel group. */
emilmont	80:8e73be2a2ac1	4633	#define PPI_CHG_CH0_Pos (0UL) /!< Position of CH0 field. /
emilmont	80:8e73be2a2ac1	4634	#define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /!< Bit mask of CH0 field. /
emilmont	80:8e73be2a2ac1	4635	#define PPI_CHG_CH0_Excluded (0UL) /!< Channel excluded. /
emilmont	80:8e73be2a2ac1	4636	#define PPI_CHG_CH0_Included (1UL) /!< Channel included. /
emilmont	80:8e73be2a2ac1	4637
emilmont	80:8e73be2a2ac1	4638
emilmont	80:8e73be2a2ac1	4639	/* Peripheral: PU */
emilmont	80:8e73be2a2ac1	4640	/* Description: Patch unit. */
emilmont	80:8e73be2a2ac1	4641
emilmont	80:8e73be2a2ac1	4642	/* Register: PU_PATCHADDR */
emilmont	80:8e73be2a2ac1	4643	/* Description: Relative address of patch instructions. */
emilmont	80:8e73be2a2ac1	4644
emilmont	80:8e73be2a2ac1	4645	/* Bits 24..0 : Relative address of patch instructions. */
emilmont	80:8e73be2a2ac1	4646	#define PU_PATCHADDR_PATCHADDR_Pos (0UL) /!< Position of PATCHADDR field. /
emilmont	80:8e73be2a2ac1	4647	#define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /!< Bit mask of PATCHADDR field. /
emilmont	80:8e73be2a2ac1	4648
emilmont	80:8e73be2a2ac1	4649	/* Register: PU_PATCHEN */
emilmont	80:8e73be2a2ac1	4650	/* Description: Patch enable register. */
emilmont	80:8e73be2a2ac1	4651
emilmont	80:8e73be2a2ac1	4652	/* Bit 7 : Patch 7 enabled. */
emilmont	80:8e73be2a2ac1	4653	#define PU_PATCHEN_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
emilmont	80:8e73be2a2ac1	4654	#define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
emilmont	80:8e73be2a2ac1	4655	#define PU_PATCHEN_PATCH7_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4656	#define PU_PATCHEN_PATCH7_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4657
emilmont	80:8e73be2a2ac1	4658	/* Bit 6 : Patch 6 enabled. */
emilmont	80:8e73be2a2ac1	4659	#define PU_PATCHEN_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
emilmont	80:8e73be2a2ac1	4660	#define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
emilmont	80:8e73be2a2ac1	4661	#define PU_PATCHEN_PATCH6_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4662	#define PU_PATCHEN_PATCH6_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4663
emilmont	80:8e73be2a2ac1	4664	/* Bit 5 : Patch 5 enabled. */
emilmont	80:8e73be2a2ac1	4665	#define PU_PATCHEN_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
emilmont	80:8e73be2a2ac1	4666	#define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
emilmont	80:8e73be2a2ac1	4667	#define PU_PATCHEN_PATCH5_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4668	#define PU_PATCHEN_PATCH5_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4669
emilmont	80:8e73be2a2ac1	4670	/* Bit 4 : Patch 4 enabled. */
emilmont	80:8e73be2a2ac1	4671	#define PU_PATCHEN_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
emilmont	80:8e73be2a2ac1	4672	#define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
emilmont	80:8e73be2a2ac1	4673	#define PU_PATCHEN_PATCH4_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4674	#define PU_PATCHEN_PATCH4_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4675
emilmont	80:8e73be2a2ac1	4676	/* Bit 3 : Patch 3 enabled. */
emilmont	80:8e73be2a2ac1	4677	#define PU_PATCHEN_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
emilmont	80:8e73be2a2ac1	4678	#define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
emilmont	80:8e73be2a2ac1	4679	#define PU_PATCHEN_PATCH3_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4680	#define PU_PATCHEN_PATCH3_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4681
emilmont	80:8e73be2a2ac1	4682	/* Bit 2 : Patch 2 enabled. */
emilmont	80:8e73be2a2ac1	4683	#define PU_PATCHEN_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
emilmont	80:8e73be2a2ac1	4684	#define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
emilmont	80:8e73be2a2ac1	4685	#define PU_PATCHEN_PATCH2_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4686	#define PU_PATCHEN_PATCH2_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4687
emilmont	80:8e73be2a2ac1	4688	/* Bit 1 : Patch 1 enabled. */
emilmont	80:8e73be2a2ac1	4689	#define PU_PATCHEN_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
emilmont	80:8e73be2a2ac1	4690	#define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
emilmont	80:8e73be2a2ac1	4691	#define PU_PATCHEN_PATCH1_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4692	#define PU_PATCHEN_PATCH1_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4693
emilmont	80:8e73be2a2ac1	4694	/* Bit 0 : Patch 0 enabled. */
emilmont	80:8e73be2a2ac1	4695	#define PU_PATCHEN_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
emilmont	80:8e73be2a2ac1	4696	#define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
emilmont	80:8e73be2a2ac1	4697	#define PU_PATCHEN_PATCH0_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4698	#define PU_PATCHEN_PATCH0_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4699
emilmont	80:8e73be2a2ac1	4700	/* Register: PU_PATCHENSET */
emilmont	80:8e73be2a2ac1	4701	/* Description: Patch enable register. */
emilmont	80:8e73be2a2ac1	4702
emilmont	80:8e73be2a2ac1	4703	/* Bit 7 : Patch 7 enabled. */
emilmont	80:8e73be2a2ac1	4704	#define PU_PATCHENSET_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
emilmont	80:8e73be2a2ac1	4705	#define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
emilmont	80:8e73be2a2ac1	4706	#define PU_PATCHENSET_PATCH7_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4707	#define PU_PATCHENSET_PATCH7_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4708	#define PU_PATCHENSET_PATCH7_Set (1UL) /!< Enable patch on write. /
emilmont	80:8e73be2a2ac1	4709
emilmont	80:8e73be2a2ac1	4710	/* Bit 6 : Patch 6 enabled. */
emilmont	80:8e73be2a2ac1	4711	#define PU_PATCHENSET_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
emilmont	80:8e73be2a2ac1	4712	#define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
emilmont	80:8e73be2a2ac1	4713	#define PU_PATCHENSET_PATCH6_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4714	#define PU_PATCHENSET_PATCH6_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4715	#define PU_PATCHENSET_PATCH6_Set (1UL) /!< Enable patch on write. /
emilmont	80:8e73be2a2ac1	4716
emilmont	80:8e73be2a2ac1	4717	/* Bit 5 : Patch 5 enabled. */
emilmont	80:8e73be2a2ac1	4718	#define PU_PATCHENSET_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
emilmont	80:8e73be2a2ac1	4719	#define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
emilmont	80:8e73be2a2ac1	4720	#define PU_PATCHENSET_PATCH5_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4721	#define PU_PATCHENSET_PATCH5_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4722	#define PU_PATCHENSET_PATCH5_Set (1UL) /!< Enable patch on write. /
emilmont	80:8e73be2a2ac1	4723
emilmont	80:8e73be2a2ac1	4724	/* Bit 4 : Patch 4 enabled. */
emilmont	80:8e73be2a2ac1	4725	#define PU_PATCHENSET_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
emilmont	80:8e73be2a2ac1	4726	#define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
emilmont	80:8e73be2a2ac1	4727	#define PU_PATCHENSET_PATCH4_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4728	#define PU_PATCHENSET_PATCH4_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4729	#define PU_PATCHENSET_PATCH4_Set (1UL) /!< Enable patch on write. /
emilmont	80:8e73be2a2ac1	4730
emilmont	80:8e73be2a2ac1	4731	/* Bit 3 : Patch 3 enabled. */
emilmont	80:8e73be2a2ac1	4732	#define PU_PATCHENSET_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
emilmont	80:8e73be2a2ac1	4733	#define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
emilmont	80:8e73be2a2ac1	4734	#define PU_PATCHENSET_PATCH3_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4735	#define PU_PATCHENSET_PATCH3_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4736	#define PU_PATCHENSET_PATCH3_Set (1UL) /!< Enable patch on write. /
emilmont	80:8e73be2a2ac1	4737
emilmont	80:8e73be2a2ac1	4738	/* Bit 2 : Patch 2 enabled. */
emilmont	80:8e73be2a2ac1	4739	#define PU_PATCHENSET_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
emilmont	80:8e73be2a2ac1	4740	#define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
emilmont	80:8e73be2a2ac1	4741	#define PU_PATCHENSET_PATCH2_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4742	#define PU_PATCHENSET_PATCH2_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4743	#define PU_PATCHENSET_PATCH2_Set (1UL) /!< Enable patch on write. /
emilmont	80:8e73be2a2ac1	4744
emilmont	80:8e73be2a2ac1	4745	/* Bit 1 : Patch 1 enabled. */
emilmont	80:8e73be2a2ac1	4746	#define PU_PATCHENSET_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
emilmont	80:8e73be2a2ac1	4747	#define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
emilmont	80:8e73be2a2ac1	4748	#define PU_PATCHENSET_PATCH1_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4749	#define PU_PATCHENSET_PATCH1_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4750	#define PU_PATCHENSET_PATCH1_Set (1UL) /!< Enable patch on write. /
emilmont	80:8e73be2a2ac1	4751
emilmont	80:8e73be2a2ac1	4752	/* Bit 0 : Patch 0 enabled. */
emilmont	80:8e73be2a2ac1	4753	#define PU_PATCHENSET_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
emilmont	80:8e73be2a2ac1	4754	#define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
emilmont	80:8e73be2a2ac1	4755	#define PU_PATCHENSET_PATCH0_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4756	#define PU_PATCHENSET_PATCH0_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4757	#define PU_PATCHENSET_PATCH0_Set (1UL) /!< Enable patch on write. /
emilmont	80:8e73be2a2ac1	4758
emilmont	80:8e73be2a2ac1	4759	/* Register: PU_PATCHENCLR */
emilmont	80:8e73be2a2ac1	4760	/* Description: Patch disable register. */
emilmont	80:8e73be2a2ac1	4761
emilmont	80:8e73be2a2ac1	4762	/* Bit 7 : Patch 7 enabled. */
emilmont	80:8e73be2a2ac1	4763	#define PU_PATCHENCLR_PATCH7_Pos (7UL) /!< Position of PATCH7 field. /
emilmont	80:8e73be2a2ac1	4764	#define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /!< Bit mask of PATCH7 field. /
emilmont	80:8e73be2a2ac1	4765	#define PU_PATCHENCLR_PATCH7_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4766	#define PU_PATCHENCLR_PATCH7_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4767	#define PU_PATCHENCLR_PATCH7_Clear (1UL) /!< Disable patch on write. /
emilmont	80:8e73be2a2ac1	4768
emilmont	80:8e73be2a2ac1	4769	/* Bit 6 : Patch 6 enabled. */
emilmont	80:8e73be2a2ac1	4770	#define PU_PATCHENCLR_PATCH6_Pos (6UL) /!< Position of PATCH6 field. /
emilmont	80:8e73be2a2ac1	4771	#define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /!< Bit mask of PATCH6 field. /
emilmont	80:8e73be2a2ac1	4772	#define PU_PATCHENCLR_PATCH6_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4773	#define PU_PATCHENCLR_PATCH6_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4774	#define PU_PATCHENCLR_PATCH6_Clear (1UL) /!< Disable patch on write. /
emilmont	80:8e73be2a2ac1	4775
emilmont	80:8e73be2a2ac1	4776	/* Bit 5 : Patch 5 enabled. */
emilmont	80:8e73be2a2ac1	4777	#define PU_PATCHENCLR_PATCH5_Pos (5UL) /!< Position of PATCH5 field. /
emilmont	80:8e73be2a2ac1	4778	#define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /!< Bit mask of PATCH5 field. /
emilmont	80:8e73be2a2ac1	4779	#define PU_PATCHENCLR_PATCH5_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4780	#define PU_PATCHENCLR_PATCH5_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4781	#define PU_PATCHENCLR_PATCH5_Clear (1UL) /!< Disable patch on write. /
emilmont	80:8e73be2a2ac1	4782
emilmont	80:8e73be2a2ac1	4783	/* Bit 4 : Patch 4 enabled. */
emilmont	80:8e73be2a2ac1	4784	#define PU_PATCHENCLR_PATCH4_Pos (4UL) /!< Position of PATCH4 field. /
emilmont	80:8e73be2a2ac1	4785	#define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /!< Bit mask of PATCH4 field. /
emilmont	80:8e73be2a2ac1	4786	#define PU_PATCHENCLR_PATCH4_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4787	#define PU_PATCHENCLR_PATCH4_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4788	#define PU_PATCHENCLR_PATCH4_Clear (1UL) /!< Disable patch on write. /
emilmont	80:8e73be2a2ac1	4789
emilmont	80:8e73be2a2ac1	4790	/* Bit 3 : Patch 3 enabled. */
emilmont	80:8e73be2a2ac1	4791	#define PU_PATCHENCLR_PATCH3_Pos (3UL) /!< Position of PATCH3 field. /
emilmont	80:8e73be2a2ac1	4792	#define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /!< Bit mask of PATCH3 field. /
emilmont	80:8e73be2a2ac1	4793	#define PU_PATCHENCLR_PATCH3_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4794	#define PU_PATCHENCLR_PATCH3_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4795	#define PU_PATCHENCLR_PATCH3_Clear (1UL) /!< Disable patch on write. /
emilmont	80:8e73be2a2ac1	4796
emilmont	80:8e73be2a2ac1	4797	/* Bit 2 : Patch 2 enabled. */
emilmont	80:8e73be2a2ac1	4798	#define PU_PATCHENCLR_PATCH2_Pos (2UL) /!< Position of PATCH2 field. /
emilmont	80:8e73be2a2ac1	4799	#define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /!< Bit mask of PATCH2 field. /
emilmont	80:8e73be2a2ac1	4800	#define PU_PATCHENCLR_PATCH2_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4801	#define PU_PATCHENCLR_PATCH2_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4802	#define PU_PATCHENCLR_PATCH2_Clear (1UL) /!< Disable patch on write. /
emilmont	80:8e73be2a2ac1	4803
emilmont	80:8e73be2a2ac1	4804	/* Bit 1 : Patch 1 enabled. */
emilmont	80:8e73be2a2ac1	4805	#define PU_PATCHENCLR_PATCH1_Pos (1UL) /!< Position of PATCH1 field. /
emilmont	80:8e73be2a2ac1	4806	#define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /!< Bit mask of PATCH1 field. /
emilmont	80:8e73be2a2ac1	4807	#define PU_PATCHENCLR_PATCH1_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4808	#define PU_PATCHENCLR_PATCH1_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4809	#define PU_PATCHENCLR_PATCH1_Clear (1UL) /!< Disable patch on write. /
emilmont	80:8e73be2a2ac1	4810
emilmont	80:8e73be2a2ac1	4811	/* Bit 0 : Patch 0 enabled. */
emilmont	80:8e73be2a2ac1	4812	#define PU_PATCHENCLR_PATCH0_Pos (0UL) /!< Position of PATCH0 field. /
emilmont	80:8e73be2a2ac1	4813	#define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /!< Bit mask of PATCH0 field. /
emilmont	80:8e73be2a2ac1	4814	#define PU_PATCHENCLR_PATCH0_Disabled (0UL) /!< Patch disabled. /
emilmont	80:8e73be2a2ac1	4815	#define PU_PATCHENCLR_PATCH0_Enabled (1UL) /!< Patch enabled. /
emilmont	80:8e73be2a2ac1	4816	#define PU_PATCHENCLR_PATCH0_Clear (1UL) /!< Disable patch on write. /
emilmont	80:8e73be2a2ac1	4817
emilmont	80:8e73be2a2ac1	4818
emilmont	80:8e73be2a2ac1	4819	/* Peripheral: QDEC */
emilmont	80:8e73be2a2ac1	4820	/* Description: Rotary decoder. */
emilmont	80:8e73be2a2ac1	4821
emilmont	80:8e73be2a2ac1	4822	/* Register: QDEC_SHORTS */
Kojto	97:433970e64889	4823	/* Description: Shortcuts for the QDEC. */
Kojto	97:433970e64889	4824
Kojto	97:433970e64889	4825	/* Bit 1 : Shortcut between SAMPLERDY event and STOP task. */
emilmont	80:8e73be2a2ac1	4826	#define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /!< Position of SAMPLERDY_STOP field. /
emilmont	80:8e73be2a2ac1	4827	#define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /!< Bit mask of SAMPLERDY_STOP field. /
emilmont	80:8e73be2a2ac1	4828	#define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	4829	#define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	4830
Kojto	97:433970e64889	4831	/* Bit 0 : Shortcut between REPORTRDY event and READCLRACC task. */
emilmont	80:8e73be2a2ac1	4832	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /!< Position of REPORTRDY_READCLRACC field. /
emilmont	80:8e73be2a2ac1	4833	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /!< Bit mask of REPORTRDY_READCLRACC field. /
emilmont	80:8e73be2a2ac1	4834	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	4835	#define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	4836
emilmont	80:8e73be2a2ac1	4837	/* Register: QDEC_INTENSET */
emilmont	80:8e73be2a2ac1	4838	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	4839
emilmont	80:8e73be2a2ac1	4840	/* Bit 2 : Enable interrupt on ACCOF event. */
emilmont	80:8e73be2a2ac1	4841	#define QDEC_INTENSET_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
emilmont	80:8e73be2a2ac1	4842	#define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /!< Bit mask of ACCOF field. /
emilmont	80:8e73be2a2ac1	4843	#define QDEC_INTENSET_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	4844	#define QDEC_INTENSET_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	4845	#define QDEC_INTENSET_ACCOF_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	4846
emilmont	80:8e73be2a2ac1	4847	/* Bit 1 : Enable interrupt on REPORTRDY event. */
emilmont	80:8e73be2a2ac1	4848	#define QDEC_INTENSET_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
emilmont	80:8e73be2a2ac1	4849	#define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
emilmont	80:8e73be2a2ac1	4850	#define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	4851	#define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	4852	#define QDEC_INTENSET_REPORTRDY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	4853
emilmont	80:8e73be2a2ac1	4854	/* Bit 0 : Enable interrupt on SAMPLERDY event. */
emilmont	80:8e73be2a2ac1	4855	#define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
emilmont	80:8e73be2a2ac1	4856	#define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
emilmont	80:8e73be2a2ac1	4857	#define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	4858	#define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	4859	#define QDEC_INTENSET_SAMPLERDY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	4860
emilmont	80:8e73be2a2ac1	4861	/* Register: QDEC_INTENCLR */
emilmont	80:8e73be2a2ac1	4862	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	4863
emilmont	80:8e73be2a2ac1	4864	/* Bit 2 : Disable interrupt on ACCOF event. */
emilmont	80:8e73be2a2ac1	4865	#define QDEC_INTENCLR_ACCOF_Pos (2UL) /!< Position of ACCOF field. /
emilmont	80:8e73be2a2ac1	4866	#define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /!< Bit mask of ACCOF field. /
emilmont	80:8e73be2a2ac1	4867	#define QDEC_INTENCLR_ACCOF_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	4868	#define QDEC_INTENCLR_ACCOF_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	4869	#define QDEC_INTENCLR_ACCOF_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	4870
emilmont	80:8e73be2a2ac1	4871	/* Bit 1 : Disable interrupt on REPORTRDY event. */
emilmont	80:8e73be2a2ac1	4872	#define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /!< Position of REPORTRDY field. /
emilmont	80:8e73be2a2ac1	4873	#define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /!< Bit mask of REPORTRDY field. /
emilmont	80:8e73be2a2ac1	4874	#define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	4875	#define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	4876	#define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	4877
emilmont	80:8e73be2a2ac1	4878	/* Bit 0 : Disable interrupt on SAMPLERDY event. */
emilmont	80:8e73be2a2ac1	4879	#define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /!< Position of SAMPLERDY field. /
emilmont	80:8e73be2a2ac1	4880	#define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /!< Bit mask of SAMPLERDY field. /
emilmont	80:8e73be2a2ac1	4881	#define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	4882	#define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	4883	#define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	4884
emilmont	80:8e73be2a2ac1	4885	/* Register: QDEC_ENABLE */
emilmont	80:8e73be2a2ac1	4886	/* Description: Enable the QDEC. */
emilmont	80:8e73be2a2ac1	4887
emilmont	80:8e73be2a2ac1	4888	/* Bit 0 : Enable or disable QDEC. */
emilmont	80:8e73be2a2ac1	4889	#define QDEC_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	4890	#define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	4891	#define QDEC_ENABLE_ENABLE_Disabled (0UL) /!< Disabled QDEC. /
emilmont	80:8e73be2a2ac1	4892	#define QDEC_ENABLE_ENABLE_Enabled (1UL) /!< Enable QDEC. /
emilmont	80:8e73be2a2ac1	4893
emilmont	80:8e73be2a2ac1	4894	/* Register: QDEC_LEDPOL */
emilmont	80:8e73be2a2ac1	4895	/* Description: LED output pin polarity. */
emilmont	80:8e73be2a2ac1	4896
emilmont	80:8e73be2a2ac1	4897	/* Bit 0 : LED output pin polarity. */
emilmont	80:8e73be2a2ac1	4898	#define QDEC_LEDPOL_LEDPOL_Pos (0UL) /!< Position of LEDPOL field. /
emilmont	80:8e73be2a2ac1	4899	#define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /!< Bit mask of LEDPOL field. /
emilmont	80:8e73be2a2ac1	4900	#define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /!< LED output is active low. /
emilmont	80:8e73be2a2ac1	4901	#define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /!< LED output is active high. /
emilmont	80:8e73be2a2ac1	4902
emilmont	80:8e73be2a2ac1	4903	/* Register: QDEC_SAMPLEPER */
emilmont	80:8e73be2a2ac1	4904	/* Description: Sample period. */
emilmont	80:8e73be2a2ac1	4905
emilmont	80:8e73be2a2ac1	4906	/* Bits 2..0 : Sample period. */
emilmont	80:8e73be2a2ac1	4907	#define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /!< Position of SAMPLEPER field. /
emilmont	80:8e73be2a2ac1	4908	#define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /!< Bit mask of SAMPLEPER field. /
emilmont	80:8e73be2a2ac1	4909	#define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /!< 128us sample period. /
emilmont	80:8e73be2a2ac1	4910	#define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /!< 256us sample period. /
emilmont	80:8e73be2a2ac1	4911	#define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /!< 512us sample period. /
emilmont	80:8e73be2a2ac1	4912	#define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /!< 1024us sample period. /
emilmont	80:8e73be2a2ac1	4913	#define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /!< 2048us sample period. /
emilmont	80:8e73be2a2ac1	4914	#define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /!< 4096us sample period. /
emilmont	80:8e73be2a2ac1	4915	#define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /!< 8192us sample period. /
emilmont	80:8e73be2a2ac1	4916	#define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /!< 16384us sample period. /
emilmont	80:8e73be2a2ac1	4917
emilmont	80:8e73be2a2ac1	4918	/* Register: QDEC_SAMPLE */
emilmont	80:8e73be2a2ac1	4919	/* Description: Motion sample value. */
emilmont	80:8e73be2a2ac1	4920
emilmont	80:8e73be2a2ac1	4921	/* Bits 31..0 : Last sample taken in compliment to 2. */
emilmont	80:8e73be2a2ac1	4922	#define QDEC_SAMPLE_SAMPLE_Pos (0UL) /!< Position of SAMPLE field. /
emilmont	80:8e73be2a2ac1	4923	#define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /!< Bit mask of SAMPLE field. /
emilmont	80:8e73be2a2ac1	4924
emilmont	80:8e73be2a2ac1	4925	/* Register: QDEC_REPORTPER */
emilmont	80:8e73be2a2ac1	4926	/* Description: Number of samples to generate an EVENT_REPORTRDY. */
emilmont	80:8e73be2a2ac1	4927
emilmont	80:8e73be2a2ac1	4928	/* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
emilmont	80:8e73be2a2ac1	4929	#define QDEC_REPORTPER_REPORTPER_Pos (0UL) /!< Position of REPORTPER field. /
emilmont	80:8e73be2a2ac1	4930	#define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /!< Bit mask of REPORTPER field. /
emilmont	80:8e73be2a2ac1	4931	#define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /!< 10 samples per report. /
emilmont	80:8e73be2a2ac1	4932	#define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /!< 40 samples per report. /
emilmont	80:8e73be2a2ac1	4933	#define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /!< 80 samples per report. /
emilmont	80:8e73be2a2ac1	4934	#define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /!< 120 samples per report. /
emilmont	80:8e73be2a2ac1	4935	#define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /!< 160 samples per report. /
emilmont	80:8e73be2a2ac1	4936	#define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /!< 200 samples per report. /
emilmont	80:8e73be2a2ac1	4937	#define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /!< 240 samples per report. /
emilmont	80:8e73be2a2ac1	4938	#define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /!< 280 samples per report. /
emilmont	80:8e73be2a2ac1	4939
emilmont	80:8e73be2a2ac1	4940	/* Register: QDEC_DBFEN */
emilmont	80:8e73be2a2ac1	4941	/* Description: Enable debouncer input filters. */
emilmont	80:8e73be2a2ac1	4942
emilmont	80:8e73be2a2ac1	4943	/* Bit 0 : Enable debounce input filters. */
emilmont	80:8e73be2a2ac1	4944	#define QDEC_DBFEN_DBFEN_Pos (0UL) /!< Position of DBFEN field. /
emilmont	80:8e73be2a2ac1	4945	#define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /!< Bit mask of DBFEN field. /
emilmont	80:8e73be2a2ac1	4946	#define QDEC_DBFEN_DBFEN_Disabled (0UL) /!< Debounce input filters disabled. /
emilmont	80:8e73be2a2ac1	4947	#define QDEC_DBFEN_DBFEN_Enabled (1UL) /!< Debounce input filters enabled. /
emilmont	80:8e73be2a2ac1	4948
emilmont	80:8e73be2a2ac1	4949	/* Register: QDEC_LEDPRE */
emilmont	80:8e73be2a2ac1	4950	/* Description: Time LED is switched ON before the sample. */
emilmont	80:8e73be2a2ac1	4951
Kojto	97:433970e64889	4952	/* Bits 8..0 : Period in us the LED in switched on prior to sampling. */
emilmont	80:8e73be2a2ac1	4953	#define QDEC_LEDPRE_LEDPRE_Pos (0UL) /!< Position of LEDPRE field. /
Kojto	97:433970e64889	4954	#define QDEC_LEDPRE_LEDPRE_Msk (0x1FFUL << QDEC_LEDPRE_LEDPRE_Pos) /!< Bit mask of LEDPRE field. /
emilmont	80:8e73be2a2ac1	4955
emilmont	80:8e73be2a2ac1	4956	/* Register: QDEC_ACCDBL */
emilmont	80:8e73be2a2ac1	4957	/* Description: Accumulated double (error) transitions register. */
emilmont	80:8e73be2a2ac1	4958
emilmont	80:8e73be2a2ac1	4959	/* Bits 3..0 : Accumulated double (error) transitions. */
emilmont	80:8e73be2a2ac1	4960	#define QDEC_ACCDBL_ACCDBL_Pos (0UL) /!< Position of ACCDBL field. /
emilmont	80:8e73be2a2ac1	4961	#define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /!< Bit mask of ACCDBL field. /
emilmont	80:8e73be2a2ac1	4962
emilmont	80:8e73be2a2ac1	4963	/* Register: QDEC_ACCDBLREAD */
emilmont	80:8e73be2a2ac1	4964	/* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
emilmont	80:8e73be2a2ac1	4965
emilmont	80:8e73be2a2ac1	4966	/* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
emilmont	80:8e73be2a2ac1	4967	#define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /!< Position of ACCDBLREAD field. /
emilmont	80:8e73be2a2ac1	4968	#define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /!< Bit mask of ACCDBLREAD field. /
emilmont	80:8e73be2a2ac1	4969
emilmont	80:8e73be2a2ac1	4970	/* Register: QDEC_POWER */
emilmont	80:8e73be2a2ac1	4971	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	4972
emilmont	80:8e73be2a2ac1	4973	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	4974	#define QDEC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	4975	#define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	4976	#define QDEC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	4977	#define QDEC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	4978
emilmont	80:8e73be2a2ac1	4979
emilmont	80:8e73be2a2ac1	4980	/* Peripheral: RADIO */
emilmont	80:8e73be2a2ac1	4981	/* Description: The radio. */
emilmont	80:8e73be2a2ac1	4982
emilmont	80:8e73be2a2ac1	4983	/* Register: RADIO_SHORTS */
Kojto	97:433970e64889	4984	/* Description: Shortcuts for the radio. */
emilmont	80:8e73be2a2ac1	4985
emilmont	80:8e73be2a2ac1	4986	/* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
emilmont	80:8e73be2a2ac1	4987	#define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /!< Position of DISABLED_RSSISTOP field. /
emilmont	80:8e73be2a2ac1	4988	#define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /!< Bit mask of DISABLED_RSSISTOP field. /
emilmont	80:8e73be2a2ac1	4989	#define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	4990	#define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	4991
emilmont	80:8e73be2a2ac1	4992	/* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
emilmont	80:8e73be2a2ac1	4993	#define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /!< Position of ADDRESS_BCSTART field. /
emilmont	80:8e73be2a2ac1	4994	#define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /!< Bit mask of ADDRESS_BCSTART field. /
emilmont	80:8e73be2a2ac1	4995	#define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	4996	#define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	4997
emilmont	80:8e73be2a2ac1	4998	/* Bit 5 : Shortcut between END event and START task. */
emilmont	80:8e73be2a2ac1	4999	#define RADIO_SHORTS_END_START_Pos (5UL) /!< Position of END_START field. /
emilmont	80:8e73be2a2ac1	5000	#define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
emilmont	80:8e73be2a2ac1	5001	#define RADIO_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	5002	#define RADIO_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	5003
emilmont	80:8e73be2a2ac1	5004	/* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
emilmont	80:8e73be2a2ac1	5005	#define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /!< Position of ADDRESS_RSSISTART field. /
emilmont	80:8e73be2a2ac1	5006	#define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /!< Bit mask of ADDRESS_RSSISTART field. /
emilmont	80:8e73be2a2ac1	5007	#define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	5008	#define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	5009
emilmont	80:8e73be2a2ac1	5010	/* Bit 3 : Shortcut between DISABLED event and RXEN task. */
emilmont	80:8e73be2a2ac1	5011	#define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /!< Position of DISABLED_RXEN field. /
emilmont	80:8e73be2a2ac1	5012	#define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /!< Bit mask of DISABLED_RXEN field. /
emilmont	80:8e73be2a2ac1	5013	#define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	5014	#define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	5015
emilmont	80:8e73be2a2ac1	5016	/* Bit 2 : Shortcut between DISABLED event and TXEN task. */
emilmont	80:8e73be2a2ac1	5017	#define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /!< Position of DISABLED_TXEN field. /
emilmont	80:8e73be2a2ac1	5018	#define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /!< Bit mask of DISABLED_TXEN field. /
emilmont	80:8e73be2a2ac1	5019	#define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	5020	#define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	5021
emilmont	80:8e73be2a2ac1	5022	/* Bit 1 : Shortcut between END event and DISABLE task. */
emilmont	80:8e73be2a2ac1	5023	#define RADIO_SHORTS_END_DISABLE_Pos (1UL) /!< Position of END_DISABLE field. /
emilmont	80:8e73be2a2ac1	5024	#define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /!< Bit mask of END_DISABLE field. /
emilmont	80:8e73be2a2ac1	5025	#define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	5026	#define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	5027
emilmont	80:8e73be2a2ac1	5028	/* Bit 0 : Shortcut between READY event and START task. */
emilmont	80:8e73be2a2ac1	5029	#define RADIO_SHORTS_READY_START_Pos (0UL) /!< Position of READY_START field. /
emilmont	80:8e73be2a2ac1	5030	#define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /!< Bit mask of READY_START field. /
emilmont	80:8e73be2a2ac1	5031	#define RADIO_SHORTS_READY_START_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	5032	#define RADIO_SHORTS_READY_START_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	5033
emilmont	80:8e73be2a2ac1	5034	/* Register: RADIO_INTENSET */
emilmont	80:8e73be2a2ac1	5035	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	5036
emilmont	80:8e73be2a2ac1	5037	/* Bit 10 : Enable interrupt on BCMATCH event. */
emilmont	80:8e73be2a2ac1	5038	#define RADIO_INTENSET_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
emilmont	80:8e73be2a2ac1	5039	#define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
emilmont	80:8e73be2a2ac1	5040	#define RADIO_INTENSET_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5041	#define RADIO_INTENSET_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5042	#define RADIO_INTENSET_BCMATCH_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5043
emilmont	80:8e73be2a2ac1	5044	/* Bit 7 : Enable interrupt on RSSIEND event. */
emilmont	80:8e73be2a2ac1	5045	#define RADIO_INTENSET_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
emilmont	80:8e73be2a2ac1	5046	#define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
emilmont	80:8e73be2a2ac1	5047	#define RADIO_INTENSET_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5048	#define RADIO_INTENSET_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5049	#define RADIO_INTENSET_RSSIEND_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5050
emilmont	80:8e73be2a2ac1	5051	/* Bit 6 : Enable interrupt on DEVMISS event. */
emilmont	80:8e73be2a2ac1	5052	#define RADIO_INTENSET_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
emilmont	80:8e73be2a2ac1	5053	#define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
emilmont	80:8e73be2a2ac1	5054	#define RADIO_INTENSET_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5055	#define RADIO_INTENSET_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5056	#define RADIO_INTENSET_DEVMISS_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5057
emilmont	80:8e73be2a2ac1	5058	/* Bit 5 : Enable interrupt on DEVMATCH event. */
emilmont	80:8e73be2a2ac1	5059	#define RADIO_INTENSET_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
emilmont	80:8e73be2a2ac1	5060	#define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
emilmont	80:8e73be2a2ac1	5061	#define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5062	#define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5063	#define RADIO_INTENSET_DEVMATCH_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5064
emilmont	80:8e73be2a2ac1	5065	/* Bit 4 : Enable interrupt on DISABLED event. */
emilmont	80:8e73be2a2ac1	5066	#define RADIO_INTENSET_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
emilmont	80:8e73be2a2ac1	5067	#define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /!< Bit mask of DISABLED field. /
emilmont	80:8e73be2a2ac1	5068	#define RADIO_INTENSET_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5069	#define RADIO_INTENSET_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5070	#define RADIO_INTENSET_DISABLED_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5071
emilmont	80:8e73be2a2ac1	5072	/* Bit 3 : Enable interrupt on END event. */
emilmont	80:8e73be2a2ac1	5073	#define RADIO_INTENSET_END_Pos (3UL) /!< Position of END field. /
emilmont	80:8e73be2a2ac1	5074	#define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /!< Bit mask of END field. /
emilmont	80:8e73be2a2ac1	5075	#define RADIO_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5076	#define RADIO_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5077	#define RADIO_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5078
emilmont	80:8e73be2a2ac1	5079	/* Bit 2 : Enable interrupt on PAYLOAD event. */
emilmont	80:8e73be2a2ac1	5080	#define RADIO_INTENSET_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
emilmont	80:8e73be2a2ac1	5081	#define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
emilmont	80:8e73be2a2ac1	5082	#define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5083	#define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5084	#define RADIO_INTENSET_PAYLOAD_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5085
emilmont	80:8e73be2a2ac1	5086	/* Bit 1 : Enable interrupt on ADDRESS event. */
emilmont	80:8e73be2a2ac1	5087	#define RADIO_INTENSET_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
emilmont	80:8e73be2a2ac1	5088	#define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
emilmont	80:8e73be2a2ac1	5089	#define RADIO_INTENSET_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5090	#define RADIO_INTENSET_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5091	#define RADIO_INTENSET_ADDRESS_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5092
emilmont	80:8e73be2a2ac1	5093	/* Bit 0 : Enable interrupt on READY event. */
emilmont	80:8e73be2a2ac1	5094	#define RADIO_INTENSET_READY_Pos (0UL) /!< Position of READY field. /
emilmont	80:8e73be2a2ac1	5095	#define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /!< Bit mask of READY field. /
emilmont	80:8e73be2a2ac1	5096	#define RADIO_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5097	#define RADIO_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5098	#define RADIO_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5099
emilmont	80:8e73be2a2ac1	5100	/* Register: RADIO_INTENCLR */
emilmont	80:8e73be2a2ac1	5101	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	5102
emilmont	80:8e73be2a2ac1	5103	/* Bit 10 : Disable interrupt on BCMATCH event. */
emilmont	80:8e73be2a2ac1	5104	#define RADIO_INTENCLR_BCMATCH_Pos (10UL) /!< Position of BCMATCH field. /
emilmont	80:8e73be2a2ac1	5105	#define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /!< Bit mask of BCMATCH field. /
emilmont	80:8e73be2a2ac1	5106	#define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5107	#define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5108	#define RADIO_INTENCLR_BCMATCH_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5109
emilmont	80:8e73be2a2ac1	5110	/* Bit 7 : Disable interrupt on RSSIEND event. */
emilmont	80:8e73be2a2ac1	5111	#define RADIO_INTENCLR_RSSIEND_Pos (7UL) /!< Position of RSSIEND field. /
emilmont	80:8e73be2a2ac1	5112	#define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /!< Bit mask of RSSIEND field. /
emilmont	80:8e73be2a2ac1	5113	#define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5114	#define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5115	#define RADIO_INTENCLR_RSSIEND_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5116
emilmont	80:8e73be2a2ac1	5117	/* Bit 6 : Disable interrupt on DEVMISS event. */
emilmont	80:8e73be2a2ac1	5118	#define RADIO_INTENCLR_DEVMISS_Pos (6UL) /!< Position of DEVMISS field. /
emilmont	80:8e73be2a2ac1	5119	#define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /!< Bit mask of DEVMISS field. /
emilmont	80:8e73be2a2ac1	5120	#define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5121	#define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5122	#define RADIO_INTENCLR_DEVMISS_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5123
emilmont	80:8e73be2a2ac1	5124	/* Bit 5 : Disable interrupt on DEVMATCH event. */
emilmont	80:8e73be2a2ac1	5125	#define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /!< Position of DEVMATCH field. /
emilmont	80:8e73be2a2ac1	5126	#define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /!< Bit mask of DEVMATCH field. /
emilmont	80:8e73be2a2ac1	5127	#define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5128	#define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5129	#define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5130
emilmont	80:8e73be2a2ac1	5131	/* Bit 4 : Disable interrupt on DISABLED event. */
emilmont	80:8e73be2a2ac1	5132	#define RADIO_INTENCLR_DISABLED_Pos (4UL) /!< Position of DISABLED field. /
emilmont	80:8e73be2a2ac1	5133	#define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /!< Bit mask of DISABLED field. /
emilmont	80:8e73be2a2ac1	5134	#define RADIO_INTENCLR_DISABLED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5135	#define RADIO_INTENCLR_DISABLED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5136	#define RADIO_INTENCLR_DISABLED_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5137
emilmont	80:8e73be2a2ac1	5138	/* Bit 3 : Disable interrupt on END event. */
emilmont	80:8e73be2a2ac1	5139	#define RADIO_INTENCLR_END_Pos (3UL) /!< Position of END field. /
emilmont	80:8e73be2a2ac1	5140	#define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /!< Bit mask of END field. /
emilmont	80:8e73be2a2ac1	5141	#define RADIO_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5142	#define RADIO_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5143	#define RADIO_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5144
emilmont	80:8e73be2a2ac1	5145	/* Bit 2 : Disable interrupt on PAYLOAD event. */
emilmont	80:8e73be2a2ac1	5146	#define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /!< Position of PAYLOAD field. /
emilmont	80:8e73be2a2ac1	5147	#define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /!< Bit mask of PAYLOAD field. /
emilmont	80:8e73be2a2ac1	5148	#define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5149	#define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5150	#define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5151
emilmont	80:8e73be2a2ac1	5152	/* Bit 1 : Disable interrupt on ADDRESS event. */
emilmont	80:8e73be2a2ac1	5153	#define RADIO_INTENCLR_ADDRESS_Pos (1UL) /!< Position of ADDRESS field. /
emilmont	80:8e73be2a2ac1	5154	#define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
emilmont	80:8e73be2a2ac1	5155	#define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5156	#define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5157	#define RADIO_INTENCLR_ADDRESS_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5158
emilmont	80:8e73be2a2ac1	5159	/* Bit 0 : Disable interrupt on READY event. */
emilmont	80:8e73be2a2ac1	5160	#define RADIO_INTENCLR_READY_Pos (0UL) /!< Position of READY field. /
emilmont	80:8e73be2a2ac1	5161	#define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
emilmont	80:8e73be2a2ac1	5162	#define RADIO_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5163	#define RADIO_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5164	#define RADIO_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5165
emilmont	80:8e73be2a2ac1	5166	/* Register: RADIO_CRCSTATUS */
emilmont	80:8e73be2a2ac1	5167	/* Description: CRC status of received packet. */
emilmont	80:8e73be2a2ac1	5168
emilmont	80:8e73be2a2ac1	5169	/* Bit 0 : CRC status of received packet. */
emilmont	80:8e73be2a2ac1	5170	#define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /!< Position of CRCSTATUS field. /
emilmont	80:8e73be2a2ac1	5171	#define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /!< Bit mask of CRCSTATUS field. /
emilmont	80:8e73be2a2ac1	5172	#define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /!< Packet received with CRC error. /
emilmont	80:8e73be2a2ac1	5173	#define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /!< Packet received with CRC ok. /
emilmont	80:8e73be2a2ac1	5174
Kojto	97:433970e64889	5175	/* Register: RADIO_CD */
Kojto	97:433970e64889	5176	/* Description: Carrier detect. */
Kojto	97:433970e64889	5177
Kojto	97:433970e64889	5178	/* Bit 0 : Carrier detect. */
Kojto	97:433970e64889	5179	#define RADIO_CD_CD_Pos (0UL) /!< Position of CD field. /
Kojto	97:433970e64889	5180	#define RADIO_CD_CD_Msk (0x1UL << RADIO_CD_CD_Pos) /!< Bit mask of CD field. /
Kojto	97:433970e64889	5181
emilmont	80:8e73be2a2ac1	5182	/* Register: RADIO_RXMATCH */
emilmont	80:8e73be2a2ac1	5183	/* Description: Received address. */
emilmont	80:8e73be2a2ac1	5184
emilmont	80:8e73be2a2ac1	5185	/* Bits 2..0 : Logical address in which previous packet was received. */
emilmont	80:8e73be2a2ac1	5186	#define RADIO_RXMATCH_RXMATCH_Pos (0UL) /!< Position of RXMATCH field. /
emilmont	80:8e73be2a2ac1	5187	#define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /!< Bit mask of RXMATCH field. /
emilmont	80:8e73be2a2ac1	5188
emilmont	80:8e73be2a2ac1	5189	/* Register: RADIO_RXCRC */
emilmont	80:8e73be2a2ac1	5190	/* Description: Received CRC. */
emilmont	80:8e73be2a2ac1	5191
emilmont	80:8e73be2a2ac1	5192	/* Bits 23..0 : CRC field of previously received packet. */
emilmont	80:8e73be2a2ac1	5193	#define RADIO_RXCRC_RXCRC_Pos (0UL) /!< Position of RXCRC field. /
emilmont	80:8e73be2a2ac1	5194	#define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /!< Bit mask of RXCRC field. /
emilmont	80:8e73be2a2ac1	5195
emilmont	80:8e73be2a2ac1	5196	/* Register: RADIO_DAI */
emilmont	80:8e73be2a2ac1	5197	/* Description: Device address match index. */
emilmont	80:8e73be2a2ac1	5198
Kojto	97:433970e64889	5199	/* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that obtained an address match. */
emilmont	80:8e73be2a2ac1	5200	#define RADIO_DAI_DAI_Pos (0UL) /!< Position of DAI field. /
emilmont	80:8e73be2a2ac1	5201	#define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /!< Bit mask of DAI field. /
emilmont	80:8e73be2a2ac1	5202
emilmont	80:8e73be2a2ac1	5203	/* Register: RADIO_FREQUENCY */
emilmont	80:8e73be2a2ac1	5204	/* Description: Frequency. */
emilmont	80:8e73be2a2ac1	5205
emilmont	80:8e73be2a2ac1	5206	/* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
emilmont	80:8e73be2a2ac1	5207	#define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
emilmont	80:8e73be2a2ac1	5208	#define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
emilmont	80:8e73be2a2ac1	5209
emilmont	80:8e73be2a2ac1	5210	/* Register: RADIO_TXPOWER */
emilmont	80:8e73be2a2ac1	5211	/* Description: Output power. */
emilmont	80:8e73be2a2ac1	5212
emilmont	80:8e73be2a2ac1	5213	/* Bits 7..0 : Radio output power. Decision point: TXEN task. */
emilmont	80:8e73be2a2ac1	5214	#define RADIO_TXPOWER_TXPOWER_Pos (0UL) /!< Position of TXPOWER field. /
emilmont	80:8e73be2a2ac1	5215	#define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /!< Bit mask of TXPOWER field. /
emilmont	80:8e73be2a2ac1	5216	#define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /!< +4dBm. /
emilmont	80:8e73be2a2ac1	5217	#define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /!< 0dBm. /
emilmont	80:8e73be2a2ac1	5218	#define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /!< -4dBm. /
emilmont	80:8e73be2a2ac1	5219	#define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /!< -8dBm. /
emilmont	80:8e73be2a2ac1	5220	#define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /!< -12dBm. /
emilmont	80:8e73be2a2ac1	5221	#define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /!< -16dBm. /
emilmont	80:8e73be2a2ac1	5222	#define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /!< -20dBm. /
emilmont	80:8e73be2a2ac1	5223	#define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /!< -30dBm. /
emilmont	80:8e73be2a2ac1	5224
emilmont	80:8e73be2a2ac1	5225	/* Register: RADIO_MODE */
emilmont	80:8e73be2a2ac1	5226	/* Description: Data rate and modulation. */
emilmont	80:8e73be2a2ac1	5227
emilmont	80:8e73be2a2ac1	5228	/* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
emilmont	80:8e73be2a2ac1	5229	#define RADIO_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
emilmont	80:8e73be2a2ac1	5230	#define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /!< Bit mask of MODE field. /
emilmont	80:8e73be2a2ac1	5231	#define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /!< 1Mbit/s Nordic propietary radio mode. /
emilmont	80:8e73be2a2ac1	5232	#define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /!< 2Mbit/s Nordic propietary radio mode. /
emilmont	80:8e73be2a2ac1	5233	#define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /!< 250kbit/s Nordic propietary radio mode. /
emilmont	80:8e73be2a2ac1	5234	#define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /!< 1Mbit/s Bluetooth Low Energy /
emilmont	80:8e73be2a2ac1	5235
emilmont	80:8e73be2a2ac1	5236	/* Register: RADIO_PCNF0 */
emilmont	80:8e73be2a2ac1	5237	/* Description: Packet configuration 0. */
emilmont	80:8e73be2a2ac1	5238
emilmont	80:8e73be2a2ac1	5239	/* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5240	#define RADIO_PCNF0_S1LEN_Pos (16UL) /!< Position of S1LEN field. /
emilmont	80:8e73be2a2ac1	5241	#define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /!< Bit mask of S1LEN field. /
emilmont	80:8e73be2a2ac1	5242
emilmont	80:8e73be2a2ac1	5243	/* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5244	#define RADIO_PCNF0_S0LEN_Pos (8UL) /!< Position of S0LEN field. /
emilmont	80:8e73be2a2ac1	5245	#define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /!< Bit mask of S0LEN field. /
emilmont	80:8e73be2a2ac1	5246
emilmont	80:8e73be2a2ac1	5247	/* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5248	#define RADIO_PCNF0_LFLEN_Pos (0UL) /!< Position of LFLEN field. /
emilmont	80:8e73be2a2ac1	5249	#define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /!< Bit mask of LFLEN field. /
emilmont	80:8e73be2a2ac1	5250
emilmont	80:8e73be2a2ac1	5251	/* Register: RADIO_PCNF1 */
emilmont	80:8e73be2a2ac1	5252	/* Description: Packet configuration 1. */
emilmont	80:8e73be2a2ac1	5253
emilmont	80:8e73be2a2ac1	5254	/* Bit 25 : Packet whitening enable. */
emilmont	80:8e73be2a2ac1	5255	#define RADIO_PCNF1_WHITEEN_Pos (25UL) /!< Position of WHITEEN field. /
emilmont	80:8e73be2a2ac1	5256	#define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /!< Bit mask of WHITEEN field. /
emilmont	80:8e73be2a2ac1	5257	#define RADIO_PCNF1_WHITEEN_Disabled (0UL) /!< Whitening disabled. /
emilmont	80:8e73be2a2ac1	5258	#define RADIO_PCNF1_WHITEEN_Enabled (1UL) /!< Whitening enabled. /
emilmont	80:8e73be2a2ac1	5259
emilmont	80:8e73be2a2ac1	5260	/* Bit 24 : On air endianness of packet length field. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5261	#define RADIO_PCNF1_ENDIAN_Pos (24UL) /!< Position of ENDIAN field. /
emilmont	80:8e73be2a2ac1	5262	#define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /!< Bit mask of ENDIAN field. /
emilmont	80:8e73be2a2ac1	5263	#define RADIO_PCNF1_ENDIAN_Little (0UL) /!< Least significant bit on air first /
emilmont	80:8e73be2a2ac1	5264	#define RADIO_PCNF1_ENDIAN_Big (1UL) /!< Most significant bit on air first /
emilmont	80:8e73be2a2ac1	5265
emilmont	80:8e73be2a2ac1	5266	/* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5267	#define RADIO_PCNF1_BALEN_Pos (16UL) /!< Position of BALEN field. /
emilmont	80:8e73be2a2ac1	5268	#define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /!< Bit mask of BALEN field. /
emilmont	80:8e73be2a2ac1	5269
emilmont	80:8e73be2a2ac1	5270	/* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5271	#define RADIO_PCNF1_STATLEN_Pos (8UL) /!< Position of STATLEN field. /
emilmont	80:8e73be2a2ac1	5272	#define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /!< Bit mask of STATLEN field. /
emilmont	80:8e73be2a2ac1	5273
emilmont	80:8e73be2a2ac1	5274	/* Bits 7..0 : Maximum length of packet payload in number of bytes. */
emilmont	80:8e73be2a2ac1	5275	#define RADIO_PCNF1_MAXLEN_Pos (0UL) /!< Position of MAXLEN field. /
emilmont	80:8e73be2a2ac1	5276	#define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /!< Bit mask of MAXLEN field. /
emilmont	80:8e73be2a2ac1	5277
emilmont	80:8e73be2a2ac1	5278	/* Register: RADIO_PREFIX0 */
emilmont	80:8e73be2a2ac1	5279	/* Description: Prefixes bytes for logical addresses 0 to 3. */
emilmont	80:8e73be2a2ac1	5280
emilmont	80:8e73be2a2ac1	5281	/* Bits 31..24 : Address prefix 3. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5282	#define RADIO_PREFIX0_AP3_Pos (24UL) /!< Position of AP3 field. /
emilmont	80:8e73be2a2ac1	5283	#define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /!< Bit mask of AP3 field. /
emilmont	80:8e73be2a2ac1	5284
emilmont	80:8e73be2a2ac1	5285	/* Bits 23..16 : Address prefix 2. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5286	#define RADIO_PREFIX0_AP2_Pos (16UL) /!< Position of AP2 field. /
emilmont	80:8e73be2a2ac1	5287	#define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /!< Bit mask of AP2 field. /
emilmont	80:8e73be2a2ac1	5288
emilmont	80:8e73be2a2ac1	5289	/* Bits 15..8 : Address prefix 1. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5290	#define RADIO_PREFIX0_AP1_Pos (8UL) /!< Position of AP1 field. /
emilmont	80:8e73be2a2ac1	5291	#define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /!< Bit mask of AP1 field. /
emilmont	80:8e73be2a2ac1	5292
emilmont	80:8e73be2a2ac1	5293	/* Bits 7..0 : Address prefix 0. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5294	#define RADIO_PREFIX0_AP0_Pos (0UL) /!< Position of AP0 field. /
emilmont	80:8e73be2a2ac1	5295	#define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /!< Bit mask of AP0 field. /
emilmont	80:8e73be2a2ac1	5296
emilmont	80:8e73be2a2ac1	5297	/* Register: RADIO_PREFIX1 */
emilmont	80:8e73be2a2ac1	5298	/* Description: Prefixes bytes for logical addresses 4 to 7. */
emilmont	80:8e73be2a2ac1	5299
emilmont	80:8e73be2a2ac1	5300	/* Bits 31..24 : Address prefix 7. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5301	#define RADIO_PREFIX1_AP7_Pos (24UL) /!< Position of AP7 field. /
emilmont	80:8e73be2a2ac1	5302	#define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /!< Bit mask of AP7 field. /
emilmont	80:8e73be2a2ac1	5303
emilmont	80:8e73be2a2ac1	5304	/* Bits 23..16 : Address prefix 6. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5305	#define RADIO_PREFIX1_AP6_Pos (16UL) /!< Position of AP6 field. /
emilmont	80:8e73be2a2ac1	5306	#define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /!< Bit mask of AP6 field. /
emilmont	80:8e73be2a2ac1	5307
emilmont	80:8e73be2a2ac1	5308	/* Bits 15..8 : Address prefix 5. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5309	#define RADIO_PREFIX1_AP5_Pos (8UL) /!< Position of AP5 field. /
emilmont	80:8e73be2a2ac1	5310	#define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /!< Bit mask of AP5 field. /
emilmont	80:8e73be2a2ac1	5311
emilmont	80:8e73be2a2ac1	5312	/* Bits 7..0 : Address prefix 4. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5313	#define RADIO_PREFIX1_AP4_Pos (0UL) /!< Position of AP4 field. /
emilmont	80:8e73be2a2ac1	5314	#define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /!< Bit mask of AP4 field. /
emilmont	80:8e73be2a2ac1	5315
emilmont	80:8e73be2a2ac1	5316	/* Register: RADIO_TXADDRESS */
emilmont	80:8e73be2a2ac1	5317	/* Description: Transmit address select. */
emilmont	80:8e73be2a2ac1	5318
emilmont	80:8e73be2a2ac1	5319	/* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5320	#define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /!< Position of TXADDRESS field. /
emilmont	80:8e73be2a2ac1	5321	#define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /!< Bit mask of TXADDRESS field. /
emilmont	80:8e73be2a2ac1	5322
emilmont	80:8e73be2a2ac1	5323	/* Register: RADIO_RXADDRESSES */
emilmont	80:8e73be2a2ac1	5324	/* Description: Receive address select. */
emilmont	80:8e73be2a2ac1	5325
emilmont	80:8e73be2a2ac1	5326	/* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5327	#define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /!< Position of ADDR7 field. /
emilmont	80:8e73be2a2ac1	5328	#define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /!< Bit mask of ADDR7 field. /
emilmont	80:8e73be2a2ac1	5329	#define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /!< Reception disabled. /
emilmont	80:8e73be2a2ac1	5330	#define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /!< Reception enabled. /
emilmont	80:8e73be2a2ac1	5331
emilmont	80:8e73be2a2ac1	5332	/* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5333	#define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /!< Position of ADDR6 field. /
emilmont	80:8e73be2a2ac1	5334	#define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /!< Bit mask of ADDR6 field. /
emilmont	80:8e73be2a2ac1	5335	#define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /!< Reception disabled. /
emilmont	80:8e73be2a2ac1	5336	#define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /!< Reception enabled. /
emilmont	80:8e73be2a2ac1	5337
emilmont	80:8e73be2a2ac1	5338	/* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5339	#define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /!< Position of ADDR5 field. /
emilmont	80:8e73be2a2ac1	5340	#define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /!< Bit mask of ADDR5 field. /
emilmont	80:8e73be2a2ac1	5341	#define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /!< Reception disabled. /
emilmont	80:8e73be2a2ac1	5342	#define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /!< Reception enabled. /
emilmont	80:8e73be2a2ac1	5343
emilmont	80:8e73be2a2ac1	5344	/* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5345	#define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /!< Position of ADDR4 field. /
emilmont	80:8e73be2a2ac1	5346	#define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /!< Bit mask of ADDR4 field. /
emilmont	80:8e73be2a2ac1	5347	#define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /!< Reception disabled. /
emilmont	80:8e73be2a2ac1	5348	#define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /!< Reception enabled. /
emilmont	80:8e73be2a2ac1	5349
emilmont	80:8e73be2a2ac1	5350	/* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5351	#define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /!< Position of ADDR3 field. /
emilmont	80:8e73be2a2ac1	5352	#define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /!< Bit mask of ADDR3 field. /
emilmont	80:8e73be2a2ac1	5353	#define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /!< Reception disabled. /
emilmont	80:8e73be2a2ac1	5354	#define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /!< Reception enabled. /
emilmont	80:8e73be2a2ac1	5355
emilmont	80:8e73be2a2ac1	5356	/* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5357	#define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /!< Position of ADDR2 field. /
emilmont	80:8e73be2a2ac1	5358	#define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /!< Bit mask of ADDR2 field. /
emilmont	80:8e73be2a2ac1	5359	#define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /!< Reception disabled. /
emilmont	80:8e73be2a2ac1	5360	#define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /!< Reception enabled. /
emilmont	80:8e73be2a2ac1	5361
emilmont	80:8e73be2a2ac1	5362	/* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5363	#define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /!< Position of ADDR1 field. /
emilmont	80:8e73be2a2ac1	5364	#define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /!< Bit mask of ADDR1 field. /
emilmont	80:8e73be2a2ac1	5365	#define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /!< Reception disabled. /
emilmont	80:8e73be2a2ac1	5366	#define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /!< Reception enabled. /
emilmont	80:8e73be2a2ac1	5367
emilmont	80:8e73be2a2ac1	5368	/* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5369	#define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /!< Position of ADDR0 field. /
emilmont	80:8e73be2a2ac1	5370	#define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /!< Bit mask of ADDR0 field. /
emilmont	80:8e73be2a2ac1	5371	#define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /!< Reception disabled. /
emilmont	80:8e73be2a2ac1	5372	#define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /!< Reception enabled. /
emilmont	80:8e73be2a2ac1	5373
emilmont	80:8e73be2a2ac1	5374	/* Register: RADIO_CRCCNF */
emilmont	80:8e73be2a2ac1	5375	/* Description: CRC configuration. */
emilmont	80:8e73be2a2ac1	5376
emilmont	80:8e73be2a2ac1	5377	/* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
Kojto	97:433970e64889	5378	#define RADIO_CRCCNF_SKIPADDR_Pos (8UL) /!< Position of SKIPADDR field. /
Kojto	97:433970e64889	5379	#define RADIO_CRCCNF_SKIPADDR_Msk (0x1UL << RADIO_CRCCNF_SKIPADDR_Pos) /!< Bit mask of SKIPADDR field. /
Kojto	97:433970e64889	5380	#define RADIO_CRCCNF_SKIPADDR_Include (0UL) /!< Include packet address in CRC calculation. /
Kojto	97:433970e64889	5381	#define RADIO_CRCCNF_SKIPADDR_Skip (1UL) /!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. /
emilmont	80:8e73be2a2ac1	5382
emilmont	80:8e73be2a2ac1	5383	/* Bits 1..0 : CRC length. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5384	#define RADIO_CRCCNF_LEN_Pos (0UL) /!< Position of LEN field. /
emilmont	80:8e73be2a2ac1	5385	#define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /!< Bit mask of LEN field. /
emilmont	80:8e73be2a2ac1	5386	#define RADIO_CRCCNF_LEN_Disabled (0UL) /!< CRC calculation disabled. /
emilmont	80:8e73be2a2ac1	5387	#define RADIO_CRCCNF_LEN_One (1UL) /!< One byte long CRC. /
emilmont	80:8e73be2a2ac1	5388	#define RADIO_CRCCNF_LEN_Two (2UL) /!< Two bytes long CRC. /
emilmont	80:8e73be2a2ac1	5389	#define RADIO_CRCCNF_LEN_Three (3UL) /!< Three bytes long CRC. /
emilmont	80:8e73be2a2ac1	5390
emilmont	80:8e73be2a2ac1	5391	/* Register: RADIO_CRCPOLY */
emilmont	80:8e73be2a2ac1	5392	/* Description: CRC polynomial. */
emilmont	80:8e73be2a2ac1	5393
Kojto	97:433970e64889	5394	/* Bits 23..0 : CRC polynomial. Decision point: START task. */
Kojto	97:433970e64889	5395	#define RADIO_CRCPOLY_CRCPOLY_Pos (0UL) /!< Position of CRCPOLY field. /
Kojto	97:433970e64889	5396	#define RADIO_CRCPOLY_CRCPOLY_Msk (0xFFFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /!< Bit mask of CRCPOLY field. /
emilmont	80:8e73be2a2ac1	5397
emilmont	80:8e73be2a2ac1	5398	/* Register: RADIO_CRCINIT */
emilmont	80:8e73be2a2ac1	5399	/* Description: CRC initial value. */
emilmont	80:8e73be2a2ac1	5400
emilmont	80:8e73be2a2ac1	5401	/* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
emilmont	80:8e73be2a2ac1	5402	#define RADIO_CRCINIT_CRCINIT_Pos (0UL) /!< Position of CRCINIT field. /
emilmont	80:8e73be2a2ac1	5403	#define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /!< Bit mask of CRCINIT field. /
emilmont	80:8e73be2a2ac1	5404
emilmont	80:8e73be2a2ac1	5405	/* Register: RADIO_TEST */
emilmont	80:8e73be2a2ac1	5406	/* Description: Test features enable register. */
emilmont	80:8e73be2a2ac1	5407
emilmont	80:8e73be2a2ac1	5408	/* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
Kojto	97:433970e64889	5409	#define RADIO_TEST_PLLLOCK_Pos (1UL) /!< Position of PLLLOCK field. /
Kojto	97:433970e64889	5410	#define RADIO_TEST_PLLLOCK_Msk (0x1UL << RADIO_TEST_PLLLOCK_Pos) /!< Bit mask of PLLLOCK field. /
Kojto	97:433970e64889	5411	#define RADIO_TEST_PLLLOCK_Disabled (0UL) /!< PLL lock disabled. /
Kojto	97:433970e64889	5412	#define RADIO_TEST_PLLLOCK_Enabled (1UL) /!< PLL lock enabled. /
emilmont	80:8e73be2a2ac1	5413
emilmont	80:8e73be2a2ac1	5414	/* Bit 0 : Constant carrier. Decision point: TXEN task. */
Kojto	97:433970e64889	5415	#define RADIO_TEST_CONSTCARRIER_Pos (0UL) /!< Position of CONSTCARRIER field. /
Kojto	97:433970e64889	5416	#define RADIO_TEST_CONSTCARRIER_Msk (0x1UL << RADIO_TEST_CONSTCARRIER_Pos) /!< Bit mask of CONSTCARRIER field. /
Kojto	97:433970e64889	5417	#define RADIO_TEST_CONSTCARRIER_Disabled (0UL) /!< Constant carrier disabled. /
Kojto	97:433970e64889	5418	#define RADIO_TEST_CONSTCARRIER_Enabled (1UL) /!< Constant carrier enabled. /
emilmont	80:8e73be2a2ac1	5419
emilmont	80:8e73be2a2ac1	5420	/* Register: RADIO_TIFS */
emilmont	80:8e73be2a2ac1	5421	/* Description: Inter Frame Spacing in microseconds. */
emilmont	80:8e73be2a2ac1	5422
emilmont	80:8e73be2a2ac1	5423	/* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
emilmont	80:8e73be2a2ac1	5424	#define RADIO_TIFS_TIFS_Pos (0UL) /!< Position of TIFS field. /
emilmont	80:8e73be2a2ac1	5425	#define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /!< Bit mask of TIFS field. /
emilmont	80:8e73be2a2ac1	5426
emilmont	80:8e73be2a2ac1	5427	/* Register: RADIO_RSSISAMPLE */
emilmont	80:8e73be2a2ac1	5428	/* Description: RSSI sample. */
emilmont	80:8e73be2a2ac1	5429
emilmont	80:8e73be2a2ac1	5430	/* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
emilmont	80:8e73be2a2ac1	5431	#define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /!< Position of RSSISAMPLE field. /
emilmont	80:8e73be2a2ac1	5432	#define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /!< Bit mask of RSSISAMPLE field. /
emilmont	80:8e73be2a2ac1	5433
emilmont	80:8e73be2a2ac1	5434	/* Register: RADIO_STATE */
emilmont	80:8e73be2a2ac1	5435	/* Description: Current radio state. */
emilmont	80:8e73be2a2ac1	5436
emilmont	80:8e73be2a2ac1	5437	/* Bits 3..0 : Current radio state. */
emilmont	80:8e73be2a2ac1	5438	#define RADIO_STATE_STATE_Pos (0UL) /!< Position of STATE field. /
emilmont	80:8e73be2a2ac1	5439	#define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /!< Bit mask of STATE field. /
emilmont	80:8e73be2a2ac1	5440	#define RADIO_STATE_STATE_Disabled (0x00UL) /!< Radio is in the Disabled state. /
emilmont	80:8e73be2a2ac1	5441	#define RADIO_STATE_STATE_RxRu (0x01UL) /!< Radio is in the Rx Ramp Up state. /
emilmont	80:8e73be2a2ac1	5442	#define RADIO_STATE_STATE_RxIdle (0x02UL) /!< Radio is in the Rx Idle state. /
emilmont	80:8e73be2a2ac1	5443	#define RADIO_STATE_STATE_Rx (0x03UL) /!< Radio is in the Rx state. /
emilmont	80:8e73be2a2ac1	5444	#define RADIO_STATE_STATE_RxDisable (0x04UL) /!< Radio is in the Rx Disable state. /
emilmont	80:8e73be2a2ac1	5445	#define RADIO_STATE_STATE_TxRu (0x09UL) /!< Radio is in the Tx Ramp Up state. /
emilmont	80:8e73be2a2ac1	5446	#define RADIO_STATE_STATE_TxIdle (0x0AUL) /!< Radio is in the Tx Idle state. /
emilmont	80:8e73be2a2ac1	5447	#define RADIO_STATE_STATE_Tx (0x0BUL) /!< Radio is in the Tx state. /
emilmont	80:8e73be2a2ac1	5448	#define RADIO_STATE_STATE_TxDisable (0x0CUL) /!< Radio is in the Tx Disable state. /
emilmont	80:8e73be2a2ac1	5449
emilmont	80:8e73be2a2ac1	5450	/* Register: RADIO_DATAWHITEIV */
emilmont	80:8e73be2a2ac1	5451	/* Description: Data whitening initial value. */
emilmont	80:8e73be2a2ac1	5452
Kojto	97:433970e64889	5453	/* Bits 6..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
emilmont	80:8e73be2a2ac1	5454	#define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /!< Position of DATAWHITEIV field. /
Kojto	97:433970e64889	5455	#define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x7FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /!< Bit mask of DATAWHITEIV field. /
emilmont	80:8e73be2a2ac1	5456
emilmont	80:8e73be2a2ac1	5457	/* Register: RADIO_DAP */
emilmont	80:8e73be2a2ac1	5458	/* Description: Device address prefix. */
emilmont	80:8e73be2a2ac1	5459
emilmont	80:8e73be2a2ac1	5460	/* Bits 15..0 : Device address prefix. */
emilmont	80:8e73be2a2ac1	5461	#define RADIO_DAP_DAP_Pos (0UL) /!< Position of DAP field. /
emilmont	80:8e73be2a2ac1	5462	#define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /!< Bit mask of DAP field. /
emilmont	80:8e73be2a2ac1	5463
emilmont	80:8e73be2a2ac1	5464	/* Register: RADIO_DACNF */
emilmont	80:8e73be2a2ac1	5465	/* Description: Device address match configuration. */
emilmont	80:8e73be2a2ac1	5466
emilmont	80:8e73be2a2ac1	5467	/* Bit 15 : TxAdd for device address 7. */
emilmont	80:8e73be2a2ac1	5468	#define RADIO_DACNF_TXADD7_Pos (15UL) /!< Position of TXADD7 field. /
emilmont	80:8e73be2a2ac1	5469	#define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /!< Bit mask of TXADD7 field. /
emilmont	80:8e73be2a2ac1	5470
emilmont	80:8e73be2a2ac1	5471	/* Bit 14 : TxAdd for device address 6. */
emilmont	80:8e73be2a2ac1	5472	#define RADIO_DACNF_TXADD6_Pos (14UL) /!< Position of TXADD6 field. /
emilmont	80:8e73be2a2ac1	5473	#define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /!< Bit mask of TXADD6 field. /
emilmont	80:8e73be2a2ac1	5474
emilmont	80:8e73be2a2ac1	5475	/* Bit 13 : TxAdd for device address 5. */
emilmont	80:8e73be2a2ac1	5476	#define RADIO_DACNF_TXADD5_Pos (13UL) /!< Position of TXADD5 field. /
emilmont	80:8e73be2a2ac1	5477	#define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /!< Bit mask of TXADD5 field. /
emilmont	80:8e73be2a2ac1	5478
emilmont	80:8e73be2a2ac1	5479	/* Bit 12 : TxAdd for device address 4. */
emilmont	80:8e73be2a2ac1	5480	#define RADIO_DACNF_TXADD4_Pos (12UL) /!< Position of TXADD4 field. /
emilmont	80:8e73be2a2ac1	5481	#define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /!< Bit mask of TXADD4 field. /
emilmont	80:8e73be2a2ac1	5482
emilmont	80:8e73be2a2ac1	5483	/* Bit 11 : TxAdd for device address 3. */
emilmont	80:8e73be2a2ac1	5484	#define RADIO_DACNF_TXADD3_Pos (11UL) /!< Position of TXADD3 field. /
emilmont	80:8e73be2a2ac1	5485	#define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /!< Bit mask of TXADD3 field. /
emilmont	80:8e73be2a2ac1	5486
emilmont	80:8e73be2a2ac1	5487	/* Bit 10 : TxAdd for device address 2. */
emilmont	80:8e73be2a2ac1	5488	#define RADIO_DACNF_TXADD2_Pos (10UL) /!< Position of TXADD2 field. /
emilmont	80:8e73be2a2ac1	5489	#define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /!< Bit mask of TXADD2 field. /
emilmont	80:8e73be2a2ac1	5490
emilmont	80:8e73be2a2ac1	5491	/* Bit 9 : TxAdd for device address 1. */
emilmont	80:8e73be2a2ac1	5492	#define RADIO_DACNF_TXADD1_Pos (9UL) /!< Position of TXADD1 field. /
emilmont	80:8e73be2a2ac1	5493	#define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /!< Bit mask of TXADD1 field. /
emilmont	80:8e73be2a2ac1	5494
emilmont	80:8e73be2a2ac1	5495	/* Bit 8 : TxAdd for device address 0. */
emilmont	80:8e73be2a2ac1	5496	#define RADIO_DACNF_TXADD0_Pos (8UL) /!< Position of TXADD0 field. /
emilmont	80:8e73be2a2ac1	5497	#define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /!< Bit mask of TXADD0 field. /
emilmont	80:8e73be2a2ac1	5498
emilmont	80:8e73be2a2ac1	5499	/* Bit 7 : Enable or disable device address matching using device address 7. */
emilmont	80:8e73be2a2ac1	5500	#define RADIO_DACNF_ENA7_Pos (7UL) /!< Position of ENA7 field. /
emilmont	80:8e73be2a2ac1	5501	#define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /!< Bit mask of ENA7 field. /
emilmont	80:8e73be2a2ac1	5502	#define RADIO_DACNF_ENA7_Disabled (0UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	5503	#define RADIO_DACNF_ENA7_Enabled (1UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	5504
emilmont	80:8e73be2a2ac1	5505	/* Bit 6 : Enable or disable device address matching using device address 6. */
emilmont	80:8e73be2a2ac1	5506	#define RADIO_DACNF_ENA6_Pos (6UL) /!< Position of ENA6 field. /
emilmont	80:8e73be2a2ac1	5507	#define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /!< Bit mask of ENA6 field. /
emilmont	80:8e73be2a2ac1	5508	#define RADIO_DACNF_ENA6_Disabled (0UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	5509	#define RADIO_DACNF_ENA6_Enabled (1UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	5510
emilmont	80:8e73be2a2ac1	5511	/* Bit 5 : Enable or disable device address matching using device address 5. */
emilmont	80:8e73be2a2ac1	5512	#define RADIO_DACNF_ENA5_Pos (5UL) /!< Position of ENA5 field. /
emilmont	80:8e73be2a2ac1	5513	#define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /!< Bit mask of ENA5 field. /
emilmont	80:8e73be2a2ac1	5514	#define RADIO_DACNF_ENA5_Disabled (0UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	5515	#define RADIO_DACNF_ENA5_Enabled (1UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	5516
emilmont	80:8e73be2a2ac1	5517	/* Bit 4 : Enable or disable device address matching using device address 4. */
emilmont	80:8e73be2a2ac1	5518	#define RADIO_DACNF_ENA4_Pos (4UL) /!< Position of ENA4 field. /
emilmont	80:8e73be2a2ac1	5519	#define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /!< Bit mask of ENA4 field. /
emilmont	80:8e73be2a2ac1	5520	#define RADIO_DACNF_ENA4_Disabled (0UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	5521	#define RADIO_DACNF_ENA4_Enabled (1UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	5522
emilmont	80:8e73be2a2ac1	5523	/* Bit 3 : Enable or disable device address matching using device address 3. */
emilmont	80:8e73be2a2ac1	5524	#define RADIO_DACNF_ENA3_Pos (3UL) /!< Position of ENA3 field. /
emilmont	80:8e73be2a2ac1	5525	#define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /!< Bit mask of ENA3 field. /
emilmont	80:8e73be2a2ac1	5526	#define RADIO_DACNF_ENA3_Disabled (0UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	5527	#define RADIO_DACNF_ENA3_Enabled (1UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	5528
emilmont	80:8e73be2a2ac1	5529	/* Bit 2 : Enable or disable device address matching using device address 2. */
emilmont	80:8e73be2a2ac1	5530	#define RADIO_DACNF_ENA2_Pos (2UL) /!< Position of ENA2 field. /
emilmont	80:8e73be2a2ac1	5531	#define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /!< Bit mask of ENA2 field. /
emilmont	80:8e73be2a2ac1	5532	#define RADIO_DACNF_ENA2_Disabled (0UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	5533	#define RADIO_DACNF_ENA2_Enabled (1UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	5534
emilmont	80:8e73be2a2ac1	5535	/* Bit 1 : Enable or disable device address matching using device address 1. */
emilmont	80:8e73be2a2ac1	5536	#define RADIO_DACNF_ENA1_Pos (1UL) /!< Position of ENA1 field. /
emilmont	80:8e73be2a2ac1	5537	#define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /!< Bit mask of ENA1 field. /
emilmont	80:8e73be2a2ac1	5538	#define RADIO_DACNF_ENA1_Disabled (0UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	5539	#define RADIO_DACNF_ENA1_Enabled (1UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	5540
emilmont	80:8e73be2a2ac1	5541	/* Bit 0 : Enable or disable device address matching using device address 0. */
emilmont	80:8e73be2a2ac1	5542	#define RADIO_DACNF_ENA0_Pos (0UL) /!< Position of ENA0 field. /
emilmont	80:8e73be2a2ac1	5543	#define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /!< Bit mask of ENA0 field. /
emilmont	80:8e73be2a2ac1	5544	#define RADIO_DACNF_ENA0_Disabled (0UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	5545	#define RADIO_DACNF_ENA0_Enabled (1UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	5546
emilmont	80:8e73be2a2ac1	5547	/* Register: RADIO_OVERRIDE0 */
emilmont	80:8e73be2a2ac1	5548	/* Description: Trim value override register 0. */
emilmont	80:8e73be2a2ac1	5549
Kojto	97:433970e64889	5550	/* Bits 31..0 : Trim value override 0. */
emilmont	80:8e73be2a2ac1	5551	#define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /!< Position of OVERRIDE0 field. /
emilmont	80:8e73be2a2ac1	5552	#define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /!< Bit mask of OVERRIDE0 field. /
emilmont	80:8e73be2a2ac1	5553
emilmont	80:8e73be2a2ac1	5554	/* Register: RADIO_OVERRIDE1 */
emilmont	80:8e73be2a2ac1	5555	/* Description: Trim value override register 1. */
emilmont	80:8e73be2a2ac1	5556
Kojto	97:433970e64889	5557	/* Bits 31..0 : Trim value override 1. */
emilmont	80:8e73be2a2ac1	5558	#define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /!< Position of OVERRIDE1 field. /
emilmont	80:8e73be2a2ac1	5559	#define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /!< Bit mask of OVERRIDE1 field. /
emilmont	80:8e73be2a2ac1	5560
emilmont	80:8e73be2a2ac1	5561	/* Register: RADIO_OVERRIDE2 */
emilmont	80:8e73be2a2ac1	5562	/* Description: Trim value override register 2. */
emilmont	80:8e73be2a2ac1	5563
Kojto	97:433970e64889	5564	/* Bits 31..0 : Trim value override 2. */
emilmont	80:8e73be2a2ac1	5565	#define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /!< Position of OVERRIDE2 field. /
emilmont	80:8e73be2a2ac1	5566	#define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /!< Bit mask of OVERRIDE2 field. /
emilmont	80:8e73be2a2ac1	5567
emilmont	80:8e73be2a2ac1	5568	/* Register: RADIO_OVERRIDE3 */
emilmont	80:8e73be2a2ac1	5569	/* Description: Trim value override register 3. */
emilmont	80:8e73be2a2ac1	5570
Kojto	97:433970e64889	5571	/* Bits 31..0 : Trim value override 3. */
emilmont	80:8e73be2a2ac1	5572	#define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /!< Position of OVERRIDE3 field. /
emilmont	80:8e73be2a2ac1	5573	#define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /!< Bit mask of OVERRIDE3 field. /
emilmont	80:8e73be2a2ac1	5574
emilmont	80:8e73be2a2ac1	5575	/* Register: RADIO_OVERRIDE4 */
emilmont	80:8e73be2a2ac1	5576	/* Description: Trim value override register 4. */
emilmont	80:8e73be2a2ac1	5577
emilmont	80:8e73be2a2ac1	5578	/* Bit 31 : Enable or disable override of default trim values. */
emilmont	80:8e73be2a2ac1	5579	#define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	5580	#define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	5581	#define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /!< Override trim values disabled. /
emilmont	80:8e73be2a2ac1	5582	#define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /!< Override trim values enabled. /
emilmont	80:8e73be2a2ac1	5583
Kojto	97:433970e64889	5584	/* Bits 27..0 : Trim value override 4. */
emilmont	80:8e73be2a2ac1	5585	#define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /!< Position of OVERRIDE4 field. /
emilmont	80:8e73be2a2ac1	5586	#define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /!< Bit mask of OVERRIDE4 field. /
emilmont	80:8e73be2a2ac1	5587
emilmont	80:8e73be2a2ac1	5588	/* Register: RADIO_POWER */
emilmont	80:8e73be2a2ac1	5589	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	5590
emilmont	80:8e73be2a2ac1	5591	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	5592	#define RADIO_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	5593	#define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	5594	#define RADIO_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	5595	#define RADIO_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	5596
emilmont	80:8e73be2a2ac1	5597
emilmont	80:8e73be2a2ac1	5598	/* Peripheral: RNG */
emilmont	80:8e73be2a2ac1	5599	/* Description: Random Number Generator. */
emilmont	80:8e73be2a2ac1	5600
emilmont	80:8e73be2a2ac1	5601	/* Register: RNG_SHORTS */
Kojto	97:433970e64889	5602	/* Description: Shortcuts for the RNG. */
Kojto	97:433970e64889	5603
Kojto	97:433970e64889	5604	/* Bit 0 : Shortcut between VALRDY event and STOP task. */
emilmont	80:8e73be2a2ac1	5605	#define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /!< Position of VALRDY_STOP field. /
emilmont	80:8e73be2a2ac1	5606	#define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /!< Bit mask of VALRDY_STOP field. /
emilmont	80:8e73be2a2ac1	5607	#define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	5608	#define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	5609
emilmont	80:8e73be2a2ac1	5610	/* Register: RNG_INTENSET */
emilmont	80:8e73be2a2ac1	5611	/* Description: Interrupt enable set register */
emilmont	80:8e73be2a2ac1	5612
emilmont	80:8e73be2a2ac1	5613	/* Bit 0 : Enable interrupt on VALRDY event. */
emilmont	80:8e73be2a2ac1	5614	#define RNG_INTENSET_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
emilmont	80:8e73be2a2ac1	5615	#define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /!< Bit mask of VALRDY field. /
emilmont	80:8e73be2a2ac1	5616	#define RNG_INTENSET_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5617	#define RNG_INTENSET_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5618	#define RNG_INTENSET_VALRDY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5619
emilmont	80:8e73be2a2ac1	5620	/* Register: RNG_INTENCLR */
emilmont	80:8e73be2a2ac1	5621	/* Description: Interrupt enable clear register */
emilmont	80:8e73be2a2ac1	5622
emilmont	80:8e73be2a2ac1	5623	/* Bit 0 : Disable interrupt on VALRDY event. */
emilmont	80:8e73be2a2ac1	5624	#define RNG_INTENCLR_VALRDY_Pos (0UL) /!< Position of VALRDY field. /
emilmont	80:8e73be2a2ac1	5625	#define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /!< Bit mask of VALRDY field. /
emilmont	80:8e73be2a2ac1	5626	#define RNG_INTENCLR_VALRDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5627	#define RNG_INTENCLR_VALRDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5628	#define RNG_INTENCLR_VALRDY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5629
emilmont	80:8e73be2a2ac1	5630	/* Register: RNG_CONFIG */
emilmont	80:8e73be2a2ac1	5631	/* Description: Configuration register. */
emilmont	80:8e73be2a2ac1	5632
emilmont	80:8e73be2a2ac1	5633	/* Bit 0 : Digital error correction enable. */
emilmont	80:8e73be2a2ac1	5634	#define RNG_CONFIG_DERCEN_Pos (0UL) /!< Position of DERCEN field. /
emilmont	80:8e73be2a2ac1	5635	#define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /!< Bit mask of DERCEN field. /
emilmont	80:8e73be2a2ac1	5636	#define RNG_CONFIG_DERCEN_Disabled (0UL) /!< Digital error correction disabled. /
emilmont	80:8e73be2a2ac1	5637	#define RNG_CONFIG_DERCEN_Enabled (1UL) /!< Digital error correction enabled. /
emilmont	80:8e73be2a2ac1	5638
emilmont	80:8e73be2a2ac1	5639	/* Register: RNG_VALUE */
emilmont	80:8e73be2a2ac1	5640	/* Description: RNG random number. */
emilmont	80:8e73be2a2ac1	5641
emilmont	80:8e73be2a2ac1	5642	/* Bits 7..0 : Generated random number. */
emilmont	80:8e73be2a2ac1	5643	#define RNG_VALUE_VALUE_Pos (0UL) /!< Position of VALUE field. /
emilmont	80:8e73be2a2ac1	5644	#define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /!< Bit mask of VALUE field. /
emilmont	80:8e73be2a2ac1	5645
emilmont	80:8e73be2a2ac1	5646	/* Register: RNG_POWER */
emilmont	80:8e73be2a2ac1	5647	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	5648
emilmont	80:8e73be2a2ac1	5649	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	5650	#define RNG_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	5651	#define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	5652	#define RNG_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	5653	#define RNG_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	5654
emilmont	80:8e73be2a2ac1	5655
emilmont	80:8e73be2a2ac1	5656	/* Peripheral: RTC */
emilmont	80:8e73be2a2ac1	5657	/* Description: Real time counter 0. */
emilmont	80:8e73be2a2ac1	5658
emilmont	80:8e73be2a2ac1	5659	/* Register: RTC_INTENSET */
emilmont	80:8e73be2a2ac1	5660	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	5661
emilmont	80:8e73be2a2ac1	5662	/* Bit 19 : Enable interrupt on COMPARE[3] event. */
emilmont	80:8e73be2a2ac1	5663	#define RTC_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5664	#define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5665	#define RTC_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5666	#define RTC_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5667	#define RTC_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5668
emilmont	80:8e73be2a2ac1	5669	/* Bit 18 : Enable interrupt on COMPARE[2] event. */
emilmont	80:8e73be2a2ac1	5670	#define RTC_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5671	#define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5672	#define RTC_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5673	#define RTC_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5674	#define RTC_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5675
emilmont	80:8e73be2a2ac1	5676	/* Bit 17 : Enable interrupt on COMPARE[1] event. */
emilmont	80:8e73be2a2ac1	5677	#define RTC_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5678	#define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5679	#define RTC_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5680	#define RTC_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5681	#define RTC_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5682
emilmont	80:8e73be2a2ac1	5683	/* Bit 16 : Enable interrupt on COMPARE[0] event. */
emilmont	80:8e73be2a2ac1	5684	#define RTC_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5685	#define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5686	#define RTC_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5687	#define RTC_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5688	#define RTC_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5689
emilmont	80:8e73be2a2ac1	5690	/* Bit 1 : Enable interrupt on OVRFLW event. */
emilmont	80:8e73be2a2ac1	5691	#define RTC_INTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5692	#define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5693	#define RTC_INTENSET_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5694	#define RTC_INTENSET_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5695	#define RTC_INTENSET_OVRFLW_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5696
emilmont	80:8e73be2a2ac1	5697	/* Bit 0 : Enable interrupt on TICK event. */
emilmont	80:8e73be2a2ac1	5698	#define RTC_INTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
emilmont	80:8e73be2a2ac1	5699	#define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /!< Bit mask of TICK field. /
emilmont	80:8e73be2a2ac1	5700	#define RTC_INTENSET_TICK_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5701	#define RTC_INTENSET_TICK_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5702	#define RTC_INTENSET_TICK_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5703
emilmont	80:8e73be2a2ac1	5704	/* Register: RTC_INTENCLR */
emilmont	80:8e73be2a2ac1	5705	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	5706
emilmont	80:8e73be2a2ac1	5707	/* Bit 19 : Disable interrupt on COMPARE[3] event. */
emilmont	80:8e73be2a2ac1	5708	#define RTC_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5709	#define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5710	#define RTC_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5711	#define RTC_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5712	#define RTC_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5713
emilmont	80:8e73be2a2ac1	5714	/* Bit 18 : Disable interrupt on COMPARE[2] event. */
emilmont	80:8e73be2a2ac1	5715	#define RTC_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5716	#define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5717	#define RTC_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5718	#define RTC_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5719	#define RTC_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5720
emilmont	80:8e73be2a2ac1	5721	/* Bit 17 : Disable interrupt on COMPARE[1] event. */
emilmont	80:8e73be2a2ac1	5722	#define RTC_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5723	#define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5724	#define RTC_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5725	#define RTC_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5726	#define RTC_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5727
emilmont	80:8e73be2a2ac1	5728	/* Bit 16 : Disable interrupt on COMPARE[0] event. */
emilmont	80:8e73be2a2ac1	5729	#define RTC_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5730	#define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5731	#define RTC_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5732	#define RTC_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5733	#define RTC_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5734
emilmont	80:8e73be2a2ac1	5735	/* Bit 1 : Disable interrupt on OVRFLW event. */
emilmont	80:8e73be2a2ac1	5736	#define RTC_INTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5737	#define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5738	#define RTC_INTENCLR_OVRFLW_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5739	#define RTC_INTENCLR_OVRFLW_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5740	#define RTC_INTENCLR_OVRFLW_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5741
emilmont	80:8e73be2a2ac1	5742	/* Bit 0 : Disable interrupt on TICK event. */
emilmont	80:8e73be2a2ac1	5743	#define RTC_INTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
emilmont	80:8e73be2a2ac1	5744	#define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
emilmont	80:8e73be2a2ac1	5745	#define RTC_INTENCLR_TICK_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5746	#define RTC_INTENCLR_TICK_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5747	#define RTC_INTENCLR_TICK_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5748
emilmont	80:8e73be2a2ac1	5749	/* Register: RTC_EVTEN */
emilmont	80:8e73be2a2ac1	5750	/* Description: Configures event enable routing to PPI for each RTC event. */
emilmont	80:8e73be2a2ac1	5751
emilmont	80:8e73be2a2ac1	5752	/* Bit 19 : COMPARE[3] event enable. */
emilmont	80:8e73be2a2ac1	5753	#define RTC_EVTEN_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5754	#define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5755	#define RTC_EVTEN_COMPARE3_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5756	#define RTC_EVTEN_COMPARE3_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5757
emilmont	80:8e73be2a2ac1	5758	/* Bit 18 : COMPARE[2] event enable. */
emilmont	80:8e73be2a2ac1	5759	#define RTC_EVTEN_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5760	#define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5761	#define RTC_EVTEN_COMPARE2_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5762	#define RTC_EVTEN_COMPARE2_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5763
emilmont	80:8e73be2a2ac1	5764	/* Bit 17 : COMPARE[1] event enable. */
emilmont	80:8e73be2a2ac1	5765	#define RTC_EVTEN_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5766	#define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5767	#define RTC_EVTEN_COMPARE1_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5768	#define RTC_EVTEN_COMPARE1_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5769
emilmont	80:8e73be2a2ac1	5770	/* Bit 16 : COMPARE[0] event enable. */
emilmont	80:8e73be2a2ac1	5771	#define RTC_EVTEN_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5772	#define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5773	#define RTC_EVTEN_COMPARE0_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5774	#define RTC_EVTEN_COMPARE0_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5775
emilmont	80:8e73be2a2ac1	5776	/* Bit 1 : OVRFLW event enable. */
emilmont	80:8e73be2a2ac1	5777	#define RTC_EVTEN_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5778	#define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5779	#define RTC_EVTEN_OVRFLW_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5780	#define RTC_EVTEN_OVRFLW_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5781
emilmont	80:8e73be2a2ac1	5782	/* Bit 0 : TICK event enable. */
emilmont	80:8e73be2a2ac1	5783	#define RTC_EVTEN_TICK_Pos (0UL) /!< Position of TICK field. /
emilmont	80:8e73be2a2ac1	5784	#define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /!< Bit mask of TICK field. /
emilmont	80:8e73be2a2ac1	5785	#define RTC_EVTEN_TICK_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5786	#define RTC_EVTEN_TICK_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5787
emilmont	80:8e73be2a2ac1	5788	/* Register: RTC_EVTENSET */
emilmont	80:8e73be2a2ac1	5789	/* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
emilmont	80:8e73be2a2ac1	5790
emilmont	80:8e73be2a2ac1	5791	/* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
emilmont	80:8e73be2a2ac1	5792	#define RTC_EVTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5793	#define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5794	#define RTC_EVTENSET_COMPARE3_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5795	#define RTC_EVTENSET_COMPARE3_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5796	#define RTC_EVTENSET_COMPARE3_Set (1UL) /!< Enable event on write. /
emilmont	80:8e73be2a2ac1	5797
emilmont	80:8e73be2a2ac1	5798	/* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
emilmont	80:8e73be2a2ac1	5799	#define RTC_EVTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5800	#define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5801	#define RTC_EVTENSET_COMPARE2_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5802	#define RTC_EVTENSET_COMPARE2_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5803	#define RTC_EVTENSET_COMPARE2_Set (1UL) /!< Enable event on write. /
emilmont	80:8e73be2a2ac1	5804
emilmont	80:8e73be2a2ac1	5805	/* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
emilmont	80:8e73be2a2ac1	5806	#define RTC_EVTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5807	#define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5808	#define RTC_EVTENSET_COMPARE1_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5809	#define RTC_EVTENSET_COMPARE1_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5810	#define RTC_EVTENSET_COMPARE1_Set (1UL) /!< Enable event on write. /
emilmont	80:8e73be2a2ac1	5811
emilmont	80:8e73be2a2ac1	5812	/* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
emilmont	80:8e73be2a2ac1	5813	#define RTC_EVTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5814	#define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5815	#define RTC_EVTENSET_COMPARE0_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5816	#define RTC_EVTENSET_COMPARE0_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5817	#define RTC_EVTENSET_COMPARE0_Set (1UL) /!< Enable event on write. /
emilmont	80:8e73be2a2ac1	5818
emilmont	80:8e73be2a2ac1	5819	/* Bit 1 : Enable routing to PPI of OVRFLW event. */
emilmont	80:8e73be2a2ac1	5820	#define RTC_EVTENSET_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5821	#define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5822	#define RTC_EVTENSET_OVRFLW_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5823	#define RTC_EVTENSET_OVRFLW_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5824	#define RTC_EVTENSET_OVRFLW_Set (1UL) /!< Enable event on write. /
emilmont	80:8e73be2a2ac1	5825
emilmont	80:8e73be2a2ac1	5826	/* Bit 0 : Enable routing to PPI of TICK event. */
emilmont	80:8e73be2a2ac1	5827	#define RTC_EVTENSET_TICK_Pos (0UL) /!< Position of TICK field. /
emilmont	80:8e73be2a2ac1	5828	#define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /!< Bit mask of TICK field. /
emilmont	80:8e73be2a2ac1	5829	#define RTC_EVTENSET_TICK_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5830	#define RTC_EVTENSET_TICK_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5831	#define RTC_EVTENSET_TICK_Set (1UL) /!< Enable event on write. /
emilmont	80:8e73be2a2ac1	5832
emilmont	80:8e73be2a2ac1	5833	/* Register: RTC_EVTENCLR */
emilmont	80:8e73be2a2ac1	5834	/* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
emilmont	80:8e73be2a2ac1	5835
emilmont	80:8e73be2a2ac1	5836	/* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
emilmont	80:8e73be2a2ac1	5837	#define RTC_EVTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5838	#define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	5839	#define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5840	#define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5841	#define RTC_EVTENCLR_COMPARE3_Clear (1UL) /!< Disable event on write. /
emilmont	80:8e73be2a2ac1	5842
emilmont	80:8e73be2a2ac1	5843	/* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
emilmont	80:8e73be2a2ac1	5844	#define RTC_EVTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5845	#define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	5846	#define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5847	#define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5848	#define RTC_EVTENCLR_COMPARE2_Clear (1UL) /!< Disable event on write. /
emilmont	80:8e73be2a2ac1	5849
emilmont	80:8e73be2a2ac1	5850	/* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
emilmont	80:8e73be2a2ac1	5851	#define RTC_EVTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5852	#define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	5853	#define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5854	#define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5855	#define RTC_EVTENCLR_COMPARE1_Clear (1UL) /!< Disable event on write. /
emilmont	80:8e73be2a2ac1	5856
emilmont	80:8e73be2a2ac1	5857	/* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
emilmont	80:8e73be2a2ac1	5858	#define RTC_EVTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5859	#define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	5860	#define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5861	#define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5862	#define RTC_EVTENCLR_COMPARE0_Clear (1UL) /!< Disable event on write. /
emilmont	80:8e73be2a2ac1	5863
emilmont	80:8e73be2a2ac1	5864	/* Bit 1 : Disable routing to PPI of OVRFLW event. */
emilmont	80:8e73be2a2ac1	5865	#define RTC_EVTENCLR_OVRFLW_Pos (1UL) /!< Position of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5866	#define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /!< Bit mask of OVRFLW field. /
emilmont	80:8e73be2a2ac1	5867	#define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5868	#define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5869	#define RTC_EVTENCLR_OVRFLW_Clear (1UL) /!< Disable event on write. /
emilmont	80:8e73be2a2ac1	5870
emilmont	80:8e73be2a2ac1	5871	/* Bit 0 : Disable routing to PPI of TICK event. */
emilmont	80:8e73be2a2ac1	5872	#define RTC_EVTENCLR_TICK_Pos (0UL) /!< Position of TICK field. /
emilmont	80:8e73be2a2ac1	5873	#define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /!< Bit mask of TICK field. /
emilmont	80:8e73be2a2ac1	5874	#define RTC_EVTENCLR_TICK_Disabled (0UL) /!< Event disabled. /
emilmont	80:8e73be2a2ac1	5875	#define RTC_EVTENCLR_TICK_Enabled (1UL) /!< Event enabled. /
emilmont	80:8e73be2a2ac1	5876	#define RTC_EVTENCLR_TICK_Clear (1UL) /!< Disable event on write. /
emilmont	80:8e73be2a2ac1	5877
emilmont	80:8e73be2a2ac1	5878	/* Register: RTC_COUNTER */
emilmont	80:8e73be2a2ac1	5879	/* Description: Current COUNTER value. */
emilmont	80:8e73be2a2ac1	5880
emilmont	80:8e73be2a2ac1	5881	/* Bits 23..0 : Counter value. */
emilmont	80:8e73be2a2ac1	5882	#define RTC_COUNTER_COUNTER_Pos (0UL) /!< Position of COUNTER field. /
emilmont	80:8e73be2a2ac1	5883	#define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /!< Bit mask of COUNTER field. /
emilmont	80:8e73be2a2ac1	5884
emilmont	80:8e73be2a2ac1	5885	/* Register: RTC_PRESCALER */
emilmont	80:8e73be2a2ac1	5886	/* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
emilmont	80:8e73be2a2ac1	5887
emilmont	80:8e73be2a2ac1	5888	/* Bits 11..0 : RTC PRESCALER value. */
emilmont	80:8e73be2a2ac1	5889	#define RTC_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
emilmont	80:8e73be2a2ac1	5890	#define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
emilmont	80:8e73be2a2ac1	5891
emilmont	80:8e73be2a2ac1	5892	/* Register: RTC_CC */
emilmont	80:8e73be2a2ac1	5893	/* Description: Capture/compare registers. */
emilmont	80:8e73be2a2ac1	5894
emilmont	80:8e73be2a2ac1	5895	/* Bits 23..0 : Compare value. */
emilmont	80:8e73be2a2ac1	5896	#define RTC_CC_COMPARE_Pos (0UL) /!< Position of COMPARE field. /
emilmont	80:8e73be2a2ac1	5897	#define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /!< Bit mask of COMPARE field. /
emilmont	80:8e73be2a2ac1	5898
emilmont	80:8e73be2a2ac1	5899	/* Register: RTC_POWER */
emilmont	80:8e73be2a2ac1	5900	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	5901
emilmont	80:8e73be2a2ac1	5902	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	5903	#define RTC_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	5904	#define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	5905	#define RTC_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	5906	#define RTC_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	5907
emilmont	80:8e73be2a2ac1	5908
emilmont	80:8e73be2a2ac1	5909	/* Peripheral: SPI */
emilmont	80:8e73be2a2ac1	5910	/* Description: SPI master 0. */
emilmont	80:8e73be2a2ac1	5911
emilmont	80:8e73be2a2ac1	5912	/* Register: SPI_INTENSET */
emilmont	80:8e73be2a2ac1	5913	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	5914
emilmont	80:8e73be2a2ac1	5915	/* Bit 2 : Enable interrupt on READY event. */
emilmont	80:8e73be2a2ac1	5916	#define SPI_INTENSET_READY_Pos (2UL) /!< Position of READY field. /
emilmont	80:8e73be2a2ac1	5917	#define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /!< Bit mask of READY field. /
emilmont	80:8e73be2a2ac1	5918	#define SPI_INTENSET_READY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5919	#define SPI_INTENSET_READY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5920	#define SPI_INTENSET_READY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	5921
emilmont	80:8e73be2a2ac1	5922	/* Register: SPI_INTENCLR */
emilmont	80:8e73be2a2ac1	5923	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	5924
emilmont	80:8e73be2a2ac1	5925	/* Bit 2 : Disable interrupt on READY event. */
emilmont	80:8e73be2a2ac1	5926	#define SPI_INTENCLR_READY_Pos (2UL) /!< Position of READY field. /
emilmont	80:8e73be2a2ac1	5927	#define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /!< Bit mask of READY field. /
emilmont	80:8e73be2a2ac1	5928	#define SPI_INTENCLR_READY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	5929	#define SPI_INTENCLR_READY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	5930	#define SPI_INTENCLR_READY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	5931
emilmont	80:8e73be2a2ac1	5932	/* Register: SPI_ENABLE */
emilmont	80:8e73be2a2ac1	5933	/* Description: Enable SPI. */
emilmont	80:8e73be2a2ac1	5934
emilmont	80:8e73be2a2ac1	5935	/* Bits 2..0 : Enable or disable SPI. */
emilmont	80:8e73be2a2ac1	5936	#define SPI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	5937	#define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	5938	#define SPI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPI. /
emilmont	80:8e73be2a2ac1	5939	#define SPI_ENABLE_ENABLE_Enabled (0x01UL) /!< Enable SPI. /
emilmont	80:8e73be2a2ac1	5940
emilmont	80:8e73be2a2ac1	5941	/* Register: SPI_RXD */
emilmont	80:8e73be2a2ac1	5942	/* Description: RX data. */
emilmont	80:8e73be2a2ac1	5943
emilmont	80:8e73be2a2ac1	5944	/* Bits 7..0 : RX data from last transfer. */
emilmont	80:8e73be2a2ac1	5945	#define SPI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
emilmont	80:8e73be2a2ac1	5946	#define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
emilmont	80:8e73be2a2ac1	5947
emilmont	80:8e73be2a2ac1	5948	/* Register: SPI_TXD */
emilmont	80:8e73be2a2ac1	5949	/* Description: TX data. */
emilmont	80:8e73be2a2ac1	5950
emilmont	80:8e73be2a2ac1	5951	/* Bits 7..0 : TX data for next transfer. */
emilmont	80:8e73be2a2ac1	5952	#define SPI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
emilmont	80:8e73be2a2ac1	5953	#define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
emilmont	80:8e73be2a2ac1	5954
emilmont	80:8e73be2a2ac1	5955	/* Register: SPI_FREQUENCY */
emilmont	80:8e73be2a2ac1	5956	/* Description: SPI frequency */
emilmont	80:8e73be2a2ac1	5957
emilmont	80:8e73be2a2ac1	5958	/* Bits 31..0 : SPI data rate. */
emilmont	80:8e73be2a2ac1	5959	#define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
emilmont	80:8e73be2a2ac1	5960	#define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
emilmont	80:8e73be2a2ac1	5961	#define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125kbps. /
emilmont	80:8e73be2a2ac1	5962	#define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250kbps. /
emilmont	80:8e73be2a2ac1	5963	#define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500kbps. /
emilmont	80:8e73be2a2ac1	5964	#define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1Mbps. /
emilmont	80:8e73be2a2ac1	5965	#define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2Mbps. /
emilmont	80:8e73be2a2ac1	5966	#define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4Mbps. /
emilmont	80:8e73be2a2ac1	5967	#define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8Mbps. /
emilmont	80:8e73be2a2ac1	5968
emilmont	80:8e73be2a2ac1	5969	/* Register: SPI_CONFIG */
emilmont	80:8e73be2a2ac1	5970	/* Description: Configuration register. */
emilmont	80:8e73be2a2ac1	5971
emilmont	80:8e73be2a2ac1	5972	/* Bit 2 : Serial clock (SCK) polarity. */
emilmont	80:8e73be2a2ac1	5973	#define SPI_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
emilmont	80:8e73be2a2ac1	5974	#define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
emilmont	80:8e73be2a2ac1	5975	#define SPI_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
emilmont	80:8e73be2a2ac1	5976	#define SPI_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
emilmont	80:8e73be2a2ac1	5977
emilmont	80:8e73be2a2ac1	5978	/* Bit 1 : Serial clock (SCK) phase. */
emilmont	80:8e73be2a2ac1	5979	#define SPI_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
emilmont	80:8e73be2a2ac1	5980	#define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
emilmont	80:8e73be2a2ac1	5981	#define SPI_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
emilmont	80:8e73be2a2ac1	5982	#define SPI_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
emilmont	80:8e73be2a2ac1	5983
emilmont	80:8e73be2a2ac1	5984	/* Bit 0 : Bit order. */
emilmont	80:8e73be2a2ac1	5985	#define SPI_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
emilmont	80:8e73be2a2ac1	5986	#define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
emilmont	80:8e73be2a2ac1	5987	#define SPI_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
emilmont	80:8e73be2a2ac1	5988	#define SPI_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
emilmont	80:8e73be2a2ac1	5989
emilmont	80:8e73be2a2ac1	5990	/* Register: SPI_POWER */
emilmont	80:8e73be2a2ac1	5991	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	5992
emilmont	80:8e73be2a2ac1	5993	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	5994	#define SPI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	5995	#define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	5996	#define SPI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	5997	#define SPI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	5998
emilmont	80:8e73be2a2ac1	5999
Kojto	97:433970e64889	6000	/* Peripheral: SPIM */
Kojto	97:433970e64889	6001	/* Description: SPI master with easyDMA 1. */
Kojto	97:433970e64889	6002
Kojto	97:433970e64889	6003	/* Register: SPIM_SHORTS */
Kojto	97:433970e64889	6004	/* Description: Shortcuts for SPIM. */
Kojto	97:433970e64889	6005
Kojto	97:433970e64889	6006	/* Bit 17 : Shortcut between END event and START task. */
Kojto	97:433970e64889	6007	#define SPIM_SHORTS_END_START_Pos (17UL) /!< Position of END_START field. /
Kojto	97:433970e64889	6008	#define SPIM_SHORTS_END_START_Msk (0x1UL << SPIM_SHORTS_END_START_Pos) /!< Bit mask of END_START field. /
Kojto	97:433970e64889	6009	#define SPIM_SHORTS_END_START_Disabled (0UL) /!< Shortcut disabled. /
Kojto	97:433970e64889	6010	#define SPIM_SHORTS_END_START_Enabled (1UL) /!< Shortcut enabled. /
Kojto	97:433970e64889	6011
Kojto	97:433970e64889	6012	/* Register: SPIM_INTENSET */
Kojto	97:433970e64889	6013	/* Description: Interrupt enable set register. */
Kojto	97:433970e64889	6014
Kojto	97:433970e64889	6015	/* Bit 19 : Enable interrupt on STARTED event. */
Kojto	97:433970e64889	6016	#define SPIM_INTENSET_STARTED_Pos (19UL) /!< Position of STARTED field. /
Kojto	97:433970e64889	6017	#define SPIM_INTENSET_STARTED_Msk (0x1UL << SPIM_INTENSET_STARTED_Pos) /!< Bit mask of STARTED field. /
Kojto	97:433970e64889	6018	#define SPIM_INTENSET_STARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6019	#define SPIM_INTENSET_STARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6020	#define SPIM_INTENSET_STARTED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6021
Kojto	97:433970e64889	6022	/* Bit 8 : Enable interrupt on ENDTX event. */
Kojto	97:433970e64889	6023	#define SPIM_INTENSET_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
Kojto	97:433970e64889	6024	#define SPIM_INTENSET_ENDTX_Msk (0x1UL << SPIM_INTENSET_ENDTX_Pos) /!< Bit mask of ENDTX field. /
Kojto	97:433970e64889	6025	#define SPIM_INTENSET_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6026	#define SPIM_INTENSET_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6027	#define SPIM_INTENSET_ENDTX_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6028
Kojto	97:433970e64889	6029	/* Bit 6 : Enable interrupt on END event. */
Kojto	97:433970e64889	6030	#define SPIM_INTENSET_END_Pos (6UL) /!< Position of END field. /
Kojto	97:433970e64889	6031	#define SPIM_INTENSET_END_Msk (0x1UL << SPIM_INTENSET_END_Pos) /!< Bit mask of END field. /
Kojto	97:433970e64889	6032	#define SPIM_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6033	#define SPIM_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6034	#define SPIM_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6035
Kojto	97:433970e64889	6036	/* Bit 4 : Enable interrupt on ENDRX event. */
Kojto	97:433970e64889	6037	#define SPIM_INTENSET_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	97:433970e64889	6038	#define SPIM_INTENSET_ENDRX_Msk (0x1UL << SPIM_INTENSET_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	97:433970e64889	6039	#define SPIM_INTENSET_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6040	#define SPIM_INTENSET_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6041	#define SPIM_INTENSET_ENDRX_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6042
Kojto	97:433970e64889	6043	/* Bit 1 : Enable interrupt on STOPPED event. */
Kojto	97:433970e64889	6044	#define SPIM_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	97:433970e64889	6045	#define SPIM_INTENSET_STOPPED_Msk (0x1UL << SPIM_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	97:433970e64889	6046	#define SPIM_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6047	#define SPIM_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6048	#define SPIM_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6049
Kojto	97:433970e64889	6050	/* Register: SPIM_INTENCLR */
Kojto	97:433970e64889	6051	/* Description: Interrupt enable clear register. */
Kojto	97:433970e64889	6052
Kojto	97:433970e64889	6053	/* Bit 19 : Disable interrupt on STARTED event. */
Kojto	97:433970e64889	6054	#define SPIM_INTENCLR_STARTED_Pos (19UL) /!< Position of STARTED field. /
Kojto	97:433970e64889	6055	#define SPIM_INTENCLR_STARTED_Msk (0x1UL << SPIM_INTENCLR_STARTED_Pos) /!< Bit mask of STARTED field. /
Kojto	97:433970e64889	6056	#define SPIM_INTENCLR_STARTED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6057	#define SPIM_INTENCLR_STARTED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6058	#define SPIM_INTENCLR_STARTED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6059
Kojto	97:433970e64889	6060	/* Bit 8 : Disable interrupt on ENDTX event. */
Kojto	97:433970e64889	6061	#define SPIM_INTENCLR_ENDTX_Pos (8UL) /!< Position of ENDTX field. /
Kojto	97:433970e64889	6062	#define SPIM_INTENCLR_ENDTX_Msk (0x1UL << SPIM_INTENCLR_ENDTX_Pos) /!< Bit mask of ENDTX field. /
Kojto	97:433970e64889	6063	#define SPIM_INTENCLR_ENDTX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6064	#define SPIM_INTENCLR_ENDTX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6065	#define SPIM_INTENCLR_ENDTX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6066
Kojto	97:433970e64889	6067	/* Bit 6 : Disable interrupt on END event. */
Kojto	97:433970e64889	6068	#define SPIM_INTENCLR_END_Pos (6UL) /!< Position of END field. /
Kojto	97:433970e64889	6069	#define SPIM_INTENCLR_END_Msk (0x1UL << SPIM_INTENCLR_END_Pos) /!< Bit mask of END field. /
Kojto	97:433970e64889	6070	#define SPIM_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6071	#define SPIM_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6072	#define SPIM_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6073
Kojto	97:433970e64889	6074	/* Bit 4 : Disable interrupt on ENDRX event. */
Kojto	97:433970e64889	6075	#define SPIM_INTENCLR_ENDRX_Pos (4UL) /!< Position of ENDRX field. /
Kojto	97:433970e64889	6076	#define SPIM_INTENCLR_ENDRX_Msk (0x1UL << SPIM_INTENCLR_ENDRX_Pos) /!< Bit mask of ENDRX field. /
Kojto	97:433970e64889	6077	#define SPIM_INTENCLR_ENDRX_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6078	#define SPIM_INTENCLR_ENDRX_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6079	#define SPIM_INTENCLR_ENDRX_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6080
Kojto	97:433970e64889	6081	/* Bit 1 : Disable interrupt on STOPPED event. */
Kojto	97:433970e64889	6082	#define SPIM_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
Kojto	97:433970e64889	6083	#define SPIM_INTENCLR_STOPPED_Msk (0x1UL << SPIM_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
Kojto	97:433970e64889	6084	#define SPIM_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6085	#define SPIM_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6086	#define SPIM_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6087
Kojto	97:433970e64889	6088	/* Register: SPIM_ENABLE */
Kojto	97:433970e64889	6089	/* Description: Enable SPIM. */
Kojto	97:433970e64889	6090
Kojto	97:433970e64889	6091	/* Bits 3..0 : Enable or disable SPIM. */
Kojto	97:433970e64889	6092	#define SPIM_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
Kojto	97:433970e64889	6093	#define SPIM_ENABLE_ENABLE_Msk (0xFUL << SPIM_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
Kojto	97:433970e64889	6094	#define SPIM_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIM. /
Kojto	97:433970e64889	6095	#define SPIM_ENABLE_ENABLE_Enabled (0x07UL) /!< Enable SPIM. /
Kojto	97:433970e64889	6096
Kojto	97:433970e64889	6097	/* Register: SPIM_RXDDATA */
Kojto	97:433970e64889	6098	/* Description: RXD register. */
Kojto	97:433970e64889	6099
Kojto	97:433970e64889	6100	/* Bits 7..0 : RX data received. Double buffered. */
Kojto	97:433970e64889	6101	#define SPIM_RXDDATA_RXD_Pos (0UL) /!< Position of RXD field. /
Kojto	97:433970e64889	6102	#define SPIM_RXDDATA_RXD_Msk (0xFFUL << SPIM_RXDDATA_RXD_Pos) /!< Bit mask of RXD field. /
Kojto	97:433970e64889	6103
Kojto	97:433970e64889	6104	/* Register: SPIM_TXDDATA */
Kojto	97:433970e64889	6105	/* Description: TXD register. */
Kojto	97:433970e64889	6106
Kojto	97:433970e64889	6107	/* Bits 7..0 : TX data to send. Double buffered. */
Kojto	97:433970e64889	6108	#define SPIM_TXDDATA_TXD_Pos (0UL) /!< Position of TXD field. /
Kojto	97:433970e64889	6109	#define SPIM_TXDDATA_TXD_Msk (0xFFUL << SPIM_TXDDATA_TXD_Pos) /!< Bit mask of TXD field. /
Kojto	97:433970e64889	6110
Kojto	97:433970e64889	6111	/* Register: SPIM_FREQUENCY */
Kojto	97:433970e64889	6112	/* Description: SPI frequency. */
Kojto	97:433970e64889	6113
Kojto	97:433970e64889	6114	/* Bits 31..0 : SPI master data rate. */
Kojto	97:433970e64889	6115	#define SPIM_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
Kojto	97:433970e64889	6116	#define SPIM_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPIM_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
Kojto	97:433970e64889	6117	#define SPIM_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /!< 125 kbps. /
Kojto	97:433970e64889	6118	#define SPIM_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
Kojto	97:433970e64889	6119	#define SPIM_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /!< 500 kbps. /
Kojto	97:433970e64889	6120	#define SPIM_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /!< 1 Mbps. /
Kojto	97:433970e64889	6121	#define SPIM_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /!< 2 Mbps. /
Kojto	97:433970e64889	6122	#define SPIM_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /!< 4 Mbps. /
Kojto	97:433970e64889	6123	#define SPIM_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /!< 8 Mbps. /
Kojto	97:433970e64889	6124
Kojto	97:433970e64889	6125	/* Register: SPIM_CONFIG */
Kojto	97:433970e64889	6126	/* Description: Configuration register. */
Kojto	97:433970e64889	6127
Kojto	97:433970e64889	6128	/* Bit 2 : Serial clock (SCK) polarity. */
Kojto	97:433970e64889	6129	#define SPIM_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
Kojto	97:433970e64889	6130	#define SPIM_CONFIG_CPOL_Msk (0x1UL << SPIM_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
Kojto	97:433970e64889	6131	#define SPIM_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
Kojto	97:433970e64889	6132	#define SPIM_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
Kojto	97:433970e64889	6133
Kojto	97:433970e64889	6134	/* Bit 1 : Serial clock (SCK) phase. */
Kojto	97:433970e64889	6135	#define SPIM_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
Kojto	97:433970e64889	6136	#define SPIM_CONFIG_CPHA_Msk (0x1UL << SPIM_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
Kojto	97:433970e64889	6137	#define SPIM_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
Kojto	97:433970e64889	6138	#define SPIM_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
Kojto	97:433970e64889	6139
Kojto	97:433970e64889	6140	/* Bit 0 : Bit order. */
Kojto	97:433970e64889	6141	#define SPIM_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
Kojto	97:433970e64889	6142	#define SPIM_CONFIG_ORDER_Msk (0x1UL << SPIM_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
Kojto	97:433970e64889	6143	#define SPIM_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
Kojto	97:433970e64889	6144	#define SPIM_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
Kojto	97:433970e64889	6145
Kojto	97:433970e64889	6146	/* Register: SPIM_ORC */
Kojto	97:433970e64889	6147	/* Description: Over-read character. */
Kojto	97:433970e64889	6148
Kojto	97:433970e64889	6149	/* Bits 7..0 : Over-read character. */
Kojto	97:433970e64889	6150	#define SPIM_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
Kojto	97:433970e64889	6151	#define SPIM_ORC_ORC_Msk (0xFFUL << SPIM_ORC_ORC_Pos) /!< Bit mask of ORC field. /
Kojto	97:433970e64889	6152
Kojto	97:433970e64889	6153	/* Register: SPIM_POWER */
Kojto	97:433970e64889	6154	/* Description: Peripheral power control. */
Kojto	97:433970e64889	6155
Kojto	97:433970e64889	6156	/* Bit 0 : Peripheral power control. */
Kojto	97:433970e64889	6157	#define SPIM_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
Kojto	97:433970e64889	6158	#define SPIM_POWER_POWER_Msk (0x1UL << SPIM_POWER_POWER_Pos) /!< Bit mask of POWER field. /
Kojto	97:433970e64889	6159	#define SPIM_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
Kojto	97:433970e64889	6160	#define SPIM_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
Kojto	97:433970e64889	6161
Kojto	97:433970e64889	6162	/* Register: SPIM_RXD_PTR */
Kojto	97:433970e64889	6163	/* Description: Data pointer. */
Kojto	97:433970e64889	6164
Kojto	97:433970e64889	6165	/* Bits 31..0 : Data pointer. */
Kojto	97:433970e64889	6166	#define SPIM_RXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
Kojto	97:433970e64889	6167	#define SPIM_RXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_RXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
Kojto	97:433970e64889	6168
Kojto	97:433970e64889	6169	/* Register: SPIM_RXD_MAXCNT */
Kojto	97:433970e64889	6170	/* Description: Maximum number of buffer bytes to receive. */
Kojto	97:433970e64889	6171
Kojto	97:433970e64889	6172	/* Bits 7..0 : Maximum number of buffer bytes to receive. */
Kojto	97:433970e64889	6173	#define SPIM_RXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
Kojto	97:433970e64889	6174	#define SPIM_RXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_RXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
Kojto	97:433970e64889	6175
Kojto	97:433970e64889	6176	/* Register: SPIM_RXD_AMOUNT */
Kojto	97:433970e64889	6177	/* Description: Number of bytes received in the last transaction. */
Kojto	97:433970e64889	6178
Kojto	97:433970e64889	6179	/* Bits 7..0 : Number of bytes received in the last transaction. */
Kojto	97:433970e64889	6180	#define SPIM_RXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
Kojto	97:433970e64889	6181	#define SPIM_RXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_RXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
Kojto	97:433970e64889	6182
Kojto	97:433970e64889	6183	/* Register: SPIM_TXD_PTR */
Kojto	97:433970e64889	6184	/* Description: Data pointer. */
Kojto	97:433970e64889	6185
Kojto	97:433970e64889	6186	/* Bits 31..0 : Data pointer. */
Kojto	97:433970e64889	6187	#define SPIM_TXD_PTR_PTR_Pos (0UL) /!< Position of PTR field. /
Kojto	97:433970e64889	6188	#define SPIM_TXD_PTR_PTR_Msk (0xFFFFFFFFUL << SPIM_TXD_PTR_PTR_Pos) /!< Bit mask of PTR field. /
Kojto	97:433970e64889	6189
Kojto	97:433970e64889	6190	/* Register: SPIM_TXD_MAXCNT */
Kojto	97:433970e64889	6191	/* Description: Maximum number of buffer bytes to send. */
Kojto	97:433970e64889	6192
Kojto	97:433970e64889	6193	/* Bits 7..0 : Maximum number of buffer bytes to send. */
Kojto	97:433970e64889	6194	#define SPIM_TXD_MAXCNT_MAXCNT_Pos (0UL) /!< Position of MAXCNT field. /
Kojto	97:433970e64889	6195	#define SPIM_TXD_MAXCNT_MAXCNT_Msk (0xFFUL << SPIM_TXD_MAXCNT_MAXCNT_Pos) /!< Bit mask of MAXCNT field. /
Kojto	97:433970e64889	6196
Kojto	97:433970e64889	6197	/* Register: SPIM_TXD_AMOUNT */
Kojto	97:433970e64889	6198	/* Description: Number of bytes sent in the last transaction. */
Kojto	97:433970e64889	6199
Kojto	97:433970e64889	6200	/* Bits 7..0 : Number of bytes sent in the last transaction. */
Kojto	97:433970e64889	6201	#define SPIM_TXD_AMOUNT_AMOUNT_Pos (0UL) /!< Position of AMOUNT field. /
Kojto	97:433970e64889	6202	#define SPIM_TXD_AMOUNT_AMOUNT_Msk (0xFFUL << SPIM_TXD_AMOUNT_AMOUNT_Pos) /!< Bit mask of AMOUNT field. /
Kojto	97:433970e64889	6203
Kojto	97:433970e64889	6204
emilmont	80:8e73be2a2ac1	6205	/* Peripheral: SPIS */
emilmont	80:8e73be2a2ac1	6206	/* Description: SPI slave 1. */
emilmont	80:8e73be2a2ac1	6207
emilmont	80:8e73be2a2ac1	6208	/* Register: SPIS_SHORTS */
emilmont	80:8e73be2a2ac1	6209	/* Description: Shortcuts for SPIS. */
emilmont	80:8e73be2a2ac1	6210
emilmont	80:8e73be2a2ac1	6211	/* Bit 2 : Shortcut between END event and the ACQUIRE task. */
emilmont	80:8e73be2a2ac1	6212	#define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /!< Position of END_ACQUIRE field. /
emilmont	80:8e73be2a2ac1	6213	#define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /!< Bit mask of END_ACQUIRE field. /
emilmont	80:8e73be2a2ac1	6214	#define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6215	#define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6216
emilmont	80:8e73be2a2ac1	6217	/* Register: SPIS_INTENSET */
emilmont	80:8e73be2a2ac1	6218	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	6219
emilmont	80:8e73be2a2ac1	6220	/* Bit 10 : Enable interrupt on ACQUIRED event. */
emilmont	80:8e73be2a2ac1	6221	#define SPIS_INTENSET_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
emilmont	80:8e73be2a2ac1	6222	#define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
emilmont	80:8e73be2a2ac1	6223	#define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6224	#define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6225	#define SPIS_INTENSET_ACQUIRED_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6226
emilmont	80:8e73be2a2ac1	6227	/* Bit 1 : Enable interrupt on END event. */
emilmont	80:8e73be2a2ac1	6228	#define SPIS_INTENSET_END_Pos (1UL) /!< Position of END field. /
emilmont	80:8e73be2a2ac1	6229	#define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /!< Bit mask of END field. /
emilmont	80:8e73be2a2ac1	6230	#define SPIS_INTENSET_END_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6231	#define SPIS_INTENSET_END_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6232	#define SPIS_INTENSET_END_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6233
emilmont	80:8e73be2a2ac1	6234	/* Register: SPIS_INTENCLR */
emilmont	80:8e73be2a2ac1	6235	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	6236
emilmont	80:8e73be2a2ac1	6237	/* Bit 10 : Disable interrupt on ACQUIRED event. */
emilmont	80:8e73be2a2ac1	6238	#define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /!< Position of ACQUIRED field. /
emilmont	80:8e73be2a2ac1	6239	#define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /!< Bit mask of ACQUIRED field. /
emilmont	80:8e73be2a2ac1	6240	#define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6241	#define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6242	#define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6243
emilmont	80:8e73be2a2ac1	6244	/* Bit 1 : Disable interrupt on END event. */
emilmont	80:8e73be2a2ac1	6245	#define SPIS_INTENCLR_END_Pos (1UL) /!< Position of END field. /
emilmont	80:8e73be2a2ac1	6246	#define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /!< Bit mask of END field. /
emilmont	80:8e73be2a2ac1	6247	#define SPIS_INTENCLR_END_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6248	#define SPIS_INTENCLR_END_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6249	#define SPIS_INTENCLR_END_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6250
emilmont	80:8e73be2a2ac1	6251	/* Register: SPIS_SEMSTAT */
emilmont	80:8e73be2a2ac1	6252	/* Description: Semaphore status. */
emilmont	80:8e73be2a2ac1	6253
emilmont	80:8e73be2a2ac1	6254	/* Bits 1..0 : Semaphore status. */
emilmont	80:8e73be2a2ac1	6255	#define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /!< Position of SEMSTAT field. /
emilmont	80:8e73be2a2ac1	6256	#define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /!< Bit mask of SEMSTAT field. /
emilmont	80:8e73be2a2ac1	6257	#define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /!< Semaphore is free. /
emilmont	80:8e73be2a2ac1	6258	#define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /!< Semaphore is assigned to the CPU. /
emilmont	80:8e73be2a2ac1	6259	#define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /!< Semaphore is assigned to the SPIS. /
emilmont	80:8e73be2a2ac1	6260	#define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. /
emilmont	80:8e73be2a2ac1	6261
emilmont	80:8e73be2a2ac1	6262	/* Register: SPIS_STATUS */
emilmont	80:8e73be2a2ac1	6263	/* Description: Status from last transaction. */
emilmont	80:8e73be2a2ac1	6264
emilmont	80:8e73be2a2ac1	6265	/* Bit 1 : RX buffer overflow detected, and prevented. */
emilmont	80:8e73be2a2ac1	6266	#define SPIS_STATUS_OVERFLOW_Pos (1UL) /!< Position of OVERFLOW field. /
emilmont	80:8e73be2a2ac1	6267	#define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /!< Bit mask of OVERFLOW field. /
emilmont	80:8e73be2a2ac1	6268	#define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /!< Error not present. /
emilmont	80:8e73be2a2ac1	6269	#define SPIS_STATUS_OVERFLOW_Present (1UL) /!< Error present. /
emilmont	80:8e73be2a2ac1	6270	#define SPIS_STATUS_OVERFLOW_Clear (1UL) /!< Clear on write. /
emilmont	80:8e73be2a2ac1	6271
emilmont	80:8e73be2a2ac1	6272	/* Bit 0 : TX buffer overread detected, and prevented. */
emilmont	80:8e73be2a2ac1	6273	#define SPIS_STATUS_OVERREAD_Pos (0UL) /!< Position of OVERREAD field. /
emilmont	80:8e73be2a2ac1	6274	#define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /!< Bit mask of OVERREAD field. /
emilmont	80:8e73be2a2ac1	6275	#define SPIS_STATUS_OVERREAD_NotPresent (0UL) /!< Error not present. /
emilmont	80:8e73be2a2ac1	6276	#define SPIS_STATUS_OVERREAD_Present (1UL) /!< Error present. /
emilmont	80:8e73be2a2ac1	6277	#define SPIS_STATUS_OVERREAD_Clear (1UL) /!< Clear on write. /
emilmont	80:8e73be2a2ac1	6278
emilmont	80:8e73be2a2ac1	6279	/* Register: SPIS_ENABLE */
emilmont	80:8e73be2a2ac1	6280	/* Description: Enable SPIS. */
emilmont	80:8e73be2a2ac1	6281
emilmont	80:8e73be2a2ac1	6282	/* Bits 2..0 : Enable or disable SPIS. */
emilmont	80:8e73be2a2ac1	6283	#define SPIS_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	6284	#define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	6285	#define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled SPIS. /
emilmont	80:8e73be2a2ac1	6286	#define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /!< Enable SPIS. /
emilmont	80:8e73be2a2ac1	6287
emilmont	80:8e73be2a2ac1	6288	/* Register: SPIS_MAXRX */
emilmont	80:8e73be2a2ac1	6289	/* Description: Maximum number of bytes in the receive buffer. */
emilmont	80:8e73be2a2ac1	6290
emilmont	80:8e73be2a2ac1	6291	/* Bits 7..0 : Maximum number of bytes in the receive buffer. */
emilmont	80:8e73be2a2ac1	6292	#define SPIS_MAXRX_MAXRX_Pos (0UL) /!< Position of MAXRX field. /
emilmont	80:8e73be2a2ac1	6293	#define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /!< Bit mask of MAXRX field. /
emilmont	80:8e73be2a2ac1	6294
emilmont	80:8e73be2a2ac1	6295	/* Register: SPIS_AMOUNTRX */
emilmont	80:8e73be2a2ac1	6296	/* Description: Number of bytes received in last granted transaction. */
emilmont	80:8e73be2a2ac1	6297
emilmont	80:8e73be2a2ac1	6298	/* Bits 7..0 : Number of bytes received in last granted transaction. */
emilmont	80:8e73be2a2ac1	6299	#define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /!< Position of AMOUNTRX field. /
emilmont	80:8e73be2a2ac1	6300	#define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /!< Bit mask of AMOUNTRX field. /
emilmont	80:8e73be2a2ac1	6301
emilmont	80:8e73be2a2ac1	6302	/* Register: SPIS_MAXTX */
emilmont	80:8e73be2a2ac1	6303	/* Description: Maximum number of bytes in the transmit buffer. */
emilmont	80:8e73be2a2ac1	6304
emilmont	80:8e73be2a2ac1	6305	/* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
emilmont	80:8e73be2a2ac1	6306	#define SPIS_MAXTX_MAXTX_Pos (0UL) /!< Position of MAXTX field. /
emilmont	80:8e73be2a2ac1	6307	#define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /!< Bit mask of MAXTX field. /
emilmont	80:8e73be2a2ac1	6308
emilmont	80:8e73be2a2ac1	6309	/* Register: SPIS_AMOUNTTX */
emilmont	80:8e73be2a2ac1	6310	/* Description: Number of bytes transmitted in last granted transaction. */
emilmont	80:8e73be2a2ac1	6311
emilmont	80:8e73be2a2ac1	6312	/* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
emilmont	80:8e73be2a2ac1	6313	#define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /!< Position of AMOUNTTX field. /
emilmont	80:8e73be2a2ac1	6314	#define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /!< Bit mask of AMOUNTTX field. /
emilmont	80:8e73be2a2ac1	6315
emilmont	80:8e73be2a2ac1	6316	/* Register: SPIS_CONFIG */
emilmont	80:8e73be2a2ac1	6317	/* Description: Configuration register. */
emilmont	80:8e73be2a2ac1	6318
emilmont	80:8e73be2a2ac1	6319	/* Bit 2 : Serial clock (SCK) polarity. */
emilmont	80:8e73be2a2ac1	6320	#define SPIS_CONFIG_CPOL_Pos (2UL) /!< Position of CPOL field. /
emilmont	80:8e73be2a2ac1	6321	#define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /!< Bit mask of CPOL field. /
emilmont	80:8e73be2a2ac1	6322	#define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /!< Active high. /
emilmont	80:8e73be2a2ac1	6323	#define SPIS_CONFIG_CPOL_ActiveLow (1UL) /!< Active low. /
emilmont	80:8e73be2a2ac1	6324
emilmont	80:8e73be2a2ac1	6325	/* Bit 1 : Serial clock (SCK) phase. */
emilmont	80:8e73be2a2ac1	6326	#define SPIS_CONFIG_CPHA_Pos (1UL) /!< Position of CPHA field. /
emilmont	80:8e73be2a2ac1	6327	#define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /!< Bit mask of CPHA field. /
emilmont	80:8e73be2a2ac1	6328	#define SPIS_CONFIG_CPHA_Leading (0UL) /!< Sample on leading edge of the clock. Shift serial data on trailing edge. /
emilmont	80:8e73be2a2ac1	6329	#define SPIS_CONFIG_CPHA_Trailing (1UL) /!< Sample on trailing edge of the clock. Shift serial data on leading edge. /
emilmont	80:8e73be2a2ac1	6330
emilmont	80:8e73be2a2ac1	6331	/* Bit 0 : Bit order. */
emilmont	80:8e73be2a2ac1	6332	#define SPIS_CONFIG_ORDER_Pos (0UL) /!< Position of ORDER field. /
emilmont	80:8e73be2a2ac1	6333	#define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /!< Bit mask of ORDER field. /
emilmont	80:8e73be2a2ac1	6334	#define SPIS_CONFIG_ORDER_MsbFirst (0UL) /!< Most significant bit transmitted out first. /
emilmont	80:8e73be2a2ac1	6335	#define SPIS_CONFIG_ORDER_LsbFirst (1UL) /!< Least significant bit transmitted out first. /
emilmont	80:8e73be2a2ac1	6336
emilmont	80:8e73be2a2ac1	6337	/* Register: SPIS_DEF */
emilmont	80:8e73be2a2ac1	6338	/* Description: Default character. */
emilmont	80:8e73be2a2ac1	6339
emilmont	80:8e73be2a2ac1	6340	/* Bits 7..0 : Default character. */
emilmont	80:8e73be2a2ac1	6341	#define SPIS_DEF_DEF_Pos (0UL) /!< Position of DEF field. /
emilmont	80:8e73be2a2ac1	6342	#define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /!< Bit mask of DEF field. /
emilmont	80:8e73be2a2ac1	6343
emilmont	80:8e73be2a2ac1	6344	/* Register: SPIS_ORC */
emilmont	80:8e73be2a2ac1	6345	/* Description: Over-read character. */
emilmont	80:8e73be2a2ac1	6346
emilmont	80:8e73be2a2ac1	6347	/* Bits 7..0 : Over-read character. */
emilmont	80:8e73be2a2ac1	6348	#define SPIS_ORC_ORC_Pos (0UL) /!< Position of ORC field. /
emilmont	80:8e73be2a2ac1	6349	#define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /!< Bit mask of ORC field. /
emilmont	80:8e73be2a2ac1	6350
emilmont	80:8e73be2a2ac1	6351	/* Register: SPIS_POWER */
emilmont	80:8e73be2a2ac1	6352	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	6353
emilmont	80:8e73be2a2ac1	6354	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	6355	#define SPIS_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	6356	#define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	6357	#define SPIS_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	6358	#define SPIS_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	6359
emilmont	80:8e73be2a2ac1	6360
emilmont	80:8e73be2a2ac1	6361	/* Peripheral: TEMP */
emilmont	80:8e73be2a2ac1	6362	/* Description: Temperature Sensor. */
emilmont	80:8e73be2a2ac1	6363
emilmont	80:8e73be2a2ac1	6364	/* Register: TEMP_INTENSET */
emilmont	80:8e73be2a2ac1	6365	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	6366
emilmont	80:8e73be2a2ac1	6367	/* Bit 0 : Enable interrupt on DATARDY event. */
emilmont	80:8e73be2a2ac1	6368	#define TEMP_INTENSET_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
emilmont	80:8e73be2a2ac1	6369	#define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /!< Bit mask of DATARDY field. /
emilmont	80:8e73be2a2ac1	6370	#define TEMP_INTENSET_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6371	#define TEMP_INTENSET_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6372	#define TEMP_INTENSET_DATARDY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6373
emilmont	80:8e73be2a2ac1	6374	/* Register: TEMP_INTENCLR */
emilmont	80:8e73be2a2ac1	6375	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	6376
emilmont	80:8e73be2a2ac1	6377	/* Bit 0 : Disable interrupt on DATARDY event. */
emilmont	80:8e73be2a2ac1	6378	#define TEMP_INTENCLR_DATARDY_Pos (0UL) /!< Position of DATARDY field. /
emilmont	80:8e73be2a2ac1	6379	#define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /!< Bit mask of DATARDY field. /
emilmont	80:8e73be2a2ac1	6380	#define TEMP_INTENCLR_DATARDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6381	#define TEMP_INTENCLR_DATARDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6382	#define TEMP_INTENCLR_DATARDY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6383
emilmont	80:8e73be2a2ac1	6384	/* Register: TEMP_POWER */
emilmont	80:8e73be2a2ac1	6385	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	6386
emilmont	80:8e73be2a2ac1	6387	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	6388	#define TEMP_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	6389	#define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	6390	#define TEMP_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	6391	#define TEMP_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	6392
emilmont	80:8e73be2a2ac1	6393
emilmont	80:8e73be2a2ac1	6394	/* Peripheral: TIMER */
emilmont	80:8e73be2a2ac1	6395	/* Description: Timer 0. */
emilmont	80:8e73be2a2ac1	6396
emilmont	80:8e73be2a2ac1	6397	/* Register: TIMER_SHORTS */
emilmont	80:8e73be2a2ac1	6398	/* Description: Shortcuts for Timer. */
emilmont	80:8e73be2a2ac1	6399
emilmont	80:8e73be2a2ac1	6400	/* Bit 11 : Shortcut between CC[3] event and the STOP task. */
emilmont	80:8e73be2a2ac1	6401	#define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /!< Position of COMPARE3_STOP field. /
emilmont	80:8e73be2a2ac1	6402	#define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /!< Bit mask of COMPARE3_STOP field. /
emilmont	80:8e73be2a2ac1	6403	#define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6404	#define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6405
emilmont	80:8e73be2a2ac1	6406	/* Bit 10 : Shortcut between CC[2] event and the STOP task. */
emilmont	80:8e73be2a2ac1	6407	#define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /!< Position of COMPARE2_STOP field. /
emilmont	80:8e73be2a2ac1	6408	#define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /!< Bit mask of COMPARE2_STOP field. /
emilmont	80:8e73be2a2ac1	6409	#define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6410	#define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6411
emilmont	80:8e73be2a2ac1	6412	/* Bit 9 : Shortcut between CC[1] event and the STOP task. */
emilmont	80:8e73be2a2ac1	6413	#define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /!< Position of COMPARE1_STOP field. /
emilmont	80:8e73be2a2ac1	6414	#define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /!< Bit mask of COMPARE1_STOP field. /
emilmont	80:8e73be2a2ac1	6415	#define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6416	#define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6417
emilmont	80:8e73be2a2ac1	6418	/* Bit 8 : Shortcut between CC[0] event and the STOP task. */
emilmont	80:8e73be2a2ac1	6419	#define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /!< Position of COMPARE0_STOP field. /
emilmont	80:8e73be2a2ac1	6420	#define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /!< Bit mask of COMPARE0_STOP field. /
emilmont	80:8e73be2a2ac1	6421	#define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6422	#define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6423
emilmont	80:8e73be2a2ac1	6424	/* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
emilmont	80:8e73be2a2ac1	6425	#define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /!< Position of COMPARE3_CLEAR field. /
emilmont	80:8e73be2a2ac1	6426	#define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /!< Bit mask of COMPARE3_CLEAR field. /
emilmont	80:8e73be2a2ac1	6427	#define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6428	#define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6429
emilmont	80:8e73be2a2ac1	6430	/* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
emilmont	80:8e73be2a2ac1	6431	#define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /!< Position of COMPARE2_CLEAR field. /
emilmont	80:8e73be2a2ac1	6432	#define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /!< Bit mask of COMPARE2_CLEAR field. /
emilmont	80:8e73be2a2ac1	6433	#define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6434	#define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6435
emilmont	80:8e73be2a2ac1	6436	/* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
emilmont	80:8e73be2a2ac1	6437	#define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /!< Position of COMPARE1_CLEAR field. /
emilmont	80:8e73be2a2ac1	6438	#define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /!< Bit mask of COMPARE1_CLEAR field. /
emilmont	80:8e73be2a2ac1	6439	#define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6440	#define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6441
emilmont	80:8e73be2a2ac1	6442	/* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
emilmont	80:8e73be2a2ac1	6443	#define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /!< Position of COMPARE0_CLEAR field. /
emilmont	80:8e73be2a2ac1	6444	#define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /!< Bit mask of COMPARE0_CLEAR field. /
emilmont	80:8e73be2a2ac1	6445	#define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6446	#define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6447
emilmont	80:8e73be2a2ac1	6448	/* Register: TIMER_INTENSET */
emilmont	80:8e73be2a2ac1	6449	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	6450
emilmont	80:8e73be2a2ac1	6451	/* Bit 19 : Enable interrupt on COMPARE[3] */
emilmont	80:8e73be2a2ac1	6452	#define TIMER_INTENSET_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	6453	#define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	6454	#define TIMER_INTENSET_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6455	#define TIMER_INTENSET_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6456	#define TIMER_INTENSET_COMPARE3_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6457
emilmont	80:8e73be2a2ac1	6458	/* Bit 18 : Enable interrupt on COMPARE[2] */
emilmont	80:8e73be2a2ac1	6459	#define TIMER_INTENSET_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	6460	#define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	6461	#define TIMER_INTENSET_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6462	#define TIMER_INTENSET_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6463	#define TIMER_INTENSET_COMPARE2_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6464
emilmont	80:8e73be2a2ac1	6465	/* Bit 17 : Enable interrupt on COMPARE[1] */
emilmont	80:8e73be2a2ac1	6466	#define TIMER_INTENSET_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	6467	#define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	6468	#define TIMER_INTENSET_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6469	#define TIMER_INTENSET_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6470	#define TIMER_INTENSET_COMPARE1_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6471
emilmont	80:8e73be2a2ac1	6472	/* Bit 16 : Enable interrupt on COMPARE[0] */
emilmont	80:8e73be2a2ac1	6473	#define TIMER_INTENSET_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	6474	#define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	6475	#define TIMER_INTENSET_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6476	#define TIMER_INTENSET_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6477	#define TIMER_INTENSET_COMPARE0_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6478
emilmont	80:8e73be2a2ac1	6479	/* Register: TIMER_INTENCLR */
emilmont	80:8e73be2a2ac1	6480	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	6481
emilmont	80:8e73be2a2ac1	6482	/* Bit 19 : Disable interrupt on COMPARE[3] */
emilmont	80:8e73be2a2ac1	6483	#define TIMER_INTENCLR_COMPARE3_Pos (19UL) /!< Position of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	6484	#define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /!< Bit mask of COMPARE3 field. /
emilmont	80:8e73be2a2ac1	6485	#define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6486	#define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6487	#define TIMER_INTENCLR_COMPARE3_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6488
emilmont	80:8e73be2a2ac1	6489	/* Bit 18 : Disable interrupt on COMPARE[2] */
emilmont	80:8e73be2a2ac1	6490	#define TIMER_INTENCLR_COMPARE2_Pos (18UL) /!< Position of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	6491	#define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /!< Bit mask of COMPARE2 field. /
emilmont	80:8e73be2a2ac1	6492	#define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6493	#define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6494	#define TIMER_INTENCLR_COMPARE2_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6495
emilmont	80:8e73be2a2ac1	6496	/* Bit 17 : Disable interrupt on COMPARE[1] */
emilmont	80:8e73be2a2ac1	6497	#define TIMER_INTENCLR_COMPARE1_Pos (17UL) /!< Position of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	6498	#define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /!< Bit mask of COMPARE1 field. /
emilmont	80:8e73be2a2ac1	6499	#define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6500	#define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6501	#define TIMER_INTENCLR_COMPARE1_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6502
emilmont	80:8e73be2a2ac1	6503	/* Bit 16 : Disable interrupt on COMPARE[0] */
emilmont	80:8e73be2a2ac1	6504	#define TIMER_INTENCLR_COMPARE0_Pos (16UL) /!< Position of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	6505	#define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /!< Bit mask of COMPARE0 field. /
emilmont	80:8e73be2a2ac1	6506	#define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6507	#define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6508	#define TIMER_INTENCLR_COMPARE0_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6509
emilmont	80:8e73be2a2ac1	6510	/* Register: TIMER_MODE */
emilmont	80:8e73be2a2ac1	6511	/* Description: Timer Mode selection. */
emilmont	80:8e73be2a2ac1	6512
emilmont	80:8e73be2a2ac1	6513	/* Bit 0 : Select Normal or Counter mode. */
emilmont	80:8e73be2a2ac1	6514	#define TIMER_MODE_MODE_Pos (0UL) /!< Position of MODE field. /
emilmont	80:8e73be2a2ac1	6515	#define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /!< Bit mask of MODE field. /
emilmont	80:8e73be2a2ac1	6516	#define TIMER_MODE_MODE_Timer (0UL) /!< Timer in Normal mode. /
emilmont	80:8e73be2a2ac1	6517	#define TIMER_MODE_MODE_Counter (1UL) /!< Timer in Counter mode. /
emilmont	80:8e73be2a2ac1	6518
emilmont	80:8e73be2a2ac1	6519	/* Register: TIMER_BITMODE */
emilmont	80:8e73be2a2ac1	6520	/* Description: Sets timer behaviour. */
emilmont	80:8e73be2a2ac1	6521
emilmont	80:8e73be2a2ac1	6522	/* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
emilmont	80:8e73be2a2ac1	6523	#define TIMER_BITMODE_BITMODE_Pos (0UL) /!< Position of BITMODE field. /
emilmont	80:8e73be2a2ac1	6524	#define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /!< Bit mask of BITMODE field. /
emilmont	80:8e73be2a2ac1	6525	#define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /!< 16-bit timer behaviour. /
emilmont	80:8e73be2a2ac1	6526	#define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /!< 8-bit timer behaviour. /
emilmont	80:8e73be2a2ac1	6527	#define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /!< 24-bit timer behaviour. /
emilmont	80:8e73be2a2ac1	6528	#define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /!< 32-bit timer behaviour. /
emilmont	80:8e73be2a2ac1	6529
emilmont	80:8e73be2a2ac1	6530	/* Register: TIMER_PRESCALER */
emilmont	80:8e73be2a2ac1	6531	/* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
emilmont	80:8e73be2a2ac1	6532
emilmont	80:8e73be2a2ac1	6533	/* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
emilmont	80:8e73be2a2ac1	6534	#define TIMER_PRESCALER_PRESCALER_Pos (0UL) /!< Position of PRESCALER field. /
emilmont	80:8e73be2a2ac1	6535	#define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /!< Bit mask of PRESCALER field. /
emilmont	80:8e73be2a2ac1	6536
emilmont	80:8e73be2a2ac1	6537	/* Register: TIMER_POWER */
emilmont	80:8e73be2a2ac1	6538	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	6539
emilmont	80:8e73be2a2ac1	6540	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	6541	#define TIMER_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	6542	#define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	6543	#define TIMER_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	6544	#define TIMER_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	6545
emilmont	80:8e73be2a2ac1	6546
emilmont	80:8e73be2a2ac1	6547	/* Peripheral: TWI */
emilmont	80:8e73be2a2ac1	6548	/* Description: Two-wire interface master 0. */
emilmont	80:8e73be2a2ac1	6549
emilmont	80:8e73be2a2ac1	6550	/* Register: TWI_SHORTS */
emilmont	80:8e73be2a2ac1	6551	/* Description: Shortcuts for TWI. */
emilmont	80:8e73be2a2ac1	6552
emilmont	80:8e73be2a2ac1	6553	/* Bit 1 : Shortcut between BB event and the STOP task. */
emilmont	80:8e73be2a2ac1	6554	#define TWI_SHORTS_BB_STOP_Pos (1UL) /!< Position of BB_STOP field. /
emilmont	80:8e73be2a2ac1	6555	#define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /!< Bit mask of BB_STOP field. /
emilmont	80:8e73be2a2ac1	6556	#define TWI_SHORTS_BB_STOP_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6557	#define TWI_SHORTS_BB_STOP_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6558
emilmont	80:8e73be2a2ac1	6559	/* Bit 0 : Shortcut between BB event and the SUSPEND task. */
emilmont	80:8e73be2a2ac1	6560	#define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /!< Position of BB_SUSPEND field. /
emilmont	80:8e73be2a2ac1	6561	#define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /!< Bit mask of BB_SUSPEND field. /
emilmont	80:8e73be2a2ac1	6562	#define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6563	#define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6564
emilmont	80:8e73be2a2ac1	6565	/* Register: TWI_INTENSET */
emilmont	80:8e73be2a2ac1	6566	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	6567
Kojto	97:433970e64889	6568	/* Bit 18 : Enable interrupt on SUSPENDED event. */
Kojto	97:433970e64889	6569	#define TWI_INTENSET_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
Kojto	97:433970e64889	6570	#define TWI_INTENSET_SUSPENDED_Msk (0x1UL << TWI_INTENSET_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
Kojto	97:433970e64889	6571	#define TWI_INTENSET_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6572	#define TWI_INTENSET_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6573	#define TWI_INTENSET_SUSPENDED_Set (1UL) /!< Enable interrupt on write. /
Kojto	97:433970e64889	6574
emilmont	80:8e73be2a2ac1	6575	/* Bit 14 : Enable interrupt on BB event. */
emilmont	80:8e73be2a2ac1	6576	#define TWI_INTENSET_BB_Pos (14UL) /!< Position of BB field. /
emilmont	80:8e73be2a2ac1	6577	#define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /!< Bit mask of BB field. /
emilmont	80:8e73be2a2ac1	6578	#define TWI_INTENSET_BB_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6579	#define TWI_INTENSET_BB_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6580	#define TWI_INTENSET_BB_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6581
emilmont	80:8e73be2a2ac1	6582	/* Bit 9 : Enable interrupt on ERROR event. */
emilmont	80:8e73be2a2ac1	6583	#define TWI_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
emilmont	80:8e73be2a2ac1	6584	#define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
emilmont	80:8e73be2a2ac1	6585	#define TWI_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6586	#define TWI_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6587	#define TWI_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6588
emilmont	80:8e73be2a2ac1	6589	/* Bit 7 : Enable interrupt on TXDSENT event. */
emilmont	80:8e73be2a2ac1	6590	#define TWI_INTENSET_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
emilmont	80:8e73be2a2ac1	6591	#define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
emilmont	80:8e73be2a2ac1	6592	#define TWI_INTENSET_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6593	#define TWI_INTENSET_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6594	#define TWI_INTENSET_TXDSENT_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6595
emilmont	80:8e73be2a2ac1	6596	/* Bit 2 : Enable interrupt on READY event. */
emilmont	80:8e73be2a2ac1	6597	#define TWI_INTENSET_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
emilmont	80:8e73be2a2ac1	6598	#define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
emilmont	80:8e73be2a2ac1	6599	#define TWI_INTENSET_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6600	#define TWI_INTENSET_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6601	#define TWI_INTENSET_RXDREADY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6602
emilmont	80:8e73be2a2ac1	6603	/* Bit 1 : Enable interrupt on STOPPED event. */
emilmont	80:8e73be2a2ac1	6604	#define TWI_INTENSET_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
emilmont	80:8e73be2a2ac1	6605	#define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /!< Bit mask of STOPPED field. /
emilmont	80:8e73be2a2ac1	6606	#define TWI_INTENSET_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6607	#define TWI_INTENSET_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6608	#define TWI_INTENSET_STOPPED_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6609
emilmont	80:8e73be2a2ac1	6610	/* Register: TWI_INTENCLR */
emilmont	80:8e73be2a2ac1	6611	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	6612
Kojto	97:433970e64889	6613	/* Bit 18 : Disable interrupt on SUSPENDED event. */
Kojto	97:433970e64889	6614	#define TWI_INTENCLR_SUSPENDED_Pos (18UL) /!< Position of SUSPENDED field. /
Kojto	97:433970e64889	6615	#define TWI_INTENCLR_SUSPENDED_Msk (0x1UL << TWI_INTENCLR_SUSPENDED_Pos) /!< Bit mask of SUSPENDED field. /
Kojto	97:433970e64889	6616	#define TWI_INTENCLR_SUSPENDED_Disabled (0UL) /!< Interrupt disabled. /
Kojto	97:433970e64889	6617	#define TWI_INTENCLR_SUSPENDED_Enabled (1UL) /!< Interrupt enabled. /
Kojto	97:433970e64889	6618	#define TWI_INTENCLR_SUSPENDED_Clear (1UL) /!< Disable interrupt on write. /
Kojto	97:433970e64889	6619
emilmont	80:8e73be2a2ac1	6620	/* Bit 14 : Disable interrupt on BB event. */
emilmont	80:8e73be2a2ac1	6621	#define TWI_INTENCLR_BB_Pos (14UL) /!< Position of BB field. /
emilmont	80:8e73be2a2ac1	6622	#define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /!< Bit mask of BB field. /
emilmont	80:8e73be2a2ac1	6623	#define TWI_INTENCLR_BB_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6624	#define TWI_INTENCLR_BB_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6625	#define TWI_INTENCLR_BB_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6626
emilmont	80:8e73be2a2ac1	6627	/* Bit 9 : Disable interrupt on ERROR event. */
emilmont	80:8e73be2a2ac1	6628	#define TWI_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
emilmont	80:8e73be2a2ac1	6629	#define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
emilmont	80:8e73be2a2ac1	6630	#define TWI_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6631	#define TWI_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6632	#define TWI_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6633
emilmont	80:8e73be2a2ac1	6634	/* Bit 7 : Disable interrupt on TXDSENT event. */
emilmont	80:8e73be2a2ac1	6635	#define TWI_INTENCLR_TXDSENT_Pos (7UL) /!< Position of TXDSENT field. /
emilmont	80:8e73be2a2ac1	6636	#define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /!< Bit mask of TXDSENT field. /
emilmont	80:8e73be2a2ac1	6637	#define TWI_INTENCLR_TXDSENT_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6638	#define TWI_INTENCLR_TXDSENT_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6639	#define TWI_INTENCLR_TXDSENT_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6640
emilmont	80:8e73be2a2ac1	6641	/* Bit 2 : Disable interrupt on RXDREADY event. */
emilmont	80:8e73be2a2ac1	6642	#define TWI_INTENCLR_RXDREADY_Pos (2UL) /!< Position of RXDREADY field. /
emilmont	80:8e73be2a2ac1	6643	#define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /!< Bit mask of RXDREADY field. /
emilmont	80:8e73be2a2ac1	6644	#define TWI_INTENCLR_RXDREADY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6645	#define TWI_INTENCLR_RXDREADY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6646	#define TWI_INTENCLR_RXDREADY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6647
emilmont	80:8e73be2a2ac1	6648	/* Bit 1 : Disable interrupt on STOPPED event. */
emilmont	80:8e73be2a2ac1	6649	#define TWI_INTENCLR_STOPPED_Pos (1UL) /!< Position of STOPPED field. /
emilmont	80:8e73be2a2ac1	6650	#define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /!< Bit mask of STOPPED field. /
emilmont	80:8e73be2a2ac1	6651	#define TWI_INTENCLR_STOPPED_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6652	#define TWI_INTENCLR_STOPPED_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6653	#define TWI_INTENCLR_STOPPED_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6654
emilmont	80:8e73be2a2ac1	6655	/* Register: TWI_ERRORSRC */
emilmont	80:8e73be2a2ac1	6656	/* Description: Two-wire error source. Write error field to 1 to clear error. */
emilmont	80:8e73be2a2ac1	6657
emilmont	80:8e73be2a2ac1	6658	/* Bit 2 : NACK received after sending a data byte. */
emilmont	80:8e73be2a2ac1	6659	#define TWI_ERRORSRC_DNACK_Pos (2UL) /!< Position of DNACK field. /
emilmont	80:8e73be2a2ac1	6660	#define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /!< Bit mask of DNACK field. /
emilmont	80:8e73be2a2ac1	6661	#define TWI_ERRORSRC_DNACK_NotPresent (0UL) /!< Error not present. /
emilmont	80:8e73be2a2ac1	6662	#define TWI_ERRORSRC_DNACK_Present (1UL) /!< Error present. /
emilmont	80:8e73be2a2ac1	6663	#define TWI_ERRORSRC_DNACK_Clear (1UL) /!< Clear error on write. /
emilmont	80:8e73be2a2ac1	6664
emilmont	80:8e73be2a2ac1	6665	/* Bit 1 : NACK received after sending the address. */
emilmont	80:8e73be2a2ac1	6666	#define TWI_ERRORSRC_ANACK_Pos (1UL) /!< Position of ANACK field. /
emilmont	80:8e73be2a2ac1	6667	#define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /!< Bit mask of ANACK field. /
emilmont	80:8e73be2a2ac1	6668	#define TWI_ERRORSRC_ANACK_NotPresent (0UL) /!< Error not present. /
emilmont	80:8e73be2a2ac1	6669	#define TWI_ERRORSRC_ANACK_Present (1UL) /!< Error present. /
emilmont	80:8e73be2a2ac1	6670	#define TWI_ERRORSRC_ANACK_Clear (1UL) /!< Clear error on write. /
emilmont	80:8e73be2a2ac1	6671
emilmont	80:8e73be2a2ac1	6672	/* Register: TWI_ENABLE */
emilmont	80:8e73be2a2ac1	6673	/* Description: Enable two-wire master. */
emilmont	80:8e73be2a2ac1	6674
emilmont	80:8e73be2a2ac1	6675	/* Bits 2..0 : Enable or disable W2M */
emilmont	80:8e73be2a2ac1	6676	#define TWI_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	6677	#define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	6678	#define TWI_ENABLE_ENABLE_Disabled (0x00UL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	6679	#define TWI_ENABLE_ENABLE_Enabled (0x05UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	6680
emilmont	80:8e73be2a2ac1	6681	/* Register: TWI_RXD */
emilmont	80:8e73be2a2ac1	6682	/* Description: RX data register. */
emilmont	80:8e73be2a2ac1	6683
emilmont	80:8e73be2a2ac1	6684	/* Bits 7..0 : RX data from last transfer. */
emilmont	80:8e73be2a2ac1	6685	#define TWI_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
emilmont	80:8e73be2a2ac1	6686	#define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /!< Bit mask of RXD field. /
emilmont	80:8e73be2a2ac1	6687
emilmont	80:8e73be2a2ac1	6688	/* Register: TWI_TXD */
emilmont	80:8e73be2a2ac1	6689	/* Description: TX data register. */
emilmont	80:8e73be2a2ac1	6690
emilmont	80:8e73be2a2ac1	6691	/* Bits 7..0 : TX data for next transfer. */
emilmont	80:8e73be2a2ac1	6692	#define TWI_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
emilmont	80:8e73be2a2ac1	6693	#define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /!< Bit mask of TXD field. /
emilmont	80:8e73be2a2ac1	6694
emilmont	80:8e73be2a2ac1	6695	/* Register: TWI_FREQUENCY */
emilmont	80:8e73be2a2ac1	6696	/* Description: Two-wire frequency. */
emilmont	80:8e73be2a2ac1	6697
emilmont	80:8e73be2a2ac1	6698	/* Bits 31..0 : Two-wire master clock frequency. */
emilmont	80:8e73be2a2ac1	6699	#define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /!< Position of FREQUENCY field. /
emilmont	80:8e73be2a2ac1	6700	#define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /!< Bit mask of FREQUENCY field. /
emilmont	80:8e73be2a2ac1	6701	#define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /!< 100 kbps. /
emilmont	80:8e73be2a2ac1	6702	#define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /!< 250 kbps. /
emilmont	80:8e73be2a2ac1	6703	#define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /!< 400 kbps. /
emilmont	80:8e73be2a2ac1	6704
emilmont	80:8e73be2a2ac1	6705	/* Register: TWI_ADDRESS */
emilmont	80:8e73be2a2ac1	6706	/* Description: Address used in the two-wire transfer. */
emilmont	80:8e73be2a2ac1	6707
emilmont	80:8e73be2a2ac1	6708	/* Bits 6..0 : Two-wire address. */
emilmont	80:8e73be2a2ac1	6709	#define TWI_ADDRESS_ADDRESS_Pos (0UL) /!< Position of ADDRESS field. /
emilmont	80:8e73be2a2ac1	6710	#define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /!< Bit mask of ADDRESS field. /
emilmont	80:8e73be2a2ac1	6711
emilmont	80:8e73be2a2ac1	6712	/* Register: TWI_POWER */
emilmont	80:8e73be2a2ac1	6713	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	6714
emilmont	80:8e73be2a2ac1	6715	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	6716	#define TWI_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	6717	#define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	6718	#define TWI_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	6719	#define TWI_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	6720
emilmont	80:8e73be2a2ac1	6721
emilmont	80:8e73be2a2ac1	6722	/* Peripheral: UART */
emilmont	80:8e73be2a2ac1	6723	/* Description: Universal Asynchronous Receiver/Transmitter. */
emilmont	80:8e73be2a2ac1	6724
emilmont	80:8e73be2a2ac1	6725	/* Register: UART_SHORTS */
Kojto	97:433970e64889	6726	/* Description: Shortcuts for UART. */
emilmont	80:8e73be2a2ac1	6727
emilmont	80:8e73be2a2ac1	6728	/* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
emilmont	80:8e73be2a2ac1	6729	#define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /!< Position of NCTS_STOPRX field. /
emilmont	80:8e73be2a2ac1	6730	#define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /!< Bit mask of NCTS_STOPRX field. /
emilmont	80:8e73be2a2ac1	6731	#define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6732	#define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6733
emilmont	80:8e73be2a2ac1	6734	/* Bit 3 : Shortcut between CTS event and the STARTRX task. */
emilmont	80:8e73be2a2ac1	6735	#define UART_SHORTS_CTS_STARTRX_Pos (3UL) /!< Position of CTS_STARTRX field. /
emilmont	80:8e73be2a2ac1	6736	#define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /!< Bit mask of CTS_STARTRX field. /
emilmont	80:8e73be2a2ac1	6737	#define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /!< Shortcut disabled. /
emilmont	80:8e73be2a2ac1	6738	#define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /!< Shortcut enabled. /
emilmont	80:8e73be2a2ac1	6739
emilmont	80:8e73be2a2ac1	6740	/* Register: UART_INTENSET */
emilmont	80:8e73be2a2ac1	6741	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	6742
emilmont	80:8e73be2a2ac1	6743	/* Bit 17 : Enable interrupt on RXTO event. */
emilmont	80:8e73be2a2ac1	6744	#define UART_INTENSET_RXTO_Pos (17UL) /!< Position of RXTO field. /
emilmont	80:8e73be2a2ac1	6745	#define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /!< Bit mask of RXTO field. /
emilmont	80:8e73be2a2ac1	6746	#define UART_INTENSET_RXTO_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6747	#define UART_INTENSET_RXTO_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6748	#define UART_INTENSET_RXTO_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6749
emilmont	80:8e73be2a2ac1	6750	/* Bit 9 : Enable interrupt on ERROR event. */
emilmont	80:8e73be2a2ac1	6751	#define UART_INTENSET_ERROR_Pos (9UL) /!< Position of ERROR field. /
emilmont	80:8e73be2a2ac1	6752	#define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /!< Bit mask of ERROR field. /
emilmont	80:8e73be2a2ac1	6753	#define UART_INTENSET_ERROR_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6754	#define UART_INTENSET_ERROR_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6755	#define UART_INTENSET_ERROR_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6756
emilmont	80:8e73be2a2ac1	6757	/* Bit 7 : Enable interrupt on TXRDY event. */
emilmont	80:8e73be2a2ac1	6758	#define UART_INTENSET_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
emilmont	80:8e73be2a2ac1	6759	#define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
emilmont	80:8e73be2a2ac1	6760	#define UART_INTENSET_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6761	#define UART_INTENSET_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6762	#define UART_INTENSET_TXDRDY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6763
emilmont	80:8e73be2a2ac1	6764	/* Bit 2 : Enable interrupt on RXRDY event. */
emilmont	80:8e73be2a2ac1	6765	#define UART_INTENSET_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
emilmont	80:8e73be2a2ac1	6766	#define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
emilmont	80:8e73be2a2ac1	6767	#define UART_INTENSET_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6768	#define UART_INTENSET_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6769	#define UART_INTENSET_RXDRDY_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6770
emilmont	80:8e73be2a2ac1	6771	/* Bit 1 : Enable interrupt on NCTS event. */
emilmont	80:8e73be2a2ac1	6772	#define UART_INTENSET_NCTS_Pos (1UL) /!< Position of NCTS field. /
emilmont	80:8e73be2a2ac1	6773	#define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /!< Bit mask of NCTS field. /
emilmont	80:8e73be2a2ac1	6774	#define UART_INTENSET_NCTS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6775	#define UART_INTENSET_NCTS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6776	#define UART_INTENSET_NCTS_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6777
emilmont	80:8e73be2a2ac1	6778	/* Bit 0 : Enable interrupt on CTS event. */
emilmont	80:8e73be2a2ac1	6779	#define UART_INTENSET_CTS_Pos (0UL) /!< Position of CTS field. /
emilmont	80:8e73be2a2ac1	6780	#define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /!< Bit mask of CTS field. /
emilmont	80:8e73be2a2ac1	6781	#define UART_INTENSET_CTS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6782	#define UART_INTENSET_CTS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6783	#define UART_INTENSET_CTS_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6784
emilmont	80:8e73be2a2ac1	6785	/* Register: UART_INTENCLR */
emilmont	80:8e73be2a2ac1	6786	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	6787
emilmont	80:8e73be2a2ac1	6788	/* Bit 17 : Disable interrupt on RXTO event. */
emilmont	80:8e73be2a2ac1	6789	#define UART_INTENCLR_RXTO_Pos (17UL) /!< Position of RXTO field. /
emilmont	80:8e73be2a2ac1	6790	#define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /!< Bit mask of RXTO field. /
emilmont	80:8e73be2a2ac1	6791	#define UART_INTENCLR_RXTO_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6792	#define UART_INTENCLR_RXTO_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6793	#define UART_INTENCLR_RXTO_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6794
emilmont	80:8e73be2a2ac1	6795	/* Bit 9 : Disable interrupt on ERROR event. */
emilmont	80:8e73be2a2ac1	6796	#define UART_INTENCLR_ERROR_Pos (9UL) /!< Position of ERROR field. /
emilmont	80:8e73be2a2ac1	6797	#define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /!< Bit mask of ERROR field. /
emilmont	80:8e73be2a2ac1	6798	#define UART_INTENCLR_ERROR_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6799	#define UART_INTENCLR_ERROR_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6800	#define UART_INTENCLR_ERROR_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6801
emilmont	80:8e73be2a2ac1	6802	/* Bit 7 : Disable interrupt on TXRDY event. */
emilmont	80:8e73be2a2ac1	6803	#define UART_INTENCLR_TXDRDY_Pos (7UL) /!< Position of TXDRDY field. /
emilmont	80:8e73be2a2ac1	6804	#define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /!< Bit mask of TXDRDY field. /
emilmont	80:8e73be2a2ac1	6805	#define UART_INTENCLR_TXDRDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6806	#define UART_INTENCLR_TXDRDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6807	#define UART_INTENCLR_TXDRDY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6808
emilmont	80:8e73be2a2ac1	6809	/* Bit 2 : Disable interrupt on RXRDY event. */
emilmont	80:8e73be2a2ac1	6810	#define UART_INTENCLR_RXDRDY_Pos (2UL) /!< Position of RXDRDY field. /
emilmont	80:8e73be2a2ac1	6811	#define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /!< Bit mask of RXDRDY field. /
emilmont	80:8e73be2a2ac1	6812	#define UART_INTENCLR_RXDRDY_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6813	#define UART_INTENCLR_RXDRDY_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6814	#define UART_INTENCLR_RXDRDY_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6815
emilmont	80:8e73be2a2ac1	6816	/* Bit 1 : Disable interrupt on NCTS event. */
emilmont	80:8e73be2a2ac1	6817	#define UART_INTENCLR_NCTS_Pos (1UL) /!< Position of NCTS field. /
emilmont	80:8e73be2a2ac1	6818	#define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /!< Bit mask of NCTS field. /
emilmont	80:8e73be2a2ac1	6819	#define UART_INTENCLR_NCTS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6820	#define UART_INTENCLR_NCTS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6821	#define UART_INTENCLR_NCTS_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6822
emilmont	80:8e73be2a2ac1	6823	/* Bit 0 : Disable interrupt on CTS event. */
emilmont	80:8e73be2a2ac1	6824	#define UART_INTENCLR_CTS_Pos (0UL) /!< Position of CTS field. /
emilmont	80:8e73be2a2ac1	6825	#define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /!< Bit mask of CTS field. /
emilmont	80:8e73be2a2ac1	6826	#define UART_INTENCLR_CTS_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6827	#define UART_INTENCLR_CTS_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6828	#define UART_INTENCLR_CTS_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6829
emilmont	80:8e73be2a2ac1	6830	/* Register: UART_ERRORSRC */
emilmont	80:8e73be2a2ac1	6831	/* Description: Error source. Write error field to 1 to clear error. */
emilmont	80:8e73be2a2ac1	6832
emilmont	80:8e73be2a2ac1	6833	/* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
emilmont	80:8e73be2a2ac1	6834	#define UART_ERRORSRC_BREAK_Pos (3UL) /!< Position of BREAK field. /
emilmont	80:8e73be2a2ac1	6835	#define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /!< Bit mask of BREAK field. /
emilmont	80:8e73be2a2ac1	6836	#define UART_ERRORSRC_BREAK_NotPresent (0UL) /!< Error not present. /
emilmont	80:8e73be2a2ac1	6837	#define UART_ERRORSRC_BREAK_Present (1UL) /!< Error present. /
emilmont	80:8e73be2a2ac1	6838	#define UART_ERRORSRC_BREAK_Clear (1UL) /!< Clear error on write. /
emilmont	80:8e73be2a2ac1	6839
emilmont	80:8e73be2a2ac1	6840	/* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
emilmont	80:8e73be2a2ac1	6841	#define UART_ERRORSRC_FRAMING_Pos (2UL) /!< Position of FRAMING field. /
emilmont	80:8e73be2a2ac1	6842	#define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /!< Bit mask of FRAMING field. /
emilmont	80:8e73be2a2ac1	6843	#define UART_ERRORSRC_FRAMING_NotPresent (0UL) /!< Error not present. /
emilmont	80:8e73be2a2ac1	6844	#define UART_ERRORSRC_FRAMING_Present (1UL) /!< Error present. /
emilmont	80:8e73be2a2ac1	6845	#define UART_ERRORSRC_FRAMING_Clear (1UL) /!< Clear error on write. /
emilmont	80:8e73be2a2ac1	6846
emilmont	80:8e73be2a2ac1	6847	/* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
emilmont	80:8e73be2a2ac1	6848	#define UART_ERRORSRC_PARITY_Pos (1UL) /!< Position of PARITY field. /
emilmont	80:8e73be2a2ac1	6849	#define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /!< Bit mask of PARITY field. /
emilmont	80:8e73be2a2ac1	6850	#define UART_ERRORSRC_PARITY_NotPresent (0UL) /!< Error not present. /
emilmont	80:8e73be2a2ac1	6851	#define UART_ERRORSRC_PARITY_Present (1UL) /!< Error present. /
emilmont	80:8e73be2a2ac1	6852	#define UART_ERRORSRC_PARITY_Clear (1UL) /!< Clear error on write. /
emilmont	80:8e73be2a2ac1	6853
emilmont	80:8e73be2a2ac1	6854	/* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
emilmont	80:8e73be2a2ac1	6855	#define UART_ERRORSRC_OVERRUN_Pos (0UL) /!< Position of OVERRUN field. /
emilmont	80:8e73be2a2ac1	6856	#define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /!< Bit mask of OVERRUN field. /
emilmont	80:8e73be2a2ac1	6857	#define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /!< Error not present. /
emilmont	80:8e73be2a2ac1	6858	#define UART_ERRORSRC_OVERRUN_Present (1UL) /!< Error present. /
emilmont	80:8e73be2a2ac1	6859	#define UART_ERRORSRC_OVERRUN_Clear (1UL) /!< Clear error on write. /
emilmont	80:8e73be2a2ac1	6860
emilmont	80:8e73be2a2ac1	6861	/* Register: UART_ENABLE */
emilmont	80:8e73be2a2ac1	6862	/* Description: Enable UART and acquire IOs. */
emilmont	80:8e73be2a2ac1	6863
emilmont	80:8e73be2a2ac1	6864	/* Bits 2..0 : Enable or disable UART and acquire IOs. */
emilmont	80:8e73be2a2ac1	6865	#define UART_ENABLE_ENABLE_Pos (0UL) /!< Position of ENABLE field. /
emilmont	80:8e73be2a2ac1	6866	#define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /!< Bit mask of ENABLE field. /
emilmont	80:8e73be2a2ac1	6867	#define UART_ENABLE_ENABLE_Disabled (0x00UL) /!< UART disabled. /
emilmont	80:8e73be2a2ac1	6868	#define UART_ENABLE_ENABLE_Enabled (0x04UL) /!< UART enabled. /
emilmont	80:8e73be2a2ac1	6869
emilmont	80:8e73be2a2ac1	6870	/* Register: UART_RXD */
Kojto	97:433970e64889	6871	/* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consumed. If read when no character available, the UART will stop working. */
emilmont	80:8e73be2a2ac1	6872
emilmont	80:8e73be2a2ac1	6873	/* Bits 7..0 : RX data from previous transfer. Double buffered. */
emilmont	80:8e73be2a2ac1	6874	#define UART_RXD_RXD_Pos (0UL) /!< Position of RXD field. /
emilmont	80:8e73be2a2ac1	6875	#define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /!< Bit mask of RXD field. /
emilmont	80:8e73be2a2ac1	6876
emilmont	80:8e73be2a2ac1	6877	/* Register: UART_TXD */
emilmont	80:8e73be2a2ac1	6878	/* Description: TXD register. */
emilmont	80:8e73be2a2ac1	6879
emilmont	80:8e73be2a2ac1	6880	/* Bits 7..0 : TX data for transfer. */
emilmont	80:8e73be2a2ac1	6881	#define UART_TXD_TXD_Pos (0UL) /!< Position of TXD field. /
emilmont	80:8e73be2a2ac1	6882	#define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /!< Bit mask of TXD field. /
emilmont	80:8e73be2a2ac1	6883
emilmont	80:8e73be2a2ac1	6884	/* Register: UART_BAUDRATE */
emilmont	80:8e73be2a2ac1	6885	/* Description: UART Baudrate. */
emilmont	80:8e73be2a2ac1	6886
emilmont	80:8e73be2a2ac1	6887	/* Bits 31..0 : UART baudrate. */
emilmont	80:8e73be2a2ac1	6888	#define UART_BAUDRATE_BAUDRATE_Pos (0UL) /!< Position of BAUDRATE field. /
emilmont	80:8e73be2a2ac1	6889	#define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /!< Bit mask of BAUDRATE field. /
emilmont	80:8e73be2a2ac1	6890	#define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /!< 1200 baud. /
emilmont	80:8e73be2a2ac1	6891	#define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /!< 2400 baud. /
emilmont	80:8e73be2a2ac1	6892	#define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /!< 4800 baud. /
emilmont	80:8e73be2a2ac1	6893	#define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /!< 9600 baud. /
emilmont	80:8e73be2a2ac1	6894	#define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /!< 14400 baud. /
emilmont	80:8e73be2a2ac1	6895	#define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /!< 19200 baud. /
emilmont	80:8e73be2a2ac1	6896	#define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /!< 28800 baud. /
emilmont	80:8e73be2a2ac1	6897	#define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /!< 38400 baud. /
emilmont	80:8e73be2a2ac1	6898	#define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /!< 57600 baud. /
emilmont	80:8e73be2a2ac1	6899	#define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /!< 76800 baud. /
emilmont	80:8e73be2a2ac1	6900	#define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /!< 115200 baud. /
emilmont	80:8e73be2a2ac1	6901	#define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /!< 230400 baud. /
emilmont	80:8e73be2a2ac1	6902	#define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /!< 250000 baud. /
emilmont	80:8e73be2a2ac1	6903	#define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /!< 460800 baud. /
emilmont	80:8e73be2a2ac1	6904	#define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /!< 921600 baud. /
emilmont	80:8e73be2a2ac1	6905	#define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /!< 1M baud. /
emilmont	80:8e73be2a2ac1	6906
emilmont	80:8e73be2a2ac1	6907	/* Register: UART_CONFIG */
emilmont	80:8e73be2a2ac1	6908	/* Description: Configuration of parity and hardware flow control register. */
emilmont	80:8e73be2a2ac1	6909
emilmont	80:8e73be2a2ac1	6910	/* Bits 3..1 : Include parity bit. */
emilmont	80:8e73be2a2ac1	6911	#define UART_CONFIG_PARITY_Pos (1UL) /!< Position of PARITY field. /
emilmont	80:8e73be2a2ac1	6912	#define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /!< Bit mask of PARITY field. /
emilmont	80:8e73be2a2ac1	6913	#define UART_CONFIG_PARITY_Excluded (0UL) /!< Parity bit excluded. /
emilmont	80:8e73be2a2ac1	6914	#define UART_CONFIG_PARITY_Included (7UL) /!< Parity bit included. /
emilmont	80:8e73be2a2ac1	6915
emilmont	80:8e73be2a2ac1	6916	/* Bit 0 : Hardware flow control. */
emilmont	80:8e73be2a2ac1	6917	#define UART_CONFIG_HWFC_Pos (0UL) /!< Position of HWFC field. /
emilmont	80:8e73be2a2ac1	6918	#define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /!< Bit mask of HWFC field. /
emilmont	80:8e73be2a2ac1	6919	#define UART_CONFIG_HWFC_Disabled (0UL) /!< Hardware flow control disabled. /
emilmont	80:8e73be2a2ac1	6920	#define UART_CONFIG_HWFC_Enabled (1UL) /!< Hardware flow control enabled. /
emilmont	80:8e73be2a2ac1	6921
emilmont	80:8e73be2a2ac1	6922	/* Register: UART_POWER */
emilmont	80:8e73be2a2ac1	6923	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	6924
emilmont	80:8e73be2a2ac1	6925	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	6926	#define UART_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	6927	#define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	6928	#define UART_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	6929	#define UART_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	6930
emilmont	80:8e73be2a2ac1	6931
emilmont	80:8e73be2a2ac1	6932	/* Peripheral: UICR */
emilmont	80:8e73be2a2ac1	6933	/* Description: User Information Configuration. */
emilmont	80:8e73be2a2ac1	6934
emilmont	80:8e73be2a2ac1	6935	/* Register: UICR_RBPCONF */
emilmont	80:8e73be2a2ac1	6936	/* Description: Readback protection configuration. */
emilmont	80:8e73be2a2ac1	6937
emilmont	80:8e73be2a2ac1	6938	/* Bits 15..8 : Readback protect all code in the device. */
emilmont	80:8e73be2a2ac1	6939	#define UICR_RBPCONF_PALL_Pos (8UL) /!< Position of PALL field. /
emilmont	80:8e73be2a2ac1	6940	#define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /!< Bit mask of PALL field. /
emilmont	80:8e73be2a2ac1	6941	#define UICR_RBPCONF_PALL_Disabled (0xFFUL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	6942	#define UICR_RBPCONF_PALL_Enabled (0x00UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	6943
emilmont	80:8e73be2a2ac1	6944	/* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
emilmont	80:8e73be2a2ac1	6945	#define UICR_RBPCONF_PR0_Pos (0UL) /!< Position of PR0 field. /
emilmont	80:8e73be2a2ac1	6946	#define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /!< Bit mask of PR0 field. /
emilmont	80:8e73be2a2ac1	6947	#define UICR_RBPCONF_PR0_Disabled (0xFFUL) /!< Disabled. /
emilmont	80:8e73be2a2ac1	6948	#define UICR_RBPCONF_PR0_Enabled (0x00UL) /!< Enabled. /
emilmont	80:8e73be2a2ac1	6949
emilmont	80:8e73be2a2ac1	6950	/* Register: UICR_XTALFREQ */
emilmont	80:8e73be2a2ac1	6951	/* Description: Reset value for CLOCK XTALFREQ register. */
emilmont	80:8e73be2a2ac1	6952
emilmont	80:8e73be2a2ac1	6953	/* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
emilmont	80:8e73be2a2ac1	6954	#define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /!< Position of XTALFREQ field. /
emilmont	80:8e73be2a2ac1	6955	#define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /!< Bit mask of XTALFREQ field. /
emilmont	80:8e73be2a2ac1	6956	#define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /!< 16MHz Xtal is used. /
emilmont	80:8e73be2a2ac1	6957	#define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /!< 32MHz Xtal is used. /
emilmont	80:8e73be2a2ac1	6958
emilmont	80:8e73be2a2ac1	6959	/* Register: UICR_FWID */
emilmont	80:8e73be2a2ac1	6960	/* Description: Firmware ID. */
emilmont	80:8e73be2a2ac1	6961
emilmont	80:8e73be2a2ac1	6962	/* Bits 15..0 : Identification number for the firmware loaded into the chip. */
emilmont	80:8e73be2a2ac1	6963	#define UICR_FWID_FWID_Pos (0UL) /!< Position of FWID field. /
emilmont	80:8e73be2a2ac1	6964	#define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /!< Bit mask of FWID field. /
emilmont	80:8e73be2a2ac1	6965
emilmont	80:8e73be2a2ac1	6966
emilmont	80:8e73be2a2ac1	6967	/* Peripheral: WDT */
emilmont	80:8e73be2a2ac1	6968	/* Description: Watchdog Timer. */
emilmont	80:8e73be2a2ac1	6969
emilmont	80:8e73be2a2ac1	6970	/* Register: WDT_INTENSET */
emilmont	80:8e73be2a2ac1	6971	/* Description: Interrupt enable set register. */
emilmont	80:8e73be2a2ac1	6972
emilmont	80:8e73be2a2ac1	6973	/* Bit 0 : Enable interrupt on TIMEOUT event. */
emilmont	80:8e73be2a2ac1	6974	#define WDT_INTENSET_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
emilmont	80:8e73be2a2ac1	6975	#define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
emilmont	80:8e73be2a2ac1	6976	#define WDT_INTENSET_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6977	#define WDT_INTENSET_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6978	#define WDT_INTENSET_TIMEOUT_Set (1UL) /!< Enable interrupt on write. /
emilmont	80:8e73be2a2ac1	6979
emilmont	80:8e73be2a2ac1	6980	/* Register: WDT_INTENCLR */
emilmont	80:8e73be2a2ac1	6981	/* Description: Interrupt enable clear register. */
emilmont	80:8e73be2a2ac1	6982
emilmont	80:8e73be2a2ac1	6983	/* Bit 0 : Disable interrupt on TIMEOUT event. */
emilmont	80:8e73be2a2ac1	6984	#define WDT_INTENCLR_TIMEOUT_Pos (0UL) /!< Position of TIMEOUT field. /
emilmont	80:8e73be2a2ac1	6985	#define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /!< Bit mask of TIMEOUT field. /
emilmont	80:8e73be2a2ac1	6986	#define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /!< Interrupt disabled. /
emilmont	80:8e73be2a2ac1	6987	#define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /!< Interrupt enabled. /
emilmont	80:8e73be2a2ac1	6988	#define WDT_INTENCLR_TIMEOUT_Clear (1UL) /!< Disable interrupt on write. /
emilmont	80:8e73be2a2ac1	6989
emilmont	80:8e73be2a2ac1	6990	/* Register: WDT_RUNSTATUS */
emilmont	80:8e73be2a2ac1	6991	/* Description: Watchdog running status. */
emilmont	80:8e73be2a2ac1	6992
emilmont	80:8e73be2a2ac1	6993	/* Bit 0 : Watchdog running status. */
emilmont	80:8e73be2a2ac1	6994	#define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /!< Position of RUNSTATUS field. /
emilmont	80:8e73be2a2ac1	6995	#define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /!< Bit mask of RUNSTATUS field. /
emilmont	80:8e73be2a2ac1	6996	#define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /!< Watchdog timer is not running. /
emilmont	80:8e73be2a2ac1	6997	#define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /!< Watchdog timer is running. /
emilmont	80:8e73be2a2ac1	6998
emilmont	80:8e73be2a2ac1	6999	/* Register: WDT_REQSTATUS */
emilmont	80:8e73be2a2ac1	7000	/* Description: Request status. */
emilmont	80:8e73be2a2ac1	7001
emilmont	80:8e73be2a2ac1	7002	/* Bit 7 : Request status for RR[7]. */
emilmont	80:8e73be2a2ac1	7003	#define WDT_REQSTATUS_RR7_Pos (7UL) /!< Position of RR7 field. /
emilmont	80:8e73be2a2ac1	7004	#define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /!< Bit mask of RR7 field. /
emilmont	80:8e73be2a2ac1	7005	#define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /!< RR[7] register is not enabled or has already requested reload. /
emilmont	80:8e73be2a2ac1	7006	#define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /!< RR[7] register is enabled and has not jet requested. /
emilmont	80:8e73be2a2ac1	7007
emilmont	80:8e73be2a2ac1	7008	/* Bit 6 : Request status for RR[6]. */
emilmont	80:8e73be2a2ac1	7009	#define WDT_REQSTATUS_RR6_Pos (6UL) /!< Position of RR6 field. /
emilmont	80:8e73be2a2ac1	7010	#define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /!< Bit mask of RR6 field. /
emilmont	80:8e73be2a2ac1	7011	#define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /!< RR[6] register is not enabled or has already requested reload. /
emilmont	80:8e73be2a2ac1	7012	#define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /!< RR[6] register is enabled and has not jet requested. /
emilmont	80:8e73be2a2ac1	7013
emilmont	80:8e73be2a2ac1	7014	/* Bit 5 : Request status for RR[5]. */
emilmont	80:8e73be2a2ac1	7015	#define WDT_REQSTATUS_RR5_Pos (5UL) /!< Position of RR5 field. /
emilmont	80:8e73be2a2ac1	7016	#define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /!< Bit mask of RR5 field. /
emilmont	80:8e73be2a2ac1	7017	#define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /!< RR[5] register is not enabled or has already requested reload. /
emilmont	80:8e73be2a2ac1	7018	#define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /!< RR[5] register is enabled and has not jet requested. /
emilmont	80:8e73be2a2ac1	7019
emilmont	80:8e73be2a2ac1	7020	/* Bit 4 : Request status for RR[4]. */
emilmont	80:8e73be2a2ac1	7021	#define WDT_REQSTATUS_RR4_Pos (4UL) /!< Position of RR4 field. /
emilmont	80:8e73be2a2ac1	7022	#define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /!< Bit mask of RR4 field. /
emilmont	80:8e73be2a2ac1	7023	#define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /!< RR[4] register is not enabled or has already requested reload. /
emilmont	80:8e73be2a2ac1	7024	#define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /!< RR[4] register is enabled and has not jet requested. /
emilmont	80:8e73be2a2ac1	7025
emilmont	80:8e73be2a2ac1	7026	/* Bit 3 : Request status for RR[3]. */
emilmont	80:8e73be2a2ac1	7027	#define WDT_REQSTATUS_RR3_Pos (3UL) /!< Position of RR3 field. /
emilmont	80:8e73be2a2ac1	7028	#define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /!< Bit mask of RR3 field. /
emilmont	80:8e73be2a2ac1	7029	#define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /!< RR[3] register is not enabled or has already requested reload. /
emilmont	80:8e73be2a2ac1	7030	#define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /!< RR[3] register is enabled and has not jet requested. /
emilmont	80:8e73be2a2ac1	7031
emilmont	80:8e73be2a2ac1	7032	/* Bit 2 : Request status for RR[2]. */
emilmont	80:8e73be2a2ac1	7033	#define WDT_REQSTATUS_RR2_Pos (2UL) /!< Position of RR2 field. /
emilmont	80:8e73be2a2ac1	7034	#define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /!< Bit mask of RR2 field. /
emilmont	80:8e73be2a2ac1	7035	#define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /!< RR[2] register is not enabled or has already requested reload. /
emilmont	80:8e73be2a2ac1	7036	#define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /!< RR[2] register is enabled and has not jet requested. /
emilmont	80:8e73be2a2ac1	7037
emilmont	80:8e73be2a2ac1	7038	/* Bit 1 : Request status for RR[1]. */
emilmont	80:8e73be2a2ac1	7039	#define WDT_REQSTATUS_RR1_Pos (1UL) /!< Position of RR1 field. /
emilmont	80:8e73be2a2ac1	7040	#define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /!< Bit mask of RR1 field. /
emilmont	80:8e73be2a2ac1	7041	#define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /!< RR[1] register is not enabled or has already requested reload. /
emilmont	80:8e73be2a2ac1	7042	#define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /!< RR[1] register is enabled and has not jet requested. /
emilmont	80:8e73be2a2ac1	7043
emilmont	80:8e73be2a2ac1	7044	/* Bit 0 : Request status for RR[0]. */
emilmont	80:8e73be2a2ac1	7045	#define WDT_REQSTATUS_RR0_Pos (0UL) /!< Position of RR0 field. /
emilmont	80:8e73be2a2ac1	7046	#define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /!< Bit mask of RR0 field. /
emilmont	80:8e73be2a2ac1	7047	#define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /!< RR[0] register is not enabled or has already requested reload. /
emilmont	80:8e73be2a2ac1	7048	#define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /!< RR[0] register is enabled and has not jet requested. /
emilmont	80:8e73be2a2ac1	7049
emilmont	80:8e73be2a2ac1	7050	/* Register: WDT_RREN */
emilmont	80:8e73be2a2ac1	7051	/* Description: Reload request enable. */
emilmont	80:8e73be2a2ac1	7052
emilmont	80:8e73be2a2ac1	7053	/* Bit 7 : Enable or disable RR[7] register. */
emilmont	80:8e73be2a2ac1	7054	#define WDT_RREN_RR7_Pos (7UL) /!< Position of RR7 field. /
emilmont	80:8e73be2a2ac1	7055	#define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /!< Bit mask of RR7 field. /
emilmont	80:8e73be2a2ac1	7056	#define WDT_RREN_RR7_Disabled (0UL) /!< RR[7] register is disabled. /
emilmont	80:8e73be2a2ac1	7057	#define WDT_RREN_RR7_Enabled (1UL) /!< RR[7] register is enabled. /
emilmont	80:8e73be2a2ac1	7058
emilmont	80:8e73be2a2ac1	7059	/* Bit 6 : Enable or disable RR[6] register. */
emilmont	80:8e73be2a2ac1	7060	#define WDT_RREN_RR6_Pos (6UL) /!< Position of RR6 field. /
emilmont	80:8e73be2a2ac1	7061	#define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /!< Bit mask of RR6 field. /
emilmont	80:8e73be2a2ac1	7062	#define WDT_RREN_RR6_Disabled (0UL) /!< RR[6] register is disabled. /
emilmont	80:8e73be2a2ac1	7063	#define WDT_RREN_RR6_Enabled (1UL) /!< RR[6] register is enabled. /
emilmont	80:8e73be2a2ac1	7064
emilmont	80:8e73be2a2ac1	7065	/* Bit 5 : Enable or disable RR[5] register. */
emilmont	80:8e73be2a2ac1	7066	#define WDT_RREN_RR5_Pos (5UL) /!< Position of RR5 field. /
emilmont	80:8e73be2a2ac1	7067	#define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /!< Bit mask of RR5 field. /
emilmont	80:8e73be2a2ac1	7068	#define WDT_RREN_RR5_Disabled (0UL) /!< RR[5] register is disabled. /
emilmont	80:8e73be2a2ac1	7069	#define WDT_RREN_RR5_Enabled (1UL) /!< RR[5] register is enabled. /
emilmont	80:8e73be2a2ac1	7070
emilmont	80:8e73be2a2ac1	7071	/* Bit 4 : Enable or disable RR[4] register. */
emilmont	80:8e73be2a2ac1	7072	#define WDT_RREN_RR4_Pos (4UL) /!< Position of RR4 field. /
emilmont	80:8e73be2a2ac1	7073	#define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /!< Bit mask of RR4 field. /
emilmont	80:8e73be2a2ac1	7074	#define WDT_RREN_RR4_Disabled (0UL) /!< RR[4] register is disabled. /
emilmont	80:8e73be2a2ac1	7075	#define WDT_RREN_RR4_Enabled (1UL) /!< RR[4] register is enabled. /
emilmont	80:8e73be2a2ac1	7076
emilmont	80:8e73be2a2ac1	7077	/* Bit 3 : Enable or disable RR[3] register. */
emilmont	80:8e73be2a2ac1	7078	#define WDT_RREN_RR3_Pos (3UL) /!< Position of RR3 field. /
emilmont	80:8e73be2a2ac1	7079	#define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /!< Bit mask of RR3 field. /
emilmont	80:8e73be2a2ac1	7080	#define WDT_RREN_RR3_Disabled (0UL) /!< RR[3] register is disabled. /
emilmont	80:8e73be2a2ac1	7081	#define WDT_RREN_RR3_Enabled (1UL) /!< RR[3] register is enabled. /
emilmont	80:8e73be2a2ac1	7082
emilmont	80:8e73be2a2ac1	7083	/* Bit 2 : Enable or disable RR[2] register. */
emilmont	80:8e73be2a2ac1	7084	#define WDT_RREN_RR2_Pos (2UL) /!< Position of RR2 field. /
emilmont	80:8e73be2a2ac1	7085	#define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /!< Bit mask of RR2 field. /
emilmont	80:8e73be2a2ac1	7086	#define WDT_RREN_RR2_Disabled (0UL) /!< RR[2] register is disabled. /
emilmont	80:8e73be2a2ac1	7087	#define WDT_RREN_RR2_Enabled (1UL) /!< RR[2] register is enabled. /
emilmont	80:8e73be2a2ac1	7088
emilmont	80:8e73be2a2ac1	7089	/* Bit 1 : Enable or disable RR[1] register. */
emilmont	80:8e73be2a2ac1	7090	#define WDT_RREN_RR1_Pos (1UL) /!< Position of RR1 field. /
emilmont	80:8e73be2a2ac1	7091	#define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /!< Bit mask of RR1 field. /
emilmont	80:8e73be2a2ac1	7092	#define WDT_RREN_RR1_Disabled (0UL) /!< RR[1] register is disabled. /
emilmont	80:8e73be2a2ac1	7093	#define WDT_RREN_RR1_Enabled (1UL) /!< RR[1] register is enabled. /
emilmont	80:8e73be2a2ac1	7094
emilmont	80:8e73be2a2ac1	7095	/* Bit 0 : Enable or disable RR[0] register. */
emilmont	80:8e73be2a2ac1	7096	#define WDT_RREN_RR0_Pos (0UL) /!< Position of RR0 field. /
emilmont	80:8e73be2a2ac1	7097	#define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /!< Bit mask of RR0 field. /
emilmont	80:8e73be2a2ac1	7098	#define WDT_RREN_RR0_Disabled (0UL) /!< RR[0] register is disabled. /
emilmont	80:8e73be2a2ac1	7099	#define WDT_RREN_RR0_Enabled (1UL) /!< RR[0] register is enabled. /
emilmont	80:8e73be2a2ac1	7100
emilmont	80:8e73be2a2ac1	7101	/* Register: WDT_CONFIG */
emilmont	80:8e73be2a2ac1	7102	/* Description: Configuration register. */
emilmont	80:8e73be2a2ac1	7103
emilmont	80:8e73be2a2ac1	7104	/* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
emilmont	80:8e73be2a2ac1	7105	#define WDT_CONFIG_HALT_Pos (3UL) /!< Position of HALT field. /
emilmont	80:8e73be2a2ac1	7106	#define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /!< Bit mask of HALT field. /
emilmont	80:8e73be2a2ac1	7107	#define WDT_CONFIG_HALT_Pause (0UL) /!< Pause watchdog while the CPU is halted by the debugger. /
emilmont	80:8e73be2a2ac1	7108	#define WDT_CONFIG_HALT_Run (1UL) /!< Do not pause watchdog while the CPU is halted by the debugger. /
emilmont	80:8e73be2a2ac1	7109
emilmont	80:8e73be2a2ac1	7110	/* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
emilmont	80:8e73be2a2ac1	7111	#define WDT_CONFIG_SLEEP_Pos (0UL) /!< Position of SLEEP field. /
emilmont	80:8e73be2a2ac1	7112	#define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /!< Bit mask of SLEEP field. /
emilmont	80:8e73be2a2ac1	7113	#define WDT_CONFIG_SLEEP_Pause (0UL) /!< Pause watchdog while the CPU is asleep. /
emilmont	80:8e73be2a2ac1	7114	#define WDT_CONFIG_SLEEP_Run (1UL) /!< Do not pause watchdog while the CPU is asleep. /
emilmont	80:8e73be2a2ac1	7115
emilmont	80:8e73be2a2ac1	7116	/* Register: WDT_RR */
emilmont	80:8e73be2a2ac1	7117	/* Description: Reload requests registers. */
emilmont	80:8e73be2a2ac1	7118
emilmont	80:8e73be2a2ac1	7119	/* Bits 31..0 : Reload register. */
emilmont	80:8e73be2a2ac1	7120	#define WDT_RR_RR_Pos (0UL) /!< Position of RR field. /
emilmont	80:8e73be2a2ac1	7121	#define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /!< Bit mask of RR field. /
emilmont	80:8e73be2a2ac1	7122	#define WDT_RR_RR_Reload (0x6E524635UL) /!< Value to request a reload of the watchdog timer. /
emilmont	80:8e73be2a2ac1	7123
emilmont	80:8e73be2a2ac1	7124	/* Register: WDT_POWER */
emilmont	80:8e73be2a2ac1	7125	/* Description: Peripheral power control. */
emilmont	80:8e73be2a2ac1	7126
emilmont	80:8e73be2a2ac1	7127	/* Bit 0 : Peripheral power control. */
emilmont	80:8e73be2a2ac1	7128	#define WDT_POWER_POWER_Pos (0UL) /!< Position of POWER field. /
emilmont	80:8e73be2a2ac1	7129	#define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /!< Bit mask of POWER field. /
emilmont	80:8e73be2a2ac1	7130	#define WDT_POWER_POWER_Disabled (0UL) /!< Module power disabled. /
emilmont	80:8e73be2a2ac1	7131	#define WDT_POWER_POWER_Enabled (1UL) /!< Module power enabled. /
emilmont	80:8e73be2a2ac1	7132
emilmont	80:8e73be2a2ac1	7133
emilmont	80:8e73be2a2ac1	7134	/lint --flb "Leave library region" /
emilmont	80:8e73be2a2ac1	7135	#endif

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Type:	Library
Created:	05 Apr 2016
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TARGET_NRF51822/nrf51_bitfields.h@97:433970e64889, 2015-04-14 (annotated)

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