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TARGET_RBLAB_BLENANO/nrf51_bitfields.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
91:031413cf7a89
Child:
97:433970e64889
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 91:031413cf7a89 1 /* Copyright (c) 2009 Nordic Semiconductor. All Rights Reserved.
Kojto 91:031413cf7a89 2 *
Kojto 91:031413cf7a89 3 * The information contained herein is property of Nordic Semiconductor ASA.
Kojto 91:031413cf7a89 4 * Terms and conditions of usage are described in detail in NORDIC
Kojto 91:031413cf7a89 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
Kojto 91:031413cf7a89 6 *
Kojto 91:031413cf7a89 7 * Licensees are granted free, non-transferable use of the information. NO
Kojto 91:031413cf7a89 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
Kojto 91:031413cf7a89 9 * the file.
Kojto 91:031413cf7a89 10 *
Kojto 91:031413cf7a89 11 */
Kojto 91:031413cf7a89 12
Kojto 91:031413cf7a89 13
Kojto 91:031413cf7a89 14 #ifndef __NRF51_BITS_H
Kojto 91:031413cf7a89 15 #define __NRF51_BITS_H
Kojto 91:031413cf7a89 16
Kojto 91:031413cf7a89 17 /*lint ++flb "Enter library region */
Kojto 91:031413cf7a89 18
Kojto 91:031413cf7a89 19 //#include <core_cm0.h>
Kojto 91:031413cf7a89 20
Kojto 91:031413cf7a89 21 /* Peripheral: AAR */
Kojto 91:031413cf7a89 22 /* Description: Accelerated Address Resolver. */
Kojto 91:031413cf7a89 23
Kojto 91:031413cf7a89 24 /* Register: AAR_INTENSET */
Kojto 91:031413cf7a89 25 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 26
Kojto 91:031413cf7a89 27 /* Bit 2 : Enable interrupt on NOTRESOLVED event. */
Kojto 91:031413cf7a89 28 #define AAR_INTENSET_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
Kojto 91:031413cf7a89 29 #define AAR_INTENSET_NOTRESOLVED_Msk (0x1UL << AAR_INTENSET_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
Kojto 91:031413cf7a89 30 #define AAR_INTENSET_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 31 #define AAR_INTENSET_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 32 #define AAR_INTENSET_NOTRESOLVED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 33
Kojto 91:031413cf7a89 34 /* Bit 1 : Enable interrupt on RESOLVED event. */
Kojto 91:031413cf7a89 35 #define AAR_INTENSET_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
Kojto 91:031413cf7a89 36 #define AAR_INTENSET_RESOLVED_Msk (0x1UL << AAR_INTENSET_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
Kojto 91:031413cf7a89 37 #define AAR_INTENSET_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 38 #define AAR_INTENSET_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 39 #define AAR_INTENSET_RESOLVED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 40
Kojto 91:031413cf7a89 41 /* Bit 0 : Enable interrupt on END event. */
Kojto 91:031413cf7a89 42 #define AAR_INTENSET_END_Pos (0UL) /*!< Position of END field. */
Kojto 91:031413cf7a89 43 #define AAR_INTENSET_END_Msk (0x1UL << AAR_INTENSET_END_Pos) /*!< Bit mask of END field. */
Kojto 91:031413cf7a89 44 #define AAR_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 45 #define AAR_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 46 #define AAR_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 47
Kojto 91:031413cf7a89 48 /* Register: AAR_INTENCLR */
Kojto 91:031413cf7a89 49 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 50
Kojto 91:031413cf7a89 51 /* Bit 2 : Disable interrupt on NOTRESOLVED event. */
Kojto 91:031413cf7a89 52 #define AAR_INTENCLR_NOTRESOLVED_Pos (2UL) /*!< Position of NOTRESOLVED field. */
Kojto 91:031413cf7a89 53 #define AAR_INTENCLR_NOTRESOLVED_Msk (0x1UL << AAR_INTENCLR_NOTRESOLVED_Pos) /*!< Bit mask of NOTRESOLVED field. */
Kojto 91:031413cf7a89 54 #define AAR_INTENCLR_NOTRESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 55 #define AAR_INTENCLR_NOTRESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 56 #define AAR_INTENCLR_NOTRESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 57
Kojto 91:031413cf7a89 58 /* Bit 1 : Disable interrupt on RESOLVED event. */
Kojto 91:031413cf7a89 59 #define AAR_INTENCLR_RESOLVED_Pos (1UL) /*!< Position of RESOLVED field. */
Kojto 91:031413cf7a89 60 #define AAR_INTENCLR_RESOLVED_Msk (0x1UL << AAR_INTENCLR_RESOLVED_Pos) /*!< Bit mask of RESOLVED field. */
Kojto 91:031413cf7a89 61 #define AAR_INTENCLR_RESOLVED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 62 #define AAR_INTENCLR_RESOLVED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 63 #define AAR_INTENCLR_RESOLVED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 64
Kojto 91:031413cf7a89 65 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
Kojto 91:031413cf7a89 66 #define AAR_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
Kojto 91:031413cf7a89 67 #define AAR_INTENCLR_END_Msk (0x1UL << AAR_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Kojto 91:031413cf7a89 68 #define AAR_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 69 #define AAR_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 70 #define AAR_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 71
Kojto 91:031413cf7a89 72 /* Register: AAR_STATUS */
Kojto 91:031413cf7a89 73 /* Description: Resolution status. */
Kojto 91:031413cf7a89 74
Kojto 91:031413cf7a89 75 /* Bits 3..0 : The IRK used last time an address was resolved. */
Kojto 91:031413cf7a89 76 #define AAR_STATUS_STATUS_Pos (0UL) /*!< Position of STATUS field. */
Kojto 91:031413cf7a89 77 #define AAR_STATUS_STATUS_Msk (0xFUL << AAR_STATUS_STATUS_Pos) /*!< Bit mask of STATUS field. */
Kojto 91:031413cf7a89 78
Kojto 91:031413cf7a89 79 /* Register: AAR_ENABLE */
Kojto 91:031413cf7a89 80 /* Description: Enable AAR. */
Kojto 91:031413cf7a89 81
Kojto 91:031413cf7a89 82 /* Bits 1..0 : Enable AAR. */
Kojto 91:031413cf7a89 83 #define AAR_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 84 #define AAR_ENABLE_ENABLE_Msk (0x3UL << AAR_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 85 #define AAR_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled AAR. */
Kojto 91:031413cf7a89 86 #define AAR_ENABLE_ENABLE_Enabled (0x03UL) /*!< Enable AAR. */
Kojto 91:031413cf7a89 87
Kojto 91:031413cf7a89 88 /* Register: AAR_NIRK */
Kojto 91:031413cf7a89 89 /* Description: Number of Identity root Keys in the IRK data structure. */
Kojto 91:031413cf7a89 90
Kojto 91:031413cf7a89 91 /* Bits 4..0 : Number of Identity root Keys in the IRK data structure. */
Kojto 91:031413cf7a89 92 #define AAR_NIRK_NIRK_Pos (0UL) /*!< Position of NIRK field. */
Kojto 91:031413cf7a89 93 #define AAR_NIRK_NIRK_Msk (0x1FUL << AAR_NIRK_NIRK_Pos) /*!< Bit mask of NIRK field. */
Kojto 91:031413cf7a89 94
Kojto 91:031413cf7a89 95 /* Register: AAR_POWER */
Kojto 91:031413cf7a89 96 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 97
Kojto 91:031413cf7a89 98 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 99 #define AAR_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 100 #define AAR_POWER_POWER_Msk (0x1UL << AAR_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 101 #define AAR_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 102 #define AAR_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 103
Kojto 91:031413cf7a89 104
Kojto 91:031413cf7a89 105 /* Peripheral: ADC */
Kojto 91:031413cf7a89 106 /* Description: Analog to digital converter. */
Kojto 91:031413cf7a89 107
Kojto 91:031413cf7a89 108 /* Register: ADC_INTENSET */
Kojto 91:031413cf7a89 109 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 110
Kojto 91:031413cf7a89 111 /* Bit 0 : Enable interrupt on END event. */
Kojto 91:031413cf7a89 112 #define ADC_INTENSET_END_Pos (0UL) /*!< Position of END field. */
Kojto 91:031413cf7a89 113 #define ADC_INTENSET_END_Msk (0x1UL << ADC_INTENSET_END_Pos) /*!< Bit mask of END field. */
Kojto 91:031413cf7a89 114 #define ADC_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 115 #define ADC_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 116 #define ADC_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 117
Kojto 91:031413cf7a89 118 /* Register: ADC_INTENCLR */
Kojto 91:031413cf7a89 119 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 120
Kojto 91:031413cf7a89 121 /* Bit 0 : Disable interrupt on END event. */
Kojto 91:031413cf7a89 122 #define ADC_INTENCLR_END_Pos (0UL) /*!< Position of END field. */
Kojto 91:031413cf7a89 123 #define ADC_INTENCLR_END_Msk (0x1UL << ADC_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Kojto 91:031413cf7a89 124 #define ADC_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 125 #define ADC_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 126 #define ADC_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 127
Kojto 91:031413cf7a89 128 /* Register: ADC_BUSY */
Kojto 91:031413cf7a89 129 /* Description: ADC busy register. */
Kojto 91:031413cf7a89 130
Kojto 91:031413cf7a89 131 /* Bit 0 : ADC busy register. */
Kojto 91:031413cf7a89 132 #define ADC_BUSY_BUSY_Pos (0UL) /*!< Position of BUSY field. */
Kojto 91:031413cf7a89 133 #define ADC_BUSY_BUSY_Msk (0x1UL << ADC_BUSY_BUSY_Pos) /*!< Bit mask of BUSY field. */
Kojto 91:031413cf7a89 134 #define ADC_BUSY_BUSY_Ready (0UL) /*!< No ongoing ADC conversion is taking place. ADC is ready. */
Kojto 91:031413cf7a89 135 #define ADC_BUSY_BUSY_Busy (1UL) /*!< An ADC conversion is taking place. ADC is busy. */
Kojto 91:031413cf7a89 136
Kojto 91:031413cf7a89 137 /* Register: ADC_ENABLE */
Kojto 91:031413cf7a89 138 /* Description: ADC enable. */
Kojto 91:031413cf7a89 139
Kojto 91:031413cf7a89 140 /* Bits 1..0 : ADC enable. */
Kojto 91:031413cf7a89 141 #define ADC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 142 #define ADC_ENABLE_ENABLE_Msk (0x3UL << ADC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 143 #define ADC_ENABLE_ENABLE_Disabled (0x00UL) /*!< ADC is disabled. */
Kojto 91:031413cf7a89 144 #define ADC_ENABLE_ENABLE_Enabled (0x01UL) /*!< ADC is enabled. If an analog input pin is selected as source of the conversion, the selected pin is configured as an analog input. */
Kojto 91:031413cf7a89 145
Kojto 91:031413cf7a89 146 /* Register: ADC_CONFIG */
Kojto 91:031413cf7a89 147 /* Description: ADC configuration register. */
Kojto 91:031413cf7a89 148
Kojto 91:031413cf7a89 149 /* Bits 17..16 : ADC external reference pin selection. */
Kojto 91:031413cf7a89 150 #define ADC_CONFIG_EXTREFSEL_Pos (16UL) /*!< Position of EXTREFSEL field. */
Kojto 91:031413cf7a89 151 #define ADC_CONFIG_EXTREFSEL_Msk (0x3UL << ADC_CONFIG_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
Kojto 91:031413cf7a89 152 #define ADC_CONFIG_EXTREFSEL_None (0UL) /*!< Analog external reference inputs disabled. */
Kojto 91:031413cf7a89 153 #define ADC_CONFIG_EXTREFSEL_AnalogReference0 (1UL) /*!< Use analog reference 0 as reference. */
Kojto 91:031413cf7a89 154 #define ADC_CONFIG_EXTREFSEL_AnalogReference1 (2UL) /*!< Use analog reference 1 as reference. */
Kojto 91:031413cf7a89 155
Kojto 91:031413cf7a89 156 /* Bits 15..8 : ADC analog pin selection. */
Kojto 91:031413cf7a89 157 #define ADC_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
Kojto 91:031413cf7a89 158 #define ADC_CONFIG_PSEL_Msk (0xFFUL << ADC_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
Kojto 91:031413cf7a89 159 #define ADC_CONFIG_PSEL_Disabled (0UL) /*!< Analog input pins disabled. */
Kojto 91:031413cf7a89 160 #define ADC_CONFIG_PSEL_AnalogInput0 (1UL) /*!< Use analog input 0 as analog input. */
Kojto 91:031413cf7a89 161 #define ADC_CONFIG_PSEL_AnalogInput1 (2UL) /*!< Use analog input 1 as analog input. */
Kojto 91:031413cf7a89 162 #define ADC_CONFIG_PSEL_AnalogInput2 (4UL) /*!< Use analog input 2 as analog input. */
Kojto 91:031413cf7a89 163 #define ADC_CONFIG_PSEL_AnalogInput3 (8UL) /*!< Use analog input 3 as analog input. */
Kojto 91:031413cf7a89 164 #define ADC_CONFIG_PSEL_AnalogInput4 (16UL) /*!< Use analog input 4 as analog input. */
Kojto 91:031413cf7a89 165 #define ADC_CONFIG_PSEL_AnalogInput5 (32UL) /*!< Use analog input 5 as analog input. */
Kojto 91:031413cf7a89 166 #define ADC_CONFIG_PSEL_AnalogInput6 (64UL) /*!< Use analog input 6 as analog input. */
Kojto 91:031413cf7a89 167 #define ADC_CONFIG_PSEL_AnalogInput7 (128UL) /*!< Use analog input 7 as analog input. */
Kojto 91:031413cf7a89 168
Kojto 91:031413cf7a89 169 /* Bits 6..5 : ADC reference selection. */
Kojto 91:031413cf7a89 170 #define ADC_CONFIG_REFSEL_Pos (5UL) /*!< Position of REFSEL field. */
Kojto 91:031413cf7a89 171 #define ADC_CONFIG_REFSEL_Msk (0x3UL << ADC_CONFIG_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
Kojto 91:031413cf7a89 172 #define ADC_CONFIG_REFSEL_VBG (0x00UL) /*!< Use internal 1.2V bandgap voltage as reference for conversion. */
Kojto 91:031413cf7a89 173 #define ADC_CONFIG_REFSEL_External (0x01UL) /*!< Use external source configured by EXTREFSEL as reference for conversion. */
Kojto 91:031413cf7a89 174 #define ADC_CONFIG_REFSEL_SupplyOneHalfPrescaling (0x02UL) /*!< Use supply voltage with 1/2 prescaling as reference for conversion. Only usable when supply voltage is between 1.7V and 2.6V. */
Kojto 91:031413cf7a89 175 #define ADC_CONFIG_REFSEL_SupplyOneThirdPrescaling (0x03UL) /*!< Use supply voltage with 1/3 prescaling as reference for conversion. Only usable when supply voltage is between 2.5V and 3.6V. */
Kojto 91:031413cf7a89 176
Kojto 91:031413cf7a89 177 /* Bits 4..2 : ADC input selection. */
Kojto 91:031413cf7a89 178 #define ADC_CONFIG_INPSEL_Pos (2UL) /*!< Position of INPSEL field. */
Kojto 91:031413cf7a89 179 #define ADC_CONFIG_INPSEL_Msk (0x7UL << ADC_CONFIG_INPSEL_Pos) /*!< Bit mask of INPSEL field. */
Kojto 91:031413cf7a89 180 #define ADC_CONFIG_INPSEL_AnalogInputNoPrescaling (0x00UL) /*!< Analog input specified by PSEL with no prescaling used as input for the conversion. */
Kojto 91:031413cf7a89 181 #define ADC_CONFIG_INPSEL_AnalogInputTwoThirdsPrescaling (0x01UL) /*!< Analog input specified by PSEL with 2/3 prescaling used as input for the conversion. */
Kojto 91:031413cf7a89 182 #define ADC_CONFIG_INPSEL_AnalogInputOneThirdPrescaling (0x02UL) /*!< Analog input specified by PSEL with 1/3 prescaling used as input for the conversion. */
Kojto 91:031413cf7a89 183 #define ADC_CONFIG_INPSEL_SupplyTwoThirdsPrescaling (0x05UL) /*!< Supply voltage with 2/3 prescaling used as input for the conversion. */
Kojto 91:031413cf7a89 184 #define ADC_CONFIG_INPSEL_SupplyOneThirdPrescaling (0x06UL) /*!< Supply voltage with 1/3 prescaling used as input for the conversion. */
Kojto 91:031413cf7a89 185
Kojto 91:031413cf7a89 186 /* Bits 1..0 : ADC resolution. */
Kojto 91:031413cf7a89 187 #define ADC_CONFIG_RES_Pos (0UL) /*!< Position of RES field. */
Kojto 91:031413cf7a89 188 #define ADC_CONFIG_RES_Msk (0x3UL << ADC_CONFIG_RES_Pos) /*!< Bit mask of RES field. */
Kojto 91:031413cf7a89 189 #define ADC_CONFIG_RES_8bit (0x00UL) /*!< 8bit ADC resolution. */
Kojto 91:031413cf7a89 190 #define ADC_CONFIG_RES_9bit (0x01UL) /*!< 9bit ADC resolution. */
Kojto 91:031413cf7a89 191 #define ADC_CONFIG_RES_10bit (0x02UL) /*!< 10bit ADC resolution. */
Kojto 91:031413cf7a89 192
Kojto 91:031413cf7a89 193 /* Register: ADC_RESULT */
Kojto 91:031413cf7a89 194 /* Description: Result of ADC conversion. */
Kojto 91:031413cf7a89 195
Kojto 91:031413cf7a89 196 /* Bits 9..0 : Result of ADC conversion. */
Kojto 91:031413cf7a89 197 #define ADC_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
Kojto 91:031413cf7a89 198 #define ADC_RESULT_RESULT_Msk (0x3FFUL << ADC_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
Kojto 91:031413cf7a89 199
Kojto 91:031413cf7a89 200 /* Register: ADC_POWER */
Kojto 91:031413cf7a89 201 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 202
Kojto 91:031413cf7a89 203 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 204 #define ADC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 205 #define ADC_POWER_POWER_Msk (0x1UL << ADC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 206 #define ADC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 207 #define ADC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 208
Kojto 91:031413cf7a89 209
Kojto 91:031413cf7a89 210 /* Peripheral: AMLI */
Kojto 91:031413cf7a89 211 /* Description: AHB Multi-Layer Interface. */
Kojto 91:031413cf7a89 212
Kojto 91:031413cf7a89 213 /* Register: AMLI_RAMPRI_CPU0 */
Kojto 91:031413cf7a89 214 /* Description: Configurable priority configuration register for CPU0. */
Kojto 91:031413cf7a89 215
Kojto 91:031413cf7a89 216 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 91:031413cf7a89 217 #define AMLI_RAMPRI_CPU0_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 91:031413cf7a89 218 #define AMLI_RAMPRI_CPU0_RAM3_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 91:031413cf7a89 219
Kojto 91:031413cf7a89 220 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 91:031413cf7a89 221 #define AMLI_RAMPRI_CPU0_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 91:031413cf7a89 222 #define AMLI_RAMPRI_CPU0_RAM2_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 91:031413cf7a89 223
Kojto 91:031413cf7a89 224 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 91:031413cf7a89 225 #define AMLI_RAMPRI_CPU0_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 91:031413cf7a89 226 #define AMLI_RAMPRI_CPU0_RAM1_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 91:031413cf7a89 227
Kojto 91:031413cf7a89 228 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 91:031413cf7a89 229 #define AMLI_RAMPRI_CPU0_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 91:031413cf7a89 230 #define AMLI_RAMPRI_CPU0_RAM0_Msk (0xFUL << AMLI_RAMPRI_CPU0_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 91:031413cf7a89 231
Kojto 91:031413cf7a89 232 /* Register: AMLI_RAMPRI_SPIS1 */
Kojto 91:031413cf7a89 233 /* Description: Configurable priority configuration register for SPIS1. */
Kojto 91:031413cf7a89 234
Kojto 91:031413cf7a89 235 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 91:031413cf7a89 236 #define AMLI_RAMPRI_SPIS1_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 91:031413cf7a89 237 #define AMLI_RAMPRI_SPIS1_RAM3_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 91:031413cf7a89 238
Kojto 91:031413cf7a89 239 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 91:031413cf7a89 240 #define AMLI_RAMPRI_SPIS1_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 91:031413cf7a89 241 #define AMLI_RAMPRI_SPIS1_RAM2_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 91:031413cf7a89 242
Kojto 91:031413cf7a89 243 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 91:031413cf7a89 244 #define AMLI_RAMPRI_SPIS1_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 91:031413cf7a89 245 #define AMLI_RAMPRI_SPIS1_RAM1_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 91:031413cf7a89 246
Kojto 91:031413cf7a89 247 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 91:031413cf7a89 248 #define AMLI_RAMPRI_SPIS1_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 91:031413cf7a89 249 #define AMLI_RAMPRI_SPIS1_RAM0_Msk (0xFUL << AMLI_RAMPRI_SPIS1_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 91:031413cf7a89 250
Kojto 91:031413cf7a89 251 /* Register: AMLI_RAMPRI_RADIO */
Kojto 91:031413cf7a89 252 /* Description: Configurable priority configuration register for RADIO. */
Kojto 91:031413cf7a89 253
Kojto 91:031413cf7a89 254 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 91:031413cf7a89 255 #define AMLI_RAMPRI_RADIO_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 91:031413cf7a89 256 #define AMLI_RAMPRI_RADIO_RAM3_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 91:031413cf7a89 257
Kojto 91:031413cf7a89 258 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 91:031413cf7a89 259 #define AMLI_RAMPRI_RADIO_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 91:031413cf7a89 260 #define AMLI_RAMPRI_RADIO_RAM2_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 91:031413cf7a89 261
Kojto 91:031413cf7a89 262 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 91:031413cf7a89 263 #define AMLI_RAMPRI_RADIO_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 91:031413cf7a89 264 #define AMLI_RAMPRI_RADIO_RAM1_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 91:031413cf7a89 265
Kojto 91:031413cf7a89 266 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 91:031413cf7a89 267 #define AMLI_RAMPRI_RADIO_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 91:031413cf7a89 268 #define AMLI_RAMPRI_RADIO_RAM0_Msk (0xFUL << AMLI_RAMPRI_RADIO_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 91:031413cf7a89 269
Kojto 91:031413cf7a89 270 /* Register: AMLI_RAMPRI_ECB */
Kojto 91:031413cf7a89 271 /* Description: Configurable priority configuration register for ECB. */
Kojto 91:031413cf7a89 272
Kojto 91:031413cf7a89 273 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 91:031413cf7a89 274 #define AMLI_RAMPRI_ECB_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 91:031413cf7a89 275 #define AMLI_RAMPRI_ECB_RAM3_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 91:031413cf7a89 276
Kojto 91:031413cf7a89 277 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 91:031413cf7a89 278 #define AMLI_RAMPRI_ECB_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 91:031413cf7a89 279 #define AMLI_RAMPRI_ECB_RAM2_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 91:031413cf7a89 280
Kojto 91:031413cf7a89 281 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 91:031413cf7a89 282 #define AMLI_RAMPRI_ECB_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 91:031413cf7a89 283 #define AMLI_RAMPRI_ECB_RAM1_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 91:031413cf7a89 284
Kojto 91:031413cf7a89 285 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 91:031413cf7a89 286 #define AMLI_RAMPRI_ECB_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 91:031413cf7a89 287 #define AMLI_RAMPRI_ECB_RAM0_Msk (0xFUL << AMLI_RAMPRI_ECB_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 91:031413cf7a89 288
Kojto 91:031413cf7a89 289 /* Register: AMLI_RAMPRI_CCM */
Kojto 91:031413cf7a89 290 /* Description: Configurable priority configuration register for CCM. */
Kojto 91:031413cf7a89 291
Kojto 91:031413cf7a89 292 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 91:031413cf7a89 293 #define AMLI_RAMPRI_CCM_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 91:031413cf7a89 294 #define AMLI_RAMPRI_CCM_RAM3_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 91:031413cf7a89 295
Kojto 91:031413cf7a89 296 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 91:031413cf7a89 297 #define AMLI_RAMPRI_CCM_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 91:031413cf7a89 298 #define AMLI_RAMPRI_CCM_RAM2_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 91:031413cf7a89 299
Kojto 91:031413cf7a89 300 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 91:031413cf7a89 301 #define AMLI_RAMPRI_CCM_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 91:031413cf7a89 302 #define AMLI_RAMPRI_CCM_RAM1_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 91:031413cf7a89 303
Kojto 91:031413cf7a89 304 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 91:031413cf7a89 305 #define AMLI_RAMPRI_CCM_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 91:031413cf7a89 306 #define AMLI_RAMPRI_CCM_RAM0_Msk (0xFUL << AMLI_RAMPRI_CCM_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 91:031413cf7a89 307
Kojto 91:031413cf7a89 308 /* Register: AMLI_RAMPRI_AAR */
Kojto 91:031413cf7a89 309 /* Description: Configurable priority configuration register for AAR. */
Kojto 91:031413cf7a89 310
Kojto 91:031413cf7a89 311 /* Bits 15..12 : Configuration field for RAM block 3. */
Kojto 91:031413cf7a89 312 #define AMLI_RAMPRI_AAR_RAM3_Pos (12UL) /*!< Position of RAM3 field. */
Kojto 91:031413cf7a89 313 #define AMLI_RAMPRI_AAR_RAM3_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM3_Pos) /*!< Bit mask of RAM3 field. */
Kojto 91:031413cf7a89 314
Kojto 91:031413cf7a89 315 /* Bits 11..8 : Configuration field for RAM block 2. */
Kojto 91:031413cf7a89 316 #define AMLI_RAMPRI_AAR_RAM2_Pos (8UL) /*!< Position of RAM2 field. */
Kojto 91:031413cf7a89 317 #define AMLI_RAMPRI_AAR_RAM2_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM2_Pos) /*!< Bit mask of RAM2 field. */
Kojto 91:031413cf7a89 318
Kojto 91:031413cf7a89 319 /* Bits 7..4 : Configuration field for RAM block 1. */
Kojto 91:031413cf7a89 320 #define AMLI_RAMPRI_AAR_RAM1_Pos (4UL) /*!< Position of RAM1 field. */
Kojto 91:031413cf7a89 321 #define AMLI_RAMPRI_AAR_RAM1_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM1_Pos) /*!< Bit mask of RAM1 field. */
Kojto 91:031413cf7a89 322
Kojto 91:031413cf7a89 323 /* Bits 3..0 : Configuration field for RAM block 0. */
Kojto 91:031413cf7a89 324 #define AMLI_RAMPRI_AAR_RAM0_Pos (0UL) /*!< Position of RAM0 field. */
Kojto 91:031413cf7a89 325 #define AMLI_RAMPRI_AAR_RAM0_Msk (0xFUL << AMLI_RAMPRI_AAR_RAM0_Pos) /*!< Bit mask of RAM0 field. */
Kojto 91:031413cf7a89 326
Kojto 91:031413cf7a89 327 /* Peripheral: CCM */
Kojto 91:031413cf7a89 328 /* Description: AES CCM Mode Encryption. */
Kojto 91:031413cf7a89 329
Kojto 91:031413cf7a89 330 /* Register: CCM_SHORTS */
Kojto 91:031413cf7a89 331 /* Description: Shortcut for the CCM. */
Kojto 91:031413cf7a89 332
Kojto 91:031413cf7a89 333 /* Bit 0 : Short-cut between ENDKSGEN event and CRYPT task. */
Kojto 91:031413cf7a89 334 #define CCM_SHORTS_ENDKSGEN_CRYPT_Pos (0UL) /*!< Position of ENDKSGEN_CRYPT field. */
Kojto 91:031413cf7a89 335 #define CCM_SHORTS_ENDKSGEN_CRYPT_Msk (0x1UL << CCM_SHORTS_ENDKSGEN_CRYPT_Pos) /*!< Bit mask of ENDKSGEN_CRYPT field. */
Kojto 91:031413cf7a89 336 #define CCM_SHORTS_ENDKSGEN_CRYPT_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 337 #define CCM_SHORTS_ENDKSGEN_CRYPT_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 338
Kojto 91:031413cf7a89 339 /* Register: CCM_INTENSET */
Kojto 91:031413cf7a89 340 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 341
Kojto 91:031413cf7a89 342 /* Bit 2 : Enable interrupt on ERROR event. */
Kojto 91:031413cf7a89 343 #define CCM_INTENSET_ERROR_Pos (2UL) /*!< Position of ERROR field. */
Kojto 91:031413cf7a89 344 #define CCM_INTENSET_ERROR_Msk (0x1UL << CCM_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 91:031413cf7a89 345 #define CCM_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 346 #define CCM_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 347 #define CCM_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 348
Kojto 91:031413cf7a89 349 /* Bit 1 : Enable interrupt on ENDCRYPT event. */
Kojto 91:031413cf7a89 350 #define CCM_INTENSET_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
Kojto 91:031413cf7a89 351 #define CCM_INTENSET_ENDCRYPT_Msk (0x1UL << CCM_INTENSET_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
Kojto 91:031413cf7a89 352 #define CCM_INTENSET_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 353 #define CCM_INTENSET_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 354 #define CCM_INTENSET_ENDCRYPT_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 355
Kojto 91:031413cf7a89 356 /* Bit 0 : Enable interrupt on ENDKSGEN event. */
Kojto 91:031413cf7a89 357 #define CCM_INTENSET_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
Kojto 91:031413cf7a89 358 #define CCM_INTENSET_ENDKSGEN_Msk (0x1UL << CCM_INTENSET_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
Kojto 91:031413cf7a89 359 #define CCM_INTENSET_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 360 #define CCM_INTENSET_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 361 #define CCM_INTENSET_ENDKSGEN_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 362
Kojto 91:031413cf7a89 363 /* Register: CCM_INTENCLR */
Kojto 91:031413cf7a89 364 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 365
Kojto 91:031413cf7a89 366 /* Bit 2 : Disable interrupt on ERROR event. */
Kojto 91:031413cf7a89 367 #define CCM_INTENCLR_ERROR_Pos (2UL) /*!< Position of ERROR field. */
Kojto 91:031413cf7a89 368 #define CCM_INTENCLR_ERROR_Msk (0x1UL << CCM_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 91:031413cf7a89 369 #define CCM_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 370 #define CCM_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 371 #define CCM_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 372
Kojto 91:031413cf7a89 373 /* Bit 1 : Disable interrupt on ENDCRYPT event. */
Kojto 91:031413cf7a89 374 #define CCM_INTENCLR_ENDCRYPT_Pos (1UL) /*!< Position of ENDCRYPT field. */
Kojto 91:031413cf7a89 375 #define CCM_INTENCLR_ENDCRYPT_Msk (0x1UL << CCM_INTENCLR_ENDCRYPT_Pos) /*!< Bit mask of ENDCRYPT field. */
Kojto 91:031413cf7a89 376 #define CCM_INTENCLR_ENDCRYPT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 377 #define CCM_INTENCLR_ENDCRYPT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 378 #define CCM_INTENCLR_ENDCRYPT_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 379
Kojto 91:031413cf7a89 380 /* Bit 0 : Disable interrupt on ENDKSGEN event. */
Kojto 91:031413cf7a89 381 #define CCM_INTENCLR_ENDKSGEN_Pos (0UL) /*!< Position of ENDKSGEN field. */
Kojto 91:031413cf7a89 382 #define CCM_INTENCLR_ENDKSGEN_Msk (0x1UL << CCM_INTENCLR_ENDKSGEN_Pos) /*!< Bit mask of ENDKSGEN field. */
Kojto 91:031413cf7a89 383 #define CCM_INTENCLR_ENDKSGEN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 384 #define CCM_INTENCLR_ENDKSGEN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 385 #define CCM_INTENCLR_ENDKSGEN_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 386
Kojto 91:031413cf7a89 387 /* Register: CCM_MICSTATUS */
Kojto 91:031413cf7a89 388 /* Description: CCM RX MIC check result. */
Kojto 91:031413cf7a89 389
Kojto 91:031413cf7a89 390 /* Bit 0 : Result of the MIC check performed during the previous CCM RX STARTCRYPT */
Kojto 91:031413cf7a89 391 #define CCM_MICSTATUS_MICSTATUS_Pos (0UL) /*!< Position of MICSTATUS field. */
Kojto 91:031413cf7a89 392 #define CCM_MICSTATUS_MICSTATUS_Msk (0x1UL << CCM_MICSTATUS_MICSTATUS_Pos) /*!< Bit mask of MICSTATUS field. */
Kojto 91:031413cf7a89 393 #define CCM_MICSTATUS_MICSTATUS_CheckFailed (0UL) /*!< MIC check failed. */
Kojto 91:031413cf7a89 394 #define CCM_MICSTATUS_MICSTATUS_CheckPassed (1UL) /*!< MIC check passed. */
Kojto 91:031413cf7a89 395
Kojto 91:031413cf7a89 396 /* Register: CCM_ENABLE */
Kojto 91:031413cf7a89 397 /* Description: CCM enable. */
Kojto 91:031413cf7a89 398
Kojto 91:031413cf7a89 399 /* Bits 1..0 : CCM enable. */
Kojto 91:031413cf7a89 400 #define CCM_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 401 #define CCM_ENABLE_ENABLE_Msk (0x3UL << CCM_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 402 #define CCM_ENABLE_ENABLE_Disabled (0x00UL) /*!< CCM is disabled. */
Kojto 91:031413cf7a89 403 #define CCM_ENABLE_ENABLE_Enabled (0x02UL) /*!< CCM is enabled. */
Kojto 91:031413cf7a89 404
Kojto 91:031413cf7a89 405 /* Register: CCM_MODE */
Kojto 91:031413cf7a89 406 /* Description: Operation mode. */
Kojto 91:031413cf7a89 407
Kojto 91:031413cf7a89 408 /* Bit 0 : CCM mode operation. */
Kojto 91:031413cf7a89 409 #define CCM_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Kojto 91:031413cf7a89 410 #define CCM_MODE_MODE_Msk (0x1UL << CCM_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Kojto 91:031413cf7a89 411 #define CCM_MODE_MODE_Encryption (0UL) /*!< CCM mode TX */
Kojto 91:031413cf7a89 412 #define CCM_MODE_MODE_Decryption (1UL) /*!< CCM mode TX */
Kojto 91:031413cf7a89 413
Kojto 91:031413cf7a89 414 /* Register: CCM_POWER */
Kojto 91:031413cf7a89 415 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 416
Kojto 91:031413cf7a89 417 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 418 #define CCM_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 419 #define CCM_POWER_POWER_Msk (0x1UL << CCM_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 420 #define CCM_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 421 #define CCM_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 422
Kojto 91:031413cf7a89 423
Kojto 91:031413cf7a89 424 /* Peripheral: CLOCK */
Kojto 91:031413cf7a89 425 /* Description: Clock control. */
Kojto 91:031413cf7a89 426
Kojto 91:031413cf7a89 427 /* Register: CLOCK_INTENSET */
Kojto 91:031413cf7a89 428 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 429
Kojto 91:031413cf7a89 430 /* Bit 4 : Enable interrupt on CTTO event. */
Kojto 91:031413cf7a89 431 #define CLOCK_INTENSET_CTTO_Pos (4UL) /*!< Position of CTTO field. */
Kojto 91:031413cf7a89 432 #define CLOCK_INTENSET_CTTO_Msk (0x1UL << CLOCK_INTENSET_CTTO_Pos) /*!< Bit mask of CTTO field. */
Kojto 91:031413cf7a89 433 #define CLOCK_INTENSET_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 434 #define CLOCK_INTENSET_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 435 #define CLOCK_INTENSET_CTTO_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 436
Kojto 91:031413cf7a89 437 /* Bit 3 : Enable interrupt on DONE event. */
Kojto 91:031413cf7a89 438 #define CLOCK_INTENSET_DONE_Pos (3UL) /*!< Position of DONE field. */
Kojto 91:031413cf7a89 439 #define CLOCK_INTENSET_DONE_Msk (0x1UL << CLOCK_INTENSET_DONE_Pos) /*!< Bit mask of DONE field. */
Kojto 91:031413cf7a89 440 #define CLOCK_INTENSET_DONE_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 441 #define CLOCK_INTENSET_DONE_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 442 #define CLOCK_INTENSET_DONE_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 443
Kojto 91:031413cf7a89 444 /* Bit 1 : Enable interrupt on LFCLKSTARTED event. */
Kojto 91:031413cf7a89 445 #define CLOCK_INTENSET_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
Kojto 91:031413cf7a89 446 #define CLOCK_INTENSET_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
Kojto 91:031413cf7a89 447 #define CLOCK_INTENSET_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 448 #define CLOCK_INTENSET_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 449 #define CLOCK_INTENSET_LFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 450
Kojto 91:031413cf7a89 451 /* Bit 0 : Enable interrupt on HFCLKSTARTED event. */
Kojto 91:031413cf7a89 452 #define CLOCK_INTENSET_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
Kojto 91:031413cf7a89 453 #define CLOCK_INTENSET_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENSET_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
Kojto 91:031413cf7a89 454 #define CLOCK_INTENSET_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 455 #define CLOCK_INTENSET_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 456 #define CLOCK_INTENSET_HFCLKSTARTED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 457
Kojto 91:031413cf7a89 458 /* Register: CLOCK_INTENCLR */
Kojto 91:031413cf7a89 459 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 460
Kojto 91:031413cf7a89 461 /* Bit 4 : Disable interrupt on CTTO event. */
Kojto 91:031413cf7a89 462 #define CLOCK_INTENCLR_CTTO_Pos (4UL) /*!< Position of CTTO field. */
Kojto 91:031413cf7a89 463 #define CLOCK_INTENCLR_CTTO_Msk (0x1UL << CLOCK_INTENCLR_CTTO_Pos) /*!< Bit mask of CTTO field. */
Kojto 91:031413cf7a89 464 #define CLOCK_INTENCLR_CTTO_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 465 #define CLOCK_INTENCLR_CTTO_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 466 #define CLOCK_INTENCLR_CTTO_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 467
Kojto 91:031413cf7a89 468 /* Bit 3 : Disable interrupt on DONE event. */
Kojto 91:031413cf7a89 469 #define CLOCK_INTENCLR_DONE_Pos (3UL) /*!< Position of DONE field. */
Kojto 91:031413cf7a89 470 #define CLOCK_INTENCLR_DONE_Msk (0x1UL << CLOCK_INTENCLR_DONE_Pos) /*!< Bit mask of DONE field. */
Kojto 91:031413cf7a89 471 #define CLOCK_INTENCLR_DONE_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 472 #define CLOCK_INTENCLR_DONE_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 473 #define CLOCK_INTENCLR_DONE_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 474
Kojto 91:031413cf7a89 475 /* Bit 1 : Disable interrupt on LFCLKSTARTED event. */
Kojto 91:031413cf7a89 476 #define CLOCK_INTENCLR_LFCLKSTARTED_Pos (1UL) /*!< Position of LFCLKSTARTED field. */
Kojto 91:031413cf7a89 477 #define CLOCK_INTENCLR_LFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_LFCLKSTARTED_Pos) /*!< Bit mask of LFCLKSTARTED field. */
Kojto 91:031413cf7a89 478 #define CLOCK_INTENCLR_LFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 479 #define CLOCK_INTENCLR_LFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 480 #define CLOCK_INTENCLR_LFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 481
Kojto 91:031413cf7a89 482 /* Bit 0 : Disable interrupt on HFCLKSTARTED event. */
Kojto 91:031413cf7a89 483 #define CLOCK_INTENCLR_HFCLKSTARTED_Pos (0UL) /*!< Position of HFCLKSTARTED field. */
Kojto 91:031413cf7a89 484 #define CLOCK_INTENCLR_HFCLKSTARTED_Msk (0x1UL << CLOCK_INTENCLR_HFCLKSTARTED_Pos) /*!< Bit mask of HFCLKSTARTED field. */
Kojto 91:031413cf7a89 485 #define CLOCK_INTENCLR_HFCLKSTARTED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 486 #define CLOCK_INTENCLR_HFCLKSTARTED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 487 #define CLOCK_INTENCLR_HFCLKSTARTED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 488
Kojto 91:031413cf7a89 489 /* Register: CLOCK_HFCLKSTAT */
Kojto 91:031413cf7a89 490 /* Description: High frequency clock status. */
Kojto 91:031413cf7a89 491
Kojto 91:031413cf7a89 492 /* Bit 16 : State for the HFCLK. */
Kojto 91:031413cf7a89 493 #define CLOCK_HFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
Kojto 91:031413cf7a89 494 #define CLOCK_HFCLKSTAT_STATE_Msk (0x1UL << CLOCK_HFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
Kojto 91:031413cf7a89 495 #define CLOCK_HFCLKSTAT_STATE_NotRunning (0UL) /*!< HFCLK clock not running. */
Kojto 91:031413cf7a89 496 #define CLOCK_HFCLKSTAT_STATE_Running (1UL) /*!< HFCLK clock running. */
Kojto 91:031413cf7a89 497
Kojto 91:031413cf7a89 498 /* Bit 0 : Active clock source for the HF clock. */
Kojto 91:031413cf7a89 499 #define CLOCK_HFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
Kojto 91:031413cf7a89 500 #define CLOCK_HFCLKSTAT_SRC_Msk (0x1UL << CLOCK_HFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
Kojto 91:031413cf7a89 501 #define CLOCK_HFCLKSTAT_SRC_RC (0UL) /*!< Internal 16MHz RC oscillator running and generating the HFCLK clock. */
Kojto 91:031413cf7a89 502 #define CLOCK_HFCLKSTAT_SRC_Xtal (1UL) /*!< External 16MHz/32MHz crystal oscillator running and generating the HFCLK clock. */
Kojto 91:031413cf7a89 503
Kojto 91:031413cf7a89 504 /* Register: CLOCK_LFCLKSTAT */
Kojto 91:031413cf7a89 505 /* Description: Low frequency clock status. */
Kojto 91:031413cf7a89 506
Kojto 91:031413cf7a89 507 /* Bit 16 : State for the LF clock. */
Kojto 91:031413cf7a89 508 #define CLOCK_LFCLKSTAT_STATE_Pos (16UL) /*!< Position of STATE field. */
Kojto 91:031413cf7a89 509 #define CLOCK_LFCLKSTAT_STATE_Msk (0x1UL << CLOCK_LFCLKSTAT_STATE_Pos) /*!< Bit mask of STATE field. */
Kojto 91:031413cf7a89 510 #define CLOCK_LFCLKSTAT_STATE_NotRunning (0UL) /*!< LFCLK clock not running. */
Kojto 91:031413cf7a89 511 #define CLOCK_LFCLKSTAT_STATE_Running (1UL) /*!< LFCLK clock running. */
Kojto 91:031413cf7a89 512
Kojto 91:031413cf7a89 513 /* Bits 1..0 : Active clock source for the LF clock. */
Kojto 91:031413cf7a89 514 #define CLOCK_LFCLKSTAT_SRC_Pos (0UL) /*!< Position of SRC field. */
Kojto 91:031413cf7a89 515 #define CLOCK_LFCLKSTAT_SRC_Msk (0x3UL << CLOCK_LFCLKSTAT_SRC_Pos) /*!< Bit mask of SRC field. */
Kojto 91:031413cf7a89 516 #define CLOCK_LFCLKSTAT_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator running and generating the LFCLK clock. */
Kojto 91:031413cf7a89 517 #define CLOCK_LFCLKSTAT_SRC_Xtal (1UL) /*!< External 32KiHz crystal oscillator running and generating the LFCLK clock. */
Kojto 91:031413cf7a89 518 #define CLOCK_LFCLKSTAT_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from the HFCLK running and generating the LFCLK clock. */
Kojto 91:031413cf7a89 519
Kojto 91:031413cf7a89 520 /* Register: CLOCK_LFCLKSRC */
Kojto 91:031413cf7a89 521 /* Description: Clock source for the LFCLK clock. */
Kojto 91:031413cf7a89 522
Kojto 91:031413cf7a89 523 /* Bits 1..0 : Clock source. */
Kojto 91:031413cf7a89 524 #define CLOCK_LFCLKSRC_SRC_Pos (0UL) /*!< Position of SRC field. */
Kojto 91:031413cf7a89 525 #define CLOCK_LFCLKSRC_SRC_Msk (0x3UL << CLOCK_LFCLKSRC_SRC_Pos) /*!< Bit mask of SRC field. */
Kojto 91:031413cf7a89 526 #define CLOCK_LFCLKSRC_SRC_RC (0UL) /*!< Internal 32KiHz RC oscillator. */
Kojto 91:031413cf7a89 527 #define CLOCK_LFCLKSRC_SRC_Xtal (1UL) /*!< External 32KiHz crystal. */
Kojto 91:031413cf7a89 528 #define CLOCK_LFCLKSRC_SRC_Synth (2UL) /*!< Internal 32KiHz synthesizer from HFCLK system clock. */
Kojto 91:031413cf7a89 529
Kojto 91:031413cf7a89 530 /* Register: CLOCK_CTIV */
Kojto 91:031413cf7a89 531 /* Description: Calibration timer interval. */
Kojto 91:031413cf7a89 532
Kojto 91:031413cf7a89 533 /* Bits 6..0 : Calibration timer interval in 0.25s resolution. */
Kojto 91:031413cf7a89 534 #define CLOCK_CTIV_CTIV_Pos (0UL) /*!< Position of CTIV field. */
Kojto 91:031413cf7a89 535 #define CLOCK_CTIV_CTIV_Msk (0x7FUL << CLOCK_CTIV_CTIV_Pos) /*!< Bit mask of CTIV field. */
Kojto 91:031413cf7a89 536
Kojto 91:031413cf7a89 537 /* Register: CLOCK_XTALFREQ */
Kojto 91:031413cf7a89 538 /* Description: Crystal frequency. */
Kojto 91:031413cf7a89 539
Kojto 91:031413cf7a89 540 /* Bits 7..0 : External Xtal frequency selection. */
Kojto 91:031413cf7a89 541 #define CLOCK_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
Kojto 91:031413cf7a89 542 #define CLOCK_XTALFREQ_XTALFREQ_Msk (0xFFUL << CLOCK_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
Kojto 91:031413cf7a89 543 #define CLOCK_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz xtal is used. */
Kojto 91:031413cf7a89 544 #define CLOCK_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz xtal is used. */
Kojto 91:031413cf7a89 545
Kojto 91:031413cf7a89 546
Kojto 91:031413cf7a89 547 /* Peripheral: COMP */
Kojto 91:031413cf7a89 548 /* Description: Comparator. */
Kojto 91:031413cf7a89 549
Kojto 91:031413cf7a89 550 /* Register: COMP_SHORTS */
Kojto 91:031413cf7a89 551 /* Description: Shortcut for the COMP. */
Kojto 91:031413cf7a89 552
Kojto 91:031413cf7a89 553 /* Bit 4 : Short-cut between CROSS event and STOP task. */
Kojto 91:031413cf7a89 554 #define COMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
Kojto 91:031413cf7a89 555 #define COMP_SHORTS_CROSS_STOP_Msk (0x1UL << COMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
Kojto 91:031413cf7a89 556 #define COMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 557 #define COMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 558
Kojto 91:031413cf7a89 559 /* Bit 3 : Short-cut between UP event and STOP task. */
Kojto 91:031413cf7a89 560 #define COMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
Kojto 91:031413cf7a89 561 #define COMP_SHORTS_UP_STOP_Msk (0x1UL << COMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
Kojto 91:031413cf7a89 562 #define COMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 563 #define COMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 564
Kojto 91:031413cf7a89 565 /* Bit 2 : Short-cut between DOWN event and STOP task. */
Kojto 91:031413cf7a89 566 #define COMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
Kojto 91:031413cf7a89 567 #define COMP_SHORTS_DOWN_STOP_Msk (0x1UL << COMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
Kojto 91:031413cf7a89 568 #define COMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 569 #define COMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 570
Kojto 91:031413cf7a89 571 /* Bit 1 : Short-cut between RADY event and STOP task. */
Kojto 91:031413cf7a89 572 #define COMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
Kojto 91:031413cf7a89 573 #define COMP_SHORTS_READY_STOP_Msk (0x1UL << COMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
Kojto 91:031413cf7a89 574 #define COMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 575 #define COMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 576
Kojto 91:031413cf7a89 577 /* Bit 0 : Short-cut between READY event and SAMPLE task. */
Kojto 91:031413cf7a89 578 #define COMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
Kojto 91:031413cf7a89 579 #define COMP_SHORTS_READY_SAMPLE_Msk (0x1UL << COMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
Kojto 91:031413cf7a89 580 #define COMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 581 #define COMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 582
Kojto 91:031413cf7a89 583 /* Register: COMP_INTENSET */
Kojto 91:031413cf7a89 584 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 585
Kojto 91:031413cf7a89 586 /* Bit 3 : Enable interrupt on CROSS event. */
Kojto 91:031413cf7a89 587 #define COMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Kojto 91:031413cf7a89 588 #define COMP_INTENSET_CROSS_Msk (0x1UL << COMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
Kojto 91:031413cf7a89 589 #define COMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 590 #define COMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 591 #define COMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 592
Kojto 91:031413cf7a89 593 /* Bit 2 : Enable interrupt on UP event. */
Kojto 91:031413cf7a89 594 #define COMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
Kojto 91:031413cf7a89 595 #define COMP_INTENSET_UP_Msk (0x1UL << COMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
Kojto 91:031413cf7a89 596 #define COMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 597 #define COMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 598 #define COMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 599
Kojto 91:031413cf7a89 600 /* Bit 1 : Enable interrupt on DOWN event. */
Kojto 91:031413cf7a89 601 #define COMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Kojto 91:031413cf7a89 602 #define COMP_INTENSET_DOWN_Msk (0x1UL << COMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
Kojto 91:031413cf7a89 603 #define COMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 604 #define COMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 605 #define COMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 606
Kojto 91:031413cf7a89 607 /* Bit 0 : Enable interrupt on READY event. */
Kojto 91:031413cf7a89 608 #define COMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 91:031413cf7a89 609 #define COMP_INTENSET_READY_Msk (0x1UL << COMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Kojto 91:031413cf7a89 610 #define COMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 611 #define COMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 612 #define COMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 613
Kojto 91:031413cf7a89 614 /* Register: COMP_INTENCLR */
Kojto 91:031413cf7a89 615 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 616
Kojto 91:031413cf7a89 617 /* Bit 3 : Disable interrupt on CROSS event. */
Kojto 91:031413cf7a89 618 #define COMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Kojto 91:031413cf7a89 619 #define COMP_INTENCLR_CROSS_Msk (0x1UL << COMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
Kojto 91:031413cf7a89 620 #define COMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 621 #define COMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 622 #define COMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 623
Kojto 91:031413cf7a89 624 /* Bit 2 : Disable interrupt on UP event. */
Kojto 91:031413cf7a89 625 #define COMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
Kojto 91:031413cf7a89 626 #define COMP_INTENCLR_UP_Msk (0x1UL << COMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
Kojto 91:031413cf7a89 627 #define COMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 628 #define COMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 629 #define COMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 630
Kojto 91:031413cf7a89 631 /* Bit 1 : Disable interrupt on DOWN event. */
Kojto 91:031413cf7a89 632 #define COMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Kojto 91:031413cf7a89 633 #define COMP_INTENCLR_DOWN_Msk (0x1UL << COMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
Kojto 91:031413cf7a89 634 #define COMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 635 #define COMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 636 #define COMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 637
Kojto 91:031413cf7a89 638 /* Bit 0 : Disable interrupt on READY event. */
Kojto 91:031413cf7a89 639 #define COMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 91:031413cf7a89 640 #define COMP_INTENCLR_READY_Msk (0x1UL << COMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Kojto 91:031413cf7a89 641 #define COMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 642 #define COMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 643 #define COMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 644
Kojto 91:031413cf7a89 645 /* Register: COMP_RESULT */
Kojto 91:031413cf7a89 646 /* Description: Compare result. */
Kojto 91:031413cf7a89 647
Kojto 91:031413cf7a89 648 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
Kojto 91:031413cf7a89 649 #define COMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
Kojto 91:031413cf7a89 650 #define COMP_RESULT_RESULT_Msk (0x1UL << COMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
Kojto 91:031413cf7a89 651 #define COMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
Kojto 91:031413cf7a89 652 #define COMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
Kojto 91:031413cf7a89 653
Kojto 91:031413cf7a89 654 /* Register: COMP_ENABLE */
Kojto 91:031413cf7a89 655 /* Description: Enable the COMP. */
Kojto 91:031413cf7a89 656
Kojto 91:031413cf7a89 657 /* Bits 1..0 : Enable or disable COMP. */
Kojto 91:031413cf7a89 658 #define COMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 659 #define COMP_ENABLE_ENABLE_Msk (0x3UL << COMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 660 #define COMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled COMP. */
Kojto 91:031413cf7a89 661 #define COMP_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable COMP. */
Kojto 91:031413cf7a89 662
Kojto 91:031413cf7a89 663 /* Register: COMP_PSEL */
Kojto 91:031413cf7a89 664 /* Description: Input pin select. */
Kojto 91:031413cf7a89 665
Kojto 91:031413cf7a89 666 /* Bits 2..0 : Analog input pin select. */
Kojto 91:031413cf7a89 667 #define COMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
Kojto 91:031413cf7a89 668 #define COMP_PSEL_PSEL_Msk (0x7UL << COMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
Kojto 91:031413cf7a89 669 #define COMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
Kojto 91:031413cf7a89 670 #define COMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
Kojto 91:031413cf7a89 671 #define COMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
Kojto 91:031413cf7a89 672 #define COMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
Kojto 91:031413cf7a89 673 #define COMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
Kojto 91:031413cf7a89 674 #define COMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
Kojto 91:031413cf7a89 675 #define COMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
Kojto 91:031413cf7a89 676 #define COMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
Kojto 91:031413cf7a89 677
Kojto 91:031413cf7a89 678 /* Register: COMP_REFSEL */
Kojto 91:031413cf7a89 679 /* Description: Reference select. */
Kojto 91:031413cf7a89 680
Kojto 91:031413cf7a89 681 /* Bits 2..0 : Reference select. */
Kojto 91:031413cf7a89 682 #define COMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
Kojto 91:031413cf7a89 683 #define COMP_REFSEL_REFSEL_Msk (0x7UL << COMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
Kojto 91:031413cf7a89 684 #define COMP_REFSEL_REFSEL_Int1V5 (0UL) /*!< Use internal 1V5 as reference. */
Kojto 91:031413cf7a89 685 #define COMP_REFSEL_REFSEL_Int2V0 (1UL) /*!< Use internal 2V0 as reference. */
Kojto 91:031413cf7a89 686 #define COMP_REFSEL_REFSEL_Int2V5 (2UL) /*!< Use internal 2V5 as reference. */
Kojto 91:031413cf7a89 687 #define COMP_REFSEL_REFSEL_Supply (4UL) /*!< Use supply as reference. */
Kojto 91:031413cf7a89 688 #define COMP_REFSEL_REFSEL_ARef (5UL) /*!< Use external analog reference as reference. */
Kojto 91:031413cf7a89 689
Kojto 91:031413cf7a89 690 /* Register: COMP_EXTREFSEL */
Kojto 91:031413cf7a89 691 /* Description: External reference select. */
Kojto 91:031413cf7a89 692
Kojto 91:031413cf7a89 693 /* Bit 0 : External analog reference pin selection. */
Kojto 91:031413cf7a89 694 #define COMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
Kojto 91:031413cf7a89 695 #define COMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << COMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
Kojto 91:031413cf7a89 696 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
Kojto 91:031413cf7a89 697 #define COMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
Kojto 91:031413cf7a89 698
Kojto 91:031413cf7a89 699 /* Register: COMP_TH */
Kojto 91:031413cf7a89 700 /* Description: Threshold configuration for hysteresis unit. */
Kojto 91:031413cf7a89 701
Kojto 91:031413cf7a89 702 /* Bits 13..8 : VDOWN configuration. */
Kojto 91:031413cf7a89 703 #define COMP_TH_THDOWN_Pos (8UL) /*!< Position of THDOWN field. */
Kojto 91:031413cf7a89 704 #define COMP_TH_THDOWN_Msk (0x3FUL << COMP_TH_THDOWN_Pos) /*!< Bit mask of THDOWN field. */
Kojto 91:031413cf7a89 705
Kojto 91:031413cf7a89 706 /* Bits 5..0 : VUP configuration. */
Kojto 91:031413cf7a89 707 #define COMP_TH_THUP_Pos (0UL) /*!< Position of THUP field. */
Kojto 91:031413cf7a89 708 #define COMP_TH_THUP_Msk (0x3FUL << COMP_TH_THUP_Pos) /*!< Bit mask of THUP field. */
Kojto 91:031413cf7a89 709
Kojto 91:031413cf7a89 710 /* Register: COMP_MODE */
Kojto 91:031413cf7a89 711 /* Description: Mode configuration. */
Kojto 91:031413cf7a89 712
Kojto 91:031413cf7a89 713 /* Bit 8 : Main operation mode. */
Kojto 91:031413cf7a89 714 #define COMP_MODE_MAIN_Pos (8UL) /*!< Position of MAIN field. */
Kojto 91:031413cf7a89 715 #define COMP_MODE_MAIN_Msk (0x1UL << COMP_MODE_MAIN_Pos) /*!< Bit mask of MAIN field. */
Kojto 91:031413cf7a89 716 #define COMP_MODE_MAIN_Single (0UL) /*!< Single ended mode. */
Kojto 91:031413cf7a89 717 #define COMP_MODE_MAIN_Diff (1UL) /*!< Differential mode. */
Kojto 91:031413cf7a89 718
Kojto 91:031413cf7a89 719 /* Bits 1..0 : Speed and power mode. */
Kojto 91:031413cf7a89 720 #define COMP_MODE_SP_Pos (0UL) /*!< Position of SP field. */
Kojto 91:031413cf7a89 721 #define COMP_MODE_SP_Msk (0x3UL << COMP_MODE_SP_Pos) /*!< Bit mask of SP field. */
Kojto 91:031413cf7a89 722 #define COMP_MODE_SP_Low (0UL) /*!< Low power mode. */
Kojto 91:031413cf7a89 723 #define COMP_MODE_SP_Normal (1UL) /*!< Normal mode. */
Kojto 91:031413cf7a89 724 #define COMP_MODE_SP_High (2UL) /*!< High speed mode. */
Kojto 91:031413cf7a89 725
Kojto 91:031413cf7a89 726 /* Register: COMP_POWER */
Kojto 91:031413cf7a89 727 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 728
Kojto 91:031413cf7a89 729 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 730 #define COMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 731 #define COMP_POWER_POWER_Msk (0x1UL << COMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 732 #define COMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 733 #define COMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 734
Kojto 91:031413cf7a89 735
Kojto 91:031413cf7a89 736 /* Peripheral: ECB */
Kojto 91:031413cf7a89 737 /* Description: AES ECB Mode Encryption. */
Kojto 91:031413cf7a89 738
Kojto 91:031413cf7a89 739 /* Register: ECB_INTENSET */
Kojto 91:031413cf7a89 740 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 741
Kojto 91:031413cf7a89 742 /* Bit 1 : Enable interrupt on ERRORECB event. */
Kojto 91:031413cf7a89 743 #define ECB_INTENSET_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
Kojto 91:031413cf7a89 744 #define ECB_INTENSET_ERRORECB_Msk (0x1UL << ECB_INTENSET_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
Kojto 91:031413cf7a89 745 #define ECB_INTENSET_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 746 #define ECB_INTENSET_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 747 #define ECB_INTENSET_ERRORECB_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 748
Kojto 91:031413cf7a89 749 /* Bit 0 : Enable interrupt on ENDECB event. */
Kojto 91:031413cf7a89 750 #define ECB_INTENSET_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
Kojto 91:031413cf7a89 751 #define ECB_INTENSET_ENDECB_Msk (0x1UL << ECB_INTENSET_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
Kojto 91:031413cf7a89 752 #define ECB_INTENSET_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 753 #define ECB_INTENSET_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 754 #define ECB_INTENSET_ENDECB_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 755
Kojto 91:031413cf7a89 756 /* Register: ECB_INTENCLR */
Kojto 91:031413cf7a89 757 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 758
Kojto 91:031413cf7a89 759 /* Bit 1 : Disable interrupt on ERRORECB event. */
Kojto 91:031413cf7a89 760 #define ECB_INTENCLR_ERRORECB_Pos (1UL) /*!< Position of ERRORECB field. */
Kojto 91:031413cf7a89 761 #define ECB_INTENCLR_ERRORECB_Msk (0x1UL << ECB_INTENCLR_ERRORECB_Pos) /*!< Bit mask of ERRORECB field. */
Kojto 91:031413cf7a89 762 #define ECB_INTENCLR_ERRORECB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 763 #define ECB_INTENCLR_ERRORECB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 764 #define ECB_INTENCLR_ERRORECB_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 765
Kojto 91:031413cf7a89 766 /* Bit 0 : Disable interrupt on ENDECB event. */
Kojto 91:031413cf7a89 767 #define ECB_INTENCLR_ENDECB_Pos (0UL) /*!< Position of ENDECB field. */
Kojto 91:031413cf7a89 768 #define ECB_INTENCLR_ENDECB_Msk (0x1UL << ECB_INTENCLR_ENDECB_Pos) /*!< Bit mask of ENDECB field. */
Kojto 91:031413cf7a89 769 #define ECB_INTENCLR_ENDECB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 770 #define ECB_INTENCLR_ENDECB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 771 #define ECB_INTENCLR_ENDECB_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 772
Kojto 91:031413cf7a89 773 /* Register: ECB_POWER */
Kojto 91:031413cf7a89 774 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 775
Kojto 91:031413cf7a89 776 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 777 #define ECB_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 778 #define ECB_POWER_POWER_Msk (0x1UL << ECB_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 779 #define ECB_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 780 #define ECB_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 781
Kojto 91:031413cf7a89 782
Kojto 91:031413cf7a89 783 /* Peripheral: FICR */
Kojto 91:031413cf7a89 784 /* Description: Factory Information Configuration. */
Kojto 91:031413cf7a89 785
Kojto 91:031413cf7a89 786 /* Register: FICR_PPFC */
Kojto 91:031413cf7a89 787 /* Description: Pre-programmed factory code present. */
Kojto 91:031413cf7a89 788
Kojto 91:031413cf7a89 789 /* Bits 7..0 : Pre-programmed factory code present. */
Kojto 91:031413cf7a89 790 #define FICR_PPFC_PPFC_Pos (0UL) /*!< Position of PPFC field. */
Kojto 91:031413cf7a89 791 #define FICR_PPFC_PPFC_Msk (0xFFUL << FICR_PPFC_PPFC_Pos) /*!< Bit mask of PPFC field. */
Kojto 91:031413cf7a89 792 #define FICR_PPFC_PPFC_NotPresent (0xFFUL) /*!< Not present. */
Kojto 91:031413cf7a89 793 #define FICR_PPFC_PPFC_Present (0x00UL) /*!< Present. */
Kojto 91:031413cf7a89 794
Kojto 91:031413cf7a89 795 /* Register: FICR_CONFIGID */
Kojto 91:031413cf7a89 796 /* Description: Configuration identifier. */
Kojto 91:031413cf7a89 797
Kojto 91:031413cf7a89 798 /* Bits 31..16 : Firmware Identification Number pre-loaded into the flash. */
Kojto 91:031413cf7a89 799 #define FICR_CONFIGID_FWID_Pos (16UL) /*!< Position of FWID field. */
Kojto 91:031413cf7a89 800 #define FICR_CONFIGID_FWID_Msk (0xFFFFUL << FICR_CONFIGID_FWID_Pos) /*!< Bit mask of FWID field. */
Kojto 91:031413cf7a89 801
Kojto 91:031413cf7a89 802 /* Bits 15..0 : Hardware Identification Number. */
Kojto 91:031413cf7a89 803 #define FICR_CONFIGID_HWID_Pos (0UL) /*!< Position of HWID field. */
Kojto 91:031413cf7a89 804 #define FICR_CONFIGID_HWID_Msk (0xFFFFUL << FICR_CONFIGID_HWID_Pos) /*!< Bit mask of HWID field. */
Kojto 91:031413cf7a89 805
Kojto 91:031413cf7a89 806 /* Register: FICR_DEVICEADDRTYPE */
Kojto 91:031413cf7a89 807 /* Description: Device address type. */
Kojto 91:031413cf7a89 808
Kojto 91:031413cf7a89 809 /* Bit 0 : Device address type. */
Kojto 91:031413cf7a89 810 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos (0UL) /*!< Position of DEVICEADDRTYPE field. */
Kojto 91:031413cf7a89 811 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Msk (0x1UL << FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Pos) /*!< Bit mask of DEVICEADDRTYPE field. */
Kojto 91:031413cf7a89 812 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Public (0UL) /*!< Public address. */
Kojto 91:031413cf7a89 813 #define FICR_DEVICEADDRTYPE_DEVICEADDRTYPE_Random (1UL) /*!< Random address. */
Kojto 91:031413cf7a89 814
Kojto 91:031413cf7a89 815 /* Register: FICR_OVERRIDEEN */
Kojto 91:031413cf7a89 816 /* Description: Radio calibration override enable. */
Kojto 91:031413cf7a89 817
Kojto 91:031413cf7a89 818 /* Bit 3 : Override default values for BLE_1Mbit mode. */
Kojto 91:031413cf7a89 819 #define FICR_OVERRIDEEN_BLE_1MBIT_Pos (3UL) /*!< Position of BLE_1MBIT field. */
Kojto 91:031413cf7a89 820 #define FICR_OVERRIDEEN_BLE_1MBIT_Msk (0x1UL << FICR_OVERRIDEEN_BLE_1MBIT_Pos) /*!< Bit mask of BLE_1MBIT field. */
Kojto 91:031413cf7a89 821 #define FICR_OVERRIDEEN_BLE_1MBIT_Override (0UL) /*!< Override the default values for BLE_1Mbit mode. */
Kojto 91:031413cf7a89 822 #define FICR_OVERRIDEEN_BLE_1MBIT_NotOverride (1UL) /*!< Do not override the default values for BLE_1Mbit mode. */
Kojto 91:031413cf7a89 823
Kojto 91:031413cf7a89 824
Kojto 91:031413cf7a89 825 /* Peripheral: GPIO */
Kojto 91:031413cf7a89 826 /* Description: General purpose input and output. */
Kojto 91:031413cf7a89 827
Kojto 91:031413cf7a89 828 /* Register: GPIO_OUT */
Kojto 91:031413cf7a89 829 /* Description: Write GPIO port. */
Kojto 91:031413cf7a89 830
Kojto 91:031413cf7a89 831 /* Bit 31 : Pin 31. */
Kojto 91:031413cf7a89 832 #define GPIO_OUT_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 91:031413cf7a89 833 #define GPIO_OUT_PIN31_Msk (0x1UL << GPIO_OUT_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 91:031413cf7a89 834 #define GPIO_OUT_PIN31_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 835 #define GPIO_OUT_PIN31_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 836
Kojto 91:031413cf7a89 837 /* Bit 30 : Pin 30. */
Kojto 91:031413cf7a89 838 #define GPIO_OUT_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 91:031413cf7a89 839 #define GPIO_OUT_PIN30_Msk (0x1UL << GPIO_OUT_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 91:031413cf7a89 840 #define GPIO_OUT_PIN30_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 841 #define GPIO_OUT_PIN30_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 842
Kojto 91:031413cf7a89 843 /* Bit 29 : Pin 29. */
Kojto 91:031413cf7a89 844 #define GPIO_OUT_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 91:031413cf7a89 845 #define GPIO_OUT_PIN29_Msk (0x1UL << GPIO_OUT_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 91:031413cf7a89 846 #define GPIO_OUT_PIN29_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 847 #define GPIO_OUT_PIN29_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 848
Kojto 91:031413cf7a89 849 /* Bit 28 : Pin 28. */
Kojto 91:031413cf7a89 850 #define GPIO_OUT_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 91:031413cf7a89 851 #define GPIO_OUT_PIN28_Msk (0x1UL << GPIO_OUT_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 91:031413cf7a89 852 #define GPIO_OUT_PIN28_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 853 #define GPIO_OUT_PIN28_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 854
Kojto 91:031413cf7a89 855 /* Bit 27 : Pin 27. */
Kojto 91:031413cf7a89 856 #define GPIO_OUT_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 91:031413cf7a89 857 #define GPIO_OUT_PIN27_Msk (0x1UL << GPIO_OUT_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 91:031413cf7a89 858 #define GPIO_OUT_PIN27_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 859 #define GPIO_OUT_PIN27_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 860
Kojto 91:031413cf7a89 861 /* Bit 26 : Pin 26. */
Kojto 91:031413cf7a89 862 #define GPIO_OUT_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 91:031413cf7a89 863 #define GPIO_OUT_PIN26_Msk (0x1UL << GPIO_OUT_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 91:031413cf7a89 864 #define GPIO_OUT_PIN26_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 865 #define GPIO_OUT_PIN26_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 866
Kojto 91:031413cf7a89 867 /* Bit 25 : Pin 25. */
Kojto 91:031413cf7a89 868 #define GPIO_OUT_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 91:031413cf7a89 869 #define GPIO_OUT_PIN25_Msk (0x1UL << GPIO_OUT_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 91:031413cf7a89 870 #define GPIO_OUT_PIN25_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 871 #define GPIO_OUT_PIN25_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 872
Kojto 91:031413cf7a89 873 /* Bit 24 : Pin 24. */
Kojto 91:031413cf7a89 874 #define GPIO_OUT_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 91:031413cf7a89 875 #define GPIO_OUT_PIN24_Msk (0x1UL << GPIO_OUT_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 91:031413cf7a89 876 #define GPIO_OUT_PIN24_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 877 #define GPIO_OUT_PIN24_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 878
Kojto 91:031413cf7a89 879 /* Bit 23 : Pin 23. */
Kojto 91:031413cf7a89 880 #define GPIO_OUT_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 91:031413cf7a89 881 #define GPIO_OUT_PIN23_Msk (0x1UL << GPIO_OUT_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 91:031413cf7a89 882 #define GPIO_OUT_PIN23_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 883 #define GPIO_OUT_PIN23_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 884
Kojto 91:031413cf7a89 885 /* Bit 22 : Pin 22. */
Kojto 91:031413cf7a89 886 #define GPIO_OUT_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 91:031413cf7a89 887 #define GPIO_OUT_PIN22_Msk (0x1UL << GPIO_OUT_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 91:031413cf7a89 888 #define GPIO_OUT_PIN22_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 889 #define GPIO_OUT_PIN22_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 890
Kojto 91:031413cf7a89 891 /* Bit 21 : Pin 21. */
Kojto 91:031413cf7a89 892 #define GPIO_OUT_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 91:031413cf7a89 893 #define GPIO_OUT_PIN21_Msk (0x1UL << GPIO_OUT_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 91:031413cf7a89 894 #define GPIO_OUT_PIN21_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 895 #define GPIO_OUT_PIN21_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 896
Kojto 91:031413cf7a89 897 /* Bit 20 : Pin 20. */
Kojto 91:031413cf7a89 898 #define GPIO_OUT_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 91:031413cf7a89 899 #define GPIO_OUT_PIN20_Msk (0x1UL << GPIO_OUT_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 91:031413cf7a89 900 #define GPIO_OUT_PIN20_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 901 #define GPIO_OUT_PIN20_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 902
Kojto 91:031413cf7a89 903 /* Bit 19 : Pin 19. */
Kojto 91:031413cf7a89 904 #define GPIO_OUT_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 91:031413cf7a89 905 #define GPIO_OUT_PIN19_Msk (0x1UL << GPIO_OUT_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 91:031413cf7a89 906 #define GPIO_OUT_PIN19_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 907 #define GPIO_OUT_PIN19_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 908
Kojto 91:031413cf7a89 909 /* Bit 18 : Pin 18. */
Kojto 91:031413cf7a89 910 #define GPIO_OUT_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 91:031413cf7a89 911 #define GPIO_OUT_PIN18_Msk (0x1UL << GPIO_OUT_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 91:031413cf7a89 912 #define GPIO_OUT_PIN18_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 913 #define GPIO_OUT_PIN18_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 914
Kojto 91:031413cf7a89 915 /* Bit 17 : Pin 17. */
Kojto 91:031413cf7a89 916 #define GPIO_OUT_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 91:031413cf7a89 917 #define GPIO_OUT_PIN17_Msk (0x1UL << GPIO_OUT_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 91:031413cf7a89 918 #define GPIO_OUT_PIN17_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 919 #define GPIO_OUT_PIN17_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 920
Kojto 91:031413cf7a89 921 /* Bit 16 : Pin 16. */
Kojto 91:031413cf7a89 922 #define GPIO_OUT_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 91:031413cf7a89 923 #define GPIO_OUT_PIN16_Msk (0x1UL << GPIO_OUT_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 91:031413cf7a89 924 #define GPIO_OUT_PIN16_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 925 #define GPIO_OUT_PIN16_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 926
Kojto 91:031413cf7a89 927 /* Bit 15 : Pin 15. */
Kojto 91:031413cf7a89 928 #define GPIO_OUT_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 91:031413cf7a89 929 #define GPIO_OUT_PIN15_Msk (0x1UL << GPIO_OUT_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 91:031413cf7a89 930 #define GPIO_OUT_PIN15_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 931 #define GPIO_OUT_PIN15_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 932
Kojto 91:031413cf7a89 933 /* Bit 14 : Pin 14. */
Kojto 91:031413cf7a89 934 #define GPIO_OUT_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 91:031413cf7a89 935 #define GPIO_OUT_PIN14_Msk (0x1UL << GPIO_OUT_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 91:031413cf7a89 936 #define GPIO_OUT_PIN14_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 937 #define GPIO_OUT_PIN14_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 938
Kojto 91:031413cf7a89 939 /* Bit 13 : Pin 13. */
Kojto 91:031413cf7a89 940 #define GPIO_OUT_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 91:031413cf7a89 941 #define GPIO_OUT_PIN13_Msk (0x1UL << GPIO_OUT_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 91:031413cf7a89 942 #define GPIO_OUT_PIN13_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 943 #define GPIO_OUT_PIN13_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 944
Kojto 91:031413cf7a89 945 /* Bit 12 : Pin 12. */
Kojto 91:031413cf7a89 946 #define GPIO_OUT_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 91:031413cf7a89 947 #define GPIO_OUT_PIN12_Msk (0x1UL << GPIO_OUT_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 91:031413cf7a89 948 #define GPIO_OUT_PIN12_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 949 #define GPIO_OUT_PIN12_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 950
Kojto 91:031413cf7a89 951 /* Bit 11 : Pin 11. */
Kojto 91:031413cf7a89 952 #define GPIO_OUT_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 91:031413cf7a89 953 #define GPIO_OUT_PIN11_Msk (0x1UL << GPIO_OUT_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 91:031413cf7a89 954 #define GPIO_OUT_PIN11_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 955 #define GPIO_OUT_PIN11_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 956
Kojto 91:031413cf7a89 957 /* Bit 10 : Pin 10. */
Kojto 91:031413cf7a89 958 #define GPIO_OUT_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 91:031413cf7a89 959 #define GPIO_OUT_PIN10_Msk (0x1UL << GPIO_OUT_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 91:031413cf7a89 960 #define GPIO_OUT_PIN10_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 961 #define GPIO_OUT_PIN10_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 962
Kojto 91:031413cf7a89 963 /* Bit 9 : Pin 9. */
Kojto 91:031413cf7a89 964 #define GPIO_OUT_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 91:031413cf7a89 965 #define GPIO_OUT_PIN9_Msk (0x1UL << GPIO_OUT_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 91:031413cf7a89 966 #define GPIO_OUT_PIN9_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 967 #define GPIO_OUT_PIN9_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 968
Kojto 91:031413cf7a89 969 /* Bit 8 : Pin 8. */
Kojto 91:031413cf7a89 970 #define GPIO_OUT_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 91:031413cf7a89 971 #define GPIO_OUT_PIN8_Msk (0x1UL << GPIO_OUT_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 91:031413cf7a89 972 #define GPIO_OUT_PIN8_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 973 #define GPIO_OUT_PIN8_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 974
Kojto 91:031413cf7a89 975 /* Bit 7 : Pin 7. */
Kojto 91:031413cf7a89 976 #define GPIO_OUT_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 91:031413cf7a89 977 #define GPIO_OUT_PIN7_Msk (0x1UL << GPIO_OUT_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 91:031413cf7a89 978 #define GPIO_OUT_PIN7_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 979 #define GPIO_OUT_PIN7_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 980
Kojto 91:031413cf7a89 981 /* Bit 6 : Pin 6. */
Kojto 91:031413cf7a89 982 #define GPIO_OUT_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 91:031413cf7a89 983 #define GPIO_OUT_PIN6_Msk (0x1UL << GPIO_OUT_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 91:031413cf7a89 984 #define GPIO_OUT_PIN6_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 985 #define GPIO_OUT_PIN6_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 986
Kojto 91:031413cf7a89 987 /* Bit 5 : Pin 5. */
Kojto 91:031413cf7a89 988 #define GPIO_OUT_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 91:031413cf7a89 989 #define GPIO_OUT_PIN5_Msk (0x1UL << GPIO_OUT_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 91:031413cf7a89 990 #define GPIO_OUT_PIN5_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 991 #define GPIO_OUT_PIN5_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 992
Kojto 91:031413cf7a89 993 /* Bit 4 : Pin 4. */
Kojto 91:031413cf7a89 994 #define GPIO_OUT_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 91:031413cf7a89 995 #define GPIO_OUT_PIN4_Msk (0x1UL << GPIO_OUT_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 91:031413cf7a89 996 #define GPIO_OUT_PIN4_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 997 #define GPIO_OUT_PIN4_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 998
Kojto 91:031413cf7a89 999 /* Bit 3 : Pin 3. */
Kojto 91:031413cf7a89 1000 #define GPIO_OUT_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 91:031413cf7a89 1001 #define GPIO_OUT_PIN3_Msk (0x1UL << GPIO_OUT_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 91:031413cf7a89 1002 #define GPIO_OUT_PIN3_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1003 #define GPIO_OUT_PIN3_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1004
Kojto 91:031413cf7a89 1005 /* Bit 2 : Pin 2. */
Kojto 91:031413cf7a89 1006 #define GPIO_OUT_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 91:031413cf7a89 1007 #define GPIO_OUT_PIN2_Msk (0x1UL << GPIO_OUT_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 91:031413cf7a89 1008 #define GPIO_OUT_PIN2_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1009 #define GPIO_OUT_PIN2_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1010
Kojto 91:031413cf7a89 1011 /* Bit 1 : Pin 1. */
Kojto 91:031413cf7a89 1012 #define GPIO_OUT_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 91:031413cf7a89 1013 #define GPIO_OUT_PIN1_Msk (0x1UL << GPIO_OUT_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 91:031413cf7a89 1014 #define GPIO_OUT_PIN1_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1015 #define GPIO_OUT_PIN1_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1016
Kojto 91:031413cf7a89 1017 /* Bit 0 : Pin 0. */
Kojto 91:031413cf7a89 1018 #define GPIO_OUT_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 91:031413cf7a89 1019 #define GPIO_OUT_PIN0_Msk (0x1UL << GPIO_OUT_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 91:031413cf7a89 1020 #define GPIO_OUT_PIN0_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1021 #define GPIO_OUT_PIN0_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1022
Kojto 91:031413cf7a89 1023 /* Register: GPIO_OUTSET */
Kojto 91:031413cf7a89 1024 /* Description: Set individual bits in GPIO port. */
Kojto 91:031413cf7a89 1025
Kojto 91:031413cf7a89 1026 /* Bit 31 : Pin 31. */
Kojto 91:031413cf7a89 1027 #define GPIO_OUTSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 91:031413cf7a89 1028 #define GPIO_OUTSET_PIN31_Msk (0x1UL << GPIO_OUTSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 91:031413cf7a89 1029 #define GPIO_OUTSET_PIN31_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1030 #define GPIO_OUTSET_PIN31_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1031 #define GPIO_OUTSET_PIN31_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1032
Kojto 91:031413cf7a89 1033 /* Bit 30 : Pin 30. */
Kojto 91:031413cf7a89 1034 #define GPIO_OUTSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 91:031413cf7a89 1035 #define GPIO_OUTSET_PIN30_Msk (0x1UL << GPIO_OUTSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 91:031413cf7a89 1036 #define GPIO_OUTSET_PIN30_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1037 #define GPIO_OUTSET_PIN30_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1038 #define GPIO_OUTSET_PIN30_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1039
Kojto 91:031413cf7a89 1040 /* Bit 29 : Pin 29. */
Kojto 91:031413cf7a89 1041 #define GPIO_OUTSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 91:031413cf7a89 1042 #define GPIO_OUTSET_PIN29_Msk (0x1UL << GPIO_OUTSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 91:031413cf7a89 1043 #define GPIO_OUTSET_PIN29_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1044 #define GPIO_OUTSET_PIN29_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1045 #define GPIO_OUTSET_PIN29_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1046
Kojto 91:031413cf7a89 1047 /* Bit 28 : Pin 28. */
Kojto 91:031413cf7a89 1048 #define GPIO_OUTSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 91:031413cf7a89 1049 #define GPIO_OUTSET_PIN28_Msk (0x1UL << GPIO_OUTSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 91:031413cf7a89 1050 #define GPIO_OUTSET_PIN28_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1051 #define GPIO_OUTSET_PIN28_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1052 #define GPIO_OUTSET_PIN28_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1053
Kojto 91:031413cf7a89 1054 /* Bit 27 : Pin 27. */
Kojto 91:031413cf7a89 1055 #define GPIO_OUTSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 91:031413cf7a89 1056 #define GPIO_OUTSET_PIN27_Msk (0x1UL << GPIO_OUTSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 91:031413cf7a89 1057 #define GPIO_OUTSET_PIN27_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1058 #define GPIO_OUTSET_PIN27_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1059 #define GPIO_OUTSET_PIN27_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1060
Kojto 91:031413cf7a89 1061 /* Bit 26 : Pin 26. */
Kojto 91:031413cf7a89 1062 #define GPIO_OUTSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 91:031413cf7a89 1063 #define GPIO_OUTSET_PIN26_Msk (0x1UL << GPIO_OUTSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 91:031413cf7a89 1064 #define GPIO_OUTSET_PIN26_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1065 #define GPIO_OUTSET_PIN26_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1066 #define GPIO_OUTSET_PIN26_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1067
Kojto 91:031413cf7a89 1068 /* Bit 25 : Pin 25. */
Kojto 91:031413cf7a89 1069 #define GPIO_OUTSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 91:031413cf7a89 1070 #define GPIO_OUTSET_PIN25_Msk (0x1UL << GPIO_OUTSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 91:031413cf7a89 1071 #define GPIO_OUTSET_PIN25_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1072 #define GPIO_OUTSET_PIN25_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1073 #define GPIO_OUTSET_PIN25_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1074
Kojto 91:031413cf7a89 1075 /* Bit 24 : Pin 24. */
Kojto 91:031413cf7a89 1076 #define GPIO_OUTSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 91:031413cf7a89 1077 #define GPIO_OUTSET_PIN24_Msk (0x1UL << GPIO_OUTSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 91:031413cf7a89 1078 #define GPIO_OUTSET_PIN24_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1079 #define GPIO_OUTSET_PIN24_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1080 #define GPIO_OUTSET_PIN24_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1081
Kojto 91:031413cf7a89 1082 /* Bit 23 : Pin 23. */
Kojto 91:031413cf7a89 1083 #define GPIO_OUTSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 91:031413cf7a89 1084 #define GPIO_OUTSET_PIN23_Msk (0x1UL << GPIO_OUTSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 91:031413cf7a89 1085 #define GPIO_OUTSET_PIN23_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1086 #define GPIO_OUTSET_PIN23_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1087 #define GPIO_OUTSET_PIN23_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1088
Kojto 91:031413cf7a89 1089 /* Bit 22 : Pin 22. */
Kojto 91:031413cf7a89 1090 #define GPIO_OUTSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 91:031413cf7a89 1091 #define GPIO_OUTSET_PIN22_Msk (0x1UL << GPIO_OUTSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 91:031413cf7a89 1092 #define GPIO_OUTSET_PIN22_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1093 #define GPIO_OUTSET_PIN22_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1094 #define GPIO_OUTSET_PIN22_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1095
Kojto 91:031413cf7a89 1096 /* Bit 21 : Pin 21. */
Kojto 91:031413cf7a89 1097 #define GPIO_OUTSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 91:031413cf7a89 1098 #define GPIO_OUTSET_PIN21_Msk (0x1UL << GPIO_OUTSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 91:031413cf7a89 1099 #define GPIO_OUTSET_PIN21_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1100 #define GPIO_OUTSET_PIN21_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1101 #define GPIO_OUTSET_PIN21_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1102
Kojto 91:031413cf7a89 1103 /* Bit 20 : Pin 20. */
Kojto 91:031413cf7a89 1104 #define GPIO_OUTSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 91:031413cf7a89 1105 #define GPIO_OUTSET_PIN20_Msk (0x1UL << GPIO_OUTSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 91:031413cf7a89 1106 #define GPIO_OUTSET_PIN20_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1107 #define GPIO_OUTSET_PIN20_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1108 #define GPIO_OUTSET_PIN20_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1109
Kojto 91:031413cf7a89 1110 /* Bit 19 : Pin 19. */
Kojto 91:031413cf7a89 1111 #define GPIO_OUTSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 91:031413cf7a89 1112 #define GPIO_OUTSET_PIN19_Msk (0x1UL << GPIO_OUTSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 91:031413cf7a89 1113 #define GPIO_OUTSET_PIN19_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1114 #define GPIO_OUTSET_PIN19_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1115 #define GPIO_OUTSET_PIN19_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1116
Kojto 91:031413cf7a89 1117 /* Bit 18 : Pin 18. */
Kojto 91:031413cf7a89 1118 #define GPIO_OUTSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 91:031413cf7a89 1119 #define GPIO_OUTSET_PIN18_Msk (0x1UL << GPIO_OUTSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 91:031413cf7a89 1120 #define GPIO_OUTSET_PIN18_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1121 #define GPIO_OUTSET_PIN18_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1122 #define GPIO_OUTSET_PIN18_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1123
Kojto 91:031413cf7a89 1124 /* Bit 17 : Pin 17. */
Kojto 91:031413cf7a89 1125 #define GPIO_OUTSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 91:031413cf7a89 1126 #define GPIO_OUTSET_PIN17_Msk (0x1UL << GPIO_OUTSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 91:031413cf7a89 1127 #define GPIO_OUTSET_PIN17_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1128 #define GPIO_OUTSET_PIN17_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1129 #define GPIO_OUTSET_PIN17_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1130
Kojto 91:031413cf7a89 1131 /* Bit 16 : Pin 16. */
Kojto 91:031413cf7a89 1132 #define GPIO_OUTSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 91:031413cf7a89 1133 #define GPIO_OUTSET_PIN16_Msk (0x1UL << GPIO_OUTSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 91:031413cf7a89 1134 #define GPIO_OUTSET_PIN16_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1135 #define GPIO_OUTSET_PIN16_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1136 #define GPIO_OUTSET_PIN16_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1137
Kojto 91:031413cf7a89 1138 /* Bit 15 : Pin 15. */
Kojto 91:031413cf7a89 1139 #define GPIO_OUTSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 91:031413cf7a89 1140 #define GPIO_OUTSET_PIN15_Msk (0x1UL << GPIO_OUTSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 91:031413cf7a89 1141 #define GPIO_OUTSET_PIN15_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1142 #define GPIO_OUTSET_PIN15_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1143 #define GPIO_OUTSET_PIN15_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1144
Kojto 91:031413cf7a89 1145 /* Bit 14 : Pin 14. */
Kojto 91:031413cf7a89 1146 #define GPIO_OUTSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 91:031413cf7a89 1147 #define GPIO_OUTSET_PIN14_Msk (0x1UL << GPIO_OUTSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 91:031413cf7a89 1148 #define GPIO_OUTSET_PIN14_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1149 #define GPIO_OUTSET_PIN14_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1150 #define GPIO_OUTSET_PIN14_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1151
Kojto 91:031413cf7a89 1152 /* Bit 13 : Pin 13. */
Kojto 91:031413cf7a89 1153 #define GPIO_OUTSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 91:031413cf7a89 1154 #define GPIO_OUTSET_PIN13_Msk (0x1UL << GPIO_OUTSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 91:031413cf7a89 1155 #define GPIO_OUTSET_PIN13_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1156 #define GPIO_OUTSET_PIN13_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1157 #define GPIO_OUTSET_PIN13_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1158
Kojto 91:031413cf7a89 1159 /* Bit 12 : Pin 12. */
Kojto 91:031413cf7a89 1160 #define GPIO_OUTSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 91:031413cf7a89 1161 #define GPIO_OUTSET_PIN12_Msk (0x1UL << GPIO_OUTSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 91:031413cf7a89 1162 #define GPIO_OUTSET_PIN12_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1163 #define GPIO_OUTSET_PIN12_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1164 #define GPIO_OUTSET_PIN12_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1165
Kojto 91:031413cf7a89 1166 /* Bit 11 : Pin 11. */
Kojto 91:031413cf7a89 1167 #define GPIO_OUTSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 91:031413cf7a89 1168 #define GPIO_OUTSET_PIN11_Msk (0x1UL << GPIO_OUTSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 91:031413cf7a89 1169 #define GPIO_OUTSET_PIN11_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1170 #define GPIO_OUTSET_PIN11_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1171 #define GPIO_OUTSET_PIN11_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1172
Kojto 91:031413cf7a89 1173 /* Bit 10 : Pin 10. */
Kojto 91:031413cf7a89 1174 #define GPIO_OUTSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 91:031413cf7a89 1175 #define GPIO_OUTSET_PIN10_Msk (0x1UL << GPIO_OUTSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 91:031413cf7a89 1176 #define GPIO_OUTSET_PIN10_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1177 #define GPIO_OUTSET_PIN10_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1178 #define GPIO_OUTSET_PIN10_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1179
Kojto 91:031413cf7a89 1180 /* Bit 9 : Pin 9. */
Kojto 91:031413cf7a89 1181 #define GPIO_OUTSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 91:031413cf7a89 1182 #define GPIO_OUTSET_PIN9_Msk (0x1UL << GPIO_OUTSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 91:031413cf7a89 1183 #define GPIO_OUTSET_PIN9_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1184 #define GPIO_OUTSET_PIN9_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1185 #define GPIO_OUTSET_PIN9_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1186
Kojto 91:031413cf7a89 1187 /* Bit 8 : Pin 8. */
Kojto 91:031413cf7a89 1188 #define GPIO_OUTSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 91:031413cf7a89 1189 #define GPIO_OUTSET_PIN8_Msk (0x1UL << GPIO_OUTSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 91:031413cf7a89 1190 #define GPIO_OUTSET_PIN8_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1191 #define GPIO_OUTSET_PIN8_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1192 #define GPIO_OUTSET_PIN8_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1193
Kojto 91:031413cf7a89 1194 /* Bit 7 : Pin 7. */
Kojto 91:031413cf7a89 1195 #define GPIO_OUTSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 91:031413cf7a89 1196 #define GPIO_OUTSET_PIN7_Msk (0x1UL << GPIO_OUTSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 91:031413cf7a89 1197 #define GPIO_OUTSET_PIN7_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1198 #define GPIO_OUTSET_PIN7_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1199 #define GPIO_OUTSET_PIN7_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1200
Kojto 91:031413cf7a89 1201 /* Bit 6 : Pin 6. */
Kojto 91:031413cf7a89 1202 #define GPIO_OUTSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 91:031413cf7a89 1203 #define GPIO_OUTSET_PIN6_Msk (0x1UL << GPIO_OUTSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 91:031413cf7a89 1204 #define GPIO_OUTSET_PIN6_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1205 #define GPIO_OUTSET_PIN6_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1206 #define GPIO_OUTSET_PIN6_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1207
Kojto 91:031413cf7a89 1208 /* Bit 5 : Pin 5. */
Kojto 91:031413cf7a89 1209 #define GPIO_OUTSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 91:031413cf7a89 1210 #define GPIO_OUTSET_PIN5_Msk (0x1UL << GPIO_OUTSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 91:031413cf7a89 1211 #define GPIO_OUTSET_PIN5_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1212 #define GPIO_OUTSET_PIN5_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1213 #define GPIO_OUTSET_PIN5_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1214
Kojto 91:031413cf7a89 1215 /* Bit 4 : Pin 4. */
Kojto 91:031413cf7a89 1216 #define GPIO_OUTSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 91:031413cf7a89 1217 #define GPIO_OUTSET_PIN4_Msk (0x1UL << GPIO_OUTSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 91:031413cf7a89 1218 #define GPIO_OUTSET_PIN4_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1219 #define GPIO_OUTSET_PIN4_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1220 #define GPIO_OUTSET_PIN4_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1221
Kojto 91:031413cf7a89 1222 /* Bit 3 : Pin 3. */
Kojto 91:031413cf7a89 1223 #define GPIO_OUTSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 91:031413cf7a89 1224 #define GPIO_OUTSET_PIN3_Msk (0x1UL << GPIO_OUTSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 91:031413cf7a89 1225 #define GPIO_OUTSET_PIN3_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1226 #define GPIO_OUTSET_PIN3_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1227 #define GPIO_OUTSET_PIN3_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1228
Kojto 91:031413cf7a89 1229 /* Bit 2 : Pin 2. */
Kojto 91:031413cf7a89 1230 #define GPIO_OUTSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 91:031413cf7a89 1231 #define GPIO_OUTSET_PIN2_Msk (0x1UL << GPIO_OUTSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 91:031413cf7a89 1232 #define GPIO_OUTSET_PIN2_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1233 #define GPIO_OUTSET_PIN2_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1234 #define GPIO_OUTSET_PIN2_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1235
Kojto 91:031413cf7a89 1236 /* Bit 1 : Pin 1. */
Kojto 91:031413cf7a89 1237 #define GPIO_OUTSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 91:031413cf7a89 1238 #define GPIO_OUTSET_PIN1_Msk (0x1UL << GPIO_OUTSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 91:031413cf7a89 1239 #define GPIO_OUTSET_PIN1_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1240 #define GPIO_OUTSET_PIN1_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1241 #define GPIO_OUTSET_PIN1_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1242
Kojto 91:031413cf7a89 1243 /* Bit 0 : Pin 0. */
Kojto 91:031413cf7a89 1244 #define GPIO_OUTSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 91:031413cf7a89 1245 #define GPIO_OUTSET_PIN0_Msk (0x1UL << GPIO_OUTSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 91:031413cf7a89 1246 #define GPIO_OUTSET_PIN0_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1247 #define GPIO_OUTSET_PIN0_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1248 #define GPIO_OUTSET_PIN0_Set (1UL) /*!< Set pin driver high. */
Kojto 91:031413cf7a89 1249
Kojto 91:031413cf7a89 1250 /* Register: GPIO_OUTCLR */
Kojto 91:031413cf7a89 1251 /* Description: Clear individual bits in GPIO port. */
Kojto 91:031413cf7a89 1252
Kojto 91:031413cf7a89 1253 /* Bit 31 : Pin 31. */
Kojto 91:031413cf7a89 1254 #define GPIO_OUTCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 91:031413cf7a89 1255 #define GPIO_OUTCLR_PIN31_Msk (0x1UL << GPIO_OUTCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 91:031413cf7a89 1256 #define GPIO_OUTCLR_PIN31_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1257 #define GPIO_OUTCLR_PIN31_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1258 #define GPIO_OUTCLR_PIN31_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1259
Kojto 91:031413cf7a89 1260 /* Bit 30 : Pin 30. */
Kojto 91:031413cf7a89 1261 #define GPIO_OUTCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 91:031413cf7a89 1262 #define GPIO_OUTCLR_PIN30_Msk (0x1UL << GPIO_OUTCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 91:031413cf7a89 1263 #define GPIO_OUTCLR_PIN30_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1264 #define GPIO_OUTCLR_PIN30_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1265 #define GPIO_OUTCLR_PIN30_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1266
Kojto 91:031413cf7a89 1267 /* Bit 29 : Pin 29. */
Kojto 91:031413cf7a89 1268 #define GPIO_OUTCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 91:031413cf7a89 1269 #define GPIO_OUTCLR_PIN29_Msk (0x1UL << GPIO_OUTCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 91:031413cf7a89 1270 #define GPIO_OUTCLR_PIN29_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1271 #define GPIO_OUTCLR_PIN29_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1272 #define GPIO_OUTCLR_PIN29_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1273
Kojto 91:031413cf7a89 1274 /* Bit 28 : Pin 28. */
Kojto 91:031413cf7a89 1275 #define GPIO_OUTCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 91:031413cf7a89 1276 #define GPIO_OUTCLR_PIN28_Msk (0x1UL << GPIO_OUTCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 91:031413cf7a89 1277 #define GPIO_OUTCLR_PIN28_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1278 #define GPIO_OUTCLR_PIN28_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1279 #define GPIO_OUTCLR_PIN28_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1280
Kojto 91:031413cf7a89 1281 /* Bit 27 : Pin 27. */
Kojto 91:031413cf7a89 1282 #define GPIO_OUTCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 91:031413cf7a89 1283 #define GPIO_OUTCLR_PIN27_Msk (0x1UL << GPIO_OUTCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 91:031413cf7a89 1284 #define GPIO_OUTCLR_PIN27_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1285 #define GPIO_OUTCLR_PIN27_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1286 #define GPIO_OUTCLR_PIN27_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1287
Kojto 91:031413cf7a89 1288 /* Bit 26 : Pin 26. */
Kojto 91:031413cf7a89 1289 #define GPIO_OUTCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 91:031413cf7a89 1290 #define GPIO_OUTCLR_PIN26_Msk (0x1UL << GPIO_OUTCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 91:031413cf7a89 1291 #define GPIO_OUTCLR_PIN26_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1292 #define GPIO_OUTCLR_PIN26_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1293 #define GPIO_OUTCLR_PIN26_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1294
Kojto 91:031413cf7a89 1295 /* Bit 25 : Pin 25. */
Kojto 91:031413cf7a89 1296 #define GPIO_OUTCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 91:031413cf7a89 1297 #define GPIO_OUTCLR_PIN25_Msk (0x1UL << GPIO_OUTCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 91:031413cf7a89 1298 #define GPIO_OUTCLR_PIN25_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1299 #define GPIO_OUTCLR_PIN25_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1300 #define GPIO_OUTCLR_PIN25_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1301
Kojto 91:031413cf7a89 1302 /* Bit 24 : Pin 24. */
Kojto 91:031413cf7a89 1303 #define GPIO_OUTCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 91:031413cf7a89 1304 #define GPIO_OUTCLR_PIN24_Msk (0x1UL << GPIO_OUTCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 91:031413cf7a89 1305 #define GPIO_OUTCLR_PIN24_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1306 #define GPIO_OUTCLR_PIN24_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1307 #define GPIO_OUTCLR_PIN24_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1308
Kojto 91:031413cf7a89 1309 /* Bit 23 : Pin 23. */
Kojto 91:031413cf7a89 1310 #define GPIO_OUTCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 91:031413cf7a89 1311 #define GPIO_OUTCLR_PIN23_Msk (0x1UL << GPIO_OUTCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 91:031413cf7a89 1312 #define GPIO_OUTCLR_PIN23_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1313 #define GPIO_OUTCLR_PIN23_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1314 #define GPIO_OUTCLR_PIN23_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1315
Kojto 91:031413cf7a89 1316 /* Bit 22 : Pin 22. */
Kojto 91:031413cf7a89 1317 #define GPIO_OUTCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 91:031413cf7a89 1318 #define GPIO_OUTCLR_PIN22_Msk (0x1UL << GPIO_OUTCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 91:031413cf7a89 1319 #define GPIO_OUTCLR_PIN22_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1320 #define GPIO_OUTCLR_PIN22_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1321 #define GPIO_OUTCLR_PIN22_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1322
Kojto 91:031413cf7a89 1323 /* Bit 21 : Pin 21. */
Kojto 91:031413cf7a89 1324 #define GPIO_OUTCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 91:031413cf7a89 1325 #define GPIO_OUTCLR_PIN21_Msk (0x1UL << GPIO_OUTCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 91:031413cf7a89 1326 #define GPIO_OUTCLR_PIN21_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1327 #define GPIO_OUTCLR_PIN21_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1328 #define GPIO_OUTCLR_PIN21_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1329
Kojto 91:031413cf7a89 1330 /* Bit 20 : Pin 20. */
Kojto 91:031413cf7a89 1331 #define GPIO_OUTCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 91:031413cf7a89 1332 #define GPIO_OUTCLR_PIN20_Msk (0x1UL << GPIO_OUTCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 91:031413cf7a89 1333 #define GPIO_OUTCLR_PIN20_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1334 #define GPIO_OUTCLR_PIN20_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1335 #define GPIO_OUTCLR_PIN20_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1336
Kojto 91:031413cf7a89 1337 /* Bit 19 : Pin 19. */
Kojto 91:031413cf7a89 1338 #define GPIO_OUTCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 91:031413cf7a89 1339 #define GPIO_OUTCLR_PIN19_Msk (0x1UL << GPIO_OUTCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 91:031413cf7a89 1340 #define GPIO_OUTCLR_PIN19_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1341 #define GPIO_OUTCLR_PIN19_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1342 #define GPIO_OUTCLR_PIN19_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1343
Kojto 91:031413cf7a89 1344 /* Bit 18 : Pin 18. */
Kojto 91:031413cf7a89 1345 #define GPIO_OUTCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 91:031413cf7a89 1346 #define GPIO_OUTCLR_PIN18_Msk (0x1UL << GPIO_OUTCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 91:031413cf7a89 1347 #define GPIO_OUTCLR_PIN18_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1348 #define GPIO_OUTCLR_PIN18_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1349 #define GPIO_OUTCLR_PIN18_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1350
Kojto 91:031413cf7a89 1351 /* Bit 17 : Pin 17. */
Kojto 91:031413cf7a89 1352 #define GPIO_OUTCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 91:031413cf7a89 1353 #define GPIO_OUTCLR_PIN17_Msk (0x1UL << GPIO_OUTCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 91:031413cf7a89 1354 #define GPIO_OUTCLR_PIN17_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1355 #define GPIO_OUTCLR_PIN17_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1356 #define GPIO_OUTCLR_PIN17_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1357
Kojto 91:031413cf7a89 1358 /* Bit 16 : Pin 16. */
Kojto 91:031413cf7a89 1359 #define GPIO_OUTCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 91:031413cf7a89 1360 #define GPIO_OUTCLR_PIN16_Msk (0x1UL << GPIO_OUTCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 91:031413cf7a89 1361 #define GPIO_OUTCLR_PIN16_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1362 #define GPIO_OUTCLR_PIN16_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1363 #define GPIO_OUTCLR_PIN16_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1364
Kojto 91:031413cf7a89 1365 /* Bit 15 : Pin 15. */
Kojto 91:031413cf7a89 1366 #define GPIO_OUTCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 91:031413cf7a89 1367 #define GPIO_OUTCLR_PIN15_Msk (0x1UL << GPIO_OUTCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 91:031413cf7a89 1368 #define GPIO_OUTCLR_PIN15_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1369 #define GPIO_OUTCLR_PIN15_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1370 #define GPIO_OUTCLR_PIN15_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1371
Kojto 91:031413cf7a89 1372 /* Bit 14 : Pin 14. */
Kojto 91:031413cf7a89 1373 #define GPIO_OUTCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 91:031413cf7a89 1374 #define GPIO_OUTCLR_PIN14_Msk (0x1UL << GPIO_OUTCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 91:031413cf7a89 1375 #define GPIO_OUTCLR_PIN14_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1376 #define GPIO_OUTCLR_PIN14_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1377 #define GPIO_OUTCLR_PIN14_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1378
Kojto 91:031413cf7a89 1379 /* Bit 13 : Pin 13. */
Kojto 91:031413cf7a89 1380 #define GPIO_OUTCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 91:031413cf7a89 1381 #define GPIO_OUTCLR_PIN13_Msk (0x1UL << GPIO_OUTCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 91:031413cf7a89 1382 #define GPIO_OUTCLR_PIN13_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1383 #define GPIO_OUTCLR_PIN13_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1384 #define GPIO_OUTCLR_PIN13_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1385
Kojto 91:031413cf7a89 1386 /* Bit 12 : Pin 12. */
Kojto 91:031413cf7a89 1387 #define GPIO_OUTCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 91:031413cf7a89 1388 #define GPIO_OUTCLR_PIN12_Msk (0x1UL << GPIO_OUTCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 91:031413cf7a89 1389 #define GPIO_OUTCLR_PIN12_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1390 #define GPIO_OUTCLR_PIN12_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1391 #define GPIO_OUTCLR_PIN12_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1392
Kojto 91:031413cf7a89 1393 /* Bit 11 : Pin 11. */
Kojto 91:031413cf7a89 1394 #define GPIO_OUTCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 91:031413cf7a89 1395 #define GPIO_OUTCLR_PIN11_Msk (0x1UL << GPIO_OUTCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 91:031413cf7a89 1396 #define GPIO_OUTCLR_PIN11_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1397 #define GPIO_OUTCLR_PIN11_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1398 #define GPIO_OUTCLR_PIN11_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1399
Kojto 91:031413cf7a89 1400 /* Bit 10 : Pin 10. */
Kojto 91:031413cf7a89 1401 #define GPIO_OUTCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 91:031413cf7a89 1402 #define GPIO_OUTCLR_PIN10_Msk (0x1UL << GPIO_OUTCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 91:031413cf7a89 1403 #define GPIO_OUTCLR_PIN10_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1404 #define GPIO_OUTCLR_PIN10_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1405 #define GPIO_OUTCLR_PIN10_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1406
Kojto 91:031413cf7a89 1407 /* Bit 9 : Pin 9. */
Kojto 91:031413cf7a89 1408 #define GPIO_OUTCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 91:031413cf7a89 1409 #define GPIO_OUTCLR_PIN9_Msk (0x1UL << GPIO_OUTCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 91:031413cf7a89 1410 #define GPIO_OUTCLR_PIN9_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1411 #define GPIO_OUTCLR_PIN9_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1412 #define GPIO_OUTCLR_PIN9_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1413
Kojto 91:031413cf7a89 1414 /* Bit 8 : Pin 8. */
Kojto 91:031413cf7a89 1415 #define GPIO_OUTCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 91:031413cf7a89 1416 #define GPIO_OUTCLR_PIN8_Msk (0x1UL << GPIO_OUTCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 91:031413cf7a89 1417 #define GPIO_OUTCLR_PIN8_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1418 #define GPIO_OUTCLR_PIN8_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1419 #define GPIO_OUTCLR_PIN8_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1420
Kojto 91:031413cf7a89 1421 /* Bit 7 : Pin 7. */
Kojto 91:031413cf7a89 1422 #define GPIO_OUTCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 91:031413cf7a89 1423 #define GPIO_OUTCLR_PIN7_Msk (0x1UL << GPIO_OUTCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 91:031413cf7a89 1424 #define GPIO_OUTCLR_PIN7_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1425 #define GPIO_OUTCLR_PIN7_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1426 #define GPIO_OUTCLR_PIN7_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1427
Kojto 91:031413cf7a89 1428 /* Bit 6 : Pin 6. */
Kojto 91:031413cf7a89 1429 #define GPIO_OUTCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 91:031413cf7a89 1430 #define GPIO_OUTCLR_PIN6_Msk (0x1UL << GPIO_OUTCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 91:031413cf7a89 1431 #define GPIO_OUTCLR_PIN6_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1432 #define GPIO_OUTCLR_PIN6_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1433 #define GPIO_OUTCLR_PIN6_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1434
Kojto 91:031413cf7a89 1435 /* Bit 5 : Pin 5. */
Kojto 91:031413cf7a89 1436 #define GPIO_OUTCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 91:031413cf7a89 1437 #define GPIO_OUTCLR_PIN5_Msk (0x1UL << GPIO_OUTCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 91:031413cf7a89 1438 #define GPIO_OUTCLR_PIN5_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1439 #define GPIO_OUTCLR_PIN5_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1440 #define GPIO_OUTCLR_PIN5_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1441
Kojto 91:031413cf7a89 1442 /* Bit 4 : Pin 4. */
Kojto 91:031413cf7a89 1443 #define GPIO_OUTCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 91:031413cf7a89 1444 #define GPIO_OUTCLR_PIN4_Msk (0x1UL << GPIO_OUTCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 91:031413cf7a89 1445 #define GPIO_OUTCLR_PIN4_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1446 #define GPIO_OUTCLR_PIN4_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1447 #define GPIO_OUTCLR_PIN4_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1448
Kojto 91:031413cf7a89 1449 /* Bit 3 : Pin 3. */
Kojto 91:031413cf7a89 1450 #define GPIO_OUTCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 91:031413cf7a89 1451 #define GPIO_OUTCLR_PIN3_Msk (0x1UL << GPIO_OUTCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 91:031413cf7a89 1452 #define GPIO_OUTCLR_PIN3_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1453 #define GPIO_OUTCLR_PIN3_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1454 #define GPIO_OUTCLR_PIN3_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1455
Kojto 91:031413cf7a89 1456 /* Bit 2 : Pin 2. */
Kojto 91:031413cf7a89 1457 #define GPIO_OUTCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 91:031413cf7a89 1458 #define GPIO_OUTCLR_PIN2_Msk (0x1UL << GPIO_OUTCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 91:031413cf7a89 1459 #define GPIO_OUTCLR_PIN2_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1460 #define GPIO_OUTCLR_PIN2_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1461 #define GPIO_OUTCLR_PIN2_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1462
Kojto 91:031413cf7a89 1463 /* Bit 1 : Pin 1. */
Kojto 91:031413cf7a89 1464 #define GPIO_OUTCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 91:031413cf7a89 1465 #define GPIO_OUTCLR_PIN1_Msk (0x1UL << GPIO_OUTCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 91:031413cf7a89 1466 #define GPIO_OUTCLR_PIN1_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1467 #define GPIO_OUTCLR_PIN1_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1468 #define GPIO_OUTCLR_PIN1_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1469
Kojto 91:031413cf7a89 1470 /* Bit 0 : Pin 0. */
Kojto 91:031413cf7a89 1471 #define GPIO_OUTCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 91:031413cf7a89 1472 #define GPIO_OUTCLR_PIN0_Msk (0x1UL << GPIO_OUTCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 91:031413cf7a89 1473 #define GPIO_OUTCLR_PIN0_Low (0UL) /*!< Pin driver is low. */
Kojto 91:031413cf7a89 1474 #define GPIO_OUTCLR_PIN0_High (1UL) /*!< Pin driver is high. */
Kojto 91:031413cf7a89 1475 #define GPIO_OUTCLR_PIN0_Clear (1UL) /*!< Set pin driver low. */
Kojto 91:031413cf7a89 1476
Kojto 91:031413cf7a89 1477 /* Register: GPIO_IN */
Kojto 91:031413cf7a89 1478 /* Description: Read GPIO port. */
Kojto 91:031413cf7a89 1479
Kojto 91:031413cf7a89 1480 /* Bit 31 : Pin 31. */
Kojto 91:031413cf7a89 1481 #define GPIO_IN_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 91:031413cf7a89 1482 #define GPIO_IN_PIN31_Msk (0x1UL << GPIO_IN_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 91:031413cf7a89 1483 #define GPIO_IN_PIN31_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1484 #define GPIO_IN_PIN31_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1485
Kojto 91:031413cf7a89 1486 /* Bit 30 : Pin 30. */
Kojto 91:031413cf7a89 1487 #define GPIO_IN_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 91:031413cf7a89 1488 #define GPIO_IN_PIN30_Msk (0x1UL << GPIO_IN_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 91:031413cf7a89 1489 #define GPIO_IN_PIN30_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1490 #define GPIO_IN_PIN30_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1491
Kojto 91:031413cf7a89 1492 /* Bit 29 : Pin 29. */
Kojto 91:031413cf7a89 1493 #define GPIO_IN_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 91:031413cf7a89 1494 #define GPIO_IN_PIN29_Msk (0x1UL << GPIO_IN_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 91:031413cf7a89 1495 #define GPIO_IN_PIN29_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1496 #define GPIO_IN_PIN29_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1497
Kojto 91:031413cf7a89 1498 /* Bit 28 : Pin 28. */
Kojto 91:031413cf7a89 1499 #define GPIO_IN_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 91:031413cf7a89 1500 #define GPIO_IN_PIN28_Msk (0x1UL << GPIO_IN_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 91:031413cf7a89 1501 #define GPIO_IN_PIN28_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1502 #define GPIO_IN_PIN28_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1503
Kojto 91:031413cf7a89 1504 /* Bit 27 : Pin 27. */
Kojto 91:031413cf7a89 1505 #define GPIO_IN_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 91:031413cf7a89 1506 #define GPIO_IN_PIN27_Msk (0x1UL << GPIO_IN_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 91:031413cf7a89 1507 #define GPIO_IN_PIN27_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1508 #define GPIO_IN_PIN27_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1509
Kojto 91:031413cf7a89 1510 /* Bit 26 : Pin 26. */
Kojto 91:031413cf7a89 1511 #define GPIO_IN_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 91:031413cf7a89 1512 #define GPIO_IN_PIN26_Msk (0x1UL << GPIO_IN_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 91:031413cf7a89 1513 #define GPIO_IN_PIN26_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1514 #define GPIO_IN_PIN26_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1515
Kojto 91:031413cf7a89 1516 /* Bit 25 : Pin 25. */
Kojto 91:031413cf7a89 1517 #define GPIO_IN_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 91:031413cf7a89 1518 #define GPIO_IN_PIN25_Msk (0x1UL << GPIO_IN_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 91:031413cf7a89 1519 #define GPIO_IN_PIN25_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1520 #define GPIO_IN_PIN25_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1521
Kojto 91:031413cf7a89 1522 /* Bit 24 : Pin 24. */
Kojto 91:031413cf7a89 1523 #define GPIO_IN_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 91:031413cf7a89 1524 #define GPIO_IN_PIN24_Msk (0x1UL << GPIO_IN_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 91:031413cf7a89 1525 #define GPIO_IN_PIN24_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1526 #define GPIO_IN_PIN24_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1527
Kojto 91:031413cf7a89 1528 /* Bit 23 : Pin 23. */
Kojto 91:031413cf7a89 1529 #define GPIO_IN_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 91:031413cf7a89 1530 #define GPIO_IN_PIN23_Msk (0x1UL << GPIO_IN_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 91:031413cf7a89 1531 #define GPIO_IN_PIN23_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1532 #define GPIO_IN_PIN23_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1533
Kojto 91:031413cf7a89 1534 /* Bit 22 : Pin 22. */
Kojto 91:031413cf7a89 1535 #define GPIO_IN_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 91:031413cf7a89 1536 #define GPIO_IN_PIN22_Msk (0x1UL << GPIO_IN_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 91:031413cf7a89 1537 #define GPIO_IN_PIN22_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1538 #define GPIO_IN_PIN22_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1539
Kojto 91:031413cf7a89 1540 /* Bit 21 : Pin 21. */
Kojto 91:031413cf7a89 1541 #define GPIO_IN_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 91:031413cf7a89 1542 #define GPIO_IN_PIN21_Msk (0x1UL << GPIO_IN_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 91:031413cf7a89 1543 #define GPIO_IN_PIN21_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1544 #define GPIO_IN_PIN21_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1545
Kojto 91:031413cf7a89 1546 /* Bit 20 : Pin 20. */
Kojto 91:031413cf7a89 1547 #define GPIO_IN_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 91:031413cf7a89 1548 #define GPIO_IN_PIN20_Msk (0x1UL << GPIO_IN_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 91:031413cf7a89 1549 #define GPIO_IN_PIN20_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1550 #define GPIO_IN_PIN20_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1551
Kojto 91:031413cf7a89 1552 /* Bit 19 : Pin 19. */
Kojto 91:031413cf7a89 1553 #define GPIO_IN_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 91:031413cf7a89 1554 #define GPIO_IN_PIN19_Msk (0x1UL << GPIO_IN_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 91:031413cf7a89 1555 #define GPIO_IN_PIN19_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1556 #define GPIO_IN_PIN19_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1557
Kojto 91:031413cf7a89 1558 /* Bit 18 : Pin 18. */
Kojto 91:031413cf7a89 1559 #define GPIO_IN_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 91:031413cf7a89 1560 #define GPIO_IN_PIN18_Msk (0x1UL << GPIO_IN_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 91:031413cf7a89 1561 #define GPIO_IN_PIN18_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1562 #define GPIO_IN_PIN18_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1563
Kojto 91:031413cf7a89 1564 /* Bit 17 : Pin 17. */
Kojto 91:031413cf7a89 1565 #define GPIO_IN_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 91:031413cf7a89 1566 #define GPIO_IN_PIN17_Msk (0x1UL << GPIO_IN_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 91:031413cf7a89 1567 #define GPIO_IN_PIN17_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1568 #define GPIO_IN_PIN17_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1569
Kojto 91:031413cf7a89 1570 /* Bit 16 : Pin 16. */
Kojto 91:031413cf7a89 1571 #define GPIO_IN_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 91:031413cf7a89 1572 #define GPIO_IN_PIN16_Msk (0x1UL << GPIO_IN_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 91:031413cf7a89 1573 #define GPIO_IN_PIN16_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1574 #define GPIO_IN_PIN16_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1575
Kojto 91:031413cf7a89 1576 /* Bit 15 : Pin 15. */
Kojto 91:031413cf7a89 1577 #define GPIO_IN_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 91:031413cf7a89 1578 #define GPIO_IN_PIN15_Msk (0x1UL << GPIO_IN_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 91:031413cf7a89 1579 #define GPIO_IN_PIN15_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1580 #define GPIO_IN_PIN15_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1581
Kojto 91:031413cf7a89 1582 /* Bit 14 : Pin 14. */
Kojto 91:031413cf7a89 1583 #define GPIO_IN_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 91:031413cf7a89 1584 #define GPIO_IN_PIN14_Msk (0x1UL << GPIO_IN_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 91:031413cf7a89 1585 #define GPIO_IN_PIN14_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1586 #define GPIO_IN_PIN14_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1587
Kojto 91:031413cf7a89 1588 /* Bit 13 : Pin 13. */
Kojto 91:031413cf7a89 1589 #define GPIO_IN_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 91:031413cf7a89 1590 #define GPIO_IN_PIN13_Msk (0x1UL << GPIO_IN_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 91:031413cf7a89 1591 #define GPIO_IN_PIN13_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1592 #define GPIO_IN_PIN13_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1593
Kojto 91:031413cf7a89 1594 /* Bit 12 : Pin 12. */
Kojto 91:031413cf7a89 1595 #define GPIO_IN_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 91:031413cf7a89 1596 #define GPIO_IN_PIN12_Msk (0x1UL << GPIO_IN_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 91:031413cf7a89 1597 #define GPIO_IN_PIN12_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1598 #define GPIO_IN_PIN12_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1599
Kojto 91:031413cf7a89 1600 /* Bit 11 : Pin 11. */
Kojto 91:031413cf7a89 1601 #define GPIO_IN_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 91:031413cf7a89 1602 #define GPIO_IN_PIN11_Msk (0x1UL << GPIO_IN_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 91:031413cf7a89 1603 #define GPIO_IN_PIN11_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1604 #define GPIO_IN_PIN11_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1605
Kojto 91:031413cf7a89 1606 /* Bit 10 : Pin 10. */
Kojto 91:031413cf7a89 1607 #define GPIO_IN_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 91:031413cf7a89 1608 #define GPIO_IN_PIN10_Msk (0x1UL << GPIO_IN_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 91:031413cf7a89 1609 #define GPIO_IN_PIN10_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1610 #define GPIO_IN_PIN10_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1611
Kojto 91:031413cf7a89 1612 /* Bit 9 : Pin 9. */
Kojto 91:031413cf7a89 1613 #define GPIO_IN_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 91:031413cf7a89 1614 #define GPIO_IN_PIN9_Msk (0x1UL << GPIO_IN_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 91:031413cf7a89 1615 #define GPIO_IN_PIN9_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1616 #define GPIO_IN_PIN9_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1617
Kojto 91:031413cf7a89 1618 /* Bit 8 : Pin 8. */
Kojto 91:031413cf7a89 1619 #define GPIO_IN_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 91:031413cf7a89 1620 #define GPIO_IN_PIN8_Msk (0x1UL << GPIO_IN_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 91:031413cf7a89 1621 #define GPIO_IN_PIN8_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1622 #define GPIO_IN_PIN8_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1623
Kojto 91:031413cf7a89 1624 /* Bit 7 : Pin 7. */
Kojto 91:031413cf7a89 1625 #define GPIO_IN_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 91:031413cf7a89 1626 #define GPIO_IN_PIN7_Msk (0x1UL << GPIO_IN_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 91:031413cf7a89 1627 #define GPIO_IN_PIN7_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1628 #define GPIO_IN_PIN7_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1629
Kojto 91:031413cf7a89 1630 /* Bit 6 : Pin 6. */
Kojto 91:031413cf7a89 1631 #define GPIO_IN_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 91:031413cf7a89 1632 #define GPIO_IN_PIN6_Msk (0x1UL << GPIO_IN_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 91:031413cf7a89 1633 #define GPIO_IN_PIN6_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1634 #define GPIO_IN_PIN6_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1635
Kojto 91:031413cf7a89 1636 /* Bit 5 : Pin 5. */
Kojto 91:031413cf7a89 1637 #define GPIO_IN_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 91:031413cf7a89 1638 #define GPIO_IN_PIN5_Msk (0x1UL << GPIO_IN_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 91:031413cf7a89 1639 #define GPIO_IN_PIN5_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1640 #define GPIO_IN_PIN5_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1641
Kojto 91:031413cf7a89 1642 /* Bit 4 : Pin 4. */
Kojto 91:031413cf7a89 1643 #define GPIO_IN_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 91:031413cf7a89 1644 #define GPIO_IN_PIN4_Msk (0x1UL << GPIO_IN_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 91:031413cf7a89 1645 #define GPIO_IN_PIN4_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1646 #define GPIO_IN_PIN4_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1647
Kojto 91:031413cf7a89 1648 /* Bit 3 : Pin 3. */
Kojto 91:031413cf7a89 1649 #define GPIO_IN_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 91:031413cf7a89 1650 #define GPIO_IN_PIN3_Msk (0x1UL << GPIO_IN_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 91:031413cf7a89 1651 #define GPIO_IN_PIN3_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1652 #define GPIO_IN_PIN3_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1653
Kojto 91:031413cf7a89 1654 /* Bit 2 : Pin 2. */
Kojto 91:031413cf7a89 1655 #define GPIO_IN_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 91:031413cf7a89 1656 #define GPIO_IN_PIN2_Msk (0x1UL << GPIO_IN_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 91:031413cf7a89 1657 #define GPIO_IN_PIN2_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1658 #define GPIO_IN_PIN2_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1659
Kojto 91:031413cf7a89 1660 /* Bit 1 : Pin 1. */
Kojto 91:031413cf7a89 1661 #define GPIO_IN_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 91:031413cf7a89 1662 #define GPIO_IN_PIN1_Msk (0x1UL << GPIO_IN_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 91:031413cf7a89 1663 #define GPIO_IN_PIN1_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1664 #define GPIO_IN_PIN1_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1665
Kojto 91:031413cf7a89 1666 /* Bit 0 : Pin 0. */
Kojto 91:031413cf7a89 1667 #define GPIO_IN_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 91:031413cf7a89 1668 #define GPIO_IN_PIN0_Msk (0x1UL << GPIO_IN_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 91:031413cf7a89 1669 #define GPIO_IN_PIN0_Low (0UL) /*!< Pin input is low. */
Kojto 91:031413cf7a89 1670 #define GPIO_IN_PIN0_High (1UL) /*!< Pin input is high. */
Kojto 91:031413cf7a89 1671
Kojto 91:031413cf7a89 1672 /* Register: GPIO_DIR */
Kojto 91:031413cf7a89 1673 /* Description: Direction of GPIO pins. */
Kojto 91:031413cf7a89 1674
Kojto 91:031413cf7a89 1675 /* Bit 31 : Pin 31. */
Kojto 91:031413cf7a89 1676 #define GPIO_DIR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 91:031413cf7a89 1677 #define GPIO_DIR_PIN31_Msk (0x1UL << GPIO_DIR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 91:031413cf7a89 1678 #define GPIO_DIR_PIN31_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1679 #define GPIO_DIR_PIN31_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1680
Kojto 91:031413cf7a89 1681 /* Bit 30 : Pin 30. */
Kojto 91:031413cf7a89 1682 #define GPIO_DIR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 91:031413cf7a89 1683 #define GPIO_DIR_PIN30_Msk (0x1UL << GPIO_DIR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 91:031413cf7a89 1684 #define GPIO_DIR_PIN30_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1685 #define GPIO_DIR_PIN30_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1686
Kojto 91:031413cf7a89 1687 /* Bit 29 : Pin 29. */
Kojto 91:031413cf7a89 1688 #define GPIO_DIR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 91:031413cf7a89 1689 #define GPIO_DIR_PIN29_Msk (0x1UL << GPIO_DIR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 91:031413cf7a89 1690 #define GPIO_DIR_PIN29_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1691 #define GPIO_DIR_PIN29_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1692
Kojto 91:031413cf7a89 1693 /* Bit 28 : Pin 28. */
Kojto 91:031413cf7a89 1694 #define GPIO_DIR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 91:031413cf7a89 1695 #define GPIO_DIR_PIN28_Msk (0x1UL << GPIO_DIR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 91:031413cf7a89 1696 #define GPIO_DIR_PIN28_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1697 #define GPIO_DIR_PIN28_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1698
Kojto 91:031413cf7a89 1699 /* Bit 27 : Pin 27. */
Kojto 91:031413cf7a89 1700 #define GPIO_DIR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 91:031413cf7a89 1701 #define GPIO_DIR_PIN27_Msk (0x1UL << GPIO_DIR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 91:031413cf7a89 1702 #define GPIO_DIR_PIN27_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1703 #define GPIO_DIR_PIN27_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1704
Kojto 91:031413cf7a89 1705 /* Bit 26 : Pin 26. */
Kojto 91:031413cf7a89 1706 #define GPIO_DIR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 91:031413cf7a89 1707 #define GPIO_DIR_PIN26_Msk (0x1UL << GPIO_DIR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 91:031413cf7a89 1708 #define GPIO_DIR_PIN26_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1709 #define GPIO_DIR_PIN26_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1710
Kojto 91:031413cf7a89 1711 /* Bit 25 : Pin 25. */
Kojto 91:031413cf7a89 1712 #define GPIO_DIR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 91:031413cf7a89 1713 #define GPIO_DIR_PIN25_Msk (0x1UL << GPIO_DIR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 91:031413cf7a89 1714 #define GPIO_DIR_PIN25_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1715 #define GPIO_DIR_PIN25_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1716
Kojto 91:031413cf7a89 1717 /* Bit 24 : Pin 24. */
Kojto 91:031413cf7a89 1718 #define GPIO_DIR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 91:031413cf7a89 1719 #define GPIO_DIR_PIN24_Msk (0x1UL << GPIO_DIR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 91:031413cf7a89 1720 #define GPIO_DIR_PIN24_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1721 #define GPIO_DIR_PIN24_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1722
Kojto 91:031413cf7a89 1723 /* Bit 23 : Pin 23. */
Kojto 91:031413cf7a89 1724 #define GPIO_DIR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 91:031413cf7a89 1725 #define GPIO_DIR_PIN23_Msk (0x1UL << GPIO_DIR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 91:031413cf7a89 1726 #define GPIO_DIR_PIN23_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1727 #define GPIO_DIR_PIN23_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1728
Kojto 91:031413cf7a89 1729 /* Bit 22 : Pin 22. */
Kojto 91:031413cf7a89 1730 #define GPIO_DIR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 91:031413cf7a89 1731 #define GPIO_DIR_PIN22_Msk (0x1UL << GPIO_DIR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 91:031413cf7a89 1732 #define GPIO_DIR_PIN22_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1733 #define GPIO_DIR_PIN22_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1734
Kojto 91:031413cf7a89 1735 /* Bit 21 : Pin 21. */
Kojto 91:031413cf7a89 1736 #define GPIO_DIR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 91:031413cf7a89 1737 #define GPIO_DIR_PIN21_Msk (0x1UL << GPIO_DIR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 91:031413cf7a89 1738 #define GPIO_DIR_PIN21_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1739 #define GPIO_DIR_PIN21_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1740
Kojto 91:031413cf7a89 1741 /* Bit 20 : Pin 20. */
Kojto 91:031413cf7a89 1742 #define GPIO_DIR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 91:031413cf7a89 1743 #define GPIO_DIR_PIN20_Msk (0x1UL << GPIO_DIR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 91:031413cf7a89 1744 #define GPIO_DIR_PIN20_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1745 #define GPIO_DIR_PIN20_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1746
Kojto 91:031413cf7a89 1747 /* Bit 19 : Pin 19. */
Kojto 91:031413cf7a89 1748 #define GPIO_DIR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 91:031413cf7a89 1749 #define GPIO_DIR_PIN19_Msk (0x1UL << GPIO_DIR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 91:031413cf7a89 1750 #define GPIO_DIR_PIN19_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1751 #define GPIO_DIR_PIN19_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1752
Kojto 91:031413cf7a89 1753 /* Bit 18 : Pin 18. */
Kojto 91:031413cf7a89 1754 #define GPIO_DIR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 91:031413cf7a89 1755 #define GPIO_DIR_PIN18_Msk (0x1UL << GPIO_DIR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 91:031413cf7a89 1756 #define GPIO_DIR_PIN18_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1757 #define GPIO_DIR_PIN18_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1758
Kojto 91:031413cf7a89 1759 /* Bit 17 : Pin 17. */
Kojto 91:031413cf7a89 1760 #define GPIO_DIR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 91:031413cf7a89 1761 #define GPIO_DIR_PIN17_Msk (0x1UL << GPIO_DIR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 91:031413cf7a89 1762 #define GPIO_DIR_PIN17_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1763 #define GPIO_DIR_PIN17_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1764
Kojto 91:031413cf7a89 1765 /* Bit 16 : Pin 16. */
Kojto 91:031413cf7a89 1766 #define GPIO_DIR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 91:031413cf7a89 1767 #define GPIO_DIR_PIN16_Msk (0x1UL << GPIO_DIR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 91:031413cf7a89 1768 #define GPIO_DIR_PIN16_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1769 #define GPIO_DIR_PIN16_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1770
Kojto 91:031413cf7a89 1771 /* Bit 15 : Pin 15. */
Kojto 91:031413cf7a89 1772 #define GPIO_DIR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 91:031413cf7a89 1773 #define GPIO_DIR_PIN15_Msk (0x1UL << GPIO_DIR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 91:031413cf7a89 1774 #define GPIO_DIR_PIN15_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1775 #define GPIO_DIR_PIN15_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1776
Kojto 91:031413cf7a89 1777 /* Bit 14 : Pin 14. */
Kojto 91:031413cf7a89 1778 #define GPIO_DIR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 91:031413cf7a89 1779 #define GPIO_DIR_PIN14_Msk (0x1UL << GPIO_DIR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 91:031413cf7a89 1780 #define GPIO_DIR_PIN14_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1781 #define GPIO_DIR_PIN14_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1782
Kojto 91:031413cf7a89 1783 /* Bit 13 : Pin 13. */
Kojto 91:031413cf7a89 1784 #define GPIO_DIR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 91:031413cf7a89 1785 #define GPIO_DIR_PIN13_Msk (0x1UL << GPIO_DIR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 91:031413cf7a89 1786 #define GPIO_DIR_PIN13_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1787 #define GPIO_DIR_PIN13_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1788
Kojto 91:031413cf7a89 1789 /* Bit 12 : Pin 12. */
Kojto 91:031413cf7a89 1790 #define GPIO_DIR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 91:031413cf7a89 1791 #define GPIO_DIR_PIN12_Msk (0x1UL << GPIO_DIR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 91:031413cf7a89 1792 #define GPIO_DIR_PIN12_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1793 #define GPIO_DIR_PIN12_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1794
Kojto 91:031413cf7a89 1795 /* Bit 11 : Pin 11. */
Kojto 91:031413cf7a89 1796 #define GPIO_DIR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 91:031413cf7a89 1797 #define GPIO_DIR_PIN11_Msk (0x1UL << GPIO_DIR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 91:031413cf7a89 1798 #define GPIO_DIR_PIN11_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1799 #define GPIO_DIR_PIN11_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1800
Kojto 91:031413cf7a89 1801 /* Bit 10 : Pin 10. */
Kojto 91:031413cf7a89 1802 #define GPIO_DIR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 91:031413cf7a89 1803 #define GPIO_DIR_PIN10_Msk (0x1UL << GPIO_DIR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 91:031413cf7a89 1804 #define GPIO_DIR_PIN10_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1805 #define GPIO_DIR_PIN10_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1806
Kojto 91:031413cf7a89 1807 /* Bit 9 : Pin 9. */
Kojto 91:031413cf7a89 1808 #define GPIO_DIR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 91:031413cf7a89 1809 #define GPIO_DIR_PIN9_Msk (0x1UL << GPIO_DIR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 91:031413cf7a89 1810 #define GPIO_DIR_PIN9_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1811 #define GPIO_DIR_PIN9_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1812
Kojto 91:031413cf7a89 1813 /* Bit 8 : Pin 8. */
Kojto 91:031413cf7a89 1814 #define GPIO_DIR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 91:031413cf7a89 1815 #define GPIO_DIR_PIN8_Msk (0x1UL << GPIO_DIR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 91:031413cf7a89 1816 #define GPIO_DIR_PIN8_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1817 #define GPIO_DIR_PIN8_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1818
Kojto 91:031413cf7a89 1819 /* Bit 7 : Pin 7. */
Kojto 91:031413cf7a89 1820 #define GPIO_DIR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 91:031413cf7a89 1821 #define GPIO_DIR_PIN7_Msk (0x1UL << GPIO_DIR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 91:031413cf7a89 1822 #define GPIO_DIR_PIN7_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1823 #define GPIO_DIR_PIN7_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1824
Kojto 91:031413cf7a89 1825 /* Bit 6 : Pin 6. */
Kojto 91:031413cf7a89 1826 #define GPIO_DIR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 91:031413cf7a89 1827 #define GPIO_DIR_PIN6_Msk (0x1UL << GPIO_DIR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 91:031413cf7a89 1828 #define GPIO_DIR_PIN6_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1829 #define GPIO_DIR_PIN6_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1830
Kojto 91:031413cf7a89 1831 /* Bit 5 : Pin 5. */
Kojto 91:031413cf7a89 1832 #define GPIO_DIR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 91:031413cf7a89 1833 #define GPIO_DIR_PIN5_Msk (0x1UL << GPIO_DIR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 91:031413cf7a89 1834 #define GPIO_DIR_PIN5_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1835 #define GPIO_DIR_PIN5_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1836
Kojto 91:031413cf7a89 1837 /* Bit 4 : Pin 4. */
Kojto 91:031413cf7a89 1838 #define GPIO_DIR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 91:031413cf7a89 1839 #define GPIO_DIR_PIN4_Msk (0x1UL << GPIO_DIR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 91:031413cf7a89 1840 #define GPIO_DIR_PIN4_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1841 #define GPIO_DIR_PIN4_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1842
Kojto 91:031413cf7a89 1843 /* Bit 3 : Pin 3. */
Kojto 91:031413cf7a89 1844 #define GPIO_DIR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 91:031413cf7a89 1845 #define GPIO_DIR_PIN3_Msk (0x1UL << GPIO_DIR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 91:031413cf7a89 1846 #define GPIO_DIR_PIN3_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1847 #define GPIO_DIR_PIN3_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1848
Kojto 91:031413cf7a89 1849 /* Bit 2 : Pin 2. */
Kojto 91:031413cf7a89 1850 #define GPIO_DIR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 91:031413cf7a89 1851 #define GPIO_DIR_PIN2_Msk (0x1UL << GPIO_DIR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 91:031413cf7a89 1852 #define GPIO_DIR_PIN2_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1853 #define GPIO_DIR_PIN2_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1854
Kojto 91:031413cf7a89 1855 /* Bit 1 : Pin 1. */
Kojto 91:031413cf7a89 1856 #define GPIO_DIR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 91:031413cf7a89 1857 #define GPIO_DIR_PIN1_Msk (0x1UL << GPIO_DIR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 91:031413cf7a89 1858 #define GPIO_DIR_PIN1_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1859 #define GPIO_DIR_PIN1_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1860
Kojto 91:031413cf7a89 1861 /* Bit 0 : Pin 0. */
Kojto 91:031413cf7a89 1862 #define GPIO_DIR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 91:031413cf7a89 1863 #define GPIO_DIR_PIN0_Msk (0x1UL << GPIO_DIR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 91:031413cf7a89 1864 #define GPIO_DIR_PIN0_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1865 #define GPIO_DIR_PIN0_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1866
Kojto 91:031413cf7a89 1867 /* Register: GPIO_DIRSET */
Kojto 91:031413cf7a89 1868 /* Description: DIR set register. */
Kojto 91:031413cf7a89 1869
Kojto 91:031413cf7a89 1870 /* Bit 31 : Set as output pin 31. */
Kojto 91:031413cf7a89 1871 #define GPIO_DIRSET_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 91:031413cf7a89 1872 #define GPIO_DIRSET_PIN31_Msk (0x1UL << GPIO_DIRSET_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 91:031413cf7a89 1873 #define GPIO_DIRSET_PIN31_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1874 #define GPIO_DIRSET_PIN31_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1875 #define GPIO_DIRSET_PIN31_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1876
Kojto 91:031413cf7a89 1877 /* Bit 30 : Set as output pin 30. */
Kojto 91:031413cf7a89 1878 #define GPIO_DIRSET_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 91:031413cf7a89 1879 #define GPIO_DIRSET_PIN30_Msk (0x1UL << GPIO_DIRSET_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 91:031413cf7a89 1880 #define GPIO_DIRSET_PIN30_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1881 #define GPIO_DIRSET_PIN30_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1882 #define GPIO_DIRSET_PIN30_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1883
Kojto 91:031413cf7a89 1884 /* Bit 29 : Set as output pin 29. */
Kojto 91:031413cf7a89 1885 #define GPIO_DIRSET_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 91:031413cf7a89 1886 #define GPIO_DIRSET_PIN29_Msk (0x1UL << GPIO_DIRSET_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 91:031413cf7a89 1887 #define GPIO_DIRSET_PIN29_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1888 #define GPIO_DIRSET_PIN29_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1889 #define GPIO_DIRSET_PIN29_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1890
Kojto 91:031413cf7a89 1891 /* Bit 28 : Set as output pin 28. */
Kojto 91:031413cf7a89 1892 #define GPIO_DIRSET_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 91:031413cf7a89 1893 #define GPIO_DIRSET_PIN28_Msk (0x1UL << GPIO_DIRSET_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 91:031413cf7a89 1894 #define GPIO_DIRSET_PIN28_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1895 #define GPIO_DIRSET_PIN28_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1896 #define GPIO_DIRSET_PIN28_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1897
Kojto 91:031413cf7a89 1898 /* Bit 27 : Set as output pin 27. */
Kojto 91:031413cf7a89 1899 #define GPIO_DIRSET_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 91:031413cf7a89 1900 #define GPIO_DIRSET_PIN27_Msk (0x1UL << GPIO_DIRSET_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 91:031413cf7a89 1901 #define GPIO_DIRSET_PIN27_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1902 #define GPIO_DIRSET_PIN27_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1903 #define GPIO_DIRSET_PIN27_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1904
Kojto 91:031413cf7a89 1905 /* Bit 26 : Set as output pin 26. */
Kojto 91:031413cf7a89 1906 #define GPIO_DIRSET_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 91:031413cf7a89 1907 #define GPIO_DIRSET_PIN26_Msk (0x1UL << GPIO_DIRSET_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 91:031413cf7a89 1908 #define GPIO_DIRSET_PIN26_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1909 #define GPIO_DIRSET_PIN26_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1910 #define GPIO_DIRSET_PIN26_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1911
Kojto 91:031413cf7a89 1912 /* Bit 25 : Set as output pin 25. */
Kojto 91:031413cf7a89 1913 #define GPIO_DIRSET_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 91:031413cf7a89 1914 #define GPIO_DIRSET_PIN25_Msk (0x1UL << GPIO_DIRSET_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 91:031413cf7a89 1915 #define GPIO_DIRSET_PIN25_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1916 #define GPIO_DIRSET_PIN25_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1917 #define GPIO_DIRSET_PIN25_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1918
Kojto 91:031413cf7a89 1919 /* Bit 24 : Set as output pin 24. */
Kojto 91:031413cf7a89 1920 #define GPIO_DIRSET_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 91:031413cf7a89 1921 #define GPIO_DIRSET_PIN24_Msk (0x1UL << GPIO_DIRSET_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 91:031413cf7a89 1922 #define GPIO_DIRSET_PIN24_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1923 #define GPIO_DIRSET_PIN24_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1924 #define GPIO_DIRSET_PIN24_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1925
Kojto 91:031413cf7a89 1926 /* Bit 23 : Set as output pin 23. */
Kojto 91:031413cf7a89 1927 #define GPIO_DIRSET_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 91:031413cf7a89 1928 #define GPIO_DIRSET_PIN23_Msk (0x1UL << GPIO_DIRSET_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 91:031413cf7a89 1929 #define GPIO_DIRSET_PIN23_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1930 #define GPIO_DIRSET_PIN23_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1931 #define GPIO_DIRSET_PIN23_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1932
Kojto 91:031413cf7a89 1933 /* Bit 22 : Set as output pin 22. */
Kojto 91:031413cf7a89 1934 #define GPIO_DIRSET_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 91:031413cf7a89 1935 #define GPIO_DIRSET_PIN22_Msk (0x1UL << GPIO_DIRSET_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 91:031413cf7a89 1936 #define GPIO_DIRSET_PIN22_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1937 #define GPIO_DIRSET_PIN22_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1938 #define GPIO_DIRSET_PIN22_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1939
Kojto 91:031413cf7a89 1940 /* Bit 21 : Set as output pin 21. */
Kojto 91:031413cf7a89 1941 #define GPIO_DIRSET_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 91:031413cf7a89 1942 #define GPIO_DIRSET_PIN21_Msk (0x1UL << GPIO_DIRSET_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 91:031413cf7a89 1943 #define GPIO_DIRSET_PIN21_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1944 #define GPIO_DIRSET_PIN21_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1945 #define GPIO_DIRSET_PIN21_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1946
Kojto 91:031413cf7a89 1947 /* Bit 20 : Set as output pin 20. */
Kojto 91:031413cf7a89 1948 #define GPIO_DIRSET_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 91:031413cf7a89 1949 #define GPIO_DIRSET_PIN20_Msk (0x1UL << GPIO_DIRSET_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 91:031413cf7a89 1950 #define GPIO_DIRSET_PIN20_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1951 #define GPIO_DIRSET_PIN20_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1952 #define GPIO_DIRSET_PIN20_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1953
Kojto 91:031413cf7a89 1954 /* Bit 19 : Set as output pin 19. */
Kojto 91:031413cf7a89 1955 #define GPIO_DIRSET_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 91:031413cf7a89 1956 #define GPIO_DIRSET_PIN19_Msk (0x1UL << GPIO_DIRSET_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 91:031413cf7a89 1957 #define GPIO_DIRSET_PIN19_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1958 #define GPIO_DIRSET_PIN19_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1959 #define GPIO_DIRSET_PIN19_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1960
Kojto 91:031413cf7a89 1961 /* Bit 18 : Set as output pin 18. */
Kojto 91:031413cf7a89 1962 #define GPIO_DIRSET_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 91:031413cf7a89 1963 #define GPIO_DIRSET_PIN18_Msk (0x1UL << GPIO_DIRSET_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 91:031413cf7a89 1964 #define GPIO_DIRSET_PIN18_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1965 #define GPIO_DIRSET_PIN18_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1966 #define GPIO_DIRSET_PIN18_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1967
Kojto 91:031413cf7a89 1968 /* Bit 17 : Set as output pin 17. */
Kojto 91:031413cf7a89 1969 #define GPIO_DIRSET_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 91:031413cf7a89 1970 #define GPIO_DIRSET_PIN17_Msk (0x1UL << GPIO_DIRSET_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 91:031413cf7a89 1971 #define GPIO_DIRSET_PIN17_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1972 #define GPIO_DIRSET_PIN17_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1973 #define GPIO_DIRSET_PIN17_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1974
Kojto 91:031413cf7a89 1975 /* Bit 16 : Set as output pin 16. */
Kojto 91:031413cf7a89 1976 #define GPIO_DIRSET_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 91:031413cf7a89 1977 #define GPIO_DIRSET_PIN16_Msk (0x1UL << GPIO_DIRSET_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 91:031413cf7a89 1978 #define GPIO_DIRSET_PIN16_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1979 #define GPIO_DIRSET_PIN16_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1980 #define GPIO_DIRSET_PIN16_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1981
Kojto 91:031413cf7a89 1982 /* Bit 15 : Set as output pin 15. */
Kojto 91:031413cf7a89 1983 #define GPIO_DIRSET_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 91:031413cf7a89 1984 #define GPIO_DIRSET_PIN15_Msk (0x1UL << GPIO_DIRSET_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 91:031413cf7a89 1985 #define GPIO_DIRSET_PIN15_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1986 #define GPIO_DIRSET_PIN15_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1987 #define GPIO_DIRSET_PIN15_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1988
Kojto 91:031413cf7a89 1989 /* Bit 14 : Set as output pin 14. */
Kojto 91:031413cf7a89 1990 #define GPIO_DIRSET_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 91:031413cf7a89 1991 #define GPIO_DIRSET_PIN14_Msk (0x1UL << GPIO_DIRSET_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 91:031413cf7a89 1992 #define GPIO_DIRSET_PIN14_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 1993 #define GPIO_DIRSET_PIN14_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 1994 #define GPIO_DIRSET_PIN14_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 1995
Kojto 91:031413cf7a89 1996 /* Bit 13 : Set as output pin 13. */
Kojto 91:031413cf7a89 1997 #define GPIO_DIRSET_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 91:031413cf7a89 1998 #define GPIO_DIRSET_PIN13_Msk (0x1UL << GPIO_DIRSET_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 91:031413cf7a89 1999 #define GPIO_DIRSET_PIN13_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2000 #define GPIO_DIRSET_PIN13_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2001 #define GPIO_DIRSET_PIN13_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2002
Kojto 91:031413cf7a89 2003 /* Bit 12 : Set as output pin 12. */
Kojto 91:031413cf7a89 2004 #define GPIO_DIRSET_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 91:031413cf7a89 2005 #define GPIO_DIRSET_PIN12_Msk (0x1UL << GPIO_DIRSET_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 91:031413cf7a89 2006 #define GPIO_DIRSET_PIN12_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2007 #define GPIO_DIRSET_PIN12_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2008 #define GPIO_DIRSET_PIN12_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2009
Kojto 91:031413cf7a89 2010 /* Bit 11 : Set as output pin 11. */
Kojto 91:031413cf7a89 2011 #define GPIO_DIRSET_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 91:031413cf7a89 2012 #define GPIO_DIRSET_PIN11_Msk (0x1UL << GPIO_DIRSET_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 91:031413cf7a89 2013 #define GPIO_DIRSET_PIN11_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2014 #define GPIO_DIRSET_PIN11_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2015 #define GPIO_DIRSET_PIN11_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2016
Kojto 91:031413cf7a89 2017 /* Bit 10 : Set as output pin 10. */
Kojto 91:031413cf7a89 2018 #define GPIO_DIRSET_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 91:031413cf7a89 2019 #define GPIO_DIRSET_PIN10_Msk (0x1UL << GPIO_DIRSET_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 91:031413cf7a89 2020 #define GPIO_DIRSET_PIN10_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2021 #define GPIO_DIRSET_PIN10_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2022 #define GPIO_DIRSET_PIN10_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2023
Kojto 91:031413cf7a89 2024 /* Bit 9 : Set as output pin 9. */
Kojto 91:031413cf7a89 2025 #define GPIO_DIRSET_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 91:031413cf7a89 2026 #define GPIO_DIRSET_PIN9_Msk (0x1UL << GPIO_DIRSET_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 91:031413cf7a89 2027 #define GPIO_DIRSET_PIN9_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2028 #define GPIO_DIRSET_PIN9_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2029 #define GPIO_DIRSET_PIN9_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2030
Kojto 91:031413cf7a89 2031 /* Bit 8 : Set as output pin 8. */
Kojto 91:031413cf7a89 2032 #define GPIO_DIRSET_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 91:031413cf7a89 2033 #define GPIO_DIRSET_PIN8_Msk (0x1UL << GPIO_DIRSET_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 91:031413cf7a89 2034 #define GPIO_DIRSET_PIN8_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2035 #define GPIO_DIRSET_PIN8_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2036 #define GPIO_DIRSET_PIN8_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2037
Kojto 91:031413cf7a89 2038 /* Bit 7 : Set as output pin 7. */
Kojto 91:031413cf7a89 2039 #define GPIO_DIRSET_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 91:031413cf7a89 2040 #define GPIO_DIRSET_PIN7_Msk (0x1UL << GPIO_DIRSET_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 91:031413cf7a89 2041 #define GPIO_DIRSET_PIN7_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2042 #define GPIO_DIRSET_PIN7_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2043 #define GPIO_DIRSET_PIN7_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2044
Kojto 91:031413cf7a89 2045 /* Bit 6 : Set as output pin 6. */
Kojto 91:031413cf7a89 2046 #define GPIO_DIRSET_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 91:031413cf7a89 2047 #define GPIO_DIRSET_PIN6_Msk (0x1UL << GPIO_DIRSET_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 91:031413cf7a89 2048 #define GPIO_DIRSET_PIN6_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2049 #define GPIO_DIRSET_PIN6_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2050 #define GPIO_DIRSET_PIN6_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2051
Kojto 91:031413cf7a89 2052 /* Bit 5 : Set as output pin 5. */
Kojto 91:031413cf7a89 2053 #define GPIO_DIRSET_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 91:031413cf7a89 2054 #define GPIO_DIRSET_PIN5_Msk (0x1UL << GPIO_DIRSET_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 91:031413cf7a89 2055 #define GPIO_DIRSET_PIN5_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2056 #define GPIO_DIRSET_PIN5_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2057 #define GPIO_DIRSET_PIN5_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2058
Kojto 91:031413cf7a89 2059 /* Bit 4 : Set as output pin 4. */
Kojto 91:031413cf7a89 2060 #define GPIO_DIRSET_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 91:031413cf7a89 2061 #define GPIO_DIRSET_PIN4_Msk (0x1UL << GPIO_DIRSET_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 91:031413cf7a89 2062 #define GPIO_DIRSET_PIN4_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2063 #define GPIO_DIRSET_PIN4_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2064 #define GPIO_DIRSET_PIN4_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2065
Kojto 91:031413cf7a89 2066 /* Bit 3 : Set as output pin 3. */
Kojto 91:031413cf7a89 2067 #define GPIO_DIRSET_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 91:031413cf7a89 2068 #define GPIO_DIRSET_PIN3_Msk (0x1UL << GPIO_DIRSET_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 91:031413cf7a89 2069 #define GPIO_DIRSET_PIN3_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2070 #define GPIO_DIRSET_PIN3_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2071 #define GPIO_DIRSET_PIN3_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2072
Kojto 91:031413cf7a89 2073 /* Bit 2 : Set as output pin 2. */
Kojto 91:031413cf7a89 2074 #define GPIO_DIRSET_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 91:031413cf7a89 2075 #define GPIO_DIRSET_PIN2_Msk (0x1UL << GPIO_DIRSET_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 91:031413cf7a89 2076 #define GPIO_DIRSET_PIN2_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2077 #define GPIO_DIRSET_PIN2_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2078 #define GPIO_DIRSET_PIN2_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2079
Kojto 91:031413cf7a89 2080 /* Bit 1 : Set as output pin 1. */
Kojto 91:031413cf7a89 2081 #define GPIO_DIRSET_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 91:031413cf7a89 2082 #define GPIO_DIRSET_PIN1_Msk (0x1UL << GPIO_DIRSET_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 91:031413cf7a89 2083 #define GPIO_DIRSET_PIN1_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2084 #define GPIO_DIRSET_PIN1_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2085 #define GPIO_DIRSET_PIN1_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2086
Kojto 91:031413cf7a89 2087 /* Bit 0 : Set as output pin 0. */
Kojto 91:031413cf7a89 2088 #define GPIO_DIRSET_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 91:031413cf7a89 2089 #define GPIO_DIRSET_PIN0_Msk (0x1UL << GPIO_DIRSET_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 91:031413cf7a89 2090 #define GPIO_DIRSET_PIN0_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2091 #define GPIO_DIRSET_PIN0_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2092 #define GPIO_DIRSET_PIN0_Set (1UL) /*!< Set pin as output. */
Kojto 91:031413cf7a89 2093
Kojto 91:031413cf7a89 2094 /* Register: GPIO_DIRCLR */
Kojto 91:031413cf7a89 2095 /* Description: DIR clear register. */
Kojto 91:031413cf7a89 2096
Kojto 91:031413cf7a89 2097 /* Bit 31 : Set as input pin 31. */
Kojto 91:031413cf7a89 2098 #define GPIO_DIRCLR_PIN31_Pos (31UL) /*!< Position of PIN31 field. */
Kojto 91:031413cf7a89 2099 #define GPIO_DIRCLR_PIN31_Msk (0x1UL << GPIO_DIRCLR_PIN31_Pos) /*!< Bit mask of PIN31 field. */
Kojto 91:031413cf7a89 2100 #define GPIO_DIRCLR_PIN31_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2101 #define GPIO_DIRCLR_PIN31_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2102 #define GPIO_DIRCLR_PIN31_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2103
Kojto 91:031413cf7a89 2104 /* Bit 30 : Set as input pin 30. */
Kojto 91:031413cf7a89 2105 #define GPIO_DIRCLR_PIN30_Pos (30UL) /*!< Position of PIN30 field. */
Kojto 91:031413cf7a89 2106 #define GPIO_DIRCLR_PIN30_Msk (0x1UL << GPIO_DIRCLR_PIN30_Pos) /*!< Bit mask of PIN30 field. */
Kojto 91:031413cf7a89 2107 #define GPIO_DIRCLR_PIN30_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2108 #define GPIO_DIRCLR_PIN30_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2109 #define GPIO_DIRCLR_PIN30_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2110
Kojto 91:031413cf7a89 2111 /* Bit 29 : Set as input pin 29. */
Kojto 91:031413cf7a89 2112 #define GPIO_DIRCLR_PIN29_Pos (29UL) /*!< Position of PIN29 field. */
Kojto 91:031413cf7a89 2113 #define GPIO_DIRCLR_PIN29_Msk (0x1UL << GPIO_DIRCLR_PIN29_Pos) /*!< Bit mask of PIN29 field. */
Kojto 91:031413cf7a89 2114 #define GPIO_DIRCLR_PIN29_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2115 #define GPIO_DIRCLR_PIN29_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2116 #define GPIO_DIRCLR_PIN29_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2117
Kojto 91:031413cf7a89 2118 /* Bit 28 : Set as input pin 28. */
Kojto 91:031413cf7a89 2119 #define GPIO_DIRCLR_PIN28_Pos (28UL) /*!< Position of PIN28 field. */
Kojto 91:031413cf7a89 2120 #define GPIO_DIRCLR_PIN28_Msk (0x1UL << GPIO_DIRCLR_PIN28_Pos) /*!< Bit mask of PIN28 field. */
Kojto 91:031413cf7a89 2121 #define GPIO_DIRCLR_PIN28_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2122 #define GPIO_DIRCLR_PIN28_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2123 #define GPIO_DIRCLR_PIN28_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2124
Kojto 91:031413cf7a89 2125 /* Bit 27 : Set as input pin 27. */
Kojto 91:031413cf7a89 2126 #define GPIO_DIRCLR_PIN27_Pos (27UL) /*!< Position of PIN27 field. */
Kojto 91:031413cf7a89 2127 #define GPIO_DIRCLR_PIN27_Msk (0x1UL << GPIO_DIRCLR_PIN27_Pos) /*!< Bit mask of PIN27 field. */
Kojto 91:031413cf7a89 2128 #define GPIO_DIRCLR_PIN27_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2129 #define GPIO_DIRCLR_PIN27_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2130 #define GPIO_DIRCLR_PIN27_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2131
Kojto 91:031413cf7a89 2132 /* Bit 26 : Set as input pin 26. */
Kojto 91:031413cf7a89 2133 #define GPIO_DIRCLR_PIN26_Pos (26UL) /*!< Position of PIN26 field. */
Kojto 91:031413cf7a89 2134 #define GPIO_DIRCLR_PIN26_Msk (0x1UL << GPIO_DIRCLR_PIN26_Pos) /*!< Bit mask of PIN26 field. */
Kojto 91:031413cf7a89 2135 #define GPIO_DIRCLR_PIN26_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2136 #define GPIO_DIRCLR_PIN26_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2137 #define GPIO_DIRCLR_PIN26_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2138
Kojto 91:031413cf7a89 2139 /* Bit 25 : Set as input pin 25. */
Kojto 91:031413cf7a89 2140 #define GPIO_DIRCLR_PIN25_Pos (25UL) /*!< Position of PIN25 field. */
Kojto 91:031413cf7a89 2141 #define GPIO_DIRCLR_PIN25_Msk (0x1UL << GPIO_DIRCLR_PIN25_Pos) /*!< Bit mask of PIN25 field. */
Kojto 91:031413cf7a89 2142 #define GPIO_DIRCLR_PIN25_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2143 #define GPIO_DIRCLR_PIN25_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2144 #define GPIO_DIRCLR_PIN25_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2145
Kojto 91:031413cf7a89 2146 /* Bit 24 : Set as input pin 24. */
Kojto 91:031413cf7a89 2147 #define GPIO_DIRCLR_PIN24_Pos (24UL) /*!< Position of PIN24 field. */
Kojto 91:031413cf7a89 2148 #define GPIO_DIRCLR_PIN24_Msk (0x1UL << GPIO_DIRCLR_PIN24_Pos) /*!< Bit mask of PIN24 field. */
Kojto 91:031413cf7a89 2149 #define GPIO_DIRCLR_PIN24_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2150 #define GPIO_DIRCLR_PIN24_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2151 #define GPIO_DIRCLR_PIN24_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2152
Kojto 91:031413cf7a89 2153 /* Bit 23 : Set as input pin 23. */
Kojto 91:031413cf7a89 2154 #define GPIO_DIRCLR_PIN23_Pos (23UL) /*!< Position of PIN23 field. */
Kojto 91:031413cf7a89 2155 #define GPIO_DIRCLR_PIN23_Msk (0x1UL << GPIO_DIRCLR_PIN23_Pos) /*!< Bit mask of PIN23 field. */
Kojto 91:031413cf7a89 2156 #define GPIO_DIRCLR_PIN23_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2157 #define GPIO_DIRCLR_PIN23_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2158 #define GPIO_DIRCLR_PIN23_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2159
Kojto 91:031413cf7a89 2160 /* Bit 22 : Set as input pin 22. */
Kojto 91:031413cf7a89 2161 #define GPIO_DIRCLR_PIN22_Pos (22UL) /*!< Position of PIN22 field. */
Kojto 91:031413cf7a89 2162 #define GPIO_DIRCLR_PIN22_Msk (0x1UL << GPIO_DIRCLR_PIN22_Pos) /*!< Bit mask of PIN22 field. */
Kojto 91:031413cf7a89 2163 #define GPIO_DIRCLR_PIN22_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2164 #define GPIO_DIRCLR_PIN22_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2165 #define GPIO_DIRCLR_PIN22_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2166
Kojto 91:031413cf7a89 2167 /* Bit 21 : Set as input pin 21. */
Kojto 91:031413cf7a89 2168 #define GPIO_DIRCLR_PIN21_Pos (21UL) /*!< Position of PIN21 field. */
Kojto 91:031413cf7a89 2169 #define GPIO_DIRCLR_PIN21_Msk (0x1UL << GPIO_DIRCLR_PIN21_Pos) /*!< Bit mask of PIN21 field. */
Kojto 91:031413cf7a89 2170 #define GPIO_DIRCLR_PIN21_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2171 #define GPIO_DIRCLR_PIN21_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2172 #define GPIO_DIRCLR_PIN21_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2173
Kojto 91:031413cf7a89 2174 /* Bit 20 : Set as input pin 20. */
Kojto 91:031413cf7a89 2175 #define GPIO_DIRCLR_PIN20_Pos (20UL) /*!< Position of PIN20 field. */
Kojto 91:031413cf7a89 2176 #define GPIO_DIRCLR_PIN20_Msk (0x1UL << GPIO_DIRCLR_PIN20_Pos) /*!< Bit mask of PIN20 field. */
Kojto 91:031413cf7a89 2177 #define GPIO_DIRCLR_PIN20_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2178 #define GPIO_DIRCLR_PIN20_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2179 #define GPIO_DIRCLR_PIN20_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2180
Kojto 91:031413cf7a89 2181 /* Bit 19 : Set as input pin 19. */
Kojto 91:031413cf7a89 2182 #define GPIO_DIRCLR_PIN19_Pos (19UL) /*!< Position of PIN19 field. */
Kojto 91:031413cf7a89 2183 #define GPIO_DIRCLR_PIN19_Msk (0x1UL << GPIO_DIRCLR_PIN19_Pos) /*!< Bit mask of PIN19 field. */
Kojto 91:031413cf7a89 2184 #define GPIO_DIRCLR_PIN19_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2185 #define GPIO_DIRCLR_PIN19_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2186 #define GPIO_DIRCLR_PIN19_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2187
Kojto 91:031413cf7a89 2188 /* Bit 18 : Set as input pin 18. */
Kojto 91:031413cf7a89 2189 #define GPIO_DIRCLR_PIN18_Pos (18UL) /*!< Position of PIN18 field. */
Kojto 91:031413cf7a89 2190 #define GPIO_DIRCLR_PIN18_Msk (0x1UL << GPIO_DIRCLR_PIN18_Pos) /*!< Bit mask of PIN18 field. */
Kojto 91:031413cf7a89 2191 #define GPIO_DIRCLR_PIN18_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2192 #define GPIO_DIRCLR_PIN18_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2193 #define GPIO_DIRCLR_PIN18_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2194
Kojto 91:031413cf7a89 2195 /* Bit 17 : Set as input pin 17. */
Kojto 91:031413cf7a89 2196 #define GPIO_DIRCLR_PIN17_Pos (17UL) /*!< Position of PIN17 field. */
Kojto 91:031413cf7a89 2197 #define GPIO_DIRCLR_PIN17_Msk (0x1UL << GPIO_DIRCLR_PIN17_Pos) /*!< Bit mask of PIN17 field. */
Kojto 91:031413cf7a89 2198 #define GPIO_DIRCLR_PIN17_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2199 #define GPIO_DIRCLR_PIN17_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2200 #define GPIO_DIRCLR_PIN17_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2201
Kojto 91:031413cf7a89 2202 /* Bit 16 : Set as input pin 16. */
Kojto 91:031413cf7a89 2203 #define GPIO_DIRCLR_PIN16_Pos (16UL) /*!< Position of PIN16 field. */
Kojto 91:031413cf7a89 2204 #define GPIO_DIRCLR_PIN16_Msk (0x1UL << GPIO_DIRCLR_PIN16_Pos) /*!< Bit mask of PIN16 field. */
Kojto 91:031413cf7a89 2205 #define GPIO_DIRCLR_PIN16_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2206 #define GPIO_DIRCLR_PIN16_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2207 #define GPIO_DIRCLR_PIN16_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2208
Kojto 91:031413cf7a89 2209 /* Bit 15 : Set as input pin 15. */
Kojto 91:031413cf7a89 2210 #define GPIO_DIRCLR_PIN15_Pos (15UL) /*!< Position of PIN15 field. */
Kojto 91:031413cf7a89 2211 #define GPIO_DIRCLR_PIN15_Msk (0x1UL << GPIO_DIRCLR_PIN15_Pos) /*!< Bit mask of PIN15 field. */
Kojto 91:031413cf7a89 2212 #define GPIO_DIRCLR_PIN15_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2213 #define GPIO_DIRCLR_PIN15_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2214 #define GPIO_DIRCLR_PIN15_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2215
Kojto 91:031413cf7a89 2216 /* Bit 14 : Set as input pin 14. */
Kojto 91:031413cf7a89 2217 #define GPIO_DIRCLR_PIN14_Pos (14UL) /*!< Position of PIN14 field. */
Kojto 91:031413cf7a89 2218 #define GPIO_DIRCLR_PIN14_Msk (0x1UL << GPIO_DIRCLR_PIN14_Pos) /*!< Bit mask of PIN14 field. */
Kojto 91:031413cf7a89 2219 #define GPIO_DIRCLR_PIN14_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2220 #define GPIO_DIRCLR_PIN14_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2221 #define GPIO_DIRCLR_PIN14_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2222
Kojto 91:031413cf7a89 2223 /* Bit 13 : Set as input pin 13. */
Kojto 91:031413cf7a89 2224 #define GPIO_DIRCLR_PIN13_Pos (13UL) /*!< Position of PIN13 field. */
Kojto 91:031413cf7a89 2225 #define GPIO_DIRCLR_PIN13_Msk (0x1UL << GPIO_DIRCLR_PIN13_Pos) /*!< Bit mask of PIN13 field. */
Kojto 91:031413cf7a89 2226 #define GPIO_DIRCLR_PIN13_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2227 #define GPIO_DIRCLR_PIN13_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2228 #define GPIO_DIRCLR_PIN13_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2229
Kojto 91:031413cf7a89 2230 /* Bit 12 : Set as input pin 12. */
Kojto 91:031413cf7a89 2231 #define GPIO_DIRCLR_PIN12_Pos (12UL) /*!< Position of PIN12 field. */
Kojto 91:031413cf7a89 2232 #define GPIO_DIRCLR_PIN12_Msk (0x1UL << GPIO_DIRCLR_PIN12_Pos) /*!< Bit mask of PIN12 field. */
Kojto 91:031413cf7a89 2233 #define GPIO_DIRCLR_PIN12_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2234 #define GPIO_DIRCLR_PIN12_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2235 #define GPIO_DIRCLR_PIN12_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2236
Kojto 91:031413cf7a89 2237 /* Bit 11 : Set as input pin 11. */
Kojto 91:031413cf7a89 2238 #define GPIO_DIRCLR_PIN11_Pos (11UL) /*!< Position of PIN11 field. */
Kojto 91:031413cf7a89 2239 #define GPIO_DIRCLR_PIN11_Msk (0x1UL << GPIO_DIRCLR_PIN11_Pos) /*!< Bit mask of PIN11 field. */
Kojto 91:031413cf7a89 2240 #define GPIO_DIRCLR_PIN11_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2241 #define GPIO_DIRCLR_PIN11_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2242 #define GPIO_DIRCLR_PIN11_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2243
Kojto 91:031413cf7a89 2244 /* Bit 10 : Set as input pin 10. */
Kojto 91:031413cf7a89 2245 #define GPIO_DIRCLR_PIN10_Pos (10UL) /*!< Position of PIN10 field. */
Kojto 91:031413cf7a89 2246 #define GPIO_DIRCLR_PIN10_Msk (0x1UL << GPIO_DIRCLR_PIN10_Pos) /*!< Bit mask of PIN10 field. */
Kojto 91:031413cf7a89 2247 #define GPIO_DIRCLR_PIN10_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2248 #define GPIO_DIRCLR_PIN10_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2249 #define GPIO_DIRCLR_PIN10_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2250
Kojto 91:031413cf7a89 2251 /* Bit 9 : Set as input pin 9. */
Kojto 91:031413cf7a89 2252 #define GPIO_DIRCLR_PIN9_Pos (9UL) /*!< Position of PIN9 field. */
Kojto 91:031413cf7a89 2253 #define GPIO_DIRCLR_PIN9_Msk (0x1UL << GPIO_DIRCLR_PIN9_Pos) /*!< Bit mask of PIN9 field. */
Kojto 91:031413cf7a89 2254 #define GPIO_DIRCLR_PIN9_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2255 #define GPIO_DIRCLR_PIN9_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2256 #define GPIO_DIRCLR_PIN9_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2257
Kojto 91:031413cf7a89 2258 /* Bit 8 : Set as input pin 8. */
Kojto 91:031413cf7a89 2259 #define GPIO_DIRCLR_PIN8_Pos (8UL) /*!< Position of PIN8 field. */
Kojto 91:031413cf7a89 2260 #define GPIO_DIRCLR_PIN8_Msk (0x1UL << GPIO_DIRCLR_PIN8_Pos) /*!< Bit mask of PIN8 field. */
Kojto 91:031413cf7a89 2261 #define GPIO_DIRCLR_PIN8_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2262 #define GPIO_DIRCLR_PIN8_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2263 #define GPIO_DIRCLR_PIN8_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2264
Kojto 91:031413cf7a89 2265 /* Bit 7 : Set as input pin 7. */
Kojto 91:031413cf7a89 2266 #define GPIO_DIRCLR_PIN7_Pos (7UL) /*!< Position of PIN7 field. */
Kojto 91:031413cf7a89 2267 #define GPIO_DIRCLR_PIN7_Msk (0x1UL << GPIO_DIRCLR_PIN7_Pos) /*!< Bit mask of PIN7 field. */
Kojto 91:031413cf7a89 2268 #define GPIO_DIRCLR_PIN7_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2269 #define GPIO_DIRCLR_PIN7_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2270 #define GPIO_DIRCLR_PIN7_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2271
Kojto 91:031413cf7a89 2272 /* Bit 6 : Set as input pin 6. */
Kojto 91:031413cf7a89 2273 #define GPIO_DIRCLR_PIN6_Pos (6UL) /*!< Position of PIN6 field. */
Kojto 91:031413cf7a89 2274 #define GPIO_DIRCLR_PIN6_Msk (0x1UL << GPIO_DIRCLR_PIN6_Pos) /*!< Bit mask of PIN6 field. */
Kojto 91:031413cf7a89 2275 #define GPIO_DIRCLR_PIN6_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2276 #define GPIO_DIRCLR_PIN6_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2277 #define GPIO_DIRCLR_PIN6_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2278
Kojto 91:031413cf7a89 2279 /* Bit 5 : Set as input pin 5. */
Kojto 91:031413cf7a89 2280 #define GPIO_DIRCLR_PIN5_Pos (5UL) /*!< Position of PIN5 field. */
Kojto 91:031413cf7a89 2281 #define GPIO_DIRCLR_PIN5_Msk (0x1UL << GPIO_DIRCLR_PIN5_Pos) /*!< Bit mask of PIN5 field. */
Kojto 91:031413cf7a89 2282 #define GPIO_DIRCLR_PIN5_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2283 #define GPIO_DIRCLR_PIN5_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2284 #define GPIO_DIRCLR_PIN5_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2285
Kojto 91:031413cf7a89 2286 /* Bit 4 : Set as input pin 4. */
Kojto 91:031413cf7a89 2287 #define GPIO_DIRCLR_PIN4_Pos (4UL) /*!< Position of PIN4 field. */
Kojto 91:031413cf7a89 2288 #define GPIO_DIRCLR_PIN4_Msk (0x1UL << GPIO_DIRCLR_PIN4_Pos) /*!< Bit mask of PIN4 field. */
Kojto 91:031413cf7a89 2289 #define GPIO_DIRCLR_PIN4_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2290 #define GPIO_DIRCLR_PIN4_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2291 #define GPIO_DIRCLR_PIN4_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2292
Kojto 91:031413cf7a89 2293 /* Bit 3 : Set as input pin 3. */
Kojto 91:031413cf7a89 2294 #define GPIO_DIRCLR_PIN3_Pos (3UL) /*!< Position of PIN3 field. */
Kojto 91:031413cf7a89 2295 #define GPIO_DIRCLR_PIN3_Msk (0x1UL << GPIO_DIRCLR_PIN3_Pos) /*!< Bit mask of PIN3 field. */
Kojto 91:031413cf7a89 2296 #define GPIO_DIRCLR_PIN3_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2297 #define GPIO_DIRCLR_PIN3_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2298 #define GPIO_DIRCLR_PIN3_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2299
Kojto 91:031413cf7a89 2300 /* Bit 2 : Set as input pin 2. */
Kojto 91:031413cf7a89 2301 #define GPIO_DIRCLR_PIN2_Pos (2UL) /*!< Position of PIN2 field. */
Kojto 91:031413cf7a89 2302 #define GPIO_DIRCLR_PIN2_Msk (0x1UL << GPIO_DIRCLR_PIN2_Pos) /*!< Bit mask of PIN2 field. */
Kojto 91:031413cf7a89 2303 #define GPIO_DIRCLR_PIN2_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2304 #define GPIO_DIRCLR_PIN2_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2305 #define GPIO_DIRCLR_PIN2_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2306
Kojto 91:031413cf7a89 2307 /* Bit 1 : Set as input pin 1. */
Kojto 91:031413cf7a89 2308 #define GPIO_DIRCLR_PIN1_Pos (1UL) /*!< Position of PIN1 field. */
Kojto 91:031413cf7a89 2309 #define GPIO_DIRCLR_PIN1_Msk (0x1UL << GPIO_DIRCLR_PIN1_Pos) /*!< Bit mask of PIN1 field. */
Kojto 91:031413cf7a89 2310 #define GPIO_DIRCLR_PIN1_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2311 #define GPIO_DIRCLR_PIN1_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2312 #define GPIO_DIRCLR_PIN1_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2313
Kojto 91:031413cf7a89 2314 /* Bit 0 : Set as input pin 0. */
Kojto 91:031413cf7a89 2315 #define GPIO_DIRCLR_PIN0_Pos (0UL) /*!< Position of PIN0 field. */
Kojto 91:031413cf7a89 2316 #define GPIO_DIRCLR_PIN0_Msk (0x1UL << GPIO_DIRCLR_PIN0_Pos) /*!< Bit mask of PIN0 field. */
Kojto 91:031413cf7a89 2317 #define GPIO_DIRCLR_PIN0_Input (0UL) /*!< Pin set as input. */
Kojto 91:031413cf7a89 2318 #define GPIO_DIRCLR_PIN0_Output (1UL) /*!< Pin set as output. */
Kojto 91:031413cf7a89 2319 #define GPIO_DIRCLR_PIN0_Clear (1UL) /*!< Set pin as input. */
Kojto 91:031413cf7a89 2320
Kojto 91:031413cf7a89 2321 /* Register: GPIO_PIN_CNF */
Kojto 91:031413cf7a89 2322 /* Description: Configuration of GPIO pins. */
Kojto 91:031413cf7a89 2323
Kojto 91:031413cf7a89 2324 /* Bits 17..16 : Pin sensing mechanism. */
Kojto 91:031413cf7a89 2325 #define GPIO_PIN_CNF_SENSE_Pos (16UL) /*!< Position of SENSE field. */
Kojto 91:031413cf7a89 2326 #define GPIO_PIN_CNF_SENSE_Msk (0x3UL << GPIO_PIN_CNF_SENSE_Pos) /*!< Bit mask of SENSE field. */
Kojto 91:031413cf7a89 2327 #define GPIO_PIN_CNF_SENSE_Disabled (0x00UL) /*!< Disabled. */
Kojto 91:031413cf7a89 2328 #define GPIO_PIN_CNF_SENSE_High (0x02UL) /*!< Wakeup on high level. */
Kojto 91:031413cf7a89 2329 #define GPIO_PIN_CNF_SENSE_Low (0x03UL) /*!< Wakeup on low level. */
Kojto 91:031413cf7a89 2330
Kojto 91:031413cf7a89 2331 /* Bits 10..8 : Drive configuration. */
Kojto 91:031413cf7a89 2332 #define GPIO_PIN_CNF_DRIVE_Pos (8UL) /*!< Position of DRIVE field. */
Kojto 91:031413cf7a89 2333 #define GPIO_PIN_CNF_DRIVE_Msk (0x7UL << GPIO_PIN_CNF_DRIVE_Pos) /*!< Bit mask of DRIVE field. */
Kojto 91:031413cf7a89 2334 #define GPIO_PIN_CNF_DRIVE_S0S1 (0x00UL) /*!< Standard '0', Standard '1'. */
Kojto 91:031413cf7a89 2335 #define GPIO_PIN_CNF_DRIVE_H0S1 (0x01UL) /*!< High '0', Standard '1'. */
Kojto 91:031413cf7a89 2336 #define GPIO_PIN_CNF_DRIVE_S0H1 (0x02UL) /*!< Standard '0', High '1'. */
Kojto 91:031413cf7a89 2337 #define GPIO_PIN_CNF_DRIVE_H0H1 (0x03UL) /*!< High '0', High '1'. */
Kojto 91:031413cf7a89 2338 #define GPIO_PIN_CNF_DRIVE_D0S1 (0x04UL) /*!< Disconnected '0', Standard '1'. */
Kojto 91:031413cf7a89 2339 #define GPIO_PIN_CNF_DRIVE_D0H1 (0x05UL) /*!< Disconnected '0', High '1'. */
Kojto 91:031413cf7a89 2340 #define GPIO_PIN_CNF_DRIVE_S0D1 (0x06UL) /*!< Standard '0', Disconnected '1'. */
Kojto 91:031413cf7a89 2341 #define GPIO_PIN_CNF_DRIVE_H0D1 (0x07UL) /*!< High '0', Disconnected '1'. */
Kojto 91:031413cf7a89 2342
Kojto 91:031413cf7a89 2343 /* Bits 3..2 : Pull-up or -down configuration. */
Kojto 91:031413cf7a89 2344 #define GPIO_PIN_CNF_PULL_Pos (2UL) /*!< Position of PULL field. */
Kojto 91:031413cf7a89 2345 #define GPIO_PIN_CNF_PULL_Msk (0x3UL << GPIO_PIN_CNF_PULL_Pos) /*!< Bit mask of PULL field. */
Kojto 91:031413cf7a89 2346 #define GPIO_PIN_CNF_PULL_Disabled (0x00UL) /*!< No pull. */
Kojto 91:031413cf7a89 2347 #define GPIO_PIN_CNF_PULL_Pulldown (0x01UL) /*!< Pulldown on pin. */
Kojto 91:031413cf7a89 2348 #define GPIO_PIN_CNF_PULL_Pullup (0x03UL) /*!< Pullup on pin. */
Kojto 91:031413cf7a89 2349
Kojto 91:031413cf7a89 2350 /* Bit 1 : Connect or disconnect input path. */
Kojto 91:031413cf7a89 2351 #define GPIO_PIN_CNF_INPUT_Pos (1UL) /*!< Position of INPUT field. */
Kojto 91:031413cf7a89 2352 #define GPIO_PIN_CNF_INPUT_Msk (0x1UL << GPIO_PIN_CNF_INPUT_Pos) /*!< Bit mask of INPUT field. */
Kojto 91:031413cf7a89 2353 #define GPIO_PIN_CNF_INPUT_Connect (0UL) /*!< Connect input pin. */
Kojto 91:031413cf7a89 2354 #define GPIO_PIN_CNF_INPUT_Disconnect (1UL) /*!< Disconnect input pin. */
Kojto 91:031413cf7a89 2355
Kojto 91:031413cf7a89 2356 /* Bit 0 : Pin direction. */
Kojto 91:031413cf7a89 2357 #define GPIO_PIN_CNF_DIR_Pos (0UL) /*!< Position of DIR field. */
Kojto 91:031413cf7a89 2358 #define GPIO_PIN_CNF_DIR_Msk (0x1UL << GPIO_PIN_CNF_DIR_Pos) /*!< Bit mask of DIR field. */
Kojto 91:031413cf7a89 2359 #define GPIO_PIN_CNF_DIR_Input (0UL) /*!< Configure pin as an input pin. */
Kojto 91:031413cf7a89 2360 #define GPIO_PIN_CNF_DIR_Output (1UL) /*!< Configure pin as an output pin. */
Kojto 91:031413cf7a89 2361
Kojto 91:031413cf7a89 2362
Kojto 91:031413cf7a89 2363 /* Peripheral: GPIOTE */
Kojto 91:031413cf7a89 2364 /* Description: GPIO tasks and events. */
Kojto 91:031413cf7a89 2365
Kojto 91:031413cf7a89 2366 /* Register: GPIOTE_INTENSET */
Kojto 91:031413cf7a89 2367 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 2368
Kojto 91:031413cf7a89 2369 /* Bit 31 : Enable interrupt on PORT event. */
Kojto 91:031413cf7a89 2370 #define GPIOTE_INTENSET_PORT_Pos (31UL) /*!< Position of PORT field. */
Kojto 91:031413cf7a89 2371 #define GPIOTE_INTENSET_PORT_Msk (0x1UL << GPIOTE_INTENSET_PORT_Pos) /*!< Bit mask of PORT field. */
Kojto 91:031413cf7a89 2372 #define GPIOTE_INTENSET_PORT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2373 #define GPIOTE_INTENSET_PORT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2374 #define GPIOTE_INTENSET_PORT_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 2375
Kojto 91:031413cf7a89 2376 /* Bit 3 : Enable interrupt on IN[3] event. */
Kojto 91:031413cf7a89 2377 #define GPIOTE_INTENSET_IN3_Pos (3UL) /*!< Position of IN3 field. */
Kojto 91:031413cf7a89 2378 #define GPIOTE_INTENSET_IN3_Msk (0x1UL << GPIOTE_INTENSET_IN3_Pos) /*!< Bit mask of IN3 field. */
Kojto 91:031413cf7a89 2379 #define GPIOTE_INTENSET_IN3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2380 #define GPIOTE_INTENSET_IN3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2381 #define GPIOTE_INTENSET_IN3_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 2382
Kojto 91:031413cf7a89 2383 /* Bit 2 : Enable interrupt on IN[2] event. */
Kojto 91:031413cf7a89 2384 #define GPIOTE_INTENSET_IN2_Pos (2UL) /*!< Position of IN2 field. */
Kojto 91:031413cf7a89 2385 #define GPIOTE_INTENSET_IN2_Msk (0x1UL << GPIOTE_INTENSET_IN2_Pos) /*!< Bit mask of IN2 field. */
Kojto 91:031413cf7a89 2386 #define GPIOTE_INTENSET_IN2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2387 #define GPIOTE_INTENSET_IN2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2388 #define GPIOTE_INTENSET_IN2_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 2389
Kojto 91:031413cf7a89 2390 /* Bit 1 : Enable interrupt on IN[1] event. */
Kojto 91:031413cf7a89 2391 #define GPIOTE_INTENSET_IN1_Pos (1UL) /*!< Position of IN1 field. */
Kojto 91:031413cf7a89 2392 #define GPIOTE_INTENSET_IN1_Msk (0x1UL << GPIOTE_INTENSET_IN1_Pos) /*!< Bit mask of IN1 field. */
Kojto 91:031413cf7a89 2393 #define GPIOTE_INTENSET_IN1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2394 #define GPIOTE_INTENSET_IN1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2395 #define GPIOTE_INTENSET_IN1_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 2396
Kojto 91:031413cf7a89 2397 /* Bit 0 : Enable interrupt on IN[0] event. */
Kojto 91:031413cf7a89 2398 #define GPIOTE_INTENSET_IN0_Pos (0UL) /*!< Position of IN0 field. */
Kojto 91:031413cf7a89 2399 #define GPIOTE_INTENSET_IN0_Msk (0x1UL << GPIOTE_INTENSET_IN0_Pos) /*!< Bit mask of IN0 field. */
Kojto 91:031413cf7a89 2400 #define GPIOTE_INTENSET_IN0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2401 #define GPIOTE_INTENSET_IN0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2402 #define GPIOTE_INTENSET_IN0_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 2403
Kojto 91:031413cf7a89 2404 /* Register: GPIOTE_INTENCLR */
Kojto 91:031413cf7a89 2405 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 2406
Kojto 91:031413cf7a89 2407 /* Bit 31 : Disable interrupt on PORT event. */
Kojto 91:031413cf7a89 2408 #define GPIOTE_INTENCLR_PORT_Pos (31UL) /*!< Position of PORT field. */
Kojto 91:031413cf7a89 2409 #define GPIOTE_INTENCLR_PORT_Msk (0x1UL << GPIOTE_INTENCLR_PORT_Pos) /*!< Bit mask of PORT field. */
Kojto 91:031413cf7a89 2410 #define GPIOTE_INTENCLR_PORT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2411 #define GPIOTE_INTENCLR_PORT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2412 #define GPIOTE_INTENCLR_PORT_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 2413
Kojto 91:031413cf7a89 2414 /* Bit 3 : Disable interrupt on IN[3] event. */
Kojto 91:031413cf7a89 2415 #define GPIOTE_INTENCLR_IN3_Pos (3UL) /*!< Position of IN3 field. */
Kojto 91:031413cf7a89 2416 #define GPIOTE_INTENCLR_IN3_Msk (0x1UL << GPIOTE_INTENCLR_IN3_Pos) /*!< Bit mask of IN3 field. */
Kojto 91:031413cf7a89 2417 #define GPIOTE_INTENCLR_IN3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2418 #define GPIOTE_INTENCLR_IN3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2419 #define GPIOTE_INTENCLR_IN3_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 2420
Kojto 91:031413cf7a89 2421 /* Bit 2 : Disable interrupt on IN[2] event. */
Kojto 91:031413cf7a89 2422 #define GPIOTE_INTENCLR_IN2_Pos (2UL) /*!< Position of IN2 field. */
Kojto 91:031413cf7a89 2423 #define GPIOTE_INTENCLR_IN2_Msk (0x1UL << GPIOTE_INTENCLR_IN2_Pos) /*!< Bit mask of IN2 field. */
Kojto 91:031413cf7a89 2424 #define GPIOTE_INTENCLR_IN2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2425 #define GPIOTE_INTENCLR_IN2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2426 #define GPIOTE_INTENCLR_IN2_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 2427
Kojto 91:031413cf7a89 2428 /* Bit 1 : Disable interrupt on IN[1] event. */
Kojto 91:031413cf7a89 2429 #define GPIOTE_INTENCLR_IN1_Pos (1UL) /*!< Position of IN1 field. */
Kojto 91:031413cf7a89 2430 #define GPIOTE_INTENCLR_IN1_Msk (0x1UL << GPIOTE_INTENCLR_IN1_Pos) /*!< Bit mask of IN1 field. */
Kojto 91:031413cf7a89 2431 #define GPIOTE_INTENCLR_IN1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2432 #define GPIOTE_INTENCLR_IN1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2433 #define GPIOTE_INTENCLR_IN1_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 2434
Kojto 91:031413cf7a89 2435 /* Bit 0 : Disable interrupt on IN[0] event. */
Kojto 91:031413cf7a89 2436 #define GPIOTE_INTENCLR_IN0_Pos (0UL) /*!< Position of IN0 field. */
Kojto 91:031413cf7a89 2437 #define GPIOTE_INTENCLR_IN0_Msk (0x1UL << GPIOTE_INTENCLR_IN0_Pos) /*!< Bit mask of IN0 field. */
Kojto 91:031413cf7a89 2438 #define GPIOTE_INTENCLR_IN0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2439 #define GPIOTE_INTENCLR_IN0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2440 #define GPIOTE_INTENCLR_IN0_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 2441
Kojto 91:031413cf7a89 2442 /* Register: GPIOTE_CONFIG */
Kojto 91:031413cf7a89 2443 /* Description: Channel configuration registers. */
Kojto 91:031413cf7a89 2444
Kojto 91:031413cf7a89 2445 /* Bit 20 : Initial value of the output when the GPIOTE channel is configured as a Task. */
Kojto 91:031413cf7a89 2446 #define GPIOTE_CONFIG_OUTINIT_Pos (20UL) /*!< Position of OUTINIT field. */
Kojto 91:031413cf7a89 2447 #define GPIOTE_CONFIG_OUTINIT_Msk (0x1UL << GPIOTE_CONFIG_OUTINIT_Pos) /*!< Bit mask of OUTINIT field. */
Kojto 91:031413cf7a89 2448 #define GPIOTE_CONFIG_OUTINIT_Low (0UL) /*!< Initial low output when in task mode. */
Kojto 91:031413cf7a89 2449 #define GPIOTE_CONFIG_OUTINIT_High (1UL) /*!< Initial high output when in task mode. */
Kojto 91:031413cf7a89 2450
Kojto 91:031413cf7a89 2451 /* Bits 17..16 : Effects on output when in Task mode, or events on input that generates an event. */
Kojto 91:031413cf7a89 2452 #define GPIOTE_CONFIG_POLARITY_Pos (16UL) /*!< Position of POLARITY field. */
Kojto 91:031413cf7a89 2453 #define GPIOTE_CONFIG_POLARITY_Msk (0x3UL << GPIOTE_CONFIG_POLARITY_Pos) /*!< Bit mask of POLARITY field. */
Kojto 91:031413cf7a89 2454 #define GPIOTE_CONFIG_POLARITY_LoToHi (0x01UL) /*!< Low to high. */
Kojto 91:031413cf7a89 2455 #define GPIOTE_CONFIG_POLARITY_HiToLo (0x02UL) /*!< High to low. */
Kojto 91:031413cf7a89 2456 #define GPIOTE_CONFIG_POLARITY_Toggle (0x03UL) /*!< Toggle. */
Kojto 91:031413cf7a89 2457
Kojto 91:031413cf7a89 2458 /* Bits 12..8 : Pin select. */
Kojto 91:031413cf7a89 2459 #define GPIOTE_CONFIG_PSEL_Pos (8UL) /*!< Position of PSEL field. */
Kojto 91:031413cf7a89 2460 #define GPIOTE_CONFIG_PSEL_Msk (0x1FUL << GPIOTE_CONFIG_PSEL_Pos) /*!< Bit mask of PSEL field. */
Kojto 91:031413cf7a89 2461
Kojto 91:031413cf7a89 2462 /* Bits 1..0 : Mode */
Kojto 91:031413cf7a89 2463 #define GPIOTE_CONFIG_MODE_Pos (0UL) /*!< Position of MODE field. */
Kojto 91:031413cf7a89 2464 #define GPIOTE_CONFIG_MODE_Msk (0x3UL << GPIOTE_CONFIG_MODE_Pos) /*!< Bit mask of MODE field. */
Kojto 91:031413cf7a89 2465 #define GPIOTE_CONFIG_MODE_Disabled (0x00UL) /*!< Disabled. */
Kojto 91:031413cf7a89 2466 #define GPIOTE_CONFIG_MODE_Event (0x01UL) /*!< Channel configure in event mode. */
Kojto 91:031413cf7a89 2467 #define GPIOTE_CONFIG_MODE_Task (0x03UL) /*!< Channel configure in task mode. */
Kojto 91:031413cf7a89 2468
Kojto 91:031413cf7a89 2469 /* Register: GPIOTE_POWER */
Kojto 91:031413cf7a89 2470 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 2471
Kojto 91:031413cf7a89 2472 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 2473 #define GPIOTE_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 2474 #define GPIOTE_POWER_POWER_Msk (0x1UL << GPIOTE_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 2475 #define GPIOTE_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 2476 #define GPIOTE_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 2477
Kojto 91:031413cf7a89 2478
Kojto 91:031413cf7a89 2479 /* Peripheral: LPCOMP */
Kojto 91:031413cf7a89 2480 /* Description: Wakeup Comparator. */
Kojto 91:031413cf7a89 2481
Kojto 91:031413cf7a89 2482 /* Register: LPCOMP_SHORTS */
Kojto 91:031413cf7a89 2483 /* Description: Shortcut for the LPCOMP. */
Kojto 91:031413cf7a89 2484
Kojto 91:031413cf7a89 2485 /* Bit 4 : Short-cut between CROSS event and STOP task. */
Kojto 91:031413cf7a89 2486 #define LPCOMP_SHORTS_CROSS_STOP_Pos (4UL) /*!< Position of CROSS_STOP field. */
Kojto 91:031413cf7a89 2487 #define LPCOMP_SHORTS_CROSS_STOP_Msk (0x1UL << LPCOMP_SHORTS_CROSS_STOP_Pos) /*!< Bit mask of CROSS_STOP field. */
Kojto 91:031413cf7a89 2488 #define LPCOMP_SHORTS_CROSS_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 2489 #define LPCOMP_SHORTS_CROSS_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 2490
Kojto 91:031413cf7a89 2491 /* Bit 3 : Short-cut between UP event and STOP task. */
Kojto 91:031413cf7a89 2492 #define LPCOMP_SHORTS_UP_STOP_Pos (3UL) /*!< Position of UP_STOP field. */
Kojto 91:031413cf7a89 2493 #define LPCOMP_SHORTS_UP_STOP_Msk (0x1UL << LPCOMP_SHORTS_UP_STOP_Pos) /*!< Bit mask of UP_STOP field. */
Kojto 91:031413cf7a89 2494 #define LPCOMP_SHORTS_UP_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 2495 #define LPCOMP_SHORTS_UP_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 2496
Kojto 91:031413cf7a89 2497 /* Bit 2 : Short-cut between DOWN event and STOP task. */
Kojto 91:031413cf7a89 2498 #define LPCOMP_SHORTS_DOWN_STOP_Pos (2UL) /*!< Position of DOWN_STOP field. */
Kojto 91:031413cf7a89 2499 #define LPCOMP_SHORTS_DOWN_STOP_Msk (0x1UL << LPCOMP_SHORTS_DOWN_STOP_Pos) /*!< Bit mask of DOWN_STOP field. */
Kojto 91:031413cf7a89 2500 #define LPCOMP_SHORTS_DOWN_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 2501 #define LPCOMP_SHORTS_DOWN_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 2502
Kojto 91:031413cf7a89 2503 /* Bit 1 : Short-cut between RADY event and STOP task. */
Kojto 91:031413cf7a89 2504 #define LPCOMP_SHORTS_READY_STOP_Pos (1UL) /*!< Position of READY_STOP field. */
Kojto 91:031413cf7a89 2505 #define LPCOMP_SHORTS_READY_STOP_Msk (0x1UL << LPCOMP_SHORTS_READY_STOP_Pos) /*!< Bit mask of READY_STOP field. */
Kojto 91:031413cf7a89 2506 #define LPCOMP_SHORTS_READY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 2507 #define LPCOMP_SHORTS_READY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 2508
Kojto 91:031413cf7a89 2509 /* Bit 0 : Short-cut between READY event and SAMPLE task. */
Kojto 91:031413cf7a89 2510 #define LPCOMP_SHORTS_READY_SAMPLE_Pos (0UL) /*!< Position of READY_SAMPLE field. */
Kojto 91:031413cf7a89 2511 #define LPCOMP_SHORTS_READY_SAMPLE_Msk (0x1UL << LPCOMP_SHORTS_READY_SAMPLE_Pos) /*!< Bit mask of READY_SAMPLE field. */
Kojto 91:031413cf7a89 2512 #define LPCOMP_SHORTS_READY_SAMPLE_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 2513 #define LPCOMP_SHORTS_READY_SAMPLE_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 2514
Kojto 91:031413cf7a89 2515 /* Register: LPCOMP_INTENSET */
Kojto 91:031413cf7a89 2516 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 2517
Kojto 91:031413cf7a89 2518 /* Bit 3 : Enable interrupt on CROSS event. */
Kojto 91:031413cf7a89 2519 #define LPCOMP_INTENSET_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Kojto 91:031413cf7a89 2520 #define LPCOMP_INTENSET_CROSS_Msk (0x1UL << LPCOMP_INTENSET_CROSS_Pos) /*!< Bit mask of CROSS field. */
Kojto 91:031413cf7a89 2521 #define LPCOMP_INTENSET_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2522 #define LPCOMP_INTENSET_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2523 #define LPCOMP_INTENSET_CROSS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 2524
Kojto 91:031413cf7a89 2525 /* Bit 2 : Enable interrupt on UP event. */
Kojto 91:031413cf7a89 2526 #define LPCOMP_INTENSET_UP_Pos (2UL) /*!< Position of UP field. */
Kojto 91:031413cf7a89 2527 #define LPCOMP_INTENSET_UP_Msk (0x1UL << LPCOMP_INTENSET_UP_Pos) /*!< Bit mask of UP field. */
Kojto 91:031413cf7a89 2528 #define LPCOMP_INTENSET_UP_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2529 #define LPCOMP_INTENSET_UP_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2530 #define LPCOMP_INTENSET_UP_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 2531
Kojto 91:031413cf7a89 2532 /* Bit 1 : Enable interrupt on DOWN event. */
Kojto 91:031413cf7a89 2533 #define LPCOMP_INTENSET_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Kojto 91:031413cf7a89 2534 #define LPCOMP_INTENSET_DOWN_Msk (0x1UL << LPCOMP_INTENSET_DOWN_Pos) /*!< Bit mask of DOWN field. */
Kojto 91:031413cf7a89 2535 #define LPCOMP_INTENSET_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2536 #define LPCOMP_INTENSET_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2537 #define LPCOMP_INTENSET_DOWN_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 2538
Kojto 91:031413cf7a89 2539 /* Bit 0 : Enable interrupt on READY event. */
Kojto 91:031413cf7a89 2540 #define LPCOMP_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 91:031413cf7a89 2541 #define LPCOMP_INTENSET_READY_Msk (0x1UL << LPCOMP_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Kojto 91:031413cf7a89 2542 #define LPCOMP_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2543 #define LPCOMP_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2544 #define LPCOMP_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 2545
Kojto 91:031413cf7a89 2546 /* Register: LPCOMP_INTENCLR */
Kojto 91:031413cf7a89 2547 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 2548
Kojto 91:031413cf7a89 2549 /* Bit 3 : Disable interrupt on CROSS event. */
Kojto 91:031413cf7a89 2550 #define LPCOMP_INTENCLR_CROSS_Pos (3UL) /*!< Position of CROSS field. */
Kojto 91:031413cf7a89 2551 #define LPCOMP_INTENCLR_CROSS_Msk (0x1UL << LPCOMP_INTENCLR_CROSS_Pos) /*!< Bit mask of CROSS field. */
Kojto 91:031413cf7a89 2552 #define LPCOMP_INTENCLR_CROSS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2553 #define LPCOMP_INTENCLR_CROSS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2554 #define LPCOMP_INTENCLR_CROSS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 2555
Kojto 91:031413cf7a89 2556 /* Bit 2 : Disable interrupt on UP event. */
Kojto 91:031413cf7a89 2557 #define LPCOMP_INTENCLR_UP_Pos (2UL) /*!< Position of UP field. */
Kojto 91:031413cf7a89 2558 #define LPCOMP_INTENCLR_UP_Msk (0x1UL << LPCOMP_INTENCLR_UP_Pos) /*!< Bit mask of UP field. */
Kojto 91:031413cf7a89 2559 #define LPCOMP_INTENCLR_UP_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2560 #define LPCOMP_INTENCLR_UP_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2561 #define LPCOMP_INTENCLR_UP_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 2562
Kojto 91:031413cf7a89 2563 /* Bit 1 : Disable interrupt on DOWN event. */
Kojto 91:031413cf7a89 2564 #define LPCOMP_INTENCLR_DOWN_Pos (1UL) /*!< Position of DOWN field. */
Kojto 91:031413cf7a89 2565 #define LPCOMP_INTENCLR_DOWN_Msk (0x1UL << LPCOMP_INTENCLR_DOWN_Pos) /*!< Bit mask of DOWN field. */
Kojto 91:031413cf7a89 2566 #define LPCOMP_INTENCLR_DOWN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2567 #define LPCOMP_INTENCLR_DOWN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2568 #define LPCOMP_INTENCLR_DOWN_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 2569
Kojto 91:031413cf7a89 2570 /* Bit 0 : Disable interrupt on READY event. */
Kojto 91:031413cf7a89 2571 #define LPCOMP_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 91:031413cf7a89 2572 #define LPCOMP_INTENCLR_READY_Msk (0x1UL << LPCOMP_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Kojto 91:031413cf7a89 2573 #define LPCOMP_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 2574 #define LPCOMP_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 2575 #define LPCOMP_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 2576
Kojto 91:031413cf7a89 2577 /* Register: LPCOMP_RESULT */
Kojto 91:031413cf7a89 2578 /* Description: Result of last compare. */
Kojto 91:031413cf7a89 2579
Kojto 91:031413cf7a89 2580 /* Bit 0 : Result of last compare. Decision point SAMPLE task. */
Kojto 91:031413cf7a89 2581 #define LPCOMP_RESULT_RESULT_Pos (0UL) /*!< Position of RESULT field. */
Kojto 91:031413cf7a89 2582 #define LPCOMP_RESULT_RESULT_Msk (0x1UL << LPCOMP_RESULT_RESULT_Pos) /*!< Bit mask of RESULT field. */
Kojto 91:031413cf7a89 2583 #define LPCOMP_RESULT_RESULT_Bellow (0UL) /*!< Input voltage is bellow the reference threshold. */
Kojto 91:031413cf7a89 2584 #define LPCOMP_RESULT_RESULT_Above (1UL) /*!< Input voltage is above the reference threshold. */
Kojto 91:031413cf7a89 2585
Kojto 91:031413cf7a89 2586 /* Register: LPCOMP_ENABLE */
Kojto 91:031413cf7a89 2587 /* Description: Enable the LPCOMP. */
Kojto 91:031413cf7a89 2588
Kojto 91:031413cf7a89 2589 /* Bits 1..0 : Enable or disable LPCOMP. */
Kojto 91:031413cf7a89 2590 #define LPCOMP_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 2591 #define LPCOMP_ENABLE_ENABLE_Msk (0x3UL << LPCOMP_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 2592 #define LPCOMP_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled LPCOMP. */
Kojto 91:031413cf7a89 2593 #define LPCOMP_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable LPCOMP. */
Kojto 91:031413cf7a89 2594
Kojto 91:031413cf7a89 2595 /* Register: LPCOMP_PSEL */
Kojto 91:031413cf7a89 2596 /* Description: Input pin select. */
Kojto 91:031413cf7a89 2597
Kojto 91:031413cf7a89 2598 /* Bits 2..0 : Analog input pin select. */
Kojto 91:031413cf7a89 2599 #define LPCOMP_PSEL_PSEL_Pos (0UL) /*!< Position of PSEL field. */
Kojto 91:031413cf7a89 2600 #define LPCOMP_PSEL_PSEL_Msk (0x7UL << LPCOMP_PSEL_PSEL_Pos) /*!< Bit mask of PSEL field. */
Kojto 91:031413cf7a89 2601 #define LPCOMP_PSEL_PSEL_AnalogInput0 (0UL) /*!< Use analog input 0 as analog input. */
Kojto 91:031413cf7a89 2602 #define LPCOMP_PSEL_PSEL_AnalogInput1 (1UL) /*!< Use analog input 1 as analog input. */
Kojto 91:031413cf7a89 2603 #define LPCOMP_PSEL_PSEL_AnalogInput2 (2UL) /*!< Use analog input 2 as analog input. */
Kojto 91:031413cf7a89 2604 #define LPCOMP_PSEL_PSEL_AnalogInput3 (3UL) /*!< Use analog input 3 as analog input. */
Kojto 91:031413cf7a89 2605 #define LPCOMP_PSEL_PSEL_AnalogInput4 (4UL) /*!< Use analog input 4 as analog input. */
Kojto 91:031413cf7a89 2606 #define LPCOMP_PSEL_PSEL_AnalogInput5 (5UL) /*!< Use analog input 5 as analog input. */
Kojto 91:031413cf7a89 2607 #define LPCOMP_PSEL_PSEL_AnalogInput6 (6UL) /*!< Use analog input 6 as analog input. */
Kojto 91:031413cf7a89 2608 #define LPCOMP_PSEL_PSEL_AnalogInput7 (7UL) /*!< Use analog input 7 as analog input. */
Kojto 91:031413cf7a89 2609
Kojto 91:031413cf7a89 2610 /* Register: LPCOMP_REFSEL */
Kojto 91:031413cf7a89 2611 /* Description: Reference select. */
Kojto 91:031413cf7a89 2612
Kojto 91:031413cf7a89 2613 /* Bits 2..0 : Reference select. */
Kojto 91:031413cf7a89 2614 #define LPCOMP_REFSEL_REFSEL_Pos (0UL) /*!< Position of REFSEL field. */
Kojto 91:031413cf7a89 2615 #define LPCOMP_REFSEL_REFSEL_Msk (0x7UL << LPCOMP_REFSEL_REFSEL_Pos) /*!< Bit mask of REFSEL field. */
Kojto 91:031413cf7a89 2616 #define LPCOMP_REFSEL_REFSEL_SupplyOneEighthPrescaling (0UL) /*!< Use analog supply with a 1/8 prescaler as reference. */
Kojto 91:031413cf7a89 2617 #define LPCOMP_REFSEL_REFSEL_SupplyTwoEighthsPrescaling (1UL) /*!< Use analog supply with a 2/8 prescaler as reference. */
Kojto 91:031413cf7a89 2618 #define LPCOMP_REFSEL_REFSEL_SupplyThreeEighthsPrescaling (2UL) /*!< Use analog supply with a 3/8 prescaler as reference. */
Kojto 91:031413cf7a89 2619 #define LPCOMP_REFSEL_REFSEL_SupplyFourEighthsPrescaling (3UL) /*!< Use analog supply with a 4/8 prescaler as reference. */
Kojto 91:031413cf7a89 2620 #define LPCOMP_REFSEL_REFSEL_SupplyFiveEighthsPrescaling (4UL) /*!< Use analog supply with a 5/8 prescaler as reference. */
Kojto 91:031413cf7a89 2621 #define LPCOMP_REFSEL_REFSEL_SupplySixEighthsPrescaling (5UL) /*!< Use analog supply with a 6/8 prescaler as reference. */
Kojto 91:031413cf7a89 2622 #define LPCOMP_REFSEL_REFSEL_SupplySevenEighthsPrescaling (6UL) /*!< Use analog supply with a 7/8 prescaler as reference. */
Kojto 91:031413cf7a89 2623 #define LPCOMP_REFSEL_REFSEL_ARef (7UL) /*!< Use external analog reference as reference. */
Kojto 91:031413cf7a89 2624
Kojto 91:031413cf7a89 2625 /* Register: LPCOMP_EXTREFSEL */
Kojto 91:031413cf7a89 2626 /* Description: External reference select. */
Kojto 91:031413cf7a89 2627
Kojto 91:031413cf7a89 2628 /* Bit 0 : External analog reference pin selection. */
Kojto 91:031413cf7a89 2629 #define LPCOMP_EXTREFSEL_EXTREFSEL_Pos (0UL) /*!< Position of EXTREFSEL field. */
Kojto 91:031413cf7a89 2630 #define LPCOMP_EXTREFSEL_EXTREFSEL_Msk (0x1UL << LPCOMP_EXTREFSEL_EXTREFSEL_Pos) /*!< Bit mask of EXTREFSEL field. */
Kojto 91:031413cf7a89 2631 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference0 (0UL) /*!< Use analog reference 0 as reference. */
Kojto 91:031413cf7a89 2632 #define LPCOMP_EXTREFSEL_EXTREFSEL_AnalogReference1 (1UL) /*!< Use analog reference 1 as reference. */
Kojto 91:031413cf7a89 2633
Kojto 91:031413cf7a89 2634 /* Register: LPCOMP_ANADETECT */
Kojto 91:031413cf7a89 2635 /* Description: Analog detect configuration. */
Kojto 91:031413cf7a89 2636
Kojto 91:031413cf7a89 2637 /* Bits 1..0 : Analog detect configuration. */
Kojto 91:031413cf7a89 2638 #define LPCOMP_ANADETECT_ANADETECT_Pos (0UL) /*!< Position of ANADETECT field. */
Kojto 91:031413cf7a89 2639 #define LPCOMP_ANADETECT_ANADETECT_Msk (0x3UL << LPCOMP_ANADETECT_ANADETECT_Pos) /*!< Bit mask of ANADETECT field. */
Kojto 91:031413cf7a89 2640 #define LPCOMP_ANADETECT_ANADETECT_Cross (0UL) /*!< Generate ANADETEC on crossing, both upwards and downwards crossing. */
Kojto 91:031413cf7a89 2641 #define LPCOMP_ANADETECT_ANADETECT_Up (1UL) /*!< Generate ANADETEC on upwards crossing only. */
Kojto 91:031413cf7a89 2642 #define LPCOMP_ANADETECT_ANADETECT_Down (2UL) /*!< Generate ANADETEC on downwards crossing only. */
Kojto 91:031413cf7a89 2643
Kojto 91:031413cf7a89 2644 /* Register: LPCOMP_POWER */
Kojto 91:031413cf7a89 2645 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 2646
Kojto 91:031413cf7a89 2647 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 2648 #define LPCOMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 2649 #define LPCOMP_POWER_POWER_Msk (0x1UL << LPCOMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 2650 #define LPCOMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 2651 #define LPCOMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 2652
Kojto 91:031413cf7a89 2653
Kojto 91:031413cf7a89 2654 /* Peripheral: MPU */
Kojto 91:031413cf7a89 2655 /* Description: Memory Protection Unit. */
Kojto 91:031413cf7a89 2656
Kojto 91:031413cf7a89 2657 /* Register: MPU_PERR0 */
Kojto 91:031413cf7a89 2658 /* Description: Configuration of peripherals in mpu regions. */
Kojto 91:031413cf7a89 2659
Kojto 91:031413cf7a89 2660 /* Bit 31 : PPI region configuration. */
Kojto 91:031413cf7a89 2661 #define MPU_PERR0_PPI_Pos (31UL) /*!< Position of PPI field. */
Kojto 91:031413cf7a89 2662 #define MPU_PERR0_PPI_Msk (0x1UL << MPU_PERR0_PPI_Pos) /*!< Bit mask of PPI field. */
Kojto 91:031413cf7a89 2663 #define MPU_PERR0_PPI_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2664 #define MPU_PERR0_PPI_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2665
Kojto 91:031413cf7a89 2666 /* Bit 30 : NVMC region configuration. */
Kojto 91:031413cf7a89 2667 #define MPU_PERR0_NVMC_Pos (30UL) /*!< Position of NVMC field. */
Kojto 91:031413cf7a89 2668 #define MPU_PERR0_NVMC_Msk (0x1UL << MPU_PERR0_NVMC_Pos) /*!< Bit mask of NVMC field. */
Kojto 91:031413cf7a89 2669 #define MPU_PERR0_NVMC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2670 #define MPU_PERR0_NVMC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2671
Kojto 91:031413cf7a89 2672 /* Bit 19 : LPCOMP_COMP region configuration. */
Kojto 91:031413cf7a89 2673 #define MPU_PERR0_LPCOMP_COMP_Pos (19UL) /*!< Position of LPCOMP_COMP field. */
Kojto 91:031413cf7a89 2674 #define MPU_PERR0_LPCOMP_COMP_Msk (0x1UL << MPU_PERR0_LPCOMP_COMP_Pos) /*!< Bit mask of LPCOMP_COMP field. */
Kojto 91:031413cf7a89 2675 #define MPU_PERR0_LPCOMP_COMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2676 #define MPU_PERR0_LPCOMP_COMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2677
Kojto 91:031413cf7a89 2678 /* Bit 18 : QDEC region configuration. */
Kojto 91:031413cf7a89 2679 #define MPU_PERR0_QDEC_Pos (18UL) /*!< Position of QDEC field. */
Kojto 91:031413cf7a89 2680 #define MPU_PERR0_QDEC_Msk (0x1UL << MPU_PERR0_QDEC_Pos) /*!< Bit mask of QDEC field. */
Kojto 91:031413cf7a89 2681 #define MPU_PERR0_QDEC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2682 #define MPU_PERR0_QDEC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2683
Kojto 91:031413cf7a89 2684 /* Bit 17 : RTC1 region configuration. */
Kojto 91:031413cf7a89 2685 #define MPU_PERR0_RTC1_Pos (17UL) /*!< Position of RTC1 field. */
Kojto 91:031413cf7a89 2686 #define MPU_PERR0_RTC1_Msk (0x1UL << MPU_PERR0_RTC1_Pos) /*!< Bit mask of RTC1 field. */
Kojto 91:031413cf7a89 2687 #define MPU_PERR0_RTC1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2688 #define MPU_PERR0_RTC1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2689
Kojto 91:031413cf7a89 2690 /* Bit 16 : WDT region configuration. */
Kojto 91:031413cf7a89 2691 #define MPU_PERR0_WDT_Pos (16UL) /*!< Position of WDT field. */
Kojto 91:031413cf7a89 2692 #define MPU_PERR0_WDT_Msk (0x1UL << MPU_PERR0_WDT_Pos) /*!< Bit mask of WDT field. */
Kojto 91:031413cf7a89 2693 #define MPU_PERR0_WDT_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2694 #define MPU_PERR0_WDT_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2695
Kojto 91:031413cf7a89 2696 /* Bit 15 : CCM and AAR region configuration. */
Kojto 91:031413cf7a89 2697 #define MPU_PERR0_CCM_AAR_Pos (15UL) /*!< Position of CCM_AAR field. */
Kojto 91:031413cf7a89 2698 #define MPU_PERR0_CCM_AAR_Msk (0x1UL << MPU_PERR0_CCM_AAR_Pos) /*!< Bit mask of CCM_AAR field. */
Kojto 91:031413cf7a89 2699 #define MPU_PERR0_CCM_AAR_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2700 #define MPU_PERR0_CCM_AAR_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2701
Kojto 91:031413cf7a89 2702 /* Bit 14 : ECB region configuration. */
Kojto 91:031413cf7a89 2703 #define MPU_PERR0_ECB_Pos (14UL) /*!< Position of ECB field. */
Kojto 91:031413cf7a89 2704 #define MPU_PERR0_ECB_Msk (0x1UL << MPU_PERR0_ECB_Pos) /*!< Bit mask of ECB field. */
Kojto 91:031413cf7a89 2705 #define MPU_PERR0_ECB_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2706 #define MPU_PERR0_ECB_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2707
Kojto 91:031413cf7a89 2708 /* Bit 13 : RNG region configuration. */
Kojto 91:031413cf7a89 2709 #define MPU_PERR0_RNG_Pos (13UL) /*!< Position of RNG field. */
Kojto 91:031413cf7a89 2710 #define MPU_PERR0_RNG_Msk (0x1UL << MPU_PERR0_RNG_Pos) /*!< Bit mask of RNG field. */
Kojto 91:031413cf7a89 2711 #define MPU_PERR0_RNG_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2712 #define MPU_PERR0_RNG_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2713
Kojto 91:031413cf7a89 2714 /* Bit 12 : TEMP region configuration. */
Kojto 91:031413cf7a89 2715 #define MPU_PERR0_TEMP_Pos (12UL) /*!< Position of TEMP field. */
Kojto 91:031413cf7a89 2716 #define MPU_PERR0_TEMP_Msk (0x1UL << MPU_PERR0_TEMP_Pos) /*!< Bit mask of TEMP field. */
Kojto 91:031413cf7a89 2717 #define MPU_PERR0_TEMP_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2718 #define MPU_PERR0_TEMP_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2719
Kojto 91:031413cf7a89 2720 /* Bit 11 : RTC0 region configuration. */
Kojto 91:031413cf7a89 2721 #define MPU_PERR0_RTC0_Pos (11UL) /*!< Position of RTC0 field. */
Kojto 91:031413cf7a89 2722 #define MPU_PERR0_RTC0_Msk (0x1UL << MPU_PERR0_RTC0_Pos) /*!< Bit mask of RTC0 field. */
Kojto 91:031413cf7a89 2723 #define MPU_PERR0_RTC0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2724 #define MPU_PERR0_RTC0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2725
Kojto 91:031413cf7a89 2726 /* Bit 10 : TIMER2 region configuration. */
Kojto 91:031413cf7a89 2727 #define MPU_PERR0_TIMER2_Pos (10UL) /*!< Position of TIMER2 field. */
Kojto 91:031413cf7a89 2728 #define MPU_PERR0_TIMER2_Msk (0x1UL << MPU_PERR0_TIMER2_Pos) /*!< Bit mask of TIMER2 field. */
Kojto 91:031413cf7a89 2729 #define MPU_PERR0_TIMER2_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2730 #define MPU_PERR0_TIMER2_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2731
Kojto 91:031413cf7a89 2732 /* Bit 9 : TIMER1 region configuration. */
Kojto 91:031413cf7a89 2733 #define MPU_PERR0_TIMER1_Pos (9UL) /*!< Position of TIMER1 field. */
Kojto 91:031413cf7a89 2734 #define MPU_PERR0_TIMER1_Msk (0x1UL << MPU_PERR0_TIMER1_Pos) /*!< Bit mask of TIMER1 field. */
Kojto 91:031413cf7a89 2735 #define MPU_PERR0_TIMER1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2736 #define MPU_PERR0_TIMER1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2737
Kojto 91:031413cf7a89 2738 /* Bit 8 : TIMER0 region configuration. */
Kojto 91:031413cf7a89 2739 #define MPU_PERR0_TIMER0_Pos (8UL) /*!< Position of TIMER0 field. */
Kojto 91:031413cf7a89 2740 #define MPU_PERR0_TIMER0_Msk (0x1UL << MPU_PERR0_TIMER0_Pos) /*!< Bit mask of TIMER0 field. */
Kojto 91:031413cf7a89 2741 #define MPU_PERR0_TIMER0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2742 #define MPU_PERR0_TIMER0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2743
Kojto 91:031413cf7a89 2744 /* Bit 7 : ADC region configuration. */
Kojto 91:031413cf7a89 2745 #define MPU_PERR0_ADC_Pos (7UL) /*!< Position of ADC field. */
Kojto 91:031413cf7a89 2746 #define MPU_PERR0_ADC_Msk (0x1UL << MPU_PERR0_ADC_Pos) /*!< Bit mask of ADC field. */
Kojto 91:031413cf7a89 2747 #define MPU_PERR0_ADC_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2748 #define MPU_PERR0_ADC_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2749
Kojto 91:031413cf7a89 2750 /* Bit 6 : GPIOTE region configuration. */
Kojto 91:031413cf7a89 2751 #define MPU_PERR0_GPIOTE_Pos (6UL) /*!< Position of GPIOTE field. */
Kojto 91:031413cf7a89 2752 #define MPU_PERR0_GPIOTE_Msk (0x1UL << MPU_PERR0_GPIOTE_Pos) /*!< Bit mask of GPIOTE field. */
Kojto 91:031413cf7a89 2753 #define MPU_PERR0_GPIOTE_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2754 #define MPU_PERR0_GPIOTE_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2755
Kojto 91:031413cf7a89 2756 /* Bit 4 : SPI1 and TWI1 region configuration. */
Kojto 91:031413cf7a89 2757 #define MPU_PERR0_SPI1_TWI1_Pos (4UL) /*!< Position of SPI1_TWI1 field. */
Kojto 91:031413cf7a89 2758 #define MPU_PERR0_SPI1_TWI1_Msk (0x1UL << MPU_PERR0_SPI1_TWI1_Pos) /*!< Bit mask of SPI1_TWI1 field. */
Kojto 91:031413cf7a89 2759 #define MPU_PERR0_SPI1_TWI1_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2760 #define MPU_PERR0_SPI1_TWI1_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2761
Kojto 91:031413cf7a89 2762 /* Bit 3 : SPI0 and TWI0 region configuration. */
Kojto 91:031413cf7a89 2763 #define MPU_PERR0_SPI0_TWI0_Pos (3UL) /*!< Position of SPI0_TWI0 field. */
Kojto 91:031413cf7a89 2764 #define MPU_PERR0_SPI0_TWI0_Msk (0x1UL << MPU_PERR0_SPI0_TWI0_Pos) /*!< Bit mask of SPI0_TWI0 field. */
Kojto 91:031413cf7a89 2765 #define MPU_PERR0_SPI0_TWI0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2766 #define MPU_PERR0_SPI0_TWI0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2767
Kojto 91:031413cf7a89 2768 /* Bit 2 : UART0 region configuration. */
Kojto 91:031413cf7a89 2769 #define MPU_PERR0_UART0_Pos (2UL) /*!< Position of UART0 field. */
Kojto 91:031413cf7a89 2770 #define MPU_PERR0_UART0_Msk (0x1UL << MPU_PERR0_UART0_Pos) /*!< Bit mask of UART0 field. */
Kojto 91:031413cf7a89 2771 #define MPU_PERR0_UART0_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2772 #define MPU_PERR0_UART0_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2773
Kojto 91:031413cf7a89 2774 /* Bit 1 : RADIO region configuration. */
Kojto 91:031413cf7a89 2775 #define MPU_PERR0_RADIO_Pos (1UL) /*!< Position of RADIO field. */
Kojto 91:031413cf7a89 2776 #define MPU_PERR0_RADIO_Msk (0x1UL << MPU_PERR0_RADIO_Pos) /*!< Bit mask of RADIO field. */
Kojto 91:031413cf7a89 2777 #define MPU_PERR0_RADIO_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2778 #define MPU_PERR0_RADIO_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2779
Kojto 91:031413cf7a89 2780 /* Bit 0 : POWER_CLOCK region configuration. */
Kojto 91:031413cf7a89 2781 #define MPU_PERR0_POWER_CLOCK_Pos (0UL) /*!< Position of POWER_CLOCK field. */
Kojto 91:031413cf7a89 2782 #define MPU_PERR0_POWER_CLOCK_Msk (0x1UL << MPU_PERR0_POWER_CLOCK_Pos) /*!< Bit mask of POWER_CLOCK field. */
Kojto 91:031413cf7a89 2783 #define MPU_PERR0_POWER_CLOCK_InRegion1 (0UL) /*!< Peripheral configured in region 1. */
Kojto 91:031413cf7a89 2784 #define MPU_PERR0_POWER_CLOCK_InRegion0 (1UL) /*!< Peripheral configured in region 0. */
Kojto 91:031413cf7a89 2785
Kojto 91:031413cf7a89 2786 /* Register: MPU_PROTENSET0 */
Kojto 91:031413cf7a89 2787 /* Description: Protection bit enable set register for low addresses. */
Kojto 91:031413cf7a89 2788
Kojto 91:031413cf7a89 2789 /* Bit 31 : Protection enable for region 31. */
Kojto 91:031413cf7a89 2790 #define MPU_PROTENSET0_PROTREG31_Pos (31UL) /*!< Position of PROTREG31 field. */
Kojto 91:031413cf7a89 2791 #define MPU_PROTENSET0_PROTREG31_Msk (0x1UL << MPU_PROTENSET0_PROTREG31_Pos) /*!< Bit mask of PROTREG31 field. */
Kojto 91:031413cf7a89 2792 #define MPU_PROTENSET0_PROTREG31_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2793 #define MPU_PROTENSET0_PROTREG31_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2794 #define MPU_PROTENSET0_PROTREG31_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2795
Kojto 91:031413cf7a89 2796 /* Bit 30 : Protection enable for region 30. */
Kojto 91:031413cf7a89 2797 #define MPU_PROTENSET0_PROTREG30_Pos (30UL) /*!< Position of PROTREG30 field. */
Kojto 91:031413cf7a89 2798 #define MPU_PROTENSET0_PROTREG30_Msk (0x1UL << MPU_PROTENSET0_PROTREG30_Pos) /*!< Bit mask of PROTREG30 field. */
Kojto 91:031413cf7a89 2799 #define MPU_PROTENSET0_PROTREG30_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2800 #define MPU_PROTENSET0_PROTREG30_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2801 #define MPU_PROTENSET0_PROTREG30_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2802
Kojto 91:031413cf7a89 2803 /* Bit 29 : Protection enable for region 29. */
Kojto 91:031413cf7a89 2804 #define MPU_PROTENSET0_PROTREG29_Pos (29UL) /*!< Position of PROTREG29 field. */
Kojto 91:031413cf7a89 2805 #define MPU_PROTENSET0_PROTREG29_Msk (0x1UL << MPU_PROTENSET0_PROTREG29_Pos) /*!< Bit mask of PROTREG29 field. */
Kojto 91:031413cf7a89 2806 #define MPU_PROTENSET0_PROTREG29_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2807 #define MPU_PROTENSET0_PROTREG29_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2808 #define MPU_PROTENSET0_PROTREG29_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2809
Kojto 91:031413cf7a89 2810 /* Bit 28 : Protection enable for region 28. */
Kojto 91:031413cf7a89 2811 #define MPU_PROTENSET0_PROTREG28_Pos (28UL) /*!< Position of PROTREG28 field. */
Kojto 91:031413cf7a89 2812 #define MPU_PROTENSET0_PROTREG28_Msk (0x1UL << MPU_PROTENSET0_PROTREG28_Pos) /*!< Bit mask of PROTREG28 field. */
Kojto 91:031413cf7a89 2813 #define MPU_PROTENSET0_PROTREG28_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2814 #define MPU_PROTENSET0_PROTREG28_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2815 #define MPU_PROTENSET0_PROTREG28_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2816
Kojto 91:031413cf7a89 2817 /* Bit 27 : Protection enable for region 27. */
Kojto 91:031413cf7a89 2818 #define MPU_PROTENSET0_PROTREG27_Pos (27UL) /*!< Position of PROTREG27 field. */
Kojto 91:031413cf7a89 2819 #define MPU_PROTENSET0_PROTREG27_Msk (0x1UL << MPU_PROTENSET0_PROTREG27_Pos) /*!< Bit mask of PROTREG27 field. */
Kojto 91:031413cf7a89 2820 #define MPU_PROTENSET0_PROTREG27_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2821 #define MPU_PROTENSET0_PROTREG27_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2822 #define MPU_PROTENSET0_PROTREG27_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2823
Kojto 91:031413cf7a89 2824 /* Bit 26 : Protection enable for region 26. */
Kojto 91:031413cf7a89 2825 #define MPU_PROTENSET0_PROTREG26_Pos (26UL) /*!< Position of PROTREG26 field. */
Kojto 91:031413cf7a89 2826 #define MPU_PROTENSET0_PROTREG26_Msk (0x1UL << MPU_PROTENSET0_PROTREG26_Pos) /*!< Bit mask of PROTREG26 field. */
Kojto 91:031413cf7a89 2827 #define MPU_PROTENSET0_PROTREG26_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2828 #define MPU_PROTENSET0_PROTREG26_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2829 #define MPU_PROTENSET0_PROTREG26_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2830
Kojto 91:031413cf7a89 2831 /* Bit 25 : Protection enable for region 25. */
Kojto 91:031413cf7a89 2832 #define MPU_PROTENSET0_PROTREG25_Pos (25UL) /*!< Position of PROTREG25 field. */
Kojto 91:031413cf7a89 2833 #define MPU_PROTENSET0_PROTREG25_Msk (0x1UL << MPU_PROTENSET0_PROTREG25_Pos) /*!< Bit mask of PROTREG25 field. */
Kojto 91:031413cf7a89 2834 #define MPU_PROTENSET0_PROTREG25_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2835 #define MPU_PROTENSET0_PROTREG25_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2836 #define MPU_PROTENSET0_PROTREG25_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2837
Kojto 91:031413cf7a89 2838 /* Bit 24 : Protection enable for region 24. */
Kojto 91:031413cf7a89 2839 #define MPU_PROTENSET0_PROTREG24_Pos (24UL) /*!< Position of PROTREG24 field. */
Kojto 91:031413cf7a89 2840 #define MPU_PROTENSET0_PROTREG24_Msk (0x1UL << MPU_PROTENSET0_PROTREG24_Pos) /*!< Bit mask of PROTREG24 field. */
Kojto 91:031413cf7a89 2841 #define MPU_PROTENSET0_PROTREG24_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2842 #define MPU_PROTENSET0_PROTREG24_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2843 #define MPU_PROTENSET0_PROTREG24_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2844
Kojto 91:031413cf7a89 2845 /* Bit 23 : Protection enable for region 23. */
Kojto 91:031413cf7a89 2846 #define MPU_PROTENSET0_PROTREG23_Pos (23UL) /*!< Position of PROTREG23 field. */
Kojto 91:031413cf7a89 2847 #define MPU_PROTENSET0_PROTREG23_Msk (0x1UL << MPU_PROTENSET0_PROTREG23_Pos) /*!< Bit mask of PROTREG23 field. */
Kojto 91:031413cf7a89 2848 #define MPU_PROTENSET0_PROTREG23_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2849 #define MPU_PROTENSET0_PROTREG23_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2850 #define MPU_PROTENSET0_PROTREG23_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2851
Kojto 91:031413cf7a89 2852 /* Bit 22 : Protection enable for region 22. */
Kojto 91:031413cf7a89 2853 #define MPU_PROTENSET0_PROTREG22_Pos (22UL) /*!< Position of PROTREG22 field. */
Kojto 91:031413cf7a89 2854 #define MPU_PROTENSET0_PROTREG22_Msk (0x1UL << MPU_PROTENSET0_PROTREG22_Pos) /*!< Bit mask of PROTREG22 field. */
Kojto 91:031413cf7a89 2855 #define MPU_PROTENSET0_PROTREG22_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2856 #define MPU_PROTENSET0_PROTREG22_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2857 #define MPU_PROTENSET0_PROTREG22_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2858
Kojto 91:031413cf7a89 2859 /* Bit 21 : Protection enable for region 21. */
Kojto 91:031413cf7a89 2860 #define MPU_PROTENSET0_PROTREG21_Pos (21UL) /*!< Position of PROTREG21 field. */
Kojto 91:031413cf7a89 2861 #define MPU_PROTENSET0_PROTREG21_Msk (0x1UL << MPU_PROTENSET0_PROTREG21_Pos) /*!< Bit mask of PROTREG21 field. */
Kojto 91:031413cf7a89 2862 #define MPU_PROTENSET0_PROTREG21_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2863 #define MPU_PROTENSET0_PROTREG21_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2864 #define MPU_PROTENSET0_PROTREG21_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2865
Kojto 91:031413cf7a89 2866 /* Bit 20 : Protection enable for region 20. */
Kojto 91:031413cf7a89 2867 #define MPU_PROTENSET0_PROTREG20_Pos (20UL) /*!< Position of PROTREG20 field. */
Kojto 91:031413cf7a89 2868 #define MPU_PROTENSET0_PROTREG20_Msk (0x1UL << MPU_PROTENSET0_PROTREG20_Pos) /*!< Bit mask of PROTREG20 field. */
Kojto 91:031413cf7a89 2869 #define MPU_PROTENSET0_PROTREG20_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2870 #define MPU_PROTENSET0_PROTREG20_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2871 #define MPU_PROTENSET0_PROTREG20_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2872
Kojto 91:031413cf7a89 2873 /* Bit 19 : Protection enable for region 19. */
Kojto 91:031413cf7a89 2874 #define MPU_PROTENSET0_PROTREG19_Pos (19UL) /*!< Position of PROTREG19 field. */
Kojto 91:031413cf7a89 2875 #define MPU_PROTENSET0_PROTREG19_Msk (0x1UL << MPU_PROTENSET0_PROTREG19_Pos) /*!< Bit mask of PROTREG19 field. */
Kojto 91:031413cf7a89 2876 #define MPU_PROTENSET0_PROTREG19_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2877 #define MPU_PROTENSET0_PROTREG19_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2878 #define MPU_PROTENSET0_PROTREG19_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2879
Kojto 91:031413cf7a89 2880 /* Bit 18 : Protection enable for region 18. */
Kojto 91:031413cf7a89 2881 #define MPU_PROTENSET0_PROTREG18_Pos (18UL) /*!< Position of PROTREG18 field. */
Kojto 91:031413cf7a89 2882 #define MPU_PROTENSET0_PROTREG18_Msk (0x1UL << MPU_PROTENSET0_PROTREG18_Pos) /*!< Bit mask of PROTREG18 field. */
Kojto 91:031413cf7a89 2883 #define MPU_PROTENSET0_PROTREG18_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2884 #define MPU_PROTENSET0_PROTREG18_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2885 #define MPU_PROTENSET0_PROTREG18_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2886
Kojto 91:031413cf7a89 2887 /* Bit 17 : Protection enable for region 17. */
Kojto 91:031413cf7a89 2888 #define MPU_PROTENSET0_PROTREG17_Pos (17UL) /*!< Position of PROTREG17 field. */
Kojto 91:031413cf7a89 2889 #define MPU_PROTENSET0_PROTREG17_Msk (0x1UL << MPU_PROTENSET0_PROTREG17_Pos) /*!< Bit mask of PROTREG17 field. */
Kojto 91:031413cf7a89 2890 #define MPU_PROTENSET0_PROTREG17_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2891 #define MPU_PROTENSET0_PROTREG17_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2892 #define MPU_PROTENSET0_PROTREG17_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2893
Kojto 91:031413cf7a89 2894 /* Bit 16 : Protection enable for region 16. */
Kojto 91:031413cf7a89 2895 #define MPU_PROTENSET0_PROTREG16_Pos (16UL) /*!< Position of PROTREG16 field. */
Kojto 91:031413cf7a89 2896 #define MPU_PROTENSET0_PROTREG16_Msk (0x1UL << MPU_PROTENSET0_PROTREG16_Pos) /*!< Bit mask of PROTREG16 field. */
Kojto 91:031413cf7a89 2897 #define MPU_PROTENSET0_PROTREG16_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2898 #define MPU_PROTENSET0_PROTREG16_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2899 #define MPU_PROTENSET0_PROTREG16_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2900
Kojto 91:031413cf7a89 2901 /* Bit 15 : Protection enable for region 15. */
Kojto 91:031413cf7a89 2902 #define MPU_PROTENSET0_PROTREG15_Pos (15UL) /*!< Position of PROTREG15 field. */
Kojto 91:031413cf7a89 2903 #define MPU_PROTENSET0_PROTREG15_Msk (0x1UL << MPU_PROTENSET0_PROTREG15_Pos) /*!< Bit mask of PROTREG15 field. */
Kojto 91:031413cf7a89 2904 #define MPU_PROTENSET0_PROTREG15_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2905 #define MPU_PROTENSET0_PROTREG15_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2906 #define MPU_PROTENSET0_PROTREG15_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2907
Kojto 91:031413cf7a89 2908 /* Bit 14 : Protection enable for region 14. */
Kojto 91:031413cf7a89 2909 #define MPU_PROTENSET0_PROTREG14_Pos (14UL) /*!< Position of PROTREG14 field. */
Kojto 91:031413cf7a89 2910 #define MPU_PROTENSET0_PROTREG14_Msk (0x1UL << MPU_PROTENSET0_PROTREG14_Pos) /*!< Bit mask of PROTREG14 field. */
Kojto 91:031413cf7a89 2911 #define MPU_PROTENSET0_PROTREG14_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2912 #define MPU_PROTENSET0_PROTREG14_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2913 #define MPU_PROTENSET0_PROTREG14_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2914
Kojto 91:031413cf7a89 2915 /* Bit 13 : Protection enable for region 13. */
Kojto 91:031413cf7a89 2916 #define MPU_PROTENSET0_PROTREG13_Pos (13UL) /*!< Position of PROTREG13 field. */
Kojto 91:031413cf7a89 2917 #define MPU_PROTENSET0_PROTREG13_Msk (0x1UL << MPU_PROTENSET0_PROTREG13_Pos) /*!< Bit mask of PROTREG13 field. */
Kojto 91:031413cf7a89 2918 #define MPU_PROTENSET0_PROTREG13_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2919 #define MPU_PROTENSET0_PROTREG13_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2920 #define MPU_PROTENSET0_PROTREG13_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2921
Kojto 91:031413cf7a89 2922 /* Bit 12 : Protection enable for region 12. */
Kojto 91:031413cf7a89 2923 #define MPU_PROTENSET0_PROTREG12_Pos (12UL) /*!< Position of PROTREG12 field. */
Kojto 91:031413cf7a89 2924 #define MPU_PROTENSET0_PROTREG12_Msk (0x1UL << MPU_PROTENSET0_PROTREG12_Pos) /*!< Bit mask of PROTREG12 field. */
Kojto 91:031413cf7a89 2925 #define MPU_PROTENSET0_PROTREG12_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2926 #define MPU_PROTENSET0_PROTREG12_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2927 #define MPU_PROTENSET0_PROTREG12_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2928
Kojto 91:031413cf7a89 2929 /* Bit 11 : Protection enable for region 11. */
Kojto 91:031413cf7a89 2930 #define MPU_PROTENSET0_PROTREG11_Pos (11UL) /*!< Position of PROTREG11 field. */
Kojto 91:031413cf7a89 2931 #define MPU_PROTENSET0_PROTREG11_Msk (0x1UL << MPU_PROTENSET0_PROTREG11_Pos) /*!< Bit mask of PROTREG11 field. */
Kojto 91:031413cf7a89 2932 #define MPU_PROTENSET0_PROTREG11_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2933 #define MPU_PROTENSET0_PROTREG11_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2934 #define MPU_PROTENSET0_PROTREG11_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2935
Kojto 91:031413cf7a89 2936 /* Bit 10 : Protection enable for region 10. */
Kojto 91:031413cf7a89 2937 #define MPU_PROTENSET0_PROTREG10_Pos (10UL) /*!< Position of PROTREG10 field. */
Kojto 91:031413cf7a89 2938 #define MPU_PROTENSET0_PROTREG10_Msk (0x1UL << MPU_PROTENSET0_PROTREG10_Pos) /*!< Bit mask of PROTREG10 field. */
Kojto 91:031413cf7a89 2939 #define MPU_PROTENSET0_PROTREG10_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2940 #define MPU_PROTENSET0_PROTREG10_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2941 #define MPU_PROTENSET0_PROTREG10_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2942
Kojto 91:031413cf7a89 2943 /* Bit 9 : Protection enable for region 9. */
Kojto 91:031413cf7a89 2944 #define MPU_PROTENSET0_PROTREG9_Pos (9UL) /*!< Position of PROTREG9 field. */
Kojto 91:031413cf7a89 2945 #define MPU_PROTENSET0_PROTREG9_Msk (0x1UL << MPU_PROTENSET0_PROTREG9_Pos) /*!< Bit mask of PROTREG9 field. */
Kojto 91:031413cf7a89 2946 #define MPU_PROTENSET0_PROTREG9_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2947 #define MPU_PROTENSET0_PROTREG9_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2948 #define MPU_PROTENSET0_PROTREG9_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2949
Kojto 91:031413cf7a89 2950 /* Bit 8 : Protection enable for region 8. */
Kojto 91:031413cf7a89 2951 #define MPU_PROTENSET0_PROTREG8_Pos (8UL) /*!< Position of PROTREG8 field. */
Kojto 91:031413cf7a89 2952 #define MPU_PROTENSET0_PROTREG8_Msk (0x1UL << MPU_PROTENSET0_PROTREG8_Pos) /*!< Bit mask of PROTREG8 field. */
Kojto 91:031413cf7a89 2953 #define MPU_PROTENSET0_PROTREG8_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2954 #define MPU_PROTENSET0_PROTREG8_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2955 #define MPU_PROTENSET0_PROTREG8_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2956
Kojto 91:031413cf7a89 2957 /* Bit 7 : Protection enable for region 7. */
Kojto 91:031413cf7a89 2958 #define MPU_PROTENSET0_PROTREG7_Pos (7UL) /*!< Position of PROTREG7 field. */
Kojto 91:031413cf7a89 2959 #define MPU_PROTENSET0_PROTREG7_Msk (0x1UL << MPU_PROTENSET0_PROTREG7_Pos) /*!< Bit mask of PROTREG7 field. */
Kojto 91:031413cf7a89 2960 #define MPU_PROTENSET0_PROTREG7_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2961 #define MPU_PROTENSET0_PROTREG7_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2962 #define MPU_PROTENSET0_PROTREG7_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2963
Kojto 91:031413cf7a89 2964 /* Bit 6 : Protection enable for region 6. */
Kojto 91:031413cf7a89 2965 #define MPU_PROTENSET0_PROTREG6_Pos (6UL) /*!< Position of PROTREG6 field. */
Kojto 91:031413cf7a89 2966 #define MPU_PROTENSET0_PROTREG6_Msk (0x1UL << MPU_PROTENSET0_PROTREG6_Pos) /*!< Bit mask of PROTREG6 field. */
Kojto 91:031413cf7a89 2967 #define MPU_PROTENSET0_PROTREG6_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2968 #define MPU_PROTENSET0_PROTREG6_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2969 #define MPU_PROTENSET0_PROTREG6_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2970
Kojto 91:031413cf7a89 2971 /* Bit 5 : Protection enable for region 5. */
Kojto 91:031413cf7a89 2972 #define MPU_PROTENSET0_PROTREG5_Pos (5UL) /*!< Position of PROTREG5 field. */
Kojto 91:031413cf7a89 2973 #define MPU_PROTENSET0_PROTREG5_Msk (0x1UL << MPU_PROTENSET0_PROTREG5_Pos) /*!< Bit mask of PROTREG5 field. */
Kojto 91:031413cf7a89 2974 #define MPU_PROTENSET0_PROTREG5_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2975 #define MPU_PROTENSET0_PROTREG5_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2976 #define MPU_PROTENSET0_PROTREG5_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2977
Kojto 91:031413cf7a89 2978 /* Bit 4 : Protection enable for region 4. */
Kojto 91:031413cf7a89 2979 #define MPU_PROTENSET0_PROTREG4_Pos (4UL) /*!< Position of PROTREG4 field. */
Kojto 91:031413cf7a89 2980 #define MPU_PROTENSET0_PROTREG4_Msk (0x1UL << MPU_PROTENSET0_PROTREG4_Pos) /*!< Bit mask of PROTREG4 field. */
Kojto 91:031413cf7a89 2981 #define MPU_PROTENSET0_PROTREG4_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2982 #define MPU_PROTENSET0_PROTREG4_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2983 #define MPU_PROTENSET0_PROTREG4_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2984
Kojto 91:031413cf7a89 2985 /* Bit 3 : Protection enable for region 3. */
Kojto 91:031413cf7a89 2986 #define MPU_PROTENSET0_PROTREG3_Pos (3UL) /*!< Position of PROTREG3 field. */
Kojto 91:031413cf7a89 2987 #define MPU_PROTENSET0_PROTREG3_Msk (0x1UL << MPU_PROTENSET0_PROTREG3_Pos) /*!< Bit mask of PROTREG3 field. */
Kojto 91:031413cf7a89 2988 #define MPU_PROTENSET0_PROTREG3_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2989 #define MPU_PROTENSET0_PROTREG3_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2990 #define MPU_PROTENSET0_PROTREG3_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2991
Kojto 91:031413cf7a89 2992 /* Bit 2 : Protection enable for region 2. */
Kojto 91:031413cf7a89 2993 #define MPU_PROTENSET0_PROTREG2_Pos (2UL) /*!< Position of PROTREG2 field. */
Kojto 91:031413cf7a89 2994 #define MPU_PROTENSET0_PROTREG2_Msk (0x1UL << MPU_PROTENSET0_PROTREG2_Pos) /*!< Bit mask of PROTREG2 field. */
Kojto 91:031413cf7a89 2995 #define MPU_PROTENSET0_PROTREG2_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 2996 #define MPU_PROTENSET0_PROTREG2_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 2997 #define MPU_PROTENSET0_PROTREG2_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 2998
Kojto 91:031413cf7a89 2999 /* Bit 1 : Protection enable for region 1. */
Kojto 91:031413cf7a89 3000 #define MPU_PROTENSET0_PROTREG1_Pos (1UL) /*!< Position of PROTREG1 field. */
Kojto 91:031413cf7a89 3001 #define MPU_PROTENSET0_PROTREG1_Msk (0x1UL << MPU_PROTENSET0_PROTREG1_Pos) /*!< Bit mask of PROTREG1 field. */
Kojto 91:031413cf7a89 3002 #define MPU_PROTENSET0_PROTREG1_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3003 #define MPU_PROTENSET0_PROTREG1_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3004 #define MPU_PROTENSET0_PROTREG1_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3005
Kojto 91:031413cf7a89 3006 /* Bit 0 : Protection enable for region 0. */
Kojto 91:031413cf7a89 3007 #define MPU_PROTENSET0_PROTREG0_Pos (0UL) /*!< Position of PROTREG0 field. */
Kojto 91:031413cf7a89 3008 #define MPU_PROTENSET0_PROTREG0_Msk (0x1UL << MPU_PROTENSET0_PROTREG0_Pos) /*!< Bit mask of PROTREG0 field. */
Kojto 91:031413cf7a89 3009 #define MPU_PROTENSET0_PROTREG0_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3010 #define MPU_PROTENSET0_PROTREG0_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3011 #define MPU_PROTENSET0_PROTREG0_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3012
Kojto 91:031413cf7a89 3013 /* Register: MPU_PROTENSET1 */
Kojto 91:031413cf7a89 3014 /* Description: Protection bit enable set register for high addresses. */
Kojto 91:031413cf7a89 3015
Kojto 91:031413cf7a89 3016 /* Bit 31 : Protection enable for region 63. */
Kojto 91:031413cf7a89 3017 #define MPU_PROTENSET1_PROTREG63_Pos (31UL) /*!< Position of PROTREG63 field. */
Kojto 91:031413cf7a89 3018 #define MPU_PROTENSET1_PROTREG63_Msk (0x1UL << MPU_PROTENSET1_PROTREG63_Pos) /*!< Bit mask of PROTREG63 field. */
Kojto 91:031413cf7a89 3019 #define MPU_PROTENSET1_PROTREG63_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3020 #define MPU_PROTENSET1_PROTREG63_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3021 #define MPU_PROTENSET1_PROTREG63_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3022
Kojto 91:031413cf7a89 3023 /* Bit 30 : Protection enable for region 62. */
Kojto 91:031413cf7a89 3024 #define MPU_PROTENSET1_PROTREG62_Pos (30UL) /*!< Position of PROTREG62 field. */
Kojto 91:031413cf7a89 3025 #define MPU_PROTENSET1_PROTREG62_Msk (0x1UL << MPU_PROTENSET1_PROTREG62_Pos) /*!< Bit mask of PROTREG62 field. */
Kojto 91:031413cf7a89 3026 #define MPU_PROTENSET1_PROTREG62_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3027 #define MPU_PROTENSET1_PROTREG62_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3028 #define MPU_PROTENSET1_PROTREG62_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3029
Kojto 91:031413cf7a89 3030 /* Bit 29 : Protection enable for region 61. */
Kojto 91:031413cf7a89 3031 #define MPU_PROTENSET1_PROTREG61_Pos (29UL) /*!< Position of PROTREG61 field. */
Kojto 91:031413cf7a89 3032 #define MPU_PROTENSET1_PROTREG61_Msk (0x1UL << MPU_PROTENSET1_PROTREG61_Pos) /*!< Bit mask of PROTREG61 field. */
Kojto 91:031413cf7a89 3033 #define MPU_PROTENSET1_PROTREG61_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3034 #define MPU_PROTENSET1_PROTREG61_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3035 #define MPU_PROTENSET1_PROTREG61_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3036
Kojto 91:031413cf7a89 3037 /* Bit 28 : Protection enable for region 60. */
Kojto 91:031413cf7a89 3038 #define MPU_PROTENSET1_PROTREG60_Pos (28UL) /*!< Position of PROTREG60 field. */
Kojto 91:031413cf7a89 3039 #define MPU_PROTENSET1_PROTREG60_Msk (0x1UL << MPU_PROTENSET1_PROTREG60_Pos) /*!< Bit mask of PROTREG60 field. */
Kojto 91:031413cf7a89 3040 #define MPU_PROTENSET1_PROTREG60_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3041 #define MPU_PROTENSET1_PROTREG60_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3042 #define MPU_PROTENSET1_PROTREG60_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3043
Kojto 91:031413cf7a89 3044 /* Bit 27 : Protection enable for region 59. */
Kojto 91:031413cf7a89 3045 #define MPU_PROTENSET1_PROTREG59_Pos (27UL) /*!< Position of PROTREG59 field. */
Kojto 91:031413cf7a89 3046 #define MPU_PROTENSET1_PROTREG59_Msk (0x1UL << MPU_PROTENSET1_PROTREG59_Pos) /*!< Bit mask of PROTREG59 field. */
Kojto 91:031413cf7a89 3047 #define MPU_PROTENSET1_PROTREG59_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3048 #define MPU_PROTENSET1_PROTREG59_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3049 #define MPU_PROTENSET1_PROTREG59_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3050
Kojto 91:031413cf7a89 3051 /* Bit 26 : Protection enable for region 58. */
Kojto 91:031413cf7a89 3052 #define MPU_PROTENSET1_PROTREG58_Pos (26UL) /*!< Position of PROTREG58 field. */
Kojto 91:031413cf7a89 3053 #define MPU_PROTENSET1_PROTREG58_Msk (0x1UL << MPU_PROTENSET1_PROTREG58_Pos) /*!< Bit mask of PROTREG58 field. */
Kojto 91:031413cf7a89 3054 #define MPU_PROTENSET1_PROTREG58_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3055 #define MPU_PROTENSET1_PROTREG58_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3056 #define MPU_PROTENSET1_PROTREG58_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3057
Kojto 91:031413cf7a89 3058 /* Bit 25 : Protection enable for region 57. */
Kojto 91:031413cf7a89 3059 #define MPU_PROTENSET1_PROTREG57_Pos (25UL) /*!< Position of PROTREG57 field. */
Kojto 91:031413cf7a89 3060 #define MPU_PROTENSET1_PROTREG57_Msk (0x1UL << MPU_PROTENSET1_PROTREG57_Pos) /*!< Bit mask of PROTREG57 field. */
Kojto 91:031413cf7a89 3061 #define MPU_PROTENSET1_PROTREG57_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3062 #define MPU_PROTENSET1_PROTREG57_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3063 #define MPU_PROTENSET1_PROTREG57_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3064
Kojto 91:031413cf7a89 3065 /* Bit 24 : Protection enable for region 56. */
Kojto 91:031413cf7a89 3066 #define MPU_PROTENSET1_PROTREG56_Pos (24UL) /*!< Position of PROTREG56 field. */
Kojto 91:031413cf7a89 3067 #define MPU_PROTENSET1_PROTREG56_Msk (0x1UL << MPU_PROTENSET1_PROTREG56_Pos) /*!< Bit mask of PROTREG56 field. */
Kojto 91:031413cf7a89 3068 #define MPU_PROTENSET1_PROTREG56_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3069 #define MPU_PROTENSET1_PROTREG56_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3070 #define MPU_PROTENSET1_PROTREG56_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3071
Kojto 91:031413cf7a89 3072 /* Bit 23 : Protection enable for region 55. */
Kojto 91:031413cf7a89 3073 #define MPU_PROTENSET1_PROTREG55_Pos (23UL) /*!< Position of PROTREG55 field. */
Kojto 91:031413cf7a89 3074 #define MPU_PROTENSET1_PROTREG55_Msk (0x1UL << MPU_PROTENSET1_PROTREG55_Pos) /*!< Bit mask of PROTREG55 field. */
Kojto 91:031413cf7a89 3075 #define MPU_PROTENSET1_PROTREG55_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3076 #define MPU_PROTENSET1_PROTREG55_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3077 #define MPU_PROTENSET1_PROTREG55_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3078
Kojto 91:031413cf7a89 3079 /* Bit 22 : Protection enable for region 54. */
Kojto 91:031413cf7a89 3080 #define MPU_PROTENSET1_PROTREG54_Pos (22UL) /*!< Position of PROTREG54 field. */
Kojto 91:031413cf7a89 3081 #define MPU_PROTENSET1_PROTREG54_Msk (0x1UL << MPU_PROTENSET1_PROTREG54_Pos) /*!< Bit mask of PROTREG54 field. */
Kojto 91:031413cf7a89 3082 #define MPU_PROTENSET1_PROTREG54_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3083 #define MPU_PROTENSET1_PROTREG54_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3084 #define MPU_PROTENSET1_PROTREG54_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3085
Kojto 91:031413cf7a89 3086 /* Bit 21 : Protection enable for region 53. */
Kojto 91:031413cf7a89 3087 #define MPU_PROTENSET1_PROTREG53_Pos (21UL) /*!< Position of PROTREG53 field. */
Kojto 91:031413cf7a89 3088 #define MPU_PROTENSET1_PROTREG53_Msk (0x1UL << MPU_PROTENSET1_PROTREG53_Pos) /*!< Bit mask of PROTREG53 field. */
Kojto 91:031413cf7a89 3089 #define MPU_PROTENSET1_PROTREG53_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3090 #define MPU_PROTENSET1_PROTREG53_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3091 #define MPU_PROTENSET1_PROTREG53_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3092
Kojto 91:031413cf7a89 3093 /* Bit 20 : Protection enable for region 52. */
Kojto 91:031413cf7a89 3094 #define MPU_PROTENSET1_PROTREG52_Pos (20UL) /*!< Position of PROTREG52 field. */
Kojto 91:031413cf7a89 3095 #define MPU_PROTENSET1_PROTREG52_Msk (0x1UL << MPU_PROTENSET1_PROTREG52_Pos) /*!< Bit mask of PROTREG52 field. */
Kojto 91:031413cf7a89 3096 #define MPU_PROTENSET1_PROTREG52_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3097 #define MPU_PROTENSET1_PROTREG52_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3098 #define MPU_PROTENSET1_PROTREG52_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3099
Kojto 91:031413cf7a89 3100 /* Bit 19 : Protection enable for region 51. */
Kojto 91:031413cf7a89 3101 #define MPU_PROTENSET1_PROTREG51_Pos (19UL) /*!< Position of PROTREG51 field. */
Kojto 91:031413cf7a89 3102 #define MPU_PROTENSET1_PROTREG51_Msk (0x1UL << MPU_PROTENSET1_PROTREG51_Pos) /*!< Bit mask of PROTREG51 field. */
Kojto 91:031413cf7a89 3103 #define MPU_PROTENSET1_PROTREG51_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3104 #define MPU_PROTENSET1_PROTREG51_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3105 #define MPU_PROTENSET1_PROTREG51_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3106
Kojto 91:031413cf7a89 3107 /* Bit 18 : Protection enable for region 50. */
Kojto 91:031413cf7a89 3108 #define MPU_PROTENSET1_PROTREG50_Pos (18UL) /*!< Position of PROTREG50 field. */
Kojto 91:031413cf7a89 3109 #define MPU_PROTENSET1_PROTREG50_Msk (0x1UL << MPU_PROTENSET1_PROTREG50_Pos) /*!< Bit mask of PROTREG50 field. */
Kojto 91:031413cf7a89 3110 #define MPU_PROTENSET1_PROTREG50_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3111 #define MPU_PROTENSET1_PROTREG50_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3112 #define MPU_PROTENSET1_PROTREG50_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3113
Kojto 91:031413cf7a89 3114 /* Bit 17 : Protection enable for region 49. */
Kojto 91:031413cf7a89 3115 #define MPU_PROTENSET1_PROTREG49_Pos (17UL) /*!< Position of PROTREG49 field. */
Kojto 91:031413cf7a89 3116 #define MPU_PROTENSET1_PROTREG49_Msk (0x1UL << MPU_PROTENSET1_PROTREG49_Pos) /*!< Bit mask of PROTREG49 field. */
Kojto 91:031413cf7a89 3117 #define MPU_PROTENSET1_PROTREG49_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3118 #define MPU_PROTENSET1_PROTREG49_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3119 #define MPU_PROTENSET1_PROTREG49_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3120
Kojto 91:031413cf7a89 3121 /* Bit 16 : Protection enable for region 48. */
Kojto 91:031413cf7a89 3122 #define MPU_PROTENSET1_PROTREG48_Pos (16UL) /*!< Position of PROTREG48 field. */
Kojto 91:031413cf7a89 3123 #define MPU_PROTENSET1_PROTREG48_Msk (0x1UL << MPU_PROTENSET1_PROTREG48_Pos) /*!< Bit mask of PROTREG48 field. */
Kojto 91:031413cf7a89 3124 #define MPU_PROTENSET1_PROTREG48_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3125 #define MPU_PROTENSET1_PROTREG48_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3126 #define MPU_PROTENSET1_PROTREG48_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3127
Kojto 91:031413cf7a89 3128 /* Bit 15 : Protection enable for region 47. */
Kojto 91:031413cf7a89 3129 #define MPU_PROTENSET1_PROTREG47_Pos (15UL) /*!< Position of PROTREG47 field. */
Kojto 91:031413cf7a89 3130 #define MPU_PROTENSET1_PROTREG47_Msk (0x1UL << MPU_PROTENSET1_PROTREG47_Pos) /*!< Bit mask of PROTREG47 field. */
Kojto 91:031413cf7a89 3131 #define MPU_PROTENSET1_PROTREG47_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3132 #define MPU_PROTENSET1_PROTREG47_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3133 #define MPU_PROTENSET1_PROTREG47_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3134
Kojto 91:031413cf7a89 3135 /* Bit 14 : Protection enable for region 46. */
Kojto 91:031413cf7a89 3136 #define MPU_PROTENSET1_PROTREG46_Pos (14UL) /*!< Position of PROTREG46 field. */
Kojto 91:031413cf7a89 3137 #define MPU_PROTENSET1_PROTREG46_Msk (0x1UL << MPU_PROTENSET1_PROTREG46_Pos) /*!< Bit mask of PROTREG46 field. */
Kojto 91:031413cf7a89 3138 #define MPU_PROTENSET1_PROTREG46_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3139 #define MPU_PROTENSET1_PROTREG46_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3140 #define MPU_PROTENSET1_PROTREG46_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3141
Kojto 91:031413cf7a89 3142 /* Bit 13 : Protection enable for region 45. */
Kojto 91:031413cf7a89 3143 #define MPU_PROTENSET1_PROTREG45_Pos (13UL) /*!< Position of PROTREG45 field. */
Kojto 91:031413cf7a89 3144 #define MPU_PROTENSET1_PROTREG45_Msk (0x1UL << MPU_PROTENSET1_PROTREG45_Pos) /*!< Bit mask of PROTREG45 field. */
Kojto 91:031413cf7a89 3145 #define MPU_PROTENSET1_PROTREG45_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3146 #define MPU_PROTENSET1_PROTREG45_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3147 #define MPU_PROTENSET1_PROTREG45_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3148
Kojto 91:031413cf7a89 3149 /* Bit 12 : Protection enable for region 44. */
Kojto 91:031413cf7a89 3150 #define MPU_PROTENSET1_PROTREG44_Pos (12UL) /*!< Position of PROTREG44 field. */
Kojto 91:031413cf7a89 3151 #define MPU_PROTENSET1_PROTREG44_Msk (0x1UL << MPU_PROTENSET1_PROTREG44_Pos) /*!< Bit mask of PROTREG44 field. */
Kojto 91:031413cf7a89 3152 #define MPU_PROTENSET1_PROTREG44_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3153 #define MPU_PROTENSET1_PROTREG44_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3154 #define MPU_PROTENSET1_PROTREG44_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3155
Kojto 91:031413cf7a89 3156 /* Bit 11 : Protection enable for region 43. */
Kojto 91:031413cf7a89 3157 #define MPU_PROTENSET1_PROTREG43_Pos (11UL) /*!< Position of PROTREG43 field. */
Kojto 91:031413cf7a89 3158 #define MPU_PROTENSET1_PROTREG43_Msk (0x1UL << MPU_PROTENSET1_PROTREG43_Pos) /*!< Bit mask of PROTREG43 field. */
Kojto 91:031413cf7a89 3159 #define MPU_PROTENSET1_PROTREG43_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3160 #define MPU_PROTENSET1_PROTREG43_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3161 #define MPU_PROTENSET1_PROTREG43_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3162
Kojto 91:031413cf7a89 3163 /* Bit 10 : Protection enable for region 42. */
Kojto 91:031413cf7a89 3164 #define MPU_PROTENSET1_PROTREG42_Pos (10UL) /*!< Position of PROTREG42 field. */
Kojto 91:031413cf7a89 3165 #define MPU_PROTENSET1_PROTREG42_Msk (0x1UL << MPU_PROTENSET1_PROTREG42_Pos) /*!< Bit mask of PROTREG42 field. */
Kojto 91:031413cf7a89 3166 #define MPU_PROTENSET1_PROTREG42_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3167 #define MPU_PROTENSET1_PROTREG42_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3168 #define MPU_PROTENSET1_PROTREG42_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3169
Kojto 91:031413cf7a89 3170 /* Bit 9 : Protection enable for region 41. */
Kojto 91:031413cf7a89 3171 #define MPU_PROTENSET1_PROTREG41_Pos (9UL) /*!< Position of PROTREG41 field. */
Kojto 91:031413cf7a89 3172 #define MPU_PROTENSET1_PROTREG41_Msk (0x1UL << MPU_PROTENSET1_PROTREG41_Pos) /*!< Bit mask of PROTREG41 field. */
Kojto 91:031413cf7a89 3173 #define MPU_PROTENSET1_PROTREG41_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3174 #define MPU_PROTENSET1_PROTREG41_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3175 #define MPU_PROTENSET1_PROTREG41_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3176
Kojto 91:031413cf7a89 3177 /* Bit 8 : Protection enable for region 40. */
Kojto 91:031413cf7a89 3178 #define MPU_PROTENSET1_PROTREG40_Pos (8UL) /*!< Position of PROTREG40 field. */
Kojto 91:031413cf7a89 3179 #define MPU_PROTENSET1_PROTREG40_Msk (0x1UL << MPU_PROTENSET1_PROTREG40_Pos) /*!< Bit mask of PROTREG40 field. */
Kojto 91:031413cf7a89 3180 #define MPU_PROTENSET1_PROTREG40_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3181 #define MPU_PROTENSET1_PROTREG40_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3182 #define MPU_PROTENSET1_PROTREG40_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3183
Kojto 91:031413cf7a89 3184 /* Bit 7 : Protection enable for region 39. */
Kojto 91:031413cf7a89 3185 #define MPU_PROTENSET1_PROTREG39_Pos (7UL) /*!< Position of PROTREG39 field. */
Kojto 91:031413cf7a89 3186 #define MPU_PROTENSET1_PROTREG39_Msk (0x1UL << MPU_PROTENSET1_PROTREG39_Pos) /*!< Bit mask of PROTREG39 field. */
Kojto 91:031413cf7a89 3187 #define MPU_PROTENSET1_PROTREG39_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3188 #define MPU_PROTENSET1_PROTREG39_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3189 #define MPU_PROTENSET1_PROTREG39_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3190
Kojto 91:031413cf7a89 3191 /* Bit 6 : Protection enable for region 38. */
Kojto 91:031413cf7a89 3192 #define MPU_PROTENSET1_PROTREG38_Pos (6UL) /*!< Position of PROTREG38 field. */
Kojto 91:031413cf7a89 3193 #define MPU_PROTENSET1_PROTREG38_Msk (0x1UL << MPU_PROTENSET1_PROTREG38_Pos) /*!< Bit mask of PROTREG38 field. */
Kojto 91:031413cf7a89 3194 #define MPU_PROTENSET1_PROTREG38_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3195 #define MPU_PROTENSET1_PROTREG38_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3196 #define MPU_PROTENSET1_PROTREG38_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3197
Kojto 91:031413cf7a89 3198 /* Bit 5 : Protection enable for region 37. */
Kojto 91:031413cf7a89 3199 #define MPU_PROTENSET1_PROTREG37_Pos (5UL) /*!< Position of PROTREG37 field. */
Kojto 91:031413cf7a89 3200 #define MPU_PROTENSET1_PROTREG37_Msk (0x1UL << MPU_PROTENSET1_PROTREG37_Pos) /*!< Bit mask of PROTREG37 field. */
Kojto 91:031413cf7a89 3201 #define MPU_PROTENSET1_PROTREG37_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3202 #define MPU_PROTENSET1_PROTREG37_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3203 #define MPU_PROTENSET1_PROTREG37_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3204
Kojto 91:031413cf7a89 3205 /* Bit 4 : Protection enable for region 36. */
Kojto 91:031413cf7a89 3206 #define MPU_PROTENSET1_PROTREG36_Pos (4UL) /*!< Position of PROTREG36 field. */
Kojto 91:031413cf7a89 3207 #define MPU_PROTENSET1_PROTREG36_Msk (0x1UL << MPU_PROTENSET1_PROTREG36_Pos) /*!< Bit mask of PROTREG36 field. */
Kojto 91:031413cf7a89 3208 #define MPU_PROTENSET1_PROTREG36_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3209 #define MPU_PROTENSET1_PROTREG36_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3210 #define MPU_PROTENSET1_PROTREG36_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3211
Kojto 91:031413cf7a89 3212 /* Bit 3 : Protection enable for region 35. */
Kojto 91:031413cf7a89 3213 #define MPU_PROTENSET1_PROTREG35_Pos (3UL) /*!< Position of PROTREG35 field. */
Kojto 91:031413cf7a89 3214 #define MPU_PROTENSET1_PROTREG35_Msk (0x1UL << MPU_PROTENSET1_PROTREG35_Pos) /*!< Bit mask of PROTREG35 field. */
Kojto 91:031413cf7a89 3215 #define MPU_PROTENSET1_PROTREG35_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3216 #define MPU_PROTENSET1_PROTREG35_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3217 #define MPU_PROTENSET1_PROTREG35_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3218
Kojto 91:031413cf7a89 3219 /* Bit 2 : Protection enable for region 34. */
Kojto 91:031413cf7a89 3220 #define MPU_PROTENSET1_PROTREG34_Pos (2UL) /*!< Position of PROTREG34 field. */
Kojto 91:031413cf7a89 3221 #define MPU_PROTENSET1_PROTREG34_Msk (0x1UL << MPU_PROTENSET1_PROTREG34_Pos) /*!< Bit mask of PROTREG34 field. */
Kojto 91:031413cf7a89 3222 #define MPU_PROTENSET1_PROTREG34_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3223 #define MPU_PROTENSET1_PROTREG34_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3224 #define MPU_PROTENSET1_PROTREG34_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3225
Kojto 91:031413cf7a89 3226 /* Bit 1 : Protection enable for region 33. */
Kojto 91:031413cf7a89 3227 #define MPU_PROTENSET1_PROTREG33_Pos (1UL) /*!< Position of PROTREG33 field. */
Kojto 91:031413cf7a89 3228 #define MPU_PROTENSET1_PROTREG33_Msk (0x1UL << MPU_PROTENSET1_PROTREG33_Pos) /*!< Bit mask of PROTREG33 field. */
Kojto 91:031413cf7a89 3229 #define MPU_PROTENSET1_PROTREG33_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3230 #define MPU_PROTENSET1_PROTREG33_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3231 #define MPU_PROTENSET1_PROTREG33_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3232
Kojto 91:031413cf7a89 3233 /* Bit 0 : Protection enable for region 32. */
Kojto 91:031413cf7a89 3234 #define MPU_PROTENSET1_PROTREG32_Pos (0UL) /*!< Position of PROTREG32 field. */
Kojto 91:031413cf7a89 3235 #define MPU_PROTENSET1_PROTREG32_Msk (0x1UL << MPU_PROTENSET1_PROTREG32_Pos) /*!< Bit mask of PROTREG32 field. */
Kojto 91:031413cf7a89 3236 #define MPU_PROTENSET1_PROTREG32_Disabled (0UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3237 #define MPU_PROTENSET1_PROTREG32_Enabled (1UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3238 #define MPU_PROTENSET1_PROTREG32_Set (1UL) /*!< Enable protection on write. */
Kojto 91:031413cf7a89 3239
Kojto 91:031413cf7a89 3240 /* Register: MPU_DISABLEINDEBUG */
Kojto 91:031413cf7a89 3241 /* Description: Disable protection mechanism in debug mode. */
Kojto 91:031413cf7a89 3242
Kojto 91:031413cf7a89 3243 /* Bit 0 : Disable protection mechanism in debug mode. */
Kojto 91:031413cf7a89 3244 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos (0UL) /*!< Position of DISABLEINDEBUG field. */
Kojto 91:031413cf7a89 3245 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Msk (0x1UL << MPU_DISABLEINDEBUG_DISABLEINDEBUG_Pos) /*!< Bit mask of DISABLEINDEBUG field. */
Kojto 91:031413cf7a89 3246 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Enabled (0UL) /*!< Protection enabled. */
Kojto 91:031413cf7a89 3247 #define MPU_DISABLEINDEBUG_DISABLEINDEBUG_Disabled (1UL) /*!< Protection disabled. */
Kojto 91:031413cf7a89 3248
Kojto 91:031413cf7a89 3249
Kojto 91:031413cf7a89 3250 /* Peripheral: NVMC */
Kojto 91:031413cf7a89 3251 /* Description: Non Volatile Memory Controller. */
Kojto 91:031413cf7a89 3252
Kojto 91:031413cf7a89 3253 /* Register: NVMC_READY */
Kojto 91:031413cf7a89 3254 /* Description: Ready flag. */
Kojto 91:031413cf7a89 3255
Kojto 91:031413cf7a89 3256 /* Bit 0 : NVMC ready. */
Kojto 91:031413cf7a89 3257 #define NVMC_READY_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 91:031413cf7a89 3258 #define NVMC_READY_READY_Msk (0x1UL << NVMC_READY_READY_Pos) /*!< Bit mask of READY field. */
Kojto 91:031413cf7a89 3259 #define NVMC_READY_READY_Busy (0UL) /*!< NVMC is busy (on-going write or erase operation). */
Kojto 91:031413cf7a89 3260 #define NVMC_READY_READY_Ready (1UL) /*!< NVMC is ready. */
Kojto 91:031413cf7a89 3261
Kojto 91:031413cf7a89 3262 /* Register: NVMC_CONFIG */
Kojto 91:031413cf7a89 3263 /* Description: Configuration register. */
Kojto 91:031413cf7a89 3264
Kojto 91:031413cf7a89 3265 /* Bits 1..0 : Program write enable. */
Kojto 91:031413cf7a89 3266 #define NVMC_CONFIG_WEN_Pos (0UL) /*!< Position of WEN field. */
Kojto 91:031413cf7a89 3267 #define NVMC_CONFIG_WEN_Msk (0x3UL << NVMC_CONFIG_WEN_Pos) /*!< Bit mask of WEN field. */
Kojto 91:031413cf7a89 3268 #define NVMC_CONFIG_WEN_Ren (0x00UL) /*!< Read only access. */
Kojto 91:031413cf7a89 3269 #define NVMC_CONFIG_WEN_Wen (0x01UL) /*!< Write enabled. */
Kojto 91:031413cf7a89 3270 #define NVMC_CONFIG_WEN_Een (0x02UL) /*!< Erase enabled. */
Kojto 91:031413cf7a89 3271
Kojto 91:031413cf7a89 3272 /* Register: NVMC_ERASEALL */
Kojto 91:031413cf7a89 3273 /* Description: Register for erasing all non-volatile user memory. */
Kojto 91:031413cf7a89 3274
Kojto 91:031413cf7a89 3275 /* Bit 0 : Starts the erasing of all user NVM (code region 0/1 and UICR registers). */
Kojto 91:031413cf7a89 3276 #define NVMC_ERASEALL_ERASEALL_Pos (0UL) /*!< Position of ERASEALL field. */
Kojto 91:031413cf7a89 3277 #define NVMC_ERASEALL_ERASEALL_Msk (0x1UL << NVMC_ERASEALL_ERASEALL_Pos) /*!< Bit mask of ERASEALL field. */
Kojto 91:031413cf7a89 3278 #define NVMC_ERASEALL_ERASEALL_NoOperation (0UL) /*!< No operation. */
Kojto 91:031413cf7a89 3279 #define NVMC_ERASEALL_ERASEALL_Erase (1UL) /*!< Start chip erase. */
Kojto 91:031413cf7a89 3280
Kojto 91:031413cf7a89 3281 /* Register: NVMC_ERASEUICR */
Kojto 91:031413cf7a89 3282 /* Description: Register for start erasing User Information Congfiguration Registers. */
Kojto 91:031413cf7a89 3283
Kojto 91:031413cf7a89 3284 /* Bit 0 : It can only be used when all contents of code region 1 are erased. */
Kojto 91:031413cf7a89 3285 #define NVMC_ERASEUICR_ERASEUICR_Pos (0UL) /*!< Position of ERASEUICR field. */
Kojto 91:031413cf7a89 3286 #define NVMC_ERASEUICR_ERASEUICR_Msk (0x1UL << NVMC_ERASEUICR_ERASEUICR_Pos) /*!< Bit mask of ERASEUICR field. */
Kojto 91:031413cf7a89 3287 #define NVMC_ERASEUICR_ERASEUICR_NoOperation (0UL) /*!< No operation. */
Kojto 91:031413cf7a89 3288 #define NVMC_ERASEUICR_ERASEUICR_Erase (1UL) /*!< Start UICR erase. */
Kojto 91:031413cf7a89 3289
Kojto 91:031413cf7a89 3290
Kojto 91:031413cf7a89 3291 /* Peripheral: POWER */
Kojto 91:031413cf7a89 3292 /* Description: Power Control. */
Kojto 91:031413cf7a89 3293
Kojto 91:031413cf7a89 3294 /* Register: POWER_INTENSET */
Kojto 91:031413cf7a89 3295 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 3296
Kojto 91:031413cf7a89 3297 /* Bit 2 : Enable interrupt on POFWARN event. */
Kojto 91:031413cf7a89 3298 #define POWER_INTENSET_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
Kojto 91:031413cf7a89 3299 #define POWER_INTENSET_POFWARN_Msk (0x1UL << POWER_INTENSET_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
Kojto 91:031413cf7a89 3300 #define POWER_INTENSET_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 3301 #define POWER_INTENSET_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 3302 #define POWER_INTENSET_POFWARN_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 3303
Kojto 91:031413cf7a89 3304 /* Register: POWER_INTENCLR */
Kojto 91:031413cf7a89 3305 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 3306
Kojto 91:031413cf7a89 3307 /* Bit 2 : Disable interrupt on POFWARN event. */
Kojto 91:031413cf7a89 3308 #define POWER_INTENCLR_POFWARN_Pos (2UL) /*!< Position of POFWARN field. */
Kojto 91:031413cf7a89 3309 #define POWER_INTENCLR_POFWARN_Msk (0x1UL << POWER_INTENCLR_POFWARN_Pos) /*!< Bit mask of POFWARN field. */
Kojto 91:031413cf7a89 3310 #define POWER_INTENCLR_POFWARN_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 3311 #define POWER_INTENCLR_POFWARN_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 3312 #define POWER_INTENCLR_POFWARN_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 3313
Kojto 91:031413cf7a89 3314 /* Register: POWER_RESETREAS */
Kojto 91:031413cf7a89 3315 /* Description: Reset reason. */
Kojto 91:031413cf7a89 3316
Kojto 91:031413cf7a89 3317 /* Bit 18 : Reset from wake-up from OFF mode detected by entering into debug interface mode. */
Kojto 91:031413cf7a89 3318 #define POWER_RESETREAS_DIF_Pos (18UL) /*!< Position of DIF field. */
Kojto 91:031413cf7a89 3319 #define POWER_RESETREAS_DIF_Msk (0x1UL << POWER_RESETREAS_DIF_Pos) /*!< Bit mask of DIF field. */
Kojto 91:031413cf7a89 3320
Kojto 91:031413cf7a89 3321 /* Bit 17 : Reset from wake-up from OFF mode detected by the use of ANADETECT signal from LPCOMP. */
Kojto 91:031413cf7a89 3322 #define POWER_RESETREAS_LPCOMP_Pos (17UL) /*!< Position of LPCOMP field. */
Kojto 91:031413cf7a89 3323 #define POWER_RESETREAS_LPCOMP_Msk (0x1UL << POWER_RESETREAS_LPCOMP_Pos) /*!< Bit mask of LPCOMP field. */
Kojto 91:031413cf7a89 3324
Kojto 91:031413cf7a89 3325 /* Bit 16 : Reset from wake-up from OFF mode detected by the use of DETECT signal from GPIO. */
Kojto 91:031413cf7a89 3326 #define POWER_RESETREAS_OFF_Pos (16UL) /*!< Position of OFF field. */
Kojto 91:031413cf7a89 3327 #define POWER_RESETREAS_OFF_Msk (0x1UL << POWER_RESETREAS_OFF_Pos) /*!< Bit mask of OFF field. */
Kojto 91:031413cf7a89 3328
Kojto 91:031413cf7a89 3329 /* Bit 3 : Reset from CPU lock-up detected. */
Kojto 91:031413cf7a89 3330 #define POWER_RESETREAS_LOCKUP_Pos (3UL) /*!< Position of LOCKUP field. */
Kojto 91:031413cf7a89 3331 #define POWER_RESETREAS_LOCKUP_Msk (0x1UL << POWER_RESETREAS_LOCKUP_Pos) /*!< Bit mask of LOCKUP field. */
Kojto 91:031413cf7a89 3332
Kojto 91:031413cf7a89 3333 /* Bit 2 : Reset from AIRCR.SYSRESETREQ detected. */
Kojto 91:031413cf7a89 3334 #define POWER_RESETREAS_SREQ_Pos (2UL) /*!< Position of SREQ field. */
Kojto 91:031413cf7a89 3335 #define POWER_RESETREAS_SREQ_Msk (0x1UL << POWER_RESETREAS_SREQ_Pos) /*!< Bit mask of SREQ field. */
Kojto 91:031413cf7a89 3336
Kojto 91:031413cf7a89 3337 /* Bit 1 : Reset from watchdog detected. */
Kojto 91:031413cf7a89 3338 #define POWER_RESETREAS_DOG_Pos (1UL) /*!< Position of DOG field. */
Kojto 91:031413cf7a89 3339 #define POWER_RESETREAS_DOG_Msk (0x1UL << POWER_RESETREAS_DOG_Pos) /*!< Bit mask of DOG field. */
Kojto 91:031413cf7a89 3340
Kojto 91:031413cf7a89 3341 /* Bit 0 : Reset from pin-reset detected. */
Kojto 91:031413cf7a89 3342 #define POWER_RESETREAS_RESETPIN_Pos (0UL) /*!< Position of RESETPIN field. */
Kojto 91:031413cf7a89 3343 #define POWER_RESETREAS_RESETPIN_Msk (0x1UL << POWER_RESETREAS_RESETPIN_Pos) /*!< Bit mask of RESETPIN field. */
Kojto 91:031413cf7a89 3344
Kojto 91:031413cf7a89 3345 /* Register: POWER_SYSTEMOFF */
Kojto 91:031413cf7a89 3346 /* Description: System off register. */
Kojto 91:031413cf7a89 3347
Kojto 91:031413cf7a89 3348 /* Bit 0 : Enter system off mode. */
Kojto 91:031413cf7a89 3349 #define POWER_SYSTEMOFF_SYSTEMOFF_Pos (0UL) /*!< Position of SYSTEMOFF field. */
Kojto 91:031413cf7a89 3350 #define POWER_SYSTEMOFF_SYSTEMOFF_Msk (0x1UL << POWER_SYSTEMOFF_SYSTEMOFF_Pos) /*!< Bit mask of SYSTEMOFF field. */
Kojto 91:031413cf7a89 3351 #define POWER_SYSTEMOFF_SYSTEMOFF_Enter (1UL) /*!< Enter system off mode. */
Kojto 91:031413cf7a89 3352
Kojto 91:031413cf7a89 3353 /* Register: POWER_POFCON */
Kojto 91:031413cf7a89 3354 /* Description: Power failure configuration. */
Kojto 91:031413cf7a89 3355
Kojto 91:031413cf7a89 3356 /* Bits 2..1 : Set threshold level. */
Kojto 91:031413cf7a89 3357 #define POWER_POFCON_THRESHOLD_Pos (1UL) /*!< Position of THRESHOLD field. */
Kojto 91:031413cf7a89 3358 #define POWER_POFCON_THRESHOLD_Msk (0x3UL << POWER_POFCON_THRESHOLD_Pos) /*!< Bit mask of THRESHOLD field. */
Kojto 91:031413cf7a89 3359 #define POWER_POFCON_THRESHOLD_V21 (0x00UL) /*!< Set threshold to 2.1Volts. */
Kojto 91:031413cf7a89 3360 #define POWER_POFCON_THRESHOLD_V23 (0x01UL) /*!< Set threshold to 2.3Volts. */
Kojto 91:031413cf7a89 3361 #define POWER_POFCON_THRESHOLD_V25 (0x02UL) /*!< Set threshold to 2.5Volts. */
Kojto 91:031413cf7a89 3362 #define POWER_POFCON_THRESHOLD_V27 (0x03UL) /*!< Set threshold to 2.7Volts. */
Kojto 91:031413cf7a89 3363
Kojto 91:031413cf7a89 3364 /* Bit 0 : Power failure comparator enable. */
Kojto 91:031413cf7a89 3365 #define POWER_POFCON_POF_Pos (0UL) /*!< Position of POF field. */
Kojto 91:031413cf7a89 3366 #define POWER_POFCON_POF_Msk (0x1UL << POWER_POFCON_POF_Pos) /*!< Bit mask of POF field. */
Kojto 91:031413cf7a89 3367 #define POWER_POFCON_POF_Disabled (0UL) /*!< Disabled. */
Kojto 91:031413cf7a89 3368 #define POWER_POFCON_POF_Enabled (1UL) /*!< Enabled. */
Kojto 91:031413cf7a89 3369
Kojto 91:031413cf7a89 3370 /* Register: POWER_GPREGRET */
Kojto 91:031413cf7a89 3371 /* Description: General purpose retention register. This register is a retained register. */
Kojto 91:031413cf7a89 3372
Kojto 91:031413cf7a89 3373 /* Bits 7..0 : General purpose retention register. */
Kojto 91:031413cf7a89 3374 #define POWER_GPREGRET_GPREGRET_Pos (0UL) /*!< Position of GPREGRET field. */
Kojto 91:031413cf7a89 3375 #define POWER_GPREGRET_GPREGRET_Msk (0xFFUL << POWER_GPREGRET_GPREGRET_Pos) /*!< Bit mask of GPREGRET field. */
Kojto 91:031413cf7a89 3376
Kojto 91:031413cf7a89 3377 /* Register: POWER_RAMON */
Kojto 91:031413cf7a89 3378 /* Description: Ram on/off. */
Kojto 91:031413cf7a89 3379
Kojto 91:031413cf7a89 3380 /* Bit 19 : RAM block 3 behaviour in OFF mode. */
Kojto 91:031413cf7a89 3381 #define POWER_RAMON_OFFRAM3_Pos (19UL) /*!< Position of OFFRAM3 field. */
Kojto 91:031413cf7a89 3382 #define POWER_RAMON_OFFRAM3_Msk (0x1UL << POWER_RAMON_OFFRAM3_Pos) /*!< Bit mask of OFFRAM3 field. */
Kojto 91:031413cf7a89 3383 #define POWER_RAMON_OFFRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in OFF mode. */
Kojto 91:031413cf7a89 3384 #define POWER_RAMON_OFFRAM3_RAM3On (1UL) /*!< RAM block 3 ON in OFF mode. */
Kojto 91:031413cf7a89 3385
Kojto 91:031413cf7a89 3386 /* Bit 18 : RAM block 2 behaviour in OFF mode. */
Kojto 91:031413cf7a89 3387 #define POWER_RAMON_OFFRAM2_Pos (18UL) /*!< Position of OFFRAM2 field. */
Kojto 91:031413cf7a89 3388 #define POWER_RAMON_OFFRAM2_Msk (0x1UL << POWER_RAMON_OFFRAM2_Pos) /*!< Bit mask of OFFRAM2 field. */
Kojto 91:031413cf7a89 3389 #define POWER_RAMON_OFFRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in OFF mode. */
Kojto 91:031413cf7a89 3390 #define POWER_RAMON_OFFRAM2_RAM2On (1UL) /*!< RAM block 2 ON in OFF mode. */
Kojto 91:031413cf7a89 3391
Kojto 91:031413cf7a89 3392 /* Bit 17 : RAM block 1 behaviour in OFF mode. */
Kojto 91:031413cf7a89 3393 #define POWER_RAMON_OFFRAM1_Pos (17UL) /*!< Position of OFFRAM1 field. */
Kojto 91:031413cf7a89 3394 #define POWER_RAMON_OFFRAM1_Msk (0x1UL << POWER_RAMON_OFFRAM1_Pos) /*!< Bit mask of OFFRAM1 field. */
Kojto 91:031413cf7a89 3395 #define POWER_RAMON_OFFRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in OFF mode. */
Kojto 91:031413cf7a89 3396 #define POWER_RAMON_OFFRAM1_RAM1On (1UL) /*!< RAM block 1 ON in OFF mode. */
Kojto 91:031413cf7a89 3397
Kojto 91:031413cf7a89 3398 /* Bit 16 : RAM block 0 behaviour in OFF mode. */
Kojto 91:031413cf7a89 3399 #define POWER_RAMON_OFFRAM0_Pos (16UL) /*!< Position of OFFRAM0 field. */
Kojto 91:031413cf7a89 3400 #define POWER_RAMON_OFFRAM0_Msk (0x1UL << POWER_RAMON_OFFRAM0_Pos) /*!< Bit mask of OFFRAM0 field. */
Kojto 91:031413cf7a89 3401 #define POWER_RAMON_OFFRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in OFF mode. */
Kojto 91:031413cf7a89 3402 #define POWER_RAMON_OFFRAM0_RAM0On (1UL) /*!< RAM block 0 ON in OFF mode. */
Kojto 91:031413cf7a89 3403
Kojto 91:031413cf7a89 3404 /* Bit 3 : RAM block 3 behaviour in ON mode. */
Kojto 91:031413cf7a89 3405 #define POWER_RAMON_ONRAM3_Pos (3UL) /*!< Position of ONRAM3 field. */
Kojto 91:031413cf7a89 3406 #define POWER_RAMON_ONRAM3_Msk (0x1UL << POWER_RAMON_ONRAM3_Pos) /*!< Bit mask of ONRAM3 field. */
Kojto 91:031413cf7a89 3407 #define POWER_RAMON_ONRAM3_RAM3Off (0UL) /*!< RAM block 3 OFF in ON mode. */
Kojto 91:031413cf7a89 3408 #define POWER_RAMON_ONRAM3_RAM3On (1UL) /*!< RAM block 3 ON in ON mode. */
Kojto 91:031413cf7a89 3409
Kojto 91:031413cf7a89 3410 /* Bit 2 : RAM block 2 behaviour in ON mode. */
Kojto 91:031413cf7a89 3411 #define POWER_RAMON_ONRAM2_Pos (2UL) /*!< Position of ONRAM2 field. */
Kojto 91:031413cf7a89 3412 #define POWER_RAMON_ONRAM2_Msk (0x1UL << POWER_RAMON_ONRAM2_Pos) /*!< Bit mask of ONRAM2 field. */
Kojto 91:031413cf7a89 3413 #define POWER_RAMON_ONRAM2_RAM2Off (0UL) /*!< RAM block 2 OFF in ON mode. */
Kojto 91:031413cf7a89 3414 #define POWER_RAMON_ONRAM2_RAM2On (1UL) /*!< RAM block 2 ON in ON mode. */
Kojto 91:031413cf7a89 3415
Kojto 91:031413cf7a89 3416 /* Bit 1 : RAM block 1 behaviour in ON mode. */
Kojto 91:031413cf7a89 3417 #define POWER_RAMON_ONRAM1_Pos (1UL) /*!< Position of ONRAM1 field. */
Kojto 91:031413cf7a89 3418 #define POWER_RAMON_ONRAM1_Msk (0x1UL << POWER_RAMON_ONRAM1_Pos) /*!< Bit mask of ONRAM1 field. */
Kojto 91:031413cf7a89 3419 #define POWER_RAMON_ONRAM1_RAM1Off (0UL) /*!< RAM block 1 OFF in ON mode. */
Kojto 91:031413cf7a89 3420 #define POWER_RAMON_ONRAM1_RAM1On (1UL) /*!< RAM block 1 ON in ON mode. */
Kojto 91:031413cf7a89 3421
Kojto 91:031413cf7a89 3422 /* Bit 0 : RAM block 0 behaviour in ON mode. */
Kojto 91:031413cf7a89 3423 #define POWER_RAMON_ONRAM0_Pos (0UL) /*!< Position of ONRAM0 field. */
Kojto 91:031413cf7a89 3424 #define POWER_RAMON_ONRAM0_Msk (0x1UL << POWER_RAMON_ONRAM0_Pos) /*!< Bit mask of ONRAM0 field. */
Kojto 91:031413cf7a89 3425 #define POWER_RAMON_ONRAM0_RAM0Off (0UL) /*!< RAM block 0 OFF in ON mode. */
Kojto 91:031413cf7a89 3426 #define POWER_RAMON_ONRAM0_RAM0On (1UL) /*!< RAM block 0 ON in ON mode. */
Kojto 91:031413cf7a89 3427
Kojto 91:031413cf7a89 3428 /* Register: POWER_RESET */
Kojto 91:031413cf7a89 3429 /* Description: Pin reset functionality configuration register. This register is a retained register. */
Kojto 91:031413cf7a89 3430
Kojto 91:031413cf7a89 3431 /* Bit 0 : Enable pin reset in debug interface mode. */
Kojto 91:031413cf7a89 3432 #define POWER_RESET_RESET_Pos (0UL) /*!< Position of RESET field. */
Kojto 91:031413cf7a89 3433 #define POWER_RESET_RESET_Msk (0x1UL << POWER_RESET_RESET_Pos) /*!< Bit mask of RESET field. */
Kojto 91:031413cf7a89 3434 #define POWER_RESET_RESET_Disabled (0UL) /*!< Pin reset in debug interface mode disabled. */
Kojto 91:031413cf7a89 3435 #define POWER_RESET_RESET_Enabled (1UL) /*!< Pin reset in debug interface mode enabled. */
Kojto 91:031413cf7a89 3436
Kojto 91:031413cf7a89 3437 /* Register: POWER_DCDCEN */
Kojto 91:031413cf7a89 3438 /* Description: DCDC converter enable configuration register. */
Kojto 91:031413cf7a89 3439
Kojto 91:031413cf7a89 3440 /* Bit 0 : Enable DCDC converter. */
Kojto 91:031413cf7a89 3441 #define POWER_DCDCEN_DCDCEN_Pos (0UL) /*!< Position of DCDCEN field. */
Kojto 91:031413cf7a89 3442 #define POWER_DCDCEN_DCDCEN_Msk (0x1UL << POWER_DCDCEN_DCDCEN_Pos) /*!< Bit mask of DCDCEN field. */
Kojto 91:031413cf7a89 3443 #define POWER_DCDCEN_DCDCEN_Disabled (0UL) /*!< DCDC converter disabled. */
Kojto 91:031413cf7a89 3444 #define POWER_DCDCEN_DCDCEN_Enabled (1UL) /*!< DCDC converter enabled. */
Kojto 91:031413cf7a89 3445
Kojto 91:031413cf7a89 3446
Kojto 91:031413cf7a89 3447 /* Peripheral: PPI */
Kojto 91:031413cf7a89 3448 /* Description: PPI controller. */
Kojto 91:031413cf7a89 3449
Kojto 91:031413cf7a89 3450 /* Register: PPI_CHEN */
Kojto 91:031413cf7a89 3451 /* Description: Channel enable. */
Kojto 91:031413cf7a89 3452
Kojto 91:031413cf7a89 3453 /* Bit 31 : Enable PPI channel 31. */
Kojto 91:031413cf7a89 3454 #define PPI_CHEN_CH31_Pos (31UL) /*!< Position of CH31 field. */
Kojto 91:031413cf7a89 3455 #define PPI_CHEN_CH31_Msk (0x1UL << PPI_CHEN_CH31_Pos) /*!< Bit mask of CH31 field. */
Kojto 91:031413cf7a89 3456 #define PPI_CHEN_CH31_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3457 #define PPI_CHEN_CH31_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3458
Kojto 91:031413cf7a89 3459 /* Bit 30 : Enable PPI channel 30. */
Kojto 91:031413cf7a89 3460 #define PPI_CHEN_CH30_Pos (30UL) /*!< Position of CH30 field. */
Kojto 91:031413cf7a89 3461 #define PPI_CHEN_CH30_Msk (0x1UL << PPI_CHEN_CH30_Pos) /*!< Bit mask of CH30 field. */
Kojto 91:031413cf7a89 3462 #define PPI_CHEN_CH30_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3463 #define PPI_CHEN_CH30_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3464
Kojto 91:031413cf7a89 3465 /* Bit 29 : Enable PPI channel 29. */
Kojto 91:031413cf7a89 3466 #define PPI_CHEN_CH29_Pos (29UL) /*!< Position of CH29 field. */
Kojto 91:031413cf7a89 3467 #define PPI_CHEN_CH29_Msk (0x1UL << PPI_CHEN_CH29_Pos) /*!< Bit mask of CH29 field. */
Kojto 91:031413cf7a89 3468 #define PPI_CHEN_CH29_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3469 #define PPI_CHEN_CH29_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3470
Kojto 91:031413cf7a89 3471 /* Bit 28 : Enable PPI channel 28. */
Kojto 91:031413cf7a89 3472 #define PPI_CHEN_CH28_Pos (28UL) /*!< Position of CH28 field. */
Kojto 91:031413cf7a89 3473 #define PPI_CHEN_CH28_Msk (0x1UL << PPI_CHEN_CH28_Pos) /*!< Bit mask of CH28 field. */
Kojto 91:031413cf7a89 3474 #define PPI_CHEN_CH28_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3475 #define PPI_CHEN_CH28_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3476
Kojto 91:031413cf7a89 3477 /* Bit 27 : Enable PPI channel 27. */
Kojto 91:031413cf7a89 3478 #define PPI_CHEN_CH27_Pos (27UL) /*!< Position of CH27 field. */
Kojto 91:031413cf7a89 3479 #define PPI_CHEN_CH27_Msk (0x1UL << PPI_CHEN_CH27_Pos) /*!< Bit mask of CH27 field. */
Kojto 91:031413cf7a89 3480 #define PPI_CHEN_CH27_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3481 #define PPI_CHEN_CH27_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3482
Kojto 91:031413cf7a89 3483 /* Bit 26 : Enable PPI channel 26. */
Kojto 91:031413cf7a89 3484 #define PPI_CHEN_CH26_Pos (26UL) /*!< Position of CH26 field. */
Kojto 91:031413cf7a89 3485 #define PPI_CHEN_CH26_Msk (0x1UL << PPI_CHEN_CH26_Pos) /*!< Bit mask of CH26 field. */
Kojto 91:031413cf7a89 3486 #define PPI_CHEN_CH26_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3487 #define PPI_CHEN_CH26_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3488
Kojto 91:031413cf7a89 3489 /* Bit 25 : Enable PPI channel 25. */
Kojto 91:031413cf7a89 3490 #define PPI_CHEN_CH25_Pos (25UL) /*!< Position of CH25 field. */
Kojto 91:031413cf7a89 3491 #define PPI_CHEN_CH25_Msk (0x1UL << PPI_CHEN_CH25_Pos) /*!< Bit mask of CH25 field. */
Kojto 91:031413cf7a89 3492 #define PPI_CHEN_CH25_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3493 #define PPI_CHEN_CH25_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3494
Kojto 91:031413cf7a89 3495 /* Bit 24 : Enable PPI channel 24. */
Kojto 91:031413cf7a89 3496 #define PPI_CHEN_CH24_Pos (24UL) /*!< Position of CH24 field. */
Kojto 91:031413cf7a89 3497 #define PPI_CHEN_CH24_Msk (0x1UL << PPI_CHEN_CH24_Pos) /*!< Bit mask of CH24 field. */
Kojto 91:031413cf7a89 3498 #define PPI_CHEN_CH24_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3499 #define PPI_CHEN_CH24_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3500
Kojto 91:031413cf7a89 3501 /* Bit 23 : Enable PPI channel 23. */
Kojto 91:031413cf7a89 3502 #define PPI_CHEN_CH23_Pos (23UL) /*!< Position of CH23 field. */
Kojto 91:031413cf7a89 3503 #define PPI_CHEN_CH23_Msk (0x1UL << PPI_CHEN_CH23_Pos) /*!< Bit mask of CH23 field. */
Kojto 91:031413cf7a89 3504 #define PPI_CHEN_CH23_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3505 #define PPI_CHEN_CH23_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3506
Kojto 91:031413cf7a89 3507 /* Bit 22 : Enable PPI channel 22. */
Kojto 91:031413cf7a89 3508 #define PPI_CHEN_CH22_Pos (22UL) /*!< Position of CH22 field. */
Kojto 91:031413cf7a89 3509 #define PPI_CHEN_CH22_Msk (0x1UL << PPI_CHEN_CH22_Pos) /*!< Bit mask of CH22 field. */
Kojto 91:031413cf7a89 3510 #define PPI_CHEN_CH22_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3511 #define PPI_CHEN_CH22_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3512
Kojto 91:031413cf7a89 3513 /* Bit 21 : Enable PPI channel 21. */
Kojto 91:031413cf7a89 3514 #define PPI_CHEN_CH21_Pos (21UL) /*!< Position of CH21 field. */
Kojto 91:031413cf7a89 3515 #define PPI_CHEN_CH21_Msk (0x1UL << PPI_CHEN_CH21_Pos) /*!< Bit mask of CH21 field. */
Kojto 91:031413cf7a89 3516 #define PPI_CHEN_CH21_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3517 #define PPI_CHEN_CH21_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3518
Kojto 91:031413cf7a89 3519 /* Bit 20 : Enable PPI channel 20. */
Kojto 91:031413cf7a89 3520 #define PPI_CHEN_CH20_Pos (20UL) /*!< Position of CH20 field. */
Kojto 91:031413cf7a89 3521 #define PPI_CHEN_CH20_Msk (0x1UL << PPI_CHEN_CH20_Pos) /*!< Bit mask of CH20 field. */
Kojto 91:031413cf7a89 3522 #define PPI_CHEN_CH20_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3523 #define PPI_CHEN_CH20_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3524
Kojto 91:031413cf7a89 3525 /* Bit 15 : Enable PPI channel 15. */
Kojto 91:031413cf7a89 3526 #define PPI_CHEN_CH15_Pos (15UL) /*!< Position of CH15 field. */
Kojto 91:031413cf7a89 3527 #define PPI_CHEN_CH15_Msk (0x1UL << PPI_CHEN_CH15_Pos) /*!< Bit mask of CH15 field. */
Kojto 91:031413cf7a89 3528 #define PPI_CHEN_CH15_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3529 #define PPI_CHEN_CH15_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3530
Kojto 91:031413cf7a89 3531 /* Bit 14 : Enable PPI channel 14. */
Kojto 91:031413cf7a89 3532 #define PPI_CHEN_CH14_Pos (14UL) /*!< Position of CH14 field. */
Kojto 91:031413cf7a89 3533 #define PPI_CHEN_CH14_Msk (0x1UL << PPI_CHEN_CH14_Pos) /*!< Bit mask of CH14 field. */
Kojto 91:031413cf7a89 3534 #define PPI_CHEN_CH14_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3535 #define PPI_CHEN_CH14_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3536
Kojto 91:031413cf7a89 3537 /* Bit 13 : Enable PPI channel 13. */
Kojto 91:031413cf7a89 3538 #define PPI_CHEN_CH13_Pos (13UL) /*!< Position of CH13 field. */
Kojto 91:031413cf7a89 3539 #define PPI_CHEN_CH13_Msk (0x1UL << PPI_CHEN_CH13_Pos) /*!< Bit mask of CH13 field. */
Kojto 91:031413cf7a89 3540 #define PPI_CHEN_CH13_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3541 #define PPI_CHEN_CH13_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3542
Kojto 91:031413cf7a89 3543 /* Bit 12 : Enable PPI channel 12. */
Kojto 91:031413cf7a89 3544 #define PPI_CHEN_CH12_Pos (12UL) /*!< Position of CH12 field. */
Kojto 91:031413cf7a89 3545 #define PPI_CHEN_CH12_Msk (0x1UL << PPI_CHEN_CH12_Pos) /*!< Bit mask of CH12 field. */
Kojto 91:031413cf7a89 3546 #define PPI_CHEN_CH12_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3547 #define PPI_CHEN_CH12_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3548
Kojto 91:031413cf7a89 3549 /* Bit 11 : Enable PPI channel 11. */
Kojto 91:031413cf7a89 3550 #define PPI_CHEN_CH11_Pos (11UL) /*!< Position of CH11 field. */
Kojto 91:031413cf7a89 3551 #define PPI_CHEN_CH11_Msk (0x1UL << PPI_CHEN_CH11_Pos) /*!< Bit mask of CH11 field. */
Kojto 91:031413cf7a89 3552 #define PPI_CHEN_CH11_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3553 #define PPI_CHEN_CH11_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3554
Kojto 91:031413cf7a89 3555 /* Bit 10 : Enable PPI channel 10. */
Kojto 91:031413cf7a89 3556 #define PPI_CHEN_CH10_Pos (10UL) /*!< Position of CH10 field. */
Kojto 91:031413cf7a89 3557 #define PPI_CHEN_CH10_Msk (0x1UL << PPI_CHEN_CH10_Pos) /*!< Bit mask of CH10 field. */
Kojto 91:031413cf7a89 3558 #define PPI_CHEN_CH10_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3559 #define PPI_CHEN_CH10_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3560
Kojto 91:031413cf7a89 3561 /* Bit 9 : Enable PPI channel 9. */
Kojto 91:031413cf7a89 3562 #define PPI_CHEN_CH9_Pos (9UL) /*!< Position of CH9 field. */
Kojto 91:031413cf7a89 3563 #define PPI_CHEN_CH9_Msk (0x1UL << PPI_CHEN_CH9_Pos) /*!< Bit mask of CH9 field. */
Kojto 91:031413cf7a89 3564 #define PPI_CHEN_CH9_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3565 #define PPI_CHEN_CH9_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3566
Kojto 91:031413cf7a89 3567 /* Bit 8 : Enable PPI channel 8. */
Kojto 91:031413cf7a89 3568 #define PPI_CHEN_CH8_Pos (8UL) /*!< Position of CH8 field. */
Kojto 91:031413cf7a89 3569 #define PPI_CHEN_CH8_Msk (0x1UL << PPI_CHEN_CH8_Pos) /*!< Bit mask of CH8 field. */
Kojto 91:031413cf7a89 3570 #define PPI_CHEN_CH8_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3571 #define PPI_CHEN_CH8_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3572
Kojto 91:031413cf7a89 3573 /* Bit 7 : Enable PPI channel 7. */
Kojto 91:031413cf7a89 3574 #define PPI_CHEN_CH7_Pos (7UL) /*!< Position of CH7 field. */
Kojto 91:031413cf7a89 3575 #define PPI_CHEN_CH7_Msk (0x1UL << PPI_CHEN_CH7_Pos) /*!< Bit mask of CH7 field. */
Kojto 91:031413cf7a89 3576 #define PPI_CHEN_CH7_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3577 #define PPI_CHEN_CH7_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3578
Kojto 91:031413cf7a89 3579 /* Bit 6 : Enable PPI channel 6. */
Kojto 91:031413cf7a89 3580 #define PPI_CHEN_CH6_Pos (6UL) /*!< Position of CH6 field. */
Kojto 91:031413cf7a89 3581 #define PPI_CHEN_CH6_Msk (0x1UL << PPI_CHEN_CH6_Pos) /*!< Bit mask of CH6 field. */
Kojto 91:031413cf7a89 3582 #define PPI_CHEN_CH6_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3583 #define PPI_CHEN_CH6_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3584
Kojto 91:031413cf7a89 3585 /* Bit 5 : Enable PPI channel 5. */
Kojto 91:031413cf7a89 3586 #define PPI_CHEN_CH5_Pos (5UL) /*!< Position of CH5 field. */
Kojto 91:031413cf7a89 3587 #define PPI_CHEN_CH5_Msk (0x1UL << PPI_CHEN_CH5_Pos) /*!< Bit mask of CH5 field. */
Kojto 91:031413cf7a89 3588 #define PPI_CHEN_CH5_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3589 #define PPI_CHEN_CH5_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3590
Kojto 91:031413cf7a89 3591 /* Bit 4 : Enable PPI channel 4. */
Kojto 91:031413cf7a89 3592 #define PPI_CHEN_CH4_Pos (4UL) /*!< Position of CH4 field. */
Kojto 91:031413cf7a89 3593 #define PPI_CHEN_CH4_Msk (0x1UL << PPI_CHEN_CH4_Pos) /*!< Bit mask of CH4 field. */
Kojto 91:031413cf7a89 3594 #define PPI_CHEN_CH4_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3595 #define PPI_CHEN_CH4_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3596
Kojto 91:031413cf7a89 3597 /* Bit 3 : Enable PPI channel 3. */
Kojto 91:031413cf7a89 3598 #define PPI_CHEN_CH3_Pos (3UL) /*!< Position of CH3 field. */
Kojto 91:031413cf7a89 3599 #define PPI_CHEN_CH3_Msk (0x1UL << PPI_CHEN_CH3_Pos) /*!< Bit mask of CH3 field. */
Kojto 91:031413cf7a89 3600 #define PPI_CHEN_CH3_Disabled (0UL) /*!< Channel disabled */
Kojto 91:031413cf7a89 3601 #define PPI_CHEN_CH3_Enabled (1UL) /*!< Channel enabled */
Kojto 91:031413cf7a89 3602
Kojto 91:031413cf7a89 3603 /* Bit 2 : Enable PPI channel 2. */
Kojto 91:031413cf7a89 3604 #define PPI_CHEN_CH2_Pos (2UL) /*!< Position of CH2 field. */
Kojto 91:031413cf7a89 3605 #define PPI_CHEN_CH2_Msk (0x1UL << PPI_CHEN_CH2_Pos) /*!< Bit mask of CH2 field. */
Kojto 91:031413cf7a89 3606 #define PPI_CHEN_CH2_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3607 #define PPI_CHEN_CH2_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3608
Kojto 91:031413cf7a89 3609 /* Bit 1 : Enable PPI channel 1. */
Kojto 91:031413cf7a89 3610 #define PPI_CHEN_CH1_Pos (1UL) /*!< Position of CH1 field. */
Kojto 91:031413cf7a89 3611 #define PPI_CHEN_CH1_Msk (0x1UL << PPI_CHEN_CH1_Pos) /*!< Bit mask of CH1 field. */
Kojto 91:031413cf7a89 3612 #define PPI_CHEN_CH1_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3613 #define PPI_CHEN_CH1_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3614
Kojto 91:031413cf7a89 3615 /* Bit 0 : Enable PPI channel 0. */
Kojto 91:031413cf7a89 3616 #define PPI_CHEN_CH0_Pos (0UL) /*!< Position of CH0 field. */
Kojto 91:031413cf7a89 3617 #define PPI_CHEN_CH0_Msk (0x1UL << PPI_CHEN_CH0_Pos) /*!< Bit mask of CH0 field. */
Kojto 91:031413cf7a89 3618 #define PPI_CHEN_CH0_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3619 #define PPI_CHEN_CH0_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3620
Kojto 91:031413cf7a89 3621 /* Register: PPI_CHENSET */
Kojto 91:031413cf7a89 3622 /* Description: Channel enable set. */
Kojto 91:031413cf7a89 3623
Kojto 91:031413cf7a89 3624 /* Bit 31 : Enable PPI channel 31. */
Kojto 91:031413cf7a89 3625 #define PPI_CHENSET_CH31_Pos (31UL) /*!< Position of CH31 field. */
Kojto 91:031413cf7a89 3626 #define PPI_CHENSET_CH31_Msk (0x1UL << PPI_CHENSET_CH31_Pos) /*!< Bit mask of CH31 field. */
Kojto 91:031413cf7a89 3627 #define PPI_CHENSET_CH31_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3628 #define PPI_CHENSET_CH31_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3629 #define PPI_CHENSET_CH31_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3630
Kojto 91:031413cf7a89 3631 /* Bit 30 : Enable PPI channel 30. */
Kojto 91:031413cf7a89 3632 #define PPI_CHENSET_CH30_Pos (30UL) /*!< Position of CH30 field. */
Kojto 91:031413cf7a89 3633 #define PPI_CHENSET_CH30_Msk (0x1UL << PPI_CHENSET_CH30_Pos) /*!< Bit mask of CH30 field. */
Kojto 91:031413cf7a89 3634 #define PPI_CHENSET_CH30_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3635 #define PPI_CHENSET_CH30_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3636 #define PPI_CHENSET_CH30_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3637
Kojto 91:031413cf7a89 3638 /* Bit 29 : Enable PPI channel 29. */
Kojto 91:031413cf7a89 3639 #define PPI_CHENSET_CH29_Pos (29UL) /*!< Position of CH29 field. */
Kojto 91:031413cf7a89 3640 #define PPI_CHENSET_CH29_Msk (0x1UL << PPI_CHENSET_CH29_Pos) /*!< Bit mask of CH29 field. */
Kojto 91:031413cf7a89 3641 #define PPI_CHENSET_CH29_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3642 #define PPI_CHENSET_CH29_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3643 #define PPI_CHENSET_CH29_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3644
Kojto 91:031413cf7a89 3645 /* Bit 28 : Enable PPI channel 28. */
Kojto 91:031413cf7a89 3646 #define PPI_CHENSET_CH28_Pos (28UL) /*!< Position of CH28 field. */
Kojto 91:031413cf7a89 3647 #define PPI_CHENSET_CH28_Msk (0x1UL << PPI_CHENSET_CH28_Pos) /*!< Bit mask of CH28 field. */
Kojto 91:031413cf7a89 3648 #define PPI_CHENSET_CH28_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3649 #define PPI_CHENSET_CH28_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3650 #define PPI_CHENSET_CH28_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3651
Kojto 91:031413cf7a89 3652 /* Bit 27 : Enable PPI channel 27. */
Kojto 91:031413cf7a89 3653 #define PPI_CHENSET_CH27_Pos (27UL) /*!< Position of CH27 field. */
Kojto 91:031413cf7a89 3654 #define PPI_CHENSET_CH27_Msk (0x1UL << PPI_CHENSET_CH27_Pos) /*!< Bit mask of CH27 field. */
Kojto 91:031413cf7a89 3655 #define PPI_CHENSET_CH27_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3656 #define PPI_CHENSET_CH27_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3657 #define PPI_CHENSET_CH27_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3658
Kojto 91:031413cf7a89 3659 /* Bit 26 : Enable PPI channel 26. */
Kojto 91:031413cf7a89 3660 #define PPI_CHENSET_CH26_Pos (26UL) /*!< Position of CH26 field. */
Kojto 91:031413cf7a89 3661 #define PPI_CHENSET_CH26_Msk (0x1UL << PPI_CHENSET_CH26_Pos) /*!< Bit mask of CH26 field. */
Kojto 91:031413cf7a89 3662 #define PPI_CHENSET_CH26_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3663 #define PPI_CHENSET_CH26_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3664 #define PPI_CHENSET_CH26_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3665
Kojto 91:031413cf7a89 3666 /* Bit 25 : Enable PPI channel 25. */
Kojto 91:031413cf7a89 3667 #define PPI_CHENSET_CH25_Pos (25UL) /*!< Position of CH25 field. */
Kojto 91:031413cf7a89 3668 #define PPI_CHENSET_CH25_Msk (0x1UL << PPI_CHENSET_CH25_Pos) /*!< Bit mask of CH25 field. */
Kojto 91:031413cf7a89 3669 #define PPI_CHENSET_CH25_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3670 #define PPI_CHENSET_CH25_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3671 #define PPI_CHENSET_CH25_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3672
Kojto 91:031413cf7a89 3673 /* Bit 24 : Enable PPI channel 24. */
Kojto 91:031413cf7a89 3674 #define PPI_CHENSET_CH24_Pos (24UL) /*!< Position of CH24 field. */
Kojto 91:031413cf7a89 3675 #define PPI_CHENSET_CH24_Msk (0x1UL << PPI_CHENSET_CH24_Pos) /*!< Bit mask of CH24 field. */
Kojto 91:031413cf7a89 3676 #define PPI_CHENSET_CH24_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3677 #define PPI_CHENSET_CH24_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3678 #define PPI_CHENSET_CH24_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3679
Kojto 91:031413cf7a89 3680 /* Bit 23 : Enable PPI channel 23. */
Kojto 91:031413cf7a89 3681 #define PPI_CHENSET_CH23_Pos (23UL) /*!< Position of CH23 field. */
Kojto 91:031413cf7a89 3682 #define PPI_CHENSET_CH23_Msk (0x1UL << PPI_CHENSET_CH23_Pos) /*!< Bit mask of CH23 field. */
Kojto 91:031413cf7a89 3683 #define PPI_CHENSET_CH23_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3684 #define PPI_CHENSET_CH23_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3685 #define PPI_CHENSET_CH23_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3686
Kojto 91:031413cf7a89 3687 /* Bit 22 : Enable PPI channel 22. */
Kojto 91:031413cf7a89 3688 #define PPI_CHENSET_CH22_Pos (22UL) /*!< Position of CH22 field. */
Kojto 91:031413cf7a89 3689 #define PPI_CHENSET_CH22_Msk (0x1UL << PPI_CHENSET_CH22_Pos) /*!< Bit mask of CH22 field. */
Kojto 91:031413cf7a89 3690 #define PPI_CHENSET_CH22_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3691 #define PPI_CHENSET_CH22_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3692 #define PPI_CHENSET_CH22_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3693
Kojto 91:031413cf7a89 3694 /* Bit 21 : Enable PPI channel 21. */
Kojto 91:031413cf7a89 3695 #define PPI_CHENSET_CH21_Pos (21UL) /*!< Position of CH21 field. */
Kojto 91:031413cf7a89 3696 #define PPI_CHENSET_CH21_Msk (0x1UL << PPI_CHENSET_CH21_Pos) /*!< Bit mask of CH21 field. */
Kojto 91:031413cf7a89 3697 #define PPI_CHENSET_CH21_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3698 #define PPI_CHENSET_CH21_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3699 #define PPI_CHENSET_CH21_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3700
Kojto 91:031413cf7a89 3701 /* Bit 20 : Enable PPI channel 20. */
Kojto 91:031413cf7a89 3702 #define PPI_CHENSET_CH20_Pos (20UL) /*!< Position of CH20 field. */
Kojto 91:031413cf7a89 3703 #define PPI_CHENSET_CH20_Msk (0x1UL << PPI_CHENSET_CH20_Pos) /*!< Bit mask of CH20 field. */
Kojto 91:031413cf7a89 3704 #define PPI_CHENSET_CH20_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3705 #define PPI_CHENSET_CH20_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3706 #define PPI_CHENSET_CH20_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3707
Kojto 91:031413cf7a89 3708 /* Bit 15 : Enable PPI channel 15. */
Kojto 91:031413cf7a89 3709 #define PPI_CHENSET_CH15_Pos (15UL) /*!< Position of CH15 field. */
Kojto 91:031413cf7a89 3710 #define PPI_CHENSET_CH15_Msk (0x1UL << PPI_CHENSET_CH15_Pos) /*!< Bit mask of CH15 field. */
Kojto 91:031413cf7a89 3711 #define PPI_CHENSET_CH15_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3712 #define PPI_CHENSET_CH15_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3713 #define PPI_CHENSET_CH15_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3714
Kojto 91:031413cf7a89 3715 /* Bit 14 : Enable PPI channel 14. */
Kojto 91:031413cf7a89 3716 #define PPI_CHENSET_CH14_Pos (14UL) /*!< Position of CH14 field. */
Kojto 91:031413cf7a89 3717 #define PPI_CHENSET_CH14_Msk (0x1UL << PPI_CHENSET_CH14_Pos) /*!< Bit mask of CH14 field. */
Kojto 91:031413cf7a89 3718 #define PPI_CHENSET_CH14_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3719 #define PPI_CHENSET_CH14_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3720 #define PPI_CHENSET_CH14_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3721
Kojto 91:031413cf7a89 3722 /* Bit 13 : Enable PPI channel 13. */
Kojto 91:031413cf7a89 3723 #define PPI_CHENSET_CH13_Pos (13UL) /*!< Position of CH13 field. */
Kojto 91:031413cf7a89 3724 #define PPI_CHENSET_CH13_Msk (0x1UL << PPI_CHENSET_CH13_Pos) /*!< Bit mask of CH13 field. */
Kojto 91:031413cf7a89 3725 #define PPI_CHENSET_CH13_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3726 #define PPI_CHENSET_CH13_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3727 #define PPI_CHENSET_CH13_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3728
Kojto 91:031413cf7a89 3729 /* Bit 12 : Enable PPI channel 12. */
Kojto 91:031413cf7a89 3730 #define PPI_CHENSET_CH12_Pos (12UL) /*!< Position of CH12 field. */
Kojto 91:031413cf7a89 3731 #define PPI_CHENSET_CH12_Msk (0x1UL << PPI_CHENSET_CH12_Pos) /*!< Bit mask of CH12 field. */
Kojto 91:031413cf7a89 3732 #define PPI_CHENSET_CH12_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3733 #define PPI_CHENSET_CH12_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3734 #define PPI_CHENSET_CH12_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3735
Kojto 91:031413cf7a89 3736 /* Bit 11 : Enable PPI channel 11. */
Kojto 91:031413cf7a89 3737 #define PPI_CHENSET_CH11_Pos (11UL) /*!< Position of CH11 field. */
Kojto 91:031413cf7a89 3738 #define PPI_CHENSET_CH11_Msk (0x1UL << PPI_CHENSET_CH11_Pos) /*!< Bit mask of CH11 field. */
Kojto 91:031413cf7a89 3739 #define PPI_CHENSET_CH11_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3740 #define PPI_CHENSET_CH11_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3741 #define PPI_CHENSET_CH11_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3742
Kojto 91:031413cf7a89 3743 /* Bit 10 : Enable PPI channel 10. */
Kojto 91:031413cf7a89 3744 #define PPI_CHENSET_CH10_Pos (10UL) /*!< Position of CH10 field. */
Kojto 91:031413cf7a89 3745 #define PPI_CHENSET_CH10_Msk (0x1UL << PPI_CHENSET_CH10_Pos) /*!< Bit mask of CH10 field. */
Kojto 91:031413cf7a89 3746 #define PPI_CHENSET_CH10_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3747 #define PPI_CHENSET_CH10_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3748 #define PPI_CHENSET_CH10_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3749
Kojto 91:031413cf7a89 3750 /* Bit 9 : Enable PPI channel 9. */
Kojto 91:031413cf7a89 3751 #define PPI_CHENSET_CH9_Pos (9UL) /*!< Position of CH9 field. */
Kojto 91:031413cf7a89 3752 #define PPI_CHENSET_CH9_Msk (0x1UL << PPI_CHENSET_CH9_Pos) /*!< Bit mask of CH9 field. */
Kojto 91:031413cf7a89 3753 #define PPI_CHENSET_CH9_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3754 #define PPI_CHENSET_CH9_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3755 #define PPI_CHENSET_CH9_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3756
Kojto 91:031413cf7a89 3757 /* Bit 8 : Enable PPI channel 8. */
Kojto 91:031413cf7a89 3758 #define PPI_CHENSET_CH8_Pos (8UL) /*!< Position of CH8 field. */
Kojto 91:031413cf7a89 3759 #define PPI_CHENSET_CH8_Msk (0x1UL << PPI_CHENSET_CH8_Pos) /*!< Bit mask of CH8 field. */
Kojto 91:031413cf7a89 3760 #define PPI_CHENSET_CH8_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3761 #define PPI_CHENSET_CH8_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3762 #define PPI_CHENSET_CH8_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3763
Kojto 91:031413cf7a89 3764 /* Bit 7 : Enable PPI channel 7. */
Kojto 91:031413cf7a89 3765 #define PPI_CHENSET_CH7_Pos (7UL) /*!< Position of CH7 field. */
Kojto 91:031413cf7a89 3766 #define PPI_CHENSET_CH7_Msk (0x1UL << PPI_CHENSET_CH7_Pos) /*!< Bit mask of CH7 field. */
Kojto 91:031413cf7a89 3767 #define PPI_CHENSET_CH7_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3768 #define PPI_CHENSET_CH7_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3769 #define PPI_CHENSET_CH7_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3770
Kojto 91:031413cf7a89 3771 /* Bit 6 : Enable PPI channel 6. */
Kojto 91:031413cf7a89 3772 #define PPI_CHENSET_CH6_Pos (6UL) /*!< Position of CH6 field. */
Kojto 91:031413cf7a89 3773 #define PPI_CHENSET_CH6_Msk (0x1UL << PPI_CHENSET_CH6_Pos) /*!< Bit mask of CH6 field. */
Kojto 91:031413cf7a89 3774 #define PPI_CHENSET_CH6_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3775 #define PPI_CHENSET_CH6_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3776 #define PPI_CHENSET_CH6_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3777
Kojto 91:031413cf7a89 3778 /* Bit 5 : Enable PPI channel 5. */
Kojto 91:031413cf7a89 3779 #define PPI_CHENSET_CH5_Pos (5UL) /*!< Position of CH5 field. */
Kojto 91:031413cf7a89 3780 #define PPI_CHENSET_CH5_Msk (0x1UL << PPI_CHENSET_CH5_Pos) /*!< Bit mask of CH5 field. */
Kojto 91:031413cf7a89 3781 #define PPI_CHENSET_CH5_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3782 #define PPI_CHENSET_CH5_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3783 #define PPI_CHENSET_CH5_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3784
Kojto 91:031413cf7a89 3785 /* Bit 4 : Enable PPI channel 4. */
Kojto 91:031413cf7a89 3786 #define PPI_CHENSET_CH4_Pos (4UL) /*!< Position of CH4 field. */
Kojto 91:031413cf7a89 3787 #define PPI_CHENSET_CH4_Msk (0x1UL << PPI_CHENSET_CH4_Pos) /*!< Bit mask of CH4 field. */
Kojto 91:031413cf7a89 3788 #define PPI_CHENSET_CH4_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3789 #define PPI_CHENSET_CH4_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3790 #define PPI_CHENSET_CH4_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3791
Kojto 91:031413cf7a89 3792 /* Bit 3 : Enable PPI channel 3. */
Kojto 91:031413cf7a89 3793 #define PPI_CHENSET_CH3_Pos (3UL) /*!< Position of CH3 field. */
Kojto 91:031413cf7a89 3794 #define PPI_CHENSET_CH3_Msk (0x1UL << PPI_CHENSET_CH3_Pos) /*!< Bit mask of CH3 field. */
Kojto 91:031413cf7a89 3795 #define PPI_CHENSET_CH3_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3796 #define PPI_CHENSET_CH3_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3797 #define PPI_CHENSET_CH3_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3798
Kojto 91:031413cf7a89 3799 /* Bit 2 : Enable PPI channel 2. */
Kojto 91:031413cf7a89 3800 #define PPI_CHENSET_CH2_Pos (2UL) /*!< Position of CH2 field. */
Kojto 91:031413cf7a89 3801 #define PPI_CHENSET_CH2_Msk (0x1UL << PPI_CHENSET_CH2_Pos) /*!< Bit mask of CH2 field. */
Kojto 91:031413cf7a89 3802 #define PPI_CHENSET_CH2_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3803 #define PPI_CHENSET_CH2_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3804 #define PPI_CHENSET_CH2_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3805
Kojto 91:031413cf7a89 3806 /* Bit 1 : Enable PPI channel 1. */
Kojto 91:031413cf7a89 3807 #define PPI_CHENSET_CH1_Pos (1UL) /*!< Position of CH1 field. */
Kojto 91:031413cf7a89 3808 #define PPI_CHENSET_CH1_Msk (0x1UL << PPI_CHENSET_CH1_Pos) /*!< Bit mask of CH1 field. */
Kojto 91:031413cf7a89 3809 #define PPI_CHENSET_CH1_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3810 #define PPI_CHENSET_CH1_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3811 #define PPI_CHENSET_CH1_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3812
Kojto 91:031413cf7a89 3813 /* Bit 0 : Enable PPI channel 0. */
Kojto 91:031413cf7a89 3814 #define PPI_CHENSET_CH0_Pos (0UL) /*!< Position of CH0 field. */
Kojto 91:031413cf7a89 3815 #define PPI_CHENSET_CH0_Msk (0x1UL << PPI_CHENSET_CH0_Pos) /*!< Bit mask of CH0 field. */
Kojto 91:031413cf7a89 3816 #define PPI_CHENSET_CH0_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3817 #define PPI_CHENSET_CH0_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3818 #define PPI_CHENSET_CH0_Set (1UL) /*!< Enable channel on write. */
Kojto 91:031413cf7a89 3819
Kojto 91:031413cf7a89 3820 /* Register: PPI_CHENCLR */
Kojto 91:031413cf7a89 3821 /* Description: Channel enable clear. */
Kojto 91:031413cf7a89 3822
Kojto 91:031413cf7a89 3823 /* Bit 31 : Disable PPI channel 31. */
Kojto 91:031413cf7a89 3824 #define PPI_CHENCLR_CH31_Pos (31UL) /*!< Position of CH31 field. */
Kojto 91:031413cf7a89 3825 #define PPI_CHENCLR_CH31_Msk (0x1UL << PPI_CHENCLR_CH31_Pos) /*!< Bit mask of CH31 field. */
Kojto 91:031413cf7a89 3826 #define PPI_CHENCLR_CH31_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3827 #define PPI_CHENCLR_CH31_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3828 #define PPI_CHENCLR_CH31_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3829
Kojto 91:031413cf7a89 3830 /* Bit 30 : Disable PPI channel 30. */
Kojto 91:031413cf7a89 3831 #define PPI_CHENCLR_CH30_Pos (30UL) /*!< Position of CH30 field. */
Kojto 91:031413cf7a89 3832 #define PPI_CHENCLR_CH30_Msk (0x1UL << PPI_CHENCLR_CH30_Pos) /*!< Bit mask of CH30 field. */
Kojto 91:031413cf7a89 3833 #define PPI_CHENCLR_CH30_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3834 #define PPI_CHENCLR_CH30_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3835 #define PPI_CHENCLR_CH30_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3836
Kojto 91:031413cf7a89 3837 /* Bit 29 : Disable PPI channel 29. */
Kojto 91:031413cf7a89 3838 #define PPI_CHENCLR_CH29_Pos (29UL) /*!< Position of CH29 field. */
Kojto 91:031413cf7a89 3839 #define PPI_CHENCLR_CH29_Msk (0x1UL << PPI_CHENCLR_CH29_Pos) /*!< Bit mask of CH29 field. */
Kojto 91:031413cf7a89 3840 #define PPI_CHENCLR_CH29_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3841 #define PPI_CHENCLR_CH29_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3842 #define PPI_CHENCLR_CH29_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3843
Kojto 91:031413cf7a89 3844 /* Bit 28 : Disable PPI channel 28. */
Kojto 91:031413cf7a89 3845 #define PPI_CHENCLR_CH28_Pos (28UL) /*!< Position of CH28 field. */
Kojto 91:031413cf7a89 3846 #define PPI_CHENCLR_CH28_Msk (0x1UL << PPI_CHENCLR_CH28_Pos) /*!< Bit mask of CH28 field. */
Kojto 91:031413cf7a89 3847 #define PPI_CHENCLR_CH28_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3848 #define PPI_CHENCLR_CH28_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3849 #define PPI_CHENCLR_CH28_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3850
Kojto 91:031413cf7a89 3851 /* Bit 27 : Disable PPI channel 27. */
Kojto 91:031413cf7a89 3852 #define PPI_CHENCLR_CH27_Pos (27UL) /*!< Position of CH27 field. */
Kojto 91:031413cf7a89 3853 #define PPI_CHENCLR_CH27_Msk (0x1UL << PPI_CHENCLR_CH27_Pos) /*!< Bit mask of CH27 field. */
Kojto 91:031413cf7a89 3854 #define PPI_CHENCLR_CH27_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3855 #define PPI_CHENCLR_CH27_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3856 #define PPI_CHENCLR_CH27_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3857
Kojto 91:031413cf7a89 3858 /* Bit 26 : Disable PPI channel 26. */
Kojto 91:031413cf7a89 3859 #define PPI_CHENCLR_CH26_Pos (26UL) /*!< Position of CH26 field. */
Kojto 91:031413cf7a89 3860 #define PPI_CHENCLR_CH26_Msk (0x1UL << PPI_CHENCLR_CH26_Pos) /*!< Bit mask of CH26 field. */
Kojto 91:031413cf7a89 3861 #define PPI_CHENCLR_CH26_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3862 #define PPI_CHENCLR_CH26_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3863 #define PPI_CHENCLR_CH26_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3864
Kojto 91:031413cf7a89 3865 /* Bit 25 : Disable PPI channel 25. */
Kojto 91:031413cf7a89 3866 #define PPI_CHENCLR_CH25_Pos (25UL) /*!< Position of CH25 field. */
Kojto 91:031413cf7a89 3867 #define PPI_CHENCLR_CH25_Msk (0x1UL << PPI_CHENCLR_CH25_Pos) /*!< Bit mask of CH25 field. */
Kojto 91:031413cf7a89 3868 #define PPI_CHENCLR_CH25_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3869 #define PPI_CHENCLR_CH25_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3870 #define PPI_CHENCLR_CH25_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3871
Kojto 91:031413cf7a89 3872 /* Bit 24 : Disable PPI channel 24. */
Kojto 91:031413cf7a89 3873 #define PPI_CHENCLR_CH24_Pos (24UL) /*!< Position of CH24 field. */
Kojto 91:031413cf7a89 3874 #define PPI_CHENCLR_CH24_Msk (0x1UL << PPI_CHENCLR_CH24_Pos) /*!< Bit mask of CH24 field. */
Kojto 91:031413cf7a89 3875 #define PPI_CHENCLR_CH24_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3876 #define PPI_CHENCLR_CH24_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3877 #define PPI_CHENCLR_CH24_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3878
Kojto 91:031413cf7a89 3879 /* Bit 23 : Disable PPI channel 23. */
Kojto 91:031413cf7a89 3880 #define PPI_CHENCLR_CH23_Pos (23UL) /*!< Position of CH23 field. */
Kojto 91:031413cf7a89 3881 #define PPI_CHENCLR_CH23_Msk (0x1UL << PPI_CHENCLR_CH23_Pos) /*!< Bit mask of CH23 field. */
Kojto 91:031413cf7a89 3882 #define PPI_CHENCLR_CH23_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3883 #define PPI_CHENCLR_CH23_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3884 #define PPI_CHENCLR_CH23_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3885
Kojto 91:031413cf7a89 3886 /* Bit 22 : Disable PPI channel 22. */
Kojto 91:031413cf7a89 3887 #define PPI_CHENCLR_CH22_Pos (22UL) /*!< Position of CH22 field. */
Kojto 91:031413cf7a89 3888 #define PPI_CHENCLR_CH22_Msk (0x1UL << PPI_CHENCLR_CH22_Pos) /*!< Bit mask of CH22 field. */
Kojto 91:031413cf7a89 3889 #define PPI_CHENCLR_CH22_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3890 #define PPI_CHENCLR_CH22_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3891 #define PPI_CHENCLR_CH22_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3892
Kojto 91:031413cf7a89 3893 /* Bit 21 : Disable PPI channel 21. */
Kojto 91:031413cf7a89 3894 #define PPI_CHENCLR_CH21_Pos (21UL) /*!< Position of CH21 field. */
Kojto 91:031413cf7a89 3895 #define PPI_CHENCLR_CH21_Msk (0x1UL << PPI_CHENCLR_CH21_Pos) /*!< Bit mask of CH21 field. */
Kojto 91:031413cf7a89 3896 #define PPI_CHENCLR_CH21_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3897 #define PPI_CHENCLR_CH21_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3898 #define PPI_CHENCLR_CH21_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3899
Kojto 91:031413cf7a89 3900 /* Bit 20 : Disable PPI channel 20. */
Kojto 91:031413cf7a89 3901 #define PPI_CHENCLR_CH20_Pos (20UL) /*!< Position of CH20 field. */
Kojto 91:031413cf7a89 3902 #define PPI_CHENCLR_CH20_Msk (0x1UL << PPI_CHENCLR_CH20_Pos) /*!< Bit mask of CH20 field. */
Kojto 91:031413cf7a89 3903 #define PPI_CHENCLR_CH20_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3904 #define PPI_CHENCLR_CH20_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3905 #define PPI_CHENCLR_CH20_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3906
Kojto 91:031413cf7a89 3907 /* Bit 15 : Disable PPI channel 15. */
Kojto 91:031413cf7a89 3908 #define PPI_CHENCLR_CH15_Pos (15UL) /*!< Position of CH15 field. */
Kojto 91:031413cf7a89 3909 #define PPI_CHENCLR_CH15_Msk (0x1UL << PPI_CHENCLR_CH15_Pos) /*!< Bit mask of CH15 field. */
Kojto 91:031413cf7a89 3910 #define PPI_CHENCLR_CH15_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3911 #define PPI_CHENCLR_CH15_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3912 #define PPI_CHENCLR_CH15_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3913
Kojto 91:031413cf7a89 3914 /* Bit 14 : Disable PPI channel 14. */
Kojto 91:031413cf7a89 3915 #define PPI_CHENCLR_CH14_Pos (14UL) /*!< Position of CH14 field. */
Kojto 91:031413cf7a89 3916 #define PPI_CHENCLR_CH14_Msk (0x1UL << PPI_CHENCLR_CH14_Pos) /*!< Bit mask of CH14 field. */
Kojto 91:031413cf7a89 3917 #define PPI_CHENCLR_CH14_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3918 #define PPI_CHENCLR_CH14_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3919 #define PPI_CHENCLR_CH14_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3920
Kojto 91:031413cf7a89 3921 /* Bit 13 : Disable PPI channel 13. */
Kojto 91:031413cf7a89 3922 #define PPI_CHENCLR_CH13_Pos (13UL) /*!< Position of CH13 field. */
Kojto 91:031413cf7a89 3923 #define PPI_CHENCLR_CH13_Msk (0x1UL << PPI_CHENCLR_CH13_Pos) /*!< Bit mask of CH13 field. */
Kojto 91:031413cf7a89 3924 #define PPI_CHENCLR_CH13_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3925 #define PPI_CHENCLR_CH13_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3926 #define PPI_CHENCLR_CH13_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3927
Kojto 91:031413cf7a89 3928 /* Bit 12 : Disable PPI channel 12. */
Kojto 91:031413cf7a89 3929 #define PPI_CHENCLR_CH12_Pos (12UL) /*!< Position of CH12 field. */
Kojto 91:031413cf7a89 3930 #define PPI_CHENCLR_CH12_Msk (0x1UL << PPI_CHENCLR_CH12_Pos) /*!< Bit mask of CH12 field. */
Kojto 91:031413cf7a89 3931 #define PPI_CHENCLR_CH12_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3932 #define PPI_CHENCLR_CH12_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3933 #define PPI_CHENCLR_CH12_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3934
Kojto 91:031413cf7a89 3935 /* Bit 11 : Disable PPI channel 11. */
Kojto 91:031413cf7a89 3936 #define PPI_CHENCLR_CH11_Pos (11UL) /*!< Position of CH11 field. */
Kojto 91:031413cf7a89 3937 #define PPI_CHENCLR_CH11_Msk (0x1UL << PPI_CHENCLR_CH11_Pos) /*!< Bit mask of CH11 field. */
Kojto 91:031413cf7a89 3938 #define PPI_CHENCLR_CH11_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3939 #define PPI_CHENCLR_CH11_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3940 #define PPI_CHENCLR_CH11_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3941
Kojto 91:031413cf7a89 3942 /* Bit 10 : Disable PPI channel 10. */
Kojto 91:031413cf7a89 3943 #define PPI_CHENCLR_CH10_Pos (10UL) /*!< Position of CH10 field. */
Kojto 91:031413cf7a89 3944 #define PPI_CHENCLR_CH10_Msk (0x1UL << PPI_CHENCLR_CH10_Pos) /*!< Bit mask of CH10 field. */
Kojto 91:031413cf7a89 3945 #define PPI_CHENCLR_CH10_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3946 #define PPI_CHENCLR_CH10_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3947 #define PPI_CHENCLR_CH10_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3948
Kojto 91:031413cf7a89 3949 /* Bit 9 : Disable PPI channel 9. */
Kojto 91:031413cf7a89 3950 #define PPI_CHENCLR_CH9_Pos (9UL) /*!< Position of CH9 field. */
Kojto 91:031413cf7a89 3951 #define PPI_CHENCLR_CH9_Msk (0x1UL << PPI_CHENCLR_CH9_Pos) /*!< Bit mask of CH9 field. */
Kojto 91:031413cf7a89 3952 #define PPI_CHENCLR_CH9_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3953 #define PPI_CHENCLR_CH9_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3954 #define PPI_CHENCLR_CH9_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3955
Kojto 91:031413cf7a89 3956 /* Bit 8 : Disable PPI channel 8. */
Kojto 91:031413cf7a89 3957 #define PPI_CHENCLR_CH8_Pos (8UL) /*!< Position of CH8 field. */
Kojto 91:031413cf7a89 3958 #define PPI_CHENCLR_CH8_Msk (0x1UL << PPI_CHENCLR_CH8_Pos) /*!< Bit mask of CH8 field. */
Kojto 91:031413cf7a89 3959 #define PPI_CHENCLR_CH8_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3960 #define PPI_CHENCLR_CH8_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3961 #define PPI_CHENCLR_CH8_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3962
Kojto 91:031413cf7a89 3963 /* Bit 7 : Disable PPI channel 7. */
Kojto 91:031413cf7a89 3964 #define PPI_CHENCLR_CH7_Pos (7UL) /*!< Position of CH7 field. */
Kojto 91:031413cf7a89 3965 #define PPI_CHENCLR_CH7_Msk (0x1UL << PPI_CHENCLR_CH7_Pos) /*!< Bit mask of CH7 field. */
Kojto 91:031413cf7a89 3966 #define PPI_CHENCLR_CH7_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3967 #define PPI_CHENCLR_CH7_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3968 #define PPI_CHENCLR_CH7_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3969
Kojto 91:031413cf7a89 3970 /* Bit 6 : Disable PPI channel 6. */
Kojto 91:031413cf7a89 3971 #define PPI_CHENCLR_CH6_Pos (6UL) /*!< Position of CH6 field. */
Kojto 91:031413cf7a89 3972 #define PPI_CHENCLR_CH6_Msk (0x1UL << PPI_CHENCLR_CH6_Pos) /*!< Bit mask of CH6 field. */
Kojto 91:031413cf7a89 3973 #define PPI_CHENCLR_CH6_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3974 #define PPI_CHENCLR_CH6_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3975 #define PPI_CHENCLR_CH6_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3976
Kojto 91:031413cf7a89 3977 /* Bit 5 : Disable PPI channel 5. */
Kojto 91:031413cf7a89 3978 #define PPI_CHENCLR_CH5_Pos (5UL) /*!< Position of CH5 field. */
Kojto 91:031413cf7a89 3979 #define PPI_CHENCLR_CH5_Msk (0x1UL << PPI_CHENCLR_CH5_Pos) /*!< Bit mask of CH5 field. */
Kojto 91:031413cf7a89 3980 #define PPI_CHENCLR_CH5_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3981 #define PPI_CHENCLR_CH5_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3982 #define PPI_CHENCLR_CH5_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3983
Kojto 91:031413cf7a89 3984 /* Bit 4 : Disable PPI channel 4. */
Kojto 91:031413cf7a89 3985 #define PPI_CHENCLR_CH4_Pos (4UL) /*!< Position of CH4 field. */
Kojto 91:031413cf7a89 3986 #define PPI_CHENCLR_CH4_Msk (0x1UL << PPI_CHENCLR_CH4_Pos) /*!< Bit mask of CH4 field. */
Kojto 91:031413cf7a89 3987 #define PPI_CHENCLR_CH4_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3988 #define PPI_CHENCLR_CH4_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3989 #define PPI_CHENCLR_CH4_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3990
Kojto 91:031413cf7a89 3991 /* Bit 3 : Disable PPI channel 3. */
Kojto 91:031413cf7a89 3992 #define PPI_CHENCLR_CH3_Pos (3UL) /*!< Position of CH3 field. */
Kojto 91:031413cf7a89 3993 #define PPI_CHENCLR_CH3_Msk (0x1UL << PPI_CHENCLR_CH3_Pos) /*!< Bit mask of CH3 field. */
Kojto 91:031413cf7a89 3994 #define PPI_CHENCLR_CH3_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 3995 #define PPI_CHENCLR_CH3_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 3996 #define PPI_CHENCLR_CH3_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 3997
Kojto 91:031413cf7a89 3998 /* Bit 2 : Disable PPI channel 2. */
Kojto 91:031413cf7a89 3999 #define PPI_CHENCLR_CH2_Pos (2UL) /*!< Position of CH2 field. */
Kojto 91:031413cf7a89 4000 #define PPI_CHENCLR_CH2_Msk (0x1UL << PPI_CHENCLR_CH2_Pos) /*!< Bit mask of CH2 field. */
Kojto 91:031413cf7a89 4001 #define PPI_CHENCLR_CH2_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 4002 #define PPI_CHENCLR_CH2_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 4003 #define PPI_CHENCLR_CH2_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 4004
Kojto 91:031413cf7a89 4005 /* Bit 1 : Disable PPI channel 1. */
Kojto 91:031413cf7a89 4006 #define PPI_CHENCLR_CH1_Pos (1UL) /*!< Position of CH1 field. */
Kojto 91:031413cf7a89 4007 #define PPI_CHENCLR_CH1_Msk (0x1UL << PPI_CHENCLR_CH1_Pos) /*!< Bit mask of CH1 field. */
Kojto 91:031413cf7a89 4008 #define PPI_CHENCLR_CH1_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 4009 #define PPI_CHENCLR_CH1_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 4010 #define PPI_CHENCLR_CH1_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 4011
Kojto 91:031413cf7a89 4012 /* Bit 0 : Disable PPI channel 0. */
Kojto 91:031413cf7a89 4013 #define PPI_CHENCLR_CH0_Pos (0UL) /*!< Position of CH0 field. */
Kojto 91:031413cf7a89 4014 #define PPI_CHENCLR_CH0_Msk (0x1UL << PPI_CHENCLR_CH0_Pos) /*!< Bit mask of CH0 field. */
Kojto 91:031413cf7a89 4015 #define PPI_CHENCLR_CH0_Disabled (0UL) /*!< Channel disabled. */
Kojto 91:031413cf7a89 4016 #define PPI_CHENCLR_CH0_Enabled (1UL) /*!< Channel enabled. */
Kojto 91:031413cf7a89 4017 #define PPI_CHENCLR_CH0_Clear (1UL) /*!< Disable channel on write. */
Kojto 91:031413cf7a89 4018
Kojto 91:031413cf7a89 4019 /* Register: PPI_CHG */
Kojto 91:031413cf7a89 4020 /* Description: Channel group configuration. */
Kojto 91:031413cf7a89 4021
Kojto 91:031413cf7a89 4022 /* Bit 31 : Include CH31 in channel group. */
Kojto 91:031413cf7a89 4023 #define PPI_CHG_CH31_Pos (31UL) /*!< Position of CH31 field. */
Kojto 91:031413cf7a89 4024 #define PPI_CHG_CH31_Msk (0x1UL << PPI_CHG_CH31_Pos) /*!< Bit mask of CH31 field. */
Kojto 91:031413cf7a89 4025 #define PPI_CHG_CH31_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4026 #define PPI_CHG_CH31_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4027
Kojto 91:031413cf7a89 4028 /* Bit 30 : Include CH30 in channel group. */
Kojto 91:031413cf7a89 4029 #define PPI_CHG_CH30_Pos (30UL) /*!< Position of CH30 field. */
Kojto 91:031413cf7a89 4030 #define PPI_CHG_CH30_Msk (0x1UL << PPI_CHG_CH30_Pos) /*!< Bit mask of CH30 field. */
Kojto 91:031413cf7a89 4031 #define PPI_CHG_CH30_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4032 #define PPI_CHG_CH30_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4033
Kojto 91:031413cf7a89 4034 /* Bit 29 : Include CH29 in channel group. */
Kojto 91:031413cf7a89 4035 #define PPI_CHG_CH29_Pos (29UL) /*!< Position of CH29 field. */
Kojto 91:031413cf7a89 4036 #define PPI_CHG_CH29_Msk (0x1UL << PPI_CHG_CH29_Pos) /*!< Bit mask of CH29 field. */
Kojto 91:031413cf7a89 4037 #define PPI_CHG_CH29_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4038 #define PPI_CHG_CH29_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4039
Kojto 91:031413cf7a89 4040 /* Bit 28 : Include CH28 in channel group. */
Kojto 91:031413cf7a89 4041 #define PPI_CHG_CH28_Pos (28UL) /*!< Position of CH28 field. */
Kojto 91:031413cf7a89 4042 #define PPI_CHG_CH28_Msk (0x1UL << PPI_CHG_CH28_Pos) /*!< Bit mask of CH28 field. */
Kojto 91:031413cf7a89 4043 #define PPI_CHG_CH28_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4044 #define PPI_CHG_CH28_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4045
Kojto 91:031413cf7a89 4046 /* Bit 27 : Include CH27 in channel group. */
Kojto 91:031413cf7a89 4047 #define PPI_CHG_CH27_Pos (27UL) /*!< Position of CH27 field. */
Kojto 91:031413cf7a89 4048 #define PPI_CHG_CH27_Msk (0x1UL << PPI_CHG_CH27_Pos) /*!< Bit mask of CH27 field. */
Kojto 91:031413cf7a89 4049 #define PPI_CHG_CH27_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4050 #define PPI_CHG_CH27_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4051
Kojto 91:031413cf7a89 4052 /* Bit 26 : Include CH26 in channel group. */
Kojto 91:031413cf7a89 4053 #define PPI_CHG_CH26_Pos (26UL) /*!< Position of CH26 field. */
Kojto 91:031413cf7a89 4054 #define PPI_CHG_CH26_Msk (0x1UL << PPI_CHG_CH26_Pos) /*!< Bit mask of CH26 field. */
Kojto 91:031413cf7a89 4055 #define PPI_CHG_CH26_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4056 #define PPI_CHG_CH26_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4057
Kojto 91:031413cf7a89 4058 /* Bit 25 : Include CH25 in channel group. */
Kojto 91:031413cf7a89 4059 #define PPI_CHG_CH25_Pos (25UL) /*!< Position of CH25 field. */
Kojto 91:031413cf7a89 4060 #define PPI_CHG_CH25_Msk (0x1UL << PPI_CHG_CH25_Pos) /*!< Bit mask of CH25 field. */
Kojto 91:031413cf7a89 4061 #define PPI_CHG_CH25_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4062 #define PPI_CHG_CH25_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4063
Kojto 91:031413cf7a89 4064 /* Bit 24 : Include CH24 in channel group. */
Kojto 91:031413cf7a89 4065 #define PPI_CHG_CH24_Pos (24UL) /*!< Position of CH24 field. */
Kojto 91:031413cf7a89 4066 #define PPI_CHG_CH24_Msk (0x1UL << PPI_CHG_CH24_Pos) /*!< Bit mask of CH24 field. */
Kojto 91:031413cf7a89 4067 #define PPI_CHG_CH24_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4068 #define PPI_CHG_CH24_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4069
Kojto 91:031413cf7a89 4070 /* Bit 23 : Include CH23 in channel group. */
Kojto 91:031413cf7a89 4071 #define PPI_CHG_CH23_Pos (23UL) /*!< Position of CH23 field. */
Kojto 91:031413cf7a89 4072 #define PPI_CHG_CH23_Msk (0x1UL << PPI_CHG_CH23_Pos) /*!< Bit mask of CH23 field. */
Kojto 91:031413cf7a89 4073 #define PPI_CHG_CH23_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4074 #define PPI_CHG_CH23_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4075
Kojto 91:031413cf7a89 4076 /* Bit 22 : Include CH22 in channel group. */
Kojto 91:031413cf7a89 4077 #define PPI_CHG_CH22_Pos (22UL) /*!< Position of CH22 field. */
Kojto 91:031413cf7a89 4078 #define PPI_CHG_CH22_Msk (0x1UL << PPI_CHG_CH22_Pos) /*!< Bit mask of CH22 field. */
Kojto 91:031413cf7a89 4079 #define PPI_CHG_CH22_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4080 #define PPI_CHG_CH22_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4081
Kojto 91:031413cf7a89 4082 /* Bit 21 : Include CH21 in channel group. */
Kojto 91:031413cf7a89 4083 #define PPI_CHG_CH21_Pos (21UL) /*!< Position of CH21 field. */
Kojto 91:031413cf7a89 4084 #define PPI_CHG_CH21_Msk (0x1UL << PPI_CHG_CH21_Pos) /*!< Bit mask of CH21 field. */
Kojto 91:031413cf7a89 4085 #define PPI_CHG_CH21_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4086 #define PPI_CHG_CH21_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4087
Kojto 91:031413cf7a89 4088 /* Bit 20 : Include CH20 in channel group. */
Kojto 91:031413cf7a89 4089 #define PPI_CHG_CH20_Pos (20UL) /*!< Position of CH20 field. */
Kojto 91:031413cf7a89 4090 #define PPI_CHG_CH20_Msk (0x1UL << PPI_CHG_CH20_Pos) /*!< Bit mask of CH20 field. */
Kojto 91:031413cf7a89 4091 #define PPI_CHG_CH20_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4092 #define PPI_CHG_CH20_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4093
Kojto 91:031413cf7a89 4094 /* Bit 15 : Include CH15 in channel group. */
Kojto 91:031413cf7a89 4095 #define PPI_CHG_CH15_Pos (15UL) /*!< Position of CH15 field. */
Kojto 91:031413cf7a89 4096 #define PPI_CHG_CH15_Msk (0x1UL << PPI_CHG_CH15_Pos) /*!< Bit mask of CH15 field. */
Kojto 91:031413cf7a89 4097 #define PPI_CHG_CH15_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4098 #define PPI_CHG_CH15_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4099
Kojto 91:031413cf7a89 4100 /* Bit 14 : Include CH14 in channel group. */
Kojto 91:031413cf7a89 4101 #define PPI_CHG_CH14_Pos (14UL) /*!< Position of CH14 field. */
Kojto 91:031413cf7a89 4102 #define PPI_CHG_CH14_Msk (0x1UL << PPI_CHG_CH14_Pos) /*!< Bit mask of CH14 field. */
Kojto 91:031413cf7a89 4103 #define PPI_CHG_CH14_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4104 #define PPI_CHG_CH14_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4105
Kojto 91:031413cf7a89 4106 /* Bit 13 : Include CH13 in channel group. */
Kojto 91:031413cf7a89 4107 #define PPI_CHG_CH13_Pos (13UL) /*!< Position of CH13 field. */
Kojto 91:031413cf7a89 4108 #define PPI_CHG_CH13_Msk (0x1UL << PPI_CHG_CH13_Pos) /*!< Bit mask of CH13 field. */
Kojto 91:031413cf7a89 4109 #define PPI_CHG_CH13_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4110 #define PPI_CHG_CH13_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4111
Kojto 91:031413cf7a89 4112 /* Bit 12 : Include CH12 in channel group. */
Kojto 91:031413cf7a89 4113 #define PPI_CHG_CH12_Pos (12UL) /*!< Position of CH12 field. */
Kojto 91:031413cf7a89 4114 #define PPI_CHG_CH12_Msk (0x1UL << PPI_CHG_CH12_Pos) /*!< Bit mask of CH12 field. */
Kojto 91:031413cf7a89 4115 #define PPI_CHG_CH12_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4116 #define PPI_CHG_CH12_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4117
Kojto 91:031413cf7a89 4118 /* Bit 11 : Include CH11 in channel group. */
Kojto 91:031413cf7a89 4119 #define PPI_CHG_CH11_Pos (11UL) /*!< Position of CH11 field. */
Kojto 91:031413cf7a89 4120 #define PPI_CHG_CH11_Msk (0x1UL << PPI_CHG_CH11_Pos) /*!< Bit mask of CH11 field. */
Kojto 91:031413cf7a89 4121 #define PPI_CHG_CH11_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4122 #define PPI_CHG_CH11_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4123
Kojto 91:031413cf7a89 4124 /* Bit 10 : Include CH10 in channel group. */
Kojto 91:031413cf7a89 4125 #define PPI_CHG_CH10_Pos (10UL) /*!< Position of CH10 field. */
Kojto 91:031413cf7a89 4126 #define PPI_CHG_CH10_Msk (0x1UL << PPI_CHG_CH10_Pos) /*!< Bit mask of CH10 field. */
Kojto 91:031413cf7a89 4127 #define PPI_CHG_CH10_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4128 #define PPI_CHG_CH10_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4129
Kojto 91:031413cf7a89 4130 /* Bit 9 : Include CH9 in channel group. */
Kojto 91:031413cf7a89 4131 #define PPI_CHG_CH9_Pos (9UL) /*!< Position of CH9 field. */
Kojto 91:031413cf7a89 4132 #define PPI_CHG_CH9_Msk (0x1UL << PPI_CHG_CH9_Pos) /*!< Bit mask of CH9 field. */
Kojto 91:031413cf7a89 4133 #define PPI_CHG_CH9_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4134 #define PPI_CHG_CH9_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4135
Kojto 91:031413cf7a89 4136 /* Bit 8 : Include CH8 in channel group. */
Kojto 91:031413cf7a89 4137 #define PPI_CHG_CH8_Pos (8UL) /*!< Position of CH8 field. */
Kojto 91:031413cf7a89 4138 #define PPI_CHG_CH8_Msk (0x1UL << PPI_CHG_CH8_Pos) /*!< Bit mask of CH8 field. */
Kojto 91:031413cf7a89 4139 #define PPI_CHG_CH8_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4140 #define PPI_CHG_CH8_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4141
Kojto 91:031413cf7a89 4142 /* Bit 7 : Include CH7 in channel group. */
Kojto 91:031413cf7a89 4143 #define PPI_CHG_CH7_Pos (7UL) /*!< Position of CH7 field. */
Kojto 91:031413cf7a89 4144 #define PPI_CHG_CH7_Msk (0x1UL << PPI_CHG_CH7_Pos) /*!< Bit mask of CH7 field. */
Kojto 91:031413cf7a89 4145 #define PPI_CHG_CH7_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4146 #define PPI_CHG_CH7_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4147
Kojto 91:031413cf7a89 4148 /* Bit 6 : Include CH6 in channel group. */
Kojto 91:031413cf7a89 4149 #define PPI_CHG_CH6_Pos (6UL) /*!< Position of CH6 field. */
Kojto 91:031413cf7a89 4150 #define PPI_CHG_CH6_Msk (0x1UL << PPI_CHG_CH6_Pos) /*!< Bit mask of CH6 field. */
Kojto 91:031413cf7a89 4151 #define PPI_CHG_CH6_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4152 #define PPI_CHG_CH6_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4153
Kojto 91:031413cf7a89 4154 /* Bit 5 : Include CH5 in channel group. */
Kojto 91:031413cf7a89 4155 #define PPI_CHG_CH5_Pos (5UL) /*!< Position of CH5 field. */
Kojto 91:031413cf7a89 4156 #define PPI_CHG_CH5_Msk (0x1UL << PPI_CHG_CH5_Pos) /*!< Bit mask of CH5 field. */
Kojto 91:031413cf7a89 4157 #define PPI_CHG_CH5_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4158 #define PPI_CHG_CH5_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4159
Kojto 91:031413cf7a89 4160 /* Bit 4 : Include CH4 in channel group. */
Kojto 91:031413cf7a89 4161 #define PPI_CHG_CH4_Pos (4UL) /*!< Position of CH4 field. */
Kojto 91:031413cf7a89 4162 #define PPI_CHG_CH4_Msk (0x1UL << PPI_CHG_CH4_Pos) /*!< Bit mask of CH4 field. */
Kojto 91:031413cf7a89 4163 #define PPI_CHG_CH4_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4164 #define PPI_CHG_CH4_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4165
Kojto 91:031413cf7a89 4166 /* Bit 3 : Include CH3 in channel group. */
Kojto 91:031413cf7a89 4167 #define PPI_CHG_CH3_Pos (3UL) /*!< Position of CH3 field. */
Kojto 91:031413cf7a89 4168 #define PPI_CHG_CH3_Msk (0x1UL << PPI_CHG_CH3_Pos) /*!< Bit mask of CH3 field. */
Kojto 91:031413cf7a89 4169 #define PPI_CHG_CH3_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4170 #define PPI_CHG_CH3_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4171
Kojto 91:031413cf7a89 4172 /* Bit 2 : Include CH2 in channel group. */
Kojto 91:031413cf7a89 4173 #define PPI_CHG_CH2_Pos (2UL) /*!< Position of CH2 field. */
Kojto 91:031413cf7a89 4174 #define PPI_CHG_CH2_Msk (0x1UL << PPI_CHG_CH2_Pos) /*!< Bit mask of CH2 field. */
Kojto 91:031413cf7a89 4175 #define PPI_CHG_CH2_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4176 #define PPI_CHG_CH2_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4177
Kojto 91:031413cf7a89 4178 /* Bit 1 : Include CH1 in channel group. */
Kojto 91:031413cf7a89 4179 #define PPI_CHG_CH1_Pos (1UL) /*!< Position of CH1 field. */
Kojto 91:031413cf7a89 4180 #define PPI_CHG_CH1_Msk (0x1UL << PPI_CHG_CH1_Pos) /*!< Bit mask of CH1 field. */
Kojto 91:031413cf7a89 4181 #define PPI_CHG_CH1_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4182 #define PPI_CHG_CH1_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4183
Kojto 91:031413cf7a89 4184 /* Bit 0 : Include CH0 in channel group. */
Kojto 91:031413cf7a89 4185 #define PPI_CHG_CH0_Pos (0UL) /*!< Position of CH0 field. */
Kojto 91:031413cf7a89 4186 #define PPI_CHG_CH0_Msk (0x1UL << PPI_CHG_CH0_Pos) /*!< Bit mask of CH0 field. */
Kojto 91:031413cf7a89 4187 #define PPI_CHG_CH0_Excluded (0UL) /*!< Channel excluded. */
Kojto 91:031413cf7a89 4188 #define PPI_CHG_CH0_Included (1UL) /*!< Channel included. */
Kojto 91:031413cf7a89 4189
Kojto 91:031413cf7a89 4190
Kojto 91:031413cf7a89 4191 /* Peripheral: PU */
Kojto 91:031413cf7a89 4192 /* Description: Patch unit. */
Kojto 91:031413cf7a89 4193
Kojto 91:031413cf7a89 4194 /* Register: PU_PATCHADDR */
Kojto 91:031413cf7a89 4195 /* Description: Relative address of patch instructions. */
Kojto 91:031413cf7a89 4196
Kojto 91:031413cf7a89 4197 /* Bits 24..0 : Relative address of patch instructions. */
Kojto 91:031413cf7a89 4198 #define PU_PATCHADDR_PATCHADDR_Pos (0UL) /*!< Position of PATCHADDR field. */
Kojto 91:031413cf7a89 4199 #define PU_PATCHADDR_PATCHADDR_Msk (0x1FFFFFFUL << PU_PATCHADDR_PATCHADDR_Pos) /*!< Bit mask of PATCHADDR field. */
Kojto 91:031413cf7a89 4200
Kojto 91:031413cf7a89 4201 /* Register: PU_PATCHEN */
Kojto 91:031413cf7a89 4202 /* Description: Patch enable register. */
Kojto 91:031413cf7a89 4203
Kojto 91:031413cf7a89 4204 /* Bit 7 : Patch 7 enabled. */
Kojto 91:031413cf7a89 4205 #define PU_PATCHEN_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
Kojto 91:031413cf7a89 4206 #define PU_PATCHEN_PATCH7_Msk (0x1UL << PU_PATCHEN_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
Kojto 91:031413cf7a89 4207 #define PU_PATCHEN_PATCH7_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4208 #define PU_PATCHEN_PATCH7_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4209
Kojto 91:031413cf7a89 4210 /* Bit 6 : Patch 6 enabled. */
Kojto 91:031413cf7a89 4211 #define PU_PATCHEN_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
Kojto 91:031413cf7a89 4212 #define PU_PATCHEN_PATCH6_Msk (0x1UL << PU_PATCHEN_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
Kojto 91:031413cf7a89 4213 #define PU_PATCHEN_PATCH6_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4214 #define PU_PATCHEN_PATCH6_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4215
Kojto 91:031413cf7a89 4216 /* Bit 5 : Patch 5 enabled. */
Kojto 91:031413cf7a89 4217 #define PU_PATCHEN_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
Kojto 91:031413cf7a89 4218 #define PU_PATCHEN_PATCH5_Msk (0x1UL << PU_PATCHEN_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
Kojto 91:031413cf7a89 4219 #define PU_PATCHEN_PATCH5_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4220 #define PU_PATCHEN_PATCH5_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4221
Kojto 91:031413cf7a89 4222 /* Bit 4 : Patch 4 enabled. */
Kojto 91:031413cf7a89 4223 #define PU_PATCHEN_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
Kojto 91:031413cf7a89 4224 #define PU_PATCHEN_PATCH4_Msk (0x1UL << PU_PATCHEN_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
Kojto 91:031413cf7a89 4225 #define PU_PATCHEN_PATCH4_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4226 #define PU_PATCHEN_PATCH4_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4227
Kojto 91:031413cf7a89 4228 /* Bit 3 : Patch 3 enabled. */
Kojto 91:031413cf7a89 4229 #define PU_PATCHEN_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
Kojto 91:031413cf7a89 4230 #define PU_PATCHEN_PATCH3_Msk (0x1UL << PU_PATCHEN_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
Kojto 91:031413cf7a89 4231 #define PU_PATCHEN_PATCH3_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4232 #define PU_PATCHEN_PATCH3_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4233
Kojto 91:031413cf7a89 4234 /* Bit 2 : Patch 2 enabled. */
Kojto 91:031413cf7a89 4235 #define PU_PATCHEN_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
Kojto 91:031413cf7a89 4236 #define PU_PATCHEN_PATCH2_Msk (0x1UL << PU_PATCHEN_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
Kojto 91:031413cf7a89 4237 #define PU_PATCHEN_PATCH2_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4238 #define PU_PATCHEN_PATCH2_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4239
Kojto 91:031413cf7a89 4240 /* Bit 1 : Patch 1 enabled. */
Kojto 91:031413cf7a89 4241 #define PU_PATCHEN_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
Kojto 91:031413cf7a89 4242 #define PU_PATCHEN_PATCH1_Msk (0x1UL << PU_PATCHEN_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
Kojto 91:031413cf7a89 4243 #define PU_PATCHEN_PATCH1_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4244 #define PU_PATCHEN_PATCH1_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4245
Kojto 91:031413cf7a89 4246 /* Bit 0 : Patch 0 enabled. */
Kojto 91:031413cf7a89 4247 #define PU_PATCHEN_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
Kojto 91:031413cf7a89 4248 #define PU_PATCHEN_PATCH0_Msk (0x1UL << PU_PATCHEN_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
Kojto 91:031413cf7a89 4249 #define PU_PATCHEN_PATCH0_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4250 #define PU_PATCHEN_PATCH0_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4251
Kojto 91:031413cf7a89 4252 /* Register: PU_PATCHENSET */
Kojto 91:031413cf7a89 4253 /* Description: Patch enable register. */
Kojto 91:031413cf7a89 4254
Kojto 91:031413cf7a89 4255 /* Bit 7 : Patch 7 enabled. */
Kojto 91:031413cf7a89 4256 #define PU_PATCHENSET_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
Kojto 91:031413cf7a89 4257 #define PU_PATCHENSET_PATCH7_Msk (0x1UL << PU_PATCHENSET_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
Kojto 91:031413cf7a89 4258 #define PU_PATCHENSET_PATCH7_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4259 #define PU_PATCHENSET_PATCH7_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4260 #define PU_PATCHENSET_PATCH7_Set (1UL) /*!< Enable patch on write. */
Kojto 91:031413cf7a89 4261
Kojto 91:031413cf7a89 4262 /* Bit 6 : Patch 6 enabled. */
Kojto 91:031413cf7a89 4263 #define PU_PATCHENSET_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
Kojto 91:031413cf7a89 4264 #define PU_PATCHENSET_PATCH6_Msk (0x1UL << PU_PATCHENSET_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
Kojto 91:031413cf7a89 4265 #define PU_PATCHENSET_PATCH6_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4266 #define PU_PATCHENSET_PATCH6_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4267 #define PU_PATCHENSET_PATCH6_Set (1UL) /*!< Enable patch on write. */
Kojto 91:031413cf7a89 4268
Kojto 91:031413cf7a89 4269 /* Bit 5 : Patch 5 enabled. */
Kojto 91:031413cf7a89 4270 #define PU_PATCHENSET_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
Kojto 91:031413cf7a89 4271 #define PU_PATCHENSET_PATCH5_Msk (0x1UL << PU_PATCHENSET_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
Kojto 91:031413cf7a89 4272 #define PU_PATCHENSET_PATCH5_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4273 #define PU_PATCHENSET_PATCH5_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4274 #define PU_PATCHENSET_PATCH5_Set (1UL) /*!< Enable patch on write. */
Kojto 91:031413cf7a89 4275
Kojto 91:031413cf7a89 4276 /* Bit 4 : Patch 4 enabled. */
Kojto 91:031413cf7a89 4277 #define PU_PATCHENSET_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
Kojto 91:031413cf7a89 4278 #define PU_PATCHENSET_PATCH4_Msk (0x1UL << PU_PATCHENSET_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
Kojto 91:031413cf7a89 4279 #define PU_PATCHENSET_PATCH4_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4280 #define PU_PATCHENSET_PATCH4_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4281 #define PU_PATCHENSET_PATCH4_Set (1UL) /*!< Enable patch on write. */
Kojto 91:031413cf7a89 4282
Kojto 91:031413cf7a89 4283 /* Bit 3 : Patch 3 enabled. */
Kojto 91:031413cf7a89 4284 #define PU_PATCHENSET_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
Kojto 91:031413cf7a89 4285 #define PU_PATCHENSET_PATCH3_Msk (0x1UL << PU_PATCHENSET_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
Kojto 91:031413cf7a89 4286 #define PU_PATCHENSET_PATCH3_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4287 #define PU_PATCHENSET_PATCH3_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4288 #define PU_PATCHENSET_PATCH3_Set (1UL) /*!< Enable patch on write. */
Kojto 91:031413cf7a89 4289
Kojto 91:031413cf7a89 4290 /* Bit 2 : Patch 2 enabled. */
Kojto 91:031413cf7a89 4291 #define PU_PATCHENSET_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
Kojto 91:031413cf7a89 4292 #define PU_PATCHENSET_PATCH2_Msk (0x1UL << PU_PATCHENSET_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
Kojto 91:031413cf7a89 4293 #define PU_PATCHENSET_PATCH2_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4294 #define PU_PATCHENSET_PATCH2_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4295 #define PU_PATCHENSET_PATCH2_Set (1UL) /*!< Enable patch on write. */
Kojto 91:031413cf7a89 4296
Kojto 91:031413cf7a89 4297 /* Bit 1 : Patch 1 enabled. */
Kojto 91:031413cf7a89 4298 #define PU_PATCHENSET_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
Kojto 91:031413cf7a89 4299 #define PU_PATCHENSET_PATCH1_Msk (0x1UL << PU_PATCHENSET_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
Kojto 91:031413cf7a89 4300 #define PU_PATCHENSET_PATCH1_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4301 #define PU_PATCHENSET_PATCH1_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4302 #define PU_PATCHENSET_PATCH1_Set (1UL) /*!< Enable patch on write. */
Kojto 91:031413cf7a89 4303
Kojto 91:031413cf7a89 4304 /* Bit 0 : Patch 0 enabled. */
Kojto 91:031413cf7a89 4305 #define PU_PATCHENSET_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
Kojto 91:031413cf7a89 4306 #define PU_PATCHENSET_PATCH0_Msk (0x1UL << PU_PATCHENSET_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
Kojto 91:031413cf7a89 4307 #define PU_PATCHENSET_PATCH0_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4308 #define PU_PATCHENSET_PATCH0_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4309 #define PU_PATCHENSET_PATCH0_Set (1UL) /*!< Enable patch on write. */
Kojto 91:031413cf7a89 4310
Kojto 91:031413cf7a89 4311 /* Register: PU_PATCHENCLR */
Kojto 91:031413cf7a89 4312 /* Description: Patch disable register. */
Kojto 91:031413cf7a89 4313
Kojto 91:031413cf7a89 4314 /* Bit 7 : Patch 7 enabled. */
Kojto 91:031413cf7a89 4315 #define PU_PATCHENCLR_PATCH7_Pos (7UL) /*!< Position of PATCH7 field. */
Kojto 91:031413cf7a89 4316 #define PU_PATCHENCLR_PATCH7_Msk (0x1UL << PU_PATCHENCLR_PATCH7_Pos) /*!< Bit mask of PATCH7 field. */
Kojto 91:031413cf7a89 4317 #define PU_PATCHENCLR_PATCH7_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4318 #define PU_PATCHENCLR_PATCH7_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4319 #define PU_PATCHENCLR_PATCH7_Clear (1UL) /*!< Disable patch on write. */
Kojto 91:031413cf7a89 4320
Kojto 91:031413cf7a89 4321 /* Bit 6 : Patch 6 enabled. */
Kojto 91:031413cf7a89 4322 #define PU_PATCHENCLR_PATCH6_Pos (6UL) /*!< Position of PATCH6 field. */
Kojto 91:031413cf7a89 4323 #define PU_PATCHENCLR_PATCH6_Msk (0x1UL << PU_PATCHENCLR_PATCH6_Pos) /*!< Bit mask of PATCH6 field. */
Kojto 91:031413cf7a89 4324 #define PU_PATCHENCLR_PATCH6_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4325 #define PU_PATCHENCLR_PATCH6_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4326 #define PU_PATCHENCLR_PATCH6_Clear (1UL) /*!< Disable patch on write. */
Kojto 91:031413cf7a89 4327
Kojto 91:031413cf7a89 4328 /* Bit 5 : Patch 5 enabled. */
Kojto 91:031413cf7a89 4329 #define PU_PATCHENCLR_PATCH5_Pos (5UL) /*!< Position of PATCH5 field. */
Kojto 91:031413cf7a89 4330 #define PU_PATCHENCLR_PATCH5_Msk (0x1UL << PU_PATCHENCLR_PATCH5_Pos) /*!< Bit mask of PATCH5 field. */
Kojto 91:031413cf7a89 4331 #define PU_PATCHENCLR_PATCH5_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4332 #define PU_PATCHENCLR_PATCH5_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4333 #define PU_PATCHENCLR_PATCH5_Clear (1UL) /*!< Disable patch on write. */
Kojto 91:031413cf7a89 4334
Kojto 91:031413cf7a89 4335 /* Bit 4 : Patch 4 enabled. */
Kojto 91:031413cf7a89 4336 #define PU_PATCHENCLR_PATCH4_Pos (4UL) /*!< Position of PATCH4 field. */
Kojto 91:031413cf7a89 4337 #define PU_PATCHENCLR_PATCH4_Msk (0x1UL << PU_PATCHENCLR_PATCH4_Pos) /*!< Bit mask of PATCH4 field. */
Kojto 91:031413cf7a89 4338 #define PU_PATCHENCLR_PATCH4_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4339 #define PU_PATCHENCLR_PATCH4_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4340 #define PU_PATCHENCLR_PATCH4_Clear (1UL) /*!< Disable patch on write. */
Kojto 91:031413cf7a89 4341
Kojto 91:031413cf7a89 4342 /* Bit 3 : Patch 3 enabled. */
Kojto 91:031413cf7a89 4343 #define PU_PATCHENCLR_PATCH3_Pos (3UL) /*!< Position of PATCH3 field. */
Kojto 91:031413cf7a89 4344 #define PU_PATCHENCLR_PATCH3_Msk (0x1UL << PU_PATCHENCLR_PATCH3_Pos) /*!< Bit mask of PATCH3 field. */
Kojto 91:031413cf7a89 4345 #define PU_PATCHENCLR_PATCH3_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4346 #define PU_PATCHENCLR_PATCH3_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4347 #define PU_PATCHENCLR_PATCH3_Clear (1UL) /*!< Disable patch on write. */
Kojto 91:031413cf7a89 4348
Kojto 91:031413cf7a89 4349 /* Bit 2 : Patch 2 enabled. */
Kojto 91:031413cf7a89 4350 #define PU_PATCHENCLR_PATCH2_Pos (2UL) /*!< Position of PATCH2 field. */
Kojto 91:031413cf7a89 4351 #define PU_PATCHENCLR_PATCH2_Msk (0x1UL << PU_PATCHENCLR_PATCH2_Pos) /*!< Bit mask of PATCH2 field. */
Kojto 91:031413cf7a89 4352 #define PU_PATCHENCLR_PATCH2_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4353 #define PU_PATCHENCLR_PATCH2_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4354 #define PU_PATCHENCLR_PATCH2_Clear (1UL) /*!< Disable patch on write. */
Kojto 91:031413cf7a89 4355
Kojto 91:031413cf7a89 4356 /* Bit 1 : Patch 1 enabled. */
Kojto 91:031413cf7a89 4357 #define PU_PATCHENCLR_PATCH1_Pos (1UL) /*!< Position of PATCH1 field. */
Kojto 91:031413cf7a89 4358 #define PU_PATCHENCLR_PATCH1_Msk (0x1UL << PU_PATCHENCLR_PATCH1_Pos) /*!< Bit mask of PATCH1 field. */
Kojto 91:031413cf7a89 4359 #define PU_PATCHENCLR_PATCH1_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4360 #define PU_PATCHENCLR_PATCH1_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4361 #define PU_PATCHENCLR_PATCH1_Clear (1UL) /*!< Disable patch on write. */
Kojto 91:031413cf7a89 4362
Kojto 91:031413cf7a89 4363 /* Bit 0 : Patch 0 enabled. */
Kojto 91:031413cf7a89 4364 #define PU_PATCHENCLR_PATCH0_Pos (0UL) /*!< Position of PATCH0 field. */
Kojto 91:031413cf7a89 4365 #define PU_PATCHENCLR_PATCH0_Msk (0x1UL << PU_PATCHENCLR_PATCH0_Pos) /*!< Bit mask of PATCH0 field. */
Kojto 91:031413cf7a89 4366 #define PU_PATCHENCLR_PATCH0_Disabled (0UL) /*!< Patch disabled. */
Kojto 91:031413cf7a89 4367 #define PU_PATCHENCLR_PATCH0_Enabled (1UL) /*!< Patch enabled. */
Kojto 91:031413cf7a89 4368 #define PU_PATCHENCLR_PATCH0_Clear (1UL) /*!< Disable patch on write. */
Kojto 91:031413cf7a89 4369
Kojto 91:031413cf7a89 4370
Kojto 91:031413cf7a89 4371 /* Peripheral: QDEC */
Kojto 91:031413cf7a89 4372 /* Description: Rotary decoder. */
Kojto 91:031413cf7a89 4373
Kojto 91:031413cf7a89 4374 /* Register: QDEC_SHORTS */
Kojto 91:031413cf7a89 4375 /* Description: Shortcut for the QDEC. */
Kojto 91:031413cf7a89 4376
Kojto 91:031413cf7a89 4377 /* Bit 1 : Short-cut between SAMPLERDY event and STOP task. */
Kojto 91:031413cf7a89 4378 #define QDEC_SHORTS_SAMPLERDY_STOP_Pos (1UL) /*!< Position of SAMPLERDY_STOP field. */
Kojto 91:031413cf7a89 4379 #define QDEC_SHORTS_SAMPLERDY_STOP_Msk (0x1UL << QDEC_SHORTS_SAMPLERDY_STOP_Pos) /*!< Bit mask of SAMPLERDY_STOP field. */
Kojto 91:031413cf7a89 4380 #define QDEC_SHORTS_SAMPLERDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4381 #define QDEC_SHORTS_SAMPLERDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4382
Kojto 91:031413cf7a89 4383 /* Bit 0 : Short-cut between REPORTRDY event and READCLRACC task. */
Kojto 91:031413cf7a89 4384 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Pos (0UL) /*!< Position of REPORTRDY_READCLRACC field. */
Kojto 91:031413cf7a89 4385 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Msk (0x1UL << QDEC_SHORTS_REPORTRDY_READCLRACC_Pos) /*!< Bit mask of REPORTRDY_READCLRACC field. */
Kojto 91:031413cf7a89 4386 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4387 #define QDEC_SHORTS_REPORTRDY_READCLRACC_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4388
Kojto 91:031413cf7a89 4389 /* Register: QDEC_INTENSET */
Kojto 91:031413cf7a89 4390 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 4391
Kojto 91:031413cf7a89 4392 /* Bit 2 : Enable interrupt on ACCOF event. */
Kojto 91:031413cf7a89 4393 #define QDEC_INTENSET_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
Kojto 91:031413cf7a89 4394 #define QDEC_INTENSET_ACCOF_Msk (0x1UL << QDEC_INTENSET_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
Kojto 91:031413cf7a89 4395 #define QDEC_INTENSET_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4396 #define QDEC_INTENSET_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4397 #define QDEC_INTENSET_ACCOF_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4398
Kojto 91:031413cf7a89 4399 /* Bit 1 : Enable interrupt on REPORTRDY event. */
Kojto 91:031413cf7a89 4400 #define QDEC_INTENSET_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
Kojto 91:031413cf7a89 4401 #define QDEC_INTENSET_REPORTRDY_Msk (0x1UL << QDEC_INTENSET_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
Kojto 91:031413cf7a89 4402 #define QDEC_INTENSET_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4403 #define QDEC_INTENSET_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4404 #define QDEC_INTENSET_REPORTRDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4405
Kojto 91:031413cf7a89 4406 /* Bit 0 : Enable interrupt on SAMPLERDY event. */
Kojto 91:031413cf7a89 4407 #define QDEC_INTENSET_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
Kojto 91:031413cf7a89 4408 #define QDEC_INTENSET_SAMPLERDY_Msk (0x1UL << QDEC_INTENSET_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
Kojto 91:031413cf7a89 4409 #define QDEC_INTENSET_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4410 #define QDEC_INTENSET_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4411 #define QDEC_INTENSET_SAMPLERDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4412
Kojto 91:031413cf7a89 4413 /* Register: QDEC_INTENCLR */
Kojto 91:031413cf7a89 4414 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 4415
Kojto 91:031413cf7a89 4416 /* Bit 2 : Disable interrupt on ACCOF event. */
Kojto 91:031413cf7a89 4417 #define QDEC_INTENCLR_ACCOF_Pos (2UL) /*!< Position of ACCOF field. */
Kojto 91:031413cf7a89 4418 #define QDEC_INTENCLR_ACCOF_Msk (0x1UL << QDEC_INTENCLR_ACCOF_Pos) /*!< Bit mask of ACCOF field. */
Kojto 91:031413cf7a89 4419 #define QDEC_INTENCLR_ACCOF_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4420 #define QDEC_INTENCLR_ACCOF_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4421 #define QDEC_INTENCLR_ACCOF_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4422
Kojto 91:031413cf7a89 4423 /* Bit 1 : Disable interrupt on REPORTRDY event. */
Kojto 91:031413cf7a89 4424 #define QDEC_INTENCLR_REPORTRDY_Pos (1UL) /*!< Position of REPORTRDY field. */
Kojto 91:031413cf7a89 4425 #define QDEC_INTENCLR_REPORTRDY_Msk (0x1UL << QDEC_INTENCLR_REPORTRDY_Pos) /*!< Bit mask of REPORTRDY field. */
Kojto 91:031413cf7a89 4426 #define QDEC_INTENCLR_REPORTRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4427 #define QDEC_INTENCLR_REPORTRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4428 #define QDEC_INTENCLR_REPORTRDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4429
Kojto 91:031413cf7a89 4430 /* Bit 0 : Disable interrupt on SAMPLERDY event. */
Kojto 91:031413cf7a89 4431 #define QDEC_INTENCLR_SAMPLERDY_Pos (0UL) /*!< Position of SAMPLERDY field. */
Kojto 91:031413cf7a89 4432 #define QDEC_INTENCLR_SAMPLERDY_Msk (0x1UL << QDEC_INTENCLR_SAMPLERDY_Pos) /*!< Bit mask of SAMPLERDY field. */
Kojto 91:031413cf7a89 4433 #define QDEC_INTENCLR_SAMPLERDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4434 #define QDEC_INTENCLR_SAMPLERDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4435 #define QDEC_INTENCLR_SAMPLERDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4436
Kojto 91:031413cf7a89 4437 /* Register: QDEC_ENABLE */
Kojto 91:031413cf7a89 4438 /* Description: Enable the QDEC. */
Kojto 91:031413cf7a89 4439
Kojto 91:031413cf7a89 4440 /* Bit 0 : Enable or disable QDEC. */
Kojto 91:031413cf7a89 4441 #define QDEC_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 4442 #define QDEC_ENABLE_ENABLE_Msk (0x1UL << QDEC_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 4443 #define QDEC_ENABLE_ENABLE_Disabled (0UL) /*!< Disabled QDEC. */
Kojto 91:031413cf7a89 4444 #define QDEC_ENABLE_ENABLE_Enabled (1UL) /*!< Enable QDEC. */
Kojto 91:031413cf7a89 4445
Kojto 91:031413cf7a89 4446 /* Register: QDEC_LEDPOL */
Kojto 91:031413cf7a89 4447 /* Description: LED output pin polarity. */
Kojto 91:031413cf7a89 4448
Kojto 91:031413cf7a89 4449 /* Bit 0 : LED output pin polarity. */
Kojto 91:031413cf7a89 4450 #define QDEC_LEDPOL_LEDPOL_Pos (0UL) /*!< Position of LEDPOL field. */
Kojto 91:031413cf7a89 4451 #define QDEC_LEDPOL_LEDPOL_Msk (0x1UL << QDEC_LEDPOL_LEDPOL_Pos) /*!< Bit mask of LEDPOL field. */
Kojto 91:031413cf7a89 4452 #define QDEC_LEDPOL_LEDPOL_ActiveLow (0UL) /*!< LED output is active low. */
Kojto 91:031413cf7a89 4453 #define QDEC_LEDPOL_LEDPOL_ActiveHigh (1UL) /*!< LED output is active high. */
Kojto 91:031413cf7a89 4454
Kojto 91:031413cf7a89 4455 /* Register: QDEC_SAMPLEPER */
Kojto 91:031413cf7a89 4456 /* Description: Sample period. */
Kojto 91:031413cf7a89 4457
Kojto 91:031413cf7a89 4458 /* Bits 2..0 : Sample period. */
Kojto 91:031413cf7a89 4459 #define QDEC_SAMPLEPER_SAMPLEPER_Pos (0UL) /*!< Position of SAMPLEPER field. */
Kojto 91:031413cf7a89 4460 #define QDEC_SAMPLEPER_SAMPLEPER_Msk (0x7UL << QDEC_SAMPLEPER_SAMPLEPER_Pos) /*!< Bit mask of SAMPLEPER field. */
Kojto 91:031413cf7a89 4461 #define QDEC_SAMPLEPER_SAMPLEPER_128us (0x00UL) /*!< 128us sample period. */
Kojto 91:031413cf7a89 4462 #define QDEC_SAMPLEPER_SAMPLEPER_256us (0x01UL) /*!< 256us sample period. */
Kojto 91:031413cf7a89 4463 #define QDEC_SAMPLEPER_SAMPLEPER_512us (0x02UL) /*!< 512us sample period. */
Kojto 91:031413cf7a89 4464 #define QDEC_SAMPLEPER_SAMPLEPER_1024us (0x03UL) /*!< 1024us sample period. */
Kojto 91:031413cf7a89 4465 #define QDEC_SAMPLEPER_SAMPLEPER_2048us (0x04UL) /*!< 2048us sample period. */
Kojto 91:031413cf7a89 4466 #define QDEC_SAMPLEPER_SAMPLEPER_4096us (0x05UL) /*!< 4096us sample period. */
Kojto 91:031413cf7a89 4467 #define QDEC_SAMPLEPER_SAMPLEPER_8192us (0x06UL) /*!< 8192us sample period. */
Kojto 91:031413cf7a89 4468 #define QDEC_SAMPLEPER_SAMPLEPER_16384us (0x07UL) /*!< 16384us sample period. */
Kojto 91:031413cf7a89 4469
Kojto 91:031413cf7a89 4470 /* Register: QDEC_SAMPLE */
Kojto 91:031413cf7a89 4471 /* Description: Motion sample value. */
Kojto 91:031413cf7a89 4472
Kojto 91:031413cf7a89 4473 /* Bits 31..0 : Last sample taken in compliment to 2. */
Kojto 91:031413cf7a89 4474 #define QDEC_SAMPLE_SAMPLE_Pos (0UL) /*!< Position of SAMPLE field. */
Kojto 91:031413cf7a89 4475 #define QDEC_SAMPLE_SAMPLE_Msk (0xFFFFFFFFUL << QDEC_SAMPLE_SAMPLE_Pos) /*!< Bit mask of SAMPLE field. */
Kojto 91:031413cf7a89 4476
Kojto 91:031413cf7a89 4477 /* Register: QDEC_REPORTPER */
Kojto 91:031413cf7a89 4478 /* Description: Number of samples to generate an EVENT_REPORTRDY. */
Kojto 91:031413cf7a89 4479
Kojto 91:031413cf7a89 4480 /* Bits 2..0 : Number of samples to generate an EVENT_REPORTRDY. */
Kojto 91:031413cf7a89 4481 #define QDEC_REPORTPER_REPORTPER_Pos (0UL) /*!< Position of REPORTPER field. */
Kojto 91:031413cf7a89 4482 #define QDEC_REPORTPER_REPORTPER_Msk (0x7UL << QDEC_REPORTPER_REPORTPER_Pos) /*!< Bit mask of REPORTPER field. */
Kojto 91:031413cf7a89 4483 #define QDEC_REPORTPER_REPORTPER_10Smpl (0x00UL) /*!< 10 samples per report. */
Kojto 91:031413cf7a89 4484 #define QDEC_REPORTPER_REPORTPER_40Smpl (0x01UL) /*!< 40 samples per report. */
Kojto 91:031413cf7a89 4485 #define QDEC_REPORTPER_REPORTPER_80Smpl (0x02UL) /*!< 80 samples per report. */
Kojto 91:031413cf7a89 4486 #define QDEC_REPORTPER_REPORTPER_120Smpl (0x03UL) /*!< 120 samples per report. */
Kojto 91:031413cf7a89 4487 #define QDEC_REPORTPER_REPORTPER_160Smpl (0x04UL) /*!< 160 samples per report. */
Kojto 91:031413cf7a89 4488 #define QDEC_REPORTPER_REPORTPER_200Smpl (0x05UL) /*!< 200 samples per report. */
Kojto 91:031413cf7a89 4489 #define QDEC_REPORTPER_REPORTPER_240Smpl (0x06UL) /*!< 240 samples per report. */
Kojto 91:031413cf7a89 4490 #define QDEC_REPORTPER_REPORTPER_280Smpl (0x07UL) /*!< 280 samples per report. */
Kojto 91:031413cf7a89 4491
Kojto 91:031413cf7a89 4492 /* Register: QDEC_DBFEN */
Kojto 91:031413cf7a89 4493 /* Description: Enable debouncer input filters. */
Kojto 91:031413cf7a89 4494
Kojto 91:031413cf7a89 4495 /* Bit 0 : Enable debounce input filters. */
Kojto 91:031413cf7a89 4496 #define QDEC_DBFEN_DBFEN_Pos (0UL) /*!< Position of DBFEN field. */
Kojto 91:031413cf7a89 4497 #define QDEC_DBFEN_DBFEN_Msk (0x1UL << QDEC_DBFEN_DBFEN_Pos) /*!< Bit mask of DBFEN field. */
Kojto 91:031413cf7a89 4498 #define QDEC_DBFEN_DBFEN_Disabled (0UL) /*!< Debounce input filters disabled. */
Kojto 91:031413cf7a89 4499 #define QDEC_DBFEN_DBFEN_Enabled (1UL) /*!< Debounce input filters enabled. */
Kojto 91:031413cf7a89 4500
Kojto 91:031413cf7a89 4501 /* Register: QDEC_LEDPRE */
Kojto 91:031413cf7a89 4502 /* Description: Time LED is switched ON before the sample. */
Kojto 91:031413cf7a89 4503
Kojto 91:031413cf7a89 4504 /* Bits 7..0 : Period in us the LED in switched on prior to sampling. */
Kojto 91:031413cf7a89 4505 #define QDEC_LEDPRE_LEDPRE_Pos (0UL) /*!< Position of LEDPRE field. */
Kojto 91:031413cf7a89 4506 #define QDEC_LEDPRE_LEDPRE_Msk (0xFFUL << QDEC_LEDPRE_LEDPRE_Pos) /*!< Bit mask of LEDPRE field. */
Kojto 91:031413cf7a89 4507
Kojto 91:031413cf7a89 4508 /* Register: QDEC_ACCDBL */
Kojto 91:031413cf7a89 4509 /* Description: Accumulated double (error) transitions register. */
Kojto 91:031413cf7a89 4510
Kojto 91:031413cf7a89 4511 /* Bits 3..0 : Accumulated double (error) transitions. */
Kojto 91:031413cf7a89 4512 #define QDEC_ACCDBL_ACCDBL_Pos (0UL) /*!< Position of ACCDBL field. */
Kojto 91:031413cf7a89 4513 #define QDEC_ACCDBL_ACCDBL_Msk (0xFUL << QDEC_ACCDBL_ACCDBL_Pos) /*!< Bit mask of ACCDBL field. */
Kojto 91:031413cf7a89 4514
Kojto 91:031413cf7a89 4515 /* Register: QDEC_ACCDBLREAD */
Kojto 91:031413cf7a89 4516 /* Description: Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC task. */
Kojto 91:031413cf7a89 4517
Kojto 91:031413cf7a89 4518 /* Bits 3..0 : Snapshot of accumulated double (error) transitions. */
Kojto 91:031413cf7a89 4519 #define QDEC_ACCDBLREAD_ACCDBLREAD_Pos (0UL) /*!< Position of ACCDBLREAD field. */
Kojto 91:031413cf7a89 4520 #define QDEC_ACCDBLREAD_ACCDBLREAD_Msk (0xFUL << QDEC_ACCDBLREAD_ACCDBLREAD_Pos) /*!< Bit mask of ACCDBLREAD field. */
Kojto 91:031413cf7a89 4521
Kojto 91:031413cf7a89 4522 /* Register: QDEC_POWER */
Kojto 91:031413cf7a89 4523 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 4524
Kojto 91:031413cf7a89 4525 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 4526 #define QDEC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 4527 #define QDEC_POWER_POWER_Msk (0x1UL << QDEC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 4528 #define QDEC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 4529 #define QDEC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 4530
Kojto 91:031413cf7a89 4531
Kojto 91:031413cf7a89 4532 /* Peripheral: RADIO */
Kojto 91:031413cf7a89 4533 /* Description: The radio. */
Kojto 91:031413cf7a89 4534
Kojto 91:031413cf7a89 4535 /* Register: RADIO_SHORTS */
Kojto 91:031413cf7a89 4536 /* Description: Shortcut for the radio. */
Kojto 91:031413cf7a89 4537
Kojto 91:031413cf7a89 4538 /* Bit 8 : Shortcut between DISABLED event and RSSISTOP task. */
Kojto 91:031413cf7a89 4539 #define RADIO_SHORTS_DISABLED_RSSISTOP_Pos (8UL) /*!< Position of DISABLED_RSSISTOP field. */
Kojto 91:031413cf7a89 4540 #define RADIO_SHORTS_DISABLED_RSSISTOP_Msk (0x1UL << RADIO_SHORTS_DISABLED_RSSISTOP_Pos) /*!< Bit mask of DISABLED_RSSISTOP field. */
Kojto 91:031413cf7a89 4541 #define RADIO_SHORTS_DISABLED_RSSISTOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4542 #define RADIO_SHORTS_DISABLED_RSSISTOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4543
Kojto 91:031413cf7a89 4544 /* Bit 6 : Shortcut between ADDRESS event and BCSTART task. */
Kojto 91:031413cf7a89 4545 #define RADIO_SHORTS_ADDRESS_BCSTART_Pos (6UL) /*!< Position of ADDRESS_BCSTART field. */
Kojto 91:031413cf7a89 4546 #define RADIO_SHORTS_ADDRESS_BCSTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_BCSTART_Pos) /*!< Bit mask of ADDRESS_BCSTART field. */
Kojto 91:031413cf7a89 4547 #define RADIO_SHORTS_ADDRESS_BCSTART_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4548 #define RADIO_SHORTS_ADDRESS_BCSTART_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4549
Kojto 91:031413cf7a89 4550 /* Bit 5 : Shortcut between END event and START task. */
Kojto 91:031413cf7a89 4551 #define RADIO_SHORTS_END_START_Pos (5UL) /*!< Position of END_START field. */
Kojto 91:031413cf7a89 4552 #define RADIO_SHORTS_END_START_Msk (0x1UL << RADIO_SHORTS_END_START_Pos) /*!< Bit mask of END_START field. */
Kojto 91:031413cf7a89 4553 #define RADIO_SHORTS_END_START_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4554 #define RADIO_SHORTS_END_START_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4555
Kojto 91:031413cf7a89 4556 /* Bit 4 : Shortcut between ADDRESS event and RSSISTART task. */
Kojto 91:031413cf7a89 4557 #define RADIO_SHORTS_ADDRESS_RSSISTART_Pos (4UL) /*!< Position of ADDRESS_RSSISTART field. */
Kojto 91:031413cf7a89 4558 #define RADIO_SHORTS_ADDRESS_RSSISTART_Msk (0x1UL << RADIO_SHORTS_ADDRESS_RSSISTART_Pos) /*!< Bit mask of ADDRESS_RSSISTART field. */
Kojto 91:031413cf7a89 4559 #define RADIO_SHORTS_ADDRESS_RSSISTART_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4560 #define RADIO_SHORTS_ADDRESS_RSSISTART_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4561
Kojto 91:031413cf7a89 4562 /* Bit 3 : Shortcut between DISABLED event and RXEN task. */
Kojto 91:031413cf7a89 4563 #define RADIO_SHORTS_DISABLED_RXEN_Pos (3UL) /*!< Position of DISABLED_RXEN field. */
Kojto 91:031413cf7a89 4564 #define RADIO_SHORTS_DISABLED_RXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_RXEN_Pos) /*!< Bit mask of DISABLED_RXEN field. */
Kojto 91:031413cf7a89 4565 #define RADIO_SHORTS_DISABLED_RXEN_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4566 #define RADIO_SHORTS_DISABLED_RXEN_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4567
Kojto 91:031413cf7a89 4568 /* Bit 2 : Shortcut between DISABLED event and TXEN task. */
Kojto 91:031413cf7a89 4569 #define RADIO_SHORTS_DISABLED_TXEN_Pos (2UL) /*!< Position of DISABLED_TXEN field. */
Kojto 91:031413cf7a89 4570 #define RADIO_SHORTS_DISABLED_TXEN_Msk (0x1UL << RADIO_SHORTS_DISABLED_TXEN_Pos) /*!< Bit mask of DISABLED_TXEN field. */
Kojto 91:031413cf7a89 4571 #define RADIO_SHORTS_DISABLED_TXEN_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4572 #define RADIO_SHORTS_DISABLED_TXEN_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4573
Kojto 91:031413cf7a89 4574 /* Bit 1 : Shortcut between END event and DISABLE task. */
Kojto 91:031413cf7a89 4575 #define RADIO_SHORTS_END_DISABLE_Pos (1UL) /*!< Position of END_DISABLE field. */
Kojto 91:031413cf7a89 4576 #define RADIO_SHORTS_END_DISABLE_Msk (0x1UL << RADIO_SHORTS_END_DISABLE_Pos) /*!< Bit mask of END_DISABLE field. */
Kojto 91:031413cf7a89 4577 #define RADIO_SHORTS_END_DISABLE_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4578 #define RADIO_SHORTS_END_DISABLE_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4579
Kojto 91:031413cf7a89 4580 /* Bit 0 : Shortcut between READY event and START task. */
Kojto 91:031413cf7a89 4581 #define RADIO_SHORTS_READY_START_Pos (0UL) /*!< Position of READY_START field. */
Kojto 91:031413cf7a89 4582 #define RADIO_SHORTS_READY_START_Msk (0x1UL << RADIO_SHORTS_READY_START_Pos) /*!< Bit mask of READY_START field. */
Kojto 91:031413cf7a89 4583 #define RADIO_SHORTS_READY_START_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 4584 #define RADIO_SHORTS_READY_START_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 4585
Kojto 91:031413cf7a89 4586 /* Register: RADIO_INTENSET */
Kojto 91:031413cf7a89 4587 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 4588
Kojto 91:031413cf7a89 4589 /* Bit 10 : Enable interrupt on BCMATCH event. */
Kojto 91:031413cf7a89 4590 #define RADIO_INTENSET_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
Kojto 91:031413cf7a89 4591 #define RADIO_INTENSET_BCMATCH_Msk (0x1UL << RADIO_INTENSET_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
Kojto 91:031413cf7a89 4592 #define RADIO_INTENSET_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4593 #define RADIO_INTENSET_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4594 #define RADIO_INTENSET_BCMATCH_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4595
Kojto 91:031413cf7a89 4596 /* Bit 7 : Enable interrupt on RSSIEND event. */
Kojto 91:031413cf7a89 4597 #define RADIO_INTENSET_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
Kojto 91:031413cf7a89 4598 #define RADIO_INTENSET_RSSIEND_Msk (0x1UL << RADIO_INTENSET_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
Kojto 91:031413cf7a89 4599 #define RADIO_INTENSET_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4600 #define RADIO_INTENSET_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4601 #define RADIO_INTENSET_RSSIEND_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4602
Kojto 91:031413cf7a89 4603 /* Bit 6 : Enable interrupt on DEVMISS event. */
Kojto 91:031413cf7a89 4604 #define RADIO_INTENSET_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
Kojto 91:031413cf7a89 4605 #define RADIO_INTENSET_DEVMISS_Msk (0x1UL << RADIO_INTENSET_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
Kojto 91:031413cf7a89 4606 #define RADIO_INTENSET_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4607 #define RADIO_INTENSET_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4608 #define RADIO_INTENSET_DEVMISS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4609
Kojto 91:031413cf7a89 4610 /* Bit 5 : Enable interrupt on DEVMATCH event. */
Kojto 91:031413cf7a89 4611 #define RADIO_INTENSET_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
Kojto 91:031413cf7a89 4612 #define RADIO_INTENSET_DEVMATCH_Msk (0x1UL << RADIO_INTENSET_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
Kojto 91:031413cf7a89 4613 #define RADIO_INTENSET_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4614 #define RADIO_INTENSET_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4615 #define RADIO_INTENSET_DEVMATCH_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4616
Kojto 91:031413cf7a89 4617 /* Bit 4 : Enable interrupt on DISABLED event. */
Kojto 91:031413cf7a89 4618 #define RADIO_INTENSET_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
Kojto 91:031413cf7a89 4619 #define RADIO_INTENSET_DISABLED_Msk (0x1UL << RADIO_INTENSET_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
Kojto 91:031413cf7a89 4620 #define RADIO_INTENSET_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4621 #define RADIO_INTENSET_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4622 #define RADIO_INTENSET_DISABLED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4623
Kojto 91:031413cf7a89 4624 /* Bit 3 : Enable interrupt on END event. */
Kojto 91:031413cf7a89 4625 #define RADIO_INTENSET_END_Pos (3UL) /*!< Position of END field. */
Kojto 91:031413cf7a89 4626 #define RADIO_INTENSET_END_Msk (0x1UL << RADIO_INTENSET_END_Pos) /*!< Bit mask of END field. */
Kojto 91:031413cf7a89 4627 #define RADIO_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4628 #define RADIO_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4629 #define RADIO_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4630
Kojto 91:031413cf7a89 4631 /* Bit 2 : Enable interrupt on PAYLOAD event. */
Kojto 91:031413cf7a89 4632 #define RADIO_INTENSET_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
Kojto 91:031413cf7a89 4633 #define RADIO_INTENSET_PAYLOAD_Msk (0x1UL << RADIO_INTENSET_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
Kojto 91:031413cf7a89 4634 #define RADIO_INTENSET_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4635 #define RADIO_INTENSET_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4636 #define RADIO_INTENSET_PAYLOAD_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4637
Kojto 91:031413cf7a89 4638 /* Bit 1 : Enable interrupt on ADDRESS event. */
Kojto 91:031413cf7a89 4639 #define RADIO_INTENSET_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
Kojto 91:031413cf7a89 4640 #define RADIO_INTENSET_ADDRESS_Msk (0x1UL << RADIO_INTENSET_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Kojto 91:031413cf7a89 4641 #define RADIO_INTENSET_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4642 #define RADIO_INTENSET_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4643 #define RADIO_INTENSET_ADDRESS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4644
Kojto 91:031413cf7a89 4645 /* Bit 0 : Enable interrupt on READY event. */
Kojto 91:031413cf7a89 4646 #define RADIO_INTENSET_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 91:031413cf7a89 4647 #define RADIO_INTENSET_READY_Msk (0x1UL << RADIO_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Kojto 91:031413cf7a89 4648 #define RADIO_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4649 #define RADIO_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4650 #define RADIO_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 4651
Kojto 91:031413cf7a89 4652 /* Register: RADIO_INTENCLR */
Kojto 91:031413cf7a89 4653 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 4654
Kojto 91:031413cf7a89 4655 /* Bit 10 : Disable interrupt on BCMATCH event. */
Kojto 91:031413cf7a89 4656 #define RADIO_INTENCLR_BCMATCH_Pos (10UL) /*!< Position of BCMATCH field. */
Kojto 91:031413cf7a89 4657 #define RADIO_INTENCLR_BCMATCH_Msk (0x1UL << RADIO_INTENCLR_BCMATCH_Pos) /*!< Bit mask of BCMATCH field. */
Kojto 91:031413cf7a89 4658 #define RADIO_INTENCLR_BCMATCH_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4659 #define RADIO_INTENCLR_BCMATCH_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4660 #define RADIO_INTENCLR_BCMATCH_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4661
Kojto 91:031413cf7a89 4662 /* Bit 7 : Disable interrupt on RSSIEND event. */
Kojto 91:031413cf7a89 4663 #define RADIO_INTENCLR_RSSIEND_Pos (7UL) /*!< Position of RSSIEND field. */
Kojto 91:031413cf7a89 4664 #define RADIO_INTENCLR_RSSIEND_Msk (0x1UL << RADIO_INTENCLR_RSSIEND_Pos) /*!< Bit mask of RSSIEND field. */
Kojto 91:031413cf7a89 4665 #define RADIO_INTENCLR_RSSIEND_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4666 #define RADIO_INTENCLR_RSSIEND_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4667 #define RADIO_INTENCLR_RSSIEND_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4668
Kojto 91:031413cf7a89 4669 /* Bit 6 : Disable interrupt on DEVMISS event. */
Kojto 91:031413cf7a89 4670 #define RADIO_INTENCLR_DEVMISS_Pos (6UL) /*!< Position of DEVMISS field. */
Kojto 91:031413cf7a89 4671 #define RADIO_INTENCLR_DEVMISS_Msk (0x1UL << RADIO_INTENCLR_DEVMISS_Pos) /*!< Bit mask of DEVMISS field. */
Kojto 91:031413cf7a89 4672 #define RADIO_INTENCLR_DEVMISS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4673 #define RADIO_INTENCLR_DEVMISS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4674 #define RADIO_INTENCLR_DEVMISS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4675
Kojto 91:031413cf7a89 4676 /* Bit 5 : Disable interrupt on DEVMATCH event. */
Kojto 91:031413cf7a89 4677 #define RADIO_INTENCLR_DEVMATCH_Pos (5UL) /*!< Position of DEVMATCH field. */
Kojto 91:031413cf7a89 4678 #define RADIO_INTENCLR_DEVMATCH_Msk (0x1UL << RADIO_INTENCLR_DEVMATCH_Pos) /*!< Bit mask of DEVMATCH field. */
Kojto 91:031413cf7a89 4679 #define RADIO_INTENCLR_DEVMATCH_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4680 #define RADIO_INTENCLR_DEVMATCH_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4681 #define RADIO_INTENCLR_DEVMATCH_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4682
Kojto 91:031413cf7a89 4683 /* Bit 4 : Disable interrupt on DISABLED event. */
Kojto 91:031413cf7a89 4684 #define RADIO_INTENCLR_DISABLED_Pos (4UL) /*!< Position of DISABLED field. */
Kojto 91:031413cf7a89 4685 #define RADIO_INTENCLR_DISABLED_Msk (0x1UL << RADIO_INTENCLR_DISABLED_Pos) /*!< Bit mask of DISABLED field. */
Kojto 91:031413cf7a89 4686 #define RADIO_INTENCLR_DISABLED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4687 #define RADIO_INTENCLR_DISABLED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4688 #define RADIO_INTENCLR_DISABLED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4689
Kojto 91:031413cf7a89 4690 /* Bit 3 : Disable interrupt on END event. */
Kojto 91:031413cf7a89 4691 #define RADIO_INTENCLR_END_Pos (3UL) /*!< Position of END field. */
Kojto 91:031413cf7a89 4692 #define RADIO_INTENCLR_END_Msk (0x1UL << RADIO_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Kojto 91:031413cf7a89 4693 #define RADIO_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4694 #define RADIO_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4695 #define RADIO_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4696
Kojto 91:031413cf7a89 4697 /* Bit 2 : Disable interrupt on PAYLOAD event. */
Kojto 91:031413cf7a89 4698 #define RADIO_INTENCLR_PAYLOAD_Pos (2UL) /*!< Position of PAYLOAD field. */
Kojto 91:031413cf7a89 4699 #define RADIO_INTENCLR_PAYLOAD_Msk (0x1UL << RADIO_INTENCLR_PAYLOAD_Pos) /*!< Bit mask of PAYLOAD field. */
Kojto 91:031413cf7a89 4700 #define RADIO_INTENCLR_PAYLOAD_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4701 #define RADIO_INTENCLR_PAYLOAD_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4702 #define RADIO_INTENCLR_PAYLOAD_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4703
Kojto 91:031413cf7a89 4704 /* Bit 1 : Disable interrupt on ADDRESS event. */
Kojto 91:031413cf7a89 4705 #define RADIO_INTENCLR_ADDRESS_Pos (1UL) /*!< Position of ADDRESS field. */
Kojto 91:031413cf7a89 4706 #define RADIO_INTENCLR_ADDRESS_Msk (0x1UL << RADIO_INTENCLR_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Kojto 91:031413cf7a89 4707 #define RADIO_INTENCLR_ADDRESS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4708 #define RADIO_INTENCLR_ADDRESS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4709 #define RADIO_INTENCLR_ADDRESS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4710
Kojto 91:031413cf7a89 4711 /* Bit 0 : Disable interrupt on READY event. */
Kojto 91:031413cf7a89 4712 #define RADIO_INTENCLR_READY_Pos (0UL) /*!< Position of READY field. */
Kojto 91:031413cf7a89 4713 #define RADIO_INTENCLR_READY_Msk (0x1UL << RADIO_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Kojto 91:031413cf7a89 4714 #define RADIO_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 4715 #define RADIO_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 4716 #define RADIO_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 4717
Kojto 91:031413cf7a89 4718 /* Register: RADIO_CRCSTATUS */
Kojto 91:031413cf7a89 4719 /* Description: CRC status of received packet. */
Kojto 91:031413cf7a89 4720
Kojto 91:031413cf7a89 4721 /* Bit 0 : CRC status of received packet. */
Kojto 91:031413cf7a89 4722 #define RADIO_CRCSTATUS_CRCSTATUS_Pos (0UL) /*!< Position of CRCSTATUS field. */
Kojto 91:031413cf7a89 4723 #define RADIO_CRCSTATUS_CRCSTATUS_Msk (0x1UL << RADIO_CRCSTATUS_CRCSTATUS_Pos) /*!< Bit mask of CRCSTATUS field. */
Kojto 91:031413cf7a89 4724 #define RADIO_CRCSTATUS_CRCSTATUS_CRCError (0UL) /*!< Packet received with CRC error. */
Kojto 91:031413cf7a89 4725 #define RADIO_CRCSTATUS_CRCSTATUS_CRCOk (1UL) /*!< Packet received with CRC ok. */
Kojto 91:031413cf7a89 4726
Kojto 91:031413cf7a89 4727 /* Register: RADIO_RXMATCH */
Kojto 91:031413cf7a89 4728 /* Description: Received address. */
Kojto 91:031413cf7a89 4729
Kojto 91:031413cf7a89 4730 /* Bits 2..0 : Logical address in which previous packet was received. */
Kojto 91:031413cf7a89 4731 #define RADIO_RXMATCH_RXMATCH_Pos (0UL) /*!< Position of RXMATCH field. */
Kojto 91:031413cf7a89 4732 #define RADIO_RXMATCH_RXMATCH_Msk (0x7UL << RADIO_RXMATCH_RXMATCH_Pos) /*!< Bit mask of RXMATCH field. */
Kojto 91:031413cf7a89 4733
Kojto 91:031413cf7a89 4734 /* Register: RADIO_RXCRC */
Kojto 91:031413cf7a89 4735 /* Description: Received CRC. */
Kojto 91:031413cf7a89 4736
Kojto 91:031413cf7a89 4737 /* Bits 23..0 : CRC field of previously received packet. */
Kojto 91:031413cf7a89 4738 #define RADIO_RXCRC_RXCRC_Pos (0UL) /*!< Position of RXCRC field. */
Kojto 91:031413cf7a89 4739 #define RADIO_RXCRC_RXCRC_Msk (0xFFFFFFUL << RADIO_RXCRC_RXCRC_Pos) /*!< Bit mask of RXCRC field. */
Kojto 91:031413cf7a89 4740
Kojto 91:031413cf7a89 4741 /* Register: RADIO_DAI */
Kojto 91:031413cf7a89 4742 /* Description: Device address match index. */
Kojto 91:031413cf7a89 4743
Kojto 91:031413cf7a89 4744 /* Bits 2..0 : Index (n) of device address (see DAB[n] and DAP[n]) that got an address match. */
Kojto 91:031413cf7a89 4745 #define RADIO_DAI_DAI_Pos (0UL) /*!< Position of DAI field. */
Kojto 91:031413cf7a89 4746 #define RADIO_DAI_DAI_Msk (0x7UL << RADIO_DAI_DAI_Pos) /*!< Bit mask of DAI field. */
Kojto 91:031413cf7a89 4747
Kojto 91:031413cf7a89 4748 /* Register: RADIO_FREQUENCY */
Kojto 91:031413cf7a89 4749 /* Description: Frequency. */
Kojto 91:031413cf7a89 4750
Kojto 91:031413cf7a89 4751 /* Bits 6..0 : Radio channel frequency offset in MHz: RF Frequency = 2400 + FREQUENCY (MHz). Decision point: TXEN or RXEN task. */
Kojto 91:031413cf7a89 4752 #define RADIO_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Kojto 91:031413cf7a89 4753 #define RADIO_FREQUENCY_FREQUENCY_Msk (0x7FUL << RADIO_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Kojto 91:031413cf7a89 4754
Kojto 91:031413cf7a89 4755 /* Register: RADIO_TXPOWER */
Kojto 91:031413cf7a89 4756 /* Description: Output power. */
Kojto 91:031413cf7a89 4757
Kojto 91:031413cf7a89 4758 /* Bits 7..0 : Radio output power. Decision point: TXEN task. */
Kojto 91:031413cf7a89 4759 #define RADIO_TXPOWER_TXPOWER_Pos (0UL) /*!< Position of TXPOWER field. */
Kojto 91:031413cf7a89 4760 #define RADIO_TXPOWER_TXPOWER_Msk (0xFFUL << RADIO_TXPOWER_TXPOWER_Pos) /*!< Bit mask of TXPOWER field. */
Kojto 91:031413cf7a89 4761 #define RADIO_TXPOWER_TXPOWER_Pos4dBm (0x04UL) /*!< +4dBm. */
Kojto 91:031413cf7a89 4762 #define RADIO_TXPOWER_TXPOWER_0dBm (0x00UL) /*!< 0dBm. */
Kojto 91:031413cf7a89 4763 #define RADIO_TXPOWER_TXPOWER_Neg4dBm (0xFCUL) /*!< -4dBm. */
Kojto 91:031413cf7a89 4764 #define RADIO_TXPOWER_TXPOWER_Neg8dBm (0xF8UL) /*!< -8dBm. */
Kojto 91:031413cf7a89 4765 #define RADIO_TXPOWER_TXPOWER_Neg12dBm (0xF4UL) /*!< -12dBm. */
Kojto 91:031413cf7a89 4766 #define RADIO_TXPOWER_TXPOWER_Neg16dBm (0xF0UL) /*!< -16dBm. */
Kojto 91:031413cf7a89 4767 #define RADIO_TXPOWER_TXPOWER_Neg20dBm (0xECUL) /*!< -20dBm. */
Kojto 91:031413cf7a89 4768 #define RADIO_TXPOWER_TXPOWER_Neg30dBm (0xD8UL) /*!< -30dBm. */
Kojto 91:031413cf7a89 4769
Kojto 91:031413cf7a89 4770 /* Register: RADIO_MODE */
Kojto 91:031413cf7a89 4771 /* Description: Data rate and modulation. */
Kojto 91:031413cf7a89 4772
Kojto 91:031413cf7a89 4773 /* Bits 1..0 : Radio data rate and modulation setting. Decision point: TXEN or RXEN task. */
Kojto 91:031413cf7a89 4774 #define RADIO_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Kojto 91:031413cf7a89 4775 #define RADIO_MODE_MODE_Msk (0x3UL << RADIO_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Kojto 91:031413cf7a89 4776 #define RADIO_MODE_MODE_Nrf_1Mbit (0x00UL) /*!< 1Mbit/s Nordic propietary radio mode. */
Kojto 91:031413cf7a89 4777 #define RADIO_MODE_MODE_Nrf_2Mbit (0x01UL) /*!< 2Mbit/s Nordic propietary radio mode. */
Kojto 91:031413cf7a89 4778 #define RADIO_MODE_MODE_Nrf_250Kbit (0x02UL) /*!< 250kbit/s Nordic propietary radio mode. */
Kojto 91:031413cf7a89 4779 #define RADIO_MODE_MODE_Ble_1Mbit (0x03UL) /*!< 1Mbit/s Bluetooth Low Energy */
Kojto 91:031413cf7a89 4780
Kojto 91:031413cf7a89 4781 /* Register: RADIO_PCNF0 */
Kojto 91:031413cf7a89 4782 /* Description: Packet configuration 0. */
Kojto 91:031413cf7a89 4783
Kojto 91:031413cf7a89 4784 /* Bits 19..16 : Length of S1 field in number of bits. Decision point: START task. */
Kojto 91:031413cf7a89 4785 #define RADIO_PCNF0_S1LEN_Pos (16UL) /*!< Position of S1LEN field. */
Kojto 91:031413cf7a89 4786 #define RADIO_PCNF0_S1LEN_Msk (0xFUL << RADIO_PCNF0_S1LEN_Pos) /*!< Bit mask of S1LEN field. */
Kojto 91:031413cf7a89 4787
Kojto 91:031413cf7a89 4788 /* Bit 8 : Length of S0 field in number of bytes. Decision point: START task. */
Kojto 91:031413cf7a89 4789 #define RADIO_PCNF0_S0LEN_Pos (8UL) /*!< Position of S0LEN field. */
Kojto 91:031413cf7a89 4790 #define RADIO_PCNF0_S0LEN_Msk (0x1UL << RADIO_PCNF0_S0LEN_Pos) /*!< Bit mask of S0LEN field. */
Kojto 91:031413cf7a89 4791
Kojto 91:031413cf7a89 4792 /* Bits 3..0 : Length of length field in number of bits. Decision point: START task. */
Kojto 91:031413cf7a89 4793 #define RADIO_PCNF0_LFLEN_Pos (0UL) /*!< Position of LFLEN field. */
Kojto 91:031413cf7a89 4794 #define RADIO_PCNF0_LFLEN_Msk (0xFUL << RADIO_PCNF0_LFLEN_Pos) /*!< Bit mask of LFLEN field. */
Kojto 91:031413cf7a89 4795
Kojto 91:031413cf7a89 4796 /* Register: RADIO_PCNF1 */
Kojto 91:031413cf7a89 4797 /* Description: Packet configuration 1. */
Kojto 91:031413cf7a89 4798
Kojto 91:031413cf7a89 4799 /* Bit 25 : Packet whitening enable. */
Kojto 91:031413cf7a89 4800 #define RADIO_PCNF1_WHITEEN_Pos (25UL) /*!< Position of WHITEEN field. */
Kojto 91:031413cf7a89 4801 #define RADIO_PCNF1_WHITEEN_Msk (0x1UL << RADIO_PCNF1_WHITEEN_Pos) /*!< Bit mask of WHITEEN field. */
Kojto 91:031413cf7a89 4802 #define RADIO_PCNF1_WHITEEN_Disabled (0UL) /*!< Whitening disabled. */
Kojto 91:031413cf7a89 4803 #define RADIO_PCNF1_WHITEEN_Enabled (1UL) /*!< Whitening enabled. */
Kojto 91:031413cf7a89 4804
Kojto 91:031413cf7a89 4805 /* Bit 24 : On air endianness of packet length field. Decision point: START task. */
Kojto 91:031413cf7a89 4806 #define RADIO_PCNF1_ENDIAN_Pos (24UL) /*!< Position of ENDIAN field. */
Kojto 91:031413cf7a89 4807 #define RADIO_PCNF1_ENDIAN_Msk (0x1UL << RADIO_PCNF1_ENDIAN_Pos) /*!< Bit mask of ENDIAN field. */
Kojto 91:031413cf7a89 4808 #define RADIO_PCNF1_ENDIAN_Little (0UL) /*!< Least significant bit on air first */
Kojto 91:031413cf7a89 4809 #define RADIO_PCNF1_ENDIAN_Big (1UL) /*!< Most significant bit on air first */
Kojto 91:031413cf7a89 4810
Kojto 91:031413cf7a89 4811 /* Bits 18..16 : Base address length in number of bytes. Decision point: START task. */
Kojto 91:031413cf7a89 4812 #define RADIO_PCNF1_BALEN_Pos (16UL) /*!< Position of BALEN field. */
Kojto 91:031413cf7a89 4813 #define RADIO_PCNF1_BALEN_Msk (0x7UL << RADIO_PCNF1_BALEN_Pos) /*!< Bit mask of BALEN field. */
Kojto 91:031413cf7a89 4814
Kojto 91:031413cf7a89 4815 /* Bits 15..8 : Static length in number of bytes. Decision point: START task. */
Kojto 91:031413cf7a89 4816 #define RADIO_PCNF1_STATLEN_Pos (8UL) /*!< Position of STATLEN field. */
Kojto 91:031413cf7a89 4817 #define RADIO_PCNF1_STATLEN_Msk (0xFFUL << RADIO_PCNF1_STATLEN_Pos) /*!< Bit mask of STATLEN field. */
Kojto 91:031413cf7a89 4818
Kojto 91:031413cf7a89 4819 /* Bits 7..0 : Maximum length of packet payload in number of bytes. */
Kojto 91:031413cf7a89 4820 #define RADIO_PCNF1_MAXLEN_Pos (0UL) /*!< Position of MAXLEN field. */
Kojto 91:031413cf7a89 4821 #define RADIO_PCNF1_MAXLEN_Msk (0xFFUL << RADIO_PCNF1_MAXLEN_Pos) /*!< Bit mask of MAXLEN field. */
Kojto 91:031413cf7a89 4822
Kojto 91:031413cf7a89 4823 /* Register: RADIO_PREFIX0 */
Kojto 91:031413cf7a89 4824 /* Description: Prefixes bytes for logical addresses 0 to 3. */
Kojto 91:031413cf7a89 4825
Kojto 91:031413cf7a89 4826 /* Bits 31..24 : Address prefix 3. Decision point: START task. */
Kojto 91:031413cf7a89 4827 #define RADIO_PREFIX0_AP3_Pos (24UL) /*!< Position of AP3 field. */
Kojto 91:031413cf7a89 4828 #define RADIO_PREFIX0_AP3_Msk (0xFFUL << RADIO_PREFIX0_AP3_Pos) /*!< Bit mask of AP3 field. */
Kojto 91:031413cf7a89 4829
Kojto 91:031413cf7a89 4830 /* Bits 23..16 : Address prefix 2. Decision point: START task. */
Kojto 91:031413cf7a89 4831 #define RADIO_PREFIX0_AP2_Pos (16UL) /*!< Position of AP2 field. */
Kojto 91:031413cf7a89 4832 #define RADIO_PREFIX0_AP2_Msk (0xFFUL << RADIO_PREFIX0_AP2_Pos) /*!< Bit mask of AP2 field. */
Kojto 91:031413cf7a89 4833
Kojto 91:031413cf7a89 4834 /* Bits 15..8 : Address prefix 1. Decision point: START task. */
Kojto 91:031413cf7a89 4835 #define RADIO_PREFIX0_AP1_Pos (8UL) /*!< Position of AP1 field. */
Kojto 91:031413cf7a89 4836 #define RADIO_PREFIX0_AP1_Msk (0xFFUL << RADIO_PREFIX0_AP1_Pos) /*!< Bit mask of AP1 field. */
Kojto 91:031413cf7a89 4837
Kojto 91:031413cf7a89 4838 /* Bits 7..0 : Address prefix 0. Decision point: START task. */
Kojto 91:031413cf7a89 4839 #define RADIO_PREFIX0_AP0_Pos (0UL) /*!< Position of AP0 field. */
Kojto 91:031413cf7a89 4840 #define RADIO_PREFIX0_AP0_Msk (0xFFUL << RADIO_PREFIX0_AP0_Pos) /*!< Bit mask of AP0 field. */
Kojto 91:031413cf7a89 4841
Kojto 91:031413cf7a89 4842 /* Register: RADIO_PREFIX1 */
Kojto 91:031413cf7a89 4843 /* Description: Prefixes bytes for logical addresses 4 to 7. */
Kojto 91:031413cf7a89 4844
Kojto 91:031413cf7a89 4845 /* Bits 31..24 : Address prefix 7. Decision point: START task. */
Kojto 91:031413cf7a89 4846 #define RADIO_PREFIX1_AP7_Pos (24UL) /*!< Position of AP7 field. */
Kojto 91:031413cf7a89 4847 #define RADIO_PREFIX1_AP7_Msk (0xFFUL << RADIO_PREFIX1_AP7_Pos) /*!< Bit mask of AP7 field. */
Kojto 91:031413cf7a89 4848
Kojto 91:031413cf7a89 4849 /* Bits 23..16 : Address prefix 6. Decision point: START task. */
Kojto 91:031413cf7a89 4850 #define RADIO_PREFIX1_AP6_Pos (16UL) /*!< Position of AP6 field. */
Kojto 91:031413cf7a89 4851 #define RADIO_PREFIX1_AP6_Msk (0xFFUL << RADIO_PREFIX1_AP6_Pos) /*!< Bit mask of AP6 field. */
Kojto 91:031413cf7a89 4852
Kojto 91:031413cf7a89 4853 /* Bits 15..8 : Address prefix 5. Decision point: START task. */
Kojto 91:031413cf7a89 4854 #define RADIO_PREFIX1_AP5_Pos (8UL) /*!< Position of AP5 field. */
Kojto 91:031413cf7a89 4855 #define RADIO_PREFIX1_AP5_Msk (0xFFUL << RADIO_PREFIX1_AP5_Pos) /*!< Bit mask of AP5 field. */
Kojto 91:031413cf7a89 4856
Kojto 91:031413cf7a89 4857 /* Bits 7..0 : Address prefix 4. Decision point: START task. */
Kojto 91:031413cf7a89 4858 #define RADIO_PREFIX1_AP4_Pos (0UL) /*!< Position of AP4 field. */
Kojto 91:031413cf7a89 4859 #define RADIO_PREFIX1_AP4_Msk (0xFFUL << RADIO_PREFIX1_AP4_Pos) /*!< Bit mask of AP4 field. */
Kojto 91:031413cf7a89 4860
Kojto 91:031413cf7a89 4861 /* Register: RADIO_TXADDRESS */
Kojto 91:031413cf7a89 4862 /* Description: Transmit address select. */
Kojto 91:031413cf7a89 4863
Kojto 91:031413cf7a89 4864 /* Bits 2..0 : Logical address to be used when transmitting a packet. Decision point: START task. */
Kojto 91:031413cf7a89 4865 #define RADIO_TXADDRESS_TXADDRESS_Pos (0UL) /*!< Position of TXADDRESS field. */
Kojto 91:031413cf7a89 4866 #define RADIO_TXADDRESS_TXADDRESS_Msk (0x7UL << RADIO_TXADDRESS_TXADDRESS_Pos) /*!< Bit mask of TXADDRESS field. */
Kojto 91:031413cf7a89 4867
Kojto 91:031413cf7a89 4868 /* Register: RADIO_RXADDRESSES */
Kojto 91:031413cf7a89 4869 /* Description: Receive address select. */
Kojto 91:031413cf7a89 4870
Kojto 91:031413cf7a89 4871 /* Bit 7 : Enable reception on logical address 7. Decision point: START task. */
Kojto 91:031413cf7a89 4872 #define RADIO_RXADDRESSES_ADDR7_Pos (7UL) /*!< Position of ADDR7 field. */
Kojto 91:031413cf7a89 4873 #define RADIO_RXADDRESSES_ADDR7_Msk (0x1UL << RADIO_RXADDRESSES_ADDR7_Pos) /*!< Bit mask of ADDR7 field. */
Kojto 91:031413cf7a89 4874 #define RADIO_RXADDRESSES_ADDR7_Disabled (0UL) /*!< Reception disabled. */
Kojto 91:031413cf7a89 4875 #define RADIO_RXADDRESSES_ADDR7_Enabled (1UL) /*!< Reception enabled. */
Kojto 91:031413cf7a89 4876
Kojto 91:031413cf7a89 4877 /* Bit 6 : Enable reception on logical address 6. Decision point: START task. */
Kojto 91:031413cf7a89 4878 #define RADIO_RXADDRESSES_ADDR6_Pos (6UL) /*!< Position of ADDR6 field. */
Kojto 91:031413cf7a89 4879 #define RADIO_RXADDRESSES_ADDR6_Msk (0x1UL << RADIO_RXADDRESSES_ADDR6_Pos) /*!< Bit mask of ADDR6 field. */
Kojto 91:031413cf7a89 4880 #define RADIO_RXADDRESSES_ADDR6_Disabled (0UL) /*!< Reception disabled. */
Kojto 91:031413cf7a89 4881 #define RADIO_RXADDRESSES_ADDR6_Enabled (1UL) /*!< Reception enabled. */
Kojto 91:031413cf7a89 4882
Kojto 91:031413cf7a89 4883 /* Bit 5 : Enable reception on logical address 5. Decision point: START task. */
Kojto 91:031413cf7a89 4884 #define RADIO_RXADDRESSES_ADDR5_Pos (5UL) /*!< Position of ADDR5 field. */
Kojto 91:031413cf7a89 4885 #define RADIO_RXADDRESSES_ADDR5_Msk (0x1UL << RADIO_RXADDRESSES_ADDR5_Pos) /*!< Bit mask of ADDR5 field. */
Kojto 91:031413cf7a89 4886 #define RADIO_RXADDRESSES_ADDR5_Disabled (0UL) /*!< Reception disabled. */
Kojto 91:031413cf7a89 4887 #define RADIO_RXADDRESSES_ADDR5_Enabled (1UL) /*!< Reception enabled. */
Kojto 91:031413cf7a89 4888
Kojto 91:031413cf7a89 4889 /* Bit 4 : Enable reception on logical address 4. Decision point: START task. */
Kojto 91:031413cf7a89 4890 #define RADIO_RXADDRESSES_ADDR4_Pos (4UL) /*!< Position of ADDR4 field. */
Kojto 91:031413cf7a89 4891 #define RADIO_RXADDRESSES_ADDR4_Msk (0x1UL << RADIO_RXADDRESSES_ADDR4_Pos) /*!< Bit mask of ADDR4 field. */
Kojto 91:031413cf7a89 4892 #define RADIO_RXADDRESSES_ADDR4_Disabled (0UL) /*!< Reception disabled. */
Kojto 91:031413cf7a89 4893 #define RADIO_RXADDRESSES_ADDR4_Enabled (1UL) /*!< Reception enabled. */
Kojto 91:031413cf7a89 4894
Kojto 91:031413cf7a89 4895 /* Bit 3 : Enable reception on logical address 3. Decision point: START task. */
Kojto 91:031413cf7a89 4896 #define RADIO_RXADDRESSES_ADDR3_Pos (3UL) /*!< Position of ADDR3 field. */
Kojto 91:031413cf7a89 4897 #define RADIO_RXADDRESSES_ADDR3_Msk (0x1UL << RADIO_RXADDRESSES_ADDR3_Pos) /*!< Bit mask of ADDR3 field. */
Kojto 91:031413cf7a89 4898 #define RADIO_RXADDRESSES_ADDR3_Disabled (0UL) /*!< Reception disabled. */
Kojto 91:031413cf7a89 4899 #define RADIO_RXADDRESSES_ADDR3_Enabled (1UL) /*!< Reception enabled. */
Kojto 91:031413cf7a89 4900
Kojto 91:031413cf7a89 4901 /* Bit 2 : Enable reception on logical address 2. Decision point: START task. */
Kojto 91:031413cf7a89 4902 #define RADIO_RXADDRESSES_ADDR2_Pos (2UL) /*!< Position of ADDR2 field. */
Kojto 91:031413cf7a89 4903 #define RADIO_RXADDRESSES_ADDR2_Msk (0x1UL << RADIO_RXADDRESSES_ADDR2_Pos) /*!< Bit mask of ADDR2 field. */
Kojto 91:031413cf7a89 4904 #define RADIO_RXADDRESSES_ADDR2_Disabled (0UL) /*!< Reception disabled. */
Kojto 91:031413cf7a89 4905 #define RADIO_RXADDRESSES_ADDR2_Enabled (1UL) /*!< Reception enabled. */
Kojto 91:031413cf7a89 4906
Kojto 91:031413cf7a89 4907 /* Bit 1 : Enable reception on logical address 1. Decision point: START task. */
Kojto 91:031413cf7a89 4908 #define RADIO_RXADDRESSES_ADDR1_Pos (1UL) /*!< Position of ADDR1 field. */
Kojto 91:031413cf7a89 4909 #define RADIO_RXADDRESSES_ADDR1_Msk (0x1UL << RADIO_RXADDRESSES_ADDR1_Pos) /*!< Bit mask of ADDR1 field. */
Kojto 91:031413cf7a89 4910 #define RADIO_RXADDRESSES_ADDR1_Disabled (0UL) /*!< Reception disabled. */
Kojto 91:031413cf7a89 4911 #define RADIO_RXADDRESSES_ADDR1_Enabled (1UL) /*!< Reception enabled. */
Kojto 91:031413cf7a89 4912
Kojto 91:031413cf7a89 4913 /* Bit 0 : Enable reception on logical address 0. Decision point: START task. */
Kojto 91:031413cf7a89 4914 #define RADIO_RXADDRESSES_ADDR0_Pos (0UL) /*!< Position of ADDR0 field. */
Kojto 91:031413cf7a89 4915 #define RADIO_RXADDRESSES_ADDR0_Msk (0x1UL << RADIO_RXADDRESSES_ADDR0_Pos) /*!< Bit mask of ADDR0 field. */
Kojto 91:031413cf7a89 4916 #define RADIO_RXADDRESSES_ADDR0_Disabled (0UL) /*!< Reception disabled. */
Kojto 91:031413cf7a89 4917 #define RADIO_RXADDRESSES_ADDR0_Enabled (1UL) /*!< Reception enabled. */
Kojto 91:031413cf7a89 4918
Kojto 91:031413cf7a89 4919 /* Register: RADIO_CRCCNF */
Kojto 91:031413cf7a89 4920 /* Description: CRC configuration. */
Kojto 91:031413cf7a89 4921
Kojto 91:031413cf7a89 4922 /* Bit 8 : Leave packet address field out of the CRC calculation. Decision point: START task. */
Kojto 91:031413cf7a89 4923 #define RADIO_CRCCNF_SKIP_ADDR_Pos (8UL) /*!< Position of SKIP_ADDR field. */
Kojto 91:031413cf7a89 4924 #define RADIO_CRCCNF_SKIP_ADDR_Msk (0x1UL << RADIO_CRCCNF_SKIP_ADDR_Pos) /*!< Bit mask of SKIP_ADDR field. */
Kojto 91:031413cf7a89 4925 #define RADIO_CRCCNF_SKIP_ADDR_Include (0UL) /*!< Include packet address in CRC calculation. */
Kojto 91:031413cf7a89 4926 #define RADIO_CRCCNF_SKIP_ADDR_Skip (1UL) /*!< Packet address is skipped in CRC calculation. The CRC calculation will start at the first byte after the address. */
Kojto 91:031413cf7a89 4927
Kojto 91:031413cf7a89 4928 /* Bits 1..0 : CRC length. Decision point: START task. */
Kojto 91:031413cf7a89 4929 #define RADIO_CRCCNF_LEN_Pos (0UL) /*!< Position of LEN field. */
Kojto 91:031413cf7a89 4930 #define RADIO_CRCCNF_LEN_Msk (0x3UL << RADIO_CRCCNF_LEN_Pos) /*!< Bit mask of LEN field. */
Kojto 91:031413cf7a89 4931 #define RADIO_CRCCNF_LEN_Disabled (0UL) /*!< CRC calculation disabled. */
Kojto 91:031413cf7a89 4932 #define RADIO_CRCCNF_LEN_One (1UL) /*!< One byte long CRC. */
Kojto 91:031413cf7a89 4933 #define RADIO_CRCCNF_LEN_Two (2UL) /*!< Two bytes long CRC. */
Kojto 91:031413cf7a89 4934 #define RADIO_CRCCNF_LEN_Three (3UL) /*!< Three bytes long CRC. */
Kojto 91:031413cf7a89 4935
Kojto 91:031413cf7a89 4936 /* Register: RADIO_CRCPOLY */
Kojto 91:031413cf7a89 4937 /* Description: CRC polynomial. */
Kojto 91:031413cf7a89 4938
Kojto 91:031413cf7a89 4939 /* Bits 23..1 : CRC polynomial. Decision point: START task. */
Kojto 91:031413cf7a89 4940 #define RADIO_CRCPOLY_CRCPOLY_Pos (1UL) /*!< Position of CRCPOLY field. */
Kojto 91:031413cf7a89 4941 #define RADIO_CRCPOLY_CRCPOLY_Msk (0x7FFFFFUL << RADIO_CRCPOLY_CRCPOLY_Pos) /*!< Bit mask of CRCPOLY field. */
Kojto 91:031413cf7a89 4942
Kojto 91:031413cf7a89 4943 /* Register: RADIO_CRCINIT */
Kojto 91:031413cf7a89 4944 /* Description: CRC initial value. */
Kojto 91:031413cf7a89 4945
Kojto 91:031413cf7a89 4946 /* Bits 23..0 : Initial value for CRC calculation. Decision point: START task. */
Kojto 91:031413cf7a89 4947 #define RADIO_CRCINIT_CRCINIT_Pos (0UL) /*!< Position of CRCINIT field. */
Kojto 91:031413cf7a89 4948 #define RADIO_CRCINIT_CRCINIT_Msk (0xFFFFFFUL << RADIO_CRCINIT_CRCINIT_Pos) /*!< Bit mask of CRCINIT field. */
Kojto 91:031413cf7a89 4949
Kojto 91:031413cf7a89 4950 /* Register: RADIO_TEST */
Kojto 91:031413cf7a89 4951 /* Description: Test features enable register. */
Kojto 91:031413cf7a89 4952
Kojto 91:031413cf7a89 4953 /* Bit 1 : PLL lock. Decision point: TXEN or RXEN task. */
Kojto 91:031413cf7a89 4954 #define RADIO_TEST_PLL_LOCK_Pos (1UL) /*!< Position of PLL_LOCK field. */
Kojto 91:031413cf7a89 4955 #define RADIO_TEST_PLL_LOCK_Msk (0x1UL << RADIO_TEST_PLL_LOCK_Pos) /*!< Bit mask of PLL_LOCK field. */
Kojto 91:031413cf7a89 4956 #define RADIO_TEST_PLL_LOCK_Disabled (0UL) /*!< PLL lock disabled. */
Kojto 91:031413cf7a89 4957 #define RADIO_TEST_PLL_LOCK_Enabled (1UL) /*!< PLL lock enabled. */
Kojto 91:031413cf7a89 4958
Kojto 91:031413cf7a89 4959 /* Bit 0 : Constant carrier. Decision point: TXEN task. */
Kojto 91:031413cf7a89 4960 #define RADIO_TEST_CONST_CARRIER_Pos (0UL) /*!< Position of CONST_CARRIER field. */
Kojto 91:031413cf7a89 4961 #define RADIO_TEST_CONST_CARRIER_Msk (0x1UL << RADIO_TEST_CONST_CARRIER_Pos) /*!< Bit mask of CONST_CARRIER field. */
Kojto 91:031413cf7a89 4962 #define RADIO_TEST_CONST_CARRIER_Disabled (0UL) /*!< Constant carrier disabled. */
Kojto 91:031413cf7a89 4963 #define RADIO_TEST_CONST_CARRIER_Enabled (1UL) /*!< Constant carrier enabled. */
Kojto 91:031413cf7a89 4964
Kojto 91:031413cf7a89 4965 /* Register: RADIO_TIFS */
Kojto 91:031413cf7a89 4966 /* Description: Inter Frame Spacing in microseconds. */
Kojto 91:031413cf7a89 4967
Kojto 91:031413cf7a89 4968 /* Bits 7..0 : Inter frame spacing in microseconds. Decision point: START rask */
Kojto 91:031413cf7a89 4969 #define RADIO_TIFS_TIFS_Pos (0UL) /*!< Position of TIFS field. */
Kojto 91:031413cf7a89 4970 #define RADIO_TIFS_TIFS_Msk (0xFFUL << RADIO_TIFS_TIFS_Pos) /*!< Bit mask of TIFS field. */
Kojto 91:031413cf7a89 4971
Kojto 91:031413cf7a89 4972 /* Register: RADIO_RSSISAMPLE */
Kojto 91:031413cf7a89 4973 /* Description: RSSI sample. */
Kojto 91:031413cf7a89 4974
Kojto 91:031413cf7a89 4975 /* Bits 6..0 : RSSI sample result. The result is read as a positive value so that ReceivedSignalStrength = -RSSISAMPLE dBm */
Kojto 91:031413cf7a89 4976 #define RADIO_RSSISAMPLE_RSSISAMPLE_Pos (0UL) /*!< Position of RSSISAMPLE field. */
Kojto 91:031413cf7a89 4977 #define RADIO_RSSISAMPLE_RSSISAMPLE_Msk (0x7FUL << RADIO_RSSISAMPLE_RSSISAMPLE_Pos) /*!< Bit mask of RSSISAMPLE field. */
Kojto 91:031413cf7a89 4978
Kojto 91:031413cf7a89 4979 /* Register: RADIO_STATE */
Kojto 91:031413cf7a89 4980 /* Description: Current radio state. */
Kojto 91:031413cf7a89 4981
Kojto 91:031413cf7a89 4982 /* Bits 3..0 : Current radio state. */
Kojto 91:031413cf7a89 4983 #define RADIO_STATE_STATE_Pos (0UL) /*!< Position of STATE field. */
Kojto 91:031413cf7a89 4984 #define RADIO_STATE_STATE_Msk (0xFUL << RADIO_STATE_STATE_Pos) /*!< Bit mask of STATE field. */
Kojto 91:031413cf7a89 4985 #define RADIO_STATE_STATE_Disabled (0x00UL) /*!< Radio is in the Disabled state. */
Kojto 91:031413cf7a89 4986 #define RADIO_STATE_STATE_RxRu (0x01UL) /*!< Radio is in the Rx Ramp Up state. */
Kojto 91:031413cf7a89 4987 #define RADIO_STATE_STATE_RxIdle (0x02UL) /*!< Radio is in the Rx Idle state. */
Kojto 91:031413cf7a89 4988 #define RADIO_STATE_STATE_Rx (0x03UL) /*!< Radio is in the Rx state. */
Kojto 91:031413cf7a89 4989 #define RADIO_STATE_STATE_RxDisable (0x04UL) /*!< Radio is in the Rx Disable state. */
Kojto 91:031413cf7a89 4990 #define RADIO_STATE_STATE_TxRu (0x09UL) /*!< Radio is in the Tx Ramp Up state. */
Kojto 91:031413cf7a89 4991 #define RADIO_STATE_STATE_TxIdle (0x0AUL) /*!< Radio is in the Tx Idle state. */
Kojto 91:031413cf7a89 4992 #define RADIO_STATE_STATE_Tx (0x0BUL) /*!< Radio is in the Tx state. */
Kojto 91:031413cf7a89 4993 #define RADIO_STATE_STATE_TxDisable (0x0CUL) /*!< Radio is in the Tx Disable state. */
Kojto 91:031413cf7a89 4994
Kojto 91:031413cf7a89 4995 /* Register: RADIO_DATAWHITEIV */
Kojto 91:031413cf7a89 4996 /* Description: Data whitening initial value. */
Kojto 91:031413cf7a89 4997
Kojto 91:031413cf7a89 4998 /* Bits 5..0 : Data whitening initial value. Bit 0 corresponds to Position 0 of the LSFR, Bit 1 to position 5... Decision point: TXEN or RXEN task. */
Kojto 91:031413cf7a89 4999 #define RADIO_DATAWHITEIV_DATAWHITEIV_Pos (0UL) /*!< Position of DATAWHITEIV field. */
Kojto 91:031413cf7a89 5000 #define RADIO_DATAWHITEIV_DATAWHITEIV_Msk (0x3FUL << RADIO_DATAWHITEIV_DATAWHITEIV_Pos) /*!< Bit mask of DATAWHITEIV field. */
Kojto 91:031413cf7a89 5001
Kojto 91:031413cf7a89 5002 /* Register: RADIO_DAP */
Kojto 91:031413cf7a89 5003 /* Description: Device address prefix. */
Kojto 91:031413cf7a89 5004
Kojto 91:031413cf7a89 5005 /* Bits 15..0 : Device address prefix. */
Kojto 91:031413cf7a89 5006 #define RADIO_DAP_DAP_Pos (0UL) /*!< Position of DAP field. */
Kojto 91:031413cf7a89 5007 #define RADIO_DAP_DAP_Msk (0xFFFFUL << RADIO_DAP_DAP_Pos) /*!< Bit mask of DAP field. */
Kojto 91:031413cf7a89 5008
Kojto 91:031413cf7a89 5009 /* Register: RADIO_DACNF */
Kojto 91:031413cf7a89 5010 /* Description: Device address match configuration. */
Kojto 91:031413cf7a89 5011
Kojto 91:031413cf7a89 5012 /* Bit 15 : TxAdd for device address 7. */
Kojto 91:031413cf7a89 5013 #define RADIO_DACNF_TXADD7_Pos (15UL) /*!< Position of TXADD7 field. */
Kojto 91:031413cf7a89 5014 #define RADIO_DACNF_TXADD7_Msk (0x1UL << RADIO_DACNF_TXADD7_Pos) /*!< Bit mask of TXADD7 field. */
Kojto 91:031413cf7a89 5015
Kojto 91:031413cf7a89 5016 /* Bit 14 : TxAdd for device address 6. */
Kojto 91:031413cf7a89 5017 #define RADIO_DACNF_TXADD6_Pos (14UL) /*!< Position of TXADD6 field. */
Kojto 91:031413cf7a89 5018 #define RADIO_DACNF_TXADD6_Msk (0x1UL << RADIO_DACNF_TXADD6_Pos) /*!< Bit mask of TXADD6 field. */
Kojto 91:031413cf7a89 5019
Kojto 91:031413cf7a89 5020 /* Bit 13 : TxAdd for device address 5. */
Kojto 91:031413cf7a89 5021 #define RADIO_DACNF_TXADD5_Pos (13UL) /*!< Position of TXADD5 field. */
Kojto 91:031413cf7a89 5022 #define RADIO_DACNF_TXADD5_Msk (0x1UL << RADIO_DACNF_TXADD5_Pos) /*!< Bit mask of TXADD5 field. */
Kojto 91:031413cf7a89 5023
Kojto 91:031413cf7a89 5024 /* Bit 12 : TxAdd for device address 4. */
Kojto 91:031413cf7a89 5025 #define RADIO_DACNF_TXADD4_Pos (12UL) /*!< Position of TXADD4 field. */
Kojto 91:031413cf7a89 5026 #define RADIO_DACNF_TXADD4_Msk (0x1UL << RADIO_DACNF_TXADD4_Pos) /*!< Bit mask of TXADD4 field. */
Kojto 91:031413cf7a89 5027
Kojto 91:031413cf7a89 5028 /* Bit 11 : TxAdd for device address 3. */
Kojto 91:031413cf7a89 5029 #define RADIO_DACNF_TXADD3_Pos (11UL) /*!< Position of TXADD3 field. */
Kojto 91:031413cf7a89 5030 #define RADIO_DACNF_TXADD3_Msk (0x1UL << RADIO_DACNF_TXADD3_Pos) /*!< Bit mask of TXADD3 field. */
Kojto 91:031413cf7a89 5031
Kojto 91:031413cf7a89 5032 /* Bit 10 : TxAdd for device address 2. */
Kojto 91:031413cf7a89 5033 #define RADIO_DACNF_TXADD2_Pos (10UL) /*!< Position of TXADD2 field. */
Kojto 91:031413cf7a89 5034 #define RADIO_DACNF_TXADD2_Msk (0x1UL << RADIO_DACNF_TXADD2_Pos) /*!< Bit mask of TXADD2 field. */
Kojto 91:031413cf7a89 5035
Kojto 91:031413cf7a89 5036 /* Bit 9 : TxAdd for device address 1. */
Kojto 91:031413cf7a89 5037 #define RADIO_DACNF_TXADD1_Pos (9UL) /*!< Position of TXADD1 field. */
Kojto 91:031413cf7a89 5038 #define RADIO_DACNF_TXADD1_Msk (0x1UL << RADIO_DACNF_TXADD1_Pos) /*!< Bit mask of TXADD1 field. */
Kojto 91:031413cf7a89 5039
Kojto 91:031413cf7a89 5040 /* Bit 8 : TxAdd for device address 0. */
Kojto 91:031413cf7a89 5041 #define RADIO_DACNF_TXADD0_Pos (8UL) /*!< Position of TXADD0 field. */
Kojto 91:031413cf7a89 5042 #define RADIO_DACNF_TXADD0_Msk (0x1UL << RADIO_DACNF_TXADD0_Pos) /*!< Bit mask of TXADD0 field. */
Kojto 91:031413cf7a89 5043
Kojto 91:031413cf7a89 5044 /* Bit 7 : Enable or disable device address matching using device address 7. */
Kojto 91:031413cf7a89 5045 #define RADIO_DACNF_ENA7_Pos (7UL) /*!< Position of ENA7 field. */
Kojto 91:031413cf7a89 5046 #define RADIO_DACNF_ENA7_Msk (0x1UL << RADIO_DACNF_ENA7_Pos) /*!< Bit mask of ENA7 field. */
Kojto 91:031413cf7a89 5047 #define RADIO_DACNF_ENA7_Disabled (0UL) /*!< Disabled. */
Kojto 91:031413cf7a89 5048 #define RADIO_DACNF_ENA7_Enabled (1UL) /*!< Enabled. */
Kojto 91:031413cf7a89 5049
Kojto 91:031413cf7a89 5050 /* Bit 6 : Enable or disable device address matching using device address 6. */
Kojto 91:031413cf7a89 5051 #define RADIO_DACNF_ENA6_Pos (6UL) /*!< Position of ENA6 field. */
Kojto 91:031413cf7a89 5052 #define RADIO_DACNF_ENA6_Msk (0x1UL << RADIO_DACNF_ENA6_Pos) /*!< Bit mask of ENA6 field. */
Kojto 91:031413cf7a89 5053 #define RADIO_DACNF_ENA6_Disabled (0UL) /*!< Disabled. */
Kojto 91:031413cf7a89 5054 #define RADIO_DACNF_ENA6_Enabled (1UL) /*!< Enabled. */
Kojto 91:031413cf7a89 5055
Kojto 91:031413cf7a89 5056 /* Bit 5 : Enable or disable device address matching using device address 5. */
Kojto 91:031413cf7a89 5057 #define RADIO_DACNF_ENA5_Pos (5UL) /*!< Position of ENA5 field. */
Kojto 91:031413cf7a89 5058 #define RADIO_DACNF_ENA5_Msk (0x1UL << RADIO_DACNF_ENA5_Pos) /*!< Bit mask of ENA5 field. */
Kojto 91:031413cf7a89 5059 #define RADIO_DACNF_ENA5_Disabled (0UL) /*!< Disabled. */
Kojto 91:031413cf7a89 5060 #define RADIO_DACNF_ENA5_Enabled (1UL) /*!< Enabled. */
Kojto 91:031413cf7a89 5061
Kojto 91:031413cf7a89 5062 /* Bit 4 : Enable or disable device address matching using device address 4. */
Kojto 91:031413cf7a89 5063 #define RADIO_DACNF_ENA4_Pos (4UL) /*!< Position of ENA4 field. */
Kojto 91:031413cf7a89 5064 #define RADIO_DACNF_ENA4_Msk (0x1UL << RADIO_DACNF_ENA4_Pos) /*!< Bit mask of ENA4 field. */
Kojto 91:031413cf7a89 5065 #define RADIO_DACNF_ENA4_Disabled (0UL) /*!< Disabled. */
Kojto 91:031413cf7a89 5066 #define RADIO_DACNF_ENA4_Enabled (1UL) /*!< Enabled. */
Kojto 91:031413cf7a89 5067
Kojto 91:031413cf7a89 5068 /* Bit 3 : Enable or disable device address matching using device address 3. */
Kojto 91:031413cf7a89 5069 #define RADIO_DACNF_ENA3_Pos (3UL) /*!< Position of ENA3 field. */
Kojto 91:031413cf7a89 5070 #define RADIO_DACNF_ENA3_Msk (0x1UL << RADIO_DACNF_ENA3_Pos) /*!< Bit mask of ENA3 field. */
Kojto 91:031413cf7a89 5071 #define RADIO_DACNF_ENA3_Disabled (0UL) /*!< Disabled. */
Kojto 91:031413cf7a89 5072 #define RADIO_DACNF_ENA3_Enabled (1UL) /*!< Enabled. */
Kojto 91:031413cf7a89 5073
Kojto 91:031413cf7a89 5074 /* Bit 2 : Enable or disable device address matching using device address 2. */
Kojto 91:031413cf7a89 5075 #define RADIO_DACNF_ENA2_Pos (2UL) /*!< Position of ENA2 field. */
Kojto 91:031413cf7a89 5076 #define RADIO_DACNF_ENA2_Msk (0x1UL << RADIO_DACNF_ENA2_Pos) /*!< Bit mask of ENA2 field. */
Kojto 91:031413cf7a89 5077 #define RADIO_DACNF_ENA2_Disabled (0UL) /*!< Disabled. */
Kojto 91:031413cf7a89 5078 #define RADIO_DACNF_ENA2_Enabled (1UL) /*!< Enabled. */
Kojto 91:031413cf7a89 5079
Kojto 91:031413cf7a89 5080 /* Bit 1 : Enable or disable device address matching using device address 1. */
Kojto 91:031413cf7a89 5081 #define RADIO_DACNF_ENA1_Pos (1UL) /*!< Position of ENA1 field. */
Kojto 91:031413cf7a89 5082 #define RADIO_DACNF_ENA1_Msk (0x1UL << RADIO_DACNF_ENA1_Pos) /*!< Bit mask of ENA1 field. */
Kojto 91:031413cf7a89 5083 #define RADIO_DACNF_ENA1_Disabled (0UL) /*!< Disabled. */
Kojto 91:031413cf7a89 5084 #define RADIO_DACNF_ENA1_Enabled (1UL) /*!< Enabled. */
Kojto 91:031413cf7a89 5085
Kojto 91:031413cf7a89 5086 /* Bit 0 : Enable or disable device address matching using device address 0. */
Kojto 91:031413cf7a89 5087 #define RADIO_DACNF_ENA0_Pos (0UL) /*!< Position of ENA0 field. */
Kojto 91:031413cf7a89 5088 #define RADIO_DACNF_ENA0_Msk (0x1UL << RADIO_DACNF_ENA0_Pos) /*!< Bit mask of ENA0 field. */
Kojto 91:031413cf7a89 5089 #define RADIO_DACNF_ENA0_Disabled (0UL) /*!< Disabled. */
Kojto 91:031413cf7a89 5090 #define RADIO_DACNF_ENA0_Enabled (1UL) /*!< Enabled. */
Kojto 91:031413cf7a89 5091
Kojto 91:031413cf7a89 5092 /* Register: RADIO_OVERRIDE0 */
Kojto 91:031413cf7a89 5093 /* Description: Trim value override register 0. */
Kojto 91:031413cf7a89 5094
Kojto 91:031413cf7a89 5095 /* Bits 31..0 : Trim value override register 0. */
Kojto 91:031413cf7a89 5096 #define RADIO_OVERRIDE0_OVERRIDE0_Pos (0UL) /*!< Position of OVERRIDE0 field. */
Kojto 91:031413cf7a89 5097 #define RADIO_OVERRIDE0_OVERRIDE0_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE0_OVERRIDE0_Pos) /*!< Bit mask of OVERRIDE0 field. */
Kojto 91:031413cf7a89 5098
Kojto 91:031413cf7a89 5099 /* Register: RADIO_OVERRIDE1 */
Kojto 91:031413cf7a89 5100 /* Description: Trim value override register 1. */
Kojto 91:031413cf7a89 5101
Kojto 91:031413cf7a89 5102 /* Bits 31..0 : Trim value override register 1. */
Kojto 91:031413cf7a89 5103 #define RADIO_OVERRIDE1_OVERRIDE1_Pos (0UL) /*!< Position of OVERRIDE1 field. */
Kojto 91:031413cf7a89 5104 #define RADIO_OVERRIDE1_OVERRIDE1_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE1_OVERRIDE1_Pos) /*!< Bit mask of OVERRIDE1 field. */
Kojto 91:031413cf7a89 5105
Kojto 91:031413cf7a89 5106 /* Register: RADIO_OVERRIDE2 */
Kojto 91:031413cf7a89 5107 /* Description: Trim value override register 2. */
Kojto 91:031413cf7a89 5108
Kojto 91:031413cf7a89 5109 /* Bits 31..0 : Trim value override register 2. */
Kojto 91:031413cf7a89 5110 #define RADIO_OVERRIDE2_OVERRIDE2_Pos (0UL) /*!< Position of OVERRIDE2 field. */
Kojto 91:031413cf7a89 5111 #define RADIO_OVERRIDE2_OVERRIDE2_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE2_OVERRIDE2_Pos) /*!< Bit mask of OVERRIDE2 field. */
Kojto 91:031413cf7a89 5112
Kojto 91:031413cf7a89 5113 /* Register: RADIO_OVERRIDE3 */
Kojto 91:031413cf7a89 5114 /* Description: Trim value override register 3. */
Kojto 91:031413cf7a89 5115
Kojto 91:031413cf7a89 5116 /* Bits 31..0 : Trim value override register 3. */
Kojto 91:031413cf7a89 5117 #define RADIO_OVERRIDE3_OVERRIDE3_Pos (0UL) /*!< Position of OVERRIDE3 field. */
Kojto 91:031413cf7a89 5118 #define RADIO_OVERRIDE3_OVERRIDE3_Msk (0xFFFFFFFFUL << RADIO_OVERRIDE3_OVERRIDE3_Pos) /*!< Bit mask of OVERRIDE3 field. */
Kojto 91:031413cf7a89 5119
Kojto 91:031413cf7a89 5120 /* Register: RADIO_OVERRIDE4 */
Kojto 91:031413cf7a89 5121 /* Description: Trim value override register 4. */
Kojto 91:031413cf7a89 5122
Kojto 91:031413cf7a89 5123 /* Bit 31 : Enable or disable override of default trim values. */
Kojto 91:031413cf7a89 5124 #define RADIO_OVERRIDE4_ENABLE_Pos (31UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 5125 #define RADIO_OVERRIDE4_ENABLE_Msk (0x1UL << RADIO_OVERRIDE4_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 5126 #define RADIO_OVERRIDE4_ENABLE_Disabled (0UL) /*!< Override trim values disabled. */
Kojto 91:031413cf7a89 5127 #define RADIO_OVERRIDE4_ENABLE_Enabled (1UL) /*!< Override trim values enabled. */
Kojto 91:031413cf7a89 5128
Kojto 91:031413cf7a89 5129 /* Bits 27..0 : Trim value override register 4. */
Kojto 91:031413cf7a89 5130 #define RADIO_OVERRIDE4_OVERRIDE4_Pos (0UL) /*!< Position of OVERRIDE4 field. */
Kojto 91:031413cf7a89 5131 #define RADIO_OVERRIDE4_OVERRIDE4_Msk (0xFFFFFFFUL << RADIO_OVERRIDE4_OVERRIDE4_Pos) /*!< Bit mask of OVERRIDE4 field. */
Kojto 91:031413cf7a89 5132
Kojto 91:031413cf7a89 5133 /* Register: RADIO_POWER */
Kojto 91:031413cf7a89 5134 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 5135
Kojto 91:031413cf7a89 5136 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 5137 #define RADIO_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 5138 #define RADIO_POWER_POWER_Msk (0x1UL << RADIO_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 5139 #define RADIO_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 5140 #define RADIO_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 5141
Kojto 91:031413cf7a89 5142
Kojto 91:031413cf7a89 5143 /* Peripheral: RNG */
Kojto 91:031413cf7a89 5144 /* Description: Random Number Generator. */
Kojto 91:031413cf7a89 5145
Kojto 91:031413cf7a89 5146 /* Register: RNG_SHORTS */
Kojto 91:031413cf7a89 5147 /* Description: Shortcut for the RNG. */
Kojto 91:031413cf7a89 5148
Kojto 91:031413cf7a89 5149 /* Bit 0 : Short-cut between VALRDY event and STOP task. */
Kojto 91:031413cf7a89 5150 #define RNG_SHORTS_VALRDY_STOP_Pos (0UL) /*!< Position of VALRDY_STOP field. */
Kojto 91:031413cf7a89 5151 #define RNG_SHORTS_VALRDY_STOP_Msk (0x1UL << RNG_SHORTS_VALRDY_STOP_Pos) /*!< Bit mask of VALRDY_STOP field. */
Kojto 91:031413cf7a89 5152 #define RNG_SHORTS_VALRDY_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5153 #define RNG_SHORTS_VALRDY_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5154
Kojto 91:031413cf7a89 5155 /* Register: RNG_INTENSET */
Kojto 91:031413cf7a89 5156 /* Description: Interrupt enable set register */
Kojto 91:031413cf7a89 5157
Kojto 91:031413cf7a89 5158 /* Bit 0 : Enable interrupt on VALRDY event. */
Kojto 91:031413cf7a89 5159 #define RNG_INTENSET_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
Kojto 91:031413cf7a89 5160 #define RNG_INTENSET_VALRDY_Msk (0x1UL << RNG_INTENSET_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
Kojto 91:031413cf7a89 5161 #define RNG_INTENSET_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5162 #define RNG_INTENSET_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5163 #define RNG_INTENSET_VALRDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5164
Kojto 91:031413cf7a89 5165 /* Register: RNG_INTENCLR */
Kojto 91:031413cf7a89 5166 /* Description: Interrupt enable clear register */
Kojto 91:031413cf7a89 5167
Kojto 91:031413cf7a89 5168 /* Bit 0 : Disable interrupt on VALRDY event. */
Kojto 91:031413cf7a89 5169 #define RNG_INTENCLR_VALRDY_Pos (0UL) /*!< Position of VALRDY field. */
Kojto 91:031413cf7a89 5170 #define RNG_INTENCLR_VALRDY_Msk (0x1UL << RNG_INTENCLR_VALRDY_Pos) /*!< Bit mask of VALRDY field. */
Kojto 91:031413cf7a89 5171 #define RNG_INTENCLR_VALRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5172 #define RNG_INTENCLR_VALRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5173 #define RNG_INTENCLR_VALRDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5174
Kojto 91:031413cf7a89 5175 /* Register: RNG_CONFIG */
Kojto 91:031413cf7a89 5176 /* Description: Configuration register. */
Kojto 91:031413cf7a89 5177
Kojto 91:031413cf7a89 5178 /* Bit 0 : Digital error correction enable. */
Kojto 91:031413cf7a89 5179 #define RNG_CONFIG_DERCEN_Pos (0UL) /*!< Position of DERCEN field. */
Kojto 91:031413cf7a89 5180 #define RNG_CONFIG_DERCEN_Msk (0x1UL << RNG_CONFIG_DERCEN_Pos) /*!< Bit mask of DERCEN field. */
Kojto 91:031413cf7a89 5181 #define RNG_CONFIG_DERCEN_Disabled (0UL) /*!< Digital error correction disabled. */
Kojto 91:031413cf7a89 5182 #define RNG_CONFIG_DERCEN_Enabled (1UL) /*!< Digital error correction enabled. */
Kojto 91:031413cf7a89 5183
Kojto 91:031413cf7a89 5184 /* Register: RNG_VALUE */
Kojto 91:031413cf7a89 5185 /* Description: RNG random number. */
Kojto 91:031413cf7a89 5186
Kojto 91:031413cf7a89 5187 /* Bits 7..0 : Generated random number. */
Kojto 91:031413cf7a89 5188 #define RNG_VALUE_VALUE_Pos (0UL) /*!< Position of VALUE field. */
Kojto 91:031413cf7a89 5189 #define RNG_VALUE_VALUE_Msk (0xFFUL << RNG_VALUE_VALUE_Pos) /*!< Bit mask of VALUE field. */
Kojto 91:031413cf7a89 5190
Kojto 91:031413cf7a89 5191 /* Register: RNG_POWER */
Kojto 91:031413cf7a89 5192 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 5193
Kojto 91:031413cf7a89 5194 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 5195 #define RNG_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 5196 #define RNG_POWER_POWER_Msk (0x1UL << RNG_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 5197 #define RNG_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 5198 #define RNG_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 5199
Kojto 91:031413cf7a89 5200
Kojto 91:031413cf7a89 5201 /* Peripheral: RTC */
Kojto 91:031413cf7a89 5202 /* Description: Real time counter 0. */
Kojto 91:031413cf7a89 5203
Kojto 91:031413cf7a89 5204 /* Register: RTC_INTENSET */
Kojto 91:031413cf7a89 5205 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 5206
Kojto 91:031413cf7a89 5207 /* Bit 19 : Enable interrupt on COMPARE[3] event. */
Kojto 91:031413cf7a89 5208 #define RTC_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 91:031413cf7a89 5209 #define RTC_INTENSET_COMPARE3_Msk (0x1UL << RTC_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 91:031413cf7a89 5210 #define RTC_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5211 #define RTC_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5212 #define RTC_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5213
Kojto 91:031413cf7a89 5214 /* Bit 18 : Enable interrupt on COMPARE[2] event. */
Kojto 91:031413cf7a89 5215 #define RTC_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 91:031413cf7a89 5216 #define RTC_INTENSET_COMPARE2_Msk (0x1UL << RTC_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 91:031413cf7a89 5217 #define RTC_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5218 #define RTC_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5219 #define RTC_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5220
Kojto 91:031413cf7a89 5221 /* Bit 17 : Enable interrupt on COMPARE[1] event. */
Kojto 91:031413cf7a89 5222 #define RTC_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 91:031413cf7a89 5223 #define RTC_INTENSET_COMPARE1_Msk (0x1UL << RTC_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 91:031413cf7a89 5224 #define RTC_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5225 #define RTC_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5226 #define RTC_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5227
Kojto 91:031413cf7a89 5228 /* Bit 16 : Enable interrupt on COMPARE[0] event. */
Kojto 91:031413cf7a89 5229 #define RTC_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 91:031413cf7a89 5230 #define RTC_INTENSET_COMPARE0_Msk (0x1UL << RTC_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 91:031413cf7a89 5231 #define RTC_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5232 #define RTC_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5233 #define RTC_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5234
Kojto 91:031413cf7a89 5235 /* Bit 1 : Enable interrupt on OVRFLW event. */
Kojto 91:031413cf7a89 5236 #define RTC_INTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 91:031413cf7a89 5237 #define RTC_INTENSET_OVRFLW_Msk (0x1UL << RTC_INTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 91:031413cf7a89 5238 #define RTC_INTENSET_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5239 #define RTC_INTENSET_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5240 #define RTC_INTENSET_OVRFLW_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5241
Kojto 91:031413cf7a89 5242 /* Bit 0 : Enable interrupt on TICK event. */
Kojto 91:031413cf7a89 5243 #define RTC_INTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 91:031413cf7a89 5244 #define RTC_INTENSET_TICK_Msk (0x1UL << RTC_INTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 91:031413cf7a89 5245 #define RTC_INTENSET_TICK_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5246 #define RTC_INTENSET_TICK_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5247 #define RTC_INTENSET_TICK_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5248
Kojto 91:031413cf7a89 5249 /* Register: RTC_INTENCLR */
Kojto 91:031413cf7a89 5250 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 5251
Kojto 91:031413cf7a89 5252 /* Bit 19 : Disable interrupt on COMPARE[3] event. */
Kojto 91:031413cf7a89 5253 #define RTC_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 91:031413cf7a89 5254 #define RTC_INTENCLR_COMPARE3_Msk (0x1UL << RTC_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 91:031413cf7a89 5255 #define RTC_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5256 #define RTC_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5257 #define RTC_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5258
Kojto 91:031413cf7a89 5259 /* Bit 18 : Disable interrupt on COMPARE[2] event. */
Kojto 91:031413cf7a89 5260 #define RTC_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 91:031413cf7a89 5261 #define RTC_INTENCLR_COMPARE2_Msk (0x1UL << RTC_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 91:031413cf7a89 5262 #define RTC_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5263 #define RTC_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5264 #define RTC_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5265
Kojto 91:031413cf7a89 5266 /* Bit 17 : Disable interrupt on COMPARE[1] event. */
Kojto 91:031413cf7a89 5267 #define RTC_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 91:031413cf7a89 5268 #define RTC_INTENCLR_COMPARE1_Msk (0x1UL << RTC_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 91:031413cf7a89 5269 #define RTC_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5270 #define RTC_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5271 #define RTC_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5272
Kojto 91:031413cf7a89 5273 /* Bit 16 : Disable interrupt on COMPARE[0] event. */
Kojto 91:031413cf7a89 5274 #define RTC_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 91:031413cf7a89 5275 #define RTC_INTENCLR_COMPARE0_Msk (0x1UL << RTC_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 91:031413cf7a89 5276 #define RTC_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5277 #define RTC_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5278 #define RTC_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5279
Kojto 91:031413cf7a89 5280 /* Bit 1 : Disable interrupt on OVRFLW event. */
Kojto 91:031413cf7a89 5281 #define RTC_INTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 91:031413cf7a89 5282 #define RTC_INTENCLR_OVRFLW_Msk (0x1UL << RTC_INTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 91:031413cf7a89 5283 #define RTC_INTENCLR_OVRFLW_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5284 #define RTC_INTENCLR_OVRFLW_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5285 #define RTC_INTENCLR_OVRFLW_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5286
Kojto 91:031413cf7a89 5287 /* Bit 0 : Disable interrupt on TICK event. */
Kojto 91:031413cf7a89 5288 #define RTC_INTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 91:031413cf7a89 5289 #define RTC_INTENCLR_TICK_Msk (0x1UL << RTC_INTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 91:031413cf7a89 5290 #define RTC_INTENCLR_TICK_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5291 #define RTC_INTENCLR_TICK_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5292 #define RTC_INTENCLR_TICK_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5293
Kojto 91:031413cf7a89 5294 /* Register: RTC_EVTEN */
Kojto 91:031413cf7a89 5295 /* Description: Configures event enable routing to PPI for each RTC event. */
Kojto 91:031413cf7a89 5296
Kojto 91:031413cf7a89 5297 /* Bit 19 : COMPARE[3] event enable. */
Kojto 91:031413cf7a89 5298 #define RTC_EVTEN_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 91:031413cf7a89 5299 #define RTC_EVTEN_COMPARE3_Msk (0x1UL << RTC_EVTEN_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 91:031413cf7a89 5300 #define RTC_EVTEN_COMPARE3_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5301 #define RTC_EVTEN_COMPARE3_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5302
Kojto 91:031413cf7a89 5303 /* Bit 18 : COMPARE[2] event enable. */
Kojto 91:031413cf7a89 5304 #define RTC_EVTEN_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 91:031413cf7a89 5305 #define RTC_EVTEN_COMPARE2_Msk (0x1UL << RTC_EVTEN_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 91:031413cf7a89 5306 #define RTC_EVTEN_COMPARE2_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5307 #define RTC_EVTEN_COMPARE2_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5308
Kojto 91:031413cf7a89 5309 /* Bit 17 : COMPARE[1] event enable. */
Kojto 91:031413cf7a89 5310 #define RTC_EVTEN_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 91:031413cf7a89 5311 #define RTC_EVTEN_COMPARE1_Msk (0x1UL << RTC_EVTEN_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 91:031413cf7a89 5312 #define RTC_EVTEN_COMPARE1_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5313 #define RTC_EVTEN_COMPARE1_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5314
Kojto 91:031413cf7a89 5315 /* Bit 16 : COMPARE[0] event enable. */
Kojto 91:031413cf7a89 5316 #define RTC_EVTEN_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 91:031413cf7a89 5317 #define RTC_EVTEN_COMPARE0_Msk (0x1UL << RTC_EVTEN_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 91:031413cf7a89 5318 #define RTC_EVTEN_COMPARE0_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5319 #define RTC_EVTEN_COMPARE0_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5320
Kojto 91:031413cf7a89 5321 /* Bit 1 : OVRFLW event enable. */
Kojto 91:031413cf7a89 5322 #define RTC_EVTEN_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 91:031413cf7a89 5323 #define RTC_EVTEN_OVRFLW_Msk (0x1UL << RTC_EVTEN_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 91:031413cf7a89 5324 #define RTC_EVTEN_OVRFLW_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5325 #define RTC_EVTEN_OVRFLW_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5326
Kojto 91:031413cf7a89 5327 /* Bit 0 : TICK event enable. */
Kojto 91:031413cf7a89 5328 #define RTC_EVTEN_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 91:031413cf7a89 5329 #define RTC_EVTEN_TICK_Msk (0x1UL << RTC_EVTEN_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 91:031413cf7a89 5330 #define RTC_EVTEN_TICK_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5331 #define RTC_EVTEN_TICK_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5332
Kojto 91:031413cf7a89 5333 /* Register: RTC_EVTENSET */
Kojto 91:031413cf7a89 5334 /* Description: Enable events routing to PPI. The reading of this register gives the value of EVTEN. */
Kojto 91:031413cf7a89 5335
Kojto 91:031413cf7a89 5336 /* Bit 19 : Enable routing to PPI of COMPARE[3] event. */
Kojto 91:031413cf7a89 5337 #define RTC_EVTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 91:031413cf7a89 5338 #define RTC_EVTENSET_COMPARE3_Msk (0x1UL << RTC_EVTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 91:031413cf7a89 5339 #define RTC_EVTENSET_COMPARE3_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5340 #define RTC_EVTENSET_COMPARE3_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5341 #define RTC_EVTENSET_COMPARE3_Set (1UL) /*!< Enable event on write. */
Kojto 91:031413cf7a89 5342
Kojto 91:031413cf7a89 5343 /* Bit 18 : Enable routing to PPI of COMPARE[2] event. */
Kojto 91:031413cf7a89 5344 #define RTC_EVTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 91:031413cf7a89 5345 #define RTC_EVTENSET_COMPARE2_Msk (0x1UL << RTC_EVTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 91:031413cf7a89 5346 #define RTC_EVTENSET_COMPARE2_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5347 #define RTC_EVTENSET_COMPARE2_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5348 #define RTC_EVTENSET_COMPARE2_Set (1UL) /*!< Enable event on write. */
Kojto 91:031413cf7a89 5349
Kojto 91:031413cf7a89 5350 /* Bit 17 : Enable routing to PPI of COMPARE[1] event. */
Kojto 91:031413cf7a89 5351 #define RTC_EVTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 91:031413cf7a89 5352 #define RTC_EVTENSET_COMPARE1_Msk (0x1UL << RTC_EVTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 91:031413cf7a89 5353 #define RTC_EVTENSET_COMPARE1_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5354 #define RTC_EVTENSET_COMPARE1_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5355 #define RTC_EVTENSET_COMPARE1_Set (1UL) /*!< Enable event on write. */
Kojto 91:031413cf7a89 5356
Kojto 91:031413cf7a89 5357 /* Bit 16 : Enable routing to PPI of COMPARE[0] event. */
Kojto 91:031413cf7a89 5358 #define RTC_EVTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 91:031413cf7a89 5359 #define RTC_EVTENSET_COMPARE0_Msk (0x1UL << RTC_EVTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 91:031413cf7a89 5360 #define RTC_EVTENSET_COMPARE0_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5361 #define RTC_EVTENSET_COMPARE0_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5362 #define RTC_EVTENSET_COMPARE0_Set (1UL) /*!< Enable event on write. */
Kojto 91:031413cf7a89 5363
Kojto 91:031413cf7a89 5364 /* Bit 1 : Enable routing to PPI of OVRFLW event. */
Kojto 91:031413cf7a89 5365 #define RTC_EVTENSET_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 91:031413cf7a89 5366 #define RTC_EVTENSET_OVRFLW_Msk (0x1UL << RTC_EVTENSET_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 91:031413cf7a89 5367 #define RTC_EVTENSET_OVRFLW_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5368 #define RTC_EVTENSET_OVRFLW_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5369 #define RTC_EVTENSET_OVRFLW_Set (1UL) /*!< Enable event on write. */
Kojto 91:031413cf7a89 5370
Kojto 91:031413cf7a89 5371 /* Bit 0 : Enable routing to PPI of TICK event. */
Kojto 91:031413cf7a89 5372 #define RTC_EVTENSET_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 91:031413cf7a89 5373 #define RTC_EVTENSET_TICK_Msk (0x1UL << RTC_EVTENSET_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 91:031413cf7a89 5374 #define RTC_EVTENSET_TICK_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5375 #define RTC_EVTENSET_TICK_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5376 #define RTC_EVTENSET_TICK_Set (1UL) /*!< Enable event on write. */
Kojto 91:031413cf7a89 5377
Kojto 91:031413cf7a89 5378 /* Register: RTC_EVTENCLR */
Kojto 91:031413cf7a89 5379 /* Description: Disable events routing to PPI. The reading of this register gives the value of EVTEN. */
Kojto 91:031413cf7a89 5380
Kojto 91:031413cf7a89 5381 /* Bit 19 : Disable routing to PPI of COMPARE[3] event. */
Kojto 91:031413cf7a89 5382 #define RTC_EVTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 91:031413cf7a89 5383 #define RTC_EVTENCLR_COMPARE3_Msk (0x1UL << RTC_EVTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 91:031413cf7a89 5384 #define RTC_EVTENCLR_COMPARE3_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5385 #define RTC_EVTENCLR_COMPARE3_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5386 #define RTC_EVTENCLR_COMPARE3_Clear (1UL) /*!< Disable event on write. */
Kojto 91:031413cf7a89 5387
Kojto 91:031413cf7a89 5388 /* Bit 18 : Disable routing to PPI of COMPARE[2] event. */
Kojto 91:031413cf7a89 5389 #define RTC_EVTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 91:031413cf7a89 5390 #define RTC_EVTENCLR_COMPARE2_Msk (0x1UL << RTC_EVTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 91:031413cf7a89 5391 #define RTC_EVTENCLR_COMPARE2_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5392 #define RTC_EVTENCLR_COMPARE2_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5393 #define RTC_EVTENCLR_COMPARE2_Clear (1UL) /*!< Disable event on write. */
Kojto 91:031413cf7a89 5394
Kojto 91:031413cf7a89 5395 /* Bit 17 : Disable routing to PPI of COMPARE[1] event. */
Kojto 91:031413cf7a89 5396 #define RTC_EVTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 91:031413cf7a89 5397 #define RTC_EVTENCLR_COMPARE1_Msk (0x1UL << RTC_EVTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 91:031413cf7a89 5398 #define RTC_EVTENCLR_COMPARE1_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5399 #define RTC_EVTENCLR_COMPARE1_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5400 #define RTC_EVTENCLR_COMPARE1_Clear (1UL) /*!< Disable event on write. */
Kojto 91:031413cf7a89 5401
Kojto 91:031413cf7a89 5402 /* Bit 16 : Disable routing to PPI of COMPARE[0] event. */
Kojto 91:031413cf7a89 5403 #define RTC_EVTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 91:031413cf7a89 5404 #define RTC_EVTENCLR_COMPARE0_Msk (0x1UL << RTC_EVTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 91:031413cf7a89 5405 #define RTC_EVTENCLR_COMPARE0_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5406 #define RTC_EVTENCLR_COMPARE0_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5407 #define RTC_EVTENCLR_COMPARE0_Clear (1UL) /*!< Disable event on write. */
Kojto 91:031413cf7a89 5408
Kojto 91:031413cf7a89 5409 /* Bit 1 : Disable routing to PPI of OVRFLW event. */
Kojto 91:031413cf7a89 5410 #define RTC_EVTENCLR_OVRFLW_Pos (1UL) /*!< Position of OVRFLW field. */
Kojto 91:031413cf7a89 5411 #define RTC_EVTENCLR_OVRFLW_Msk (0x1UL << RTC_EVTENCLR_OVRFLW_Pos) /*!< Bit mask of OVRFLW field. */
Kojto 91:031413cf7a89 5412 #define RTC_EVTENCLR_OVRFLW_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5413 #define RTC_EVTENCLR_OVRFLW_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5414 #define RTC_EVTENCLR_OVRFLW_Clear (1UL) /*!< Disable event on write. */
Kojto 91:031413cf7a89 5415
Kojto 91:031413cf7a89 5416 /* Bit 0 : Disable routing to PPI of TICK event. */
Kojto 91:031413cf7a89 5417 #define RTC_EVTENCLR_TICK_Pos (0UL) /*!< Position of TICK field. */
Kojto 91:031413cf7a89 5418 #define RTC_EVTENCLR_TICK_Msk (0x1UL << RTC_EVTENCLR_TICK_Pos) /*!< Bit mask of TICK field. */
Kojto 91:031413cf7a89 5419 #define RTC_EVTENCLR_TICK_Disabled (0UL) /*!< Event disabled. */
Kojto 91:031413cf7a89 5420 #define RTC_EVTENCLR_TICK_Enabled (1UL) /*!< Event enabled. */
Kojto 91:031413cf7a89 5421 #define RTC_EVTENCLR_TICK_Clear (1UL) /*!< Disable event on write. */
Kojto 91:031413cf7a89 5422
Kojto 91:031413cf7a89 5423 /* Register: RTC_COUNTER */
Kojto 91:031413cf7a89 5424 /* Description: Current COUNTER value. */
Kojto 91:031413cf7a89 5425
Kojto 91:031413cf7a89 5426 /* Bits 23..0 : Counter value. */
Kojto 91:031413cf7a89 5427 #define RTC_COUNTER_COUNTER_Pos (0UL) /*!< Position of COUNTER field. */
Kojto 91:031413cf7a89 5428 #define RTC_COUNTER_COUNTER_Msk (0xFFFFFFUL << RTC_COUNTER_COUNTER_Pos) /*!< Bit mask of COUNTER field. */
Kojto 91:031413cf7a89 5429
Kojto 91:031413cf7a89 5430 /* Register: RTC_PRESCALER */
Kojto 91:031413cf7a89 5431 /* Description: 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)). Must be written when RTC is STOPed. */
Kojto 91:031413cf7a89 5432
Kojto 91:031413cf7a89 5433 /* Bits 11..0 : RTC PRESCALER value. */
Kojto 91:031413cf7a89 5434 #define RTC_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
Kojto 91:031413cf7a89 5435 #define RTC_PRESCALER_PRESCALER_Msk (0xFFFUL << RTC_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
Kojto 91:031413cf7a89 5436
Kojto 91:031413cf7a89 5437 /* Register: RTC_CC */
Kojto 91:031413cf7a89 5438 /* Description: Capture/compare registers. */
Kojto 91:031413cf7a89 5439
Kojto 91:031413cf7a89 5440 /* Bits 23..0 : Compare value. */
Kojto 91:031413cf7a89 5441 #define RTC_CC_COMPARE_Pos (0UL) /*!< Position of COMPARE field. */
Kojto 91:031413cf7a89 5442 #define RTC_CC_COMPARE_Msk (0xFFFFFFUL << RTC_CC_COMPARE_Pos) /*!< Bit mask of COMPARE field. */
Kojto 91:031413cf7a89 5443
Kojto 91:031413cf7a89 5444 /* Register: RTC_POWER */
Kojto 91:031413cf7a89 5445 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 5446
Kojto 91:031413cf7a89 5447 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 5448 #define RTC_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 5449 #define RTC_POWER_POWER_Msk (0x1UL << RTC_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 5450 #define RTC_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 5451 #define RTC_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 5452
Kojto 91:031413cf7a89 5453
Kojto 91:031413cf7a89 5454 /* Peripheral: SPI */
Kojto 91:031413cf7a89 5455 /* Description: SPI master 0. */
Kojto 91:031413cf7a89 5456
Kojto 91:031413cf7a89 5457 /* Register: SPI_INTENSET */
Kojto 91:031413cf7a89 5458 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 5459
Kojto 91:031413cf7a89 5460 /* Bit 2 : Enable interrupt on READY event. */
Kojto 91:031413cf7a89 5461 #define SPI_INTENSET_READY_Pos (2UL) /*!< Position of READY field. */
Kojto 91:031413cf7a89 5462 #define SPI_INTENSET_READY_Msk (0x1UL << SPI_INTENSET_READY_Pos) /*!< Bit mask of READY field. */
Kojto 91:031413cf7a89 5463 #define SPI_INTENSET_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5464 #define SPI_INTENSET_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5465 #define SPI_INTENSET_READY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5466
Kojto 91:031413cf7a89 5467 /* Register: SPI_INTENCLR */
Kojto 91:031413cf7a89 5468 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 5469
Kojto 91:031413cf7a89 5470 /* Bit 2 : Disable interrupt on READY event. */
Kojto 91:031413cf7a89 5471 #define SPI_INTENCLR_READY_Pos (2UL) /*!< Position of READY field. */
Kojto 91:031413cf7a89 5472 #define SPI_INTENCLR_READY_Msk (0x1UL << SPI_INTENCLR_READY_Pos) /*!< Bit mask of READY field. */
Kojto 91:031413cf7a89 5473 #define SPI_INTENCLR_READY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5474 #define SPI_INTENCLR_READY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5475 #define SPI_INTENCLR_READY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5476
Kojto 91:031413cf7a89 5477 /* Register: SPI_ENABLE */
Kojto 91:031413cf7a89 5478 /* Description: Enable SPI. */
Kojto 91:031413cf7a89 5479
Kojto 91:031413cf7a89 5480 /* Bits 2..0 : Enable or disable SPI. */
Kojto 91:031413cf7a89 5481 #define SPI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 5482 #define SPI_ENABLE_ENABLE_Msk (0x7UL << SPI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 5483 #define SPI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPI. */
Kojto 91:031413cf7a89 5484 #define SPI_ENABLE_ENABLE_Enabled (0x01UL) /*!< Enable SPI. */
Kojto 91:031413cf7a89 5485
Kojto 91:031413cf7a89 5486 /* Register: SPI_RXD */
Kojto 91:031413cf7a89 5487 /* Description: RX data. */
Kojto 91:031413cf7a89 5488
Kojto 91:031413cf7a89 5489 /* Bits 7..0 : RX data from last transfer. */
Kojto 91:031413cf7a89 5490 #define SPI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
Kojto 91:031413cf7a89 5491 #define SPI_RXD_RXD_Msk (0xFFUL << SPI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
Kojto 91:031413cf7a89 5492
Kojto 91:031413cf7a89 5493 /* Register: SPI_TXD */
Kojto 91:031413cf7a89 5494 /* Description: TX data. */
Kojto 91:031413cf7a89 5495
Kojto 91:031413cf7a89 5496 /* Bits 7..0 : TX data for next transfer. */
Kojto 91:031413cf7a89 5497 #define SPI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
Kojto 91:031413cf7a89 5498 #define SPI_TXD_TXD_Msk (0xFFUL << SPI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
Kojto 91:031413cf7a89 5499
Kojto 91:031413cf7a89 5500 /* Register: SPI_FREQUENCY */
Kojto 91:031413cf7a89 5501 /* Description: SPI frequency */
Kojto 91:031413cf7a89 5502
Kojto 91:031413cf7a89 5503 /* Bits 31..0 : SPI data rate. */
Kojto 91:031413cf7a89 5504 #define SPI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Kojto 91:031413cf7a89 5505 #define SPI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << SPI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Kojto 91:031413cf7a89 5506 #define SPI_FREQUENCY_FREQUENCY_K125 (0x02000000UL) /*!< 125kbps. */
Kojto 91:031413cf7a89 5507 #define SPI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250kbps. */
Kojto 91:031413cf7a89 5508 #define SPI_FREQUENCY_FREQUENCY_K500 (0x08000000UL) /*!< 500kbps. */
Kojto 91:031413cf7a89 5509 #define SPI_FREQUENCY_FREQUENCY_M1 (0x10000000UL) /*!< 1Mbps. */
Kojto 91:031413cf7a89 5510 #define SPI_FREQUENCY_FREQUENCY_M2 (0x20000000UL) /*!< 2Mbps. */
Kojto 91:031413cf7a89 5511 #define SPI_FREQUENCY_FREQUENCY_M4 (0x40000000UL) /*!< 4Mbps. */
Kojto 91:031413cf7a89 5512 #define SPI_FREQUENCY_FREQUENCY_M8 (0x80000000UL) /*!< 8Mbps. */
Kojto 91:031413cf7a89 5513
Kojto 91:031413cf7a89 5514 /* Register: SPI_CONFIG */
Kojto 91:031413cf7a89 5515 /* Description: Configuration register. */
Kojto 91:031413cf7a89 5516
Kojto 91:031413cf7a89 5517 /* Bit 2 : Serial clock (SCK) polarity. */
Kojto 91:031413cf7a89 5518 #define SPI_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
Kojto 91:031413cf7a89 5519 #define SPI_CONFIG_CPOL_Msk (0x1UL << SPI_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
Kojto 91:031413cf7a89 5520 #define SPI_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
Kojto 91:031413cf7a89 5521 #define SPI_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
Kojto 91:031413cf7a89 5522
Kojto 91:031413cf7a89 5523 /* Bit 1 : Serial clock (SCK) phase. */
Kojto 91:031413cf7a89 5524 #define SPI_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
Kojto 91:031413cf7a89 5525 #define SPI_CONFIG_CPHA_Msk (0x1UL << SPI_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
Kojto 91:031413cf7a89 5526 #define SPI_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
Kojto 91:031413cf7a89 5527 #define SPI_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
Kojto 91:031413cf7a89 5528
Kojto 91:031413cf7a89 5529 /* Bit 0 : Bit order. */
Kojto 91:031413cf7a89 5530 #define SPI_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
Kojto 91:031413cf7a89 5531 #define SPI_CONFIG_ORDER_Msk (0x1UL << SPI_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
Kojto 91:031413cf7a89 5532 #define SPI_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
Kojto 91:031413cf7a89 5533 #define SPI_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
Kojto 91:031413cf7a89 5534
Kojto 91:031413cf7a89 5535 /* Register: SPI_POWER */
Kojto 91:031413cf7a89 5536 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 5537
Kojto 91:031413cf7a89 5538 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 5539 #define SPI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 5540 #define SPI_POWER_POWER_Msk (0x1UL << SPI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 5541 #define SPI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 5542 #define SPI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 5543
Kojto 91:031413cf7a89 5544
Kojto 91:031413cf7a89 5545 /* Peripheral: SPIS */
Kojto 91:031413cf7a89 5546 /* Description: SPI slave 1. */
Kojto 91:031413cf7a89 5547
Kojto 91:031413cf7a89 5548 /* Register: SPIS_SHORTS */
Kojto 91:031413cf7a89 5549 /* Description: Shortcuts for SPIS. */
Kojto 91:031413cf7a89 5550
Kojto 91:031413cf7a89 5551 /* Bit 2 : Shortcut between END event and the ACQUIRE task. */
Kojto 91:031413cf7a89 5552 #define SPIS_SHORTS_END_ACQUIRE_Pos (2UL) /*!< Position of END_ACQUIRE field. */
Kojto 91:031413cf7a89 5553 #define SPIS_SHORTS_END_ACQUIRE_Msk (0x1UL << SPIS_SHORTS_END_ACQUIRE_Pos) /*!< Bit mask of END_ACQUIRE field. */
Kojto 91:031413cf7a89 5554 #define SPIS_SHORTS_END_ACQUIRE_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5555 #define SPIS_SHORTS_END_ACQUIRE_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5556
Kojto 91:031413cf7a89 5557 /* Register: SPIS_INTENSET */
Kojto 91:031413cf7a89 5558 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 5559
Kojto 91:031413cf7a89 5560 /* Bit 10 : Enable interrupt on ACQUIRED event. */
Kojto 91:031413cf7a89 5561 #define SPIS_INTENSET_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
Kojto 91:031413cf7a89 5562 #define SPIS_INTENSET_ACQUIRED_Msk (0x1UL << SPIS_INTENSET_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
Kojto 91:031413cf7a89 5563 #define SPIS_INTENSET_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5564 #define SPIS_INTENSET_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5565 #define SPIS_INTENSET_ACQUIRED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5566
Kojto 91:031413cf7a89 5567 /* Bit 1 : Enable interrupt on END event. */
Kojto 91:031413cf7a89 5568 #define SPIS_INTENSET_END_Pos (1UL) /*!< Position of END field. */
Kojto 91:031413cf7a89 5569 #define SPIS_INTENSET_END_Msk (0x1UL << SPIS_INTENSET_END_Pos) /*!< Bit mask of END field. */
Kojto 91:031413cf7a89 5570 #define SPIS_INTENSET_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5571 #define SPIS_INTENSET_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5572 #define SPIS_INTENSET_END_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5573
Kojto 91:031413cf7a89 5574 /* Register: SPIS_INTENCLR */
Kojto 91:031413cf7a89 5575 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 5576
Kojto 91:031413cf7a89 5577 /* Bit 10 : Disable interrupt on ACQUIRED event. */
Kojto 91:031413cf7a89 5578 #define SPIS_INTENCLR_ACQUIRED_Pos (10UL) /*!< Position of ACQUIRED field. */
Kojto 91:031413cf7a89 5579 #define SPIS_INTENCLR_ACQUIRED_Msk (0x1UL << SPIS_INTENCLR_ACQUIRED_Pos) /*!< Bit mask of ACQUIRED field. */
Kojto 91:031413cf7a89 5580 #define SPIS_INTENCLR_ACQUIRED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5581 #define SPIS_INTENCLR_ACQUIRED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5582 #define SPIS_INTENCLR_ACQUIRED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5583
Kojto 91:031413cf7a89 5584 /* Bit 1 : Disable interrupt on END event. */
Kojto 91:031413cf7a89 5585 #define SPIS_INTENCLR_END_Pos (1UL) /*!< Position of END field. */
Kojto 91:031413cf7a89 5586 #define SPIS_INTENCLR_END_Msk (0x1UL << SPIS_INTENCLR_END_Pos) /*!< Bit mask of END field. */
Kojto 91:031413cf7a89 5587 #define SPIS_INTENCLR_END_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5588 #define SPIS_INTENCLR_END_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5589 #define SPIS_INTENCLR_END_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5590
Kojto 91:031413cf7a89 5591 /* Register: SPIS_SEMSTAT */
Kojto 91:031413cf7a89 5592 /* Description: Semaphore status. */
Kojto 91:031413cf7a89 5593
Kojto 91:031413cf7a89 5594 /* Bits 1..0 : Semaphore status. */
Kojto 91:031413cf7a89 5595 #define SPIS_SEMSTAT_SEMSTAT_Pos (0UL) /*!< Position of SEMSTAT field. */
Kojto 91:031413cf7a89 5596 #define SPIS_SEMSTAT_SEMSTAT_Msk (0x3UL << SPIS_SEMSTAT_SEMSTAT_Pos) /*!< Bit mask of SEMSTAT field. */
Kojto 91:031413cf7a89 5597 #define SPIS_SEMSTAT_SEMSTAT_Free (0x00UL) /*!< Semaphore is free. */
Kojto 91:031413cf7a89 5598 #define SPIS_SEMSTAT_SEMSTAT_CPU (0x01UL) /*!< Semaphore is assigned to the CPU. */
Kojto 91:031413cf7a89 5599 #define SPIS_SEMSTAT_SEMSTAT_SPIS (0x02UL) /*!< Semaphore is assigned to the SPIS. */
Kojto 91:031413cf7a89 5600 #define SPIS_SEMSTAT_SEMSTAT_CPUPending (0x03UL) /*!< Semaphore is assigned to the SPIS, but a handover to the CPU is pending. */
Kojto 91:031413cf7a89 5601
Kojto 91:031413cf7a89 5602 /* Register: SPIS_STATUS */
Kojto 91:031413cf7a89 5603 /* Description: Status from last transaction. */
Kojto 91:031413cf7a89 5604
Kojto 91:031413cf7a89 5605 /* Bit 1 : RX buffer overflow detected, and prevented. */
Kojto 91:031413cf7a89 5606 #define SPIS_STATUS_OVERFLOW_Pos (1UL) /*!< Position of OVERFLOW field. */
Kojto 91:031413cf7a89 5607 #define SPIS_STATUS_OVERFLOW_Msk (0x1UL << SPIS_STATUS_OVERFLOW_Pos) /*!< Bit mask of OVERFLOW field. */
Kojto 91:031413cf7a89 5608 #define SPIS_STATUS_OVERFLOW_NotPresent (0UL) /*!< Error not present. */
Kojto 91:031413cf7a89 5609 #define SPIS_STATUS_OVERFLOW_Present (1UL) /*!< Error present. */
Kojto 91:031413cf7a89 5610 #define SPIS_STATUS_OVERFLOW_Clear (1UL) /*!< Clear on write. */
Kojto 91:031413cf7a89 5611
Kojto 91:031413cf7a89 5612 /* Bit 0 : TX buffer overread detected, and prevented. */
Kojto 91:031413cf7a89 5613 #define SPIS_STATUS_OVERREAD_Pos (0UL) /*!< Position of OVERREAD field. */
Kojto 91:031413cf7a89 5614 #define SPIS_STATUS_OVERREAD_Msk (0x1UL << SPIS_STATUS_OVERREAD_Pos) /*!< Bit mask of OVERREAD field. */
Kojto 91:031413cf7a89 5615 #define SPIS_STATUS_OVERREAD_NotPresent (0UL) /*!< Error not present. */
Kojto 91:031413cf7a89 5616 #define SPIS_STATUS_OVERREAD_Present (1UL) /*!< Error present. */
Kojto 91:031413cf7a89 5617 #define SPIS_STATUS_OVERREAD_Clear (1UL) /*!< Clear on write. */
Kojto 91:031413cf7a89 5618
Kojto 91:031413cf7a89 5619 /* Register: SPIS_ENABLE */
Kojto 91:031413cf7a89 5620 /* Description: Enable SPIS. */
Kojto 91:031413cf7a89 5621
Kojto 91:031413cf7a89 5622 /* Bits 2..0 : Enable or disable SPIS. */
Kojto 91:031413cf7a89 5623 #define SPIS_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 5624 #define SPIS_ENABLE_ENABLE_Msk (0x7UL << SPIS_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 5625 #define SPIS_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled SPIS. */
Kojto 91:031413cf7a89 5626 #define SPIS_ENABLE_ENABLE_Enabled (0x02UL) /*!< Enable SPIS. */
Kojto 91:031413cf7a89 5627
Kojto 91:031413cf7a89 5628 /* Register: SPIS_MAXRX */
Kojto 91:031413cf7a89 5629 /* Description: Maximum number of bytes in the receive buffer. */
Kojto 91:031413cf7a89 5630
Kojto 91:031413cf7a89 5631 /* Bits 7..0 : Maximum number of bytes in the receive buffer. */
Kojto 91:031413cf7a89 5632 #define SPIS_MAXRX_MAXRX_Pos (0UL) /*!< Position of MAXRX field. */
Kojto 91:031413cf7a89 5633 #define SPIS_MAXRX_MAXRX_Msk (0xFFUL << SPIS_MAXRX_MAXRX_Pos) /*!< Bit mask of MAXRX field. */
Kojto 91:031413cf7a89 5634
Kojto 91:031413cf7a89 5635 /* Register: SPIS_AMOUNTRX */
Kojto 91:031413cf7a89 5636 /* Description: Number of bytes received in last granted transaction. */
Kojto 91:031413cf7a89 5637
Kojto 91:031413cf7a89 5638 /* Bits 7..0 : Number of bytes received in last granted transaction. */
Kojto 91:031413cf7a89 5639 #define SPIS_AMOUNTRX_AMOUNTRX_Pos (0UL) /*!< Position of AMOUNTRX field. */
Kojto 91:031413cf7a89 5640 #define SPIS_AMOUNTRX_AMOUNTRX_Msk (0xFFUL << SPIS_AMOUNTRX_AMOUNTRX_Pos) /*!< Bit mask of AMOUNTRX field. */
Kojto 91:031413cf7a89 5641
Kojto 91:031413cf7a89 5642 /* Register: SPIS_MAXTX */
Kojto 91:031413cf7a89 5643 /* Description: Maximum number of bytes in the transmit buffer. */
Kojto 91:031413cf7a89 5644
Kojto 91:031413cf7a89 5645 /* Bits 7..0 : Maximum number of bytes in the transmit buffer. */
Kojto 91:031413cf7a89 5646 #define SPIS_MAXTX_MAXTX_Pos (0UL) /*!< Position of MAXTX field. */
Kojto 91:031413cf7a89 5647 #define SPIS_MAXTX_MAXTX_Msk (0xFFUL << SPIS_MAXTX_MAXTX_Pos) /*!< Bit mask of MAXTX field. */
Kojto 91:031413cf7a89 5648
Kojto 91:031413cf7a89 5649 /* Register: SPIS_AMOUNTTX */
Kojto 91:031413cf7a89 5650 /* Description: Number of bytes transmitted in last granted transaction. */
Kojto 91:031413cf7a89 5651
Kojto 91:031413cf7a89 5652 /* Bits 7..0 : Number of bytes transmitted in last granted transaction. */
Kojto 91:031413cf7a89 5653 #define SPIS_AMOUNTTX_AMOUNTTX_Pos (0UL) /*!< Position of AMOUNTTX field. */
Kojto 91:031413cf7a89 5654 #define SPIS_AMOUNTTX_AMOUNTTX_Msk (0xFFUL << SPIS_AMOUNTTX_AMOUNTTX_Pos) /*!< Bit mask of AMOUNTTX field. */
Kojto 91:031413cf7a89 5655
Kojto 91:031413cf7a89 5656 /* Register: SPIS_CONFIG */
Kojto 91:031413cf7a89 5657 /* Description: Configuration register. */
Kojto 91:031413cf7a89 5658
Kojto 91:031413cf7a89 5659 /* Bit 2 : Serial clock (SCK) polarity. */
Kojto 91:031413cf7a89 5660 #define SPIS_CONFIG_CPOL_Pos (2UL) /*!< Position of CPOL field. */
Kojto 91:031413cf7a89 5661 #define SPIS_CONFIG_CPOL_Msk (0x1UL << SPIS_CONFIG_CPOL_Pos) /*!< Bit mask of CPOL field. */
Kojto 91:031413cf7a89 5662 #define SPIS_CONFIG_CPOL_ActiveHigh (0UL) /*!< Active high. */
Kojto 91:031413cf7a89 5663 #define SPIS_CONFIG_CPOL_ActiveLow (1UL) /*!< Active low. */
Kojto 91:031413cf7a89 5664
Kojto 91:031413cf7a89 5665 /* Bit 1 : Serial clock (SCK) phase. */
Kojto 91:031413cf7a89 5666 #define SPIS_CONFIG_CPHA_Pos (1UL) /*!< Position of CPHA field. */
Kojto 91:031413cf7a89 5667 #define SPIS_CONFIG_CPHA_Msk (0x1UL << SPIS_CONFIG_CPHA_Pos) /*!< Bit mask of CPHA field. */
Kojto 91:031413cf7a89 5668 #define SPIS_CONFIG_CPHA_Leading (0UL) /*!< Sample on leading edge of the clock. Shift serial data on trailing edge. */
Kojto 91:031413cf7a89 5669 #define SPIS_CONFIG_CPHA_Trailing (1UL) /*!< Sample on trailing edge of the clock. Shift serial data on leading edge. */
Kojto 91:031413cf7a89 5670
Kojto 91:031413cf7a89 5671 /* Bit 0 : Bit order. */
Kojto 91:031413cf7a89 5672 #define SPIS_CONFIG_ORDER_Pos (0UL) /*!< Position of ORDER field. */
Kojto 91:031413cf7a89 5673 #define SPIS_CONFIG_ORDER_Msk (0x1UL << SPIS_CONFIG_ORDER_Pos) /*!< Bit mask of ORDER field. */
Kojto 91:031413cf7a89 5674 #define SPIS_CONFIG_ORDER_MsbFirst (0UL) /*!< Most significant bit transmitted out first. */
Kojto 91:031413cf7a89 5675 #define SPIS_CONFIG_ORDER_LsbFirst (1UL) /*!< Least significant bit transmitted out first. */
Kojto 91:031413cf7a89 5676
Kojto 91:031413cf7a89 5677 /* Register: SPIS_DEF */
Kojto 91:031413cf7a89 5678 /* Description: Default character. */
Kojto 91:031413cf7a89 5679
Kojto 91:031413cf7a89 5680 /* Bits 7..0 : Default character. */
Kojto 91:031413cf7a89 5681 #define SPIS_DEF_DEF_Pos (0UL) /*!< Position of DEF field. */
Kojto 91:031413cf7a89 5682 #define SPIS_DEF_DEF_Msk (0xFFUL << SPIS_DEF_DEF_Pos) /*!< Bit mask of DEF field. */
Kojto 91:031413cf7a89 5683
Kojto 91:031413cf7a89 5684 /* Register: SPIS_ORC */
Kojto 91:031413cf7a89 5685 /* Description: Over-read character. */
Kojto 91:031413cf7a89 5686
Kojto 91:031413cf7a89 5687 /* Bits 7..0 : Over-read character. */
Kojto 91:031413cf7a89 5688 #define SPIS_ORC_ORC_Pos (0UL) /*!< Position of ORC field. */
Kojto 91:031413cf7a89 5689 #define SPIS_ORC_ORC_Msk (0xFFUL << SPIS_ORC_ORC_Pos) /*!< Bit mask of ORC field. */
Kojto 91:031413cf7a89 5690
Kojto 91:031413cf7a89 5691 /* Register: SPIS_POWER */
Kojto 91:031413cf7a89 5692 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 5693
Kojto 91:031413cf7a89 5694 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 5695 #define SPIS_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 5696 #define SPIS_POWER_POWER_Msk (0x1UL << SPIS_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 5697 #define SPIS_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 5698 #define SPIS_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 5699
Kojto 91:031413cf7a89 5700
Kojto 91:031413cf7a89 5701 /* Peripheral: TEMP */
Kojto 91:031413cf7a89 5702 /* Description: Temperature Sensor. */
Kojto 91:031413cf7a89 5703
Kojto 91:031413cf7a89 5704 /* Register: TEMP_INTENSET */
Kojto 91:031413cf7a89 5705 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 5706
Kojto 91:031413cf7a89 5707 /* Bit 0 : Enable interrupt on DATARDY event. */
Kojto 91:031413cf7a89 5708 #define TEMP_INTENSET_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
Kojto 91:031413cf7a89 5709 #define TEMP_INTENSET_DATARDY_Msk (0x1UL << TEMP_INTENSET_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
Kojto 91:031413cf7a89 5710 #define TEMP_INTENSET_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5711 #define TEMP_INTENSET_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5712 #define TEMP_INTENSET_DATARDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5713
Kojto 91:031413cf7a89 5714 /* Register: TEMP_INTENCLR */
Kojto 91:031413cf7a89 5715 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 5716
Kojto 91:031413cf7a89 5717 /* Bit 0 : Disable interrupt on DATARDY event. */
Kojto 91:031413cf7a89 5718 #define TEMP_INTENCLR_DATARDY_Pos (0UL) /*!< Position of DATARDY field. */
Kojto 91:031413cf7a89 5719 #define TEMP_INTENCLR_DATARDY_Msk (0x1UL << TEMP_INTENCLR_DATARDY_Pos) /*!< Bit mask of DATARDY field. */
Kojto 91:031413cf7a89 5720 #define TEMP_INTENCLR_DATARDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5721 #define TEMP_INTENCLR_DATARDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5722 #define TEMP_INTENCLR_DATARDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5723
Kojto 91:031413cf7a89 5724 /* Register: TEMP_POWER */
Kojto 91:031413cf7a89 5725 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 5726
Kojto 91:031413cf7a89 5727 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 5728 #define TEMP_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 5729 #define TEMP_POWER_POWER_Msk (0x1UL << TEMP_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 5730 #define TEMP_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 5731 #define TEMP_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 5732
Kojto 91:031413cf7a89 5733
Kojto 91:031413cf7a89 5734 /* Peripheral: TIMER */
Kojto 91:031413cf7a89 5735 /* Description: Timer 0. */
Kojto 91:031413cf7a89 5736
Kojto 91:031413cf7a89 5737 /* Register: TIMER_SHORTS */
Kojto 91:031413cf7a89 5738 /* Description: Shortcuts for Timer. */
Kojto 91:031413cf7a89 5739
Kojto 91:031413cf7a89 5740 /* Bit 11 : Shortcut between CC[3] event and the STOP task. */
Kojto 91:031413cf7a89 5741 #define TIMER_SHORTS_COMPARE3_STOP_Pos (11UL) /*!< Position of COMPARE3_STOP field. */
Kojto 91:031413cf7a89 5742 #define TIMER_SHORTS_COMPARE3_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE3_STOP_Pos) /*!< Bit mask of COMPARE3_STOP field. */
Kojto 91:031413cf7a89 5743 #define TIMER_SHORTS_COMPARE3_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5744 #define TIMER_SHORTS_COMPARE3_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5745
Kojto 91:031413cf7a89 5746 /* Bit 10 : Shortcut between CC[2] event and the STOP task. */
Kojto 91:031413cf7a89 5747 #define TIMER_SHORTS_COMPARE2_STOP_Pos (10UL) /*!< Position of COMPARE2_STOP field. */
Kojto 91:031413cf7a89 5748 #define TIMER_SHORTS_COMPARE2_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE2_STOP_Pos) /*!< Bit mask of COMPARE2_STOP field. */
Kojto 91:031413cf7a89 5749 #define TIMER_SHORTS_COMPARE2_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5750 #define TIMER_SHORTS_COMPARE2_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5751
Kojto 91:031413cf7a89 5752 /* Bit 9 : Shortcut between CC[1] event and the STOP task. */
Kojto 91:031413cf7a89 5753 #define TIMER_SHORTS_COMPARE1_STOP_Pos (9UL) /*!< Position of COMPARE1_STOP field. */
Kojto 91:031413cf7a89 5754 #define TIMER_SHORTS_COMPARE1_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE1_STOP_Pos) /*!< Bit mask of COMPARE1_STOP field. */
Kojto 91:031413cf7a89 5755 #define TIMER_SHORTS_COMPARE1_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5756 #define TIMER_SHORTS_COMPARE1_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5757
Kojto 91:031413cf7a89 5758 /* Bit 8 : Shortcut between CC[0] event and the STOP task. */
Kojto 91:031413cf7a89 5759 #define TIMER_SHORTS_COMPARE0_STOP_Pos (8UL) /*!< Position of COMPARE0_STOP field. */
Kojto 91:031413cf7a89 5760 #define TIMER_SHORTS_COMPARE0_STOP_Msk (0x1UL << TIMER_SHORTS_COMPARE0_STOP_Pos) /*!< Bit mask of COMPARE0_STOP field. */
Kojto 91:031413cf7a89 5761 #define TIMER_SHORTS_COMPARE0_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5762 #define TIMER_SHORTS_COMPARE0_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5763
Kojto 91:031413cf7a89 5764 /* Bit 3 : Shortcut between CC[3] event and the CLEAR task. */
Kojto 91:031413cf7a89 5765 #define TIMER_SHORTS_COMPARE3_CLEAR_Pos (3UL) /*!< Position of COMPARE3_CLEAR field. */
Kojto 91:031413cf7a89 5766 #define TIMER_SHORTS_COMPARE3_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE3_CLEAR_Pos) /*!< Bit mask of COMPARE3_CLEAR field. */
Kojto 91:031413cf7a89 5767 #define TIMER_SHORTS_COMPARE3_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5768 #define TIMER_SHORTS_COMPARE3_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5769
Kojto 91:031413cf7a89 5770 /* Bit 2 : Shortcut between CC[2] event and the CLEAR task. */
Kojto 91:031413cf7a89 5771 #define TIMER_SHORTS_COMPARE2_CLEAR_Pos (2UL) /*!< Position of COMPARE2_CLEAR field. */
Kojto 91:031413cf7a89 5772 #define TIMER_SHORTS_COMPARE2_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE2_CLEAR_Pos) /*!< Bit mask of COMPARE2_CLEAR field. */
Kojto 91:031413cf7a89 5773 #define TIMER_SHORTS_COMPARE2_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5774 #define TIMER_SHORTS_COMPARE2_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5775
Kojto 91:031413cf7a89 5776 /* Bit 1 : Shortcut between CC[1] event and the CLEAR task. */
Kojto 91:031413cf7a89 5777 #define TIMER_SHORTS_COMPARE1_CLEAR_Pos (1UL) /*!< Position of COMPARE1_CLEAR field. */
Kojto 91:031413cf7a89 5778 #define TIMER_SHORTS_COMPARE1_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE1_CLEAR_Pos) /*!< Bit mask of COMPARE1_CLEAR field. */
Kojto 91:031413cf7a89 5779 #define TIMER_SHORTS_COMPARE1_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5780 #define TIMER_SHORTS_COMPARE1_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5781
Kojto 91:031413cf7a89 5782 /* Bit 0 : Shortcut between CC[0] event and the CLEAR task. */
Kojto 91:031413cf7a89 5783 #define TIMER_SHORTS_COMPARE0_CLEAR_Pos (0UL) /*!< Position of COMPARE0_CLEAR field. */
Kojto 91:031413cf7a89 5784 #define TIMER_SHORTS_COMPARE0_CLEAR_Msk (0x1UL << TIMER_SHORTS_COMPARE0_CLEAR_Pos) /*!< Bit mask of COMPARE0_CLEAR field. */
Kojto 91:031413cf7a89 5785 #define TIMER_SHORTS_COMPARE0_CLEAR_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5786 #define TIMER_SHORTS_COMPARE0_CLEAR_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5787
Kojto 91:031413cf7a89 5788 /* Register: TIMER_INTENSET */
Kojto 91:031413cf7a89 5789 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 5790
Kojto 91:031413cf7a89 5791 /* Bit 19 : Enable interrupt on COMPARE[3] */
Kojto 91:031413cf7a89 5792 #define TIMER_INTENSET_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 91:031413cf7a89 5793 #define TIMER_INTENSET_COMPARE3_Msk (0x1UL << TIMER_INTENSET_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 91:031413cf7a89 5794 #define TIMER_INTENSET_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5795 #define TIMER_INTENSET_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5796 #define TIMER_INTENSET_COMPARE3_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5797
Kojto 91:031413cf7a89 5798 /* Bit 18 : Enable interrupt on COMPARE[2] */
Kojto 91:031413cf7a89 5799 #define TIMER_INTENSET_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 91:031413cf7a89 5800 #define TIMER_INTENSET_COMPARE2_Msk (0x1UL << TIMER_INTENSET_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 91:031413cf7a89 5801 #define TIMER_INTENSET_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5802 #define TIMER_INTENSET_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5803 #define TIMER_INTENSET_COMPARE2_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5804
Kojto 91:031413cf7a89 5805 /* Bit 17 : Enable interrupt on COMPARE[1] */
Kojto 91:031413cf7a89 5806 #define TIMER_INTENSET_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 91:031413cf7a89 5807 #define TIMER_INTENSET_COMPARE1_Msk (0x1UL << TIMER_INTENSET_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 91:031413cf7a89 5808 #define TIMER_INTENSET_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5809 #define TIMER_INTENSET_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5810 #define TIMER_INTENSET_COMPARE1_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5811
Kojto 91:031413cf7a89 5812 /* Bit 16 : Enable interrupt on COMPARE[0] */
Kojto 91:031413cf7a89 5813 #define TIMER_INTENSET_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 91:031413cf7a89 5814 #define TIMER_INTENSET_COMPARE0_Msk (0x1UL << TIMER_INTENSET_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 91:031413cf7a89 5815 #define TIMER_INTENSET_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5816 #define TIMER_INTENSET_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5817 #define TIMER_INTENSET_COMPARE0_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5818
Kojto 91:031413cf7a89 5819 /* Register: TIMER_INTENCLR */
Kojto 91:031413cf7a89 5820 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 5821
Kojto 91:031413cf7a89 5822 /* Bit 19 : Disable interrupt on COMPARE[3] */
Kojto 91:031413cf7a89 5823 #define TIMER_INTENCLR_COMPARE3_Pos (19UL) /*!< Position of COMPARE3 field. */
Kojto 91:031413cf7a89 5824 #define TIMER_INTENCLR_COMPARE3_Msk (0x1UL << TIMER_INTENCLR_COMPARE3_Pos) /*!< Bit mask of COMPARE3 field. */
Kojto 91:031413cf7a89 5825 #define TIMER_INTENCLR_COMPARE3_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5826 #define TIMER_INTENCLR_COMPARE3_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5827 #define TIMER_INTENCLR_COMPARE3_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5828
Kojto 91:031413cf7a89 5829 /* Bit 18 : Disable interrupt on COMPARE[2] */
Kojto 91:031413cf7a89 5830 #define TIMER_INTENCLR_COMPARE2_Pos (18UL) /*!< Position of COMPARE2 field. */
Kojto 91:031413cf7a89 5831 #define TIMER_INTENCLR_COMPARE2_Msk (0x1UL << TIMER_INTENCLR_COMPARE2_Pos) /*!< Bit mask of COMPARE2 field. */
Kojto 91:031413cf7a89 5832 #define TIMER_INTENCLR_COMPARE2_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5833 #define TIMER_INTENCLR_COMPARE2_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5834 #define TIMER_INTENCLR_COMPARE2_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5835
Kojto 91:031413cf7a89 5836 /* Bit 17 : Disable interrupt on COMPARE[1] */
Kojto 91:031413cf7a89 5837 #define TIMER_INTENCLR_COMPARE1_Pos (17UL) /*!< Position of COMPARE1 field. */
Kojto 91:031413cf7a89 5838 #define TIMER_INTENCLR_COMPARE1_Msk (0x1UL << TIMER_INTENCLR_COMPARE1_Pos) /*!< Bit mask of COMPARE1 field. */
Kojto 91:031413cf7a89 5839 #define TIMER_INTENCLR_COMPARE1_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5840 #define TIMER_INTENCLR_COMPARE1_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5841 #define TIMER_INTENCLR_COMPARE1_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5842
Kojto 91:031413cf7a89 5843 /* Bit 16 : Disable interrupt on COMPARE[0] */
Kojto 91:031413cf7a89 5844 #define TIMER_INTENCLR_COMPARE0_Pos (16UL) /*!< Position of COMPARE0 field. */
Kojto 91:031413cf7a89 5845 #define TIMER_INTENCLR_COMPARE0_Msk (0x1UL << TIMER_INTENCLR_COMPARE0_Pos) /*!< Bit mask of COMPARE0 field. */
Kojto 91:031413cf7a89 5846 #define TIMER_INTENCLR_COMPARE0_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5847 #define TIMER_INTENCLR_COMPARE0_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5848 #define TIMER_INTENCLR_COMPARE0_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5849
Kojto 91:031413cf7a89 5850 /* Register: TIMER_MODE */
Kojto 91:031413cf7a89 5851 /* Description: Timer Mode selection. */
Kojto 91:031413cf7a89 5852
Kojto 91:031413cf7a89 5853 /* Bit 0 : Select Normal or Counter mode. */
Kojto 91:031413cf7a89 5854 #define TIMER_MODE_MODE_Pos (0UL) /*!< Position of MODE field. */
Kojto 91:031413cf7a89 5855 #define TIMER_MODE_MODE_Msk (0x1UL << TIMER_MODE_MODE_Pos) /*!< Bit mask of MODE field. */
Kojto 91:031413cf7a89 5856 #define TIMER_MODE_MODE_Timer (0UL) /*!< Timer in Normal mode. */
Kojto 91:031413cf7a89 5857 #define TIMER_MODE_MODE_Counter (1UL) /*!< Timer in Counter mode. */
Kojto 91:031413cf7a89 5858
Kojto 91:031413cf7a89 5859 /* Register: TIMER_BITMODE */
Kojto 91:031413cf7a89 5860 /* Description: Sets timer behaviour. */
Kojto 91:031413cf7a89 5861
Kojto 91:031413cf7a89 5862 /* Bits 1..0 : Sets timer behaviour ro be like the implementation of a timer with width as indicated. */
Kojto 91:031413cf7a89 5863 #define TIMER_BITMODE_BITMODE_Pos (0UL) /*!< Position of BITMODE field. */
Kojto 91:031413cf7a89 5864 #define TIMER_BITMODE_BITMODE_Msk (0x3UL << TIMER_BITMODE_BITMODE_Pos) /*!< Bit mask of BITMODE field. */
Kojto 91:031413cf7a89 5865 #define TIMER_BITMODE_BITMODE_16Bit (0x00UL) /*!< 16-bit timer behaviour. */
Kojto 91:031413cf7a89 5866 #define TIMER_BITMODE_BITMODE_08Bit (0x01UL) /*!< 8-bit timer behaviour. */
Kojto 91:031413cf7a89 5867 #define TIMER_BITMODE_BITMODE_24Bit (0x02UL) /*!< 24-bit timer behaviour. */
Kojto 91:031413cf7a89 5868 #define TIMER_BITMODE_BITMODE_32Bit (0x03UL) /*!< 32-bit timer behaviour. */
Kojto 91:031413cf7a89 5869
Kojto 91:031413cf7a89 5870 /* Register: TIMER_PRESCALER */
Kojto 91:031413cf7a89 5871 /* Description: 4-bit prescaler to source clock frequency (max value 9). Source clock frequency is divided by 2^SCALE. */
Kojto 91:031413cf7a89 5872
Kojto 91:031413cf7a89 5873 /* Bits 3..0 : Timer PRESCALER value. Max value is 9. */
Kojto 91:031413cf7a89 5874 #define TIMER_PRESCALER_PRESCALER_Pos (0UL) /*!< Position of PRESCALER field. */
Kojto 91:031413cf7a89 5875 #define TIMER_PRESCALER_PRESCALER_Msk (0xFUL << TIMER_PRESCALER_PRESCALER_Pos) /*!< Bit mask of PRESCALER field. */
Kojto 91:031413cf7a89 5876
Kojto 91:031413cf7a89 5877 /* Register: TIMER_POWER */
Kojto 91:031413cf7a89 5878 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 5879
Kojto 91:031413cf7a89 5880 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 5881 #define TIMER_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 5882 #define TIMER_POWER_POWER_Msk (0x1UL << TIMER_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 5883 #define TIMER_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 5884 #define TIMER_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 5885
Kojto 91:031413cf7a89 5886
Kojto 91:031413cf7a89 5887 /* Peripheral: TWI */
Kojto 91:031413cf7a89 5888 /* Description: Two-wire interface master 0. */
Kojto 91:031413cf7a89 5889
Kojto 91:031413cf7a89 5890 /* Register: TWI_SHORTS */
Kojto 91:031413cf7a89 5891 /* Description: Shortcuts for TWI. */
Kojto 91:031413cf7a89 5892
Kojto 91:031413cf7a89 5893 /* Bit 1 : Shortcut between BB event and the STOP task. */
Kojto 91:031413cf7a89 5894 #define TWI_SHORTS_BB_STOP_Pos (1UL) /*!< Position of BB_STOP field. */
Kojto 91:031413cf7a89 5895 #define TWI_SHORTS_BB_STOP_Msk (0x1UL << TWI_SHORTS_BB_STOP_Pos) /*!< Bit mask of BB_STOP field. */
Kojto 91:031413cf7a89 5896 #define TWI_SHORTS_BB_STOP_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5897 #define TWI_SHORTS_BB_STOP_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5898
Kojto 91:031413cf7a89 5899 /* Bit 0 : Shortcut between BB event and the SUSPEND task. */
Kojto 91:031413cf7a89 5900 #define TWI_SHORTS_BB_SUSPEND_Pos (0UL) /*!< Position of BB_SUSPEND field. */
Kojto 91:031413cf7a89 5901 #define TWI_SHORTS_BB_SUSPEND_Msk (0x1UL << TWI_SHORTS_BB_SUSPEND_Pos) /*!< Bit mask of BB_SUSPEND field. */
Kojto 91:031413cf7a89 5902 #define TWI_SHORTS_BB_SUSPEND_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 5903 #define TWI_SHORTS_BB_SUSPEND_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 5904
Kojto 91:031413cf7a89 5905 /* Register: TWI_INTENSET */
Kojto 91:031413cf7a89 5906 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 5907
Kojto 91:031413cf7a89 5908 /* Bit 14 : Enable interrupt on BB event. */
Kojto 91:031413cf7a89 5909 #define TWI_INTENSET_BB_Pos (14UL) /*!< Position of BB field. */
Kojto 91:031413cf7a89 5910 #define TWI_INTENSET_BB_Msk (0x1UL << TWI_INTENSET_BB_Pos) /*!< Bit mask of BB field. */
Kojto 91:031413cf7a89 5911 #define TWI_INTENSET_BB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5912 #define TWI_INTENSET_BB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5913 #define TWI_INTENSET_BB_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5914
Kojto 91:031413cf7a89 5915 /* Bit 9 : Enable interrupt on ERROR event. */
Kojto 91:031413cf7a89 5916 #define TWI_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Kojto 91:031413cf7a89 5917 #define TWI_INTENSET_ERROR_Msk (0x1UL << TWI_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 91:031413cf7a89 5918 #define TWI_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5919 #define TWI_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5920 #define TWI_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5921
Kojto 91:031413cf7a89 5922 /* Bit 7 : Enable interrupt on TXDSENT event. */
Kojto 91:031413cf7a89 5923 #define TWI_INTENSET_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
Kojto 91:031413cf7a89 5924 #define TWI_INTENSET_TXDSENT_Msk (0x1UL << TWI_INTENSET_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
Kojto 91:031413cf7a89 5925 #define TWI_INTENSET_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5926 #define TWI_INTENSET_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5927 #define TWI_INTENSET_TXDSENT_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5928
Kojto 91:031413cf7a89 5929 /* Bit 2 : Enable interrupt on READY event. */
Kojto 91:031413cf7a89 5930 #define TWI_INTENSET_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
Kojto 91:031413cf7a89 5931 #define TWI_INTENSET_RXDREADY_Msk (0x1UL << TWI_INTENSET_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
Kojto 91:031413cf7a89 5932 #define TWI_INTENSET_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5933 #define TWI_INTENSET_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5934 #define TWI_INTENSET_RXDREADY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5935
Kojto 91:031413cf7a89 5936 /* Bit 1 : Enable interrupt on STOPPED event. */
Kojto 91:031413cf7a89 5937 #define TWI_INTENSET_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Kojto 91:031413cf7a89 5938 #define TWI_INTENSET_STOPPED_Msk (0x1UL << TWI_INTENSET_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Kojto 91:031413cf7a89 5939 #define TWI_INTENSET_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5940 #define TWI_INTENSET_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5941 #define TWI_INTENSET_STOPPED_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 5942
Kojto 91:031413cf7a89 5943 /* Register: TWI_INTENCLR */
Kojto 91:031413cf7a89 5944 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 5945
Kojto 91:031413cf7a89 5946 /* Bit 14 : Disable interrupt on BB event. */
Kojto 91:031413cf7a89 5947 #define TWI_INTENCLR_BB_Pos (14UL) /*!< Position of BB field. */
Kojto 91:031413cf7a89 5948 #define TWI_INTENCLR_BB_Msk (0x1UL << TWI_INTENCLR_BB_Pos) /*!< Bit mask of BB field. */
Kojto 91:031413cf7a89 5949 #define TWI_INTENCLR_BB_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5950 #define TWI_INTENCLR_BB_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5951 #define TWI_INTENCLR_BB_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5952
Kojto 91:031413cf7a89 5953 /* Bit 9 : Disable interrupt on ERROR event. */
Kojto 91:031413cf7a89 5954 #define TWI_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Kojto 91:031413cf7a89 5955 #define TWI_INTENCLR_ERROR_Msk (0x1UL << TWI_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 91:031413cf7a89 5956 #define TWI_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5957 #define TWI_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5958 #define TWI_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5959
Kojto 91:031413cf7a89 5960 /* Bit 7 : Disable interrupt on TXDSENT event. */
Kojto 91:031413cf7a89 5961 #define TWI_INTENCLR_TXDSENT_Pos (7UL) /*!< Position of TXDSENT field. */
Kojto 91:031413cf7a89 5962 #define TWI_INTENCLR_TXDSENT_Msk (0x1UL << TWI_INTENCLR_TXDSENT_Pos) /*!< Bit mask of TXDSENT field. */
Kojto 91:031413cf7a89 5963 #define TWI_INTENCLR_TXDSENT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5964 #define TWI_INTENCLR_TXDSENT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5965 #define TWI_INTENCLR_TXDSENT_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5966
Kojto 91:031413cf7a89 5967 /* Bit 2 : Disable interrupt on RXDREADY event. */
Kojto 91:031413cf7a89 5968 #define TWI_INTENCLR_RXDREADY_Pos (2UL) /*!< Position of RXDREADY field. */
Kojto 91:031413cf7a89 5969 #define TWI_INTENCLR_RXDREADY_Msk (0x1UL << TWI_INTENCLR_RXDREADY_Pos) /*!< Bit mask of RXDREADY field. */
Kojto 91:031413cf7a89 5970 #define TWI_INTENCLR_RXDREADY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5971 #define TWI_INTENCLR_RXDREADY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5972 #define TWI_INTENCLR_RXDREADY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5973
Kojto 91:031413cf7a89 5974 /* Bit 1 : Disable interrupt on STOPPED event. */
Kojto 91:031413cf7a89 5975 #define TWI_INTENCLR_STOPPED_Pos (1UL) /*!< Position of STOPPED field. */
Kojto 91:031413cf7a89 5976 #define TWI_INTENCLR_STOPPED_Msk (0x1UL << TWI_INTENCLR_STOPPED_Pos) /*!< Bit mask of STOPPED field. */
Kojto 91:031413cf7a89 5977 #define TWI_INTENCLR_STOPPED_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 5978 #define TWI_INTENCLR_STOPPED_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 5979 #define TWI_INTENCLR_STOPPED_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 5980
Kojto 91:031413cf7a89 5981 /* Register: TWI_ERRORSRC */
Kojto 91:031413cf7a89 5982 /* Description: Two-wire error source. Write error field to 1 to clear error. */
Kojto 91:031413cf7a89 5983
Kojto 91:031413cf7a89 5984 /* Bit 2 : NACK received after sending a data byte. */
Kojto 91:031413cf7a89 5985 #define TWI_ERRORSRC_DNACK_Pos (2UL) /*!< Position of DNACK field. */
Kojto 91:031413cf7a89 5986 #define TWI_ERRORSRC_DNACK_Msk (0x1UL << TWI_ERRORSRC_DNACK_Pos) /*!< Bit mask of DNACK field. */
Kojto 91:031413cf7a89 5987 #define TWI_ERRORSRC_DNACK_NotPresent (0UL) /*!< Error not present. */
Kojto 91:031413cf7a89 5988 #define TWI_ERRORSRC_DNACK_Present (1UL) /*!< Error present. */
Kojto 91:031413cf7a89 5989 #define TWI_ERRORSRC_DNACK_Clear (1UL) /*!< Clear error on write. */
Kojto 91:031413cf7a89 5990
Kojto 91:031413cf7a89 5991 /* Bit 1 : NACK received after sending the address. */
Kojto 91:031413cf7a89 5992 #define TWI_ERRORSRC_ANACK_Pos (1UL) /*!< Position of ANACK field. */
Kojto 91:031413cf7a89 5993 #define TWI_ERRORSRC_ANACK_Msk (0x1UL << TWI_ERRORSRC_ANACK_Pos) /*!< Bit mask of ANACK field. */
Kojto 91:031413cf7a89 5994 #define TWI_ERRORSRC_ANACK_NotPresent (0UL) /*!< Error not present. */
Kojto 91:031413cf7a89 5995 #define TWI_ERRORSRC_ANACK_Present (1UL) /*!< Error present. */
Kojto 91:031413cf7a89 5996 #define TWI_ERRORSRC_ANACK_Clear (1UL) /*!< Clear error on write. */
Kojto 91:031413cf7a89 5997
Kojto 91:031413cf7a89 5998 /* Register: TWI_ENABLE */
Kojto 91:031413cf7a89 5999 /* Description: Enable two-wire master. */
Kojto 91:031413cf7a89 6000
Kojto 91:031413cf7a89 6001 /* Bits 2..0 : Enable or disable W2M */
Kojto 91:031413cf7a89 6002 #define TWI_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 6003 #define TWI_ENABLE_ENABLE_Msk (0x7UL << TWI_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 6004 #define TWI_ENABLE_ENABLE_Disabled (0x00UL) /*!< Disabled. */
Kojto 91:031413cf7a89 6005 #define TWI_ENABLE_ENABLE_Enabled (0x05UL) /*!< Enabled. */
Kojto 91:031413cf7a89 6006
Kojto 91:031413cf7a89 6007 /* Register: TWI_RXD */
Kojto 91:031413cf7a89 6008 /* Description: RX data register. */
Kojto 91:031413cf7a89 6009
Kojto 91:031413cf7a89 6010 /* Bits 7..0 : RX data from last transfer. */
Kojto 91:031413cf7a89 6011 #define TWI_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
Kojto 91:031413cf7a89 6012 #define TWI_RXD_RXD_Msk (0xFFUL << TWI_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
Kojto 91:031413cf7a89 6013
Kojto 91:031413cf7a89 6014 /* Register: TWI_TXD */
Kojto 91:031413cf7a89 6015 /* Description: TX data register. */
Kojto 91:031413cf7a89 6016
Kojto 91:031413cf7a89 6017 /* Bits 7..0 : TX data for next transfer. */
Kojto 91:031413cf7a89 6018 #define TWI_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
Kojto 91:031413cf7a89 6019 #define TWI_TXD_TXD_Msk (0xFFUL << TWI_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
Kojto 91:031413cf7a89 6020
Kojto 91:031413cf7a89 6021 /* Register: TWI_FREQUENCY */
Kojto 91:031413cf7a89 6022 /* Description: Two-wire frequency. */
Kojto 91:031413cf7a89 6023
Kojto 91:031413cf7a89 6024 /* Bits 31..0 : Two-wire master clock frequency. */
Kojto 91:031413cf7a89 6025 #define TWI_FREQUENCY_FREQUENCY_Pos (0UL) /*!< Position of FREQUENCY field. */
Kojto 91:031413cf7a89 6026 #define TWI_FREQUENCY_FREQUENCY_Msk (0xFFFFFFFFUL << TWI_FREQUENCY_FREQUENCY_Pos) /*!< Bit mask of FREQUENCY field. */
Kojto 91:031413cf7a89 6027 #define TWI_FREQUENCY_FREQUENCY_K100 (0x01980000UL) /*!< 100 kbps. */
Kojto 91:031413cf7a89 6028 #define TWI_FREQUENCY_FREQUENCY_K250 (0x04000000UL) /*!< 250 kbps. */
Kojto 91:031413cf7a89 6029 #define TWI_FREQUENCY_FREQUENCY_K400 (0x06680000UL) /*!< 400 kbps. */
Kojto 91:031413cf7a89 6030
Kojto 91:031413cf7a89 6031 /* Register: TWI_ADDRESS */
Kojto 91:031413cf7a89 6032 /* Description: Address used in the two-wire transfer. */
Kojto 91:031413cf7a89 6033
Kojto 91:031413cf7a89 6034 /* Bits 6..0 : Two-wire address. */
Kojto 91:031413cf7a89 6035 #define TWI_ADDRESS_ADDRESS_Pos (0UL) /*!< Position of ADDRESS field. */
Kojto 91:031413cf7a89 6036 #define TWI_ADDRESS_ADDRESS_Msk (0x7FUL << TWI_ADDRESS_ADDRESS_Pos) /*!< Bit mask of ADDRESS field. */
Kojto 91:031413cf7a89 6037
Kojto 91:031413cf7a89 6038 /* Register: TWI_POWER */
Kojto 91:031413cf7a89 6039 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 6040
Kojto 91:031413cf7a89 6041 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 6042 #define TWI_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 6043 #define TWI_POWER_POWER_Msk (0x1UL << TWI_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 6044 #define TWI_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 6045 #define TWI_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 6046
Kojto 91:031413cf7a89 6047
Kojto 91:031413cf7a89 6048 /* Peripheral: UART */
Kojto 91:031413cf7a89 6049 /* Description: Universal Asynchronous Receiver/Transmitter. */
Kojto 91:031413cf7a89 6050
Kojto 91:031413cf7a89 6051 /* Register: UART_SHORTS */
Kojto 91:031413cf7a89 6052 /* Description: Shortcuts for TWI. */
Kojto 91:031413cf7a89 6053
Kojto 91:031413cf7a89 6054 /* Bit 4 : Shortcut between NCTS event and the STOPRX task. */
Kojto 91:031413cf7a89 6055 #define UART_SHORTS_NCTS_STOPRX_Pos (4UL) /*!< Position of NCTS_STOPRX field. */
Kojto 91:031413cf7a89 6056 #define UART_SHORTS_NCTS_STOPRX_Msk (0x1UL << UART_SHORTS_NCTS_STOPRX_Pos) /*!< Bit mask of NCTS_STOPRX field. */
Kojto 91:031413cf7a89 6057 #define UART_SHORTS_NCTS_STOPRX_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 6058 #define UART_SHORTS_NCTS_STOPRX_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 6059
Kojto 91:031413cf7a89 6060 /* Bit 3 : Shortcut between CTS event and the STARTRX task. */
Kojto 91:031413cf7a89 6061 #define UART_SHORTS_CTS_STARTRX_Pos (3UL) /*!< Position of CTS_STARTRX field. */
Kojto 91:031413cf7a89 6062 #define UART_SHORTS_CTS_STARTRX_Msk (0x1UL << UART_SHORTS_CTS_STARTRX_Pos) /*!< Bit mask of CTS_STARTRX field. */
Kojto 91:031413cf7a89 6063 #define UART_SHORTS_CTS_STARTRX_Disabled (0UL) /*!< Shortcut disabled. */
Kojto 91:031413cf7a89 6064 #define UART_SHORTS_CTS_STARTRX_Enabled (1UL) /*!< Shortcut enabled. */
Kojto 91:031413cf7a89 6065
Kojto 91:031413cf7a89 6066 /* Register: UART_INTENSET */
Kojto 91:031413cf7a89 6067 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 6068
Kojto 91:031413cf7a89 6069 /* Bit 17 : Enable interrupt on RXTO event. */
Kojto 91:031413cf7a89 6070 #define UART_INTENSET_RXTO_Pos (17UL) /*!< Position of RXTO field. */
Kojto 91:031413cf7a89 6071 #define UART_INTENSET_RXTO_Msk (0x1UL << UART_INTENSET_RXTO_Pos) /*!< Bit mask of RXTO field. */
Kojto 91:031413cf7a89 6072 #define UART_INTENSET_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6073 #define UART_INTENSET_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6074 #define UART_INTENSET_RXTO_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 6075
Kojto 91:031413cf7a89 6076 /* Bit 9 : Enable interrupt on ERROR event. */
Kojto 91:031413cf7a89 6077 #define UART_INTENSET_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Kojto 91:031413cf7a89 6078 #define UART_INTENSET_ERROR_Msk (0x1UL << UART_INTENSET_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 91:031413cf7a89 6079 #define UART_INTENSET_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6080 #define UART_INTENSET_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6081 #define UART_INTENSET_ERROR_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 6082
Kojto 91:031413cf7a89 6083 /* Bit 7 : Enable interrupt on TXRDY event. */
Kojto 91:031413cf7a89 6084 #define UART_INTENSET_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
Kojto 91:031413cf7a89 6085 #define UART_INTENSET_TXDRDY_Msk (0x1UL << UART_INTENSET_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
Kojto 91:031413cf7a89 6086 #define UART_INTENSET_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6087 #define UART_INTENSET_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6088 #define UART_INTENSET_TXDRDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 6089
Kojto 91:031413cf7a89 6090 /* Bit 2 : Enable interrupt on RXRDY event. */
Kojto 91:031413cf7a89 6091 #define UART_INTENSET_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
Kojto 91:031413cf7a89 6092 #define UART_INTENSET_RXDRDY_Msk (0x1UL << UART_INTENSET_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
Kojto 91:031413cf7a89 6093 #define UART_INTENSET_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6094 #define UART_INTENSET_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6095 #define UART_INTENSET_RXDRDY_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 6096
Kojto 91:031413cf7a89 6097 /* Bit 1 : Enable interrupt on NCTS event. */
Kojto 91:031413cf7a89 6098 #define UART_INTENSET_NCTS_Pos (1UL) /*!< Position of NCTS field. */
Kojto 91:031413cf7a89 6099 #define UART_INTENSET_NCTS_Msk (0x1UL << UART_INTENSET_NCTS_Pos) /*!< Bit mask of NCTS field. */
Kojto 91:031413cf7a89 6100 #define UART_INTENSET_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6101 #define UART_INTENSET_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6102 #define UART_INTENSET_NCTS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 6103
Kojto 91:031413cf7a89 6104 /* Bit 0 : Enable interrupt on CTS event. */
Kojto 91:031413cf7a89 6105 #define UART_INTENSET_CTS_Pos (0UL) /*!< Position of CTS field. */
Kojto 91:031413cf7a89 6106 #define UART_INTENSET_CTS_Msk (0x1UL << UART_INTENSET_CTS_Pos) /*!< Bit mask of CTS field. */
Kojto 91:031413cf7a89 6107 #define UART_INTENSET_CTS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6108 #define UART_INTENSET_CTS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6109 #define UART_INTENSET_CTS_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 6110
Kojto 91:031413cf7a89 6111 /* Register: UART_INTENCLR */
Kojto 91:031413cf7a89 6112 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 6113
Kojto 91:031413cf7a89 6114 /* Bit 17 : Disable interrupt on RXTO event. */
Kojto 91:031413cf7a89 6115 #define UART_INTENCLR_RXTO_Pos (17UL) /*!< Position of RXTO field. */
Kojto 91:031413cf7a89 6116 #define UART_INTENCLR_RXTO_Msk (0x1UL << UART_INTENCLR_RXTO_Pos) /*!< Bit mask of RXTO field. */
Kojto 91:031413cf7a89 6117 #define UART_INTENCLR_RXTO_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6118 #define UART_INTENCLR_RXTO_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6119 #define UART_INTENCLR_RXTO_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 6120
Kojto 91:031413cf7a89 6121 /* Bit 9 : Disable interrupt on ERROR event. */
Kojto 91:031413cf7a89 6122 #define UART_INTENCLR_ERROR_Pos (9UL) /*!< Position of ERROR field. */
Kojto 91:031413cf7a89 6123 #define UART_INTENCLR_ERROR_Msk (0x1UL << UART_INTENCLR_ERROR_Pos) /*!< Bit mask of ERROR field. */
Kojto 91:031413cf7a89 6124 #define UART_INTENCLR_ERROR_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6125 #define UART_INTENCLR_ERROR_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6126 #define UART_INTENCLR_ERROR_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 6127
Kojto 91:031413cf7a89 6128 /* Bit 7 : Disable interrupt on TXRDY event. */
Kojto 91:031413cf7a89 6129 #define UART_INTENCLR_TXDRDY_Pos (7UL) /*!< Position of TXDRDY field. */
Kojto 91:031413cf7a89 6130 #define UART_INTENCLR_TXDRDY_Msk (0x1UL << UART_INTENCLR_TXDRDY_Pos) /*!< Bit mask of TXDRDY field. */
Kojto 91:031413cf7a89 6131 #define UART_INTENCLR_TXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6132 #define UART_INTENCLR_TXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6133 #define UART_INTENCLR_TXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 6134
Kojto 91:031413cf7a89 6135 /* Bit 2 : Disable interrupt on RXRDY event. */
Kojto 91:031413cf7a89 6136 #define UART_INTENCLR_RXDRDY_Pos (2UL) /*!< Position of RXDRDY field. */
Kojto 91:031413cf7a89 6137 #define UART_INTENCLR_RXDRDY_Msk (0x1UL << UART_INTENCLR_RXDRDY_Pos) /*!< Bit mask of RXDRDY field. */
Kojto 91:031413cf7a89 6138 #define UART_INTENCLR_RXDRDY_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6139 #define UART_INTENCLR_RXDRDY_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6140 #define UART_INTENCLR_RXDRDY_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 6141
Kojto 91:031413cf7a89 6142 /* Bit 1 : Disable interrupt on NCTS event. */
Kojto 91:031413cf7a89 6143 #define UART_INTENCLR_NCTS_Pos (1UL) /*!< Position of NCTS field. */
Kojto 91:031413cf7a89 6144 #define UART_INTENCLR_NCTS_Msk (0x1UL << UART_INTENCLR_NCTS_Pos) /*!< Bit mask of NCTS field. */
Kojto 91:031413cf7a89 6145 #define UART_INTENCLR_NCTS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6146 #define UART_INTENCLR_NCTS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6147 #define UART_INTENCLR_NCTS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 6148
Kojto 91:031413cf7a89 6149 /* Bit 0 : Disable interrupt on CTS event. */
Kojto 91:031413cf7a89 6150 #define UART_INTENCLR_CTS_Pos (0UL) /*!< Position of CTS field. */
Kojto 91:031413cf7a89 6151 #define UART_INTENCLR_CTS_Msk (0x1UL << UART_INTENCLR_CTS_Pos) /*!< Bit mask of CTS field. */
Kojto 91:031413cf7a89 6152 #define UART_INTENCLR_CTS_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6153 #define UART_INTENCLR_CTS_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6154 #define UART_INTENCLR_CTS_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 6155
Kojto 91:031413cf7a89 6156 /* Register: UART_ERRORSRC */
Kojto 91:031413cf7a89 6157 /* Description: Error source. Write error field to 1 to clear error. */
Kojto 91:031413cf7a89 6158
Kojto 91:031413cf7a89 6159 /* Bit 3 : The serial data input is '0' for longer than the length of a data frame. */
Kojto 91:031413cf7a89 6160 #define UART_ERRORSRC_BREAK_Pos (3UL) /*!< Position of BREAK field. */
Kojto 91:031413cf7a89 6161 #define UART_ERRORSRC_BREAK_Msk (0x1UL << UART_ERRORSRC_BREAK_Pos) /*!< Bit mask of BREAK field. */
Kojto 91:031413cf7a89 6162 #define UART_ERRORSRC_BREAK_NotPresent (0UL) /*!< Error not present. */
Kojto 91:031413cf7a89 6163 #define UART_ERRORSRC_BREAK_Present (1UL) /*!< Error present. */
Kojto 91:031413cf7a89 6164 #define UART_ERRORSRC_BREAK_Clear (1UL) /*!< Clear error on write. */
Kojto 91:031413cf7a89 6165
Kojto 91:031413cf7a89 6166 /* Bit 2 : A valid stop bit is not detected on the serial data input after all bits in a character have been received. */
Kojto 91:031413cf7a89 6167 #define UART_ERRORSRC_FRAMING_Pos (2UL) /*!< Position of FRAMING field. */
Kojto 91:031413cf7a89 6168 #define UART_ERRORSRC_FRAMING_Msk (0x1UL << UART_ERRORSRC_FRAMING_Pos) /*!< Bit mask of FRAMING field. */
Kojto 91:031413cf7a89 6169 #define UART_ERRORSRC_FRAMING_NotPresent (0UL) /*!< Error not present. */
Kojto 91:031413cf7a89 6170 #define UART_ERRORSRC_FRAMING_Present (1UL) /*!< Error present. */
Kojto 91:031413cf7a89 6171 #define UART_ERRORSRC_FRAMING_Clear (1UL) /*!< Clear error on write. */
Kojto 91:031413cf7a89 6172
Kojto 91:031413cf7a89 6173 /* Bit 1 : A character with bad parity is received. Only checked if HW parity control is enabled. */
Kojto 91:031413cf7a89 6174 #define UART_ERRORSRC_PARITY_Pos (1UL) /*!< Position of PARITY field. */
Kojto 91:031413cf7a89 6175 #define UART_ERRORSRC_PARITY_Msk (0x1UL << UART_ERRORSRC_PARITY_Pos) /*!< Bit mask of PARITY field. */
Kojto 91:031413cf7a89 6176 #define UART_ERRORSRC_PARITY_NotPresent (0UL) /*!< Error not present. */
Kojto 91:031413cf7a89 6177 #define UART_ERRORSRC_PARITY_Present (1UL) /*!< Error present. */
Kojto 91:031413cf7a89 6178 #define UART_ERRORSRC_PARITY_Clear (1UL) /*!< Clear error on write. */
Kojto 91:031413cf7a89 6179
Kojto 91:031413cf7a89 6180 /* Bit 0 : A start bit is received while the previous data still lies in RXD. (Data loss). */
Kojto 91:031413cf7a89 6181 #define UART_ERRORSRC_OVERRUN_Pos (0UL) /*!< Position of OVERRUN field. */
Kojto 91:031413cf7a89 6182 #define UART_ERRORSRC_OVERRUN_Msk (0x1UL << UART_ERRORSRC_OVERRUN_Pos) /*!< Bit mask of OVERRUN field. */
Kojto 91:031413cf7a89 6183 #define UART_ERRORSRC_OVERRUN_NotPresent (0UL) /*!< Error not present. */
Kojto 91:031413cf7a89 6184 #define UART_ERRORSRC_OVERRUN_Present (1UL) /*!< Error present. */
Kojto 91:031413cf7a89 6185 #define UART_ERRORSRC_OVERRUN_Clear (1UL) /*!< Clear error on write. */
Kojto 91:031413cf7a89 6186
Kojto 91:031413cf7a89 6187 /* Register: UART_ENABLE */
Kojto 91:031413cf7a89 6188 /* Description: Enable UART and acquire IOs. */
Kojto 91:031413cf7a89 6189
Kojto 91:031413cf7a89 6190 /* Bits 2..0 : Enable or disable UART and acquire IOs. */
Kojto 91:031413cf7a89 6191 #define UART_ENABLE_ENABLE_Pos (0UL) /*!< Position of ENABLE field. */
Kojto 91:031413cf7a89 6192 #define UART_ENABLE_ENABLE_Msk (0x7UL << UART_ENABLE_ENABLE_Pos) /*!< Bit mask of ENABLE field. */
Kojto 91:031413cf7a89 6193 #define UART_ENABLE_ENABLE_Disabled (0x00UL) /*!< UART disabled. */
Kojto 91:031413cf7a89 6194 #define UART_ENABLE_ENABLE_Enabled (0x04UL) /*!< UART enabled. */
Kojto 91:031413cf7a89 6195
Kojto 91:031413cf7a89 6196 /* Register: UART_RXD */
Kojto 91:031413cf7a89 6197 /* Description: RXD register. On read action the buffer pointer is displaced. Once read the character is consummed. If read when no character available, the UART will stop working. */
Kojto 91:031413cf7a89 6198
Kojto 91:031413cf7a89 6199 /* Bits 7..0 : RX data from previous transfer. Double buffered. */
Kojto 91:031413cf7a89 6200 #define UART_RXD_RXD_Pos (0UL) /*!< Position of RXD field. */
Kojto 91:031413cf7a89 6201 #define UART_RXD_RXD_Msk (0xFFUL << UART_RXD_RXD_Pos) /*!< Bit mask of RXD field. */
Kojto 91:031413cf7a89 6202
Kojto 91:031413cf7a89 6203 /* Register: UART_TXD */
Kojto 91:031413cf7a89 6204 /* Description: TXD register. */
Kojto 91:031413cf7a89 6205
Kojto 91:031413cf7a89 6206 /* Bits 7..0 : TX data for transfer. */
Kojto 91:031413cf7a89 6207 #define UART_TXD_TXD_Pos (0UL) /*!< Position of TXD field. */
Kojto 91:031413cf7a89 6208 #define UART_TXD_TXD_Msk (0xFFUL << UART_TXD_TXD_Pos) /*!< Bit mask of TXD field. */
Kojto 91:031413cf7a89 6209
Kojto 91:031413cf7a89 6210 /* Register: UART_BAUDRATE */
Kojto 91:031413cf7a89 6211 /* Description: UART Baudrate. */
Kojto 91:031413cf7a89 6212
Kojto 91:031413cf7a89 6213 /* Bits 31..0 : UART baudrate. */
Kojto 91:031413cf7a89 6214 #define UART_BAUDRATE_BAUDRATE_Pos (0UL) /*!< Position of BAUDRATE field. */
Kojto 91:031413cf7a89 6215 #define UART_BAUDRATE_BAUDRATE_Msk (0xFFFFFFFFUL << UART_BAUDRATE_BAUDRATE_Pos) /*!< Bit mask of BAUDRATE field. */
Kojto 91:031413cf7a89 6216 #define UART_BAUDRATE_BAUDRATE_Baud1200 (0x0004F000UL) /*!< 1200 baud. */
Kojto 91:031413cf7a89 6217 #define UART_BAUDRATE_BAUDRATE_Baud2400 (0x0009D000UL) /*!< 2400 baud. */
Kojto 91:031413cf7a89 6218 #define UART_BAUDRATE_BAUDRATE_Baud4800 (0x0013B000UL) /*!< 4800 baud. */
Kojto 91:031413cf7a89 6219 #define UART_BAUDRATE_BAUDRATE_Baud9600 (0x00275000UL) /*!< 9600 baud. */
Kojto 91:031413cf7a89 6220 #define UART_BAUDRATE_BAUDRATE_Baud14400 (0x003B0000UL) /*!< 14400 baud. */
Kojto 91:031413cf7a89 6221 #define UART_BAUDRATE_BAUDRATE_Baud19200 (0x004EA000UL) /*!< 19200 baud. */
Kojto 91:031413cf7a89 6222 #define UART_BAUDRATE_BAUDRATE_Baud28800 (0x0075F000UL) /*!< 28800 baud. */
Kojto 91:031413cf7a89 6223 #define UART_BAUDRATE_BAUDRATE_Baud38400 (0x009D5000UL) /*!< 38400 baud. */
Kojto 91:031413cf7a89 6224 #define UART_BAUDRATE_BAUDRATE_Baud57600 (0x00EBF000UL) /*!< 57600 baud. */
Kojto 91:031413cf7a89 6225 #define UART_BAUDRATE_BAUDRATE_Baud76800 (0x013A9000UL) /*!< 76800 baud. */
Kojto 91:031413cf7a89 6226 #define UART_BAUDRATE_BAUDRATE_Baud115200 (0x01D7E000UL) /*!< 115200 baud. */
Kojto 91:031413cf7a89 6227 #define UART_BAUDRATE_BAUDRATE_Baud230400 (0x03AFB000UL) /*!< 230400 baud. */
Kojto 91:031413cf7a89 6228 #define UART_BAUDRATE_BAUDRATE_Baud250000 (0x04000000UL) /*!< 250000 baud. */
Kojto 91:031413cf7a89 6229 #define UART_BAUDRATE_BAUDRATE_Baud460800 (0x075F7000UL) /*!< 460800 baud. */
Kojto 91:031413cf7a89 6230 #define UART_BAUDRATE_BAUDRATE_Baud921600 (0x0EBEDFA4UL) /*!< 921600 baud. */
Kojto 91:031413cf7a89 6231 #define UART_BAUDRATE_BAUDRATE_Baud1M (0x10000000UL) /*!< 1M baud. */
Kojto 91:031413cf7a89 6232
Kojto 91:031413cf7a89 6233 /* Register: UART_CONFIG */
Kojto 91:031413cf7a89 6234 /* Description: Configuration of parity and hardware flow control register. */
Kojto 91:031413cf7a89 6235
Kojto 91:031413cf7a89 6236 /* Bits 3..1 : Include parity bit. */
Kojto 91:031413cf7a89 6237 #define UART_CONFIG_PARITY_Pos (1UL) /*!< Position of PARITY field. */
Kojto 91:031413cf7a89 6238 #define UART_CONFIG_PARITY_Msk (0x7UL << UART_CONFIG_PARITY_Pos) /*!< Bit mask of PARITY field. */
Kojto 91:031413cf7a89 6239 #define UART_CONFIG_PARITY_Excluded (0UL) /*!< Parity bit excluded. */
Kojto 91:031413cf7a89 6240 #define UART_CONFIG_PARITY_Included (7UL) /*!< Parity bit included. */
Kojto 91:031413cf7a89 6241
Kojto 91:031413cf7a89 6242 /* Bit 0 : Hardware flow control. */
Kojto 91:031413cf7a89 6243 #define UART_CONFIG_HWFC_Pos (0UL) /*!< Position of HWFC field. */
Kojto 91:031413cf7a89 6244 #define UART_CONFIG_HWFC_Msk (0x1UL << UART_CONFIG_HWFC_Pos) /*!< Bit mask of HWFC field. */
Kojto 91:031413cf7a89 6245 #define UART_CONFIG_HWFC_Disabled (0UL) /*!< Hardware flow control disabled. */
Kojto 91:031413cf7a89 6246 #define UART_CONFIG_HWFC_Enabled (1UL) /*!< Hardware flow control enabled. */
Kojto 91:031413cf7a89 6247
Kojto 91:031413cf7a89 6248 /* Register: UART_POWER */
Kojto 91:031413cf7a89 6249 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 6250
Kojto 91:031413cf7a89 6251 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 6252 #define UART_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 6253 #define UART_POWER_POWER_Msk (0x1UL << UART_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 6254 #define UART_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 6255 #define UART_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 6256
Kojto 91:031413cf7a89 6257
Kojto 91:031413cf7a89 6258 /* Peripheral: UICR */
Kojto 91:031413cf7a89 6259 /* Description: User Information Configuration. */
Kojto 91:031413cf7a89 6260
Kojto 91:031413cf7a89 6261 /* Register: UICR_RBPCONF */
Kojto 91:031413cf7a89 6262 /* Description: Readback protection configuration. */
Kojto 91:031413cf7a89 6263
Kojto 91:031413cf7a89 6264 /* Bits 15..8 : Readback protect all code in the device. */
Kojto 91:031413cf7a89 6265 #define UICR_RBPCONF_PALL_Pos (8UL) /*!< Position of PALL field. */
Kojto 91:031413cf7a89 6266 #define UICR_RBPCONF_PALL_Msk (0xFFUL << UICR_RBPCONF_PALL_Pos) /*!< Bit mask of PALL field. */
Kojto 91:031413cf7a89 6267 #define UICR_RBPCONF_PALL_Disabled (0xFFUL) /*!< Disabled. */
Kojto 91:031413cf7a89 6268 #define UICR_RBPCONF_PALL_Enabled (0x00UL) /*!< Enabled. */
Kojto 91:031413cf7a89 6269
Kojto 91:031413cf7a89 6270 /* Bits 7..0 : Readback protect region 0. Will be ignored if pre-programmed factory code is present on the chip. */
Kojto 91:031413cf7a89 6271 #define UICR_RBPCONF_PR0_Pos (0UL) /*!< Position of PR0 field. */
Kojto 91:031413cf7a89 6272 #define UICR_RBPCONF_PR0_Msk (0xFFUL << UICR_RBPCONF_PR0_Pos) /*!< Bit mask of PR0 field. */
Kojto 91:031413cf7a89 6273 #define UICR_RBPCONF_PR0_Disabled (0xFFUL) /*!< Disabled. */
Kojto 91:031413cf7a89 6274 #define UICR_RBPCONF_PR0_Enabled (0x00UL) /*!< Enabled. */
Kojto 91:031413cf7a89 6275
Kojto 91:031413cf7a89 6276 /* Register: UICR_XTALFREQ */
Kojto 91:031413cf7a89 6277 /* Description: Reset value for CLOCK XTALFREQ register. */
Kojto 91:031413cf7a89 6278
Kojto 91:031413cf7a89 6279 /* Bits 7..0 : Reset value for CLOCK XTALFREQ register. */
Kojto 91:031413cf7a89 6280 #define UICR_XTALFREQ_XTALFREQ_Pos (0UL) /*!< Position of XTALFREQ field. */
Kojto 91:031413cf7a89 6281 #define UICR_XTALFREQ_XTALFREQ_Msk (0xFFUL << UICR_XTALFREQ_XTALFREQ_Pos) /*!< Bit mask of XTALFREQ field. */
Kojto 91:031413cf7a89 6282 #define UICR_XTALFREQ_XTALFREQ_16MHz (0xFFUL) /*!< 16MHz Xtal is used. */
Kojto 91:031413cf7a89 6283 #define UICR_XTALFREQ_XTALFREQ_32MHz (0x00UL) /*!< 32MHz Xtal is used. */
Kojto 91:031413cf7a89 6284
Kojto 91:031413cf7a89 6285 /* Register: UICR_FWID */
Kojto 91:031413cf7a89 6286 /* Description: Firmware ID. */
Kojto 91:031413cf7a89 6287
Kojto 91:031413cf7a89 6288 /* Bits 15..0 : Identification number for the firmware loaded into the chip. */
Kojto 91:031413cf7a89 6289 #define UICR_FWID_FWID_Pos (0UL) /*!< Position of FWID field. */
Kojto 91:031413cf7a89 6290 #define UICR_FWID_FWID_Msk (0xFFFFUL << UICR_FWID_FWID_Pos) /*!< Bit mask of FWID field. */
Kojto 91:031413cf7a89 6291
Kojto 91:031413cf7a89 6292
Kojto 91:031413cf7a89 6293 /* Peripheral: WDT */
Kojto 91:031413cf7a89 6294 /* Description: Watchdog Timer. */
Kojto 91:031413cf7a89 6295
Kojto 91:031413cf7a89 6296 /* Register: WDT_INTENSET */
Kojto 91:031413cf7a89 6297 /* Description: Interrupt enable set register. */
Kojto 91:031413cf7a89 6298
Kojto 91:031413cf7a89 6299 /* Bit 0 : Enable interrupt on TIMEOUT event. */
Kojto 91:031413cf7a89 6300 #define WDT_INTENSET_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
Kojto 91:031413cf7a89 6301 #define WDT_INTENSET_TIMEOUT_Msk (0x1UL << WDT_INTENSET_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
Kojto 91:031413cf7a89 6302 #define WDT_INTENSET_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6303 #define WDT_INTENSET_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6304 #define WDT_INTENSET_TIMEOUT_Set (1UL) /*!< Enable interrupt on write. */
Kojto 91:031413cf7a89 6305
Kojto 91:031413cf7a89 6306 /* Register: WDT_INTENCLR */
Kojto 91:031413cf7a89 6307 /* Description: Interrupt enable clear register. */
Kojto 91:031413cf7a89 6308
Kojto 91:031413cf7a89 6309 /* Bit 0 : Disable interrupt on TIMEOUT event. */
Kojto 91:031413cf7a89 6310 #define WDT_INTENCLR_TIMEOUT_Pos (0UL) /*!< Position of TIMEOUT field. */
Kojto 91:031413cf7a89 6311 #define WDT_INTENCLR_TIMEOUT_Msk (0x1UL << WDT_INTENCLR_TIMEOUT_Pos) /*!< Bit mask of TIMEOUT field. */
Kojto 91:031413cf7a89 6312 #define WDT_INTENCLR_TIMEOUT_Disabled (0UL) /*!< Interrupt disabled. */
Kojto 91:031413cf7a89 6313 #define WDT_INTENCLR_TIMEOUT_Enabled (1UL) /*!< Interrupt enabled. */
Kojto 91:031413cf7a89 6314 #define WDT_INTENCLR_TIMEOUT_Clear (1UL) /*!< Disable interrupt on write. */
Kojto 91:031413cf7a89 6315
Kojto 91:031413cf7a89 6316 /* Register: WDT_RUNSTATUS */
Kojto 91:031413cf7a89 6317 /* Description: Watchdog running status. */
Kojto 91:031413cf7a89 6318
Kojto 91:031413cf7a89 6319 /* Bit 0 : Watchdog running status. */
Kojto 91:031413cf7a89 6320 #define WDT_RUNSTATUS_RUNSTATUS_Pos (0UL) /*!< Position of RUNSTATUS field. */
Kojto 91:031413cf7a89 6321 #define WDT_RUNSTATUS_RUNSTATUS_Msk (0x1UL << WDT_RUNSTATUS_RUNSTATUS_Pos) /*!< Bit mask of RUNSTATUS field. */
Kojto 91:031413cf7a89 6322 #define WDT_RUNSTATUS_RUNSTATUS_NotRunning (0UL) /*!< Watchdog timer is not running. */
Kojto 91:031413cf7a89 6323 #define WDT_RUNSTATUS_RUNSTATUS_Running (1UL) /*!< Watchdog timer is running. */
Kojto 91:031413cf7a89 6324
Kojto 91:031413cf7a89 6325 /* Register: WDT_REQSTATUS */
Kojto 91:031413cf7a89 6326 /* Description: Request status. */
Kojto 91:031413cf7a89 6327
Kojto 91:031413cf7a89 6328 /* Bit 7 : Request status for RR[7]. */
Kojto 91:031413cf7a89 6329 #define WDT_REQSTATUS_RR7_Pos (7UL) /*!< Position of RR7 field. */
Kojto 91:031413cf7a89 6330 #define WDT_REQSTATUS_RR7_Msk (0x1UL << WDT_REQSTATUS_RR7_Pos) /*!< Bit mask of RR7 field. */
Kojto 91:031413cf7a89 6331 #define WDT_REQSTATUS_RR7_DisabledOrRequested (0UL) /*!< RR[7] register is not enabled or has already requested reload. */
Kojto 91:031413cf7a89 6332 #define WDT_REQSTATUS_RR7_EnabledAndUnrequested (1UL) /*!< RR[7] register is enabled and has not jet requested. */
Kojto 91:031413cf7a89 6333
Kojto 91:031413cf7a89 6334 /* Bit 6 : Request status for RR[6]. */
Kojto 91:031413cf7a89 6335 #define WDT_REQSTATUS_RR6_Pos (6UL) /*!< Position of RR6 field. */
Kojto 91:031413cf7a89 6336 #define WDT_REQSTATUS_RR6_Msk (0x1UL << WDT_REQSTATUS_RR6_Pos) /*!< Bit mask of RR6 field. */
Kojto 91:031413cf7a89 6337 #define WDT_REQSTATUS_RR6_DisabledOrRequested (0UL) /*!< RR[6] register is not enabled or has already requested reload. */
Kojto 91:031413cf7a89 6338 #define WDT_REQSTATUS_RR6_EnabledAndUnrequested (1UL) /*!< RR[6] register is enabled and has not jet requested. */
Kojto 91:031413cf7a89 6339
Kojto 91:031413cf7a89 6340 /* Bit 5 : Request status for RR[5]. */
Kojto 91:031413cf7a89 6341 #define WDT_REQSTATUS_RR5_Pos (5UL) /*!< Position of RR5 field. */
Kojto 91:031413cf7a89 6342 #define WDT_REQSTATUS_RR5_Msk (0x1UL << WDT_REQSTATUS_RR5_Pos) /*!< Bit mask of RR5 field. */
Kojto 91:031413cf7a89 6343 #define WDT_REQSTATUS_RR5_DisabledOrRequested (0UL) /*!< RR[5] register is not enabled or has already requested reload. */
Kojto 91:031413cf7a89 6344 #define WDT_REQSTATUS_RR5_EnabledAndUnrequested (1UL) /*!< RR[5] register is enabled and has not jet requested. */
Kojto 91:031413cf7a89 6345
Kojto 91:031413cf7a89 6346 /* Bit 4 : Request status for RR[4]. */
Kojto 91:031413cf7a89 6347 #define WDT_REQSTATUS_RR4_Pos (4UL) /*!< Position of RR4 field. */
Kojto 91:031413cf7a89 6348 #define WDT_REQSTATUS_RR4_Msk (0x1UL << WDT_REQSTATUS_RR4_Pos) /*!< Bit mask of RR4 field. */
Kojto 91:031413cf7a89 6349 #define WDT_REQSTATUS_RR4_DisabledOrRequested (0UL) /*!< RR[4] register is not enabled or has already requested reload. */
Kojto 91:031413cf7a89 6350 #define WDT_REQSTATUS_RR4_EnabledAndUnrequested (1UL) /*!< RR[4] register is enabled and has not jet requested. */
Kojto 91:031413cf7a89 6351
Kojto 91:031413cf7a89 6352 /* Bit 3 : Request status for RR[3]. */
Kojto 91:031413cf7a89 6353 #define WDT_REQSTATUS_RR3_Pos (3UL) /*!< Position of RR3 field. */
Kojto 91:031413cf7a89 6354 #define WDT_REQSTATUS_RR3_Msk (0x1UL << WDT_REQSTATUS_RR3_Pos) /*!< Bit mask of RR3 field. */
Kojto 91:031413cf7a89 6355 #define WDT_REQSTATUS_RR3_DisabledOrRequested (0UL) /*!< RR[3] register is not enabled or has already requested reload. */
Kojto 91:031413cf7a89 6356 #define WDT_REQSTATUS_RR3_EnabledAndUnrequested (1UL) /*!< RR[3] register is enabled and has not jet requested. */
Kojto 91:031413cf7a89 6357
Kojto 91:031413cf7a89 6358 /* Bit 2 : Request status for RR[2]. */
Kojto 91:031413cf7a89 6359 #define WDT_REQSTATUS_RR2_Pos (2UL) /*!< Position of RR2 field. */
Kojto 91:031413cf7a89 6360 #define WDT_REQSTATUS_RR2_Msk (0x1UL << WDT_REQSTATUS_RR2_Pos) /*!< Bit mask of RR2 field. */
Kojto 91:031413cf7a89 6361 #define WDT_REQSTATUS_RR2_DisabledOrRequested (0UL) /*!< RR[2] register is not enabled or has already requested reload. */
Kojto 91:031413cf7a89 6362 #define WDT_REQSTATUS_RR2_EnabledAndUnrequested (1UL) /*!< RR[2] register is enabled and has not jet requested. */
Kojto 91:031413cf7a89 6363
Kojto 91:031413cf7a89 6364 /* Bit 1 : Request status for RR[1]. */
Kojto 91:031413cf7a89 6365 #define WDT_REQSTATUS_RR1_Pos (1UL) /*!< Position of RR1 field. */
Kojto 91:031413cf7a89 6366 #define WDT_REQSTATUS_RR1_Msk (0x1UL << WDT_REQSTATUS_RR1_Pos) /*!< Bit mask of RR1 field. */
Kojto 91:031413cf7a89 6367 #define WDT_REQSTATUS_RR1_DisabledOrRequested (0UL) /*!< RR[1] register is not enabled or has already requested reload. */
Kojto 91:031413cf7a89 6368 #define WDT_REQSTATUS_RR1_EnabledAndUnrequested (1UL) /*!< RR[1] register is enabled and has not jet requested. */
Kojto 91:031413cf7a89 6369
Kojto 91:031413cf7a89 6370 /* Bit 0 : Request status for RR[0]. */
Kojto 91:031413cf7a89 6371 #define WDT_REQSTATUS_RR0_Pos (0UL) /*!< Position of RR0 field. */
Kojto 91:031413cf7a89 6372 #define WDT_REQSTATUS_RR0_Msk (0x1UL << WDT_REQSTATUS_RR0_Pos) /*!< Bit mask of RR0 field. */
Kojto 91:031413cf7a89 6373 #define WDT_REQSTATUS_RR0_DisabledOrRequested (0UL) /*!< RR[0] register is not enabled or has already requested reload. */
Kojto 91:031413cf7a89 6374 #define WDT_REQSTATUS_RR0_EnabledAndUnrequested (1UL) /*!< RR[0] register is enabled and has not jet requested. */
Kojto 91:031413cf7a89 6375
Kojto 91:031413cf7a89 6376 /* Register: WDT_RREN */
Kojto 91:031413cf7a89 6377 /* Description: Reload request enable. */
Kojto 91:031413cf7a89 6378
Kojto 91:031413cf7a89 6379 /* Bit 7 : Enable or disable RR[7] register. */
Kojto 91:031413cf7a89 6380 #define WDT_RREN_RR7_Pos (7UL) /*!< Position of RR7 field. */
Kojto 91:031413cf7a89 6381 #define WDT_RREN_RR7_Msk (0x1UL << WDT_RREN_RR7_Pos) /*!< Bit mask of RR7 field. */
Kojto 91:031413cf7a89 6382 #define WDT_RREN_RR7_Disabled (0UL) /*!< RR[7] register is disabled. */
Kojto 91:031413cf7a89 6383 #define WDT_RREN_RR7_Enabled (1UL) /*!< RR[7] register is enabled. */
Kojto 91:031413cf7a89 6384
Kojto 91:031413cf7a89 6385 /* Bit 6 : Enable or disable RR[6] register. */
Kojto 91:031413cf7a89 6386 #define WDT_RREN_RR6_Pos (6UL) /*!< Position of RR6 field. */
Kojto 91:031413cf7a89 6387 #define WDT_RREN_RR6_Msk (0x1UL << WDT_RREN_RR6_Pos) /*!< Bit mask of RR6 field. */
Kojto 91:031413cf7a89 6388 #define WDT_RREN_RR6_Disabled (0UL) /*!< RR[6] register is disabled. */
Kojto 91:031413cf7a89 6389 #define WDT_RREN_RR6_Enabled (1UL) /*!< RR[6] register is enabled. */
Kojto 91:031413cf7a89 6390
Kojto 91:031413cf7a89 6391 /* Bit 5 : Enable or disable RR[5] register. */
Kojto 91:031413cf7a89 6392 #define WDT_RREN_RR5_Pos (5UL) /*!< Position of RR5 field. */
Kojto 91:031413cf7a89 6393 #define WDT_RREN_RR5_Msk (0x1UL << WDT_RREN_RR5_Pos) /*!< Bit mask of RR5 field. */
Kojto 91:031413cf7a89 6394 #define WDT_RREN_RR5_Disabled (0UL) /*!< RR[5] register is disabled. */
Kojto 91:031413cf7a89 6395 #define WDT_RREN_RR5_Enabled (1UL) /*!< RR[5] register is enabled. */
Kojto 91:031413cf7a89 6396
Kojto 91:031413cf7a89 6397 /* Bit 4 : Enable or disable RR[4] register. */
Kojto 91:031413cf7a89 6398 #define WDT_RREN_RR4_Pos (4UL) /*!< Position of RR4 field. */
Kojto 91:031413cf7a89 6399 #define WDT_RREN_RR4_Msk (0x1UL << WDT_RREN_RR4_Pos) /*!< Bit mask of RR4 field. */
Kojto 91:031413cf7a89 6400 #define WDT_RREN_RR4_Disabled (0UL) /*!< RR[4] register is disabled. */
Kojto 91:031413cf7a89 6401 #define WDT_RREN_RR4_Enabled (1UL) /*!< RR[4] register is enabled. */
Kojto 91:031413cf7a89 6402
Kojto 91:031413cf7a89 6403 /* Bit 3 : Enable or disable RR[3] register. */
Kojto 91:031413cf7a89 6404 #define WDT_RREN_RR3_Pos (3UL) /*!< Position of RR3 field. */
Kojto 91:031413cf7a89 6405 #define WDT_RREN_RR3_Msk (0x1UL << WDT_RREN_RR3_Pos) /*!< Bit mask of RR3 field. */
Kojto 91:031413cf7a89 6406 #define WDT_RREN_RR3_Disabled (0UL) /*!< RR[3] register is disabled. */
Kojto 91:031413cf7a89 6407 #define WDT_RREN_RR3_Enabled (1UL) /*!< RR[3] register is enabled. */
Kojto 91:031413cf7a89 6408
Kojto 91:031413cf7a89 6409 /* Bit 2 : Enable or disable RR[2] register. */
Kojto 91:031413cf7a89 6410 #define WDT_RREN_RR2_Pos (2UL) /*!< Position of RR2 field. */
Kojto 91:031413cf7a89 6411 #define WDT_RREN_RR2_Msk (0x1UL << WDT_RREN_RR2_Pos) /*!< Bit mask of RR2 field. */
Kojto 91:031413cf7a89 6412 #define WDT_RREN_RR2_Disabled (0UL) /*!< RR[2] register is disabled. */
Kojto 91:031413cf7a89 6413 #define WDT_RREN_RR2_Enabled (1UL) /*!< RR[2] register is enabled. */
Kojto 91:031413cf7a89 6414
Kojto 91:031413cf7a89 6415 /* Bit 1 : Enable or disable RR[1] register. */
Kojto 91:031413cf7a89 6416 #define WDT_RREN_RR1_Pos (1UL) /*!< Position of RR1 field. */
Kojto 91:031413cf7a89 6417 #define WDT_RREN_RR1_Msk (0x1UL << WDT_RREN_RR1_Pos) /*!< Bit mask of RR1 field. */
Kojto 91:031413cf7a89 6418 #define WDT_RREN_RR1_Disabled (0UL) /*!< RR[1] register is disabled. */
Kojto 91:031413cf7a89 6419 #define WDT_RREN_RR1_Enabled (1UL) /*!< RR[1] register is enabled. */
Kojto 91:031413cf7a89 6420
Kojto 91:031413cf7a89 6421 /* Bit 0 : Enable or disable RR[0] register. */
Kojto 91:031413cf7a89 6422 #define WDT_RREN_RR0_Pos (0UL) /*!< Position of RR0 field. */
Kojto 91:031413cf7a89 6423 #define WDT_RREN_RR0_Msk (0x1UL << WDT_RREN_RR0_Pos) /*!< Bit mask of RR0 field. */
Kojto 91:031413cf7a89 6424 #define WDT_RREN_RR0_Disabled (0UL) /*!< RR[0] register is disabled. */
Kojto 91:031413cf7a89 6425 #define WDT_RREN_RR0_Enabled (1UL) /*!< RR[0] register is enabled. */
Kojto 91:031413cf7a89 6426
Kojto 91:031413cf7a89 6427 /* Register: WDT_CONFIG */
Kojto 91:031413cf7a89 6428 /* Description: Configuration register. */
Kojto 91:031413cf7a89 6429
Kojto 91:031413cf7a89 6430 /* Bit 3 : Configure the watchdog to pause or not while the CPU is halted by the debugger. */
Kojto 91:031413cf7a89 6431 #define WDT_CONFIG_HALT_Pos (3UL) /*!< Position of HALT field. */
Kojto 91:031413cf7a89 6432 #define WDT_CONFIG_HALT_Msk (0x1UL << WDT_CONFIG_HALT_Pos) /*!< Bit mask of HALT field. */
Kojto 91:031413cf7a89 6433 #define WDT_CONFIG_HALT_Pause (0UL) /*!< Pause watchdog while the CPU is halted by the debugger. */
Kojto 91:031413cf7a89 6434 #define WDT_CONFIG_HALT_Run (1UL) /*!< Do not pause watchdog while the CPU is halted by the debugger. */
Kojto 91:031413cf7a89 6435
Kojto 91:031413cf7a89 6436 /* Bit 0 : Configure the watchdog to pause or not while the CPU is sleeping. */
Kojto 91:031413cf7a89 6437 #define WDT_CONFIG_SLEEP_Pos (0UL) /*!< Position of SLEEP field. */
Kojto 91:031413cf7a89 6438 #define WDT_CONFIG_SLEEP_Msk (0x1UL << WDT_CONFIG_SLEEP_Pos) /*!< Bit mask of SLEEP field. */
Kojto 91:031413cf7a89 6439 #define WDT_CONFIG_SLEEP_Pause (0UL) /*!< Pause watchdog while the CPU is asleep. */
Kojto 91:031413cf7a89 6440 #define WDT_CONFIG_SLEEP_Run (1UL) /*!< Do not pause watchdog while the CPU is asleep. */
Kojto 91:031413cf7a89 6441
Kojto 91:031413cf7a89 6442 /* Register: WDT_RR */
Kojto 91:031413cf7a89 6443 /* Description: Reload requests registers. */
Kojto 91:031413cf7a89 6444
Kojto 91:031413cf7a89 6445 /* Bits 31..0 : Reload register. */
Kojto 91:031413cf7a89 6446 #define WDT_RR_RR_Pos (0UL) /*!< Position of RR field. */
Kojto 91:031413cf7a89 6447 #define WDT_RR_RR_Msk (0xFFFFFFFFUL << WDT_RR_RR_Pos) /*!< Bit mask of RR field. */
Kojto 91:031413cf7a89 6448 #define WDT_RR_RR_Reload (0x6E524635UL) /*!< Value to request a reload of the watchdog timer. */
Kojto 91:031413cf7a89 6449
Kojto 91:031413cf7a89 6450 /* Register: WDT_POWER */
Kojto 91:031413cf7a89 6451 /* Description: Peripheral power control. */
Kojto 91:031413cf7a89 6452
Kojto 91:031413cf7a89 6453 /* Bit 0 : Peripheral power control. */
Kojto 91:031413cf7a89 6454 #define WDT_POWER_POWER_Pos (0UL) /*!< Position of POWER field. */
Kojto 91:031413cf7a89 6455 #define WDT_POWER_POWER_Msk (0x1UL << WDT_POWER_POWER_Pos) /*!< Bit mask of POWER field. */
Kojto 91:031413cf7a89 6456 #define WDT_POWER_POWER_Disabled (0UL) /*!< Module power disabled. */
Kojto 91:031413cf7a89 6457 #define WDT_POWER_POWER_Enabled (1UL) /*!< Module power enabled. */
Kojto 91:031413cf7a89 6458
Kojto 91:031413cf7a89 6459
Kojto 91:031413cf7a89 6460 /*lint --flb "Leave library region" */
Kojto 91:031413cf7a89 6461 #endif