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TARGET_NRF51822/nrf51.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
80:8e73be2a2ac1
Child:
93:e188a91d3eaa
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 80:8e73be2a2ac1 1 /* Copyright (c) 2012 Nordic Semiconductor. All Rights Reserved.
emilmont 80:8e73be2a2ac1 2 *
emilmont 80:8e73be2a2ac1 3 * The information contained herein is property of Nordic Semiconductor ASA.
emilmont 80:8e73be2a2ac1 4 * Terms and conditions of usage are described in detail in NORDIC
emilmont 80:8e73be2a2ac1 5 * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 * Licensees are granted free, non-transferable use of the information. NO
emilmont 80:8e73be2a2ac1 8 * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
emilmont 80:8e73be2a2ac1 9 * the file.
emilmont 80:8e73be2a2ac1 10 *
emilmont 80:8e73be2a2ac1 11 */
emilmont 80:8e73be2a2ac1 12
emilmont 80:8e73be2a2ac1 13
emilmont 80:8e73be2a2ac1 14
emilmont 80:8e73be2a2ac1 15 /** @addtogroup Nordic Semiconductor
emilmont 80:8e73be2a2ac1 16 * @{
emilmont 80:8e73be2a2ac1 17 */
emilmont 80:8e73be2a2ac1 18
emilmont 80:8e73be2a2ac1 19 /** @addtogroup nRF51
emilmont 80:8e73be2a2ac1 20 * @{
emilmont 80:8e73be2a2ac1 21 */
emilmont 80:8e73be2a2ac1 22
emilmont 80:8e73be2a2ac1 23 #ifndef NRF51_H
emilmont 80:8e73be2a2ac1 24 #define NRF51_H
emilmont 80:8e73be2a2ac1 25
emilmont 80:8e73be2a2ac1 26 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 27 extern "C" {
emilmont 80:8e73be2a2ac1 28 #endif
emilmont 80:8e73be2a2ac1 29
emilmont 80:8e73be2a2ac1 30
emilmont 80:8e73be2a2ac1 31 /* ------------------------- Interrupt Number Definition ------------------------ */
emilmont 80:8e73be2a2ac1 32
emilmont 80:8e73be2a2ac1 33 typedef enum {
emilmont 80:8e73be2a2ac1 34 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
emilmont 80:8e73be2a2ac1 35 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
emilmont 80:8e73be2a2ac1 36 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
emilmont 80:8e73be2a2ac1 37 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
emilmont 80:8e73be2a2ac1 38 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
emilmont 80:8e73be2a2ac1 39 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
emilmont 80:8e73be2a2ac1 40 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
emilmont 80:8e73be2a2ac1 41 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
emilmont 80:8e73be2a2ac1 42 /* ---------------------- nRF51 Specific Interrupt Numbers ---------------------- */
emilmont 80:8e73be2a2ac1 43 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
emilmont 80:8e73be2a2ac1 44 RADIO_IRQn = 1, /*!< 1 RADIO */
emilmont 80:8e73be2a2ac1 45 UART0_IRQn = 2, /*!< 2 UART0 */
emilmont 80:8e73be2a2ac1 46 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
emilmont 80:8e73be2a2ac1 47 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
emilmont 80:8e73be2a2ac1 48 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
emilmont 80:8e73be2a2ac1 49 ADC_IRQn = 7, /*!< 7 ADC */
emilmont 80:8e73be2a2ac1 50 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
emilmont 80:8e73be2a2ac1 51 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
emilmont 80:8e73be2a2ac1 52 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
emilmont 80:8e73be2a2ac1 53 RTC0_IRQn = 11, /*!< 11 RTC0 */
emilmont 80:8e73be2a2ac1 54 TEMP_IRQn = 12, /*!< 12 TEMP */
emilmont 80:8e73be2a2ac1 55 RNG_IRQn = 13, /*!< 13 RNG */
emilmont 80:8e73be2a2ac1 56 ECB_IRQn = 14, /*!< 14 ECB */
emilmont 80:8e73be2a2ac1 57 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
emilmont 80:8e73be2a2ac1 58 WDT_IRQn = 16, /*!< 16 WDT */
emilmont 80:8e73be2a2ac1 59 RTC1_IRQn = 17, /*!< 17 RTC1 */
emilmont 80:8e73be2a2ac1 60 QDEC_IRQn = 18, /*!< 18 QDEC */
emilmont 80:8e73be2a2ac1 61 LPCOMP_COMP_IRQn = 19, /*!< 19 LPCOMP_COMP */
emilmont 80:8e73be2a2ac1 62 SWI0_IRQn = 20, /*!< 20 SWI0 */
emilmont 80:8e73be2a2ac1 63 SWI1_IRQn = 21, /*!< 21 SWI1 */
emilmont 80:8e73be2a2ac1 64 SWI2_IRQn = 22, /*!< 22 SWI2 */
emilmont 80:8e73be2a2ac1 65 SWI3_IRQn = 23, /*!< 23 SWI3 */
emilmont 80:8e73be2a2ac1 66 SWI4_IRQn = 24, /*!< 24 SWI4 */
emilmont 80:8e73be2a2ac1 67 SWI5_IRQn = 25 /*!< 25 SWI5 */
emilmont 80:8e73be2a2ac1 68 } IRQn_Type;
emilmont 80:8e73be2a2ac1 69
emilmont 80:8e73be2a2ac1 70
emilmont 80:8e73be2a2ac1 71 /** @addtogroup Configuration_of_CMSIS
emilmont 80:8e73be2a2ac1 72 * @{
emilmont 80:8e73be2a2ac1 73 */
emilmont 80:8e73be2a2ac1 74
emilmont 80:8e73be2a2ac1 75
emilmont 80:8e73be2a2ac1 76 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 77 /* ================ Processor and Core Peripheral Section ================ */
emilmont 80:8e73be2a2ac1 78 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 79
emilmont 80:8e73be2a2ac1 80 /* ----------------Configuration of the cm0 Processor and Core Peripherals---------------- */
emilmont 80:8e73be2a2ac1 81 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
emilmont 80:8e73be2a2ac1 82 #define __MPU_PRESENT 0 /*!< MPU present or not */
emilmont 80:8e73be2a2ac1 83 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
emilmont 80:8e73be2a2ac1 84 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 80:8e73be2a2ac1 85 /** @} */ /* End of group Configuration_of_CMSIS */
emilmont 80:8e73be2a2ac1 86
emilmont 80:8e73be2a2ac1 87 #include <core_cm0.h> /*!< Cortex-M0 processor and core peripherals */
emilmont 80:8e73be2a2ac1 88 #include "system_nrf51822.h" /*!< nRF51 System */
emilmont 80:8e73be2a2ac1 89
emilmont 80:8e73be2a2ac1 90
emilmont 80:8e73be2a2ac1 91 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 92 /* ================ Device Specific Peripheral Section ================ */
emilmont 80:8e73be2a2ac1 93 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 94
emilmont 80:8e73be2a2ac1 95
emilmont 80:8e73be2a2ac1 96 /** @addtogroup Device_Peripheral_Registers
emilmont 80:8e73be2a2ac1 97 * @{
emilmont 80:8e73be2a2ac1 98 */
emilmont 80:8e73be2a2ac1 99
emilmont 80:8e73be2a2ac1 100
emilmont 80:8e73be2a2ac1 101 /* ------------------- Start of section using anonymous unions ------------------ */
emilmont 80:8e73be2a2ac1 102 #if defined(__CC_ARM)
emilmont 80:8e73be2a2ac1 103 #pragma push
emilmont 80:8e73be2a2ac1 104 #pragma anon_unions
emilmont 80:8e73be2a2ac1 105 #elif defined(__ICCARM__)
emilmont 80:8e73be2a2ac1 106 #pragma language=extended
emilmont 80:8e73be2a2ac1 107 #elif defined(__GNUC__)
emilmont 80:8e73be2a2ac1 108 /* anonymous unions are enabled by default */
emilmont 80:8e73be2a2ac1 109 #elif defined(__TMS470__)
emilmont 80:8e73be2a2ac1 110 /* anonymous unions are enabled by default */
emilmont 80:8e73be2a2ac1 111 #elif defined(__TASKING__)
emilmont 80:8e73be2a2ac1 112 #pragma warning 586
emilmont 80:8e73be2a2ac1 113 #else
emilmont 80:8e73be2a2ac1 114 #warning Not supported compiler type
emilmont 80:8e73be2a2ac1 115 #endif
emilmont 80:8e73be2a2ac1 116
emilmont 80:8e73be2a2ac1 117
emilmont 80:8e73be2a2ac1 118 typedef struct {
emilmont 80:8e73be2a2ac1 119 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
emilmont 80:8e73be2a2ac1 120 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
emilmont 80:8e73be2a2ac1 121 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
emilmont 80:8e73be2a2ac1 122 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
emilmont 80:8e73be2a2ac1 123 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
emilmont 80:8e73be2a2ac1 124 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
emilmont 80:8e73be2a2ac1 125 } AMLI_RAMPRI_Type;
emilmont 80:8e73be2a2ac1 126
emilmont 80:8e73be2a2ac1 127 typedef struct {
emilmont 80:8e73be2a2ac1 128 __O uint32_t EN; /*!< Enable channel group. */
emilmont 80:8e73be2a2ac1 129 __O uint32_t DIS; /*!< Disable channel group. */
emilmont 80:8e73be2a2ac1 130 } PPI_TASKS_CHG_Type;
emilmont 80:8e73be2a2ac1 131
emilmont 80:8e73be2a2ac1 132 typedef struct {
emilmont 80:8e73be2a2ac1 133 __IO uint32_t EEP; /*!< Channel event end-point. */
emilmont 80:8e73be2a2ac1 134 __IO uint32_t TEP; /*!< Channel task end-point. */
emilmont 80:8e73be2a2ac1 135 } PPI_CH_Type;
emilmont 80:8e73be2a2ac1 136
emilmont 80:8e73be2a2ac1 137
emilmont 80:8e73be2a2ac1 138 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 139 /* ================ POWER ================ */
emilmont 80:8e73be2a2ac1 140 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 141
emilmont 80:8e73be2a2ac1 142
emilmont 80:8e73be2a2ac1 143 /**
emilmont 80:8e73be2a2ac1 144 * @brief Power Control. (POWER)
emilmont 80:8e73be2a2ac1 145 */
emilmont 80:8e73be2a2ac1 146
emilmont 80:8e73be2a2ac1 147 typedef struct { /*!< POWER Structure */
emilmont 80:8e73be2a2ac1 148 __I uint32_t RESERVED0[30];
emilmont 80:8e73be2a2ac1 149 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
emilmont 80:8e73be2a2ac1 150 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
emilmont 80:8e73be2a2ac1 151 __I uint32_t RESERVED1[34];
emilmont 80:8e73be2a2ac1 152 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
emilmont 80:8e73be2a2ac1 153 __I uint32_t RESERVED2[126];
emilmont 80:8e73be2a2ac1 154 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 155 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 156 __I uint32_t RESERVED3[61];
emilmont 80:8e73be2a2ac1 157 __IO uint32_t RESETREAS; /*!< Reset reason. */
emilmont 80:8e73be2a2ac1 158 __I uint32_t RESERVED4[63];
emilmont 80:8e73be2a2ac1 159 __O uint32_t SYSTEMOFF; /*!< System off register. */
emilmont 80:8e73be2a2ac1 160 __I uint32_t RESERVED5[3];
emilmont 80:8e73be2a2ac1 161 __IO uint32_t POFCON; /*!< Power failure configuration. */
emilmont 80:8e73be2a2ac1 162 __I uint32_t RESERVED6[2];
emilmont 80:8e73be2a2ac1 163 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
emilmont 80:8e73be2a2ac1 164 register. */
emilmont 80:8e73be2a2ac1 165 __I uint32_t RESERVED7;
emilmont 80:8e73be2a2ac1 166 __IO uint32_t RAMON; /*!< Ram on/off. */
emilmont 80:8e73be2a2ac1 167 __I uint32_t RESERVED8[7];
emilmont 80:8e73be2a2ac1 168 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
emilmont 80:8e73be2a2ac1 169 is a retained register. */
emilmont 80:8e73be2a2ac1 170 __I uint32_t RESERVED9[12];
emilmont 80:8e73be2a2ac1 171 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
emilmont 80:8e73be2a2ac1 172 } NRF_POWER_Type;
emilmont 80:8e73be2a2ac1 173
emilmont 80:8e73be2a2ac1 174
emilmont 80:8e73be2a2ac1 175 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 176 /* ================ CLOCK ================ */
emilmont 80:8e73be2a2ac1 177 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 178
emilmont 80:8e73be2a2ac1 179
emilmont 80:8e73be2a2ac1 180 /**
emilmont 80:8e73be2a2ac1 181 * @brief Clock control. (CLOCK)
emilmont 80:8e73be2a2ac1 182 */
emilmont 80:8e73be2a2ac1 183
emilmont 80:8e73be2a2ac1 184 typedef struct { /*!< CLOCK Structure */
emilmont 80:8e73be2a2ac1 185 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
emilmont 80:8e73be2a2ac1 186 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
emilmont 80:8e73be2a2ac1 187 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
emilmont 80:8e73be2a2ac1 188 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
emilmont 80:8e73be2a2ac1 189 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
emilmont 80:8e73be2a2ac1 190 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
emilmont 80:8e73be2a2ac1 191 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
emilmont 80:8e73be2a2ac1 192 __I uint32_t RESERVED0[57];
emilmont 80:8e73be2a2ac1 193 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
emilmont 80:8e73be2a2ac1 194 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
emilmont 80:8e73be2a2ac1 195 __I uint32_t RESERVED1;
emilmont 80:8e73be2a2ac1 196 __IO uint32_t EVENTS_DONE; /*!< Callibration of LFCLK RC oscillator completed. */
emilmont 80:8e73be2a2ac1 197 __IO uint32_t EVENTS_CTTO; /*!< Callibration timer timeout. */
emilmont 80:8e73be2a2ac1 198 __I uint32_t RESERVED2[124];
emilmont 80:8e73be2a2ac1 199 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 200 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 201 __I uint32_t RESERVED3[64];
emilmont 80:8e73be2a2ac1 202 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
emilmont 80:8e73be2a2ac1 203 __I uint32_t RESERVED4[2];
emilmont 80:8e73be2a2ac1 204 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
emilmont 80:8e73be2a2ac1 205 __I uint32_t RESERVED5[63];
emilmont 80:8e73be2a2ac1 206 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
emilmont 80:8e73be2a2ac1 207 __I uint32_t RESERVED6[7];
emilmont 80:8e73be2a2ac1 208 __IO uint32_t CTIV; /*!< Calibration timer interval. */
emilmont 80:8e73be2a2ac1 209 __I uint32_t RESERVED7[5];
emilmont 80:8e73be2a2ac1 210 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
emilmont 80:8e73be2a2ac1 211 } NRF_CLOCK_Type;
emilmont 80:8e73be2a2ac1 212
emilmont 80:8e73be2a2ac1 213
emilmont 80:8e73be2a2ac1 214 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 215 /* ================ MPU ================ */
emilmont 80:8e73be2a2ac1 216 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 217
emilmont 80:8e73be2a2ac1 218
emilmont 80:8e73be2a2ac1 219 /**
emilmont 80:8e73be2a2ac1 220 * @brief Memory Protection Unit. (MPU)
emilmont 80:8e73be2a2ac1 221 */
emilmont 80:8e73be2a2ac1 222
emilmont 80:8e73be2a2ac1 223 typedef struct { /*!< MPU Structure */
emilmont 80:8e73be2a2ac1 224 __I uint32_t RESERVED0[330];
emilmont 80:8e73be2a2ac1 225 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
emilmont 80:8e73be2a2ac1 226 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
emilmont 80:8e73be2a2ac1 227 __I uint32_t RESERVED1[52];
emilmont 80:8e73be2a2ac1 228 __IO uint32_t PROTENSET0; /*!< Protection bit enable set register for low addresses. */
emilmont 80:8e73be2a2ac1 229 __IO uint32_t PROTENSET1; /*!< Protection bit enable set register for high addresses. */
emilmont 80:8e73be2a2ac1 230 __IO uint32_t DISABLEINDEBUG; /*!< Disable protection mechanism in debug mode. */
emilmont 80:8e73be2a2ac1 231 } NRF_MPU_Type;
emilmont 80:8e73be2a2ac1 232
emilmont 80:8e73be2a2ac1 233
emilmont 80:8e73be2a2ac1 234 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 235 /* ================ PU ================ */
emilmont 80:8e73be2a2ac1 236 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 237
emilmont 80:8e73be2a2ac1 238
emilmont 80:8e73be2a2ac1 239 /**
emilmont 80:8e73be2a2ac1 240 * @brief Patch unit. (PU)
emilmont 80:8e73be2a2ac1 241 */
emilmont 80:8e73be2a2ac1 242
emilmont 80:8e73be2a2ac1 243 typedef struct { /*!< PU Structure */
emilmont 80:8e73be2a2ac1 244 __I uint32_t RESERVED0[448];
emilmont 80:8e73be2a2ac1 245 __IO uint32_t REPLACEADDR[8]; /*!< Address of first instruction to replace. */
emilmont 80:8e73be2a2ac1 246 __I uint32_t RESERVED1[24];
emilmont 80:8e73be2a2ac1 247 __IO uint32_t PATCHADDR[8]; /*!< Relative address of patch instructions. */
emilmont 80:8e73be2a2ac1 248 __I uint32_t RESERVED2[24];
emilmont 80:8e73be2a2ac1 249 __IO uint32_t PATCHEN; /*!< Patch enable register. */
emilmont 80:8e73be2a2ac1 250 __IO uint32_t PATCHENSET; /*!< Patch enable register. */
emilmont 80:8e73be2a2ac1 251 __IO uint32_t PATCHENCLR; /*!< Patch disable register. */
emilmont 80:8e73be2a2ac1 252 } NRF_PU_Type;
emilmont 80:8e73be2a2ac1 253
emilmont 80:8e73be2a2ac1 254
emilmont 80:8e73be2a2ac1 255 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 256 /* ================ AMLI ================ */
emilmont 80:8e73be2a2ac1 257 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 258
emilmont 80:8e73be2a2ac1 259
emilmont 80:8e73be2a2ac1 260 /**
emilmont 80:8e73be2a2ac1 261 * @brief AHB Multi-Layer Interface. (AMLI)
emilmont 80:8e73be2a2ac1 262 */
emilmont 80:8e73be2a2ac1 263
emilmont 80:8e73be2a2ac1 264 typedef struct { /*!< AMLI Structure */
emilmont 80:8e73be2a2ac1 265 __I uint32_t RESERVED0[896];
emilmont 80:8e73be2a2ac1 266 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
emilmont 80:8e73be2a2ac1 267 } NRF_AMLI_Type;
emilmont 80:8e73be2a2ac1 268
emilmont 80:8e73be2a2ac1 269
emilmont 80:8e73be2a2ac1 270 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 271 /* ================ RADIO ================ */
emilmont 80:8e73be2a2ac1 272 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 273
emilmont 80:8e73be2a2ac1 274
emilmont 80:8e73be2a2ac1 275 /**
emilmont 80:8e73be2a2ac1 276 * @brief The radio. (RADIO)
emilmont 80:8e73be2a2ac1 277 */
emilmont 80:8e73be2a2ac1 278
emilmont 80:8e73be2a2ac1 279 typedef struct { /*!< RADIO Structure */
emilmont 80:8e73be2a2ac1 280 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
emilmont 80:8e73be2a2ac1 281 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
emilmont 80:8e73be2a2ac1 282 __O uint32_t TASKS_START; /*!< Start radio. */
emilmont 80:8e73be2a2ac1 283 __O uint32_t TASKS_STOP; /*!< Stop radio. */
emilmont 80:8e73be2a2ac1 284 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
emilmont 80:8e73be2a2ac1 285 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
emilmont 80:8e73be2a2ac1 286 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
emilmont 80:8e73be2a2ac1 287 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
emilmont 80:8e73be2a2ac1 288 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
emilmont 80:8e73be2a2ac1 289 __I uint32_t RESERVED0[55];
emilmont 80:8e73be2a2ac1 290 __IO uint32_t EVENTS_READY; /*!< Ready event. */
emilmont 80:8e73be2a2ac1 291 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
emilmont 80:8e73be2a2ac1 292 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
emilmont 80:8e73be2a2ac1 293 __IO uint32_t EVENTS_END; /*!< End event. */
emilmont 80:8e73be2a2ac1 294 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
emilmont 80:8e73be2a2ac1 295 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
emilmont 80:8e73be2a2ac1 296 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
emilmont 80:8e73be2a2ac1 297 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
emilmont 80:8e73be2a2ac1 298 sample is ready for readout at the RSSISAMPLE register. */
emilmont 80:8e73be2a2ac1 299 __I uint32_t RESERVED1[2];
emilmont 80:8e73be2a2ac1 300 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BC register. */
emilmont 80:8e73be2a2ac1 301 __I uint32_t RESERVED2[53];
emilmont 80:8e73be2a2ac1 302 __IO uint32_t SHORTS; /*!< Shortcut for the radio. */
emilmont 80:8e73be2a2ac1 303 __I uint32_t RESERVED3[64];
emilmont 80:8e73be2a2ac1 304 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 305 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 306 __I uint32_t RESERVED4[61];
emilmont 80:8e73be2a2ac1 307 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
emilmont 80:8e73be2a2ac1 308 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 309 __I uint32_t RXMATCH; /*!< Received address. */
emilmont 80:8e73be2a2ac1 310 __I uint32_t RXCRC; /*!< Received CRC. */
emilmont 80:8e73be2a2ac1 311 __IO uint32_t DAI; /*!< Device address match index. */
emilmont 80:8e73be2a2ac1 312 __I uint32_t RESERVED6[60];
emilmont 80:8e73be2a2ac1 313 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
emilmont 80:8e73be2a2ac1 314 __IO uint32_t FREQUENCY; /*!< Frequency. */
emilmont 80:8e73be2a2ac1 315 __IO uint32_t TXPOWER; /*!< Output power. */
emilmont 80:8e73be2a2ac1 316 __IO uint32_t MODE; /*!< Data rate and modulation. */
emilmont 80:8e73be2a2ac1 317 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
emilmont 80:8e73be2a2ac1 318 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
emilmont 80:8e73be2a2ac1 319 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
emilmont 80:8e73be2a2ac1 320 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
emilmont 80:8e73be2a2ac1 321 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
emilmont 80:8e73be2a2ac1 322 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
emilmont 80:8e73be2a2ac1 323 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
emilmont 80:8e73be2a2ac1 324 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
emilmont 80:8e73be2a2ac1 325 __IO uint32_t CRCCNF; /*!< CRC configuration. */
emilmont 80:8e73be2a2ac1 326 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
emilmont 80:8e73be2a2ac1 327 __IO uint32_t CRCINIT; /*!< CRC initial value. */
emilmont 80:8e73be2a2ac1 328 __IO uint32_t TEST; /*!< Test features enable register. */
emilmont 80:8e73be2a2ac1 329 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
emilmont 80:8e73be2a2ac1 330 __IO uint32_t RSSISAMPLE; /*!< RSSI sample. */
emilmont 80:8e73be2a2ac1 331 __I uint32_t RESERVED7;
emilmont 80:8e73be2a2ac1 332 __I uint32_t STATE; /*!< Current radio state. */
emilmont 80:8e73be2a2ac1 333 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
emilmont 80:8e73be2a2ac1 334 __I uint32_t RESERVED8[2];
emilmont 80:8e73be2a2ac1 335 __IO uint32_t BCC; /*!< Bit counter compare. */
emilmont 80:8e73be2a2ac1 336 __I uint32_t RESERVED9[39];
emilmont 80:8e73be2a2ac1 337 __IO uint32_t DAB[8]; /*!< Device address base segment. */
emilmont 80:8e73be2a2ac1 338 __IO uint32_t DAP[8]; /*!< Device address prefix. */
emilmont 80:8e73be2a2ac1 339 __IO uint32_t DACNF; /*!< Device address match configuration. */
emilmont 80:8e73be2a2ac1 340 __I uint32_t RESERVED10[56];
emilmont 80:8e73be2a2ac1 341 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
emilmont 80:8e73be2a2ac1 342 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
emilmont 80:8e73be2a2ac1 343 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
emilmont 80:8e73be2a2ac1 344 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
emilmont 80:8e73be2a2ac1 345 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
emilmont 80:8e73be2a2ac1 346 __I uint32_t RESERVED11[561];
emilmont 80:8e73be2a2ac1 347 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 348 } NRF_RADIO_Type;
emilmont 80:8e73be2a2ac1 349
emilmont 80:8e73be2a2ac1 350
emilmont 80:8e73be2a2ac1 351 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 352 /* ================ UART ================ */
emilmont 80:8e73be2a2ac1 353 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 354
emilmont 80:8e73be2a2ac1 355
emilmont 80:8e73be2a2ac1 356 /**
emilmont 80:8e73be2a2ac1 357 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
emilmont 80:8e73be2a2ac1 358 */
emilmont 80:8e73be2a2ac1 359
emilmont 80:8e73be2a2ac1 360 typedef struct { /*!< UART Structure */
emilmont 80:8e73be2a2ac1 361 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
emilmont 80:8e73be2a2ac1 362 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
emilmont 80:8e73be2a2ac1 363 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
emilmont 80:8e73be2a2ac1 364 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
emilmont 80:8e73be2a2ac1 365 __I uint32_t RESERVED0[3];
emilmont 80:8e73be2a2ac1 366 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
emilmont 80:8e73be2a2ac1 367 __I uint32_t RESERVED1[56];
emilmont 80:8e73be2a2ac1 368 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
emilmont 80:8e73be2a2ac1 369 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
emilmont 80:8e73be2a2ac1 370 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
emilmont 80:8e73be2a2ac1 371 __I uint32_t RESERVED2[4];
emilmont 80:8e73be2a2ac1 372 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
emilmont 80:8e73be2a2ac1 373 __I uint32_t RESERVED3;
emilmont 80:8e73be2a2ac1 374 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
emilmont 80:8e73be2a2ac1 375 __I uint32_t RESERVED4[7];
emilmont 80:8e73be2a2ac1 376 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
emilmont 80:8e73be2a2ac1 377 __I uint32_t RESERVED5[46];
emilmont 80:8e73be2a2ac1 378 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
emilmont 80:8e73be2a2ac1 379 __I uint32_t RESERVED6[64];
emilmont 80:8e73be2a2ac1 380 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 381 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 382 __I uint32_t RESERVED7[93];
emilmont 80:8e73be2a2ac1 383 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
emilmont 80:8e73be2a2ac1 384 __I uint32_t RESERVED8[31];
emilmont 80:8e73be2a2ac1 385 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
emilmont 80:8e73be2a2ac1 386 __I uint32_t RESERVED9;
emilmont 80:8e73be2a2ac1 387 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
emilmont 80:8e73be2a2ac1 388 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
emilmont 80:8e73be2a2ac1 389 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
emilmont 80:8e73be2a2ac1 390 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
emilmont 80:8e73be2a2ac1 391 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
emilmont 80:8e73be2a2ac1 392 Once read the character is consummed. If read when no character
emilmont 80:8e73be2a2ac1 393 available, the UART will stop working. */
emilmont 80:8e73be2a2ac1 394 __O uint32_t TXD; /*!< TXD register. */
emilmont 80:8e73be2a2ac1 395 __I uint32_t RESERVED10;
emilmont 80:8e73be2a2ac1 396 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
emilmont 80:8e73be2a2ac1 397 __I uint32_t RESERVED11[17];
emilmont 80:8e73be2a2ac1 398 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
emilmont 80:8e73be2a2ac1 399 __I uint32_t RESERVED12[675];
emilmont 80:8e73be2a2ac1 400 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 401 } NRF_UART_Type;
emilmont 80:8e73be2a2ac1 402
emilmont 80:8e73be2a2ac1 403
emilmont 80:8e73be2a2ac1 404 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 405 /* ================ SPI ================ */
emilmont 80:8e73be2a2ac1 406 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 407
emilmont 80:8e73be2a2ac1 408
emilmont 80:8e73be2a2ac1 409 /**
emilmont 80:8e73be2a2ac1 410 * @brief SPI master 0. (SPI)
emilmont 80:8e73be2a2ac1 411 */
emilmont 80:8e73be2a2ac1 412
emilmont 80:8e73be2a2ac1 413 typedef struct { /*!< SPI Structure */
emilmont 80:8e73be2a2ac1 414 __I uint32_t RESERVED0[66];
emilmont 80:8e73be2a2ac1 415 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
emilmont 80:8e73be2a2ac1 416 __I uint32_t RESERVED1[126];
emilmont 80:8e73be2a2ac1 417 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 418 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 419 __I uint32_t RESERVED2[125];
emilmont 80:8e73be2a2ac1 420 __IO uint32_t ENABLE; /*!< Enable SPI. */
emilmont 80:8e73be2a2ac1 421 __I uint32_t RESERVED3;
emilmont 80:8e73be2a2ac1 422 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
emilmont 80:8e73be2a2ac1 423 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
emilmont 80:8e73be2a2ac1 424 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
emilmont 80:8e73be2a2ac1 425 __I uint32_t RESERVED4;
emilmont 80:8e73be2a2ac1 426 __IO uint32_t RXD; /*!< RX data. */
emilmont 80:8e73be2a2ac1 427 __IO uint32_t TXD; /*!< TX data. */
emilmont 80:8e73be2a2ac1 428 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 429 __IO uint32_t FREQUENCY; /*!< SPI frequency */
emilmont 80:8e73be2a2ac1 430 __I uint32_t RESERVED6[11];
emilmont 80:8e73be2a2ac1 431 __IO uint32_t CONFIG; /*!< Configuration register. */
emilmont 80:8e73be2a2ac1 432 __I uint32_t RESERVED7[681];
emilmont 80:8e73be2a2ac1 433 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 434 } NRF_SPI_Type;
emilmont 80:8e73be2a2ac1 435
emilmont 80:8e73be2a2ac1 436
emilmont 80:8e73be2a2ac1 437 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 438 /* ================ TWI ================ */
emilmont 80:8e73be2a2ac1 439 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 440
emilmont 80:8e73be2a2ac1 441
emilmont 80:8e73be2a2ac1 442 /**
emilmont 80:8e73be2a2ac1 443 * @brief Two-wire interface master 0. (TWI)
emilmont 80:8e73be2a2ac1 444 */
emilmont 80:8e73be2a2ac1 445
emilmont 80:8e73be2a2ac1 446 typedef struct { /*!< TWI Structure */
emilmont 80:8e73be2a2ac1 447 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
emilmont 80:8e73be2a2ac1 448 __I uint32_t RESERVED0;
emilmont 80:8e73be2a2ac1 449 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
emilmont 80:8e73be2a2ac1 450 __I uint32_t RESERVED1[2];
emilmont 80:8e73be2a2ac1 451 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
emilmont 80:8e73be2a2ac1 452 __I uint32_t RESERVED2;
emilmont 80:8e73be2a2ac1 453 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
emilmont 80:8e73be2a2ac1 454 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
emilmont 80:8e73be2a2ac1 455 __I uint32_t RESERVED3[56];
emilmont 80:8e73be2a2ac1 456 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
emilmont 80:8e73be2a2ac1 457 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
emilmont 80:8e73be2a2ac1 458 __I uint32_t RESERVED4[4];
emilmont 80:8e73be2a2ac1 459 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
emilmont 80:8e73be2a2ac1 460 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 461 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
emilmont 80:8e73be2a2ac1 462 __I uint32_t RESERVED6[4];
emilmont 80:8e73be2a2ac1 463 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
emilmont 80:8e73be2a2ac1 464 __I uint32_t RESERVED7[49];
emilmont 80:8e73be2a2ac1 465 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
emilmont 80:8e73be2a2ac1 466 __I uint32_t RESERVED8[64];
emilmont 80:8e73be2a2ac1 467 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 468 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 469 __I uint32_t RESERVED9[110];
emilmont 80:8e73be2a2ac1 470 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
emilmont 80:8e73be2a2ac1 471 __I uint32_t RESERVED10[14];
emilmont 80:8e73be2a2ac1 472 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
emilmont 80:8e73be2a2ac1 473 __I uint32_t RESERVED11;
emilmont 80:8e73be2a2ac1 474 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
emilmont 80:8e73be2a2ac1 475 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
emilmont 80:8e73be2a2ac1 476 __I uint32_t RESERVED12[2];
emilmont 80:8e73be2a2ac1 477 __IO uint32_t RXD; /*!< RX data register. */
emilmont 80:8e73be2a2ac1 478 __IO uint32_t TXD; /*!< TX data register. */
emilmont 80:8e73be2a2ac1 479 __I uint32_t RESERVED13;
emilmont 80:8e73be2a2ac1 480 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
emilmont 80:8e73be2a2ac1 481 __I uint32_t RESERVED14[24];
emilmont 80:8e73be2a2ac1 482 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
emilmont 80:8e73be2a2ac1 483 __I uint32_t RESERVED15[668];
emilmont 80:8e73be2a2ac1 484 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 485 } NRF_TWI_Type;
emilmont 80:8e73be2a2ac1 486
emilmont 80:8e73be2a2ac1 487
emilmont 80:8e73be2a2ac1 488 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 489 /* ================ SPIS ================ */
emilmont 80:8e73be2a2ac1 490 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 491
emilmont 80:8e73be2a2ac1 492
emilmont 80:8e73be2a2ac1 493 /**
emilmont 80:8e73be2a2ac1 494 * @brief SPI slave 1. (SPIS)
emilmont 80:8e73be2a2ac1 495 */
emilmont 80:8e73be2a2ac1 496
emilmont 80:8e73be2a2ac1 497 typedef struct { /*!< SPIS Structure */
emilmont 80:8e73be2a2ac1 498 __I uint32_t RESERVED0[9];
emilmont 80:8e73be2a2ac1 499 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
emilmont 80:8e73be2a2ac1 500 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
emilmont 80:8e73be2a2ac1 501 __I uint32_t RESERVED1[54];
emilmont 80:8e73be2a2ac1 502 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
emilmont 80:8e73be2a2ac1 503 __I uint32_t RESERVED2[8];
emilmont 80:8e73be2a2ac1 504 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
emilmont 80:8e73be2a2ac1 505 __I uint32_t RESERVED3[53];
emilmont 80:8e73be2a2ac1 506 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
emilmont 80:8e73be2a2ac1 507 __I uint32_t RESERVED4[64];
emilmont 80:8e73be2a2ac1 508 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 509 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 510 __I uint32_t RESERVED5[61];
emilmont 80:8e73be2a2ac1 511 __I uint32_t SEMSTAT; /*!< Semaphore status. */
emilmont 80:8e73be2a2ac1 512 __I uint32_t RESERVED6[15];
emilmont 80:8e73be2a2ac1 513 __IO uint32_t STATUS; /*!< Status from last transaction. */
emilmont 80:8e73be2a2ac1 514 __I uint32_t RESERVED7[47];
emilmont 80:8e73be2a2ac1 515 __IO uint32_t ENABLE; /*!< Enable SPIS. */
emilmont 80:8e73be2a2ac1 516 __I uint32_t RESERVED8;
emilmont 80:8e73be2a2ac1 517 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
emilmont 80:8e73be2a2ac1 518 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
emilmont 80:8e73be2a2ac1 519 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
emilmont 80:8e73be2a2ac1 520 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
emilmont 80:8e73be2a2ac1 521 __I uint32_t RESERVED9[7];
emilmont 80:8e73be2a2ac1 522 __IO uint32_t RXDPTR; /*!< RX data pointer. */
emilmont 80:8e73be2a2ac1 523 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
emilmont 80:8e73be2a2ac1 524 __IO uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
emilmont 80:8e73be2a2ac1 525 __I uint32_t RESERVED10;
emilmont 80:8e73be2a2ac1 526 __IO uint32_t TXDPTR; /*!< TX data pointer. */
emilmont 80:8e73be2a2ac1 527 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
emilmont 80:8e73be2a2ac1 528 __IO uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
emilmont 80:8e73be2a2ac1 529 __I uint32_t RESERVED11;
emilmont 80:8e73be2a2ac1 530 __IO uint32_t CONFIG; /*!< Configuration register. */
emilmont 80:8e73be2a2ac1 531 __I uint32_t RESERVED12;
emilmont 80:8e73be2a2ac1 532 __IO uint32_t DEF; /*!< Default character. */
emilmont 80:8e73be2a2ac1 533 __I uint32_t RESERVED13[24];
emilmont 80:8e73be2a2ac1 534 __IO uint32_t ORC; /*!< Over-read character. */
emilmont 80:8e73be2a2ac1 535 __I uint32_t RESERVED14[654];
emilmont 80:8e73be2a2ac1 536 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 537 } NRF_SPIS_Type;
emilmont 80:8e73be2a2ac1 538
emilmont 80:8e73be2a2ac1 539
emilmont 80:8e73be2a2ac1 540 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 541 /* ================ GPIOTE ================ */
emilmont 80:8e73be2a2ac1 542 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 543
emilmont 80:8e73be2a2ac1 544
emilmont 80:8e73be2a2ac1 545 /**
emilmont 80:8e73be2a2ac1 546 * @brief GPIO tasks and events. (GPIOTE)
emilmont 80:8e73be2a2ac1 547 */
emilmont 80:8e73be2a2ac1 548
emilmont 80:8e73be2a2ac1 549 typedef struct { /*!< GPIOTE Structure */
emilmont 80:8e73be2a2ac1 550 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
emilmont 80:8e73be2a2ac1 551 __I uint32_t RESERVED0[60];
emilmont 80:8e73be2a2ac1 552 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
emilmont 80:8e73be2a2ac1 553 __I uint32_t RESERVED1[27];
emilmont 80:8e73be2a2ac1 554 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
emilmont 80:8e73be2a2ac1 555 __I uint32_t RESERVED2[97];
emilmont 80:8e73be2a2ac1 556 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 557 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 558 __I uint32_t RESERVED3[129];
emilmont 80:8e73be2a2ac1 559 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
emilmont 80:8e73be2a2ac1 560 __I uint32_t RESERVED4[695];
emilmont 80:8e73be2a2ac1 561 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 562 } NRF_GPIOTE_Type;
emilmont 80:8e73be2a2ac1 563
emilmont 80:8e73be2a2ac1 564
emilmont 80:8e73be2a2ac1 565 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 566 /* ================ ADC ================ */
emilmont 80:8e73be2a2ac1 567 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 568
emilmont 80:8e73be2a2ac1 569
emilmont 80:8e73be2a2ac1 570 /**
emilmont 80:8e73be2a2ac1 571 * @brief Analog to digital converter. (ADC)
emilmont 80:8e73be2a2ac1 572 */
emilmont 80:8e73be2a2ac1 573
emilmont 80:8e73be2a2ac1 574 typedef struct { /*!< ADC Structure */
emilmont 80:8e73be2a2ac1 575 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
emilmont 80:8e73be2a2ac1 576 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
emilmont 80:8e73be2a2ac1 577 __I uint32_t RESERVED0[62];
emilmont 80:8e73be2a2ac1 578 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
emilmont 80:8e73be2a2ac1 579 __I uint32_t RESERVED1[128];
emilmont 80:8e73be2a2ac1 580 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 581 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 582 __I uint32_t RESERVED2[61];
emilmont 80:8e73be2a2ac1 583 __I uint32_t BUSY; /*!< ADC busy register. */
emilmont 80:8e73be2a2ac1 584 __I uint32_t RESERVED3[63];
emilmont 80:8e73be2a2ac1 585 __IO uint32_t ENABLE; /*!< ADC enable. */
emilmont 80:8e73be2a2ac1 586 __IO uint32_t CONFIG; /*!< ADC configuration register. */
emilmont 80:8e73be2a2ac1 587 __I uint32_t RESULT; /*!< Result of ADC conversion. */
emilmont 80:8e73be2a2ac1 588 __I uint32_t RESERVED4[700];
emilmont 80:8e73be2a2ac1 589 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 590 } NRF_ADC_Type;
emilmont 80:8e73be2a2ac1 591
emilmont 80:8e73be2a2ac1 592
emilmont 80:8e73be2a2ac1 593 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 594 /* ================ TIMER ================ */
emilmont 80:8e73be2a2ac1 595 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 596
emilmont 80:8e73be2a2ac1 597
emilmont 80:8e73be2a2ac1 598 /**
emilmont 80:8e73be2a2ac1 599 * @brief Timer 0. (TIMER)
emilmont 80:8e73be2a2ac1 600 */
emilmont 80:8e73be2a2ac1 601
emilmont 80:8e73be2a2ac1 602 typedef struct { /*!< TIMER Structure */
emilmont 80:8e73be2a2ac1 603 __O uint32_t TASKS_START; /*!< Start Timer. */
emilmont 80:8e73be2a2ac1 604 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
emilmont 80:8e73be2a2ac1 605 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
emilmont 80:8e73be2a2ac1 606 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
emilmont 80:8e73be2a2ac1 607 __I uint32_t RESERVED0[12];
emilmont 80:8e73be2a2ac1 608 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
emilmont 80:8e73be2a2ac1 609 __I uint32_t RESERVED1[60];
emilmont 80:8e73be2a2ac1 610 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
emilmont 80:8e73be2a2ac1 611 __I uint32_t RESERVED2[44];
emilmont 80:8e73be2a2ac1 612 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
emilmont 80:8e73be2a2ac1 613 __I uint32_t RESERVED3[64];
emilmont 80:8e73be2a2ac1 614 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 615 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 616 __I uint32_t RESERVED4[126];
emilmont 80:8e73be2a2ac1 617 __IO uint32_t MODE; /*!< Timer Mode selection. */
emilmont 80:8e73be2a2ac1 618 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
emilmont 80:8e73be2a2ac1 619 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 620 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
emilmont 80:8e73be2a2ac1 621 clock frequency is divided by 2^SCALE. */
emilmont 80:8e73be2a2ac1 622 __I uint32_t RESERVED6[11];
emilmont 80:8e73be2a2ac1 623 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
emilmont 80:8e73be2a2ac1 624 __I uint32_t RESERVED7[683];
emilmont 80:8e73be2a2ac1 625 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 626 } NRF_TIMER_Type;
emilmont 80:8e73be2a2ac1 627
emilmont 80:8e73be2a2ac1 628
emilmont 80:8e73be2a2ac1 629 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 630 /* ================ RTC ================ */
emilmont 80:8e73be2a2ac1 631 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 632
emilmont 80:8e73be2a2ac1 633
emilmont 80:8e73be2a2ac1 634 /**
emilmont 80:8e73be2a2ac1 635 * @brief Real time counter 0. (RTC)
emilmont 80:8e73be2a2ac1 636 */
emilmont 80:8e73be2a2ac1 637
emilmont 80:8e73be2a2ac1 638 typedef struct { /*!< RTC Structure */
emilmont 80:8e73be2a2ac1 639 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
emilmont 80:8e73be2a2ac1 640 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
emilmont 80:8e73be2a2ac1 641 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
emilmont 80:8e73be2a2ac1 642 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
emilmont 80:8e73be2a2ac1 643 __I uint32_t RESERVED0[60];
emilmont 80:8e73be2a2ac1 644 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
emilmont 80:8e73be2a2ac1 645 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
emilmont 80:8e73be2a2ac1 646 __I uint32_t RESERVED1[14];
emilmont 80:8e73be2a2ac1 647 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
emilmont 80:8e73be2a2ac1 648 __I uint32_t RESERVED2[109];
emilmont 80:8e73be2a2ac1 649 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 650 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 651 __I uint32_t RESERVED3[13];
emilmont 80:8e73be2a2ac1 652 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
emilmont 80:8e73be2a2ac1 653 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
emilmont 80:8e73be2a2ac1 654 the value of EVTEN. */
emilmont 80:8e73be2a2ac1 655 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
emilmont 80:8e73be2a2ac1 656 gives the value of EVTEN. */
emilmont 80:8e73be2a2ac1 657 __I uint32_t RESERVED4[110];
emilmont 80:8e73be2a2ac1 658 __IO uint32_t COUNTER; /*!< Current COUNTER value. */
emilmont 80:8e73be2a2ac1 659 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
emilmont 80:8e73be2a2ac1 660 Must be written when RTC is STOPed. */
emilmont 80:8e73be2a2ac1 661 __I uint32_t RESERVED5[13];
emilmont 80:8e73be2a2ac1 662 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
emilmont 80:8e73be2a2ac1 663 __I uint32_t RESERVED6[683];
emilmont 80:8e73be2a2ac1 664 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 665 } NRF_RTC_Type;
emilmont 80:8e73be2a2ac1 666
emilmont 80:8e73be2a2ac1 667
emilmont 80:8e73be2a2ac1 668 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 669 /* ================ TEMP ================ */
emilmont 80:8e73be2a2ac1 670 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 671
emilmont 80:8e73be2a2ac1 672
emilmont 80:8e73be2a2ac1 673 /**
emilmont 80:8e73be2a2ac1 674 * @brief Temperature Sensor. (TEMP)
emilmont 80:8e73be2a2ac1 675 */
emilmont 80:8e73be2a2ac1 676
emilmont 80:8e73be2a2ac1 677 typedef struct { /*!< TEMP Structure */
emilmont 80:8e73be2a2ac1 678 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
emilmont 80:8e73be2a2ac1 679 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
emilmont 80:8e73be2a2ac1 680 __I uint32_t RESERVED0[62];
emilmont 80:8e73be2a2ac1 681 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
emilmont 80:8e73be2a2ac1 682 __I uint32_t RESERVED1[128];
emilmont 80:8e73be2a2ac1 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 685 __I uint32_t RESERVED2[127];
emilmont 80:8e73be2a2ac1 686 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
emilmont 80:8e73be2a2ac1 687 __I uint32_t RESERVED3[700];
emilmont 80:8e73be2a2ac1 688 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 689 } NRF_TEMP_Type;
emilmont 80:8e73be2a2ac1 690
emilmont 80:8e73be2a2ac1 691
emilmont 80:8e73be2a2ac1 692 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 693 /* ================ RNG ================ */
emilmont 80:8e73be2a2ac1 694 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 695
emilmont 80:8e73be2a2ac1 696
emilmont 80:8e73be2a2ac1 697 /**
emilmont 80:8e73be2a2ac1 698 * @brief Random Number Generator. (RNG)
emilmont 80:8e73be2a2ac1 699 */
emilmont 80:8e73be2a2ac1 700
emilmont 80:8e73be2a2ac1 701 typedef struct { /*!< RNG Structure */
emilmont 80:8e73be2a2ac1 702 __O uint32_t TASKS_START; /*!< Start the random number generator. */
emilmont 80:8e73be2a2ac1 703 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
emilmont 80:8e73be2a2ac1 704 __I uint32_t RESERVED0[62];
emilmont 80:8e73be2a2ac1 705 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
emilmont 80:8e73be2a2ac1 706 __I uint32_t RESERVED1[63];
emilmont 80:8e73be2a2ac1 707 __IO uint32_t SHORTS; /*!< Shortcut for the RNG. */
emilmont 80:8e73be2a2ac1 708 __I uint32_t RESERVED2[64];
emilmont 80:8e73be2a2ac1 709 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
emilmont 80:8e73be2a2ac1 710 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
emilmont 80:8e73be2a2ac1 711 __I uint32_t RESERVED3[126];
emilmont 80:8e73be2a2ac1 712 __IO uint32_t CONFIG; /*!< Configuration register. */
emilmont 80:8e73be2a2ac1 713 __I uint32_t VALUE; /*!< RNG random number. */
emilmont 80:8e73be2a2ac1 714 __I uint32_t RESERVED4[700];
emilmont 80:8e73be2a2ac1 715 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 716 } NRF_RNG_Type;
emilmont 80:8e73be2a2ac1 717
emilmont 80:8e73be2a2ac1 718
emilmont 80:8e73be2a2ac1 719 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 720 /* ================ ECB ================ */
emilmont 80:8e73be2a2ac1 721 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 722
emilmont 80:8e73be2a2ac1 723
emilmont 80:8e73be2a2ac1 724 /**
emilmont 80:8e73be2a2ac1 725 * @brief AES ECB Mode Encryption. (ECB)
emilmont 80:8e73be2a2ac1 726 */
emilmont 80:8e73be2a2ac1 727
emilmont 80:8e73be2a2ac1 728 typedef struct { /*!< ECB Structure */
emilmont 80:8e73be2a2ac1 729 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
emilmont 80:8e73be2a2ac1 730 will not initiate a new encryption and the ERRORECB event will
emilmont 80:8e73be2a2ac1 731 be triggered. */
emilmont 80:8e73be2a2ac1 732 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
emilmont 80:8e73be2a2ac1 733 this will will trigger the ERRORECB event. */
emilmont 80:8e73be2a2ac1 734 __I uint32_t RESERVED0[62];
emilmont 80:8e73be2a2ac1 735 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
emilmont 80:8e73be2a2ac1 736 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
emilmont 80:8e73be2a2ac1 737 error. */
emilmont 80:8e73be2a2ac1 738 __I uint32_t RESERVED1[127];
emilmont 80:8e73be2a2ac1 739 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 740 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 741 __I uint32_t RESERVED2[126];
emilmont 80:8e73be2a2ac1 742 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
emilmont 80:8e73be2a2ac1 743 __I uint32_t RESERVED3[701];
emilmont 80:8e73be2a2ac1 744 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 745 } NRF_ECB_Type;
emilmont 80:8e73be2a2ac1 746
emilmont 80:8e73be2a2ac1 747
emilmont 80:8e73be2a2ac1 748 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 749 /* ================ AAR ================ */
emilmont 80:8e73be2a2ac1 750 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 751
emilmont 80:8e73be2a2ac1 752
emilmont 80:8e73be2a2ac1 753 /**
emilmont 80:8e73be2a2ac1 754 * @brief Accelerated Address Resolver. (AAR)
emilmont 80:8e73be2a2ac1 755 */
emilmont 80:8e73be2a2ac1 756
emilmont 80:8e73be2a2ac1 757 typedef struct { /*!< AAR Structure */
emilmont 80:8e73be2a2ac1 758 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
emilmont 80:8e73be2a2ac1 759 data structure. */
emilmont 80:8e73be2a2ac1 760 __I uint32_t RESERVED0;
emilmont 80:8e73be2a2ac1 761 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
emilmont 80:8e73be2a2ac1 762 __I uint32_t RESERVED1[61];
emilmont 80:8e73be2a2ac1 763 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
emilmont 80:8e73be2a2ac1 764 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
emilmont 80:8e73be2a2ac1 765 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
emilmont 80:8e73be2a2ac1 766 __I uint32_t RESERVED2[126];
emilmont 80:8e73be2a2ac1 767 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 768 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 769 __I uint32_t RESERVED3[61];
emilmont 80:8e73be2a2ac1 770 __I uint32_t STATUS; /*!< Resolution status. */
emilmont 80:8e73be2a2ac1 771 __I uint32_t RESERVED4[63];
emilmont 80:8e73be2a2ac1 772 __IO uint32_t ENABLE; /*!< Enable AAR. */
emilmont 80:8e73be2a2ac1 773 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
emilmont 80:8e73be2a2ac1 774 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
emilmont 80:8e73be2a2ac1 775 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 776 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
emilmont 80:8e73be2a2ac1 777 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
emilmont 80:8e73be2a2ac1 778 resolution. A minimum of 3 bytes must be reserved. */
emilmont 80:8e73be2a2ac1 779 __I uint32_t RESERVED6[697];
emilmont 80:8e73be2a2ac1 780 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 781 } NRF_AAR_Type;
emilmont 80:8e73be2a2ac1 782
emilmont 80:8e73be2a2ac1 783
emilmont 80:8e73be2a2ac1 784 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 785 /* ================ CCM ================ */
emilmont 80:8e73be2a2ac1 786 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 787
emilmont 80:8e73be2a2ac1 788
emilmont 80:8e73be2a2ac1 789 /**
emilmont 80:8e73be2a2ac1 790 * @brief AES CCM Mode Encryption. (CCM)
emilmont 80:8e73be2a2ac1 791 */
emilmont 80:8e73be2a2ac1 792
emilmont 80:8e73be2a2ac1 793 typedef struct { /*!< CCM Structure */
emilmont 80:8e73be2a2ac1 794 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
emilmont 80:8e73be2a2ac1 795 itself when completed. */
emilmont 80:8e73be2a2ac1 796 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
emilmont 80:8e73be2a2ac1 797 completed. */
emilmont 80:8e73be2a2ac1 798 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
emilmont 80:8e73be2a2ac1 799 __I uint32_t RESERVED0[61];
emilmont 80:8e73be2a2ac1 800 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
emilmont 80:8e73be2a2ac1 801 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
emilmont 80:8e73be2a2ac1 802 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
emilmont 80:8e73be2a2ac1 803 __I uint32_t RESERVED1[61];
emilmont 80:8e73be2a2ac1 804 __IO uint32_t SHORTS; /*!< Shortcut for the CCM. */
emilmont 80:8e73be2a2ac1 805 __I uint32_t RESERVED2[64];
emilmont 80:8e73be2a2ac1 806 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 807 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 808 __I uint32_t RESERVED3[61];
emilmont 80:8e73be2a2ac1 809 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
emilmont 80:8e73be2a2ac1 810 __I uint32_t RESERVED4[63];
emilmont 80:8e73be2a2ac1 811 __IO uint32_t ENABLE; /*!< CCM enable. */
emilmont 80:8e73be2a2ac1 812 __IO uint32_t MODE; /*!< Operation mode. */
emilmont 80:8e73be2a2ac1 813 __IO uint32_t CNFPTR; /*!< Pointer to data structure holding AES key and NONCE vector. */
emilmont 80:8e73be2a2ac1 814 __IO uint32_t INPTR; /*!< Pointer to input packet. */
emilmont 80:8e73be2a2ac1 815 __IO uint32_t OUTPTR; /*!< Pointer to output packet. */
emilmont 80:8e73be2a2ac1 816 __IO uint32_t SCRATCHPTR; /*!< Pointer to "scratch" data area used for temporary storage during
emilmont 80:8e73be2a2ac1 817 resolution. A minimum of 43 bytes must be reserved. */
emilmont 80:8e73be2a2ac1 818 __I uint32_t RESERVED5[697];
emilmont 80:8e73be2a2ac1 819 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 820 } NRF_CCM_Type;
emilmont 80:8e73be2a2ac1 821
emilmont 80:8e73be2a2ac1 822
emilmont 80:8e73be2a2ac1 823 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 824 /* ================ WDT ================ */
emilmont 80:8e73be2a2ac1 825 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 826
emilmont 80:8e73be2a2ac1 827
emilmont 80:8e73be2a2ac1 828 /**
emilmont 80:8e73be2a2ac1 829 * @brief Watchdog Timer. (WDT)
emilmont 80:8e73be2a2ac1 830 */
emilmont 80:8e73be2a2ac1 831
emilmont 80:8e73be2a2ac1 832 typedef struct { /*!< WDT Structure */
emilmont 80:8e73be2a2ac1 833 __O uint32_t TASKS_START; /*!< Start the watchdog. */
emilmont 80:8e73be2a2ac1 834 __I uint32_t RESERVED0[63];
emilmont 80:8e73be2a2ac1 835 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
emilmont 80:8e73be2a2ac1 836 __I uint32_t RESERVED1[128];
emilmont 80:8e73be2a2ac1 837 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 838 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 839 __I uint32_t RESERVED2[61];
emilmont 80:8e73be2a2ac1 840 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
emilmont 80:8e73be2a2ac1 841 __I uint32_t REQSTATUS; /*!< Request status. */
emilmont 80:8e73be2a2ac1 842 __I uint32_t RESERVED3[63];
emilmont 80:8e73be2a2ac1 843 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
emilmont 80:8e73be2a2ac1 844 __IO uint32_t RREN; /*!< Reload request enable. */
emilmont 80:8e73be2a2ac1 845 __IO uint32_t CONFIG; /*!< Configuration register. */
emilmont 80:8e73be2a2ac1 846 __I uint32_t RESERVED4[60];
emilmont 80:8e73be2a2ac1 847 __O uint32_t RR[8]; /*!< Reload requests registers. */
emilmont 80:8e73be2a2ac1 848 __I uint32_t RESERVED5[631];
emilmont 80:8e73be2a2ac1 849 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 850 } NRF_WDT_Type;
emilmont 80:8e73be2a2ac1 851
emilmont 80:8e73be2a2ac1 852
emilmont 80:8e73be2a2ac1 853 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 854 /* ================ QDEC ================ */
emilmont 80:8e73be2a2ac1 855 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 856
emilmont 80:8e73be2a2ac1 857
emilmont 80:8e73be2a2ac1 858 /**
emilmont 80:8e73be2a2ac1 859 * @brief Rotary decoder. (QDEC)
emilmont 80:8e73be2a2ac1 860 */
emilmont 80:8e73be2a2ac1 861
emilmont 80:8e73be2a2ac1 862 typedef struct { /*!< QDEC Structure */
emilmont 80:8e73be2a2ac1 863 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
emilmont 80:8e73be2a2ac1 864 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
emilmont 80:8e73be2a2ac1 865 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
emilmont 80:8e73be2a2ac1 866 and clears the ACC registers. */
emilmont 80:8e73be2a2ac1 867 __I uint32_t RESERVED0[61];
emilmont 80:8e73be2a2ac1 868 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
emilmont 80:8e73be2a2ac1 869 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
emilmont 80:8e73be2a2ac1 870 ACC register different than zero. */
emilmont 80:8e73be2a2ac1 871 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
emilmont 80:8e73be2a2ac1 872 __I uint32_t RESERVED1[61];
emilmont 80:8e73be2a2ac1 873 __IO uint32_t SHORTS; /*!< Shortcut for the QDEC. */
emilmont 80:8e73be2a2ac1 874 __I uint32_t RESERVED2[64];
emilmont 80:8e73be2a2ac1 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 877 __I uint32_t RESERVED3[125];
emilmont 80:8e73be2a2ac1 878 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
emilmont 80:8e73be2a2ac1 879 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
emilmont 80:8e73be2a2ac1 880 __IO uint32_t SAMPLEPER; /*!< Sample period. */
emilmont 80:8e73be2a2ac1 881 __I int32_t SAMPLE; /*!< Motion sample value. */
emilmont 80:8e73be2a2ac1 882 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
emilmont 80:8e73be2a2ac1 883 __I int32_t ACC; /*!< Accumulated valid transitions register. */
emilmont 80:8e73be2a2ac1 884 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
emilmont 80:8e73be2a2ac1 885 task. */
emilmont 80:8e73be2a2ac1 886 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
emilmont 80:8e73be2a2ac1 887 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
emilmont 80:8e73be2a2ac1 888 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
emilmont 80:8e73be2a2ac1 889 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
emilmont 80:8e73be2a2ac1 890 __I uint32_t RESERVED4[5];
emilmont 80:8e73be2a2ac1 891 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
emilmont 80:8e73be2a2ac1 892 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
emilmont 80:8e73be2a2ac1 893 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
emilmont 80:8e73be2a2ac1 894 task. */
emilmont 80:8e73be2a2ac1 895 __I uint32_t RESERVED5[684];
emilmont 80:8e73be2a2ac1 896 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 897 } NRF_QDEC_Type;
emilmont 80:8e73be2a2ac1 898
emilmont 80:8e73be2a2ac1 899
emilmont 80:8e73be2a2ac1 900 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 901 /* ================ LPCOMP ================ */
emilmont 80:8e73be2a2ac1 902 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 903
emilmont 80:8e73be2a2ac1 904
emilmont 80:8e73be2a2ac1 905 /**
emilmont 80:8e73be2a2ac1 906 * @brief Wakeup Comparator. (LPCOMP)
emilmont 80:8e73be2a2ac1 907 */
emilmont 80:8e73be2a2ac1 908
emilmont 80:8e73be2a2ac1 909 typedef struct { /*!< LPCOMP Structure */
emilmont 80:8e73be2a2ac1 910 __O uint32_t TASKS_START; /*!< Start the comparator. */
emilmont 80:8e73be2a2ac1 911 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
emilmont 80:8e73be2a2ac1 912 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
emilmont 80:8e73be2a2ac1 913 __I uint32_t RESERVED0[61];
emilmont 80:8e73be2a2ac1 914 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
emilmont 80:8e73be2a2ac1 915 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
emilmont 80:8e73be2a2ac1 916 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
emilmont 80:8e73be2a2ac1 917 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
emilmont 80:8e73be2a2ac1 918 __I uint32_t RESERVED1[60];
emilmont 80:8e73be2a2ac1 919 __IO uint32_t SHORTS; /*!< Shortcut for the LPCOMP. */
emilmont 80:8e73be2a2ac1 920 __I uint32_t RESERVED2[64];
emilmont 80:8e73be2a2ac1 921 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 922 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 923 __I uint32_t RESERVED3[61];
emilmont 80:8e73be2a2ac1 924 __I uint32_t RESULT; /*!< Result of last compare. */
emilmont 80:8e73be2a2ac1 925 __I uint32_t RESERVED4[63];
emilmont 80:8e73be2a2ac1 926 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
emilmont 80:8e73be2a2ac1 927 __IO uint32_t PSEL; /*!< Input pin select. */
emilmont 80:8e73be2a2ac1 928 __IO uint32_t REFSEL; /*!< Reference select. */
emilmont 80:8e73be2a2ac1 929 __IO uint32_t EXTREFSEL; /*!< External reference select. */
emilmont 80:8e73be2a2ac1 930 __I uint32_t RESERVED5[4];
emilmont 80:8e73be2a2ac1 931 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
emilmont 80:8e73be2a2ac1 932 __I uint32_t RESERVED6[694];
emilmont 80:8e73be2a2ac1 933 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 934 } NRF_LPCOMP_Type;
emilmont 80:8e73be2a2ac1 935
emilmont 80:8e73be2a2ac1 936
emilmont 80:8e73be2a2ac1 937 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 938 /* ================ COMP ================ */
emilmont 80:8e73be2a2ac1 939 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 940
emilmont 80:8e73be2a2ac1 941
emilmont 80:8e73be2a2ac1 942 /**
emilmont 80:8e73be2a2ac1 943 * @brief Comparator. (COMP)
emilmont 80:8e73be2a2ac1 944 */
emilmont 80:8e73be2a2ac1 945
emilmont 80:8e73be2a2ac1 946 typedef struct { /*!< COMP Structure */
emilmont 80:8e73be2a2ac1 947 __O uint32_t TASKS_START; /*!< Start the comparator. */
emilmont 80:8e73be2a2ac1 948 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
emilmont 80:8e73be2a2ac1 949 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
emilmont 80:8e73be2a2ac1 950 __I uint32_t RESERVED0[61];
emilmont 80:8e73be2a2ac1 951 __IO uint32_t EVENTS_READY; /*!< COMP is ready and output is valid. */
emilmont 80:8e73be2a2ac1 952 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
emilmont 80:8e73be2a2ac1 953 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
emilmont 80:8e73be2a2ac1 954 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
emilmont 80:8e73be2a2ac1 955 __I uint32_t RESERVED1[60];
emilmont 80:8e73be2a2ac1 956 __IO uint32_t SHORTS; /*!< Shortcut for the COMP. */
emilmont 80:8e73be2a2ac1 957 __I uint32_t RESERVED2[64];
emilmont 80:8e73be2a2ac1 958 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 959 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 960 __I uint32_t RESERVED3[61];
emilmont 80:8e73be2a2ac1 961 __I uint32_t RESULT; /*!< Compare result. */
emilmont 80:8e73be2a2ac1 962 __I uint32_t RESERVED4[63];
emilmont 80:8e73be2a2ac1 963 __IO uint32_t ENABLE; /*!< Enable the COMP. */
emilmont 80:8e73be2a2ac1 964 __IO uint32_t PSEL; /*!< Input pin select. */
emilmont 80:8e73be2a2ac1 965 __IO uint32_t REFSEL; /*!< Reference select. */
emilmont 80:8e73be2a2ac1 966 __IO uint32_t EXTREFSEL; /*!< External reference select. */
emilmont 80:8e73be2a2ac1 967 __I uint32_t RESERVED5[8];
emilmont 80:8e73be2a2ac1 968 __IO uint32_t TH; /*!< Threshold configuration for hysteresis unit. */
emilmont 80:8e73be2a2ac1 969 __IO uint32_t MODE; /*!< Mode configuration. */
emilmont 80:8e73be2a2ac1 970 __I uint32_t RESERVED6[689];
emilmont 80:8e73be2a2ac1 971 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 972 } NRF_COMP_Type;
emilmont 80:8e73be2a2ac1 973
emilmont 80:8e73be2a2ac1 974
emilmont 80:8e73be2a2ac1 975 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 976 /* ================ SWI ================ */
emilmont 80:8e73be2a2ac1 977 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 978
emilmont 80:8e73be2a2ac1 979
emilmont 80:8e73be2a2ac1 980 /**
emilmont 80:8e73be2a2ac1 981 * @brief SW Interrupts. (SWI)
emilmont 80:8e73be2a2ac1 982 */
emilmont 80:8e73be2a2ac1 983
emilmont 80:8e73be2a2ac1 984 typedef struct { /*!< SWI Structure */
emilmont 80:8e73be2a2ac1 985 __I uint32_t UNUSED; /*!< Unused. */
emilmont 80:8e73be2a2ac1 986 } NRF_SWI_Type;
emilmont 80:8e73be2a2ac1 987
emilmont 80:8e73be2a2ac1 988
emilmont 80:8e73be2a2ac1 989 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 990 /* ================ NVMC ================ */
emilmont 80:8e73be2a2ac1 991 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 992
emilmont 80:8e73be2a2ac1 993
emilmont 80:8e73be2a2ac1 994 /**
emilmont 80:8e73be2a2ac1 995 * @brief Non Volatile Memory Controller. (NVMC)
emilmont 80:8e73be2a2ac1 996 */
emilmont 80:8e73be2a2ac1 997
emilmont 80:8e73be2a2ac1 998 typedef struct { /*!< NVMC Structure */
emilmont 80:8e73be2a2ac1 999 __I uint32_t RESERVED0[256];
emilmont 80:8e73be2a2ac1 1000 __I uint32_t READY; /*!< Ready flag. */
emilmont 80:8e73be2a2ac1 1001 __I uint32_t RESERVED1[64];
emilmont 80:8e73be2a2ac1 1002 __IO uint32_t CONFIG; /*!< Configuration register. */
emilmont 80:8e73be2a2ac1 1003 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
emilmont 80:8e73be2a2ac1 1004 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
emilmont 80:8e73be2a2ac1 1005 __IO uint32_t ERASEPROTECTEDPAGE; /*!< Register for erasing a protected non-volatile memory page. */
emilmont 80:8e73be2a2ac1 1006 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
emilmont 80:8e73be2a2ac1 1007 } NRF_NVMC_Type;
emilmont 80:8e73be2a2ac1 1008
emilmont 80:8e73be2a2ac1 1009
emilmont 80:8e73be2a2ac1 1010 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1011 /* ================ PPI ================ */
emilmont 80:8e73be2a2ac1 1012 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1013
emilmont 80:8e73be2a2ac1 1014
emilmont 80:8e73be2a2ac1 1015 /**
emilmont 80:8e73be2a2ac1 1016 * @brief PPI controller. (PPI)
emilmont 80:8e73be2a2ac1 1017 */
emilmont 80:8e73be2a2ac1 1018
emilmont 80:8e73be2a2ac1 1019 typedef struct { /*!< PPI Structure */
emilmont 80:8e73be2a2ac1 1020 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
emilmont 80:8e73be2a2ac1 1021 __I uint32_t RESERVED0[312];
emilmont 80:8e73be2a2ac1 1022 __IO uint32_t CHEN; /*!< Channel enable. */
emilmont 80:8e73be2a2ac1 1023 __IO uint32_t CHENSET; /*!< Channel enable set. */
emilmont 80:8e73be2a2ac1 1024 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
emilmont 80:8e73be2a2ac1 1025 __I uint32_t RESERVED1;
emilmont 80:8e73be2a2ac1 1026 PPI_CH_Type CH[16]; /*!< PPI Channel. */
emilmont 80:8e73be2a2ac1 1027 __I uint32_t RESERVED2[156];
emilmont 80:8e73be2a2ac1 1028 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
emilmont 80:8e73be2a2ac1 1029 } NRF_PPI_Type;
emilmont 80:8e73be2a2ac1 1030
emilmont 80:8e73be2a2ac1 1031
emilmont 80:8e73be2a2ac1 1032 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1033 /* ================ FICR ================ */
emilmont 80:8e73be2a2ac1 1034 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1035
emilmont 80:8e73be2a2ac1 1036
emilmont 80:8e73be2a2ac1 1037 /**
emilmont 80:8e73be2a2ac1 1038 * @brief Factory Information Configuration. (FICR)
emilmont 80:8e73be2a2ac1 1039 */
emilmont 80:8e73be2a2ac1 1040
emilmont 80:8e73be2a2ac1 1041 typedef struct { /*!< FICR Structure */
emilmont 80:8e73be2a2ac1 1042 __I uint32_t RESERVED0[4];
emilmont 80:8e73be2a2ac1 1043 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
emilmont 80:8e73be2a2ac1 1044 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
emilmont 80:8e73be2a2ac1 1045 __I uint32_t RESERVED1[4];
emilmont 80:8e73be2a2ac1 1046 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
emilmont 80:8e73be2a2ac1 1047 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
emilmont 80:8e73be2a2ac1 1048 __I uint32_t RESERVED2;
emilmont 80:8e73be2a2ac1 1049 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
emilmont 80:8e73be2a2ac1 1050 __I uint32_t SIZERAMBLOCK[4]; /*!< Size of RAM block in bytes. */
emilmont 80:8e73be2a2ac1 1051 __I uint32_t RESERVED3[5];
emilmont 80:8e73be2a2ac1 1052 __I uint32_t CONFIGID; /*!< Configuration identifier. */
emilmont 80:8e73be2a2ac1 1053 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
emilmont 80:8e73be2a2ac1 1054 __I uint32_t RESERVED4[6];
emilmont 80:8e73be2a2ac1 1055 __I uint32_t ER[4]; /*!< Encryption root. */
emilmont 80:8e73be2a2ac1 1056 __I uint32_t IR[4]; /*!< Identity root. */
emilmont 80:8e73be2a2ac1 1057 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
emilmont 80:8e73be2a2ac1 1058 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
emilmont 80:8e73be2a2ac1 1059 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
emilmont 80:8e73be2a2ac1 1060 __I uint32_t RESERVED5[15];
emilmont 80:8e73be2a2ac1 1061 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
emilmont 80:8e73be2a2ac1 1062 mode. */
emilmont 80:8e73be2a2ac1 1063 } NRF_FICR_Type;
emilmont 80:8e73be2a2ac1 1064
emilmont 80:8e73be2a2ac1 1065
emilmont 80:8e73be2a2ac1 1066 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1067 /* ================ UICR ================ */
emilmont 80:8e73be2a2ac1 1068 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1069
emilmont 80:8e73be2a2ac1 1070
emilmont 80:8e73be2a2ac1 1071 /**
emilmont 80:8e73be2a2ac1 1072 * @brief User Information Configuration. (UICR)
emilmont 80:8e73be2a2ac1 1073 */
emilmont 80:8e73be2a2ac1 1074
emilmont 80:8e73be2a2ac1 1075 typedef struct { /*!< UICR Structure */
emilmont 80:8e73be2a2ac1 1076 __IO uint32_t CLENR0; /*!< Length of code region 0. */
emilmont 80:8e73be2a2ac1 1077 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
emilmont 80:8e73be2a2ac1 1078 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
emilmont 80:8e73be2a2ac1 1079 __I uint32_t RESERVED0;
emilmont 80:8e73be2a2ac1 1080 __I uint32_t FWID; /*!< Firmware ID. */
emilmont 80:8e73be2a2ac1 1081 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
emilmont 80:8e73be2a2ac1 1082 } NRF_UICR_Type;
emilmont 80:8e73be2a2ac1 1083
emilmont 80:8e73be2a2ac1 1084
emilmont 80:8e73be2a2ac1 1085 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1086 /* ================ GPIO ================ */
emilmont 80:8e73be2a2ac1 1087 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1088
emilmont 80:8e73be2a2ac1 1089
emilmont 80:8e73be2a2ac1 1090 /**
emilmont 80:8e73be2a2ac1 1091 * @brief General purpose input and output. (GPIO)
emilmont 80:8e73be2a2ac1 1092 */
emilmont 80:8e73be2a2ac1 1093
emilmont 80:8e73be2a2ac1 1094 typedef struct { /*!< GPIO Structure */
emilmont 80:8e73be2a2ac1 1095 __I uint32_t RESERVED0[321];
emilmont 80:8e73be2a2ac1 1096 __IO uint32_t OUT; /*!< Write GPIO port. */
emilmont 80:8e73be2a2ac1 1097 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
emilmont 80:8e73be2a2ac1 1098 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
emilmont 80:8e73be2a2ac1 1099 __I uint32_t IN; /*!< Read GPIO port. */
emilmont 80:8e73be2a2ac1 1100 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
emilmont 80:8e73be2a2ac1 1101 __IO uint32_t DIRSET; /*!< DIR set register. */
emilmont 80:8e73be2a2ac1 1102 __IO uint32_t DIRCLR; /*!< DIR clear register. */
emilmont 80:8e73be2a2ac1 1103 __I uint32_t RESERVED1[120];
emilmont 80:8e73be2a2ac1 1104 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
emilmont 80:8e73be2a2ac1 1105 } NRF_GPIO_Type;
emilmont 80:8e73be2a2ac1 1106
emilmont 80:8e73be2a2ac1 1107
emilmont 80:8e73be2a2ac1 1108 /* -------------------- End of section using anonymous unions ------------------- */
emilmont 80:8e73be2a2ac1 1109 #if defined(__CC_ARM)
emilmont 80:8e73be2a2ac1 1110 #pragma pop
emilmont 80:8e73be2a2ac1 1111 #elif defined(__ICCARM__)
emilmont 80:8e73be2a2ac1 1112 /* leave anonymous unions enabled */
emilmont 80:8e73be2a2ac1 1113 #elif defined(__GNUC__)
emilmont 80:8e73be2a2ac1 1114 /* anonymous unions are enabled by default */
emilmont 80:8e73be2a2ac1 1115 #elif defined(__TMS470__)
emilmont 80:8e73be2a2ac1 1116 /* anonymous unions are enabled by default */
emilmont 80:8e73be2a2ac1 1117 #elif defined(__TASKING__)
emilmont 80:8e73be2a2ac1 1118 #pragma warning restore
emilmont 80:8e73be2a2ac1 1119 #else
emilmont 80:8e73be2a2ac1 1120 #warning Not supported compiler type
emilmont 80:8e73be2a2ac1 1121 #endif
emilmont 80:8e73be2a2ac1 1122
emilmont 80:8e73be2a2ac1 1123
emilmont 80:8e73be2a2ac1 1124
emilmont 80:8e73be2a2ac1 1125
emilmont 80:8e73be2a2ac1 1126 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1127 /* ================ Peripheral memory map ================ */
emilmont 80:8e73be2a2ac1 1128 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1129
emilmont 80:8e73be2a2ac1 1130 #define NRF_POWER_BASE 0x40000000UL
emilmont 80:8e73be2a2ac1 1131 #define NRF_CLOCK_BASE 0x40000000UL
emilmont 80:8e73be2a2ac1 1132 #define NRF_MPU_BASE 0x40000000UL
emilmont 80:8e73be2a2ac1 1133 #define NRF_PU_BASE 0x40000000UL
emilmont 80:8e73be2a2ac1 1134 #define NRF_AMLI_BASE 0x40000000UL
emilmont 80:8e73be2a2ac1 1135 #define NRF_RADIO_BASE 0x40001000UL
emilmont 80:8e73be2a2ac1 1136 #define NRF_UART0_BASE 0x40002000UL
emilmont 80:8e73be2a2ac1 1137 #define NRF_SPI0_BASE 0x40003000UL
emilmont 80:8e73be2a2ac1 1138 #define NRF_TWI0_BASE 0x40003000UL
emilmont 80:8e73be2a2ac1 1139 #define NRF_SPI1_BASE 0x40004000UL
emilmont 80:8e73be2a2ac1 1140 #define NRF_TWI1_BASE 0x40004000UL
emilmont 80:8e73be2a2ac1 1141 #define NRF_SPIS1_BASE 0x40004000UL
emilmont 80:8e73be2a2ac1 1142 #define NRF_GPIOTE_BASE 0x40006000UL
emilmont 80:8e73be2a2ac1 1143 #define NRF_ADC_BASE 0x40007000UL
emilmont 80:8e73be2a2ac1 1144 #define NRF_TIMER0_BASE 0x40008000UL
emilmont 80:8e73be2a2ac1 1145 #define NRF_TIMER1_BASE 0x40009000UL
emilmont 80:8e73be2a2ac1 1146 #define NRF_TIMER2_BASE 0x4000A000UL
emilmont 80:8e73be2a2ac1 1147 #define NRF_RTC0_BASE 0x4000B000UL
emilmont 80:8e73be2a2ac1 1148 #define NRF_TEMP_BASE 0x4000C000UL
emilmont 80:8e73be2a2ac1 1149 #define NRF_RNG_BASE 0x4000D000UL
emilmont 80:8e73be2a2ac1 1150 #define NRF_ECB_BASE 0x4000E000UL
emilmont 80:8e73be2a2ac1 1151 #define NRF_AAR_BASE 0x4000F000UL
emilmont 80:8e73be2a2ac1 1152 #define NRF_CCM_BASE 0x4000F000UL
emilmont 80:8e73be2a2ac1 1153 #define NRF_WDT_BASE 0x40010000UL
emilmont 80:8e73be2a2ac1 1154 #define NRF_RTC1_BASE 0x40011000UL
emilmont 80:8e73be2a2ac1 1155 #define NRF_QDEC_BASE 0x40012000UL
emilmont 80:8e73be2a2ac1 1156 #define NRF_LPCOMP_BASE 0x40013000UL
emilmont 80:8e73be2a2ac1 1157 #define NRF_COMP_BASE 0x40013000UL
emilmont 80:8e73be2a2ac1 1158 #define NRF_SWI_BASE 0x40014000UL
emilmont 80:8e73be2a2ac1 1159 #define NRF_NVMC_BASE 0x4001E000UL
emilmont 80:8e73be2a2ac1 1160 #define NRF_PPI_BASE 0x4001F000UL
emilmont 80:8e73be2a2ac1 1161 #define NRF_FICR_BASE 0x10000000UL
emilmont 80:8e73be2a2ac1 1162 #define NRF_UICR_BASE 0x10001000UL
emilmont 80:8e73be2a2ac1 1163 #define NRF_GPIO_BASE 0x50000000UL
emilmont 80:8e73be2a2ac1 1164
emilmont 80:8e73be2a2ac1 1165
emilmont 80:8e73be2a2ac1 1166 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1167 /* ================ Peripheral declaration ================ */
emilmont 80:8e73be2a2ac1 1168 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1169
emilmont 80:8e73be2a2ac1 1170 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
emilmont 80:8e73be2a2ac1 1171 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
emilmont 80:8e73be2a2ac1 1172 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
emilmont 80:8e73be2a2ac1 1173 #define NRF_PU ((NRF_PU_Type *) NRF_PU_BASE)
emilmont 80:8e73be2a2ac1 1174 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
emilmont 80:8e73be2a2ac1 1175 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
emilmont 80:8e73be2a2ac1 1176 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
emilmont 80:8e73be2a2ac1 1177 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
emilmont 80:8e73be2a2ac1 1178 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
emilmont 80:8e73be2a2ac1 1179 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
emilmont 80:8e73be2a2ac1 1180 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
emilmont 80:8e73be2a2ac1 1181 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
emilmont 80:8e73be2a2ac1 1182 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
emilmont 80:8e73be2a2ac1 1183 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
emilmont 80:8e73be2a2ac1 1184 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
emilmont 80:8e73be2a2ac1 1185 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
emilmont 80:8e73be2a2ac1 1186 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
emilmont 80:8e73be2a2ac1 1187 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
emilmont 80:8e73be2a2ac1 1188 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
emilmont 80:8e73be2a2ac1 1189 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
emilmont 80:8e73be2a2ac1 1190 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
emilmont 80:8e73be2a2ac1 1191 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
emilmont 80:8e73be2a2ac1 1192 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
emilmont 80:8e73be2a2ac1 1193 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
emilmont 80:8e73be2a2ac1 1194 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
emilmont 80:8e73be2a2ac1 1195 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
emilmont 80:8e73be2a2ac1 1196 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
emilmont 80:8e73be2a2ac1 1197 #define NRF_COMP ((NRF_COMP_Type *) NRF_COMP_BASE)
emilmont 80:8e73be2a2ac1 1198 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
emilmont 80:8e73be2a2ac1 1199 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
emilmont 80:8e73be2a2ac1 1200 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
emilmont 80:8e73be2a2ac1 1201 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
emilmont 80:8e73be2a2ac1 1202 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
emilmont 80:8e73be2a2ac1 1203 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
emilmont 80:8e73be2a2ac1 1204
emilmont 80:8e73be2a2ac1 1205
emilmont 80:8e73be2a2ac1 1206 /** @} */ /* End of group Device_Peripheral_Registers */
emilmont 80:8e73be2a2ac1 1207 /** @} */ /* End of group nRF51 */
emilmont 80:8e73be2a2ac1 1208 /** @} */ /* End of group Nordic Semiconductor */
emilmont 80:8e73be2a2ac1 1209
emilmont 80:8e73be2a2ac1 1210 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 1211 }
emilmont 80:8e73be2a2ac1 1212 #endif
emilmont 80:8e73be2a2ac1 1213
emilmont 80:8e73be2a2ac1 1214
emilmont 80:8e73be2a2ac1 1215 #endif /* nRF51_H */
emilmont 80:8e73be2a2ac1 1216