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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_spi.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5
Child:
99:dbbf35b96557
dgdgr

Who changed what in which revision?

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bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_spi.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of SPI HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_SPI_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_SPI_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 47 #include "stm32f4xx_hal_def.h"
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 50 * @{
bogdanm 92:4fc01daae5a5 51 */
bogdanm 92:4fc01daae5a5 52
bogdanm 92:4fc01daae5a5 53 /** @addtogroup SPI
bogdanm 92:4fc01daae5a5 54 * @{
bogdanm 92:4fc01daae5a5 55 */
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /**
bogdanm 92:4fc01daae5a5 60 * @brief SPI Configuration Structure definition
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62 typedef struct
bogdanm 92:4fc01daae5a5 63 {
bogdanm 92:4fc01daae5a5 64 uint32_t Mode; /*!< Specifies the SPI operating mode.
bogdanm 92:4fc01daae5a5 65 This parameter can be a value of @ref SPI_mode */
bogdanm 92:4fc01daae5a5 66
bogdanm 92:4fc01daae5a5 67 uint32_t Direction; /*!< Specifies the SPI Directional mode state.
bogdanm 92:4fc01daae5a5 68 This parameter can be a value of @ref SPI_Direction_mode */
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 uint32_t DataSize; /*!< Specifies the SPI data size.
bogdanm 92:4fc01daae5a5 71 This parameter can be a value of @ref SPI_data_size */
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 uint32_t CLKPolarity; /*!< Specifies the serial clock steady state.
bogdanm 92:4fc01daae5a5 74 This parameter can be a value of @ref SPI_Clock_Polarity */
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 uint32_t CLKPhase; /*!< Specifies the clock active edge for the bit capture.
bogdanm 92:4fc01daae5a5 77 This parameter can be a value of @ref SPI_Clock_Phase */
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 uint32_t NSS; /*!< Specifies whether the NSS signal is managed by
bogdanm 92:4fc01daae5a5 80 hardware (NSS pin) or by software using the SSI bit.
bogdanm 92:4fc01daae5a5 81 This parameter can be a value of @ref SPI_Slave_Select_management */
bogdanm 92:4fc01daae5a5 82
bogdanm 92:4fc01daae5a5 83 uint32_t BaudRatePrescaler; /*!< Specifies the Baud Rate prescaler value which will be
bogdanm 92:4fc01daae5a5 84 used to configure the transmit and receive SCK clock.
bogdanm 92:4fc01daae5a5 85 This parameter can be a value of @ref SPI_BaudRate_Prescaler
bogdanm 92:4fc01daae5a5 86 @note The communication clock is derived from the master
bogdanm 92:4fc01daae5a5 87 clock. The slave clock does not need to be set */
bogdanm 92:4fc01daae5a5 88
bogdanm 92:4fc01daae5a5 89 uint32_t FirstBit; /*!< Specifies whether data transfers start from MSB or LSB bit.
bogdanm 92:4fc01daae5a5 90 This parameter can be a value of @ref SPI_MSB_LSB_transmission */
bogdanm 92:4fc01daae5a5 91
bogdanm 92:4fc01daae5a5 92 uint32_t TIMode; /*!< Specifies if the TI mode is enabled or not.
bogdanm 92:4fc01daae5a5 93 This parameter can be a value of @ref SPI_TI_mode */
bogdanm 92:4fc01daae5a5 94
bogdanm 92:4fc01daae5a5 95 uint32_t CRCCalculation; /*!< Specifies if the CRC calculation is enabled or not.
bogdanm 92:4fc01daae5a5 96 This parameter can be a value of @ref SPI_CRC_Calculation */
bogdanm 92:4fc01daae5a5 97
bogdanm 92:4fc01daae5a5 98 uint32_t CRCPolynomial; /*!< Specifies the polynomial used for the CRC calculation.
bogdanm 92:4fc01daae5a5 99 This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 }SPI_InitTypeDef;
bogdanm 92:4fc01daae5a5 102
bogdanm 92:4fc01daae5a5 103 /**
bogdanm 92:4fc01daae5a5 104 * @brief HAL SPI State structure definition
bogdanm 92:4fc01daae5a5 105 */
bogdanm 92:4fc01daae5a5 106 typedef enum
bogdanm 92:4fc01daae5a5 107 {
bogdanm 92:4fc01daae5a5 108 HAL_SPI_STATE_RESET = 0x00, /*!< SPI not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 109 HAL_SPI_STATE_READY = 0x01, /*!< SPI initialized and ready for use */
bogdanm 92:4fc01daae5a5 110 HAL_SPI_STATE_BUSY = 0x02, /*!< SPI process is ongoing */
bogdanm 92:4fc01daae5a5 111 HAL_SPI_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
bogdanm 92:4fc01daae5a5 112 HAL_SPI_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
bogdanm 92:4fc01daae5a5 113 HAL_SPI_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
bogdanm 92:4fc01daae5a5 114 HAL_SPI_STATE_ERROR = 0x03 /*!< SPI error state */
bogdanm 92:4fc01daae5a5 115
bogdanm 92:4fc01daae5a5 116 }HAL_SPI_StateTypeDef;
bogdanm 92:4fc01daae5a5 117
bogdanm 92:4fc01daae5a5 118 /**
bogdanm 92:4fc01daae5a5 119 * @brief HAL SPI Error Code structure definition
bogdanm 92:4fc01daae5a5 120 */
bogdanm 92:4fc01daae5a5 121 typedef enum
bogdanm 92:4fc01daae5a5 122 {
bogdanm 92:4fc01daae5a5 123 HAL_SPI_ERROR_NONE = 0x00, /*!< No error */
bogdanm 92:4fc01daae5a5 124 HAL_SPI_ERROR_MODF = 0x01, /*!< MODF error */
bogdanm 92:4fc01daae5a5 125 HAL_SPI_ERROR_CRC = 0x02, /*!< CRC error */
bogdanm 92:4fc01daae5a5 126 HAL_SPI_ERROR_OVR = 0x04, /*!< OVR error */
bogdanm 92:4fc01daae5a5 127 HAL_SPI_ERROR_FRE = 0x08, /*!< FRE error */
bogdanm 92:4fc01daae5a5 128 HAL_SPI_ERROR_DMA = 0x10, /*!< DMA transfer error */
bogdanm 92:4fc01daae5a5 129 HAL_SPI_ERROR_FLAG = 0x20 /*!< Flag: RXNE,TXE, BSY */
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 }HAL_SPI_ErrorTypeDef;
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133 /**
bogdanm 92:4fc01daae5a5 134 * @brief SPI handle Structure definition
bogdanm 92:4fc01daae5a5 135 */
bogdanm 92:4fc01daae5a5 136 typedef struct __SPI_HandleTypeDef
bogdanm 92:4fc01daae5a5 137 {
bogdanm 92:4fc01daae5a5 138 SPI_TypeDef *Instance; /* SPI registers base address */
bogdanm 92:4fc01daae5a5 139
bogdanm 92:4fc01daae5a5 140 SPI_InitTypeDef Init; /* SPI communication parameters */
bogdanm 92:4fc01daae5a5 141
bogdanm 92:4fc01daae5a5 142 uint8_t *pTxBuffPtr; /* Pointer to SPI Tx transfer Buffer */
bogdanm 92:4fc01daae5a5 143
bogdanm 92:4fc01daae5a5 144 uint16_t TxXferSize; /* SPI Tx transfer size */
bogdanm 92:4fc01daae5a5 145
bogdanm 92:4fc01daae5a5 146 uint16_t TxXferCount; /* SPI Tx Transfer Counter */
bogdanm 92:4fc01daae5a5 147
bogdanm 92:4fc01daae5a5 148 uint8_t *pRxBuffPtr; /* Pointer to SPI Rx transfer Buffer */
bogdanm 92:4fc01daae5a5 149
bogdanm 92:4fc01daae5a5 150 uint16_t RxXferSize; /* SPI Rx transfer size */
bogdanm 92:4fc01daae5a5 151
bogdanm 92:4fc01daae5a5 152 uint16_t RxXferCount; /* SPI Rx Transfer Counter */
bogdanm 92:4fc01daae5a5 153
bogdanm 92:4fc01daae5a5 154 DMA_HandleTypeDef *hdmatx; /* SPI Tx DMA handle parameters */
bogdanm 92:4fc01daae5a5 155
bogdanm 92:4fc01daae5a5 156 DMA_HandleTypeDef *hdmarx; /* SPI Rx DMA handle parameters */
bogdanm 92:4fc01daae5a5 157
bogdanm 92:4fc01daae5a5 158 void (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
bogdanm 92:4fc01daae5a5 159
bogdanm 92:4fc01daae5a5 160 void (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
bogdanm 92:4fc01daae5a5 161
bogdanm 92:4fc01daae5a5 162 HAL_LockTypeDef Lock; /* SPI locking object */
bogdanm 92:4fc01daae5a5 163
bogdanm 92:4fc01daae5a5 164 __IO HAL_SPI_StateTypeDef State; /* SPI communication state */
bogdanm 92:4fc01daae5a5 165
bogdanm 92:4fc01daae5a5 166 __IO HAL_SPI_ErrorTypeDef ErrorCode; /* SPI Error code */
bogdanm 92:4fc01daae5a5 167
bogdanm 92:4fc01daae5a5 168 }SPI_HandleTypeDef;
bogdanm 92:4fc01daae5a5 169
bogdanm 92:4fc01daae5a5 170 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 171
bogdanm 92:4fc01daae5a5 172 /** @defgroup SPI_Exported_Constants
bogdanm 92:4fc01daae5a5 173 * @{
bogdanm 92:4fc01daae5a5 174 */
bogdanm 92:4fc01daae5a5 175
bogdanm 92:4fc01daae5a5 176 /** @defgroup SPI_mode
bogdanm 92:4fc01daae5a5 177 * @{
bogdanm 92:4fc01daae5a5 178 */
bogdanm 92:4fc01daae5a5 179 #define SPI_MODE_SLAVE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 180 #define SPI_MODE_MASTER (SPI_CR1_MSTR | SPI_CR1_SSI)
bogdanm 92:4fc01daae5a5 181
bogdanm 92:4fc01daae5a5 182 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
bogdanm 92:4fc01daae5a5 183 ((MODE) == SPI_MODE_MASTER))
bogdanm 92:4fc01daae5a5 184 /**
bogdanm 92:4fc01daae5a5 185 * @}
bogdanm 92:4fc01daae5a5 186 */
bogdanm 92:4fc01daae5a5 187
bogdanm 92:4fc01daae5a5 188 /** @defgroup SPI_Direction_mode
bogdanm 92:4fc01daae5a5 189 * @{
bogdanm 92:4fc01daae5a5 190 */
bogdanm 92:4fc01daae5a5 191 #define SPI_DIRECTION_2LINES ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 192 #define SPI_DIRECTION_2LINES_RXONLY SPI_CR1_RXONLY
bogdanm 92:4fc01daae5a5 193 #define SPI_DIRECTION_1LINE SPI_CR1_BIDIMODE
bogdanm 92:4fc01daae5a5 194
bogdanm 92:4fc01daae5a5 195 #define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
bogdanm 92:4fc01daae5a5 196 ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
bogdanm 92:4fc01daae5a5 197 ((MODE) == SPI_DIRECTION_1LINE))
bogdanm 92:4fc01daae5a5 198
bogdanm 92:4fc01daae5a5 199 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
bogdanm 92:4fc01daae5a5 200 ((MODE) == SPI_DIRECTION_1LINE))
bogdanm 92:4fc01daae5a5 201
bogdanm 92:4fc01daae5a5 202 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
bogdanm 92:4fc01daae5a5 203
bogdanm 92:4fc01daae5a5 204 /**
bogdanm 92:4fc01daae5a5 205 * @}
bogdanm 92:4fc01daae5a5 206 */
bogdanm 92:4fc01daae5a5 207
bogdanm 92:4fc01daae5a5 208 /** @defgroup SPI_data_size
bogdanm 92:4fc01daae5a5 209 * @{
bogdanm 92:4fc01daae5a5 210 */
bogdanm 92:4fc01daae5a5 211 #define SPI_DATASIZE_8BIT ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 212 #define SPI_DATASIZE_16BIT SPI_CR1_DFF
bogdanm 92:4fc01daae5a5 213
bogdanm 92:4fc01daae5a5 214 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
bogdanm 92:4fc01daae5a5 215 ((DATASIZE) == SPI_DATASIZE_8BIT))
bogdanm 92:4fc01daae5a5 216 /**
bogdanm 92:4fc01daae5a5 217 * @}
bogdanm 92:4fc01daae5a5 218 */
bogdanm 92:4fc01daae5a5 219
bogdanm 92:4fc01daae5a5 220 /** @defgroup SPI_Clock_Polarity
bogdanm 92:4fc01daae5a5 221 * @{
bogdanm 92:4fc01daae5a5 222 */
bogdanm 92:4fc01daae5a5 223 #define SPI_POLARITY_LOW ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 224 #define SPI_POLARITY_HIGH SPI_CR1_CPOL
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
bogdanm 92:4fc01daae5a5 227 ((CPOL) == SPI_POLARITY_HIGH))
bogdanm 92:4fc01daae5a5 228 /**
bogdanm 92:4fc01daae5a5 229 * @}
bogdanm 92:4fc01daae5a5 230 */
bogdanm 92:4fc01daae5a5 231
bogdanm 92:4fc01daae5a5 232 /** @defgroup SPI_Clock_Phase
bogdanm 92:4fc01daae5a5 233 * @{
bogdanm 92:4fc01daae5a5 234 */
bogdanm 92:4fc01daae5a5 235 #define SPI_PHASE_1EDGE ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 236 #define SPI_PHASE_2EDGE SPI_CR1_CPHA
bogdanm 92:4fc01daae5a5 237
bogdanm 92:4fc01daae5a5 238 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
bogdanm 92:4fc01daae5a5 239 ((CPHA) == SPI_PHASE_2EDGE))
bogdanm 92:4fc01daae5a5 240 /**
bogdanm 92:4fc01daae5a5 241 * @}
bogdanm 92:4fc01daae5a5 242 */
bogdanm 92:4fc01daae5a5 243
bogdanm 92:4fc01daae5a5 244 /** @defgroup SPI_Slave_Select_management
bogdanm 92:4fc01daae5a5 245 * @{
bogdanm 92:4fc01daae5a5 246 */
bogdanm 92:4fc01daae5a5 247 #define SPI_NSS_SOFT SPI_CR1_SSM
bogdanm 92:4fc01daae5a5 248 #define SPI_NSS_HARD_INPUT ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 249 #define SPI_NSS_HARD_OUTPUT ((uint32_t)0x00040000)
bogdanm 92:4fc01daae5a5 250
bogdanm 92:4fc01daae5a5 251 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT) || \
bogdanm 92:4fc01daae5a5 252 ((NSS) == SPI_NSS_HARD_INPUT) || \
bogdanm 92:4fc01daae5a5 253 ((NSS) == SPI_NSS_HARD_OUTPUT))
bogdanm 92:4fc01daae5a5 254 /**
bogdanm 92:4fc01daae5a5 255 * @}
bogdanm 92:4fc01daae5a5 256 */
bogdanm 92:4fc01daae5a5 257
bogdanm 92:4fc01daae5a5 258 /** @defgroup SPI_BaudRate_Prescaler
bogdanm 92:4fc01daae5a5 259 * @{
bogdanm 92:4fc01daae5a5 260 */
bogdanm 92:4fc01daae5a5 261 #define SPI_BAUDRATEPRESCALER_2 ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 262 #define SPI_BAUDRATEPRESCALER_4 ((uint32_t)0x00000008)
bogdanm 92:4fc01daae5a5 263 #define SPI_BAUDRATEPRESCALER_8 ((uint32_t)0x00000010)
bogdanm 92:4fc01daae5a5 264 #define SPI_BAUDRATEPRESCALER_16 ((uint32_t)0x00000018)
bogdanm 92:4fc01daae5a5 265 #define SPI_BAUDRATEPRESCALER_32 ((uint32_t)0x00000020)
bogdanm 92:4fc01daae5a5 266 #define SPI_BAUDRATEPRESCALER_64 ((uint32_t)0x00000028)
bogdanm 92:4fc01daae5a5 267 #define SPI_BAUDRATEPRESCALER_128 ((uint32_t)0x00000030)
bogdanm 92:4fc01daae5a5 268 #define SPI_BAUDRATEPRESCALER_256 ((uint32_t)0x00000038)
bogdanm 92:4fc01daae5a5 269
bogdanm 92:4fc01daae5a5 270 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2) || \
bogdanm 92:4fc01daae5a5 271 ((PRESCALER) == SPI_BAUDRATEPRESCALER_4) || \
bogdanm 92:4fc01daae5a5 272 ((PRESCALER) == SPI_BAUDRATEPRESCALER_8) || \
bogdanm 92:4fc01daae5a5 273 ((PRESCALER) == SPI_BAUDRATEPRESCALER_16) || \
bogdanm 92:4fc01daae5a5 274 ((PRESCALER) == SPI_BAUDRATEPRESCALER_32) || \
bogdanm 92:4fc01daae5a5 275 ((PRESCALER) == SPI_BAUDRATEPRESCALER_64) || \
bogdanm 92:4fc01daae5a5 276 ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
bogdanm 92:4fc01daae5a5 277 ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
bogdanm 92:4fc01daae5a5 278 /**
bogdanm 92:4fc01daae5a5 279 * @}
bogdanm 92:4fc01daae5a5 280 */
bogdanm 92:4fc01daae5a5 281
bogdanm 92:4fc01daae5a5 282 /** @defgroup SPI_MSB_LSB_transmission
bogdanm 92:4fc01daae5a5 283 * @{
bogdanm 92:4fc01daae5a5 284 */
bogdanm 92:4fc01daae5a5 285 #define SPI_FIRSTBIT_MSB ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 286 #define SPI_FIRSTBIT_LSB SPI_CR1_LSBFIRST
bogdanm 92:4fc01daae5a5 287
bogdanm 92:4fc01daae5a5 288 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
bogdanm 92:4fc01daae5a5 289 ((BIT) == SPI_FIRSTBIT_LSB))
bogdanm 92:4fc01daae5a5 290 /**
bogdanm 92:4fc01daae5a5 291 * @}
bogdanm 92:4fc01daae5a5 292 */
bogdanm 92:4fc01daae5a5 293
bogdanm 92:4fc01daae5a5 294 /** @defgroup SPI_TI_mode
bogdanm 92:4fc01daae5a5 295 * @{
bogdanm 92:4fc01daae5a5 296 */
bogdanm 92:4fc01daae5a5 297 #define SPI_TIMODE_DISABLED ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 298 #define SPI_TIMODE_ENABLED SPI_CR2_FRF
bogdanm 92:4fc01daae5a5 299
bogdanm 92:4fc01daae5a5 300 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
bogdanm 92:4fc01daae5a5 301 ((MODE) == SPI_TIMODE_ENABLED))
bogdanm 92:4fc01daae5a5 302 /**
bogdanm 92:4fc01daae5a5 303 * @}
bogdanm 92:4fc01daae5a5 304 */
bogdanm 92:4fc01daae5a5 305
bogdanm 92:4fc01daae5a5 306 /** @defgroup SPI_CRC_Calculation
bogdanm 92:4fc01daae5a5 307 * @{
bogdanm 92:4fc01daae5a5 308 */
bogdanm 92:4fc01daae5a5 309 #define SPI_CRCCALCULATION_DISABLED ((uint32_t)0x00000000)
bogdanm 92:4fc01daae5a5 310 #define SPI_CRCCALCULATION_ENABLED SPI_CR1_CRCEN
bogdanm 92:4fc01daae5a5 311
bogdanm 92:4fc01daae5a5 312 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
bogdanm 92:4fc01daae5a5 313 ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
bogdanm 92:4fc01daae5a5 314 /**
bogdanm 92:4fc01daae5a5 315 * @}
bogdanm 92:4fc01daae5a5 316 */
bogdanm 92:4fc01daae5a5 317
bogdanm 92:4fc01daae5a5 318 /** @defgroup SPI_Interrupt_configuration_definition
bogdanm 92:4fc01daae5a5 319 * @{
bogdanm 92:4fc01daae5a5 320 */
bogdanm 92:4fc01daae5a5 321 #define SPI_IT_TXE SPI_CR2_TXEIE
bogdanm 92:4fc01daae5a5 322 #define SPI_IT_RXNE SPI_CR2_RXNEIE
bogdanm 92:4fc01daae5a5 323 #define SPI_IT_ERR SPI_CR2_ERRIE
bogdanm 92:4fc01daae5a5 324 /**
bogdanm 92:4fc01daae5a5 325 * @}
bogdanm 92:4fc01daae5a5 326 */
bogdanm 92:4fc01daae5a5 327
bogdanm 92:4fc01daae5a5 328 /** @defgroup SPI_Flag_definition
bogdanm 92:4fc01daae5a5 329 * @{
bogdanm 92:4fc01daae5a5 330 */
bogdanm 92:4fc01daae5a5 331 #define SPI_FLAG_RXNE SPI_SR_RXNE
bogdanm 92:4fc01daae5a5 332 #define SPI_FLAG_TXE SPI_SR_TXE
bogdanm 92:4fc01daae5a5 333 #define SPI_FLAG_CRCERR SPI_SR_CRCERR
bogdanm 92:4fc01daae5a5 334 #define SPI_FLAG_MODF SPI_SR_MODF
bogdanm 92:4fc01daae5a5 335 #define SPI_FLAG_OVR SPI_SR_OVR
bogdanm 92:4fc01daae5a5 336 #define SPI_FLAG_BSY SPI_SR_BSY
bogdanm 92:4fc01daae5a5 337 #define SPI_FLAG_FRE SPI_SR_FRE
bogdanm 92:4fc01daae5a5 338
bogdanm 92:4fc01daae5a5 339 /**
bogdanm 92:4fc01daae5a5 340 * @}
bogdanm 92:4fc01daae5a5 341 */
bogdanm 92:4fc01daae5a5 342
bogdanm 92:4fc01daae5a5 343 /**
bogdanm 92:4fc01daae5a5 344 * @}
bogdanm 92:4fc01daae5a5 345 */
bogdanm 92:4fc01daae5a5 346
bogdanm 92:4fc01daae5a5 347 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 348
bogdanm 92:4fc01daae5a5 349 /** @brief Reset SPI handle state
bogdanm 92:4fc01daae5a5 350 * @param __HANDLE__: specifies the SPI handle.
bogdanm 92:4fc01daae5a5 351 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 92:4fc01daae5a5 352 * @retval None
bogdanm 92:4fc01daae5a5 353 */
bogdanm 92:4fc01daae5a5 354 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
bogdanm 92:4fc01daae5a5 355
bogdanm 92:4fc01daae5a5 356 /** @brief Enable or disable the specified SPI interrupts.
bogdanm 92:4fc01daae5a5 357 * @param __HANDLE__: specifies the SPI handle.
bogdanm 92:4fc01daae5a5 358 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 92:4fc01daae5a5 359 * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
bogdanm 92:4fc01daae5a5 360 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 361 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 92:4fc01daae5a5 362 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 92:4fc01daae5a5 363 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 92:4fc01daae5a5 364 * @retval None
bogdanm 92:4fc01daae5a5 365 */
bogdanm 92:4fc01daae5a5 366 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
bogdanm 92:4fc01daae5a5 367 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
bogdanm 92:4fc01daae5a5 368
bogdanm 92:4fc01daae5a5 369 /** @brief Check if the specified SPI interrupt source is enabled or disabled.
bogdanm 92:4fc01daae5a5 370 * @param __HANDLE__: specifies the SPI handle.
bogdanm 92:4fc01daae5a5 371 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 92:4fc01daae5a5 372 * @param __INTERRUPT__: specifies the SPI interrupt source to check.
bogdanm 92:4fc01daae5a5 373 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 374 * @arg SPI_IT_TXE: Tx buffer empty interrupt enable
bogdanm 92:4fc01daae5a5 375 * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
bogdanm 92:4fc01daae5a5 376 * @arg SPI_IT_ERR: Error interrupt enable
bogdanm 92:4fc01daae5a5 377 * @retval The new state of __IT__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 378 */
bogdanm 92:4fc01daae5a5 379 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 92:4fc01daae5a5 380
bogdanm 92:4fc01daae5a5 381 /** @brief Check whether the specified SPI flag is set or not.
bogdanm 92:4fc01daae5a5 382 * @param __HANDLE__: specifies the SPI handle.
bogdanm 92:4fc01daae5a5 383 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 92:4fc01daae5a5 384 * @param __FLAG__: specifies the flag to check.
bogdanm 92:4fc01daae5a5 385 * This parameter can be one of the following values:
bogdanm 92:4fc01daae5a5 386 * @arg SPI_FLAG_RXNE: Receive buffer not empty flag
bogdanm 92:4fc01daae5a5 387 * @arg SPI_FLAG_TXE: Transmit buffer empty flag
bogdanm 92:4fc01daae5a5 388 * @arg SPI_FLAG_CRCERR: CRC error flag
bogdanm 92:4fc01daae5a5 389 * @arg SPI_FLAG_MODF: Mode fault flag
bogdanm 92:4fc01daae5a5 390 * @arg SPI_FLAG_OVR: Overrun flag
bogdanm 92:4fc01daae5a5 391 * @arg SPI_FLAG_BSY: Busy flag
bogdanm 92:4fc01daae5a5 392 * @arg SPI_FLAG_FRE: Frame format error flag
bogdanm 92:4fc01daae5a5 393 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 92:4fc01daae5a5 394 */
bogdanm 92:4fc01daae5a5 395 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
bogdanm 92:4fc01daae5a5 396
bogdanm 92:4fc01daae5a5 397 /** @brief Clear the SPI CRCERR pending flag.
bogdanm 92:4fc01daae5a5 398 * @param __HANDLE__: specifies the SPI handle.
bogdanm 92:4fc01daae5a5 399 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 92:4fc01daae5a5 400 * @retval None
bogdanm 92:4fc01daae5a5 401 */
bogdanm 92:4fc01daae5a5 402 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
bogdanm 92:4fc01daae5a5 403
bogdanm 92:4fc01daae5a5 404 /** @brief Clear the SPI MODF pending flag.
bogdanm 92:4fc01daae5a5 405 * @param __HANDLE__: specifies the SPI handle.
bogdanm 92:4fc01daae5a5 406 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 92:4fc01daae5a5 407 * @retval None
bogdanm 92:4fc01daae5a5 408 */
bogdanm 92:4fc01daae5a5 409 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
bogdanm 92:4fc01daae5a5 410 (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE);}while(0)
bogdanm 92:4fc01daae5a5 411
bogdanm 92:4fc01daae5a5 412 /** @brief Clear the SPI OVR pending flag.
bogdanm 92:4fc01daae5a5 413 * @param __HANDLE__: specifies the SPI handle.
bogdanm 92:4fc01daae5a5 414 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 92:4fc01daae5a5 415 * @retval None
bogdanm 92:4fc01daae5a5 416 */
bogdanm 92:4fc01daae5a5 417 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
bogdanm 92:4fc01daae5a5 418 (__HANDLE__)->Instance->SR;}while(0)
bogdanm 92:4fc01daae5a5 419
bogdanm 92:4fc01daae5a5 420 /** @brief Clear the SPI FRE pending flag.
bogdanm 92:4fc01daae5a5 421 * @param __HANDLE__: specifies the SPI handle.
bogdanm 92:4fc01daae5a5 422 * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
bogdanm 92:4fc01daae5a5 423 * @retval None
bogdanm 92:4fc01daae5a5 424 */
bogdanm 92:4fc01daae5a5 425 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
bogdanm 92:4fc01daae5a5 426
bogdanm 92:4fc01daae5a5 427 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE)
bogdanm 92:4fc01daae5a5 428 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_SPE)
bogdanm 92:4fc01daae5a5 429
bogdanm 92:4fc01daae5a5 430 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
bogdanm 92:4fc01daae5a5 431
bogdanm 92:4fc01daae5a5 432 #define __HAL_SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
bogdanm 92:4fc01daae5a5 433
bogdanm 92:4fc01daae5a5 434 #define __HAL_SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SPI_CR1_BIDIOE)
bogdanm 92:4fc01daae5a5 435
bogdanm 92:4fc01daae5a5 436 #define __HAL_SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (~SPI_CR1_CRCEN);\
bogdanm 92:4fc01daae5a5 437 (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
bogdanm 92:4fc01daae5a5 438
bogdanm 92:4fc01daae5a5 439 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 440
bogdanm 92:4fc01daae5a5 441 /* Initialization/de-initialization functions **********************************/
bogdanm 92:4fc01daae5a5 442 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 443 HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 444 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 445 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 446
bogdanm 92:4fc01daae5a5 447 /* I/O operation functions *****************************************************/
bogdanm 92:4fc01daae5a5 448 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 449 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 450 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 451 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 452 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 453 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 92:4fc01daae5a5 454 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 455 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
bogdanm 92:4fc01daae5a5 456 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
bogdanm 92:4fc01daae5a5 457 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 458 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 459 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 460
bogdanm 92:4fc01daae5a5 461 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 462 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 463 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 464 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 465 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 466 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 467 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 468 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 469
bogdanm 92:4fc01daae5a5 470 /* Peripheral State and Control functions **************************************/
bogdanm 92:4fc01daae5a5 471 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 472 HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
bogdanm 92:4fc01daae5a5 473
bogdanm 92:4fc01daae5a5 474 /**
bogdanm 92:4fc01daae5a5 475 * @}
bogdanm 92:4fc01daae5a5 476 */
bogdanm 92:4fc01daae5a5 477
bogdanm 92:4fc01daae5a5 478 /**
bogdanm 92:4fc01daae5a5 479 * @}
bogdanm 92:4fc01daae5a5 480 */
bogdanm 92:4fc01daae5a5 481
bogdanm 92:4fc01daae5a5 482 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 483 }
bogdanm 92:4fc01daae5a5 484 #endif
bogdanm 92:4fc01daae5a5 485
bogdanm 92:4fc01daae5a5 486 #endif /* __STM32F4xx_HAL_SPI_H */
bogdanm 92:4fc01daae5a5 487
bogdanm 92:4fc01daae5a5 488 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/