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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_sdram.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
92:4fc01daae5a5
Child:
99:dbbf35b96557
dgdgr

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bogdanm 92:4fc01daae5a5 1 /**
bogdanm 92:4fc01daae5a5 2 ******************************************************************************
bogdanm 92:4fc01daae5a5 3 * @file stm32f4xx_hal_sdram.h
bogdanm 92:4fc01daae5a5 4 * @author MCD Application Team
bogdanm 92:4fc01daae5a5 5 * @version V1.1.0
bogdanm 92:4fc01daae5a5 6 * @date 19-June-2014
bogdanm 92:4fc01daae5a5 7 * @brief Header file of SDRAM HAL module.
bogdanm 92:4fc01daae5a5 8 ******************************************************************************
bogdanm 92:4fc01daae5a5 9 * @attention
bogdanm 92:4fc01daae5a5 10 *
bogdanm 92:4fc01daae5a5 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 92:4fc01daae5a5 12 *
bogdanm 92:4fc01daae5a5 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 92:4fc01daae5a5 14 * are permitted provided that the following conditions are met:
bogdanm 92:4fc01daae5a5 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 92:4fc01daae5a5 16 * this list of conditions and the following disclaimer.
bogdanm 92:4fc01daae5a5 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 92:4fc01daae5a5 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 92:4fc01daae5a5 19 * and/or other materials provided with the distribution.
bogdanm 92:4fc01daae5a5 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 92:4fc01daae5a5 21 * may be used to endorse or promote products derived from this software
bogdanm 92:4fc01daae5a5 22 * without specific prior written permission.
bogdanm 92:4fc01daae5a5 23 *
bogdanm 92:4fc01daae5a5 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 92:4fc01daae5a5 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 92:4fc01daae5a5 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 92:4fc01daae5a5 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 92:4fc01daae5a5 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 92:4fc01daae5a5 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 92:4fc01daae5a5 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 92:4fc01daae5a5 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 92:4fc01daae5a5 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 92:4fc01daae5a5 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 92:4fc01daae5a5 34 *
bogdanm 92:4fc01daae5a5 35 ******************************************************************************
bogdanm 92:4fc01daae5a5 36 */
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 92:4fc01daae5a5 39 #ifndef __STM32F4xx_HAL_SDRAM_H
bogdanm 92:4fc01daae5a5 40 #define __STM32F4xx_HAL_SDRAM_H
bogdanm 92:4fc01daae5a5 41
bogdanm 92:4fc01daae5a5 42 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 43 extern "C" {
bogdanm 92:4fc01daae5a5 44 #endif
bogdanm 92:4fc01daae5a5 45
bogdanm 92:4fc01daae5a5 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
bogdanm 92:4fc01daae5a5 47
bogdanm 92:4fc01daae5a5 48 /* Includes ------------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 49 #include "stm32f4xx_ll_fmc.h"
bogdanm 92:4fc01daae5a5 50
bogdanm 92:4fc01daae5a5 51 /** @addtogroup STM32F4xx_HAL_Driver
bogdanm 92:4fc01daae5a5 52 * @{
bogdanm 92:4fc01daae5a5 53 */
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 /** @addtogroup SDRAM
bogdanm 92:4fc01daae5a5 56 * @{
bogdanm 92:4fc01daae5a5 57 */
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 /* Exported typedef ----------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 60
bogdanm 92:4fc01daae5a5 61 /**
bogdanm 92:4fc01daae5a5 62 * @brief HAL SDRAM State structure definition
bogdanm 92:4fc01daae5a5 63 */
bogdanm 92:4fc01daae5a5 64 typedef enum
bogdanm 92:4fc01daae5a5 65 {
bogdanm 92:4fc01daae5a5 66 HAL_SDRAM_STATE_RESET = 0x00, /*!< SDRAM not yet initialized or disabled */
bogdanm 92:4fc01daae5a5 67 HAL_SDRAM_STATE_READY = 0x01, /*!< SDRAM initialized and ready for use */
bogdanm 92:4fc01daae5a5 68 HAL_SDRAM_STATE_BUSY = 0x02, /*!< SDRAM internal process is ongoing */
bogdanm 92:4fc01daae5a5 69 HAL_SDRAM_STATE_ERROR = 0x03, /*!< SDRAM error state */
bogdanm 92:4fc01daae5a5 70 HAL_SDRAM_STATE_WRITE_PROTECTED = 0x04, /*!< SDRAM device write protected */
bogdanm 92:4fc01daae5a5 71 HAL_SDRAM_STATE_PRECHARGED = 0x05 /*!< SDRAM device precharged */
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 }HAL_SDRAM_StateTypeDef;
bogdanm 92:4fc01daae5a5 74
bogdanm 92:4fc01daae5a5 75 /**
bogdanm 92:4fc01daae5a5 76 * @brief SDRAM handle Structure definition
bogdanm 92:4fc01daae5a5 77 */
bogdanm 92:4fc01daae5a5 78 typedef struct
bogdanm 92:4fc01daae5a5 79 {
bogdanm 92:4fc01daae5a5 80 FMC_SDRAM_TypeDef *Instance; /*!< Register base address */
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 FMC_SDRAM_InitTypeDef Init; /*!< SDRAM device configuration parameters */
bogdanm 92:4fc01daae5a5 83
bogdanm 92:4fc01daae5a5 84 __IO HAL_SDRAM_StateTypeDef State; /*!< SDRAM access state */
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 HAL_LockTypeDef Lock; /*!< SDRAM locking object */
bogdanm 92:4fc01daae5a5 87
bogdanm 92:4fc01daae5a5 88 DMA_HandleTypeDef *hdma; /*!< Pointer DMA handler */
bogdanm 92:4fc01daae5a5 89
bogdanm 92:4fc01daae5a5 90 }SDRAM_HandleTypeDef;
bogdanm 92:4fc01daae5a5 91
bogdanm 92:4fc01daae5a5 92 /* Exported types ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 93 /* Exported macro ------------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 94
bogdanm 92:4fc01daae5a5 95 /** @brief Reset SDRAM handle state
bogdanm 92:4fc01daae5a5 96 * @param __HANDLE__: specifies the SDRAM handle.
bogdanm 92:4fc01daae5a5 97 * @retval None
bogdanm 92:4fc01daae5a5 98 */
bogdanm 92:4fc01daae5a5 99 #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 /* Exported functions --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 102
bogdanm 92:4fc01daae5a5 103 /* Initialization/de-initialization functions **********************************/
bogdanm 92:4fc01daae5a5 104 HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing);
bogdanm 92:4fc01daae5a5 105 HAL_StatusTypeDef HAL_SDRAM_DeInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 92:4fc01daae5a5 106 void HAL_SDRAM_MspInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 92:4fc01daae5a5 107 void HAL_SDRAM_MspDeInit(SDRAM_HandleTypeDef *hsdram);
bogdanm 92:4fc01daae5a5 108
bogdanm 92:4fc01daae5a5 109 void HAL_SDRAM_IRQHandler(SDRAM_HandleTypeDef *hsdram);
bogdanm 92:4fc01daae5a5 110 void HAL_SDRAM_RefreshErrorCallback(SDRAM_HandleTypeDef *hsdram);
bogdanm 92:4fc01daae5a5 111 void HAL_SDRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 112 void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
bogdanm 92:4fc01daae5a5 113
bogdanm 92:4fc01daae5a5 114 /* I/O operation functions *****************************************************/
bogdanm 92:4fc01daae5a5 115 HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 116 HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 117 HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 118 HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 119 HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 120 HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 121
bogdanm 92:4fc01daae5a5 122 HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t * pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 123 HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
bogdanm 92:4fc01daae5a5 124
bogdanm 92:4fc01daae5a5 125 /* SDRAM Control functions *****************************************************/
bogdanm 92:4fc01daae5a5 126 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Enable(SDRAM_HandleTypeDef *hsdram);
bogdanm 92:4fc01daae5a5 127 HAL_StatusTypeDef HAL_SDRAM_WriteProtection_Disable(SDRAM_HandleTypeDef *hsdram);
bogdanm 92:4fc01daae5a5 128 HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
bogdanm 92:4fc01daae5a5 129 HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate);
bogdanm 92:4fc01daae5a5 130 HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber);
bogdanm 92:4fc01daae5a5 131 uint32_t HAL_SDRAM_GetModeStatus(SDRAM_HandleTypeDef *hsdram);
bogdanm 92:4fc01daae5a5 132
bogdanm 92:4fc01daae5a5 133 /* SDRAM State functions ********************************************************/
bogdanm 92:4fc01daae5a5 134 HAL_SDRAM_StateTypeDef HAL_SDRAM_GetState(SDRAM_HandleTypeDef *hsdram);
bogdanm 92:4fc01daae5a5 135
bogdanm 92:4fc01daae5a5 136 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
bogdanm 92:4fc01daae5a5 137 /**
bogdanm 92:4fc01daae5a5 138 * @}
bogdanm 92:4fc01daae5a5 139 */
bogdanm 92:4fc01daae5a5 140
bogdanm 92:4fc01daae5a5 141 /**
bogdanm 92:4fc01daae5a5 142 * @}
bogdanm 92:4fc01daae5a5 143 */
bogdanm 92:4fc01daae5a5 144
bogdanm 92:4fc01daae5a5 145 #ifdef __cplusplus
bogdanm 92:4fc01daae5a5 146 }
bogdanm 92:4fc01daae5a5 147 #endif
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 #endif /* __STM32F4xx_HAL_SDRAM_H */
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/