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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_rcc.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:: ricardobtez
Date:: Tue Apr 05 23:51:21 2016 +0000
Revision:: 118:16969dd821af
Parent:: 92:4fc01daae5a5
Child:: 93:e188a91d3eaa

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User	Revision	Line number	New contents of line
bogdanm	92:4fc01daae5a5	1	/**
bogdanm	92:4fc01daae5a5	2	******************************************************************************
bogdanm	92:4fc01daae5a5	3	* @file stm32f4xx_hal_rcc.h
bogdanm	92:4fc01daae5a5	4	* @author MCD Application Team
bogdanm	92:4fc01daae5a5	5	* @version V1.1.0
bogdanm	92:4fc01daae5a5	6	* @date 19-June-2014
bogdanm	92:4fc01daae5a5	7	* @brief Header file of RCC HAL module.
bogdanm	92:4fc01daae5a5	8	******************************************************************************
bogdanm	92:4fc01daae5a5	9	* @attention
bogdanm	92:4fc01daae5a5	10	*
bogdanm	92:4fc01daae5a5	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	92:4fc01daae5a5	12	*
bogdanm	92:4fc01daae5a5	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	92:4fc01daae5a5	14	* are permitted provided that the following conditions are met:
bogdanm	92:4fc01daae5a5	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	92:4fc01daae5a5	16	* this list of conditions and the following disclaimer.
bogdanm	92:4fc01daae5a5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	92:4fc01daae5a5	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	92:4fc01daae5a5	19	* and/or other materials provided with the distribution.
bogdanm	92:4fc01daae5a5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	92:4fc01daae5a5	21	* may be used to endorse or promote products derived from this software
bogdanm	92:4fc01daae5a5	22	* without specific prior written permission.
bogdanm	92:4fc01daae5a5	23	*
bogdanm	92:4fc01daae5a5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	92:4fc01daae5a5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	92:4fc01daae5a5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	92:4fc01daae5a5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	92:4fc01daae5a5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	92:4fc01daae5a5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	92:4fc01daae5a5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	92:4fc01daae5a5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	92:4fc01daae5a5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	92:4fc01daae5a5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	92:4fc01daae5a5	34	*
bogdanm	92:4fc01daae5a5	35	******************************************************************************
bogdanm	92:4fc01daae5a5	36	*/
bogdanm	92:4fc01daae5a5	37
bogdanm	92:4fc01daae5a5	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	92:4fc01daae5a5	39	#ifndef __STM32F4xx_HAL_RCC_H
bogdanm	92:4fc01daae5a5	40	#define __STM32F4xx_HAL_RCC_H
bogdanm	92:4fc01daae5a5	41
bogdanm	92:4fc01daae5a5	42	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	43	extern "C" {
bogdanm	92:4fc01daae5a5	44	#endif
bogdanm	92:4fc01daae5a5	45
bogdanm	92:4fc01daae5a5	46	/* Includes ------------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	47	#include "stm32f4xx_hal_def.h"
bogdanm	92:4fc01daae5a5	48
bogdanm	92:4fc01daae5a5	49	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	92:4fc01daae5a5	50	* @{
bogdanm	92:4fc01daae5a5	51	*/
bogdanm	92:4fc01daae5a5	52
bogdanm	92:4fc01daae5a5	53	/** @addtogroup RCC
bogdanm	92:4fc01daae5a5	54	* @{
bogdanm	92:4fc01daae5a5	55	*/
bogdanm	92:4fc01daae5a5	56
bogdanm	92:4fc01daae5a5	57	/* Exported types ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	58
bogdanm	92:4fc01daae5a5	59	/**
bogdanm	92:4fc01daae5a5	60	* @brief RCC PLL configuration structure definition
bogdanm	92:4fc01daae5a5	61	*/
bogdanm	92:4fc01daae5a5	62	typedef struct
bogdanm	92:4fc01daae5a5	63	{
bogdanm	92:4fc01daae5a5	64	uint32_t PLLState; /*!< The new state of the PLL.
bogdanm	92:4fc01daae5a5	65	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	92:4fc01daae5a5	66
bogdanm	92:4fc01daae5a5	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
bogdanm	92:4fc01daae5a5	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
bogdanm	92:4fc01daae5a5	69
bogdanm	92:4fc01daae5a5	70	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock.
bogdanm	92:4fc01daae5a5	71	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
bogdanm	92:4fc01daae5a5	72
bogdanm	92:4fc01daae5a5	73	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock.
bogdanm	92:4fc01daae5a5	74	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
bogdanm	92:4fc01daae5a5	75
bogdanm	92:4fc01daae5a5	76	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK).
bogdanm	92:4fc01daae5a5	77	This parameter must be a value of @ref RCC_PLLP_Clock_Divider */
bogdanm	92:4fc01daae5a5	78
bogdanm	92:4fc01daae5a5	79	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks.
bogdanm	92:4fc01daae5a5	80	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
bogdanm	92:4fc01daae5a5	81
bogdanm	92:4fc01daae5a5	82	}RCC_PLLInitTypeDef;
bogdanm	92:4fc01daae5a5	83
bogdanm	92:4fc01daae5a5	84	/**
bogdanm	92:4fc01daae5a5	85	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	92:4fc01daae5a5	86	*/
bogdanm	92:4fc01daae5a5	87	typedef struct
bogdanm	92:4fc01daae5a5	88	{
bogdanm	92:4fc01daae5a5	89	uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm	92:4fc01daae5a5	90	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	92:4fc01daae5a5	91
bogdanm	92:4fc01daae5a5	92	uint32_t HSEState; /*!< The new state of the HSE.
bogdanm	92:4fc01daae5a5	93	This parameter can be a value of @ref RCC_HSE_Config */
bogdanm	92:4fc01daae5a5	94
bogdanm	92:4fc01daae5a5	95	uint32_t LSEState; /*!< The new state of the LSE.
bogdanm	92:4fc01daae5a5	96	This parameter can be a value of @ref RCC_LSE_Config */
bogdanm	92:4fc01daae5a5	97
bogdanm	92:4fc01daae5a5	98	uint32_t HSIState; /*!< The new state of the HSI.
bogdanm	92:4fc01daae5a5	99	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	92:4fc01daae5a5	100
bogdanm	92:4fc01daae5a5	101	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm	92:4fc01daae5a5	102	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	92:4fc01daae5a5	103
bogdanm	92:4fc01daae5a5	104	uint32_t LSIState; /*!< The new state of the LSI.
bogdanm	92:4fc01daae5a5	105	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	92:4fc01daae5a5	106
bogdanm	92:4fc01daae5a5	107	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
bogdanm	92:4fc01daae5a5	108
bogdanm	92:4fc01daae5a5	109	}RCC_OscInitTypeDef;
bogdanm	92:4fc01daae5a5	110
bogdanm	92:4fc01daae5a5	111	/**
bogdanm	92:4fc01daae5a5	112	* @brief RCC System, AHB and APB busses clock configuration structure definition
bogdanm	92:4fc01daae5a5	113	*/
bogdanm	92:4fc01daae5a5	114	typedef struct
bogdanm	92:4fc01daae5a5	115	{
bogdanm	92:4fc01daae5a5	116	uint32_t ClockType; /*!< The clock to be configured.
bogdanm	92:4fc01daae5a5	117	This parameter can be a value of @ref RCC_System_Clock_Type */
bogdanm	92:4fc01daae5a5	118
bogdanm	92:4fc01daae5a5	119	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
bogdanm	92:4fc01daae5a5	120	This parameter can be a value of @ref RCC_System_Clock_Source */
bogdanm	92:4fc01daae5a5	121
bogdanm	92:4fc01daae5a5	122	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
bogdanm	92:4fc01daae5a5	123	This parameter can be a value of @ref RCC_AHB_Clock_Source */
bogdanm	92:4fc01daae5a5	124
bogdanm	92:4fc01daae5a5	125	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	92:4fc01daae5a5	126	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	92:4fc01daae5a5	127
bogdanm	92:4fc01daae5a5	128	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
bogdanm	92:4fc01daae5a5	129	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
bogdanm	92:4fc01daae5a5	130
bogdanm	92:4fc01daae5a5	131	}RCC_ClkInitTypeDef;
bogdanm	92:4fc01daae5a5	132
bogdanm	92:4fc01daae5a5	133	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	134	/** @defgroup RCC_Exported_Constants
bogdanm	92:4fc01daae5a5	135	* @{
bogdanm	92:4fc01daae5a5	136	*/
bogdanm	92:4fc01daae5a5	137
bogdanm	92:4fc01daae5a5	138	/** @defgroup RCC_BitAddress_AliasRegion
bogdanm	92:4fc01daae5a5	139	* @brief RCC registers bit address in the alias region
bogdanm	92:4fc01daae5a5	140	* @{
bogdanm	92:4fc01daae5a5	141	*/
bogdanm	92:4fc01daae5a5	142	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
bogdanm	92:4fc01daae5a5	143	/* --- CR Register ---*/
bogdanm	92:4fc01daae5a5	144	/* Alias word address of HSION bit */
bogdanm	92:4fc01daae5a5	145	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
bogdanm	92:4fc01daae5a5	146	#define HSION_BitNumber 0x00
bogdanm	92:4fc01daae5a5	147	#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
bogdanm	92:4fc01daae5a5	148	/* Alias word address of CSSON bit */
bogdanm	92:4fc01daae5a5	149	#define CSSON_BitNumber 0x13
bogdanm	92:4fc01daae5a5	150	#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
bogdanm	92:4fc01daae5a5	151	/* Alias word address of PLLON bit */
bogdanm	92:4fc01daae5a5	152	#define PLLON_BitNumber 0x18
bogdanm	92:4fc01daae5a5	153	#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
bogdanm	92:4fc01daae5a5	154	/* Alias word address of PLLI2SON bit */
bogdanm	92:4fc01daae5a5	155	#define PLLI2SON_BitNumber 0x1A
bogdanm	92:4fc01daae5a5	156	#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
bogdanm	92:4fc01daae5a5	157
bogdanm	92:4fc01daae5a5	158	/* --- CFGR Register ---*/
bogdanm	92:4fc01daae5a5	159	/* Alias word address of I2SSRC bit */
bogdanm	92:4fc01daae5a5	160	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
bogdanm	92:4fc01daae5a5	161	#define I2SSRC_BitNumber 0x17
bogdanm	92:4fc01daae5a5	162	#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
bogdanm	92:4fc01daae5a5	163
bogdanm	92:4fc01daae5a5	164	/* --- BDCR Register ---*/
bogdanm	92:4fc01daae5a5	165	/* Alias word address of RTCEN bit */
bogdanm	92:4fc01daae5a5	166	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
bogdanm	92:4fc01daae5a5	167	#define RTCEN_BitNumber 0x0F
bogdanm	92:4fc01daae5a5	168	#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
bogdanm	92:4fc01daae5a5	169	/* Alias word address of BDRST bit */
bogdanm	92:4fc01daae5a5	170	#define BDRST_BitNumber 0x10
bogdanm	92:4fc01daae5a5	171	#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
bogdanm	92:4fc01daae5a5	172
bogdanm	92:4fc01daae5a5	173	/* --- CSR Register ---*/
bogdanm	92:4fc01daae5a5	174	/* Alias word address of LSION bit */
bogdanm	92:4fc01daae5a5	175	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
bogdanm	92:4fc01daae5a5	176	#define LSION_BitNumber 0x00
bogdanm	92:4fc01daae5a5	177	#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
bogdanm	92:4fc01daae5a5	178
bogdanm	92:4fc01daae5a5	179	/* CR register byte 3 (Bits[23:16]) base address */
bogdanm	92:4fc01daae5a5	180	#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
bogdanm	92:4fc01daae5a5	181
bogdanm	92:4fc01daae5a5	182	/* CIR register byte 2 (Bits[15:8]) base address */
bogdanm	92:4fc01daae5a5	183	#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
bogdanm	92:4fc01daae5a5	184
bogdanm	92:4fc01daae5a5	185	/* CIR register byte 3 (Bits[23:16]) base address */
bogdanm	92:4fc01daae5a5	186	#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
bogdanm	92:4fc01daae5a5	187
bogdanm	92:4fc01daae5a5	188	/* BDCR register base address */
bogdanm	92:4fc01daae5a5	189	#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
bogdanm	92:4fc01daae5a5	190
bogdanm	92:4fc01daae5a5	191
bogdanm	92:4fc01daae5a5	192	#define DBP_TIMEOUT_VALUE ((uint32_t)100)
bogdanm	92:4fc01daae5a5	193	#define LSE_TIMEOUT_VALUE ((uint32_t)600)
bogdanm	92:4fc01daae5a5	194	/**
bogdanm	92:4fc01daae5a5	195	* @}
bogdanm	92:4fc01daae5a5	196	*/
bogdanm	92:4fc01daae5a5	197
bogdanm	92:4fc01daae5a5	198	/** @defgroup RCC_Oscillator_Type
bogdanm	92:4fc01daae5a5	199	* @{
bogdanm	92:4fc01daae5a5	200	*/
bogdanm	92:4fc01daae5a5	201	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	202	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	203	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	204	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	205	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	206
bogdanm	92:4fc01daae5a5	207	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
bogdanm	92:4fc01daae5a5	208	/**
bogdanm	92:4fc01daae5a5	209	* @}
bogdanm	92:4fc01daae5a5	210	*/
bogdanm	92:4fc01daae5a5	211
bogdanm	92:4fc01daae5a5	212	/** @defgroup RCC_HSE_Config
bogdanm	92:4fc01daae5a5	213	* @{
bogdanm	92:4fc01daae5a5	214	*/
bogdanm	92:4fc01daae5a5	215	#define RCC_HSE_OFF ((uint8_t)0x00)
bogdanm	92:4fc01daae5a5	216	#define RCC_HSE_ON ((uint8_t)0x01)
bogdanm	92:4fc01daae5a5	217	#define RCC_HSE_BYPASS ((uint8_t)0x05)
bogdanm	92:4fc01daae5a5	218
bogdanm	92:4fc01daae5a5	219	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
bogdanm	92:4fc01daae5a5	220	((HSE) == RCC_HSE_BYPASS))
bogdanm	92:4fc01daae5a5	221	/**
bogdanm	92:4fc01daae5a5	222	* @}
bogdanm	92:4fc01daae5a5	223	*/
bogdanm	92:4fc01daae5a5	224
bogdanm	92:4fc01daae5a5	225	/** @defgroup RCC_LSE_Config
bogdanm	92:4fc01daae5a5	226	* @{
bogdanm	92:4fc01daae5a5	227	*/
bogdanm	92:4fc01daae5a5	228	#define RCC_LSE_OFF ((uint8_t)0x00)
bogdanm	92:4fc01daae5a5	229	#define RCC_LSE_ON ((uint8_t)0x01)
bogdanm	92:4fc01daae5a5	230	#define RCC_LSE_BYPASS ((uint8_t)0x05)
bogdanm	92:4fc01daae5a5	231
bogdanm	92:4fc01daae5a5	232	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
bogdanm	92:4fc01daae5a5	233	((LSE) == RCC_LSE_BYPASS))
bogdanm	92:4fc01daae5a5	234	/**
bogdanm	92:4fc01daae5a5	235	* @}
bogdanm	92:4fc01daae5a5	236	*/
bogdanm	92:4fc01daae5a5	237
bogdanm	92:4fc01daae5a5	238	/** @defgroup RCC_HSI_Config
bogdanm	92:4fc01daae5a5	239	* @{
bogdanm	92:4fc01daae5a5	240	*/
bogdanm	92:4fc01daae5a5	241	#define RCC_HSI_OFF ((uint8_t)0x00)
bogdanm	92:4fc01daae5a5	242	#define RCC_HSI_ON ((uint8_t)0x01)
bogdanm	92:4fc01daae5a5	243
bogdanm	92:4fc01daae5a5	244	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
bogdanm	92:4fc01daae5a5	245	/**
bogdanm	92:4fc01daae5a5	246	* @}
bogdanm	92:4fc01daae5a5	247	*/
bogdanm	92:4fc01daae5a5	248
bogdanm	92:4fc01daae5a5	249	/** @defgroup RCC_LSI_Config
bogdanm	92:4fc01daae5a5	250	* @{
bogdanm	92:4fc01daae5a5	251	*/
bogdanm	92:4fc01daae5a5	252	#define RCC_LSI_OFF ((uint8_t)0x00)
bogdanm	92:4fc01daae5a5	253	#define RCC_LSI_ON ((uint8_t)0x01)
bogdanm	92:4fc01daae5a5	254
bogdanm	92:4fc01daae5a5	255	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
bogdanm	92:4fc01daae5a5	256	/**
bogdanm	92:4fc01daae5a5	257	* @}
bogdanm	92:4fc01daae5a5	258	*/
bogdanm	92:4fc01daae5a5	259
bogdanm	92:4fc01daae5a5	260	/** @defgroup RCC_PLL_Config
bogdanm	92:4fc01daae5a5	261	* @{
bogdanm	92:4fc01daae5a5	262	*/
bogdanm	92:4fc01daae5a5	263	#define RCC_PLL_NONE ((uint8_t)0x00)
bogdanm	92:4fc01daae5a5	264	#define RCC_PLL_OFF ((uint8_t)0x01)
bogdanm	92:4fc01daae5a5	265	#define RCC_PLL_ON ((uint8_t)0x02)
bogdanm	92:4fc01daae5a5	266
bogdanm	92:4fc01daae5a5	267	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
bogdanm	92:4fc01daae5a5	268	/**
bogdanm	92:4fc01daae5a5	269	* @}
bogdanm	92:4fc01daae5a5	270	*/
bogdanm	92:4fc01daae5a5	271
bogdanm	92:4fc01daae5a5	272	/** @defgroup RCC_PLLP_Clock_Divider
bogdanm	92:4fc01daae5a5	273	* @{
bogdanm	92:4fc01daae5a5	274	*/
bogdanm	92:4fc01daae5a5	275	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	276	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	277	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
bogdanm	92:4fc01daae5a5	278	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	279	/**
bogdanm	92:4fc01daae5a5	280	* @}
bogdanm	92:4fc01daae5a5	281	*/
bogdanm	92:4fc01daae5a5	282
bogdanm	92:4fc01daae5a5	283	/** @defgroup RCC_PLL_Clock_Source
bogdanm	92:4fc01daae5a5	284	* @{
bogdanm	92:4fc01daae5a5	285	*/
bogdanm	92:4fc01daae5a5	286	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
bogdanm	92:4fc01daae5a5	287	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
bogdanm	92:4fc01daae5a5	288
bogdanm	92:4fc01daae5a5	289	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	92:4fc01daae5a5	290	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	92:4fc01daae5a5	291	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
bogdanm	92:4fc01daae5a5	292	#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm	92:4fc01daae5a5	293	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) \|\| ((VALUE) == 4) \|\| ((VALUE) == 6) \|\| ((VALUE) == 8))
bogdanm	92:4fc01daae5a5	294	#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
bogdanm	92:4fc01daae5a5	295
bogdanm	92:4fc01daae5a5	296	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
bogdanm	92:4fc01daae5a5	297	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
bogdanm	92:4fc01daae5a5	298
bogdanm	92:4fc01daae5a5	299	/**
bogdanm	92:4fc01daae5a5	300	* @}
bogdanm	92:4fc01daae5a5	301	*/
bogdanm	92:4fc01daae5a5	302
bogdanm	92:4fc01daae5a5	303	/** @defgroup RCC_System_Clock_Type
bogdanm	92:4fc01daae5a5	304	* @{
bogdanm	92:4fc01daae5a5	305	*/
bogdanm	92:4fc01daae5a5	306	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	307	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	308	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	309	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	310
bogdanm	92:4fc01daae5a5	311	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
bogdanm	92:4fc01daae5a5	312	/**
bogdanm	92:4fc01daae5a5	313	* @}
bogdanm	92:4fc01daae5a5	314	*/
bogdanm	92:4fc01daae5a5	315
bogdanm	92:4fc01daae5a5	316	/** @defgroup RCC_System_Clock_Source
bogdanm	92:4fc01daae5a5	317	* @{
bogdanm	92:4fc01daae5a5	318	*/
bogdanm	92:4fc01daae5a5	319	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
bogdanm	92:4fc01daae5a5	320	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
bogdanm	92:4fc01daae5a5	321	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
bogdanm	92:4fc01daae5a5	322
bogdanm	92:4fc01daae5a5	323	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	92:4fc01daae5a5	324	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	92:4fc01daae5a5	325	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm	92:4fc01daae5a5	326	/**
bogdanm	92:4fc01daae5a5	327	* @}
bogdanm	92:4fc01daae5a5	328	*/
bogdanm	92:4fc01daae5a5	329
bogdanm	92:4fc01daae5a5	330	/** @defgroup RCC_AHB_Clock_Source
bogdanm	92:4fc01daae5a5	331	* @{
bogdanm	92:4fc01daae5a5	332	*/
bogdanm	92:4fc01daae5a5	333	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
bogdanm	92:4fc01daae5a5	334	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
bogdanm	92:4fc01daae5a5	335	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
bogdanm	92:4fc01daae5a5	336	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
bogdanm	92:4fc01daae5a5	337	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
bogdanm	92:4fc01daae5a5	338	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
bogdanm	92:4fc01daae5a5	339	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
bogdanm	92:4fc01daae5a5	340	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
bogdanm	92:4fc01daae5a5	341	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
bogdanm	92:4fc01daae5a5	342
bogdanm	92:4fc01daae5a5	343	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	344	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
bogdanm	92:4fc01daae5a5	345	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
bogdanm	92:4fc01daae5a5	346	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
bogdanm	92:4fc01daae5a5	347	((HCLK) == RCC_SYSCLK_DIV512))
bogdanm	92:4fc01daae5a5	348	/**
bogdanm	92:4fc01daae5a5	349	* @}
bogdanm	92:4fc01daae5a5	350	*/
bogdanm	92:4fc01daae5a5	351
bogdanm	92:4fc01daae5a5	352	/** @defgroup RCC_APB1_APB2_Clock_Source
bogdanm	92:4fc01daae5a5	353	* @{
bogdanm	92:4fc01daae5a5	354	*/
bogdanm	92:4fc01daae5a5	355	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
bogdanm	92:4fc01daae5a5	356	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
bogdanm	92:4fc01daae5a5	357	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
bogdanm	92:4fc01daae5a5	358	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
bogdanm	92:4fc01daae5a5	359	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
bogdanm	92:4fc01daae5a5	360
bogdanm	92:4fc01daae5a5	361	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	362	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
bogdanm	92:4fc01daae5a5	363	((PCLK) == RCC_HCLK_DIV16))
bogdanm	92:4fc01daae5a5	364	/**
bogdanm	92:4fc01daae5a5	365	* @}
bogdanm	92:4fc01daae5a5	366	*/
bogdanm	92:4fc01daae5a5	367
bogdanm	92:4fc01daae5a5	368	/** @defgroup RCC_RTC_Clock_Source
bogdanm	92:4fc01daae5a5	369	* @{
bogdanm	92:4fc01daae5a5	370	*/
bogdanm	92:4fc01daae5a5	371	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
bogdanm	92:4fc01daae5a5	372	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	373	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
bogdanm	92:4fc01daae5a5	374	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
bogdanm	92:4fc01daae5a5	375	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
bogdanm	92:4fc01daae5a5	376	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
bogdanm	92:4fc01daae5a5	377	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
bogdanm	92:4fc01daae5a5	378	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
bogdanm	92:4fc01daae5a5	379	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
bogdanm	92:4fc01daae5a5	380	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
bogdanm	92:4fc01daae5a5	381	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
bogdanm	92:4fc01daae5a5	382	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
bogdanm	92:4fc01daae5a5	383	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
bogdanm	92:4fc01daae5a5	384	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
bogdanm	92:4fc01daae5a5	385	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
bogdanm	92:4fc01daae5a5	386	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
bogdanm	92:4fc01daae5a5	387	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
bogdanm	92:4fc01daae5a5	388	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
bogdanm	92:4fc01daae5a5	389	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
bogdanm	92:4fc01daae5a5	390	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
bogdanm	92:4fc01daae5a5	391	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
bogdanm	92:4fc01daae5a5	392	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
bogdanm	92:4fc01daae5a5	393	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
bogdanm	92:4fc01daae5a5	394	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
bogdanm	92:4fc01daae5a5	395	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
bogdanm	92:4fc01daae5a5	396	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
bogdanm	92:4fc01daae5a5	397	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
bogdanm	92:4fc01daae5a5	398	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
bogdanm	92:4fc01daae5a5	399	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
bogdanm	92:4fc01daae5a5	400	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
bogdanm	92:4fc01daae5a5	401	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
bogdanm	92:4fc01daae5a5	402	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
bogdanm	92:4fc01daae5a5	403	/**
bogdanm	92:4fc01daae5a5	404	* @}
bogdanm	92:4fc01daae5a5	405	*/
bogdanm	92:4fc01daae5a5	406
bogdanm	92:4fc01daae5a5	407	/** @defgroup RCC_I2S_Clock_Source
bogdanm	92:4fc01daae5a5	408	* @{
bogdanm	92:4fc01daae5a5	409	*/
bogdanm	92:4fc01daae5a5	410	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	411	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	412	/**
bogdanm	92:4fc01daae5a5	413	* @}
bogdanm	92:4fc01daae5a5	414	*/
bogdanm	92:4fc01daae5a5	415
bogdanm	92:4fc01daae5a5	416	/** @defgroup RCC_MCO_Index
bogdanm	92:4fc01daae5a5	417	* @{
bogdanm	92:4fc01daae5a5	418	*/
bogdanm	92:4fc01daae5a5	419	#define RCC_MCO1 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	420	#define RCC_MCO2 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	421
bogdanm	92:4fc01daae5a5	422	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
bogdanm	92:4fc01daae5a5	423	/**
bogdanm	92:4fc01daae5a5	424	* @}
bogdanm	92:4fc01daae5a5	425	*/
bogdanm	92:4fc01daae5a5	426
bogdanm	92:4fc01daae5a5	427	/** @defgroup RCC_MCO1_Clock_Source
bogdanm	92:4fc01daae5a5	428	* @{
bogdanm	92:4fc01daae5a5	429	*/
bogdanm	92:4fc01daae5a5	430	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	431	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
bogdanm	92:4fc01daae5a5	432	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
bogdanm	92:4fc01daae5a5	433	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
bogdanm	92:4fc01daae5a5	434
bogdanm	92:4fc01daae5a5	435	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
bogdanm	92:4fc01daae5a5	436	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
bogdanm	92:4fc01daae5a5	437	/**
bogdanm	92:4fc01daae5a5	438	* @}
bogdanm	92:4fc01daae5a5	439	*/
bogdanm	92:4fc01daae5a5	440
bogdanm	92:4fc01daae5a5	441	/** @defgroup RCC_MCO2_Clock_Source
bogdanm	92:4fc01daae5a5	442	* @{
bogdanm	92:4fc01daae5a5	443	*/
bogdanm	92:4fc01daae5a5	444	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	445	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
bogdanm	92:4fc01daae5a5	446	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
bogdanm	92:4fc01daae5a5	447	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
bogdanm	92:4fc01daae5a5	448
bogdanm	92:4fc01daae5a5	449	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
bogdanm	92:4fc01daae5a5	450	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
bogdanm	92:4fc01daae5a5	451	/**
bogdanm	92:4fc01daae5a5	452	* @}
bogdanm	92:4fc01daae5a5	453	*/
bogdanm	92:4fc01daae5a5	454
bogdanm	92:4fc01daae5a5	455	/** @defgroup RCC_MCOx_Clock_Prescaler
bogdanm	92:4fc01daae5a5	456	* @{
bogdanm	92:4fc01daae5a5	457	*/
bogdanm	92:4fc01daae5a5	458	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	459	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
bogdanm	92:4fc01daae5a5	460	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
bogdanm	92:4fc01daae5a5	461	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
bogdanm	92:4fc01daae5a5	462	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
bogdanm	92:4fc01daae5a5	463
bogdanm	92:4fc01daae5a5	464	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
bogdanm	92:4fc01daae5a5	465	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
bogdanm	92:4fc01daae5a5	466	((DIV) == RCC_MCODIV_5))
bogdanm	92:4fc01daae5a5	467	/**
bogdanm	92:4fc01daae5a5	468	* @}
bogdanm	92:4fc01daae5a5	469	*/
bogdanm	92:4fc01daae5a5	470
bogdanm	92:4fc01daae5a5	471	/** @defgroup RCC_Interrupt
bogdanm	92:4fc01daae5a5	472	* @{
bogdanm	92:4fc01daae5a5	473	*/
bogdanm	92:4fc01daae5a5	474	#define RCC_IT_LSIRDY ((uint8_t)0x01)
bogdanm	92:4fc01daae5a5	475	#define RCC_IT_LSERDY ((uint8_t)0x02)
bogdanm	92:4fc01daae5a5	476	#define RCC_IT_HSIRDY ((uint8_t)0x04)
bogdanm	92:4fc01daae5a5	477	#define RCC_IT_HSERDY ((uint8_t)0x08)
bogdanm	92:4fc01daae5a5	478	#define RCC_IT_PLLRDY ((uint8_t)0x10)
bogdanm	92:4fc01daae5a5	479	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
bogdanm	92:4fc01daae5a5	480	#define RCC_IT_CSS ((uint8_t)0x80)
bogdanm	92:4fc01daae5a5	481	/**
bogdanm	92:4fc01daae5a5	482	* @}
bogdanm	92:4fc01daae5a5	483	*/
bogdanm	92:4fc01daae5a5	484
bogdanm	92:4fc01daae5a5	485	/** @defgroup RCC_Flag
bogdanm	92:4fc01daae5a5	486	* Elements values convention: 0XXYYYYYb
bogdanm	92:4fc01daae5a5	487	* - YYYYY : Flag position in the register
bogdanm	92:4fc01daae5a5	488	* - 0XX : Register index
bogdanm	92:4fc01daae5a5	489	* - 01: CR register
bogdanm	92:4fc01daae5a5	490	* - 10: BDCR register
bogdanm	92:4fc01daae5a5	491	* - 11: CSR register
bogdanm	92:4fc01daae5a5	492	* @{
bogdanm	92:4fc01daae5a5	493	*/
bogdanm	92:4fc01daae5a5	494	/* Flags in the CR register */
bogdanm	92:4fc01daae5a5	495	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
bogdanm	92:4fc01daae5a5	496	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
bogdanm	92:4fc01daae5a5	497	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
bogdanm	92:4fc01daae5a5	498	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
bogdanm	92:4fc01daae5a5	499
bogdanm	92:4fc01daae5a5	500	/* Flags in the BDCR register */
bogdanm	92:4fc01daae5a5	501	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
bogdanm	92:4fc01daae5a5	502
bogdanm	92:4fc01daae5a5	503	/* Flags in the CSR register */
bogdanm	92:4fc01daae5a5	504	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
bogdanm	92:4fc01daae5a5	505	#define RCC_FLAG_BORRST ((uint8_t)0x79)
bogdanm	92:4fc01daae5a5	506	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
bogdanm	92:4fc01daae5a5	507	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
bogdanm	92:4fc01daae5a5	508	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
bogdanm	92:4fc01daae5a5	509	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
bogdanm	92:4fc01daae5a5	510	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
bogdanm	92:4fc01daae5a5	511	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
bogdanm	92:4fc01daae5a5	512
bogdanm	92:4fc01daae5a5	513	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
bogdanm	92:4fc01daae5a5	514	/**
bogdanm	92:4fc01daae5a5	515	* @}
bogdanm	92:4fc01daae5a5	516	*/
bogdanm	92:4fc01daae5a5	517
bogdanm	92:4fc01daae5a5	518	/**
bogdanm	92:4fc01daae5a5	519	* @}
bogdanm	92:4fc01daae5a5	520	*/
bogdanm	92:4fc01daae5a5	521	/* Exported macro ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	522
bogdanm	92:4fc01daae5a5	523	/** @brief Enable or disable the AHB1 peripheral clock.
bogdanm	92:4fc01daae5a5	524	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	525	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	526	* using it.
bogdanm	92:4fc01daae5a5	527	*/
bogdanm	92:4fc01daae5a5	528	#define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOAEN))
bogdanm	92:4fc01daae5a5	529	#define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOBEN))
bogdanm	92:4fc01daae5a5	530	#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOCEN))
bogdanm	92:4fc01daae5a5	531	#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIODEN))
bogdanm	92:4fc01daae5a5	532	#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOEEN))
bogdanm	92:4fc01daae5a5	533	#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOHEN))
bogdanm	92:4fc01daae5a5	534	#define __CRC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CRCEN))
bogdanm	92:4fc01daae5a5	535	#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_BKPSRAMEN))
bogdanm	92:4fc01daae5a5	536	#define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CCMDATARAMEN))
bogdanm	92:4fc01daae5a5	537	#define __DMA1_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA1EN))
bogdanm	92:4fc01daae5a5	538	#define __DMA2_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA2EN))
bogdanm	92:4fc01daae5a5	539
bogdanm	92:4fc01daae5a5	540	#define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
bogdanm	92:4fc01daae5a5	541	#define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
bogdanm	92:4fc01daae5a5	542	#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
bogdanm	92:4fc01daae5a5	543	#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
bogdanm	92:4fc01daae5a5	544	#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
bogdanm	92:4fc01daae5a5	545	#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
bogdanm	92:4fc01daae5a5	546	#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
bogdanm	92:4fc01daae5a5	547	#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
bogdanm	92:4fc01daae5a5	548	#define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
bogdanm	92:4fc01daae5a5	549	#define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
bogdanm	92:4fc01daae5a5	550	#define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
bogdanm	92:4fc01daae5a5	551
bogdanm	92:4fc01daae5a5	552	/** @brief Enable or disable the AHB2 peripheral clock.
bogdanm	92:4fc01daae5a5	553	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	554	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	555	* using it.
bogdanm	92:4fc01daae5a5	556	*/
bogdanm	92:4fc01daae5a5	557	#define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
bogdanm	92:4fc01daae5a5	558	__SYSCFG_CLK_ENABLE();\
bogdanm	92:4fc01daae5a5	559	}while(0)
bogdanm	92:4fc01daae5a5	560
bogdanm	92:4fc01daae5a5	561
bogdanm	92:4fc01daae5a5	562	#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
bogdanm	92:4fc01daae5a5	563	__SYSCFG_CLK_DISABLE();\
bogdanm	92:4fc01daae5a5	564	}while(0)
bogdanm	92:4fc01daae5a5	565
bogdanm	92:4fc01daae5a5	566	#define __RNG_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_RNGEN))
bogdanm	92:4fc01daae5a5	567	#define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
bogdanm	92:4fc01daae5a5	568	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	92:4fc01daae5a5	569	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	570	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	571	* using it.
bogdanm	92:4fc01daae5a5	572	*/
bogdanm	92:4fc01daae5a5	573	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
bogdanm	92:4fc01daae5a5	574	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
bogdanm	92:4fc01daae5a5	575	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
bogdanm	92:4fc01daae5a5	576	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
bogdanm	92:4fc01daae5a5	577	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
bogdanm	92:4fc01daae5a5	578	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	92:4fc01daae5a5	579	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
bogdanm	92:4fc01daae5a5	580	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
bogdanm	92:4fc01daae5a5	581	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
bogdanm	92:4fc01daae5a5	582	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	92:4fc01daae5a5	583	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
bogdanm	92:4fc01daae5a5	584	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
bogdanm	92:4fc01daae5a5	585
bogdanm	92:4fc01daae5a5	586	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	92:4fc01daae5a5	587	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	92:4fc01daae5a5	588	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
bogdanm	92:4fc01daae5a5	589	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
bogdanm	92:4fc01daae5a5	590	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
bogdanm	92:4fc01daae5a5	591	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	92:4fc01daae5a5	592	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm	92:4fc01daae5a5	593	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	92:4fc01daae5a5	594	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
bogdanm	92:4fc01daae5a5	595	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	92:4fc01daae5a5	596	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm	92:4fc01daae5a5	597	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
bogdanm	92:4fc01daae5a5	598
bogdanm	92:4fc01daae5a5	599	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	92:4fc01daae5a5	600	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	92:4fc01daae5a5	601	* is disabled and the application software has to enable this clock before
bogdanm	92:4fc01daae5a5	602	* using it.
bogdanm	92:4fc01daae5a5	603	*/
bogdanm	92:4fc01daae5a5	604	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
bogdanm	92:4fc01daae5a5	605	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
bogdanm	92:4fc01daae5a5	606	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
bogdanm	92:4fc01daae5a5	607	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
bogdanm	92:4fc01daae5a5	608	#define __SDIO_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDIOEN))
bogdanm	92:4fc01daae5a5	609	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
bogdanm	92:4fc01daae5a5	610	#define __SPI4_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI4EN))
bogdanm	92:4fc01daae5a5	611	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
bogdanm	92:4fc01daae5a5	612	#define __TIM9_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM9EN))
bogdanm	92:4fc01daae5a5	613	#define __TIM10_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM10EN))
bogdanm	92:4fc01daae5a5	614	#define __TIM11_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM11EN))
bogdanm	92:4fc01daae5a5	615
bogdanm	92:4fc01daae5a5	616	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm	92:4fc01daae5a5	617	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
bogdanm	92:4fc01daae5a5	618	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
bogdanm	92:4fc01daae5a5	619	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm	92:4fc01daae5a5	620	#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
bogdanm	92:4fc01daae5a5	621	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	92:4fc01daae5a5	622	#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
bogdanm	92:4fc01daae5a5	623	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
bogdanm	92:4fc01daae5a5	624	#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
bogdanm	92:4fc01daae5a5	625	#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
bogdanm	92:4fc01daae5a5	626	#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
bogdanm	92:4fc01daae5a5	627
bogdanm	92:4fc01daae5a5	628	/** @brief Force or release AHB1 peripheral reset.
bogdanm	92:4fc01daae5a5	629	*/
bogdanm	92:4fc01daae5a5	630	#define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
bogdanm	92:4fc01daae5a5	631	#define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
bogdanm	92:4fc01daae5a5	632	#define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
bogdanm	92:4fc01daae5a5	633	#define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
bogdanm	92:4fc01daae5a5	634	#define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
bogdanm	92:4fc01daae5a5	635	#define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
bogdanm	92:4fc01daae5a5	636	#define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
bogdanm	92:4fc01daae5a5	637	#define __CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
bogdanm	92:4fc01daae5a5	638	#define __DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
bogdanm	92:4fc01daae5a5	639	#define __DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
bogdanm	92:4fc01daae5a5	640
bogdanm	92:4fc01daae5a5	641	#define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
bogdanm	92:4fc01daae5a5	642	#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
bogdanm	92:4fc01daae5a5	643	#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
bogdanm	92:4fc01daae5a5	644	#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
bogdanm	92:4fc01daae5a5	645	#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
bogdanm	92:4fc01daae5a5	646	#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
bogdanm	92:4fc01daae5a5	647	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
bogdanm	92:4fc01daae5a5	648	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
bogdanm	92:4fc01daae5a5	649	#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
bogdanm	92:4fc01daae5a5	650	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
bogdanm	92:4fc01daae5a5	651	#define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
bogdanm	92:4fc01daae5a5	652	#define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
bogdanm	92:4fc01daae5a5	653	#define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
bogdanm	92:4fc01daae5a5	654
bogdanm	92:4fc01daae5a5	655	/** @brief Force or release AHB2 peripheral reset.
bogdanm	92:4fc01daae5a5	656	*/
bogdanm	92:4fc01daae5a5	657	#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
bogdanm	92:4fc01daae5a5	658	#define __USB_OTG_FS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
bogdanm	92:4fc01daae5a5	659
bogdanm	92:4fc01daae5a5	660	#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
bogdanm	92:4fc01daae5a5	661	#define __USB_OTG_FS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
bogdanm	92:4fc01daae5a5	662
bogdanm	92:4fc01daae5a5	663	/* alias define maintained for legacy */
bogdanm	92:4fc01daae5a5	664	#define __OTGFS_FORCE_RESET __USB_OTG_FS_FORCE_RESET
bogdanm	92:4fc01daae5a5	665	#define __OTGFS_RELEASE_RESET __USB_OTG_FS_RELEASE_RESET
bogdanm	92:4fc01daae5a5	666
bogdanm	92:4fc01daae5a5	667	#define __RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
bogdanm	92:4fc01daae5a5	668	#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
bogdanm	92:4fc01daae5a5	669
bogdanm	92:4fc01daae5a5	670	/** @brief Force or release APB1 peripheral reset.
bogdanm	92:4fc01daae5a5	671	*/
bogdanm	92:4fc01daae5a5	672	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
bogdanm	92:4fc01daae5a5	673	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	92:4fc01daae5a5	674	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	92:4fc01daae5a5	675	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
bogdanm	92:4fc01daae5a5	676	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
bogdanm	92:4fc01daae5a5	677	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
bogdanm	92:4fc01daae5a5	678	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	92:4fc01daae5a5	679	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
bogdanm	92:4fc01daae5a5	680	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	92:4fc01daae5a5	681	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
bogdanm	92:4fc01daae5a5	682	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	92:4fc01daae5a5	683	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
bogdanm	92:4fc01daae5a5	684	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
bogdanm	92:4fc01daae5a5	685
bogdanm	92:4fc01daae5a5	686	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
bogdanm	92:4fc01daae5a5	687	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	92:4fc01daae5a5	688	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	92:4fc01daae5a5	689	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
bogdanm	92:4fc01daae5a5	690	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
bogdanm	92:4fc01daae5a5	691	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
bogdanm	92:4fc01daae5a5	692	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	92:4fc01daae5a5	693	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm	92:4fc01daae5a5	694	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm	92:4fc01daae5a5	695	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
bogdanm	92:4fc01daae5a5	696	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	92:4fc01daae5a5	697	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm	92:4fc01daae5a5	698	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
bogdanm	92:4fc01daae5a5	699
bogdanm	92:4fc01daae5a5	700	/** @brief Force or release APB2 peripheral reset.
bogdanm	92:4fc01daae5a5	701	*/
bogdanm	92:4fc01daae5a5	702	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
bogdanm	92:4fc01daae5a5	703	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
bogdanm	92:4fc01daae5a5	704	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
bogdanm	92:4fc01daae5a5	705	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
bogdanm	92:4fc01daae5a5	706	#define __ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
bogdanm	92:4fc01daae5a5	707	#define __SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
bogdanm	92:4fc01daae5a5	708	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	92:4fc01daae5a5	709	#define __SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
bogdanm	92:4fc01daae5a5	710	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
bogdanm	92:4fc01daae5a5	711	#define __TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
bogdanm	92:4fc01daae5a5	712	#define __TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
bogdanm	92:4fc01daae5a5	713	#define __TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
bogdanm	92:4fc01daae5a5	714
bogdanm	92:4fc01daae5a5	715	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
bogdanm	92:4fc01daae5a5	716	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm	92:4fc01daae5a5	717	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
bogdanm	92:4fc01daae5a5	718	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
bogdanm	92:4fc01daae5a5	719	#define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
bogdanm	92:4fc01daae5a5	720	#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
bogdanm	92:4fc01daae5a5	721	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	92:4fc01daae5a5	722	#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
bogdanm	92:4fc01daae5a5	723	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
bogdanm	92:4fc01daae5a5	724	#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
bogdanm	92:4fc01daae5a5	725	#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
bogdanm	92:4fc01daae5a5	726	#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
bogdanm	92:4fc01daae5a5	727
bogdanm	92:4fc01daae5a5	728	/** @brief Force or release AHB3 peripheral reset.
bogdanm	92:4fc01daae5a5	729	*/
bogdanm	92:4fc01daae5a5	730	#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
bogdanm	92:4fc01daae5a5	731	#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
bogdanm	92:4fc01daae5a5	732
bogdanm	92:4fc01daae5a5	733	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	734	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	735	* power consumption.
bogdanm	92:4fc01daae5a5	736	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	737	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	738	*/
bogdanm	92:4fc01daae5a5	739	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
bogdanm	92:4fc01daae5a5	740	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
bogdanm	92:4fc01daae5a5	741	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
bogdanm	92:4fc01daae5a5	742	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
bogdanm	92:4fc01daae5a5	743	#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
bogdanm	92:4fc01daae5a5	744	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
bogdanm	92:4fc01daae5a5	745	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
bogdanm	92:4fc01daae5a5	746	#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
bogdanm	92:4fc01daae5a5	747	#define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
bogdanm	92:4fc01daae5a5	748	#define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm	92:4fc01daae5a5	749	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
bogdanm	92:4fc01daae5a5	750	#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
bogdanm	92:4fc01daae5a5	751
bogdanm	92:4fc01daae5a5	752	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
bogdanm	92:4fc01daae5a5	753	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
bogdanm	92:4fc01daae5a5	754	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
bogdanm	92:4fc01daae5a5	755	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
bogdanm	92:4fc01daae5a5	756	#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
bogdanm	92:4fc01daae5a5	757	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
bogdanm	92:4fc01daae5a5	758	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
bogdanm	92:4fc01daae5a5	759	#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
bogdanm	92:4fc01daae5a5	760	#define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
bogdanm	92:4fc01daae5a5	761	#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
bogdanm	92:4fc01daae5a5	762	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
bogdanm	92:4fc01daae5a5	763	#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
bogdanm	92:4fc01daae5a5	764
bogdanm	92:4fc01daae5a5	765	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	766	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	767	* power consumption.
bogdanm	92:4fc01daae5a5	768	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	769	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	770	*/
bogdanm	92:4fc01daae5a5	771	#define __USB_OTG_FS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
bogdanm	92:4fc01daae5a5	772
bogdanm	92:4fc01daae5a5	773	#define __USB_OTG_FS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
bogdanm	92:4fc01daae5a5	774
bogdanm	92:4fc01daae5a5	775	/* alias define maintained for legacy */
bogdanm	92:4fc01daae5a5	776	#define __OTGFS_CLK_SLEEP_ENABLE __USB_OTG_FS_CLK_SLEEP_ENABLE
bogdanm	92:4fc01daae5a5	777	#define __OTGFS_CLK_SLEEP_DISABLE __USB_OTG_FS_CLK_SLEEP_DISABLE
bogdanm	92:4fc01daae5a5	778
bogdanm	92:4fc01daae5a5	779	#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
bogdanm	92:4fc01daae5a5	780	#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
bogdanm	92:4fc01daae5a5	781
bogdanm	92:4fc01daae5a5	782	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	783	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	784	* power consumption.
bogdanm	92:4fc01daae5a5	785	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	786	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	787	*/
bogdanm	92:4fc01daae5a5	788	#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
bogdanm	92:4fc01daae5a5	789	#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
bogdanm	92:4fc01daae5a5	790	#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
bogdanm	92:4fc01daae5a5	791	#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
bogdanm	92:4fc01daae5a5	792	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
bogdanm	92:4fc01daae5a5	793	#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
bogdanm	92:4fc01daae5a5	794	#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
bogdanm	92:4fc01daae5a5	795	#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
bogdanm	92:4fc01daae5a5	796	#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
bogdanm	92:4fc01daae5a5	797	#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
bogdanm	92:4fc01daae5a5	798	#define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
bogdanm	92:4fc01daae5a5	799	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
bogdanm	92:4fc01daae5a5	800
bogdanm	92:4fc01daae5a5	801	#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
bogdanm	92:4fc01daae5a5	802	#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
bogdanm	92:4fc01daae5a5	803	#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
bogdanm	92:4fc01daae5a5	804	#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
bogdanm	92:4fc01daae5a5	805	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
bogdanm	92:4fc01daae5a5	806	#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
bogdanm	92:4fc01daae5a5	807	#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
bogdanm	92:4fc01daae5a5	808	#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
bogdanm	92:4fc01daae5a5	809	#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
bogdanm	92:4fc01daae5a5	810	#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
bogdanm	92:4fc01daae5a5	811	#define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
bogdanm	92:4fc01daae5a5	812	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
bogdanm	92:4fc01daae5a5	813
bogdanm	92:4fc01daae5a5	814	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	92:4fc01daae5a5	815	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	92:4fc01daae5a5	816	* power consumption.
bogdanm	92:4fc01daae5a5	817	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	92:4fc01daae5a5	818	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	92:4fc01daae5a5	819	*/
bogdanm	92:4fc01daae5a5	820	#define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
bogdanm	92:4fc01daae5a5	821	#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
bogdanm	92:4fc01daae5a5	822	#define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
bogdanm	92:4fc01daae5a5	823	#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
bogdanm	92:4fc01daae5a5	824	#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
bogdanm	92:4fc01daae5a5	825	#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
bogdanm	92:4fc01daae5a5	826	#define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
bogdanm	92:4fc01daae5a5	827	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
bogdanm	92:4fc01daae5a5	828	#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
bogdanm	92:4fc01daae5a5	829	#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
bogdanm	92:4fc01daae5a5	830	#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
bogdanm	92:4fc01daae5a5	831
bogdanm	92:4fc01daae5a5	832	#define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
bogdanm	92:4fc01daae5a5	833	#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
bogdanm	92:4fc01daae5a5	834	#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
bogdanm	92:4fc01daae5a5	835	#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
bogdanm	92:4fc01daae5a5	836	#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
bogdanm	92:4fc01daae5a5	837	#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
bogdanm	92:4fc01daae5a5	838	#define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
bogdanm	92:4fc01daae5a5	839	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
bogdanm	92:4fc01daae5a5	840	#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
bogdanm	92:4fc01daae5a5	841	#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
bogdanm	92:4fc01daae5a5	842	#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
bogdanm	92:4fc01daae5a5	843
bogdanm	92:4fc01daae5a5	844	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
bogdanm	92:4fc01daae5a5	845	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	92:4fc01daae5a5	846	* It is used (enabled by hardware) as system clock source after startup
bogdanm	92:4fc01daae5a5	847	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
bogdanm	92:4fc01daae5a5	848	* of the HSE used directly or indirectly as system clock (if the Clock
bogdanm	92:4fc01daae5a5	849	* Security System CSS is enabled).
bogdanm	92:4fc01daae5a5	850	* @note HSI can not be stopped if it is used as system clock source. In this case,
bogdanm	92:4fc01daae5a5	851	* you have to select another source of the system clock then stop the HSI.
bogdanm	92:4fc01daae5a5	852	* @note After enabling the HSI, the application software should wait on HSIRDY
bogdanm	92:4fc01daae5a5	853	* flag to be set indicating that HSI clock is stable and can be used as
bogdanm	92:4fc01daae5a5	854	* system clock source.
bogdanm	92:4fc01daae5a5	855	* This parameter can be: ENABLE or DISABLE.
bogdanm	92:4fc01daae5a5	856	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
bogdanm	92:4fc01daae5a5	857	* clock cycles.
bogdanm	92:4fc01daae5a5	858	*/
bogdanm	92:4fc01daae5a5	859	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) CR_HSION_BB = ENABLE)
bogdanm	92:4fc01daae5a5	860	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) CR_HSION_BB = DISABLE)
bogdanm	92:4fc01daae5a5	861
bogdanm	92:4fc01daae5a5	862	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
bogdanm	92:4fc01daae5a5	863	* @note The calibration is used to compensate for the variations in voltage
bogdanm	92:4fc01daae5a5	864	* and temperature that influence the frequency of the internal HSI RC.
bogdanm	92:4fc01daae5a5	865	* @param __HSICalibrationValue__: specifies the calibration trimming value.
bogdanm	92:4fc01daae5a5	866	* This parameter must be a number between 0 and 0x1F.
bogdanm	92:4fc01daae5a5	867	*/
bogdanm	92:4fc01daae5a5	868	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
bogdanm	92:4fc01daae5a5	869	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
bogdanm	92:4fc01daae5a5	870
bogdanm	92:4fc01daae5a5	871	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
bogdanm	92:4fc01daae5a5	872	* @note After enabling the LSI, the application software should wait on
bogdanm	92:4fc01daae5a5	873	* LSIRDY flag to be set indicating that LSI clock is stable and can
bogdanm	92:4fc01daae5a5	874	* be used to clock the IWDG and/or the RTC.
bogdanm	92:4fc01daae5a5	875	* @note LSI can not be disabled if the IWDG is running.
bogdanm	92:4fc01daae5a5	876	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
bogdanm	92:4fc01daae5a5	877	* clock cycles.
bogdanm	92:4fc01daae5a5	878	*/
bogdanm	92:4fc01daae5a5	879	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) CSR_LSION_BB = ENABLE)
bogdanm	92:4fc01daae5a5	880	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) CSR_LSION_BB = DISABLE)
bogdanm	92:4fc01daae5a5	881
bogdanm	92:4fc01daae5a5	882	/**
bogdanm	92:4fc01daae5a5	883	* @brief Macro to configure the External High Speed oscillator (HSE).
bogdanm	92:4fc01daae5a5	884	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
bogdanm	92:4fc01daae5a5	885	* software should wait on HSERDY flag to be set indicating that HSE clock
bogdanm	92:4fc01daae5a5	886	* is stable and can be used to clock the PLL and/or system clock.
bogdanm	92:4fc01daae5a5	887	* @note HSE state can not be changed if it is used directly or through the
bogdanm	92:4fc01daae5a5	888	* PLL as system clock. In this case, you have to select another source
bogdanm	92:4fc01daae5a5	889	* of the system clock then change the HSE state (ex. disable it).
bogdanm	92:4fc01daae5a5	890	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	92:4fc01daae5a5	891	* @note This function reset the CSSON bit, so if the clock security system(CSS)
bogdanm	92:4fc01daae5a5	892	* was previously enabled you have to enable it again after calling this
bogdanm	92:4fc01daae5a5	893	* function.
bogdanm	92:4fc01daae5a5	894	* @param __STATE__: specifies the new state of the HSE.
bogdanm	92:4fc01daae5a5	895	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	896	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
bogdanm	92:4fc01daae5a5	897	* 6 HSE oscillator clock cycles.
bogdanm	92:4fc01daae5a5	898	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
bogdanm	92:4fc01daae5a5	899	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
bogdanm	92:4fc01daae5a5	900	*/
bogdanm	92:4fc01daae5a5	901	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) CR_BYTE2_ADDRESS = (__STATE__))
bogdanm	92:4fc01daae5a5	902
bogdanm	92:4fc01daae5a5	903	/**
bogdanm	92:4fc01daae5a5	904	* @brief Macro to configure the External Low Speed oscillator (LSE).
bogdanm	92:4fc01daae5a5	905	* @note As the LSE is in the Backup domain and write access is denied to
bogdanm	92:4fc01daae5a5	906	* this domain after reset, you have to enable write access using
bogdanm	92:4fc01daae5a5	907	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
bogdanm	92:4fc01daae5a5	908	* (to be done once after reset).
bogdanm	92:4fc01daae5a5	909	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
bogdanm	92:4fc01daae5a5	910	* software should wait on LSERDY flag to be set indicating that LSE clock
bogdanm	92:4fc01daae5a5	911	* is stable and can be used to clock the RTC.
bogdanm	92:4fc01daae5a5	912	* @param __STATE__: specifies the new state of the LSE.
bogdanm	92:4fc01daae5a5	913	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	914	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
bogdanm	92:4fc01daae5a5	915	* 6 LSE oscillator clock cycles.
bogdanm	92:4fc01daae5a5	916	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
bogdanm	92:4fc01daae5a5	917	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
bogdanm	92:4fc01daae5a5	918	*/
bogdanm	92:4fc01daae5a5	919	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) BDCR_BYTE0_ADDRESS = (__STATE__))
bogdanm	92:4fc01daae5a5	920
bogdanm	92:4fc01daae5a5	921	/** @brief Macros to enable or disable the the RTC clock.
bogdanm	92:4fc01daae5a5	922	* @note These macros must be used only after the RTC clock source was selected.
bogdanm	92:4fc01daae5a5	923	*/
bogdanm	92:4fc01daae5a5	924	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = ENABLE)
bogdanm	92:4fc01daae5a5	925	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = DISABLE)
bogdanm	92:4fc01daae5a5	926
bogdanm	92:4fc01daae5a5	927	/** @brief Macros to configure the RTC clock (RTCCLK).
bogdanm	92:4fc01daae5a5	928	* @note As the RTC clock configuration bits are in the Backup domain and write
bogdanm	92:4fc01daae5a5	929	* access is denied to this domain after reset, you have to enable write
bogdanm	92:4fc01daae5a5	930	* access using the Power Backup Access macro before to configure
bogdanm	92:4fc01daae5a5	931	* the RTC clock source (to be done once after reset).
bogdanm	92:4fc01daae5a5	932	* @note Once the RTC clock is configured it can't be changed unless the
bogdanm	92:4fc01daae5a5	933	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
bogdanm	92:4fc01daae5a5	934	* a Power On Reset (POR).
bogdanm	92:4fc01daae5a5	935	* @param __RTCCLKSource__: specifies the RTC clock source.
bogdanm	92:4fc01daae5a5	936	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	937	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
bogdanm	92:4fc01daae5a5	938	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
bogdanm	92:4fc01daae5a5	939	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
bogdanm	92:4fc01daae5a5	940	* as RTC clock, where x:[2,31]
bogdanm	92:4fc01daae5a5	941	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
bogdanm	92:4fc01daae5a5	942	* work in STOP and STANDBY modes, and can be used as wakeup source.
bogdanm	92:4fc01daae5a5	943	* However, when the HSE clock is used as RTC clock source, the RTC
bogdanm	92:4fc01daae5a5	944	* cannot be used in STOP and STANDBY modes.
bogdanm	92:4fc01daae5a5	945	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
bogdanm	92:4fc01daae5a5	946	* RTC clock source).
bogdanm	92:4fc01daae5a5	947	*/
bogdanm	92:4fc01daae5a5	948	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
bogdanm	92:4fc01daae5a5	949	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm	92:4fc01daae5a5	950
bogdanm	92:4fc01daae5a5	951	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
bogdanm	92:4fc01daae5a5	952	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
bogdanm	92:4fc01daae5a5	953	} while (0)
bogdanm	92:4fc01daae5a5	954
bogdanm	92:4fc01daae5a5	955	/** @brief Macros to force or release the Backup domain reset.
bogdanm	92:4fc01daae5a5	956	* @note This function resets the RTC peripheral (including the backup registers)
bogdanm	92:4fc01daae5a5	957	* and the RTC clock source selection in RCC_CSR register.
bogdanm	92:4fc01daae5a5	958	* @note The BKPSRAM is not affected by this reset.
bogdanm	92:4fc01daae5a5	959	*/
bogdanm	92:4fc01daae5a5	960	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) BDCR_BDRST_BB = ENABLE)
bogdanm	92:4fc01daae5a5	961	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) BDCR_BDRST_BB = DISABLE)
bogdanm	92:4fc01daae5a5	962
bogdanm	92:4fc01daae5a5	963	/** @brief Macros to enable or disable the main PLL.
bogdanm	92:4fc01daae5a5	964	* @note After enabling the main PLL, the application software should wait on
bogdanm	92:4fc01daae5a5	965	* PLLRDY flag to be set indicating that PLL clock is stable and can
bogdanm	92:4fc01daae5a5	966	* be used as system clock source.
bogdanm	92:4fc01daae5a5	967	* @note The main PLL can not be disabled if it is used as system clock source
bogdanm	92:4fc01daae5a5	968	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	92:4fc01daae5a5	969	*/
bogdanm	92:4fc01daae5a5	970	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) CR_PLLON_BB = ENABLE)
bogdanm	92:4fc01daae5a5	971	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) CR_PLLON_BB = DISABLE)
bogdanm	92:4fc01daae5a5	972
bogdanm	92:4fc01daae5a5	973	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
bogdanm	92:4fc01daae5a5	974	* @note This function must be used only when the main PLL is disabled.
bogdanm	92:4fc01daae5a5	975	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm	92:4fc01daae5a5	976	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	977	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	92:4fc01daae5a5	978	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	92:4fc01daae5a5	979	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
bogdanm	92:4fc01daae5a5	980	* @param __PLLM__: specifies the division factor for PLL VCO input clock
bogdanm	92:4fc01daae5a5	981	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
bogdanm	92:4fc01daae5a5	982	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
bogdanm	92:4fc01daae5a5	983	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
bogdanm	92:4fc01daae5a5	984	* of 2 MHz to limit PLL jitter.
bogdanm	92:4fc01daae5a5	985	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
bogdanm	92:4fc01daae5a5	986	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	92:4fc01daae5a5	987	* @note You have to set the PLLN parameter correctly to ensure that the VCO
bogdanm	92:4fc01daae5a5	988	* output frequency is between 192 and 432 MHz.
bogdanm	92:4fc01daae5a5	989	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
bogdanm	92:4fc01daae5a5	990	* This parameter must be a number in the range {2, 4, 6, or 8}.
bogdanm	92:4fc01daae5a5	991	* @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
bogdanm	92:4fc01daae5a5	992	* the System clock frequency.
bogdanm	92:4fc01daae5a5	993	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
bogdanm	92:4fc01daae5a5	994	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
bogdanm	92:4fc01daae5a5	995	* @note If the USB OTG FS is used in your application, you have to set the
bogdanm	92:4fc01daae5a5	996	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
bogdanm	92:4fc01daae5a5	997	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
bogdanm	92:4fc01daae5a5	998	* correctly.
bogdanm	92:4fc01daae5a5	999	*/
bogdanm	92:4fc01daae5a5	1000	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
bogdanm	92:4fc01daae5a5	1001	(RCC->PLLCFGR = (0x20000000 \| (__PLLM__) \| ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
bogdanm	92:4fc01daae5a5	1002	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| (__RCC_PLLSource__) \| \
bogdanm	92:4fc01daae5a5	1003	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
bogdanm	92:4fc01daae5a5	1004
bogdanm	92:4fc01daae5a5	1005	/** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm	92:4fc01daae5a5	1006	* @note This function must be called before enabling the I2S APB clock.
bogdanm	92:4fc01daae5a5	1007	* @param __SOURCE__: specifies the I2S clock source.
bogdanm	92:4fc01daae5a5	1008	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1009	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
bogdanm	92:4fc01daae5a5	1010	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm	92:4fc01daae5a5	1011	* used as I2S clock source.
bogdanm	92:4fc01daae5a5	1012	*/
bogdanm	92:4fc01daae5a5	1013	#define __HAL_RCC_I2SCLK(__SOURCE__) ((__IO uint32_t ) CFGR_I2SSRC_BB = (__SOURCE__))
bogdanm	92:4fc01daae5a5	1014
bogdanm	92:4fc01daae5a5	1015	/** @brief Macros to enable or disable the PLLI2S.
bogdanm	92:4fc01daae5a5	1016	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
bogdanm	92:4fc01daae5a5	1017	*/
bogdanm	92:4fc01daae5a5	1018	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = ENABLE)
bogdanm	92:4fc01daae5a5	1019	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = DISABLE)
bogdanm	92:4fc01daae5a5	1020
bogdanm	92:4fc01daae5a5	1021	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
bogdanm	92:4fc01daae5a5	1022	* @note This macro must be used only when the PLLI2S is disabled.
bogdanm	92:4fc01daae5a5	1023	* @note PLLI2S clock source is common with the main PLL (configured in
bogdanm	92:4fc01daae5a5	1024	* HAL_RCC_ClockConfig() API).
bogdanm	92:4fc01daae5a5	1025	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
bogdanm	92:4fc01daae5a5	1026	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
bogdanm	92:4fc01daae5a5	1027	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
bogdanm	92:4fc01daae5a5	1028	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
bogdanm	92:4fc01daae5a5	1029	* @param __PLLI2SR__: specifies the division factor for I2S clock
bogdanm	92:4fc01daae5a5	1030	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
bogdanm	92:4fc01daae5a5	1031	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
bogdanm	92:4fc01daae5a5	1032	* on the I2S clock frequency.
bogdanm	92:4fc01daae5a5	1033	*/
bogdanm	92:4fc01daae5a5	1034	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
bogdanm	92:4fc01daae5a5	1035
bogdanm	92:4fc01daae5a5	1036	/** @brief Macro to get the clock source used as system clock.
bogdanm	92:4fc01daae5a5	1037	* @retval The clock source used as system clock. The returned value can be one
bogdanm	92:4fc01daae5a5	1038	* of the following:
bogdanm	92:4fc01daae5a5	1039	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
bogdanm	92:4fc01daae5a5	1040	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
bogdanm	92:4fc01daae5a5	1041	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
bogdanm	92:4fc01daae5a5	1042	*/
bogdanm	92:4fc01daae5a5	1043	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
bogdanm	92:4fc01daae5a5	1044
bogdanm	92:4fc01daae5a5	1045	/** @brief Macro to get the oscillator used as PLL clock source.
bogdanm	92:4fc01daae5a5	1046	* @retval The oscillator used as PLL clock source. The returned value can be one
bogdanm	92:4fc01daae5a5	1047	* of the following:
bogdanm	92:4fc01daae5a5	1048	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
bogdanm	92:4fc01daae5a5	1049	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
bogdanm	92:4fc01daae5a5	1050	*/
bogdanm	92:4fc01daae5a5	1051	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
bogdanm	92:4fc01daae5a5	1052
bogdanm	92:4fc01daae5a5	1053	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
bogdanm	92:4fc01daae5a5	1054	* the selected interrupts).
bogdanm	92:4fc01daae5a5	1055	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
bogdanm	92:4fc01daae5a5	1056	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1057	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	92:4fc01daae5a5	1058	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	92:4fc01daae5a5	1059	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	92:4fc01daae5a5	1060	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	92:4fc01daae5a5	1061	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	92:4fc01daae5a5	1062	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm	92:4fc01daae5a5	1063	*/
bogdanm	92:4fc01daae5a5	1064	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1065
bogdanm	92:4fc01daae5a5	1066	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
bogdanm	92:4fc01daae5a5	1067	* the selected interrupts).
bogdanm	92:4fc01daae5a5	1068	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
bogdanm	92:4fc01daae5a5	1069	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1070	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	92:4fc01daae5a5	1071	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	92:4fc01daae5a5	1072	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	92:4fc01daae5a5	1073	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	92:4fc01daae5a5	1074	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	92:4fc01daae5a5	1075	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm	92:4fc01daae5a5	1076	*/
bogdanm	92:4fc01daae5a5	1077	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1078
bogdanm	92:4fc01daae5a5	1079	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
bogdanm	92:4fc01daae5a5	1080	* bits to clear the selected interrupt pending bits.
bogdanm	92:4fc01daae5a5	1081	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	92:4fc01daae5a5	1082	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1083	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	92:4fc01daae5a5	1084	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	92:4fc01daae5a5	1085	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	92:4fc01daae5a5	1086	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	92:4fc01daae5a5	1087	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	92:4fc01daae5a5	1088	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm	92:4fc01daae5a5	1089	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	92:4fc01daae5a5	1090	*/
bogdanm	92:4fc01daae5a5	1091	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1092
bogdanm	92:4fc01daae5a5	1093	/** @brief Check the RCC's interrupt has occurred or not.
bogdanm	92:4fc01daae5a5	1094	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
bogdanm	92:4fc01daae5a5	1095	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1096	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
bogdanm	92:4fc01daae5a5	1097	* @arg RCC_IT_LSERDY: LSE ready interrupt.
bogdanm	92:4fc01daae5a5	1098	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
bogdanm	92:4fc01daae5a5	1099	* @arg RCC_IT_HSERDY: HSE ready interrupt.
bogdanm	92:4fc01daae5a5	1100	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
bogdanm	92:4fc01daae5a5	1101	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
bogdanm	92:4fc01daae5a5	1102	* @arg RCC_IT_CSS: Clock Security System interrupt
bogdanm	92:4fc01daae5a5	1103	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
bogdanm	92:4fc01daae5a5	1104	*/
bogdanm	92:4fc01daae5a5	1105	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1106
bogdanm	92:4fc01daae5a5	1107	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
bogdanm	92:4fc01daae5a5	1108	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
bogdanm	92:4fc01daae5a5	1109	*/
bogdanm	92:4fc01daae5a5	1110	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
bogdanm	92:4fc01daae5a5	1111
bogdanm	92:4fc01daae5a5	1112	/** @brief Check RCC flag is set or not.
bogdanm	92:4fc01daae5a5	1113	* @param __FLAG__: specifies the flag to check.
bogdanm	92:4fc01daae5a5	1114	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1115	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
bogdanm	92:4fc01daae5a5	1116	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
bogdanm	92:4fc01daae5a5	1117	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
bogdanm	92:4fc01daae5a5	1118	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
bogdanm	92:4fc01daae5a5	1119	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
bogdanm	92:4fc01daae5a5	1120	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
bogdanm	92:4fc01daae5a5	1121	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
bogdanm	92:4fc01daae5a5	1122	* @arg RCC_FLAG_PINRST: Pin reset.
bogdanm	92:4fc01daae5a5	1123	* @arg RCC_FLAG_PORRST: POR/PDR reset.
bogdanm	92:4fc01daae5a5	1124	* @arg RCC_FLAG_SFTRST: Software reset.
bogdanm	92:4fc01daae5a5	1125	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
bogdanm	92:4fc01daae5a5	1126	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
bogdanm	92:4fc01daae5a5	1127	* @arg RCC_FLAG_LPWRRST: Low Power reset.
bogdanm	92:4fc01daae5a5	1128	* @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm	92:4fc01daae5a5	1129	*/
bogdanm	92:4fc01daae5a5	1130	#define RCC_FLAG_MASK ((uint8_t)0x1F)
bogdanm	92:4fc01daae5a5	1131	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
bogdanm	92:4fc01daae5a5	1132
bogdanm	92:4fc01daae5a5	1133	#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
bogdanm	92:4fc01daae5a5	1134
bogdanm	92:4fc01daae5a5	1135
bogdanm	92:4fc01daae5a5	1136	/* Include RCC HAL Extension module */
bogdanm	92:4fc01daae5a5	1137	#include "stm32f4xx_hal_rcc_ex.h"
bogdanm	92:4fc01daae5a5	1138
bogdanm	92:4fc01daae5a5	1139	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1140
bogdanm	92:4fc01daae5a5	1141	/* Initialization and de-initialization functions ******************************/
bogdanm	92:4fc01daae5a5	1142	void HAL_RCC_DeInit(void);
bogdanm	92:4fc01daae5a5	1143	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	92:4fc01daae5a5	1144	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
bogdanm	92:4fc01daae5a5	1145
bogdanm	92:4fc01daae5a5	1146	/* Peripheral Control functions ************************************************/
bogdanm	92:4fc01daae5a5	1147	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
bogdanm	92:4fc01daae5a5	1148	void HAL_RCC_EnableCSS(void);
bogdanm	92:4fc01daae5a5	1149	void HAL_RCC_DisableCSS(void);
bogdanm	92:4fc01daae5a5	1150	uint32_t HAL_RCC_GetSysClockFreq(void);
bogdanm	92:4fc01daae5a5	1151	uint32_t HAL_RCC_GetHCLKFreq(void);
bogdanm	92:4fc01daae5a5	1152	uint32_t HAL_RCC_GetPCLK1Freq(void);
bogdanm	92:4fc01daae5a5	1153	uint32_t HAL_RCC_GetPCLK2Freq(void);
bogdanm	92:4fc01daae5a5	1154	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
bogdanm	92:4fc01daae5a5	1155	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
bogdanm	92:4fc01daae5a5	1156
bogdanm	92:4fc01daae5a5	1157	/* CSS NMI IRQ handler */
bogdanm	92:4fc01daae5a5	1158	void HAL_RCC_NMI_IRQHandler(void);
bogdanm	92:4fc01daae5a5	1159
bogdanm	92:4fc01daae5a5	1160	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	92:4fc01daae5a5	1161	void HAL_RCC_CCSCallback(void);
bogdanm	92:4fc01daae5a5	1162
bogdanm	92:4fc01daae5a5	1163	/**
bogdanm	92:4fc01daae5a5	1164	* @}
bogdanm	92:4fc01daae5a5	1165	*/
bogdanm	92:4fc01daae5a5	1166
bogdanm	92:4fc01daae5a5	1167	/**
bogdanm	92:4fc01daae5a5	1168	* @}
bogdanm	92:4fc01daae5a5	1169	*/
bogdanm	92:4fc01daae5a5	1170
bogdanm	92:4fc01daae5a5	1171	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	1172	}
bogdanm	92:4fc01daae5a5	1173	#endif
bogdanm	92:4fc01daae5a5	1174
bogdanm	92:4fc01daae5a5	1175	#endif /* __STM32F4xx_HAL_RCC_H */
bogdanm	92:4fc01daae5a5	1176
bogdanm	92:4fc01daae5a5	1177	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Apr 2016
Imports:	0
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Commits:	119
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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_rcc.h@118:16969dd821af, 2016-04-05 (annotated)

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