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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_eth.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:: ricardobtez
Date:: Tue Apr 05 23:51:21 2016 +0000
Revision:: 118:16969dd821af
Parent:: 92:4fc01daae5a5
Child:: 99:dbbf35b96557

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User	Revision	Line number	New contents of line
bogdanm	92:4fc01daae5a5	1	/**
bogdanm	92:4fc01daae5a5	2	******************************************************************************
bogdanm	92:4fc01daae5a5	3	* @file stm32f4xx_hal_eth.h
bogdanm	92:4fc01daae5a5	4	* @author MCD Application Team
bogdanm	92:4fc01daae5a5	5	* @version V1.1.0
bogdanm	92:4fc01daae5a5	6	* @date 19-June-2014
bogdanm	92:4fc01daae5a5	7	* @brief Header file of ETH HAL module.
bogdanm	92:4fc01daae5a5	8	******************************************************************************
bogdanm	92:4fc01daae5a5	9	* @attention
bogdanm	92:4fc01daae5a5	10	*
bogdanm	92:4fc01daae5a5	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	92:4fc01daae5a5	12	*
bogdanm	92:4fc01daae5a5	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	92:4fc01daae5a5	14	* are permitted provided that the following conditions are met:
bogdanm	92:4fc01daae5a5	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	92:4fc01daae5a5	16	* this list of conditions and the following disclaimer.
bogdanm	92:4fc01daae5a5	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	92:4fc01daae5a5	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	92:4fc01daae5a5	19	* and/or other materials provided with the distribution.
bogdanm	92:4fc01daae5a5	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	92:4fc01daae5a5	21	* may be used to endorse or promote products derived from this software
bogdanm	92:4fc01daae5a5	22	* without specific prior written permission.
bogdanm	92:4fc01daae5a5	23	*
bogdanm	92:4fc01daae5a5	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	92:4fc01daae5a5	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	92:4fc01daae5a5	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	92:4fc01daae5a5	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	92:4fc01daae5a5	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	92:4fc01daae5a5	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	92:4fc01daae5a5	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	92:4fc01daae5a5	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	92:4fc01daae5a5	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	92:4fc01daae5a5	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	92:4fc01daae5a5	34	*
bogdanm	92:4fc01daae5a5	35	******************************************************************************
bogdanm	92:4fc01daae5a5	36	*/
bogdanm	92:4fc01daae5a5	37
bogdanm	92:4fc01daae5a5	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	92:4fc01daae5a5	39	#ifndef __STM32F4xx_HAL_ETH_H
bogdanm	92:4fc01daae5a5	40	#define __STM32F4xx_HAL_ETH_H
bogdanm	92:4fc01daae5a5	41
bogdanm	92:4fc01daae5a5	42	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	43	extern "C" {
bogdanm	92:4fc01daae5a5	44	#endif
bogdanm	92:4fc01daae5a5	45
bogdanm	92:4fc01daae5a5	46	#if defined(STM32F407xx) \|\| defined(STM32F417xx) \|\| defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
bogdanm	92:4fc01daae5a5	47	/* Includes ------------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	48	#include "stm32f4xx_hal_def.h"
bogdanm	92:4fc01daae5a5	49
bogdanm	92:4fc01daae5a5	50	/** @addtogroup STM32F4xx_HAL_Driver
bogdanm	92:4fc01daae5a5	51	* @{
bogdanm	92:4fc01daae5a5	52	*/
bogdanm	92:4fc01daae5a5	53
bogdanm	92:4fc01daae5a5	54	/** @addtogroup ETH
bogdanm	92:4fc01daae5a5	55	* @{
bogdanm	92:4fc01daae5a5	56	*/
bogdanm	92:4fc01daae5a5	57
bogdanm	92:4fc01daae5a5	58	/* Exported types ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	59
bogdanm	92:4fc01daae5a5	60	/**
bogdanm	92:4fc01daae5a5	61	* @brief HAL State structures definition
bogdanm	92:4fc01daae5a5	62	*/
bogdanm	92:4fc01daae5a5	63	typedef enum
bogdanm	92:4fc01daae5a5	64	{
bogdanm	92:4fc01daae5a5	65	HAL_ETH_STATE_RESET = 0x00, /!< Peripheral not yet Initialized or disabled /
bogdanm	92:4fc01daae5a5	66	HAL_ETH_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	92:4fc01daae5a5	67	HAL_ETH_STATE_BUSY = 0x02, /!< an internal process is ongoing /
bogdanm	92:4fc01daae5a5	68	HAL_ETH_STATE_BUSY_TX = 0x12, /!< Data Transmission process is ongoing /
bogdanm	92:4fc01daae5a5	69	HAL_ETH_STATE_BUSY_RX = 0x22, /!< Data Reception process is ongoing /
bogdanm	92:4fc01daae5a5	70	HAL_ETH_STATE_BUSY_TX_RX = 0x32, /!< Data Transmission and Reception process is ongoing /
bogdanm	92:4fc01daae5a5	71	HAL_ETH_STATE_BUSY_WR = 0x42, /!< Write process is ongoing /
bogdanm	92:4fc01daae5a5	72	HAL_ETH_STATE_BUSY_RD = 0x82, /!< Read process is ongoing /
bogdanm	92:4fc01daae5a5	73	HAL_ETH_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	92:4fc01daae5a5	74	HAL_ETH_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	92:4fc01daae5a5	75	}HAL_ETH_StateTypeDef;
bogdanm	92:4fc01daae5a5	76
bogdanm	92:4fc01daae5a5	77	/**
bogdanm	92:4fc01daae5a5	78	* @brief ETH Init Structure definition
bogdanm	92:4fc01daae5a5	79	*/
bogdanm	92:4fc01daae5a5	80
bogdanm	92:4fc01daae5a5	81	typedef struct
bogdanm	92:4fc01daae5a5	82	{
bogdanm	92:4fc01daae5a5	83	uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
bogdanm	92:4fc01daae5a5	84	The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
bogdanm	92:4fc01daae5a5	85	and the mode (half/full-duplex).
bogdanm	92:4fc01daae5a5	86	This parameter can be a value of @ref ETH_AutoNegotiation */
bogdanm	92:4fc01daae5a5	87
bogdanm	92:4fc01daae5a5	88	uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
bogdanm	92:4fc01daae5a5	89	This parameter can be a value of @ref ETH_Speed */
bogdanm	92:4fc01daae5a5	90
bogdanm	92:4fc01daae5a5	91	uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
bogdanm	92:4fc01daae5a5	92	This parameter can be a value of @ref ETH_Duplex_Mode */
bogdanm	92:4fc01daae5a5	93
bogdanm	92:4fc01daae5a5	94	uint16_t PhyAddress; /*!< Ethernet PHY address.
bogdanm	92:4fc01daae5a5	95	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
bogdanm	92:4fc01daae5a5	96
bogdanm	92:4fc01daae5a5	97	uint8_t MACAddr; /!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
bogdanm	92:4fc01daae5a5	98
bogdanm	92:4fc01daae5a5	99	uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
bogdanm	92:4fc01daae5a5	100	This parameter can be a value of @ref ETH_Rx_Mode */
bogdanm	92:4fc01daae5a5	101
bogdanm	92:4fc01daae5a5	102	uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
bogdanm	92:4fc01daae5a5	103	This parameter can be a value of @ref ETH_Checksum_Mode */
bogdanm	92:4fc01daae5a5	104
bogdanm	92:4fc01daae5a5	105	uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
bogdanm	92:4fc01daae5a5	106	This parameter can be a value of @ref ETH_Media_Interface */
bogdanm	92:4fc01daae5a5	107
bogdanm	92:4fc01daae5a5	108	} ETH_InitTypeDef;
bogdanm	92:4fc01daae5a5	109
bogdanm	92:4fc01daae5a5	110
bogdanm	92:4fc01daae5a5	111	/**
bogdanm	92:4fc01daae5a5	112	* @brief ETH MAC Configuration Structure definition
bogdanm	92:4fc01daae5a5	113	*/
bogdanm	92:4fc01daae5a5	114
bogdanm	92:4fc01daae5a5	115	typedef struct
bogdanm	92:4fc01daae5a5	116	{
bogdanm	92:4fc01daae5a5	117	uint32_t Watchdog; /*!< Selects or not the Watchdog timer
bogdanm	92:4fc01daae5a5	118	When enabled, the MAC allows no more then 2048 bytes to be received.
bogdanm	92:4fc01daae5a5	119	When disabled, the MAC can receive up to 16384 bytes.
bogdanm	92:4fc01daae5a5	120	This parameter can be a value of @ref ETH_watchdog */
bogdanm	92:4fc01daae5a5	121
bogdanm	92:4fc01daae5a5	122	uint32_t Jabber; /*!< Selects or not Jabber timer
bogdanm	92:4fc01daae5a5	123	When enabled, the MAC allows no more then 2048 bytes to be sent.
bogdanm	92:4fc01daae5a5	124	When disabled, the MAC can send up to 16384 bytes.
bogdanm	92:4fc01daae5a5	125	This parameter can be a value of @ref ETH_Jabber */
bogdanm	92:4fc01daae5a5	126
bogdanm	92:4fc01daae5a5	127	uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
bogdanm	92:4fc01daae5a5	128	This parameter can be a value of @ref ETH_Inter_Frame_Gap */
bogdanm	92:4fc01daae5a5	129
bogdanm	92:4fc01daae5a5	130	uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
bogdanm	92:4fc01daae5a5	131	This parameter can be a value of @ref ETH_Carrier_Sense */
bogdanm	92:4fc01daae5a5	132
bogdanm	92:4fc01daae5a5	133	uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
bogdanm	92:4fc01daae5a5	134	ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
bogdanm	92:4fc01daae5a5	135	in Half-Duplex mode.
bogdanm	92:4fc01daae5a5	136	This parameter can be a value of @ref ETH_Receive_Own */
bogdanm	92:4fc01daae5a5	137
bogdanm	92:4fc01daae5a5	138	uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
bogdanm	92:4fc01daae5a5	139	This parameter can be a value of @ref ETH_Loop_Back_Mode */
bogdanm	92:4fc01daae5a5	140
bogdanm	92:4fc01daae5a5	141	uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
bogdanm	92:4fc01daae5a5	142	This parameter can be a value of @ref ETH_Checksum_Offload */
bogdanm	92:4fc01daae5a5	143
bogdanm	92:4fc01daae5a5	144	uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
bogdanm	92:4fc01daae5a5	145	when a collision occurs (Half-Duplex mode).
bogdanm	92:4fc01daae5a5	146	This parameter can be a value of @ref ETH_Retry_Transmission */
bogdanm	92:4fc01daae5a5	147
bogdanm	92:4fc01daae5a5	148	uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
bogdanm	92:4fc01daae5a5	149	This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
bogdanm	92:4fc01daae5a5	150
bogdanm	92:4fc01daae5a5	151	uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
bogdanm	92:4fc01daae5a5	152	This parameter can be a value of @ref ETH_Back_Off_Limit */
bogdanm	92:4fc01daae5a5	153
bogdanm	92:4fc01daae5a5	154	uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
bogdanm	92:4fc01daae5a5	155	This parameter can be a value of @ref ETH_Deferral_Check */
bogdanm	92:4fc01daae5a5	156
bogdanm	92:4fc01daae5a5	157	uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
bogdanm	92:4fc01daae5a5	158	This parameter can be a value of @ref ETH_Receive_All */
bogdanm	92:4fc01daae5a5	159
bogdanm	92:4fc01daae5a5	160	uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
bogdanm	92:4fc01daae5a5	161	This parameter can be a value of @ref ETH_Source_Addr_Filter */
bogdanm	92:4fc01daae5a5	162
bogdanm	92:4fc01daae5a5	163	uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
bogdanm	92:4fc01daae5a5	164	This parameter can be a value of @ref ETH_Pass_Control_Frames */
bogdanm	92:4fc01daae5a5	165
bogdanm	92:4fc01daae5a5	166	uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
bogdanm	92:4fc01daae5a5	167	This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
bogdanm	92:4fc01daae5a5	168
bogdanm	92:4fc01daae5a5	169	uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
bogdanm	92:4fc01daae5a5	170	This parameter can be a value of @ref ETH_Destination_Addr_Filter */
bogdanm	92:4fc01daae5a5	171
bogdanm	92:4fc01daae5a5	172	uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
bogdanm	92:4fc01daae5a5	173	This parameter can be a value of @ref ETH_Promiscuous_Mode */
bogdanm	92:4fc01daae5a5	174
bogdanm	92:4fc01daae5a5	175	uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
bogdanm	92:4fc01daae5a5	176	This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
bogdanm	92:4fc01daae5a5	177
bogdanm	92:4fc01daae5a5	178	uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
bogdanm	92:4fc01daae5a5	179	This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
bogdanm	92:4fc01daae5a5	180
bogdanm	92:4fc01daae5a5	181	uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
bogdanm	92:4fc01daae5a5	182	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
bogdanm	92:4fc01daae5a5	183
bogdanm	92:4fc01daae5a5	184	uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
bogdanm	92:4fc01daae5a5	185	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
bogdanm	92:4fc01daae5a5	186
bogdanm	92:4fc01daae5a5	187	uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
bogdanm	92:4fc01daae5a5	188	This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
bogdanm	92:4fc01daae5a5	189
bogdanm	92:4fc01daae5a5	190	uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
bogdanm	92:4fc01daae5a5	191	This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
bogdanm	92:4fc01daae5a5	192
bogdanm	92:4fc01daae5a5	193	uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
bogdanm	92:4fc01daae5a5	194	automatic retransmission of PAUSE Frame.
bogdanm	92:4fc01daae5a5	195	This parameter can be a value of @ref ETH_Pause_Low_Threshold */
bogdanm	92:4fc01daae5a5	196
bogdanm	92:4fc01daae5a5	197	uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
bogdanm	92:4fc01daae5a5	198	unicast address and unique multicast address).
bogdanm	92:4fc01daae5a5	199	This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
bogdanm	92:4fc01daae5a5	200
bogdanm	92:4fc01daae5a5	201	uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
bogdanm	92:4fc01daae5a5	202	disable its transmitter for a specified time (Pause Time)
bogdanm	92:4fc01daae5a5	203	This parameter can be a value of @ref ETH_Receive_Flow_Control */
bogdanm	92:4fc01daae5a5	204
bogdanm	92:4fc01daae5a5	205	uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
bogdanm	92:4fc01daae5a5	206	or the MAC back-pressure operation (Half-Duplex mode)
bogdanm	92:4fc01daae5a5	207	This parameter can be a value of @ref ETH_Transmit_Flow_Control */
bogdanm	92:4fc01daae5a5	208
bogdanm	92:4fc01daae5a5	209	uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
bogdanm	92:4fc01daae5a5	210	comparison and filtering.
bogdanm	92:4fc01daae5a5	211	This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
bogdanm	92:4fc01daae5a5	212
bogdanm	92:4fc01daae5a5	213	uint32_t VLANTagIdentifier; /!< Holds the VLAN tag identifier for receive frames /
bogdanm	92:4fc01daae5a5	214
bogdanm	92:4fc01daae5a5	215	} ETH_MACInitTypeDef;
bogdanm	92:4fc01daae5a5	216
bogdanm	92:4fc01daae5a5	217
bogdanm	92:4fc01daae5a5	218	/**
bogdanm	92:4fc01daae5a5	219	* @brief ETH DMA Configuration Structure definition
bogdanm	92:4fc01daae5a5	220	*/
bogdanm	92:4fc01daae5a5	221
bogdanm	92:4fc01daae5a5	222	typedef struct
bogdanm	92:4fc01daae5a5	223	{
bogdanm	92:4fc01daae5a5	224	uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
bogdanm	92:4fc01daae5a5	225	This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
bogdanm	92:4fc01daae5a5	226
bogdanm	92:4fc01daae5a5	227	uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
bogdanm	92:4fc01daae5a5	228	This parameter can be a value of @ref ETH_Receive_Store_Forward */
bogdanm	92:4fc01daae5a5	229
bogdanm	92:4fc01daae5a5	230	uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
bogdanm	92:4fc01daae5a5	231	This parameter can be a value of @ref ETH_Flush_Received_Frame */
bogdanm	92:4fc01daae5a5	232
bogdanm	92:4fc01daae5a5	233	uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
bogdanm	92:4fc01daae5a5	234	This parameter can be a value of @ref ETH_Transmit_Store_Forward */
bogdanm	92:4fc01daae5a5	235
bogdanm	92:4fc01daae5a5	236	uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
bogdanm	92:4fc01daae5a5	237	This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
bogdanm	92:4fc01daae5a5	238
bogdanm	92:4fc01daae5a5	239	uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
bogdanm	92:4fc01daae5a5	240	This parameter can be a value of @ref ETH_Forward_Error_Frames */
bogdanm	92:4fc01daae5a5	241
bogdanm	92:4fc01daae5a5	242	uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
bogdanm	92:4fc01daae5a5	243	and length less than 64 bytes) including pad-bytes and CRC)
bogdanm	92:4fc01daae5a5	244	This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
bogdanm	92:4fc01daae5a5	245
bogdanm	92:4fc01daae5a5	246	uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
bogdanm	92:4fc01daae5a5	247	This parameter can be a value of @ref ETH_Receive_Threshold_Control */
bogdanm	92:4fc01daae5a5	248
bogdanm	92:4fc01daae5a5	249	uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
bogdanm	92:4fc01daae5a5	250	frame of Transmit data even before obtaining the status for the first frame.
bogdanm	92:4fc01daae5a5	251	This parameter can be a value of @ref ETH_Second_Frame_Operate */
bogdanm	92:4fc01daae5a5	252
bogdanm	92:4fc01daae5a5	253	uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
bogdanm	92:4fc01daae5a5	254	This parameter can be a value of @ref ETH_Address_Aligned_Beats */
bogdanm	92:4fc01daae5a5	255
bogdanm	92:4fc01daae5a5	256	uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
bogdanm	92:4fc01daae5a5	257	This parameter can be a value of @ref ETH_Fixed_Burst */
bogdanm	92:4fc01daae5a5	258
bogdanm	92:4fc01daae5a5	259	uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
bogdanm	92:4fc01daae5a5	260	This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
bogdanm	92:4fc01daae5a5	261
bogdanm	92:4fc01daae5a5	262	uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
bogdanm	92:4fc01daae5a5	263	This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
bogdanm	92:4fc01daae5a5	264
bogdanm	92:4fc01daae5a5	265	uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
bogdanm	92:4fc01daae5a5	266	This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
bogdanm	92:4fc01daae5a5	267
bogdanm	92:4fc01daae5a5	268	uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
bogdanm	92:4fc01daae5a5	269	This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
bogdanm	92:4fc01daae5a5	270
bogdanm	92:4fc01daae5a5	271	uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
bogdanm	92:4fc01daae5a5	272	This parameter can be a value of @ref ETH_DMA_Arbitration */
bogdanm	92:4fc01daae5a5	273	} ETH_DMAInitTypeDef;
bogdanm	92:4fc01daae5a5	274
bogdanm	92:4fc01daae5a5	275
bogdanm	92:4fc01daae5a5	276	/**
bogdanm	92:4fc01daae5a5	277	* @brief ETH DMA Descriptors data structure definition
bogdanm	92:4fc01daae5a5	278	*/
bogdanm	92:4fc01daae5a5	279
bogdanm	92:4fc01daae5a5	280	typedef struct
bogdanm	92:4fc01daae5a5	281	{
bogdanm	92:4fc01daae5a5	282	__IO uint32_t Status; /!< Status /
bogdanm	92:4fc01daae5a5	283
bogdanm	92:4fc01daae5a5	284	uint32_t ControlBufferSize; /!< Control and Buffer1, Buffer2 lengths /
bogdanm	92:4fc01daae5a5	285
bogdanm	92:4fc01daae5a5	286	uint32_t Buffer1Addr; /!< Buffer1 address pointer /
bogdanm	92:4fc01daae5a5	287
bogdanm	92:4fc01daae5a5	288	uint32_t Buffer2NextDescAddr; /!< Buffer2 or next descriptor address pointer /
bogdanm	92:4fc01daae5a5	289
bogdanm	92:4fc01daae5a5	290	/!< Enhanced ETHERNET DMA PTP Descriptors /
bogdanm	92:4fc01daae5a5	291	uint32_t ExtendedStatus; /!< Extended status for PTP receive descriptor /
bogdanm	92:4fc01daae5a5	292
bogdanm	92:4fc01daae5a5	293	uint32_t Reserved1; /!< Reserved /
bogdanm	92:4fc01daae5a5	294
bogdanm	92:4fc01daae5a5	295	uint32_t TimeStampLow; /!< Time Stamp Low value for transmit and receive /
bogdanm	92:4fc01daae5a5	296
bogdanm	92:4fc01daae5a5	297	uint32_t TimeStampHigh; /!< Time Stamp High value for transmit and receive /
bogdanm	92:4fc01daae5a5	298
bogdanm	92:4fc01daae5a5	299	} ETH_DMADescTypeDef;
bogdanm	92:4fc01daae5a5	300
bogdanm	92:4fc01daae5a5	301
bogdanm	92:4fc01daae5a5	302	/**
bogdanm	92:4fc01daae5a5	303	* @brief Received Frame Informations structure definition
bogdanm	92:4fc01daae5a5	304	*/
bogdanm	92:4fc01daae5a5	305	typedef struct
bogdanm	92:4fc01daae5a5	306	{
bogdanm	92:4fc01daae5a5	307	ETH_DMADescTypeDef FSRxDesc; /!< First Segment Rx Desc */
bogdanm	92:4fc01daae5a5	308
bogdanm	92:4fc01daae5a5	309	ETH_DMADescTypeDef LSRxDesc; /!< Last Segment Rx Desc */
bogdanm	92:4fc01daae5a5	310
bogdanm	92:4fc01daae5a5	311	uint32_t SegCount; /!< Segment count /
bogdanm	92:4fc01daae5a5	312
bogdanm	92:4fc01daae5a5	313	uint32_t length; /!< Frame length /
bogdanm	92:4fc01daae5a5	314
bogdanm	92:4fc01daae5a5	315	uint32_t buffer; /!< Frame buffer /
bogdanm	92:4fc01daae5a5	316
bogdanm	92:4fc01daae5a5	317	} ETH_DMARxFrameInfos;
bogdanm	92:4fc01daae5a5	318
bogdanm	92:4fc01daae5a5	319
bogdanm	92:4fc01daae5a5	320	/**
bogdanm	92:4fc01daae5a5	321	* @brief ETH Handle Structure definition
bogdanm	92:4fc01daae5a5	322	*/
bogdanm	92:4fc01daae5a5	323
bogdanm	92:4fc01daae5a5	324	typedef struct
bogdanm	92:4fc01daae5a5	325	{
bogdanm	92:4fc01daae5a5	326	ETH_TypeDef Instance; /!< Register base address */
bogdanm	92:4fc01daae5a5	327
bogdanm	92:4fc01daae5a5	328	ETH_InitTypeDef Init; /!< Ethernet Init Configuration /
bogdanm	92:4fc01daae5a5	329
bogdanm	92:4fc01daae5a5	330	uint32_t LinkStatus; /!< Ethernet link status /
bogdanm	92:4fc01daae5a5	331
bogdanm	92:4fc01daae5a5	332	ETH_DMADescTypeDef RxDesc; /!< Rx descriptor to Get */
bogdanm	92:4fc01daae5a5	333
bogdanm	92:4fc01daae5a5	334	ETH_DMADescTypeDef TxDesc; /!< Tx descriptor to Set */
bogdanm	92:4fc01daae5a5	335
bogdanm	92:4fc01daae5a5	336	ETH_DMARxFrameInfos RxFrameInfos; /!< last Rx frame infos /
bogdanm	92:4fc01daae5a5	337
bogdanm	92:4fc01daae5a5	338	__IO HAL_ETH_StateTypeDef State; /!< ETH communication state /
bogdanm	92:4fc01daae5a5	339
bogdanm	92:4fc01daae5a5	340	HAL_LockTypeDef Lock; /!< ETH Lock /
bogdanm	92:4fc01daae5a5	341
bogdanm	92:4fc01daae5a5	342	} ETH_HandleTypeDef;
bogdanm	92:4fc01daae5a5	343
bogdanm	92:4fc01daae5a5	344	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	345
bogdanm	92:4fc01daae5a5	346	#define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
bogdanm	92:4fc01daae5a5	347
bogdanm	92:4fc01daae5a5	348	/* Delay to wait when writing to some Ethernet registers */
bogdanm	92:4fc01daae5a5	349	#define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	350
bogdanm	92:4fc01daae5a5	351
bogdanm	92:4fc01daae5a5	352	/* ETHERNET Errors */
bogdanm	92:4fc01daae5a5	353	#define ETH_SUCCESS ((uint32_t)0)
bogdanm	92:4fc01daae5a5	354	#define ETH_ERROR ((uint32_t)1)
bogdanm	92:4fc01daae5a5	355
bogdanm	92:4fc01daae5a5	356	/** @defgroup ETH_Buffers_setting
bogdanm	92:4fc01daae5a5	357	* @{
bogdanm	92:4fc01daae5a5	358	*/
bogdanm	92:4fc01daae5a5	359	#define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /!< ETH_HEADER + ETH_EXTRA + VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC /
bogdanm	92:4fc01daae5a5	360	#define ETH_HEADER ((uint32_t)14) /!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type /
bogdanm	92:4fc01daae5a5	361	#define ETH_CRC ((uint32_t)4) /!< Ethernet CRC /
bogdanm	92:4fc01daae5a5	362	#define ETH_EXTRA ((uint32_t)2) /!< Extra bytes in some cases /
bogdanm	92:4fc01daae5a5	363	#define VLAN_TAG ((uint32_t)4) /!< optional 802.1q VLAN Tag /
bogdanm	92:4fc01daae5a5	364	#define MIN_ETH_PAYLOAD ((uint32_t)46) /!< Minimum Ethernet payload size /
bogdanm	92:4fc01daae5a5	365	#define MAX_ETH_PAYLOAD ((uint32_t)1500) /!< Maximum Ethernet payload size /
bogdanm	92:4fc01daae5a5	366	#define JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /!< Jumbo frame payload size /
bogdanm	92:4fc01daae5a5	367
bogdanm	92:4fc01daae5a5	368	/* Ethernet driver receive buffers are organized in a chained linked-list, when
bogdanm	92:4fc01daae5a5	369	an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
bogdanm	92:4fc01daae5a5	370	to the driver receive buffers memory.
bogdanm	92:4fc01daae5a5	371
bogdanm	92:4fc01daae5a5	372	Depending on the size of the received ethernet packet and the size of
bogdanm	92:4fc01daae5a5	373	each ethernet driver receive buffer, the received packet can take one or more
bogdanm	92:4fc01daae5a5	374	ethernet driver receive buffer.
bogdanm	92:4fc01daae5a5	375
bogdanm	92:4fc01daae5a5	376	In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
bogdanm	92:4fc01daae5a5	377	and the total count of the driver receive buffers ETH_RXBUFNB.
bogdanm	92:4fc01daae5a5	378
bogdanm	92:4fc01daae5a5	379	The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
bogdanm	92:4fc01daae5a5	380	example, they can be reconfigured in the application layer to fit the application
bogdanm	92:4fc01daae5a5	381	needs */
bogdanm	92:4fc01daae5a5	382
bogdanm	92:4fc01daae5a5	383	/* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
bogdanm	92:4fc01daae5a5	384	packet */
bogdanm	92:4fc01daae5a5	385	#ifndef ETH_RX_BUF_SIZE
bogdanm	92:4fc01daae5a5	386	#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
bogdanm	92:4fc01daae5a5	387	#endif
bogdanm	92:4fc01daae5a5	388
bogdanm	92:4fc01daae5a5	389	/* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
bogdanm	92:4fc01daae5a5	390	#ifndef ETH_RXBUFNB
bogdanm	92:4fc01daae5a5	391	#define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
bogdanm	92:4fc01daae5a5	392	#endif
bogdanm	92:4fc01daae5a5	393
bogdanm	92:4fc01daae5a5	394
bogdanm	92:4fc01daae5a5	395	/* Ethernet driver transmit buffers are organized in a chained linked-list, when
bogdanm	92:4fc01daae5a5	396	an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
bogdanm	92:4fc01daae5a5	397	driver transmit buffers memory to the TxFIFO.
bogdanm	92:4fc01daae5a5	398
bogdanm	92:4fc01daae5a5	399	Depending on the size of the Ethernet packet to be transmitted and the size of
bogdanm	92:4fc01daae5a5	400	each ethernet driver transmit buffer, the packet to be transmitted can take
bogdanm	92:4fc01daae5a5	401	one or more ethernet driver transmit buffer.
bogdanm	92:4fc01daae5a5	402
bogdanm	92:4fc01daae5a5	403	In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
bogdanm	92:4fc01daae5a5	404	and the total count of the driver transmit buffers ETH_TXBUFNB.
bogdanm	92:4fc01daae5a5	405
bogdanm	92:4fc01daae5a5	406	The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
bogdanm	92:4fc01daae5a5	407	example, they can be reconfigured in the application layer to fit the application
bogdanm	92:4fc01daae5a5	408	needs */
bogdanm	92:4fc01daae5a5	409
bogdanm	92:4fc01daae5a5	410	/* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
bogdanm	92:4fc01daae5a5	411	packet */
bogdanm	92:4fc01daae5a5	412	#ifndef ETH_TX_BUF_SIZE
bogdanm	92:4fc01daae5a5	413	#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
bogdanm	92:4fc01daae5a5	414	#endif
bogdanm	92:4fc01daae5a5	415
bogdanm	92:4fc01daae5a5	416	/* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
bogdanm	92:4fc01daae5a5	417	#ifndef ETH_TXBUFNB
bogdanm	92:4fc01daae5a5	418	#define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
bogdanm	92:4fc01daae5a5	419	#endif
bogdanm	92:4fc01daae5a5	420
bogdanm	92:4fc01daae5a5	421
bogdanm	92:4fc01daae5a5	422	/*
bogdanm	92:4fc01daae5a5	423	DMA Tx Desciptor
bogdanm	92:4fc01daae5a5	424	-----------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	425	TDES0 \| OWN(31) \| CTRL[30:26] \| Reserved[25:24] \| CTRL[23:20] \| Reserved[19:17] \| Status[16:0] \|
bogdanm	92:4fc01daae5a5	426	-----------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	427	TDES1 \| Reserved[31:29] \| Buffer2 ByteCount[28:16] \| Reserved[15:13] \| Buffer1 ByteCount[12:0] \|
bogdanm	92:4fc01daae5a5	428	-----------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	429	TDES2 \| Buffer1 Address [31:0] \|
bogdanm	92:4fc01daae5a5	430	-----------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	431	TDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
bogdanm	92:4fc01daae5a5	432	-----------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	433	*/
bogdanm	92:4fc01daae5a5	434
bogdanm	92:4fc01daae5a5	435	/**
bogdanm	92:4fc01daae5a5	436	* @brief Bit definition of TDES0 register: DMA Tx descriptor status register
bogdanm	92:4fc01daae5a5	437	*/
bogdanm	92:4fc01daae5a5	438	#define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
bogdanm	92:4fc01daae5a5	439	#define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /!< Interrupt on Completion /
bogdanm	92:4fc01daae5a5	440	#define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /!< Last Segment /
bogdanm	92:4fc01daae5a5	441	#define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /!< First Segment /
bogdanm	92:4fc01daae5a5	442	#define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /!< Disable CRC /
bogdanm	92:4fc01daae5a5	443	#define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /!< Disable Padding /
bogdanm	92:4fc01daae5a5	444	#define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /!< Transmit Time Stamp Enable /
bogdanm	92:4fc01daae5a5	445	#define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /!< Checksum Insertion Control: 4 cases /
bogdanm	92:4fc01daae5a5	446	#define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /!< Do Nothing: Checksum Engine is bypassed /
bogdanm	92:4fc01daae5a5	447	#define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /!< IPV4 header Checksum Insertion /
bogdanm	92:4fc01daae5a5	448	#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP Checksum Insertion calculated over segment only /
bogdanm	92:4fc01daae5a5	449	#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP Checksum Insertion fully calculated /
bogdanm	92:4fc01daae5a5	450	#define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /!< Transmit End of Ring /
bogdanm	92:4fc01daae5a5	451	#define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /!< Second Address Chained /
bogdanm	92:4fc01daae5a5	452	#define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /!< Tx Time Stamp Status /
bogdanm	92:4fc01daae5a5	453	#define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /!< IP Header Error /
bogdanm	92:4fc01daae5a5	454	#define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: UE \|\| ED \|\| EC \|\| LCO \|\| NC \|\| LCA \|\| FF \|\| JT /
bogdanm	92:4fc01daae5a5	455	#define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /!< Jabber Timeout /
bogdanm	92:4fc01daae5a5	456	#define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /!< Frame Flushed: DMA/MTL flushed the frame due to SW flush /
bogdanm	92:4fc01daae5a5	457	#define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /!< Payload Checksum Error /
bogdanm	92:4fc01daae5a5	458	#define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /!< Loss of Carrier: carrier lost during transmission /
bogdanm	92:4fc01daae5a5	459	#define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /!< No Carrier: no carrier signal from the transceiver /
bogdanm	92:4fc01daae5a5	460	#define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /!< Late Collision: transmission aborted due to collision /
bogdanm	92:4fc01daae5a5	461	#define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /!< Excessive Collision: transmission aborted after 16 collisions /
bogdanm	92:4fc01daae5a5	462	#define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /!< VLAN Frame /
bogdanm	92:4fc01daae5a5	463	#define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /!< Collision Count /
bogdanm	92:4fc01daae5a5	464	#define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /!< Excessive Deferral /
bogdanm	92:4fc01daae5a5	465	#define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /!< Underflow Error: late data arrival from the memory /
bogdanm	92:4fc01daae5a5	466	#define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /!< Deferred Bit /
bogdanm	92:4fc01daae5a5	467
bogdanm	92:4fc01daae5a5	468	/**
bogdanm	92:4fc01daae5a5	469	* @brief Bit definition of TDES1 register
bogdanm	92:4fc01daae5a5	470	*/
bogdanm	92:4fc01daae5a5	471	#define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /!< Transmit Buffer2 Size /
bogdanm	92:4fc01daae5a5	472	#define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /!< Transmit Buffer1 Size /
bogdanm	92:4fc01daae5a5	473
bogdanm	92:4fc01daae5a5	474	/**
bogdanm	92:4fc01daae5a5	475	* @brief Bit definition of TDES2 register
bogdanm	92:4fc01daae5a5	476	*/
bogdanm	92:4fc01daae5a5	477	#define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
bogdanm	92:4fc01daae5a5	478
bogdanm	92:4fc01daae5a5	479	/**
bogdanm	92:4fc01daae5a5	480	* @brief Bit definition of TDES3 register
bogdanm	92:4fc01daae5a5	481	*/
bogdanm	92:4fc01daae5a5	482	#define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
bogdanm	92:4fc01daae5a5	483
bogdanm	92:4fc01daae5a5	484	/*---------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	485	TDES6 \| Transmit Time Stamp Low [31:0] \|
bogdanm	92:4fc01daae5a5	486	-----------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	487	TDES7 \| Transmit Time Stamp High [31:0] \|
bogdanm	92:4fc01daae5a5	488	----------------------------------------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	489
bogdanm	92:4fc01daae5a5	490	/* Bit definition of TDES6 register */
bogdanm	92:4fc01daae5a5	491	#define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
bogdanm	92:4fc01daae5a5	492
bogdanm	92:4fc01daae5a5	493	/* Bit definition of TDES7 register */
bogdanm	92:4fc01daae5a5	494	#define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
bogdanm	92:4fc01daae5a5	495
bogdanm	92:4fc01daae5a5	496	/**
bogdanm	92:4fc01daae5a5	497	* @}
bogdanm	92:4fc01daae5a5	498	*/
bogdanm	92:4fc01daae5a5	499
bogdanm	92:4fc01daae5a5	500
bogdanm	92:4fc01daae5a5	501	/** @defgroup ETH_DMA_Rx_descriptor
bogdanm	92:4fc01daae5a5	502	* @{
bogdanm	92:4fc01daae5a5	503	*/
bogdanm	92:4fc01daae5a5	504
bogdanm	92:4fc01daae5a5	505	/*
bogdanm	92:4fc01daae5a5	506	DMA Rx Descriptor
bogdanm	92:4fc01daae5a5	507	--------------------------------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	508	RDES0 \| OWN(31) \| Status [30:0] \|
bogdanm	92:4fc01daae5a5	509	---------------------------------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	510	RDES1 \| CTRL(31) \| Reserved[30:29] \| Buffer2 ByteCount[28:16] \| CTRL[15:14] \| Reserved(13) \| Buffer1 ByteCount[12:0] \|
bogdanm	92:4fc01daae5a5	511	---------------------------------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	512	RDES2 \| Buffer1 Address [31:0] \|
bogdanm	92:4fc01daae5a5	513	---------------------------------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	514	RDES3 \| Buffer2 Address [31:0] / Next Descriptor Address [31:0] \|
bogdanm	92:4fc01daae5a5	515	---------------------------------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	516	*/
bogdanm	92:4fc01daae5a5	517
bogdanm	92:4fc01daae5a5	518	/**
bogdanm	92:4fc01daae5a5	519	* @brief Bit definition of RDES0 register: DMA Rx descriptor status register
bogdanm	92:4fc01daae5a5	520	*/
bogdanm	92:4fc01daae5a5	521	#define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /!< OWN bit: descriptor is owned by DMA engine /
bogdanm	92:4fc01daae5a5	522	#define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /!< DA Filter Fail for the rx frame /
bogdanm	92:4fc01daae5a5	523	#define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /!< Receive descriptor frame length /
bogdanm	92:4fc01daae5a5	524	#define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /!< Error summary: OR of the following bits: DE \|\| OE \|\| IPC \|\| LC \|\| RWT \|\| RE \|\| CE /
bogdanm	92:4fc01daae5a5	525	#define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /!< Descriptor error: no more descriptors for receive frame /
bogdanm	92:4fc01daae5a5	526	#define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /!< SA Filter Fail for the received frame /
bogdanm	92:4fc01daae5a5	527	#define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /!< Frame size not matching with length field /
bogdanm	92:4fc01daae5a5	528	#define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /!< Overflow Error: Frame was damaged due to buffer overflow /
bogdanm	92:4fc01daae5a5	529	#define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /!< VLAN Tag: received frame is a VLAN frame /
bogdanm	92:4fc01daae5a5	530	#define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /!< First descriptor of the frame /
bogdanm	92:4fc01daae5a5	531	#define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /!< Last descriptor of the frame /
bogdanm	92:4fc01daae5a5	532	#define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /!< IPC Checksum Error: Rx Ipv4 header checksum error /
bogdanm	92:4fc01daae5a5	533	#define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /!< Late collision occurred during reception /
bogdanm	92:4fc01daae5a5	534	#define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /!< Frame type - Ethernet, otherwise 802.3 /
bogdanm	92:4fc01daae5a5	535	#define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /!< Receive Watchdog Timeout: watchdog timer expired during reception /
bogdanm	92:4fc01daae5a5	536	#define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /!< Receive error: error reported by MII interface /
bogdanm	92:4fc01daae5a5	537	#define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /!< Dribble bit error: frame contains non int multiple of 8 bits /
bogdanm	92:4fc01daae5a5	538	#define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /!< CRC error /
bogdanm	92:4fc01daae5a5	539	#define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error /
bogdanm	92:4fc01daae5a5	540
bogdanm	92:4fc01daae5a5	541	/**
bogdanm	92:4fc01daae5a5	542	* @brief Bit definition of RDES1 register
bogdanm	92:4fc01daae5a5	543	*/
bogdanm	92:4fc01daae5a5	544	#define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /!< Disable Interrupt on Completion /
bogdanm	92:4fc01daae5a5	545	#define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /!< Receive Buffer2 Size /
bogdanm	92:4fc01daae5a5	546	#define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /!< Receive End of Ring /
bogdanm	92:4fc01daae5a5	547	#define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /!< Second Address Chained /
bogdanm	92:4fc01daae5a5	548	#define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /!< Receive Buffer1 Size /
bogdanm	92:4fc01daae5a5	549
bogdanm	92:4fc01daae5a5	550	/**
bogdanm	92:4fc01daae5a5	551	* @brief Bit definition of RDES2 register
bogdanm	92:4fc01daae5a5	552	*/
bogdanm	92:4fc01daae5a5	553	#define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /!< Buffer1 Address Pointer /
bogdanm	92:4fc01daae5a5	554
bogdanm	92:4fc01daae5a5	555	/**
bogdanm	92:4fc01daae5a5	556	* @brief Bit definition of RDES3 register
bogdanm	92:4fc01daae5a5	557	*/
bogdanm	92:4fc01daae5a5	558	#define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /!< Buffer2 Address Pointer /
bogdanm	92:4fc01daae5a5	559
bogdanm	92:4fc01daae5a5	560	/*---------------------------------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	561	RDES4 \| Reserved[31:15] \| Extended Status [14:0] \|
bogdanm	92:4fc01daae5a5	562	---------------------------------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	563	RDES5 \| Reserved[31:0] \|
bogdanm	92:4fc01daae5a5	564	---------------------------------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	565	RDES6 \| Receive Time Stamp Low [31:0] \|
bogdanm	92:4fc01daae5a5	566	---------------------------------------------------------------------------------------------------------------------
bogdanm	92:4fc01daae5a5	567	RDES7 \| Receive Time Stamp High [31:0] \|
bogdanm	92:4fc01daae5a5	568	--------------------------------------------------------------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	569
bogdanm	92:4fc01daae5a5	570	/* Bit definition of RDES4 register */
bogdanm	92:4fc01daae5a5	571	#define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
bogdanm	92:4fc01daae5a5	572	#define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
bogdanm	92:4fc01daae5a5	573	#define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
bogdanm	92:4fc01daae5a5	574	#define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
bogdanm	92:4fc01daae5a5	575	#define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
bogdanm	92:4fc01daae5a5	576	#define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
bogdanm	92:4fc01daae5a5	577	#define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
bogdanm	92:4fc01daae5a5	578	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
bogdanm	92:4fc01daae5a5	579	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
bogdanm	92:4fc01daae5a5	580	#define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
bogdanm	92:4fc01daae5a5	581	#define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
bogdanm	92:4fc01daae5a5	582	#define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
bogdanm	92:4fc01daae5a5	583	#define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
bogdanm	92:4fc01daae5a5	584	#define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
bogdanm	92:4fc01daae5a5	585	#define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
bogdanm	92:4fc01daae5a5	586	#define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
bogdanm	92:4fc01daae5a5	587	#define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
bogdanm	92:4fc01daae5a5	588	#define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
bogdanm	92:4fc01daae5a5	589	#define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
bogdanm	92:4fc01daae5a5	590
bogdanm	92:4fc01daae5a5	591	/* Bit definition of RDES6 register */
bogdanm	92:4fc01daae5a5	592	#define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
bogdanm	92:4fc01daae5a5	593
bogdanm	92:4fc01daae5a5	594	/* Bit definition of RDES7 register */
bogdanm	92:4fc01daae5a5	595	#define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
bogdanm	92:4fc01daae5a5	596
bogdanm	92:4fc01daae5a5	597
bogdanm	92:4fc01daae5a5	598	/** @defgroup ETH_AutoNegotiation
bogdanm	92:4fc01daae5a5	599	* @{
bogdanm	92:4fc01daae5a5	600	*/
bogdanm	92:4fc01daae5a5	601	#define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	602	#define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	603	#define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	604	((CMD) == ETH_AUTONEGOTIATION_DISABLE))
bogdanm	92:4fc01daae5a5	605	/**
bogdanm	92:4fc01daae5a5	606	* @}
bogdanm	92:4fc01daae5a5	607	*/
bogdanm	92:4fc01daae5a5	608	/** @defgroup ETH_Speed
bogdanm	92:4fc01daae5a5	609	* @{
bogdanm	92:4fc01daae5a5	610	*/
bogdanm	92:4fc01daae5a5	611	#define ETH_SPEED_10M ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	612	#define ETH_SPEED_100M ((uint32_t)0x00004000)
bogdanm	92:4fc01daae5a5	613	#define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) \|\| \
bogdanm	92:4fc01daae5a5	614	((SPEED) == ETH_SPEED_100M))
bogdanm	92:4fc01daae5a5	615	/**
bogdanm	92:4fc01daae5a5	616	* @}
bogdanm	92:4fc01daae5a5	617	*/
bogdanm	92:4fc01daae5a5	618	/** @defgroup ETH_Duplex_Mode
bogdanm	92:4fc01daae5a5	619	* @{
bogdanm	92:4fc01daae5a5	620	*/
bogdanm	92:4fc01daae5a5	621	#define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
bogdanm	92:4fc01daae5a5	622	#define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	623	#define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) \|\| \
bogdanm	92:4fc01daae5a5	624	((MODE) == ETH_MODE_HALFDUPLEX))
bogdanm	92:4fc01daae5a5	625	/**
bogdanm	92:4fc01daae5a5	626	* @}
bogdanm	92:4fc01daae5a5	627	*/
bogdanm	92:4fc01daae5a5	628	/** @defgroup ETH_Rx_Mode
bogdanm	92:4fc01daae5a5	629	* @{
bogdanm	92:4fc01daae5a5	630	*/
bogdanm	92:4fc01daae5a5	631	#define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	632	#define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	633	#define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) \|\| \
bogdanm	92:4fc01daae5a5	634	((MODE) == ETH_RXINTERRUPT_MODE))
bogdanm	92:4fc01daae5a5	635	/**
bogdanm	92:4fc01daae5a5	636	* @}
bogdanm	92:4fc01daae5a5	637	*/
bogdanm	92:4fc01daae5a5	638
bogdanm	92:4fc01daae5a5	639	/** @defgroup ETH_Checksum_Mode
bogdanm	92:4fc01daae5a5	640	* @{
bogdanm	92:4fc01daae5a5	641	*/
bogdanm	92:4fc01daae5a5	642	#define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	643	#define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	644	#define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) \|\| \
bogdanm	92:4fc01daae5a5	645	((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
bogdanm	92:4fc01daae5a5	646	/**
bogdanm	92:4fc01daae5a5	647	* @}
bogdanm	92:4fc01daae5a5	648	*/
bogdanm	92:4fc01daae5a5	649
bogdanm	92:4fc01daae5a5	650	/** @defgroup ETH_Media_Interface
bogdanm	92:4fc01daae5a5	651	* @{
bogdanm	92:4fc01daae5a5	652	*/
bogdanm	92:4fc01daae5a5	653	#define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	654	#define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
bogdanm	92:4fc01daae5a5	655	#define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) \|\| \
bogdanm	92:4fc01daae5a5	656	((MODE) == ETH_MEDIA_INTERFACE_RMII))
bogdanm	92:4fc01daae5a5	657
bogdanm	92:4fc01daae5a5	658	/**
bogdanm	92:4fc01daae5a5	659	* @}
bogdanm	92:4fc01daae5a5	660	*/
bogdanm	92:4fc01daae5a5	661
bogdanm	92:4fc01daae5a5	662	/** @defgroup ETH_watchdog
bogdanm	92:4fc01daae5a5	663	* @{
bogdanm	92:4fc01daae5a5	664	*/
bogdanm	92:4fc01daae5a5	665	#define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	666	#define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
bogdanm	92:4fc01daae5a5	667	#define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	668	((CMD) == ETH_WATCHDOG_DISABLE))
bogdanm	92:4fc01daae5a5	669
bogdanm	92:4fc01daae5a5	670	/**
bogdanm	92:4fc01daae5a5	671	* @}
bogdanm	92:4fc01daae5a5	672	*/
bogdanm	92:4fc01daae5a5	673
bogdanm	92:4fc01daae5a5	674	/** @defgroup ETH_Jabber
bogdanm	92:4fc01daae5a5	675	* @{
bogdanm	92:4fc01daae5a5	676	*/
bogdanm	92:4fc01daae5a5	677	#define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	678	#define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
bogdanm	92:4fc01daae5a5	679	#define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	680	((CMD) == ETH_JABBER_DISABLE))
bogdanm	92:4fc01daae5a5	681
bogdanm	92:4fc01daae5a5	682	/**
bogdanm	92:4fc01daae5a5	683	* @}
bogdanm	92:4fc01daae5a5	684	*/
bogdanm	92:4fc01daae5a5	685
bogdanm	92:4fc01daae5a5	686	/** @defgroup ETH_Inter_Frame_Gap
bogdanm	92:4fc01daae5a5	687	* @{
bogdanm	92:4fc01daae5a5	688	*/
bogdanm	92:4fc01daae5a5	689	#define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /!< minimum IFG between frames during transmission is 96Bit /
bogdanm	92:4fc01daae5a5	690	#define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /!< minimum IFG between frames during transmission is 88Bit /
bogdanm	92:4fc01daae5a5	691	#define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /!< minimum IFG between frames during transmission is 80Bit /
bogdanm	92:4fc01daae5a5	692	#define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /!< minimum IFG between frames during transmission is 72Bit /
bogdanm	92:4fc01daae5a5	693	#define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /!< minimum IFG between frames during transmission is 64Bit /
bogdanm	92:4fc01daae5a5	694	#define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /!< minimum IFG between frames during transmission is 56Bit /
bogdanm	92:4fc01daae5a5	695	#define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /!< minimum IFG between frames during transmission is 48Bit /
bogdanm	92:4fc01daae5a5	696	#define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /!< minimum IFG between frames during transmission is 40Bit /
bogdanm	92:4fc01daae5a5	697	#define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) \|\| \
bogdanm	92:4fc01daae5a5	698	((GAP) == ETH_INTERFRAMEGAP_88BIT) \|\| \
bogdanm	92:4fc01daae5a5	699	((GAP) == ETH_INTERFRAMEGAP_80BIT) \|\| \
bogdanm	92:4fc01daae5a5	700	((GAP) == ETH_INTERFRAMEGAP_72BIT) \|\| \
bogdanm	92:4fc01daae5a5	701	((GAP) == ETH_INTERFRAMEGAP_64BIT) \|\| \
bogdanm	92:4fc01daae5a5	702	((GAP) == ETH_INTERFRAMEGAP_56BIT) \|\| \
bogdanm	92:4fc01daae5a5	703	((GAP) == ETH_INTERFRAMEGAP_48BIT) \|\| \
bogdanm	92:4fc01daae5a5	704	((GAP) == ETH_INTERFRAMEGAP_40BIT))
bogdanm	92:4fc01daae5a5	705
bogdanm	92:4fc01daae5a5	706	/**
bogdanm	92:4fc01daae5a5	707	* @}
bogdanm	92:4fc01daae5a5	708	*/
bogdanm	92:4fc01daae5a5	709
bogdanm	92:4fc01daae5a5	710	/** @defgroup ETH_Carrier_Sense
bogdanm	92:4fc01daae5a5	711	* @{
bogdanm	92:4fc01daae5a5	712	*/
bogdanm	92:4fc01daae5a5	713	#define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	714	#define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	715	#define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	716	((CMD) == ETH_CARRIERSENCE_DISABLE))
bogdanm	92:4fc01daae5a5	717
bogdanm	92:4fc01daae5a5	718	/**
bogdanm	92:4fc01daae5a5	719	* @}
bogdanm	92:4fc01daae5a5	720	*/
bogdanm	92:4fc01daae5a5	721
bogdanm	92:4fc01daae5a5	722	/** @defgroup ETH_Receive_Own
bogdanm	92:4fc01daae5a5	723	* @{
bogdanm	92:4fc01daae5a5	724	*/
bogdanm	92:4fc01daae5a5	725	#define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	726	#define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
bogdanm	92:4fc01daae5a5	727	#define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	728	((CMD) == ETH_RECEIVEOWN_DISABLE))
bogdanm	92:4fc01daae5a5	729
bogdanm	92:4fc01daae5a5	730	/**
bogdanm	92:4fc01daae5a5	731	* @}
bogdanm	92:4fc01daae5a5	732	*/
bogdanm	92:4fc01daae5a5	733
bogdanm	92:4fc01daae5a5	734	/** @defgroup ETH_Loop_Back_Mode
bogdanm	92:4fc01daae5a5	735	* @{
bogdanm	92:4fc01daae5a5	736	*/
bogdanm	92:4fc01daae5a5	737	#define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
bogdanm	92:4fc01daae5a5	738	#define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	739	#define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	740	((CMD) == ETH_LOOPBACKMODE_DISABLE))
bogdanm	92:4fc01daae5a5	741
bogdanm	92:4fc01daae5a5	742	/**
bogdanm	92:4fc01daae5a5	743	* @}
bogdanm	92:4fc01daae5a5	744	*/
bogdanm	92:4fc01daae5a5	745
bogdanm	92:4fc01daae5a5	746	/** @defgroup ETH_Checksum_Offload
bogdanm	92:4fc01daae5a5	747	* @{
bogdanm	92:4fc01daae5a5	748	*/
bogdanm	92:4fc01daae5a5	749	#define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
bogdanm	92:4fc01daae5a5	750	#define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	751	#define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	752	((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
bogdanm	92:4fc01daae5a5	753
bogdanm	92:4fc01daae5a5	754	/**
bogdanm	92:4fc01daae5a5	755	* @}
bogdanm	92:4fc01daae5a5	756	*/
bogdanm	92:4fc01daae5a5	757
bogdanm	92:4fc01daae5a5	758	/** @defgroup ETH_Retry_Transmission
bogdanm	92:4fc01daae5a5	759	* @{
bogdanm	92:4fc01daae5a5	760	*/
bogdanm	92:4fc01daae5a5	761	#define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	762	#define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	763	#define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	764	((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
bogdanm	92:4fc01daae5a5	765
bogdanm	92:4fc01daae5a5	766	/**
bogdanm	92:4fc01daae5a5	767	* @}
bogdanm	92:4fc01daae5a5	768	*/
bogdanm	92:4fc01daae5a5	769
bogdanm	92:4fc01daae5a5	770	/** @defgroup ETH_Automatic_Pad_CRC_Strip
bogdanm	92:4fc01daae5a5	771	* @{
bogdanm	92:4fc01daae5a5	772	*/
bogdanm	92:4fc01daae5a5	773	#define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
bogdanm	92:4fc01daae5a5	774	#define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	775	#define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	776	((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
bogdanm	92:4fc01daae5a5	777
bogdanm	92:4fc01daae5a5	778	/**
bogdanm	92:4fc01daae5a5	779	* @}
bogdanm	92:4fc01daae5a5	780	*/
bogdanm	92:4fc01daae5a5	781
bogdanm	92:4fc01daae5a5	782	/** @defgroup ETH_Back_Off_Limit
bogdanm	92:4fc01daae5a5	783	* @{
bogdanm	92:4fc01daae5a5	784	*/
bogdanm	92:4fc01daae5a5	785	#define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	786	#define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	787	#define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	788	#define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
bogdanm	92:4fc01daae5a5	789	#define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) \|\| \
bogdanm	92:4fc01daae5a5	790	((LIMIT) == ETH_BACKOFFLIMIT_8) \|\| \
bogdanm	92:4fc01daae5a5	791	((LIMIT) == ETH_BACKOFFLIMIT_4) \|\| \
bogdanm	92:4fc01daae5a5	792	((LIMIT) == ETH_BACKOFFLIMIT_1))
bogdanm	92:4fc01daae5a5	793
bogdanm	92:4fc01daae5a5	794	/**
bogdanm	92:4fc01daae5a5	795	* @}
bogdanm	92:4fc01daae5a5	796	*/
bogdanm	92:4fc01daae5a5	797
bogdanm	92:4fc01daae5a5	798	/** @defgroup ETH_Deferral_Check
bogdanm	92:4fc01daae5a5	799	* @{
bogdanm	92:4fc01daae5a5	800	*/
bogdanm	92:4fc01daae5a5	801	#define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	802	#define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	803	#define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	804	((CMD) == ETH_DEFFERRALCHECK_DISABLE))
bogdanm	92:4fc01daae5a5	805
bogdanm	92:4fc01daae5a5	806	/**
bogdanm	92:4fc01daae5a5	807	* @}
bogdanm	92:4fc01daae5a5	808	*/
bogdanm	92:4fc01daae5a5	809
bogdanm	92:4fc01daae5a5	810	/** @defgroup ETH_Receive_All
bogdanm	92:4fc01daae5a5	811	* @{
bogdanm	92:4fc01daae5a5	812	*/
bogdanm	92:4fc01daae5a5	813	#define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
bogdanm	92:4fc01daae5a5	814	#define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	815	#define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	816	((CMD) == ETH_RECEIVEAll_DISABLE))
bogdanm	92:4fc01daae5a5	817
bogdanm	92:4fc01daae5a5	818	/**
bogdanm	92:4fc01daae5a5	819	* @}
bogdanm	92:4fc01daae5a5	820	*/
bogdanm	92:4fc01daae5a5	821
bogdanm	92:4fc01daae5a5	822	/** @defgroup ETH_Source_Addr_Filter
bogdanm	92:4fc01daae5a5	823	* @{
bogdanm	92:4fc01daae5a5	824	*/
bogdanm	92:4fc01daae5a5	825	#define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	826	#define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
bogdanm	92:4fc01daae5a5	827	#define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	828	#define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	829	((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	830	((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
bogdanm	92:4fc01daae5a5	831
bogdanm	92:4fc01daae5a5	832	/**
bogdanm	92:4fc01daae5a5	833	* @}
bogdanm	92:4fc01daae5a5	834	*/
bogdanm	92:4fc01daae5a5	835
bogdanm	92:4fc01daae5a5	836	/** @defgroup ETH_Pass_Control_Frames
bogdanm	92:4fc01daae5a5	837	* @{
bogdanm	92:4fc01daae5a5	838	*/
bogdanm	92:4fc01daae5a5	839	#define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /!< MAC filters all control frames from reaching the application /
bogdanm	92:4fc01daae5a5	840	#define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /!< MAC forwards all control frames to application even if they fail the Address Filter /
bogdanm	92:4fc01daae5a5	841	#define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /!< MAC forwards control frames that pass the Address Filter. /
bogdanm	92:4fc01daae5a5	842	#define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) \|\| \
bogdanm	92:4fc01daae5a5	843	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) \|\| \
bogdanm	92:4fc01daae5a5	844	((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
bogdanm	92:4fc01daae5a5	845
bogdanm	92:4fc01daae5a5	846	/**
bogdanm	92:4fc01daae5a5	847	* @}
bogdanm	92:4fc01daae5a5	848	*/
bogdanm	92:4fc01daae5a5	849
bogdanm	92:4fc01daae5a5	850	/** @defgroup ETH_Broadcast_Frames_Reception
bogdanm	92:4fc01daae5a5	851	* @{
bogdanm	92:4fc01daae5a5	852	*/
bogdanm	92:4fc01daae5a5	853	#define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	854	#define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	855	#define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	856	((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
bogdanm	92:4fc01daae5a5	857
bogdanm	92:4fc01daae5a5	858	/**
bogdanm	92:4fc01daae5a5	859	* @}
bogdanm	92:4fc01daae5a5	860	*/
bogdanm	92:4fc01daae5a5	861
bogdanm	92:4fc01daae5a5	862	/** @defgroup ETH_Destination_Addr_Filter
bogdanm	92:4fc01daae5a5	863	* @{
bogdanm	92:4fc01daae5a5	864	*/
bogdanm	92:4fc01daae5a5	865	#define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	866	#define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	867	#define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) \|\| \
bogdanm	92:4fc01daae5a5	868	((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
bogdanm	92:4fc01daae5a5	869
bogdanm	92:4fc01daae5a5	870	/**
bogdanm	92:4fc01daae5a5	871	* @}
bogdanm	92:4fc01daae5a5	872	*/
bogdanm	92:4fc01daae5a5	873
bogdanm	92:4fc01daae5a5	874	/** @defgroup ETH_Promiscuous_Mode
bogdanm	92:4fc01daae5a5	875	* @{
bogdanm	92:4fc01daae5a5	876	*/
bogdanm	92:4fc01daae5a5	877	#define ETH_PROMISCIOUSMODE_ENABLE ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	878	#define ETH_PROMISCIOUSMODE_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	879	#define IS_ETH_PROMISCIOUS_MODE(CMD) (((CMD) == ETH_PROMISCIOUSMODE_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	880	((CMD) == ETH_PROMISCIOUSMODE_DISABLE))
bogdanm	92:4fc01daae5a5	881
bogdanm	92:4fc01daae5a5	882	/**
bogdanm	92:4fc01daae5a5	883	* @}
bogdanm	92:4fc01daae5a5	884	*/
bogdanm	92:4fc01daae5a5	885
bogdanm	92:4fc01daae5a5	886	/** @defgroup ETH_Multicast_Frames_Filter
bogdanm	92:4fc01daae5a5	887	* @{
bogdanm	92:4fc01daae5a5	888	*/
bogdanm	92:4fc01daae5a5	889	#define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
bogdanm	92:4fc01daae5a5	890	#define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	891	#define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	892	#define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	893	#define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
bogdanm	92:4fc01daae5a5	894	((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) \|\| \
bogdanm	92:4fc01daae5a5	895	((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) \|\| \
bogdanm	92:4fc01daae5a5	896	((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
bogdanm	92:4fc01daae5a5	897	/**
bogdanm	92:4fc01daae5a5	898	* @}
bogdanm	92:4fc01daae5a5	899	*/
bogdanm	92:4fc01daae5a5	900
bogdanm	92:4fc01daae5a5	901	/** @defgroup ETH_Unicast_Frames_Filter
bogdanm	92:4fc01daae5a5	902	* @{
bogdanm	92:4fc01daae5a5	903	*/
bogdanm	92:4fc01daae5a5	904	#define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
bogdanm	92:4fc01daae5a5	905	#define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	906	#define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	907	#define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) \|\| \
bogdanm	92:4fc01daae5a5	908	((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) \|\| \
bogdanm	92:4fc01daae5a5	909	((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
bogdanm	92:4fc01daae5a5	910	/**
bogdanm	92:4fc01daae5a5	911	* @}
bogdanm	92:4fc01daae5a5	912	*/
bogdanm	92:4fc01daae5a5	913
bogdanm	92:4fc01daae5a5	914	/** @defgroup ETH_Pause_Time
bogdanm	92:4fc01daae5a5	915	* @{
bogdanm	92:4fc01daae5a5	916	*/
bogdanm	92:4fc01daae5a5	917	#define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
bogdanm	92:4fc01daae5a5	918
bogdanm	92:4fc01daae5a5	919	/**
bogdanm	92:4fc01daae5a5	920	* @}
bogdanm	92:4fc01daae5a5	921	*/
bogdanm	92:4fc01daae5a5	922
bogdanm	92:4fc01daae5a5	923	/** @defgroup ETH_Zero_Quanta_Pause
bogdanm	92:4fc01daae5a5	924	* @{
bogdanm	92:4fc01daae5a5	925	*/
bogdanm	92:4fc01daae5a5	926	#define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	927	#define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
bogdanm	92:4fc01daae5a5	928	#define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	929	((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
bogdanm	92:4fc01daae5a5	930	/**
bogdanm	92:4fc01daae5a5	931	* @}
bogdanm	92:4fc01daae5a5	932	*/
bogdanm	92:4fc01daae5a5	933
bogdanm	92:4fc01daae5a5	934	/** @defgroup ETH_Pause_Low_Threshold
bogdanm	92:4fc01daae5a5	935	* @{
bogdanm	92:4fc01daae5a5	936	*/
bogdanm	92:4fc01daae5a5	937	#define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /!< Pause time minus 4 slot times /
bogdanm	92:4fc01daae5a5	938	#define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /!< Pause time minus 28 slot times /
bogdanm	92:4fc01daae5a5	939	#define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /!< Pause time minus 144 slot times /
bogdanm	92:4fc01daae5a5	940	#define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /!< Pause time minus 256 slot times /
bogdanm	92:4fc01daae5a5	941	#define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) \|\| \
bogdanm	92:4fc01daae5a5	942	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) \|\| \
bogdanm	92:4fc01daae5a5	943	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) \|\| \
bogdanm	92:4fc01daae5a5	944	((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
bogdanm	92:4fc01daae5a5	945	/**
bogdanm	92:4fc01daae5a5	946	* @}
bogdanm	92:4fc01daae5a5	947	*/
bogdanm	92:4fc01daae5a5	948
bogdanm	92:4fc01daae5a5	949	/** @defgroup ETH_Unicast_Pause_Frame_Detect
bogdanm	92:4fc01daae5a5	950	* @{
bogdanm	92:4fc01daae5a5	951	*/
bogdanm	92:4fc01daae5a5	952	#define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	953	#define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	954	#define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	955	((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
bogdanm	92:4fc01daae5a5	956	/**
bogdanm	92:4fc01daae5a5	957	* @}
bogdanm	92:4fc01daae5a5	958	*/
bogdanm	92:4fc01daae5a5	959
bogdanm	92:4fc01daae5a5	960	/** @defgroup ETH_Receive_Flow_Control
bogdanm	92:4fc01daae5a5	961	* @{
bogdanm	92:4fc01daae5a5	962	*/
bogdanm	92:4fc01daae5a5	963	#define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	964	#define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	965	#define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	966	((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
bogdanm	92:4fc01daae5a5	967	/**
bogdanm	92:4fc01daae5a5	968	* @}
bogdanm	92:4fc01daae5a5	969	*/
bogdanm	92:4fc01daae5a5	970
bogdanm	92:4fc01daae5a5	971	/** @defgroup ETH_Transmit_Flow_Control
bogdanm	92:4fc01daae5a5	972	* @{
bogdanm	92:4fc01daae5a5	973	*/
bogdanm	92:4fc01daae5a5	974	#define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	975	#define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	976	#define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	977	((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
bogdanm	92:4fc01daae5a5	978	/**
bogdanm	92:4fc01daae5a5	979	* @}
bogdanm	92:4fc01daae5a5	980	*/
bogdanm	92:4fc01daae5a5	981
bogdanm	92:4fc01daae5a5	982	/** @defgroup ETH_VLAN_Tag_Comparison
bogdanm	92:4fc01daae5a5	983	* @{
bogdanm	92:4fc01daae5a5	984	*/
bogdanm	92:4fc01daae5a5	985	#define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	986	#define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	987	#define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) \|\| \
bogdanm	92:4fc01daae5a5	988	((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
bogdanm	92:4fc01daae5a5	989	#define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
bogdanm	92:4fc01daae5a5	990
bogdanm	92:4fc01daae5a5	991	/**
bogdanm	92:4fc01daae5a5	992	* @}
bogdanm	92:4fc01daae5a5	993	*/
bogdanm	92:4fc01daae5a5	994
bogdanm	92:4fc01daae5a5	995	/** @defgroup ETH_MAC_addresses
bogdanm	92:4fc01daae5a5	996	* @{
bogdanm	92:4fc01daae5a5	997	*/
bogdanm	92:4fc01daae5a5	998	#define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	999	#define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	1000	#define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	1001	#define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
bogdanm	92:4fc01daae5a5	1002	#define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) \|\| \
bogdanm	92:4fc01daae5a5	1003	((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
bogdanm	92:4fc01daae5a5	1004	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
bogdanm	92:4fc01daae5a5	1005	((ADDRESS) == ETH_MAC_ADDRESS3))
bogdanm	92:4fc01daae5a5	1006	#define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) \|\| \
bogdanm	92:4fc01daae5a5	1007	((ADDRESS) == ETH_MAC_ADDRESS2) \|\| \
bogdanm	92:4fc01daae5a5	1008	((ADDRESS) == ETH_MAC_ADDRESS3))
bogdanm	92:4fc01daae5a5	1009	/**
bogdanm	92:4fc01daae5a5	1010	* @}
bogdanm	92:4fc01daae5a5	1011	*/
bogdanm	92:4fc01daae5a5	1012
bogdanm	92:4fc01daae5a5	1013	/** @defgroup ETH_MAC_addresses_filter_SA_DA_filed_of_received_frames
bogdanm	92:4fc01daae5a5	1014	* @{
bogdanm	92:4fc01daae5a5	1015	*/
bogdanm	92:4fc01daae5a5	1016	#define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1017	#define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	1018	#define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) \|\| \
bogdanm	92:4fc01daae5a5	1019	((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
bogdanm	92:4fc01daae5a5	1020	/**
bogdanm	92:4fc01daae5a5	1021	* @}
bogdanm	92:4fc01daae5a5	1022	*/
bogdanm	92:4fc01daae5a5	1023
bogdanm	92:4fc01daae5a5	1024	/** @defgroup ETH_MAC_addresses_filter_Mask_bytes
bogdanm	92:4fc01daae5a5	1025	* @{
bogdanm	92:4fc01daae5a5	1026	*/
bogdanm	92:4fc01daae5a5	1027	#define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /!< Mask MAC Address high reg bits [15:8] /
bogdanm	92:4fc01daae5a5	1028	#define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /!< Mask MAC Address high reg bits [7:0] /
bogdanm	92:4fc01daae5a5	1029	#define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /!< Mask MAC Address low reg bits [31:24] /
bogdanm	92:4fc01daae5a5	1030	#define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /!< Mask MAC Address low reg bits [23:16] /
bogdanm	92:4fc01daae5a5	1031	#define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /!< Mask MAC Address low reg bits [15:8] /
bogdanm	92:4fc01daae5a5	1032	#define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /!< Mask MAC Address low reg bits [70] /
bogdanm	92:4fc01daae5a5	1033	#define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) \|\| \
bogdanm	92:4fc01daae5a5	1034	((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) \|\| \
bogdanm	92:4fc01daae5a5	1035	((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) \|\| \
bogdanm	92:4fc01daae5a5	1036	((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) \|\| \
bogdanm	92:4fc01daae5a5	1037	((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) \|\| \
bogdanm	92:4fc01daae5a5	1038	((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
bogdanm	92:4fc01daae5a5	1039
bogdanm	92:4fc01daae5a5	1040	/**
bogdanm	92:4fc01daae5a5	1041	* @}
bogdanm	92:4fc01daae5a5	1042	*/
bogdanm	92:4fc01daae5a5	1043
bogdanm	92:4fc01daae5a5	1044	/** @defgroup ETH_MAC_Debug_flags
bogdanm	92:4fc01daae5a5	1045	* @{
bogdanm	92:4fc01daae5a5	1046	*/
bogdanm	92:4fc01daae5a5	1047	#define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
bogdanm	92:4fc01daae5a5	1048
bogdanm	92:4fc01daae5a5	1049	#define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
bogdanm	92:4fc01daae5a5	1050
bogdanm	92:4fc01daae5a5	1051	#define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
bogdanm	92:4fc01daae5a5	1052
bogdanm	92:4fc01daae5a5	1053	#define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
bogdanm	92:4fc01daae5a5	1054	#define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
bogdanm	92:4fc01daae5a5	1055	#define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
bogdanm	92:4fc01daae5a5	1056	#define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
bogdanm	92:4fc01daae5a5	1057
bogdanm	92:4fc01daae5a5	1058	#define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
bogdanm	92:4fc01daae5a5	1059
bogdanm	92:4fc01daae5a5	1060	#define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
bogdanm	92:4fc01daae5a5	1061	#define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
bogdanm	92:4fc01daae5a5	1062	#define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
bogdanm	92:4fc01daae5a5	1063	#define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
bogdanm	92:4fc01daae5a5	1064
bogdanm	92:4fc01daae5a5	1065	#define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
bogdanm	92:4fc01daae5a5	1066
bogdanm	92:4fc01daae5a5	1067	#define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
bogdanm	92:4fc01daae5a5	1068	#define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
bogdanm	92:4fc01daae5a5	1069	#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
bogdanm	92:4fc01daae5a5	1070	#define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
bogdanm	92:4fc01daae5a5	1071
bogdanm	92:4fc01daae5a5	1072	#define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000060) /* Rx FIFO read controller IDLE state */
bogdanm	92:4fc01daae5a5	1073	#define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame data */
bogdanm	92:4fc01daae5a5	1074	#define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000060) /* Rx FIFO read controller Reading frame status (or time-stamp) */
bogdanm	92:4fc01daae5a5	1075	#define ETH_MAC_READCONTROLLER_ FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
bogdanm	92:4fc01daae5a5	1076
bogdanm	92:4fc01daae5a5	1077	#define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
bogdanm	92:4fc01daae5a5	1078
bogdanm	92:4fc01daae5a5	1079	#define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
bogdanm	92:4fc01daae5a5	1080	#define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
bogdanm	92:4fc01daae5a5	1081	#define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
bogdanm	92:4fc01daae5a5	1082	#define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
bogdanm	92:4fc01daae5a5	1083
bogdanm	92:4fc01daae5a5	1084	#define ETH_MAC_MII_RECEIVE_PROTOCOL_AVTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
bogdanm	92:4fc01daae5a5	1085
bogdanm	92:4fc01daae5a5	1086	/**
bogdanm	92:4fc01daae5a5	1087	* @}
bogdanm	92:4fc01daae5a5	1088	*/
bogdanm	92:4fc01daae5a5	1089
bogdanm	92:4fc01daae5a5	1090	/** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame
bogdanm	92:4fc01daae5a5	1091	* @{
bogdanm	92:4fc01daae5a5	1092	*/
bogdanm	92:4fc01daae5a5	1093	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1094	#define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
bogdanm	92:4fc01daae5a5	1095	#define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1096	((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
bogdanm	92:4fc01daae5a5	1097	/**
bogdanm	92:4fc01daae5a5	1098	* @}
bogdanm	92:4fc01daae5a5	1099	*/
bogdanm	92:4fc01daae5a5	1100
bogdanm	92:4fc01daae5a5	1101	/** @defgroup ETH_Receive_Store_Forward
bogdanm	92:4fc01daae5a5	1102	* @{
bogdanm	92:4fc01daae5a5	1103	*/
bogdanm	92:4fc01daae5a5	1104	#define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
bogdanm	92:4fc01daae5a5	1105	#define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1106	#define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1107	((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
bogdanm	92:4fc01daae5a5	1108	/**
bogdanm	92:4fc01daae5a5	1109	* @}
bogdanm	92:4fc01daae5a5	1110	*/
bogdanm	92:4fc01daae5a5	1111
bogdanm	92:4fc01daae5a5	1112	/** @defgroup ETH_Flush_Received_Frame
bogdanm	92:4fc01daae5a5	1113	* @{
bogdanm	92:4fc01daae5a5	1114	*/
bogdanm	92:4fc01daae5a5	1115	#define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1116	#define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
bogdanm	92:4fc01daae5a5	1117	#define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1118	((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
bogdanm	92:4fc01daae5a5	1119	/**
bogdanm	92:4fc01daae5a5	1120	* @}
bogdanm	92:4fc01daae5a5	1121	*/
bogdanm	92:4fc01daae5a5	1122
bogdanm	92:4fc01daae5a5	1123	/** @defgroup ETH_Transmit_Store_Forward
bogdanm	92:4fc01daae5a5	1124	* @{
bogdanm	92:4fc01daae5a5	1125	*/
bogdanm	92:4fc01daae5a5	1126	#define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
bogdanm	92:4fc01daae5a5	1127	#define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1128	#define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1129	((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
bogdanm	92:4fc01daae5a5	1130	/**
bogdanm	92:4fc01daae5a5	1131	* @}
bogdanm	92:4fc01daae5a5	1132	*/
bogdanm	92:4fc01daae5a5	1133
bogdanm	92:4fc01daae5a5	1134	/** @defgroup ETH_Transmit_Threshold_Control
bogdanm	92:4fc01daae5a5	1135	* @{
bogdanm	92:4fc01daae5a5	1136	*/
bogdanm	92:4fc01daae5a5	1137	#define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Transmit FIFO is 64 Bytes /
bogdanm	92:4fc01daae5a5	1138	#define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /!< threshold level of the MTL Transmit FIFO is 128 Bytes /
bogdanm	92:4fc01daae5a5	1139	#define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /!< threshold level of the MTL Transmit FIFO is 192 Bytes /
bogdanm	92:4fc01daae5a5	1140	#define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /!< threshold level of the MTL Transmit FIFO is 256 Bytes /
bogdanm	92:4fc01daae5a5	1141	#define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /!< threshold level of the MTL Transmit FIFO is 40 Bytes /
bogdanm	92:4fc01daae5a5	1142	#define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /!< threshold level of the MTL Transmit FIFO is 32 Bytes /
bogdanm	92:4fc01daae5a5	1143	#define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /!< threshold level of the MTL Transmit FIFO is 24 Bytes /
bogdanm	92:4fc01daae5a5	1144	#define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /!< threshold level of the MTL Transmit FIFO is 16 Bytes /
bogdanm	92:4fc01daae5a5	1145	#define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1146	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1147	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1148	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1149	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1150	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1151	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1152	((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
bogdanm	92:4fc01daae5a5	1153	/**
bogdanm	92:4fc01daae5a5	1154	* @}
bogdanm	92:4fc01daae5a5	1155	*/
bogdanm	92:4fc01daae5a5	1156
bogdanm	92:4fc01daae5a5	1157	/** @defgroup ETH_Forward_Error_Frames
bogdanm	92:4fc01daae5a5	1158	* @{
bogdanm	92:4fc01daae5a5	1159	*/
bogdanm	92:4fc01daae5a5	1160	#define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
bogdanm	92:4fc01daae5a5	1161	#define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1162	#define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1163	((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
bogdanm	92:4fc01daae5a5	1164	/**
bogdanm	92:4fc01daae5a5	1165	* @}
bogdanm	92:4fc01daae5a5	1166	*/
bogdanm	92:4fc01daae5a5	1167
bogdanm	92:4fc01daae5a5	1168	/** @defgroup ETH_Forward_Undersized_Good_Frames
bogdanm	92:4fc01daae5a5	1169	* @{
bogdanm	92:4fc01daae5a5	1170	*/
bogdanm	92:4fc01daae5a5	1171	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	1172	#define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1173	#define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1174	((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
bogdanm	92:4fc01daae5a5	1175
bogdanm	92:4fc01daae5a5	1176	/**
bogdanm	92:4fc01daae5a5	1177	* @}
bogdanm	92:4fc01daae5a5	1178	*/
bogdanm	92:4fc01daae5a5	1179
bogdanm	92:4fc01daae5a5	1180	/** @defgroup ETH_Receive_Threshold_Control
bogdanm	92:4fc01daae5a5	1181	* @{
bogdanm	92:4fc01daae5a5	1182	*/
bogdanm	92:4fc01daae5a5	1183	#define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /!< threshold level of the MTL Receive FIFO is 64 Bytes /
bogdanm	92:4fc01daae5a5	1184	#define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /!< threshold level of the MTL Receive FIFO is 32 Bytes /
bogdanm	92:4fc01daae5a5	1185	#define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /!< threshold level of the MTL Receive FIFO is 96 Bytes /
bogdanm	92:4fc01daae5a5	1186	#define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /!< threshold level of the MTL Receive FIFO is 128 Bytes /
bogdanm	92:4fc01daae5a5	1187	#define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1188	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1189	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) \|\| \
bogdanm	92:4fc01daae5a5	1190	((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
bogdanm	92:4fc01daae5a5	1191	/**
bogdanm	92:4fc01daae5a5	1192	* @}
bogdanm	92:4fc01daae5a5	1193	*/
bogdanm	92:4fc01daae5a5	1194
bogdanm	92:4fc01daae5a5	1195	/** @defgroup ETH_Second_Frame_Operate
bogdanm	92:4fc01daae5a5	1196	* @{
bogdanm	92:4fc01daae5a5	1197	*/
bogdanm	92:4fc01daae5a5	1198	#define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	1199	#define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1200	#define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1201	((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
bogdanm	92:4fc01daae5a5	1202
bogdanm	92:4fc01daae5a5	1203	/**
bogdanm	92:4fc01daae5a5	1204	* @}
bogdanm	92:4fc01daae5a5	1205	*/
bogdanm	92:4fc01daae5a5	1206
bogdanm	92:4fc01daae5a5	1207	/** @defgroup ETH_Address_Aligned_Beats
bogdanm	92:4fc01daae5a5	1208	* @{
bogdanm	92:4fc01daae5a5	1209	*/
bogdanm	92:4fc01daae5a5	1210	#define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
bogdanm	92:4fc01daae5a5	1211	#define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1212	#define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1213	((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
bogdanm	92:4fc01daae5a5	1214
bogdanm	92:4fc01daae5a5	1215	/**
bogdanm	92:4fc01daae5a5	1216	* @}
bogdanm	92:4fc01daae5a5	1217	*/
bogdanm	92:4fc01daae5a5	1218
bogdanm	92:4fc01daae5a5	1219	/** @defgroup ETH_Fixed_Burst
bogdanm	92:4fc01daae5a5	1220	* @{
bogdanm	92:4fc01daae5a5	1221	*/
bogdanm	92:4fc01daae5a5	1222	#define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	1223	#define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1224	#define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1225	((CMD) == ETH_FIXEDBURST_DISABLE))
bogdanm	92:4fc01daae5a5	1226
bogdanm	92:4fc01daae5a5	1227	/**
bogdanm	92:4fc01daae5a5	1228	* @}
bogdanm	92:4fc01daae5a5	1229	*/
bogdanm	92:4fc01daae5a5	1230
bogdanm	92:4fc01daae5a5	1231	/** @defgroup ETH_Rx_DMA_Burst_Length
bogdanm	92:4fc01daae5a5	1232	* @{
bogdanm	92:4fc01daae5a5	1233	*/
bogdanm	92:4fc01daae5a5	1234	#define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 1 /
bogdanm	92:4fc01daae5a5	1235	#define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 2 /
bogdanm	92:4fc01daae5a5	1236	#define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
bogdanm	92:4fc01daae5a5	1237	#define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
bogdanm	92:4fc01daae5a5	1238	#define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
bogdanm	92:4fc01daae5a5	1239	#define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
bogdanm	92:4fc01daae5a5	1240	#define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /!< maximum number of beats to be transferred in one RxDMA transaction is 4 /
bogdanm	92:4fc01daae5a5	1241	#define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /!< maximum number of beats to be transferred in one RxDMA transaction is 8 /
bogdanm	92:4fc01daae5a5	1242	#define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /!< maximum number of beats to be transferred in one RxDMA transaction is 16 /
bogdanm	92:4fc01daae5a5	1243	#define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /!< maximum number of beats to be transferred in one RxDMA transaction is 32 /
bogdanm	92:4fc01daae5a5	1244	#define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /!< maximum number of beats to be transferred in one RxDMA transaction is 64 /
bogdanm	92:4fc01daae5a5	1245	#define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /!< maximum number of beats to be transferred in one RxDMA transaction is 128 /
bogdanm	92:4fc01daae5a5	1246
bogdanm	92:4fc01daae5a5	1247	#define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1248	((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1249	((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1250	((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1251	((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1252	((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1253	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1254	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1255	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1256	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1257	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1258	((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
bogdanm	92:4fc01daae5a5	1259
bogdanm	92:4fc01daae5a5	1260	/**
bogdanm	92:4fc01daae5a5	1261	* @}
bogdanm	92:4fc01daae5a5	1262	*/
bogdanm	92:4fc01daae5a5	1263
bogdanm	92:4fc01daae5a5	1264	/** @defgroup ETH_Tx_DMA_Burst_Length
bogdanm	92:4fc01daae5a5	1265	* @{
bogdanm	92:4fc01daae5a5	1266	*/
bogdanm	92:4fc01daae5a5	1267	#define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 /
bogdanm	92:4fc01daae5a5	1268	#define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 /
bogdanm	92:4fc01daae5a5	1269	#define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
bogdanm	92:4fc01daae5a5	1270	#define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
bogdanm	92:4fc01daae5a5	1271	#define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
bogdanm	92:4fc01daae5a5	1272	#define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
bogdanm	92:4fc01daae5a5	1273	#define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 /
bogdanm	92:4fc01daae5a5	1274	#define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 /
bogdanm	92:4fc01daae5a5	1275	#define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 /
bogdanm	92:4fc01daae5a5	1276	#define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 /
bogdanm	92:4fc01daae5a5	1277	#define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 /
bogdanm	92:4fc01daae5a5	1278	#define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 /
bogdanm	92:4fc01daae5a5	1279
bogdanm	92:4fc01daae5a5	1280	#define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1281	((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1282	((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1283	((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1284	((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1285	((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1286	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1287	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1288	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1289	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1290	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) \|\| \
bogdanm	92:4fc01daae5a5	1291	((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
bogdanm	92:4fc01daae5a5	1292
bogdanm	92:4fc01daae5a5	1293	/** @defgroup ETH_DMA_Enhanced_descriptor_format
bogdanm	92:4fc01daae5a5	1294	* @{
bogdanm	92:4fc01daae5a5	1295	*/
bogdanm	92:4fc01daae5a5	1296	#define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
bogdanm	92:4fc01daae5a5	1297	#define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1298
bogdanm	92:4fc01daae5a5	1299	#define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) \|\| \
bogdanm	92:4fc01daae5a5	1300	((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
bogdanm	92:4fc01daae5a5	1301
bogdanm	92:4fc01daae5a5	1302	/**
bogdanm	92:4fc01daae5a5	1303	* @}
bogdanm	92:4fc01daae5a5	1304	*/
bogdanm	92:4fc01daae5a5	1305
bogdanm	92:4fc01daae5a5	1306	/**
bogdanm	92:4fc01daae5a5	1307	* @brief ETH DMA Descriptor SkipLength
bogdanm	92:4fc01daae5a5	1308	*/
bogdanm	92:4fc01daae5a5	1309	#define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
bogdanm	92:4fc01daae5a5	1310
bogdanm	92:4fc01daae5a5	1311
bogdanm	92:4fc01daae5a5	1312	/** @defgroup ETH_DMA_Arbitration
bogdanm	92:4fc01daae5a5	1313	* @{
bogdanm	92:4fc01daae5a5	1314	*/
bogdanm	92:4fc01daae5a5	1315	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
bogdanm	92:4fc01daae5a5	1316	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
bogdanm	92:4fc01daae5a5	1317	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
bogdanm	92:4fc01daae5a5	1318	#define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
bogdanm	92:4fc01daae5a5	1319	#define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	1320	#define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) \|\| \
bogdanm	92:4fc01daae5a5	1321	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) \|\| \
bogdanm	92:4fc01daae5a5	1322	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) \|\| \
bogdanm	92:4fc01daae5a5	1323	((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) \|\| \
bogdanm	92:4fc01daae5a5	1324	((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
bogdanm	92:4fc01daae5a5	1325	/**
bogdanm	92:4fc01daae5a5	1326	* @}
bogdanm	92:4fc01daae5a5	1327	*/
bogdanm	92:4fc01daae5a5	1328
bogdanm	92:4fc01daae5a5	1329	/** @defgroup ETH_DMA_Tx_descriptor_flags
bogdanm	92:4fc01daae5a5	1330	* @{
bogdanm	92:4fc01daae5a5	1331	*/
bogdanm	92:4fc01daae5a5	1332	#define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) \|\| \
bogdanm	92:4fc01daae5a5	1333	((FLAG) == ETH_DMATXDESC_IC) \|\| \
bogdanm	92:4fc01daae5a5	1334	((FLAG) == ETH_DMATXDESC_LS) \|\| \
bogdanm	92:4fc01daae5a5	1335	((FLAG) == ETH_DMATXDESC_FS) \|\| \
bogdanm	92:4fc01daae5a5	1336	((FLAG) == ETH_DMATXDESC_DC) \|\| \
bogdanm	92:4fc01daae5a5	1337	((FLAG) == ETH_DMATXDESC_DP) \|\| \
bogdanm	92:4fc01daae5a5	1338	((FLAG) == ETH_DMATXDESC_TTSE) \|\| \
bogdanm	92:4fc01daae5a5	1339	((FLAG) == ETH_DMATXDESC_TER) \|\| \
bogdanm	92:4fc01daae5a5	1340	((FLAG) == ETH_DMATXDESC_TCH) \|\| \
bogdanm	92:4fc01daae5a5	1341	((FLAG) == ETH_DMATXDESC_TTSS) \|\| \
bogdanm	92:4fc01daae5a5	1342	((FLAG) == ETH_DMATXDESC_IHE) \|\| \
bogdanm	92:4fc01daae5a5	1343	((FLAG) == ETH_DMATXDESC_ES) \|\| \
bogdanm	92:4fc01daae5a5	1344	((FLAG) == ETH_DMATXDESC_JT) \|\| \
bogdanm	92:4fc01daae5a5	1345	((FLAG) == ETH_DMATXDESC_FF) \|\| \
bogdanm	92:4fc01daae5a5	1346	((FLAG) == ETH_DMATXDESC_PCE) \|\| \
bogdanm	92:4fc01daae5a5	1347	((FLAG) == ETH_DMATXDESC_LCA) \|\| \
bogdanm	92:4fc01daae5a5	1348	((FLAG) == ETH_DMATXDESC_NC) \|\| \
bogdanm	92:4fc01daae5a5	1349	((FLAG) == ETH_DMATXDESC_LCO) \|\| \
bogdanm	92:4fc01daae5a5	1350	((FLAG) == ETH_DMATXDESC_EC) \|\| \
bogdanm	92:4fc01daae5a5	1351	((FLAG) == ETH_DMATXDESC_VF) \|\| \
bogdanm	92:4fc01daae5a5	1352	((FLAG) == ETH_DMATXDESC_CC) \|\| \
bogdanm	92:4fc01daae5a5	1353	((FLAG) == ETH_DMATXDESC_ED) \|\| \
bogdanm	92:4fc01daae5a5	1354	((FLAG) == ETH_DMATXDESC_UF) \|\| \
bogdanm	92:4fc01daae5a5	1355	((FLAG) == ETH_DMATXDESC_DB))
bogdanm	92:4fc01daae5a5	1356
bogdanm	92:4fc01daae5a5	1357	/**
bogdanm	92:4fc01daae5a5	1358	* @}
bogdanm	92:4fc01daae5a5	1359	*/
bogdanm	92:4fc01daae5a5	1360
bogdanm	92:4fc01daae5a5	1361	/** @defgroup ETH_DMA_Tx_descriptor_segment
bogdanm	92:4fc01daae5a5	1362	* @{
bogdanm	92:4fc01daae5a5	1363	*/
bogdanm	92:4fc01daae5a5	1364	#define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /!< Last Segment /
bogdanm	92:4fc01daae5a5	1365	#define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /!< First Segment /
bogdanm	92:4fc01daae5a5	1366	#define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) \|\| \
bogdanm	92:4fc01daae5a5	1367	((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
bogdanm	92:4fc01daae5a5	1368
bogdanm	92:4fc01daae5a5	1369	/**
bogdanm	92:4fc01daae5a5	1370	* @}
bogdanm	92:4fc01daae5a5	1371	*/
bogdanm	92:4fc01daae5a5	1372
bogdanm	92:4fc01daae5a5	1373	/** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control
bogdanm	92:4fc01daae5a5	1374	* @{
bogdanm	92:4fc01daae5a5	1375	*/
bogdanm	92:4fc01daae5a5	1376	#define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /!< Checksum engine bypass /
bogdanm	92:4fc01daae5a5	1377	#define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /!< IPv4 header checksum insertion /
bogdanm	92:4fc01daae5a5	1378	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present /
bogdanm	92:4fc01daae5a5	1379	#define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /!< TCP/UDP/ICMP checksum fully in hardware including pseudo header /
bogdanm	92:4fc01daae5a5	1380	#define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) \|\| \
bogdanm	92:4fc01daae5a5	1381	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) \|\| \
bogdanm	92:4fc01daae5a5	1382	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) \|\| \
bogdanm	92:4fc01daae5a5	1383	((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
bogdanm	92:4fc01daae5a5	1384	/**
bogdanm	92:4fc01daae5a5	1385	* @brief ETH DMA Tx Desciptor buffer size
bogdanm	92:4fc01daae5a5	1386	*/
bogdanm	92:4fc01daae5a5	1387	#define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
bogdanm	92:4fc01daae5a5	1388
bogdanm	92:4fc01daae5a5	1389	/**
bogdanm	92:4fc01daae5a5	1390	* @}
bogdanm	92:4fc01daae5a5	1391	*/
bogdanm	92:4fc01daae5a5	1392
bogdanm	92:4fc01daae5a5	1393	/** @defgroup ETH_DMA_Rx_descriptor_flags
bogdanm	92:4fc01daae5a5	1394	* @{
bogdanm	92:4fc01daae5a5	1395	*/
bogdanm	92:4fc01daae5a5	1396	#define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) \|\| \
bogdanm	92:4fc01daae5a5	1397	((FLAG) == ETH_DMARXDESC_AFM) \|\| \
bogdanm	92:4fc01daae5a5	1398	((FLAG) == ETH_DMARXDESC_ES) \|\| \
bogdanm	92:4fc01daae5a5	1399	((FLAG) == ETH_DMARXDESC_DE) \|\| \
bogdanm	92:4fc01daae5a5	1400	((FLAG) == ETH_DMARXDESC_SAF) \|\| \
bogdanm	92:4fc01daae5a5	1401	((FLAG) == ETH_DMARXDESC_LE) \|\| \
bogdanm	92:4fc01daae5a5	1402	((FLAG) == ETH_DMARXDESC_OE) \|\| \
bogdanm	92:4fc01daae5a5	1403	((FLAG) == ETH_DMARXDESC_VLAN) \|\| \
bogdanm	92:4fc01daae5a5	1404	((FLAG) == ETH_DMARXDESC_FS) \|\| \
bogdanm	92:4fc01daae5a5	1405	((FLAG) == ETH_DMARXDESC_LS) \|\| \
bogdanm	92:4fc01daae5a5	1406	((FLAG) == ETH_DMARXDESC_IPV4HCE) \|\| \
bogdanm	92:4fc01daae5a5	1407	((FLAG) == ETH_DMARXDESC_LC) \|\| \
bogdanm	92:4fc01daae5a5	1408	((FLAG) == ETH_DMARXDESC_FT) \|\| \
bogdanm	92:4fc01daae5a5	1409	((FLAG) == ETH_DMARXDESC_RWT) \|\| \
bogdanm	92:4fc01daae5a5	1410	((FLAG) == ETH_DMARXDESC_RE) \|\| \
bogdanm	92:4fc01daae5a5	1411	((FLAG) == ETH_DMARXDESC_DBE) \|\| \
bogdanm	92:4fc01daae5a5	1412	((FLAG) == ETH_DMARXDESC_CE) \|\| \
bogdanm	92:4fc01daae5a5	1413	((FLAG) == ETH_DMARXDESC_MAMPCE))
bogdanm	92:4fc01daae5a5	1414
bogdanm	92:4fc01daae5a5	1415	/* ETHERNET DMA PTP Rx descriptor extended flags --------------------------------*/
bogdanm	92:4fc01daae5a5	1416	#define IS_ETH_DMAPTPRXDESC_GET_EXTENDED_FLAG(FLAG) (((FLAG) == ETH_DMAPTPRXDESC_PTPV) \|\| \
bogdanm	92:4fc01daae5a5	1417	((FLAG) == ETH_DMAPTPRXDESC_PTPFT) \|\| \
bogdanm	92:4fc01daae5a5	1418	((FLAG) == ETH_DMAPTPRXDESC_PTPMT) \|\| \
bogdanm	92:4fc01daae5a5	1419	((FLAG) == ETH_DMAPTPRXDESC_IPV6PR) \|\| \
bogdanm	92:4fc01daae5a5	1420	((FLAG) == ETH_DMAPTPRXDESC_IPV4PR) \|\| \
bogdanm	92:4fc01daae5a5	1421	((FLAG) == ETH_DMAPTPRXDESC_IPCB) \|\| \
bogdanm	92:4fc01daae5a5	1422	((FLAG) == ETH_DMAPTPRXDESC_IPPE) \|\| \
bogdanm	92:4fc01daae5a5	1423	((FLAG) == ETH_DMAPTPRXDESC_IPHE) \|\| \
bogdanm	92:4fc01daae5a5	1424	((FLAG) == ETH_DMAPTPRXDESC_IPPT))
bogdanm	92:4fc01daae5a5	1425
bogdanm	92:4fc01daae5a5	1426	/**
bogdanm	92:4fc01daae5a5	1427	* @}
bogdanm	92:4fc01daae5a5	1428	*/
bogdanm	92:4fc01daae5a5	1429
bogdanm	92:4fc01daae5a5	1430	/** @defgroup ETH_DMA_Rx_descriptor_buffers_
bogdanm	92:4fc01daae5a5	1431	* @{
bogdanm	92:4fc01daae5a5	1432	*/
bogdanm	92:4fc01daae5a5	1433	#define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /!< DMA Rx Desc Buffer1 /
bogdanm	92:4fc01daae5a5	1434	#define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /!< DMA Rx Desc Buffer2 /
bogdanm	92:4fc01daae5a5	1435	#define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) \|\| \
bogdanm	92:4fc01daae5a5	1436	((BUFFER) == ETH_DMARXDESC_BUFFER2))
bogdanm	92:4fc01daae5a5	1437
bogdanm	92:4fc01daae5a5	1438
bogdanm	92:4fc01daae5a5	1439	/* ETHERNET DMA Tx descriptors Collision Count Shift */
bogdanm	92:4fc01daae5a5	1440	#define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
bogdanm	92:4fc01daae5a5	1441
bogdanm	92:4fc01daae5a5	1442	/* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
bogdanm	92:4fc01daae5a5	1443	#define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
bogdanm	92:4fc01daae5a5	1444
bogdanm	92:4fc01daae5a5	1445	/* ETHERNET DMA Rx descriptors Frame Length Shift */
bogdanm	92:4fc01daae5a5	1446	#define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
bogdanm	92:4fc01daae5a5	1447
bogdanm	92:4fc01daae5a5	1448	/* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
bogdanm	92:4fc01daae5a5	1449	#define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
bogdanm	92:4fc01daae5a5	1450
bogdanm	92:4fc01daae5a5	1451	/* ETHERNET DMA Rx descriptors Frame length Shift */
bogdanm	92:4fc01daae5a5	1452	#define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
bogdanm	92:4fc01daae5a5	1453
bogdanm	92:4fc01daae5a5	1454	/**
bogdanm	92:4fc01daae5a5	1455	* @}
bogdanm	92:4fc01daae5a5	1456	*/
bogdanm	92:4fc01daae5a5	1457
bogdanm	92:4fc01daae5a5	1458	/** @defgroup ETH_PMT_Flags
bogdanm	92:4fc01daae5a5	1459	* @{
bogdanm	92:4fc01daae5a5	1460	*/
bogdanm	92:4fc01daae5a5	1461	#define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /!< Wake-Up Frame Filter Register Pointer Reset /
bogdanm	92:4fc01daae5a5	1462	#define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /!< Wake-Up Frame Received /
bogdanm	92:4fc01daae5a5	1463	#define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /!< Magic Packet Received /
bogdanm	92:4fc01daae5a5	1464	#define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) \|\| \
bogdanm	92:4fc01daae5a5	1465	((FLAG) == ETH_PMT_FLAG_MPR))
bogdanm	92:4fc01daae5a5	1466	/**
bogdanm	92:4fc01daae5a5	1467	* @}
bogdanm	92:4fc01daae5a5	1468	*/
bogdanm	92:4fc01daae5a5	1469
bogdanm	92:4fc01daae5a5	1470	/** @defgroup ETH_MMC_Tx_Interrupts
bogdanm	92:4fc01daae5a5	1471	* @{
bogdanm	92:4fc01daae5a5	1472	*/
bogdanm	92:4fc01daae5a5	1473	#define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /!< When Tx good frame counter reaches half the maximum value /
bogdanm	92:4fc01daae5a5	1474	#define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /!< When Tx good multi col counter reaches half the maximum value /
bogdanm	92:4fc01daae5a5	1475	#define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /!< When Tx good single col counter reaches half the maximum value /
bogdanm	92:4fc01daae5a5	1476
bogdanm	92:4fc01daae5a5	1477	/**
bogdanm	92:4fc01daae5a5	1478	* @}
bogdanm	92:4fc01daae5a5	1479	*/
bogdanm	92:4fc01daae5a5	1480
bogdanm	92:4fc01daae5a5	1481	/** @defgroup ETH_MMC_Rx_Interrupts
bogdanm	92:4fc01daae5a5	1482	* @{
bogdanm	92:4fc01daae5a5	1483	*/
bogdanm	92:4fc01daae5a5	1484	#define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /!< When Rx good unicast frames counter reaches half the maximum value /
bogdanm	92:4fc01daae5a5	1485	#define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /!< When Rx alignment error counter reaches half the maximum value /
bogdanm	92:4fc01daae5a5	1486	#define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /!< When Rx crc error counter reaches half the maximum value /
bogdanm	92:4fc01daae5a5	1487	#define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) \|\| (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
bogdanm	92:4fc01daae5a5	1488	((IT) != 0x00))
bogdanm	92:4fc01daae5a5	1489	#define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) \|\| ((IT) == ETH_MMC_IT_TGFMSC) \|\| \
bogdanm	92:4fc01daae5a5	1490	((IT) == ETH_MMC_IT_TGFSC) \|\| ((IT) == ETH_MMC_IT_RGUF) \|\| \
bogdanm	92:4fc01daae5a5	1491	((IT) == ETH_MMC_IT_RFAE) \|\| ((IT) == ETH_MMC_IT_RFCE))
bogdanm	92:4fc01daae5a5	1492	/**
bogdanm	92:4fc01daae5a5	1493	* @}
bogdanm	92:4fc01daae5a5	1494	*/
bogdanm	92:4fc01daae5a5	1495
bogdanm	92:4fc01daae5a5	1496	/** @defgroup ETH_MMC_Registers
bogdanm	92:4fc01daae5a5	1497	* @{
bogdanm	92:4fc01daae5a5	1498	*/
bogdanm	92:4fc01daae5a5	1499	#define ETH_MMCCR ((uint32_t)0x00000100) /!< MMC CR register /
bogdanm	92:4fc01daae5a5	1500	#define ETH_MMCRIR ((uint32_t)0x00000104) /!< MMC RIR register /
bogdanm	92:4fc01daae5a5	1501	#define ETH_MMCTIR ((uint32_t)0x00000108) /!< MMC TIR register /
bogdanm	92:4fc01daae5a5	1502	#define ETH_MMCRIMR ((uint32_t)0x0000010C) /!< MMC RIMR register /
bogdanm	92:4fc01daae5a5	1503	#define ETH_MMCTIMR ((uint32_t)0x00000110) /!< MMC TIMR register /
bogdanm	92:4fc01daae5a5	1504	#define ETH_MMCTGFSCCR ((uint32_t)0x0000014C) /!< MMC TGFSCCR register /
bogdanm	92:4fc01daae5a5	1505	#define ETH_MMCTGFMSCCR ((uint32_t)0x00000150) /!< MMC TGFMSCCR register /
bogdanm	92:4fc01daae5a5	1506	#define ETH_MMCTGFCR ((uint32_t)0x00000168) /!< MMC TGFCR register /
bogdanm	92:4fc01daae5a5	1507	#define ETH_MMCRFCECR ((uint32_t)0x00000194) /!< MMC RFCECR register /
bogdanm	92:4fc01daae5a5	1508	#define ETH_MMCRFAECR ((uint32_t)0x00000198) /!< MMC RFAECR register /
bogdanm	92:4fc01daae5a5	1509	#define ETH_MMCRGUFCR ((uint32_t)0x000001C4) /!< MMC RGUFCR register /
bogdanm	92:4fc01daae5a5	1510
bogdanm	92:4fc01daae5a5	1511	/**
bogdanm	92:4fc01daae5a5	1512	* @brief ETH MMC registers
bogdanm	92:4fc01daae5a5	1513	*/
bogdanm	92:4fc01daae5a5	1514	#define IS_ETH_MMC_REGISTER(REG) (((REG) == ETH_MMCCR) \|\| ((REG) == ETH_MMCRIR) \|\| \
bogdanm	92:4fc01daae5a5	1515	((REG) == ETH_MMCTIR) \|\| ((REG) == ETH_MMCRIMR) \|\| \
bogdanm	92:4fc01daae5a5	1516	((REG) == ETH_MMCTIMR) \|\| ((REG) == ETH_MMCTGFSCCR) \|\| \
bogdanm	92:4fc01daae5a5	1517	((REG) == ETH_MMCTGFMSCCR) \|\| ((REG) == ETH_MMCTGFCR) \|\| \
bogdanm	92:4fc01daae5a5	1518	((REG) == ETH_MMCRFCECR) \|\| ((REG) == ETH_MMCRFAECR) \|\| \
bogdanm	92:4fc01daae5a5	1519	((REG) == ETH_MMCRGUFCR))
bogdanm	92:4fc01daae5a5	1520	/**
bogdanm	92:4fc01daae5a5	1521	* @}
bogdanm	92:4fc01daae5a5	1522	*/
bogdanm	92:4fc01daae5a5	1523
bogdanm	92:4fc01daae5a5	1524	/** @defgroup ETH_MAC_Flags
bogdanm	92:4fc01daae5a5	1525	* @{
bogdanm	92:4fc01daae5a5	1526	*/
bogdanm	92:4fc01daae5a5	1527	#define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /!< Time stamp trigger flag (on MAC) /
bogdanm	92:4fc01daae5a5	1528	#define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /!< MMC transmit flag /
bogdanm	92:4fc01daae5a5	1529	#define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /!< MMC receive flag /
bogdanm	92:4fc01daae5a5	1530	#define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /!< MMC flag (on MAC) /
bogdanm	92:4fc01daae5a5	1531	#define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /!< PMT flag (on MAC) /
bogdanm	92:4fc01daae5a5	1532	#define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) \|\| ((FLAG) == ETH_MAC_FLAG_MMCT) \|\| \
bogdanm	92:4fc01daae5a5	1533	((FLAG) == ETH_MAC_FLAG_MMCR) \|\| ((FLAG) == ETH_MAC_FLAG_MMC) \|\| \
bogdanm	92:4fc01daae5a5	1534	((FLAG) == ETH_MAC_FLAG_PMT))
bogdanm	92:4fc01daae5a5	1535	/**
bogdanm	92:4fc01daae5a5	1536	* @}
bogdanm	92:4fc01daae5a5	1537	*/
bogdanm	92:4fc01daae5a5	1538
bogdanm	92:4fc01daae5a5	1539	/** @defgroup ETH_DMA_Flags
bogdanm	92:4fc01daae5a5	1540	* @{
bogdanm	92:4fc01daae5a5	1541	*/
bogdanm	92:4fc01daae5a5	1542	#define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
bogdanm	92:4fc01daae5a5	1543	#define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
bogdanm	92:4fc01daae5a5	1544	#define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
bogdanm	92:4fc01daae5a5	1545	#define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /!< Error bits 0-Rx DMA, 1-Tx DMA /
bogdanm	92:4fc01daae5a5	1546	#define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /!< Error bits 0-write trnsf, 1-read transfr /
bogdanm	92:4fc01daae5a5	1547	#define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /!< Error bits 0-data buffer, 1-desc. access /
bogdanm	92:4fc01daae5a5	1548	#define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary flag /
bogdanm	92:4fc01daae5a5	1549	#define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary flag /
bogdanm	92:4fc01daae5a5	1550	#define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /!< Early receive flag /
bogdanm	92:4fc01daae5a5	1551	#define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /!< Fatal bus error flag /
bogdanm	92:4fc01daae5a5	1552	#define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /!< Early transmit flag /
bogdanm	92:4fc01daae5a5	1553	#define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout flag /
bogdanm	92:4fc01daae5a5	1554	#define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /!< Receive process stopped flag /
bogdanm	92:4fc01daae5a5	1555	#define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable flag /
bogdanm	92:4fc01daae5a5	1556	#define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /!< Receive flag /
bogdanm	92:4fc01daae5a5	1557	#define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /!< Underflow flag /
bogdanm	92:4fc01daae5a5	1558	#define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /!< Overflow flag /
bogdanm	92:4fc01daae5a5	1559	#define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout flag /
bogdanm	92:4fc01daae5a5	1560	#define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable flag /
bogdanm	92:4fc01daae5a5	1561	#define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /!< Transmit process stopped flag /
bogdanm	92:4fc01daae5a5	1562	#define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /!< Transmit flag /
bogdanm	92:4fc01daae5a5	1563
bogdanm	92:4fc01daae5a5	1564	#define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
bogdanm	92:4fc01daae5a5	1565	#define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) \|\| ((FLAG) == ETH_DMA_FLAG_PMT) \|\| \
bogdanm	92:4fc01daae5a5	1566	((FLAG) == ETH_DMA_FLAG_MMC) \|\| ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) \|\| \
bogdanm	92:4fc01daae5a5	1567	((FLAG) == ETH_DMA_FLAG_READWRITEERROR) \|\| ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) \|\| \
bogdanm	92:4fc01daae5a5	1568	((FLAG) == ETH_DMA_FLAG_NIS) \|\| ((FLAG) == ETH_DMA_FLAG_AIS) \|\| \
bogdanm	92:4fc01daae5a5	1569	((FLAG) == ETH_DMA_FLAG_ER) \|\| ((FLAG) == ETH_DMA_FLAG_FBE) \|\| \
bogdanm	92:4fc01daae5a5	1570	((FLAG) == ETH_DMA_FLAG_ET) \|\| ((FLAG) == ETH_DMA_FLAG_RWT) \|\| \
bogdanm	92:4fc01daae5a5	1571	((FLAG) == ETH_DMA_FLAG_RPS) \|\| ((FLAG) == ETH_DMA_FLAG_RBU) \|\| \
bogdanm	92:4fc01daae5a5	1572	((FLAG) == ETH_DMA_FLAG_R) \|\| ((FLAG) == ETH_DMA_FLAG_TU) \|\| \
bogdanm	92:4fc01daae5a5	1573	((FLAG) == ETH_DMA_FLAG_RO) \|\| ((FLAG) == ETH_DMA_FLAG_TJT) \|\| \
bogdanm	92:4fc01daae5a5	1574	((FLAG) == ETH_DMA_FLAG_TBU) \|\| ((FLAG) == ETH_DMA_FLAG_TPS) \|\| \
bogdanm	92:4fc01daae5a5	1575	((FLAG) == ETH_DMA_FLAG_T))
bogdanm	92:4fc01daae5a5	1576	/**
bogdanm	92:4fc01daae5a5	1577	* @}
bogdanm	92:4fc01daae5a5	1578	*/
bogdanm	92:4fc01daae5a5	1579
bogdanm	92:4fc01daae5a5	1580	/** @defgroup ETH_MAC_Interrupts
bogdanm	92:4fc01daae5a5	1581	* @{
bogdanm	92:4fc01daae5a5	1582	*/
bogdanm	92:4fc01daae5a5	1583	#define ETH_MAC_IT_TST ((uint32_t)0x00000200) /!< Time stamp trigger interrupt (on MAC) /
bogdanm	92:4fc01daae5a5	1584	#define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /!< MMC transmit interrupt /
bogdanm	92:4fc01daae5a5	1585	#define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /!< MMC receive interrupt /
bogdanm	92:4fc01daae5a5	1586	#define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /!< MMC interrupt (on MAC) /
bogdanm	92:4fc01daae5a5	1587	#define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /!< PMT interrupt (on MAC) /
bogdanm	92:4fc01daae5a5	1588	#define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF7) == 0x00) && ((IT) != 0x00))
bogdanm	92:4fc01daae5a5	1589	#define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) \|\| ((IT) == ETH_MAC_IT_MMCT) \|\| \
bogdanm	92:4fc01daae5a5	1590	((IT) == ETH_MAC_IT_MMCR) \|\| ((IT) == ETH_MAC_IT_MMC) \|\| \
bogdanm	92:4fc01daae5a5	1591	((IT) == ETH_MAC_IT_PMT))
bogdanm	92:4fc01daae5a5	1592	/**
bogdanm	92:4fc01daae5a5	1593	* @}
bogdanm	92:4fc01daae5a5	1594	*/
bogdanm	92:4fc01daae5a5	1595
bogdanm	92:4fc01daae5a5	1596	/** @defgroup ETH_DMA_Interrupts
bogdanm	92:4fc01daae5a5	1597	* @{
bogdanm	92:4fc01daae5a5	1598	*/
bogdanm	92:4fc01daae5a5	1599	#define ETH_DMA_IT_TST ((uint32_t)0x20000000) /!< Time-stamp trigger interrupt (on DMA) /
bogdanm	92:4fc01daae5a5	1600	#define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /!< PMT interrupt (on DMA) /
bogdanm	92:4fc01daae5a5	1601	#define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /!< MMC interrupt (on DMA) /
bogdanm	92:4fc01daae5a5	1602	#define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /!< Normal interrupt summary /
bogdanm	92:4fc01daae5a5	1603	#define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /!< Abnormal interrupt summary /
bogdanm	92:4fc01daae5a5	1604	#define ETH_DMA_IT_ER ((uint32_t)0x00004000) /!< Early receive interrupt /
bogdanm	92:4fc01daae5a5	1605	#define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /!< Fatal bus error interrupt /
bogdanm	92:4fc01daae5a5	1606	#define ETH_DMA_IT_ET ((uint32_t)0x00000400) /!< Early transmit interrupt /
bogdanm	92:4fc01daae5a5	1607	#define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /!< Receive watchdog timeout interrupt /
bogdanm	92:4fc01daae5a5	1608	#define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /!< Receive process stopped interrupt /
bogdanm	92:4fc01daae5a5	1609	#define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /!< Receive buffer unavailable interrupt /
bogdanm	92:4fc01daae5a5	1610	#define ETH_DMA_IT_R ((uint32_t)0x00000040) /!< Receive interrupt /
bogdanm	92:4fc01daae5a5	1611	#define ETH_DMA_IT_TU ((uint32_t)0x00000020) /!< Underflow interrupt /
bogdanm	92:4fc01daae5a5	1612	#define ETH_DMA_IT_RO ((uint32_t)0x00000010) /!< Overflow interrupt /
bogdanm	92:4fc01daae5a5	1613	#define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /!< Transmit jabber timeout interrupt /
bogdanm	92:4fc01daae5a5	1614	#define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /!< Transmit buffer unavailable interrupt /
bogdanm	92:4fc01daae5a5	1615	#define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /!< Transmit process stopped interrupt /
bogdanm	92:4fc01daae5a5	1616	#define ETH_DMA_IT_T ((uint32_t)0x00000001) /!< Transmit interrupt /
bogdanm	92:4fc01daae5a5	1617
bogdanm	92:4fc01daae5a5	1618	#define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
bogdanm	92:4fc01daae5a5	1619	#define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) \|\| ((IT) == ETH_DMA_IT_PMT) \|\| \
bogdanm	92:4fc01daae5a5	1620	((IT) == ETH_DMA_IT_MMC) \|\| ((IT) == ETH_DMA_IT_NIS) \|\| \
bogdanm	92:4fc01daae5a5	1621	((IT) == ETH_DMA_IT_AIS) \|\| ((IT) == ETH_DMA_IT_ER) \|\| \
bogdanm	92:4fc01daae5a5	1622	((IT) == ETH_DMA_IT_FBE) \|\| ((IT) == ETH_DMA_IT_ET) \|\| \
bogdanm	92:4fc01daae5a5	1623	((IT) == ETH_DMA_IT_RWT) \|\| ((IT) == ETH_DMA_IT_RPS) \|\| \
bogdanm	92:4fc01daae5a5	1624	((IT) == ETH_DMA_IT_RBU) \|\| ((IT) == ETH_DMA_IT_R) \|\| \
bogdanm	92:4fc01daae5a5	1625	((IT) == ETH_DMA_IT_TU) \|\| ((IT) == ETH_DMA_IT_RO) \|\| \
bogdanm	92:4fc01daae5a5	1626	((IT) == ETH_DMA_IT_TJT) \|\| ((IT) == ETH_DMA_IT_TBU) \|\| \
bogdanm	92:4fc01daae5a5	1627	((IT) == ETH_DMA_IT_TPS) \|\| ((IT) == ETH_DMA_IT_T))
bogdanm	92:4fc01daae5a5	1628
bogdanm	92:4fc01daae5a5	1629	/**
bogdanm	92:4fc01daae5a5	1630	* @}
bogdanm	92:4fc01daae5a5	1631	*/
bogdanm	92:4fc01daae5a5	1632
bogdanm	92:4fc01daae5a5	1633	/** @defgroup ETH_DMA_transmit_process_state_
bogdanm	92:4fc01daae5a5	1634	* @{
bogdanm	92:4fc01daae5a5	1635	*/
bogdanm	92:4fc01daae5a5	1636	#define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Tx Command issued /
bogdanm	92:4fc01daae5a5	1637	#define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /!< Running - fetching the Tx descriptor /
bogdanm	92:4fc01daae5a5	1638	#define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /!< Running - waiting for status /
bogdanm	92:4fc01daae5a5	1639	#define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /!< Running - reading the data from host memory /
bogdanm	92:4fc01daae5a5	1640	#define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /!< Suspended - Tx Descriptor unavailable /
bogdanm	92:4fc01daae5a5	1641	#define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /!< Running - closing Rx descriptor /
bogdanm	92:4fc01daae5a5	1642
bogdanm	92:4fc01daae5a5	1643	/**
bogdanm	92:4fc01daae5a5	1644	* @}
bogdanm	92:4fc01daae5a5	1645	*/
bogdanm	92:4fc01daae5a5	1646
bogdanm	92:4fc01daae5a5	1647
bogdanm	92:4fc01daae5a5	1648	/** @defgroup ETH_DMA_receive_process_state_
bogdanm	92:4fc01daae5a5	1649	* @{
bogdanm	92:4fc01daae5a5	1650	*/
bogdanm	92:4fc01daae5a5	1651	#define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /!< Stopped - Reset or Stop Rx Command issued /
bogdanm	92:4fc01daae5a5	1652	#define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /!< Running - fetching the Rx descriptor /
bogdanm	92:4fc01daae5a5	1653	#define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /!< Running - waiting for packet /
bogdanm	92:4fc01daae5a5	1654	#define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /!< Suspended - Rx Descriptor unavailable /
bogdanm	92:4fc01daae5a5	1655	#define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /!< Running - closing descriptor /
bogdanm	92:4fc01daae5a5	1656	#define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /!< Running - queuing the receive frame into host memory /
bogdanm	92:4fc01daae5a5	1657
bogdanm	92:4fc01daae5a5	1658	/**
bogdanm	92:4fc01daae5a5	1659	* @}
bogdanm	92:4fc01daae5a5	1660	*/
bogdanm	92:4fc01daae5a5	1661
bogdanm	92:4fc01daae5a5	1662	/** @defgroup ETH_DMA_overflow_
bogdanm	92:4fc01daae5a5	1663	* @{
bogdanm	92:4fc01daae5a5	1664	*/
bogdanm	92:4fc01daae5a5	1665	#define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /!< Overflow bit for FIFO overflow counter /
bogdanm	92:4fc01daae5a5	1666	#define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /!< Overflow bit for missed frame counter /
bogdanm	92:4fc01daae5a5	1667	#define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) \|\| \
bogdanm	92:4fc01daae5a5	1668	((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
bogdanm	92:4fc01daae5a5	1669	/**
bogdanm	92:4fc01daae5a5	1670	* @}
bogdanm	92:4fc01daae5a5	1671	*/
bogdanm	92:4fc01daae5a5	1672
bogdanm	92:4fc01daae5a5	1673	/* ETHERNET MAC address offsets */
bogdanm	92:4fc01daae5a5	1674	#define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
bogdanm	92:4fc01daae5a5	1675	#define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
bogdanm	92:4fc01daae5a5	1676
bogdanm	92:4fc01daae5a5	1677	/* ETHERNET MACMIIAR register Mask */
bogdanm	92:4fc01daae5a5	1678	#define MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
bogdanm	92:4fc01daae5a5	1679
bogdanm	92:4fc01daae5a5	1680	/* ETHERNET MACCR register Mask */
bogdanm	92:4fc01daae5a5	1681	#define MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
bogdanm	92:4fc01daae5a5	1682
bogdanm	92:4fc01daae5a5	1683	/* ETHERNET MACFCR register Mask */
bogdanm	92:4fc01daae5a5	1684	#define MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
bogdanm	92:4fc01daae5a5	1685
bogdanm	92:4fc01daae5a5	1686
bogdanm	92:4fc01daae5a5	1687	/* ETHERNET DMAOMR register Mask */
bogdanm	92:4fc01daae5a5	1688	#define DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
bogdanm	92:4fc01daae5a5	1689
bogdanm	92:4fc01daae5a5	1690
bogdanm	92:4fc01daae5a5	1691	/* ETHERNET Remote Wake-up frame register length */
bogdanm	92:4fc01daae5a5	1692	#define ETH_WAKEUP_REGISTER_LENGTH 8
bogdanm	92:4fc01daae5a5	1693
bogdanm	92:4fc01daae5a5	1694	/* ETHERNET Missed frames counter Shift */
bogdanm	92:4fc01daae5a5	1695	#define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
bogdanm	92:4fc01daae5a5	1696
bogdanm	92:4fc01daae5a5	1697	/**
bogdanm	92:4fc01daae5a5	1698	* @}
bogdanm	92:4fc01daae5a5	1699	*/
bogdanm	92:4fc01daae5a5	1700
bogdanm	92:4fc01daae5a5	1701	/* Exported macro ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1702
bogdanm	92:4fc01daae5a5	1703	/** @brief Reset ETH handle state
bogdanm	92:4fc01daae5a5	1704	* @param __HANDLE__: specifies the ETH handle.
bogdanm	92:4fc01daae5a5	1705	* @retval None
bogdanm	92:4fc01daae5a5	1706	*/
bogdanm	92:4fc01daae5a5	1707	#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
bogdanm	92:4fc01daae5a5	1708
bogdanm	92:4fc01daae5a5	1709	/**
bogdanm	92:4fc01daae5a5	1710	* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
bogdanm	92:4fc01daae5a5	1711	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1712	* @param __FLAG__: specifies the flag to check.
bogdanm	92:4fc01daae5a5	1713	* @retval the ETH_DMATxDescFlag (SET or RESET).
bogdanm	92:4fc01daae5a5	1714	*/
bogdanm	92:4fc01daae5a5	1715	#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
bogdanm	92:4fc01daae5a5	1716
bogdanm	92:4fc01daae5a5	1717	/**
bogdanm	92:4fc01daae5a5	1718	* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
bogdanm	92:4fc01daae5a5	1719	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1720	* @param __FLAG__: specifies the flag to check.
bogdanm	92:4fc01daae5a5	1721	* @retval the ETH_DMATxDescFlag (SET or RESET).
bogdanm	92:4fc01daae5a5	1722	*/
bogdanm	92:4fc01daae5a5	1723	#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
bogdanm	92:4fc01daae5a5	1724
bogdanm	92:4fc01daae5a5	1725	/**
bogdanm	92:4fc01daae5a5	1726	* @brief Enables the specified DMA Rx Desc receive interrupt.
bogdanm	92:4fc01daae5a5	1727	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1728	* @retval None
bogdanm	92:4fc01daae5a5	1729	*/
bogdanm	92:4fc01daae5a5	1730	#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
bogdanm	92:4fc01daae5a5	1731
bogdanm	92:4fc01daae5a5	1732	/**
bogdanm	92:4fc01daae5a5	1733	* @brief Disables the specified DMA Rx Desc receive interrupt.
bogdanm	92:4fc01daae5a5	1734	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1735	* @retval None
bogdanm	92:4fc01daae5a5	1736	*/
bogdanm	92:4fc01daae5a5	1737	#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize \|= ETH_DMARXDESC_DIC)
bogdanm	92:4fc01daae5a5	1738
bogdanm	92:4fc01daae5a5	1739	/**
bogdanm	92:4fc01daae5a5	1740	* @brief Set the specified DMA Rx Desc Own bit.
bogdanm	92:4fc01daae5a5	1741	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1742	* @retval None
bogdanm	92:4fc01daae5a5	1743	*/
bogdanm	92:4fc01daae5a5	1744	#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status \|= ETH_DMARXDESC_OWN)
bogdanm	92:4fc01daae5a5	1745
bogdanm	92:4fc01daae5a5	1746	/**
bogdanm	92:4fc01daae5a5	1747	* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
bogdanm	92:4fc01daae5a5	1748	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1749	* @retval The Transmit descriptor collision counter value.
bogdanm	92:4fc01daae5a5	1750	*/
bogdanm	92:4fc01daae5a5	1751	#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
bogdanm	92:4fc01daae5a5	1752
bogdanm	92:4fc01daae5a5	1753	/**
bogdanm	92:4fc01daae5a5	1754	* @brief Set the specified DMA Tx Desc Own bit.
bogdanm	92:4fc01daae5a5	1755	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1756	* @retval None
bogdanm	92:4fc01daae5a5	1757	*/
bogdanm	92:4fc01daae5a5	1758	#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_OWN)
bogdanm	92:4fc01daae5a5	1759
bogdanm	92:4fc01daae5a5	1760	/**
bogdanm	92:4fc01daae5a5	1761	* @brief Enables the specified DMA Tx Desc Transmit interrupt.
bogdanm	92:4fc01daae5a5	1762	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1763	* @retval None
bogdanm	92:4fc01daae5a5	1764	*/
bogdanm	92:4fc01daae5a5	1765	#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_IC)
bogdanm	92:4fc01daae5a5	1766
bogdanm	92:4fc01daae5a5	1767	/**
bogdanm	92:4fc01daae5a5	1768	* @brief Disables the specified DMA Tx Desc Transmit interrupt.
bogdanm	92:4fc01daae5a5	1769	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1770	* @retval None
bogdanm	92:4fc01daae5a5	1771	*/
bogdanm	92:4fc01daae5a5	1772	#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
bogdanm	92:4fc01daae5a5	1773
bogdanm	92:4fc01daae5a5	1774	/**
bogdanm	92:4fc01daae5a5	1775	* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
bogdanm	92:4fc01daae5a5	1776	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1777	* @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
bogdanm	92:4fc01daae5a5	1778	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1779	* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
bogdanm	92:4fc01daae5a5	1780	* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
bogdanm	92:4fc01daae5a5	1781	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
bogdanm	92:4fc01daae5a5	1782	* @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
bogdanm	92:4fc01daae5a5	1783	* @retval None
bogdanm	92:4fc01daae5a5	1784	*/
bogdanm	92:4fc01daae5a5	1785	#define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status \|= (__CHECKSUM__))
bogdanm	92:4fc01daae5a5	1786
bogdanm	92:4fc01daae5a5	1787	/**
bogdanm	92:4fc01daae5a5	1788	* @brief Enables the DMA Tx Desc CRC.
bogdanm	92:4fc01daae5a5	1789	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1790	* @retval None
bogdanm	92:4fc01daae5a5	1791	*/
bogdanm	92:4fc01daae5a5	1792	#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
bogdanm	92:4fc01daae5a5	1793
bogdanm	92:4fc01daae5a5	1794	/**
bogdanm	92:4fc01daae5a5	1795	* @brief Disables the DMA Tx Desc CRC.
bogdanm	92:4fc01daae5a5	1796	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1797	* @retval None
bogdanm	92:4fc01daae5a5	1798	*/
bogdanm	92:4fc01daae5a5	1799	#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DC)
bogdanm	92:4fc01daae5a5	1800
bogdanm	92:4fc01daae5a5	1801	/**
bogdanm	92:4fc01daae5a5	1802	* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
bogdanm	92:4fc01daae5a5	1803	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1804	* @retval None
bogdanm	92:4fc01daae5a5	1805	*/
bogdanm	92:4fc01daae5a5	1806	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
bogdanm	92:4fc01daae5a5	1807
bogdanm	92:4fc01daae5a5	1808	/**
bogdanm	92:4fc01daae5a5	1809	* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
bogdanm	92:4fc01daae5a5	1810	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1811	* @retval None
bogdanm	92:4fc01daae5a5	1812	*/
bogdanm	92:4fc01daae5a5	1813	#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status \|= ETH_DMATXDESC_DP)
bogdanm	92:4fc01daae5a5	1814
bogdanm	92:4fc01daae5a5	1815	/**
bogdanm	92:4fc01daae5a5	1816	* @brief Enables the specified ETHERNET MAC interrupts.
bogdanm	92:4fc01daae5a5	1817	* @param __HANDLE__ : ETH Handle
bogdanm	92:4fc01daae5a5	1818	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
bogdanm	92:4fc01daae5a5	1819	* enabled or disabled.
bogdanm	92:4fc01daae5a5	1820	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1821	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
bogdanm	92:4fc01daae5a5	1822	* @arg ETH_MAC_IT_PMT : PMT interrupt
bogdanm	92:4fc01daae5a5	1823	* @retval None
bogdanm	92:4fc01daae5a5	1824	*/
bogdanm	92:4fc01daae5a5	1825	#define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1826
bogdanm	92:4fc01daae5a5	1827	/**
bogdanm	92:4fc01daae5a5	1828	* @brief Disables the specified ETHERNET MAC interrupts.
bogdanm	92:4fc01daae5a5	1829	* @param __HANDLE__ : ETH Handle
bogdanm	92:4fc01daae5a5	1830	* @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
bogdanm	92:4fc01daae5a5	1831	* enabled or disabled.
bogdanm	92:4fc01daae5a5	1832	* This parameter can be any combination of the following values:
bogdanm	92:4fc01daae5a5	1833	* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
bogdanm	92:4fc01daae5a5	1834	* @arg ETH_MAC_IT_PMT : PMT interrupt
bogdanm	92:4fc01daae5a5	1835	* @retval None
bogdanm	92:4fc01daae5a5	1836	*/
bogdanm	92:4fc01daae5a5	1837	#define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1838
bogdanm	92:4fc01daae5a5	1839	/**
bogdanm	92:4fc01daae5a5	1840	* @brief Initiate a Pause Control Frame (Full-duplex only).
bogdanm	92:4fc01daae5a5	1841	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1842	* @retval None
bogdanm	92:4fc01daae5a5	1843	*/
bogdanm	92:4fc01daae5a5	1844	#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
bogdanm	92:4fc01daae5a5	1845
bogdanm	92:4fc01daae5a5	1846	/**
bogdanm	92:4fc01daae5a5	1847	* @brief Checks whether the ETHERNET flow control busy bit is set or not.
bogdanm	92:4fc01daae5a5	1848	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1849	* @retval The new state of flow control busy status bit (SET or RESET).
bogdanm	92:4fc01daae5a5	1850	*/
bogdanm	92:4fc01daae5a5	1851	#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
bogdanm	92:4fc01daae5a5	1852
bogdanm	92:4fc01daae5a5	1853	/**
bogdanm	92:4fc01daae5a5	1854	* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
bogdanm	92:4fc01daae5a5	1855	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1856	* @retval None
bogdanm	92:4fc01daae5a5	1857	*/
bogdanm	92:4fc01daae5a5	1858	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR \|= ETH_MACFCR_FCBBPA)
bogdanm	92:4fc01daae5a5	1859
bogdanm	92:4fc01daae5a5	1860	/**
bogdanm	92:4fc01daae5a5	1861	* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
bogdanm	92:4fc01daae5a5	1862	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1863	* @retval None
bogdanm	92:4fc01daae5a5	1864	*/
bogdanm	92:4fc01daae5a5	1865	#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
bogdanm	92:4fc01daae5a5	1866
bogdanm	92:4fc01daae5a5	1867	/**
bogdanm	92:4fc01daae5a5	1868	* @brief Checks whether the specified ETHERNET MAC flag is set or not.
bogdanm	92:4fc01daae5a5	1869	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1870	* @param __FLAG__: specifies the flag to check.
bogdanm	92:4fc01daae5a5	1871	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1872	* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
bogdanm	92:4fc01daae5a5	1873	* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
bogdanm	92:4fc01daae5a5	1874	* @arg ETH_MAC_FLAG_MMCR : MMC receive flag
bogdanm	92:4fc01daae5a5	1875	* @arg ETH_MAC_FLAG_MMC : MMC flag
bogdanm	92:4fc01daae5a5	1876	* @arg ETH_MAC_FLAG_PMT : PMT flag
bogdanm	92:4fc01daae5a5	1877	* @retval The state of ETHERNET MAC flag.
bogdanm	92:4fc01daae5a5	1878	*/
bogdanm	92:4fc01daae5a5	1879	#define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
bogdanm	92:4fc01daae5a5	1880
bogdanm	92:4fc01daae5a5	1881	/**
bogdanm	92:4fc01daae5a5	1882	* @brief Enables the specified ETHERNET DMA interrupts.
bogdanm	92:4fc01daae5a5	1883	* @param __HANDLE__ : ETH Handle
bogdanm	92:4fc01daae5a5	1884	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
bogdanm	92:4fc01daae5a5	1885	* enabled @defgroup ETH_DMA_Interrupts
bogdanm	92:4fc01daae5a5	1886	* @retval None
bogdanm	92:4fc01daae5a5	1887	*/
bogdanm	92:4fc01daae5a5	1888	#define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1889
bogdanm	92:4fc01daae5a5	1890	/**
bogdanm	92:4fc01daae5a5	1891	* @brief Disables the specified ETHERNET DMA interrupts.
bogdanm	92:4fc01daae5a5	1892	* @param __HANDLE__ : ETH Handle
bogdanm	92:4fc01daae5a5	1893	* @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
bogdanm	92:4fc01daae5a5	1894	* disabled. @defgroup ETH_DMA_Interrupts
bogdanm	92:4fc01daae5a5	1895	* @retval None
bogdanm	92:4fc01daae5a5	1896	*/
bogdanm	92:4fc01daae5a5	1897	#define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1898
bogdanm	92:4fc01daae5a5	1899	/**
bogdanm	92:4fc01daae5a5	1900	* @brief Clears the ETHERNET DMA IT pending bit.
bogdanm	92:4fc01daae5a5	1901	* @param __HANDLE__ : ETH Handle
bogdanm	92:4fc01daae5a5	1902	* @param __INTERRUPT__: specifies the interrupt pending bit to clear. @defgroup ETH_DMA_Interrupts
bogdanm	92:4fc01daae5a5	1903	* @retval None
bogdanm	92:4fc01daae5a5	1904	*/
bogdanm	92:4fc01daae5a5	1905	#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
bogdanm	92:4fc01daae5a5	1906
bogdanm	92:4fc01daae5a5	1907	/**
bogdanm	92:4fc01daae5a5	1908	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
bogdanm	92:4fc01daae5a5	1909	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1910	* @param __FLAG__: specifies the flag to check. @defgroup ETH_DMA_Flags
bogdanm	92:4fc01daae5a5	1911	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
bogdanm	92:4fc01daae5a5	1912	*/
bogdanm	92:4fc01daae5a5	1913	#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
bogdanm	92:4fc01daae5a5	1914
bogdanm	92:4fc01daae5a5	1915	/**
bogdanm	92:4fc01daae5a5	1916	* @brief Checks whether the specified ETHERNET DMA flag is set or not.
bogdanm	92:4fc01daae5a5	1917	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1918	* @param __FLAG__: specifies the flag to clear. @defgroup ETH_DMA_Flags
bogdanm	92:4fc01daae5a5	1919	* @retval The new state of ETH_DMA_FLAG (SET or RESET).
bogdanm	92:4fc01daae5a5	1920	*/
bogdanm	92:4fc01daae5a5	1921	#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
bogdanm	92:4fc01daae5a5	1922
bogdanm	92:4fc01daae5a5	1923	/**
bogdanm	92:4fc01daae5a5	1924	* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
bogdanm	92:4fc01daae5a5	1925	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1926	* @param __OVERFLOW__: specifies the DMA overflow flag to check.
bogdanm	92:4fc01daae5a5	1927	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1928	* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
bogdanm	92:4fc01daae5a5	1929	* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
bogdanm	92:4fc01daae5a5	1930	* @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
bogdanm	92:4fc01daae5a5	1931	*/
bogdanm	92:4fc01daae5a5	1932	#define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
bogdanm	92:4fc01daae5a5	1933
bogdanm	92:4fc01daae5a5	1934	/**
bogdanm	92:4fc01daae5a5	1935	* @brief Set the DMA Receive status watchdog timer register value
bogdanm	92:4fc01daae5a5	1936	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1937	* @param __VALUE__: DMA Receive status watchdog timer register value
bogdanm	92:4fc01daae5a5	1938	* @retval None
bogdanm	92:4fc01daae5a5	1939	*/
bogdanm	92:4fc01daae5a5	1940	#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
bogdanm	92:4fc01daae5a5	1941
bogdanm	92:4fc01daae5a5	1942	/**
bogdanm	92:4fc01daae5a5	1943	* @brief Enables any unicast packet filtered by the MAC address
bogdanm	92:4fc01daae5a5	1944	* recognition to be a wake-up frame.
bogdanm	92:4fc01daae5a5	1945	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	1946	* @retval None
bogdanm	92:4fc01daae5a5	1947	*/
bogdanm	92:4fc01daae5a5	1948	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_GU)
bogdanm	92:4fc01daae5a5	1949
bogdanm	92:4fc01daae5a5	1950	/**
bogdanm	92:4fc01daae5a5	1951	* @brief Disables any unicast packet filtered by the MAC address
bogdanm	92:4fc01daae5a5	1952	* recognition to be a wake-up frame.
bogdanm	92:4fc01daae5a5	1953	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	1954	* @retval None
bogdanm	92:4fc01daae5a5	1955	*/
bogdanm	92:4fc01daae5a5	1956	#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
bogdanm	92:4fc01daae5a5	1957
bogdanm	92:4fc01daae5a5	1958	/**
bogdanm	92:4fc01daae5a5	1959	* @brief Enables the MAC Wake-Up Frame Detection.
bogdanm	92:4fc01daae5a5	1960	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	1961	* @retval None
bogdanm	92:4fc01daae5a5	1962	*/
bogdanm	92:4fc01daae5a5	1963	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_WFE)
bogdanm	92:4fc01daae5a5	1964
bogdanm	92:4fc01daae5a5	1965	/**
bogdanm	92:4fc01daae5a5	1966	* @brief Disables the MAC Wake-Up Frame Detection.
bogdanm	92:4fc01daae5a5	1967	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	1968	* @retval None
bogdanm	92:4fc01daae5a5	1969	*/
bogdanm	92:4fc01daae5a5	1970	#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
bogdanm	92:4fc01daae5a5	1971
bogdanm	92:4fc01daae5a5	1972	/**
bogdanm	92:4fc01daae5a5	1973	* @brief Enables the MAC Magic Packet Detection.
bogdanm	92:4fc01daae5a5	1974	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	1975	* @retval None
bogdanm	92:4fc01daae5a5	1976	*/
bogdanm	92:4fc01daae5a5	1977	#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_MPE)
bogdanm	92:4fc01daae5a5	1978
bogdanm	92:4fc01daae5a5	1979	/**
bogdanm	92:4fc01daae5a5	1980	* @brief Disables the MAC Magic Packet Detection.
bogdanm	92:4fc01daae5a5	1981	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	1982	* @retval None
bogdanm	92:4fc01daae5a5	1983	*/
bogdanm	92:4fc01daae5a5	1984	#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
bogdanm	92:4fc01daae5a5	1985
bogdanm	92:4fc01daae5a5	1986	/**
bogdanm	92:4fc01daae5a5	1987	* @brief Enables the MAC Power Down.
bogdanm	92:4fc01daae5a5	1988	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1989	* @retval None
bogdanm	92:4fc01daae5a5	1990	*/
bogdanm	92:4fc01daae5a5	1991	#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR \|= ETH_MACPMTCSR_PD)
bogdanm	92:4fc01daae5a5	1992
bogdanm	92:4fc01daae5a5	1993	/**
bogdanm	92:4fc01daae5a5	1994	* @brief Disables the MAC Power Down.
bogdanm	92:4fc01daae5a5	1995	* @param __HANDLE__: ETH Handle
bogdanm	92:4fc01daae5a5	1996	* @retval None
bogdanm	92:4fc01daae5a5	1997	*/
bogdanm	92:4fc01daae5a5	1998	#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
bogdanm	92:4fc01daae5a5	1999
bogdanm	92:4fc01daae5a5	2000	/**
bogdanm	92:4fc01daae5a5	2001	* @brief Checks whether the specified ETHERNET PMT flag is set or not.
bogdanm	92:4fc01daae5a5	2002	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2003	* @param __FLAG__: specifies the flag to check.
bogdanm	92:4fc01daae5a5	2004	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	2005	* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
bogdanm	92:4fc01daae5a5	2006	* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
bogdanm	92:4fc01daae5a5	2007	* @arg ETH_PMT_FLAG_MPR : Magic Packet Received
bogdanm	92:4fc01daae5a5	2008	* @retval The new state of ETHERNET PMT Flag (SET or RESET).
bogdanm	92:4fc01daae5a5	2009	*/
bogdanm	92:4fc01daae5a5	2010	#define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
bogdanm	92:4fc01daae5a5	2011
bogdanm	92:4fc01daae5a5	2012	/**
bogdanm	92:4fc01daae5a5	2013	* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
bogdanm	92:4fc01daae5a5	2014	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2015	* @retval None
bogdanm	92:4fc01daae5a5	2016	*/
bogdanm	92:4fc01daae5a5	2017	#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= (ETH_MMCCR_MCFHP \| ETH_MMCCR_MCP))
bogdanm	92:4fc01daae5a5	2018
bogdanm	92:4fc01daae5a5	2019	/**
bogdanm	92:4fc01daae5a5	2020	* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
bogdanm	92:4fc01daae5a5	2021	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2022	* @retval None
bogdanm	92:4fc01daae5a5	2023	*/
bogdanm	92:4fc01daae5a5	2024	#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
bogdanm	92:4fc01daae5a5	2025	(__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCP;} while (0)
bogdanm	92:4fc01daae5a5	2026
bogdanm	92:4fc01daae5a5	2027	/**
bogdanm	92:4fc01daae5a5	2028	* @brief Enables the MMC Counter Freeze.
bogdanm	92:4fc01daae5a5	2029	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2030	* @retval None
bogdanm	92:4fc01daae5a5	2031	*/
bogdanm	92:4fc01daae5a5	2032	#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_MCF)
bogdanm	92:4fc01daae5a5	2033
bogdanm	92:4fc01daae5a5	2034	/**
bogdanm	92:4fc01daae5a5	2035	* @brief Disables the MMC Counter Freeze.
bogdanm	92:4fc01daae5a5	2036	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2037	* @retval None
bogdanm	92:4fc01daae5a5	2038	*/
bogdanm	92:4fc01daae5a5	2039	#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
bogdanm	92:4fc01daae5a5	2040
bogdanm	92:4fc01daae5a5	2041	/**
bogdanm	92:4fc01daae5a5	2042	* @brief Enables the MMC Reset On Read.
bogdanm	92:4fc01daae5a5	2043	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2044	* @retval None
bogdanm	92:4fc01daae5a5	2045	*/
bogdanm	92:4fc01daae5a5	2046	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_ROR)
bogdanm	92:4fc01daae5a5	2047
bogdanm	92:4fc01daae5a5	2048	/**
bogdanm	92:4fc01daae5a5	2049	* @brief Disables the MMC Reset On Read.
bogdanm	92:4fc01daae5a5	2050	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2051	* @retval None
bogdanm	92:4fc01daae5a5	2052	*/
bogdanm	92:4fc01daae5a5	2053	#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
bogdanm	92:4fc01daae5a5	2054
bogdanm	92:4fc01daae5a5	2055	/**
bogdanm	92:4fc01daae5a5	2056	* @brief Enables the MMC Counter Stop Rollover.
bogdanm	92:4fc01daae5a5	2057	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2058	* @retval None
bogdanm	92:4fc01daae5a5	2059	*/
bogdanm	92:4fc01daae5a5	2060	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
bogdanm	92:4fc01daae5a5	2061
bogdanm	92:4fc01daae5a5	2062	/**
bogdanm	92:4fc01daae5a5	2063	* @brief Disables the MMC Counter Stop Rollover.
bogdanm	92:4fc01daae5a5	2064	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2065	* @retval None
bogdanm	92:4fc01daae5a5	2066	*/
bogdanm	92:4fc01daae5a5	2067	#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CSR)
bogdanm	92:4fc01daae5a5	2068
bogdanm	92:4fc01daae5a5	2069	/**
bogdanm	92:4fc01daae5a5	2070	* @brief Resets the MMC Counters.
bogdanm	92:4fc01daae5a5	2071	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2072	* @retval None
bogdanm	92:4fc01daae5a5	2073	*/
bogdanm	92:4fc01daae5a5	2074	#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR \|= ETH_MMCCR_CR)
bogdanm	92:4fc01daae5a5	2075
bogdanm	92:4fc01daae5a5	2076	/**
bogdanm	92:4fc01daae5a5	2077	* @brief Enables the specified ETHERNET MMC Rx interrupts.
bogdanm	92:4fc01daae5a5	2078	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2079	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm	92:4fc01daae5a5	2080	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	2081	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2082	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2083	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2084	* @retval None
bogdanm	92:4fc01daae5a5	2085	*/
bogdanm	92:4fc01daae5a5	2086	#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
bogdanm	92:4fc01daae5a5	2087	/**
bogdanm	92:4fc01daae5a5	2088	* @brief Disables the specified ETHERNET MMC Rx interrupts.
bogdanm	92:4fc01daae5a5	2089	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2090	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm	92:4fc01daae5a5	2091	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	2092	* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2093	* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2094	* @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2095	* @retval None
bogdanm	92:4fc01daae5a5	2096	*/
bogdanm	92:4fc01daae5a5	2097	#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR \|= ((__INTERRUPT__) & 0xEFFFFFFF)
bogdanm	92:4fc01daae5a5	2098	/**
bogdanm	92:4fc01daae5a5	2099	* @brief Enables the specified ETHERNET MMC Tx interrupts.
bogdanm	92:4fc01daae5a5	2100	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2101	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm	92:4fc01daae5a5	2102	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	2103	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2104	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2105	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2106	* @retval None
bogdanm	92:4fc01daae5a5	2107	*/
bogdanm	92:4fc01daae5a5	2108	#define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	2109
bogdanm	92:4fc01daae5a5	2110	/**
bogdanm	92:4fc01daae5a5	2111	* @brief Disables the specified ETHERNET MMC Tx interrupts.
bogdanm	92:4fc01daae5a5	2112	* @param __HANDLE__: ETH Handle.
bogdanm	92:4fc01daae5a5	2113	* @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
bogdanm	92:4fc01daae5a5	2114	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	2115	* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2116	* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2117	* @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
bogdanm	92:4fc01daae5a5	2118	* @retval None
bogdanm	92:4fc01daae5a5	2119	*/
bogdanm	92:4fc01daae5a5	2120	#define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR \|= (__INTERRUPT__))
bogdanm	92:4fc01daae5a5	2121
bogdanm	92:4fc01daae5a5	2122	/** @defgroup ETH_EXTI_LINE_WAKEUP
bogdanm	92:4fc01daae5a5	2123	* @{
bogdanm	92:4fc01daae5a5	2124	*/
bogdanm	92:4fc01daae5a5	2125	#define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /!< External interrupt line 19 Connected to the ETH EXTI Line /
bogdanm	92:4fc01daae5a5	2126
bogdanm	92:4fc01daae5a5	2127	/**
bogdanm	92:4fc01daae5a5	2128	* @}
bogdanm	92:4fc01daae5a5	2129	*/
bogdanm	92:4fc01daae5a5	2130
bogdanm	92:4fc01daae5a5	2131	/**
bogdanm	92:4fc01daae5a5	2132	* @brief Enables the ETH External interrupt line.
bogdanm	92:4fc01daae5a5	2133	* @param None
bogdanm	92:4fc01daae5a5	2134	* @retval None
bogdanm	92:4fc01daae5a5	2135	*/
bogdanm	92:4fc01daae5a5	2136	#define __HAL_ETH_EXTI_ENABLE_IT() EXTI->IMR \|= (ETH_EXTI_LINE_WAKEUP)
bogdanm	92:4fc01daae5a5	2137
bogdanm	92:4fc01daae5a5	2138	/**
bogdanm	92:4fc01daae5a5	2139	* @brief Disables the ETH External interrupt line.
bogdanm	92:4fc01daae5a5	2140	* @param None
bogdanm	92:4fc01daae5a5	2141	* @retval None
bogdanm	92:4fc01daae5a5	2142	*/
bogdanm	92:4fc01daae5a5	2143	#define __HAL_ETH_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
bogdanm	92:4fc01daae5a5	2144
bogdanm	92:4fc01daae5a5	2145	/**
bogdanm	92:4fc01daae5a5	2146	* @brief Get flag of the ETH External interrupt line.
bogdanm	92:4fc01daae5a5	2147	* @param None
bogdanm	92:4fc01daae5a5	2148	* @retval None
bogdanm	92:4fc01daae5a5	2149	*/
bogdanm	92:4fc01daae5a5	2150	#define __HAL_ETH_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
bogdanm	92:4fc01daae5a5	2151
bogdanm	92:4fc01daae5a5	2152	/**
bogdanm	92:4fc01daae5a5	2153	* @brief Clear flag of the ETH External interrupt line.
bogdanm	92:4fc01daae5a5	2154	* @param None
bogdanm	92:4fc01daae5a5	2155	* @retval None
bogdanm	92:4fc01daae5a5	2156	*/
bogdanm	92:4fc01daae5a5	2157	#define __HAL_ETH_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
bogdanm	92:4fc01daae5a5	2158
bogdanm	92:4fc01daae5a5	2159	/**
bogdanm	92:4fc01daae5a5	2160	* @brief Sets rising edge trigger to the ETH External interrupt line.
bogdanm	92:4fc01daae5a5	2161	* @param None
bogdanm	92:4fc01daae5a5	2162	* @retval None
bogdanm	92:4fc01daae5a5	2163	*/
bogdanm	92:4fc01daae5a5	2164	#define __HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
bogdanm	92:4fc01daae5a5	2165	EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP
bogdanm	92:4fc01daae5a5	2166
bogdanm	92:4fc01daae5a5	2167	/**
bogdanm	92:4fc01daae5a5	2168	* @brief Sets falling edge trigger to the ETH External interrupt line.
bogdanm	92:4fc01daae5a5	2169	* @param None
bogdanm	92:4fc01daae5a5	2170	* @retval None
bogdanm	92:4fc01daae5a5	2171	*/
bogdanm	92:4fc01daae5a5	2172	#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR \|= (ETH_EXTI_LINE_WAKEUP);\
bogdanm	92:4fc01daae5a5	2173	EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
bogdanm	92:4fc01daae5a5	2174
bogdanm	92:4fc01daae5a5	2175	/**
bogdanm	92:4fc01daae5a5	2176	* @brief Sets rising/falling edge trigger to the ETH External interrupt line.
bogdanm	92:4fc01daae5a5	2177	* @param None
bogdanm	92:4fc01daae5a5	2178	* @retval None
bogdanm	92:4fc01daae5a5	2179	*/
bogdanm	92:4fc01daae5a5	2180	#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
bogdanm	92:4fc01daae5a5	2181	EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
bogdanm	92:4fc01daae5a5	2182	EXTI->RTSR \|= ETH_EXTI_LINE_WAKEUP;\
bogdanm	92:4fc01daae5a5	2183	EXTI->FTSR \|= ETH_EXTI_LINE_WAKEUP
bogdanm	92:4fc01daae5a5	2184
bogdanm	92:4fc01daae5a5	2185	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	2186
bogdanm	92:4fc01daae5a5	2187	/* Initialization and de-initialization functions ****************************/
bogdanm	92:4fc01daae5a5	2188	HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2189	HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2190	void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2191	void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2192	HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
bogdanm	92:4fc01daae5a5	2193	HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef heth, ETH_DMADescTypeDef DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
bogdanm	92:4fc01daae5a5	2194
bogdanm	92:4fc01daae5a5	2195	/* IO operation functions ****************************************************/
bogdanm	92:4fc01daae5a5	2196	HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
bogdanm	92:4fc01daae5a5	2197	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2198
bogdanm	92:4fc01daae5a5	2199	/* Non-Blocking mode: Interrupt */
bogdanm	92:4fc01daae5a5	2200	HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2201	void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2202
bogdanm	92:4fc01daae5a5	2203	/* Callback in non blocking modes (Interrupt) */
bogdanm	92:4fc01daae5a5	2204	void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2205	void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2206	void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2207
bogdanm	92:4fc01daae5a5	2208	/* Cmmunication with PHY functions*/
bogdanm	92:4fc01daae5a5	2209	HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef heth, uint16_t PHYReg, uint32_t RegValue);
bogdanm	92:4fc01daae5a5	2210	HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
bogdanm	92:4fc01daae5a5	2211
bogdanm	92:4fc01daae5a5	2212	/* Peripheral Control functions **********************************************/
bogdanm	92:4fc01daae5a5	2213	HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2214	HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2215
bogdanm	92:4fc01daae5a5	2216	HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef heth, ETH_MACInitTypeDef macconf);
bogdanm	92:4fc01daae5a5	2217	HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef heth, ETH_DMAInitTypeDef dmaconf);
bogdanm	92:4fc01daae5a5	2218
bogdanm	92:4fc01daae5a5	2219	/* Peripheral State functions ************************************************/
bogdanm	92:4fc01daae5a5	2220	HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
bogdanm	92:4fc01daae5a5	2221
bogdanm	92:4fc01daae5a5	2222	#endif /* STM32F405xx \|\| STM32F415xx \|\| STM32F407xx \|\| STM32F417xx \|\| STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
bogdanm	92:4fc01daae5a5	2223	/**
bogdanm	92:4fc01daae5a5	2224	* @}
bogdanm	92:4fc01daae5a5	2225	*/
bogdanm	92:4fc01daae5a5	2226
bogdanm	92:4fc01daae5a5	2227	/**
bogdanm	92:4fc01daae5a5	2228	* @}
bogdanm	92:4fc01daae5a5	2229	*/
bogdanm	92:4fc01daae5a5	2230
bogdanm	92:4fc01daae5a5	2231	#ifdef __cplusplus
bogdanm	92:4fc01daae5a5	2232	}
bogdanm	92:4fc01daae5a5	2233	#endif
bogdanm	92:4fc01daae5a5	2234
bogdanm	92:4fc01daae5a5	2235	#endif /* __STM32F4xx_HAL_ETH_H */
bogdanm	92:4fc01daae5a5	2236
bogdanm	92:4fc01daae5a5	2237
bogdanm	92:4fc01daae5a5	2238
bogdanm	92:4fc01daae5a5	2239	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	05 Apr 2016
Imports:	0
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Commits:	119
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TARGET_MTS_MDOT_F405RG/stm32f4xx_hal_eth.h@118:16969dd821af, 2016-04-05 (annotated)

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