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TARGET_LPC4337/core_cm4.h@118:16969dd821af, 2016-04-05 (annotated)

Committer:
ricardobtez
Date:
Tue Apr 05 23:51:21 2016 +0000
Revision:
118:16969dd821af
Parent:
89:552587b429a1
Child:
110:165afa46840b
dgdgr

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 88:9327015d4013 1 /**************************************************************************//**
bogdanm 88:9327015d4013 2 * @file core_cm4.h
bogdanm 88:9327015d4013 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
bogdanm 88:9327015d4013 4 * @version V3.20
bogdanm 88:9327015d4013 5 * @date 25. February 2013
bogdanm 88:9327015d4013 6 *
bogdanm 88:9327015d4013 7 * @note
bogdanm 88:9327015d4013 8 *
bogdanm 88:9327015d4013 9 ******************************************************************************/
bogdanm 88:9327015d4013 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
bogdanm 88:9327015d4013 11
bogdanm 88:9327015d4013 12 All rights reserved.
bogdanm 88:9327015d4013 13 Redistribution and use in source and binary forms, with or without
bogdanm 88:9327015d4013 14 modification, are permitted provided that the following conditions are met:
bogdanm 88:9327015d4013 15 - Redistributions of source code must retain the above copyright
bogdanm 88:9327015d4013 16 notice, this list of conditions and the following disclaimer.
bogdanm 88:9327015d4013 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 88:9327015d4013 18 notice, this list of conditions and the following disclaimer in the
bogdanm 88:9327015d4013 19 documentation and/or other materials provided with the distribution.
bogdanm 88:9327015d4013 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 88:9327015d4013 21 to endorse or promote products derived from this software without
bogdanm 88:9327015d4013 22 specific prior written permission.
bogdanm 88:9327015d4013 23 *
bogdanm 88:9327015d4013 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 88:9327015d4013 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 88:9327015d4013 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 88:9327015d4013 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 88:9327015d4013 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 88:9327015d4013 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 88:9327015d4013 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 88:9327015d4013 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 88:9327015d4013 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 88:9327015d4013 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 88:9327015d4013 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 88:9327015d4013 35 ---------------------------------------------------------------------------*/
bogdanm 88:9327015d4013 36
bogdanm 88:9327015d4013 37
bogdanm 88:9327015d4013 38 #if defined ( __ICCARM__ )
bogdanm 88:9327015d4013 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 88:9327015d4013 40 #endif
bogdanm 88:9327015d4013 41
bogdanm 88:9327015d4013 42 #ifdef __cplusplus
bogdanm 88:9327015d4013 43 extern "C" {
bogdanm 88:9327015d4013 44 #endif
bogdanm 88:9327015d4013 45
bogdanm 88:9327015d4013 46 #ifndef __CORE_CM4_H_GENERIC
bogdanm 88:9327015d4013 47 #define __CORE_CM4_H_GENERIC
bogdanm 88:9327015d4013 48
bogdanm 88:9327015d4013 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 88:9327015d4013 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 88:9327015d4013 51
bogdanm 88:9327015d4013 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 88:9327015d4013 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 88:9327015d4013 54
bogdanm 88:9327015d4013 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 88:9327015d4013 56 Unions are used for effective representation of core registers.
bogdanm 88:9327015d4013 57
bogdanm 88:9327015d4013 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 88:9327015d4013 59 Function-like macros are used to allow more efficient code.
bogdanm 88:9327015d4013 60 */
bogdanm 88:9327015d4013 61
bogdanm 88:9327015d4013 62
bogdanm 88:9327015d4013 63 /*******************************************************************************
bogdanm 88:9327015d4013 64 * CMSIS definitions
bogdanm 88:9327015d4013 65 ******************************************************************************/
bogdanm 88:9327015d4013 66 /** \ingroup Cortex_M4
bogdanm 88:9327015d4013 67 @{
bogdanm 88:9327015d4013 68 */
bogdanm 88:9327015d4013 69
bogdanm 88:9327015d4013 70 /* CMSIS CM4 definitions */
bogdanm 88:9327015d4013 71 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
bogdanm 88:9327015d4013 72 #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 88:9327015d4013 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
bogdanm 88:9327015d4013 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 88:9327015d4013 75
bogdanm 88:9327015d4013 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
bogdanm 88:9327015d4013 77
bogdanm 88:9327015d4013 78
bogdanm 88:9327015d4013 79 #if defined ( __CC_ARM )
bogdanm 88:9327015d4013 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 88:9327015d4013 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 88:9327015d4013 82 #define __STATIC_INLINE static __inline
bogdanm 88:9327015d4013 83
bogdanm 88:9327015d4013 84 #elif defined ( __ICCARM__ )
bogdanm 88:9327015d4013 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 88:9327015d4013 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 88:9327015d4013 87 #define __STATIC_INLINE static inline
bogdanm 88:9327015d4013 88
bogdanm 88:9327015d4013 89 #elif defined ( __TMS470__ )
bogdanm 88:9327015d4013 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 88:9327015d4013 91 #define __STATIC_INLINE static inline
bogdanm 88:9327015d4013 92
bogdanm 88:9327015d4013 93 #elif defined ( __GNUC__ )
bogdanm 88:9327015d4013 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 88:9327015d4013 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 88:9327015d4013 96 #define __STATIC_INLINE static inline
bogdanm 88:9327015d4013 97
bogdanm 88:9327015d4013 98 #elif defined ( __TASKING__ )
bogdanm 88:9327015d4013 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 88:9327015d4013 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 88:9327015d4013 101 #define __STATIC_INLINE static inline
bogdanm 88:9327015d4013 102
bogdanm 88:9327015d4013 103 #endif
bogdanm 88:9327015d4013 104
bogdanm 88:9327015d4013 105 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
bogdanm 88:9327015d4013 106 */
bogdanm 88:9327015d4013 107 #if defined ( __CC_ARM )
bogdanm 88:9327015d4013 108 #if defined __TARGET_FPU_VFP
bogdanm 88:9327015d4013 109 #if (__FPU_PRESENT == 1)
bogdanm 88:9327015d4013 110 #define __FPU_USED 1
bogdanm 88:9327015d4013 111 #else
bogdanm 88:9327015d4013 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 88:9327015d4013 113 #define __FPU_USED 0
bogdanm 88:9327015d4013 114 #endif
bogdanm 88:9327015d4013 115 #else
bogdanm 88:9327015d4013 116 #define __FPU_USED 0
bogdanm 88:9327015d4013 117 #endif
bogdanm 88:9327015d4013 118
bogdanm 88:9327015d4013 119 #elif defined ( __ICCARM__ )
bogdanm 88:9327015d4013 120 #if defined __ARMVFP__
bogdanm 88:9327015d4013 121 #if (__FPU_PRESENT == 1)
bogdanm 88:9327015d4013 122 #define __FPU_USED 1
bogdanm 88:9327015d4013 123 #else
bogdanm 88:9327015d4013 124 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 88:9327015d4013 125 #define __FPU_USED 0
bogdanm 88:9327015d4013 126 #endif
bogdanm 88:9327015d4013 127 #else
bogdanm 88:9327015d4013 128 #define __FPU_USED 0
bogdanm 88:9327015d4013 129 #endif
bogdanm 88:9327015d4013 130
bogdanm 88:9327015d4013 131 #elif defined ( __TMS470__ )
bogdanm 88:9327015d4013 132 #if defined __TI_VFP_SUPPORT__
bogdanm 88:9327015d4013 133 #if (__FPU_PRESENT == 1)
bogdanm 88:9327015d4013 134 #define __FPU_USED 1
bogdanm 88:9327015d4013 135 #else
bogdanm 88:9327015d4013 136 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 88:9327015d4013 137 #define __FPU_USED 0
bogdanm 88:9327015d4013 138 #endif
bogdanm 88:9327015d4013 139 #else
bogdanm 88:9327015d4013 140 #define __FPU_USED 0
bogdanm 88:9327015d4013 141 #endif
bogdanm 88:9327015d4013 142
bogdanm 88:9327015d4013 143 #elif defined ( __GNUC__ )
bogdanm 88:9327015d4013 144 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
bogdanm 88:9327015d4013 145 #if (__FPU_PRESENT == 1)
bogdanm 88:9327015d4013 146 #define __FPU_USED 1
bogdanm 88:9327015d4013 147 #else
bogdanm 88:9327015d4013 148 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 88:9327015d4013 149 #define __FPU_USED 0
bogdanm 88:9327015d4013 150 #endif
bogdanm 88:9327015d4013 151 #else
bogdanm 88:9327015d4013 152 #define __FPU_USED 0
bogdanm 88:9327015d4013 153 #endif
bogdanm 88:9327015d4013 154
bogdanm 88:9327015d4013 155 #elif defined ( __TASKING__ )
bogdanm 88:9327015d4013 156 #if defined __FPU_VFP__
bogdanm 88:9327015d4013 157 #if (__FPU_PRESENT == 1)
bogdanm 88:9327015d4013 158 #define __FPU_USED 1
bogdanm 88:9327015d4013 159 #else
bogdanm 88:9327015d4013 160 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 88:9327015d4013 161 #define __FPU_USED 0
bogdanm 88:9327015d4013 162 #endif
bogdanm 88:9327015d4013 163 #else
bogdanm 88:9327015d4013 164 #define __FPU_USED 0
bogdanm 88:9327015d4013 165 #endif
bogdanm 88:9327015d4013 166 #endif
bogdanm 88:9327015d4013 167
bogdanm 88:9327015d4013 168 #include <stdint.h> /* standard types definitions */
bogdanm 88:9327015d4013 169 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 88:9327015d4013 170 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 88:9327015d4013 171 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
bogdanm 88:9327015d4013 172
bogdanm 88:9327015d4013 173 #endif /* __CORE_CM4_H_GENERIC */
bogdanm 88:9327015d4013 174
bogdanm 88:9327015d4013 175 #ifndef __CMSIS_GENERIC
bogdanm 88:9327015d4013 176
bogdanm 88:9327015d4013 177 #ifndef __CORE_CM4_H_DEPENDANT
bogdanm 88:9327015d4013 178 #define __CORE_CM4_H_DEPENDANT
bogdanm 88:9327015d4013 179
bogdanm 88:9327015d4013 180 /* check device defines and use defaults */
bogdanm 88:9327015d4013 181 #if defined __CHECK_DEVICE_DEFINES
bogdanm 88:9327015d4013 182 #ifndef __CM4_REV
bogdanm 88:9327015d4013 183 #define __CM4_REV 0x0000
bogdanm 88:9327015d4013 184 #warning "__CM4_REV not defined in device header file; using default!"
bogdanm 88:9327015d4013 185 #endif
bogdanm 88:9327015d4013 186
bogdanm 88:9327015d4013 187 #ifndef __FPU_PRESENT
bogdanm 88:9327015d4013 188 #define __FPU_PRESENT 0
bogdanm 88:9327015d4013 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
bogdanm 88:9327015d4013 190 #endif
bogdanm 88:9327015d4013 191
bogdanm 88:9327015d4013 192 #ifndef __MPU_PRESENT
bogdanm 88:9327015d4013 193 #define __MPU_PRESENT 0
bogdanm 88:9327015d4013 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
bogdanm 88:9327015d4013 195 #endif
bogdanm 88:9327015d4013 196
bogdanm 88:9327015d4013 197 #ifndef __NVIC_PRIO_BITS
bogdanm 88:9327015d4013 198 #define __NVIC_PRIO_BITS 4
bogdanm 88:9327015d4013 199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 88:9327015d4013 200 #endif
bogdanm 88:9327015d4013 201
bogdanm 88:9327015d4013 202 #ifndef __Vendor_SysTickConfig
bogdanm 88:9327015d4013 203 #define __Vendor_SysTickConfig 0
bogdanm 88:9327015d4013 204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 88:9327015d4013 205 #endif
bogdanm 88:9327015d4013 206 #endif
bogdanm 88:9327015d4013 207
bogdanm 88:9327015d4013 208 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 88:9327015d4013 209 /**
bogdanm 88:9327015d4013 210 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 88:9327015d4013 211
bogdanm 88:9327015d4013 212 <strong>IO Type Qualifiers</strong> are used
bogdanm 88:9327015d4013 213 \li to specify the access to peripheral variables.
bogdanm 88:9327015d4013 214 \li for automatic generation of peripheral register debug information.
bogdanm 88:9327015d4013 215 */
bogdanm 88:9327015d4013 216 #ifdef __cplusplus
bogdanm 88:9327015d4013 217 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 88:9327015d4013 218 #else
bogdanm 88:9327015d4013 219 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 88:9327015d4013 220 #endif
bogdanm 88:9327015d4013 221 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 88:9327015d4013 222 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 88:9327015d4013 223
bogdanm 88:9327015d4013 224 /*@} end of group Cortex_M4 */
bogdanm 88:9327015d4013 225
bogdanm 88:9327015d4013 226
bogdanm 88:9327015d4013 227
bogdanm 88:9327015d4013 228 /*******************************************************************************
bogdanm 88:9327015d4013 229 * Register Abstraction
bogdanm 88:9327015d4013 230 Core Register contain:
bogdanm 88:9327015d4013 231 - Core Register
bogdanm 88:9327015d4013 232 - Core NVIC Register
bogdanm 88:9327015d4013 233 - Core SCB Register
bogdanm 88:9327015d4013 234 - Core SysTick Register
bogdanm 88:9327015d4013 235 - Core Debug Register
bogdanm 88:9327015d4013 236 - Core MPU Register
bogdanm 88:9327015d4013 237 - Core FPU Register
bogdanm 88:9327015d4013 238 ******************************************************************************/
bogdanm 88:9327015d4013 239 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 88:9327015d4013 240 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 88:9327015d4013 241 */
bogdanm 88:9327015d4013 242
bogdanm 88:9327015d4013 243 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 244 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 88:9327015d4013 245 \brief Core Register type definitions.
bogdanm 88:9327015d4013 246 @{
bogdanm 88:9327015d4013 247 */
bogdanm 88:9327015d4013 248
bogdanm 88:9327015d4013 249 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 88:9327015d4013 250 */
bogdanm 88:9327015d4013 251 typedef union
bogdanm 88:9327015d4013 252 {
bogdanm 88:9327015d4013 253 struct
bogdanm 88:9327015d4013 254 {
bogdanm 88:9327015d4013 255 #if (__CORTEX_M != 0x04)
bogdanm 88:9327015d4013 256 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
bogdanm 88:9327015d4013 257 #else
bogdanm 88:9327015d4013 258 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
bogdanm 88:9327015d4013 259 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 88:9327015d4013 260 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
bogdanm 88:9327015d4013 261 #endif
bogdanm 88:9327015d4013 262 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 88:9327015d4013 263 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 88:9327015d4013 264 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 88:9327015d4013 265 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 88:9327015d4013 266 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 88:9327015d4013 267 } b; /*!< Structure used for bit access */
bogdanm 88:9327015d4013 268 uint32_t w; /*!< Type used for word access */
bogdanm 88:9327015d4013 269 } APSR_Type;
bogdanm 88:9327015d4013 270
bogdanm 88:9327015d4013 271
bogdanm 88:9327015d4013 272 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 88:9327015d4013 273 */
bogdanm 88:9327015d4013 274 typedef union
bogdanm 88:9327015d4013 275 {
bogdanm 88:9327015d4013 276 struct
bogdanm 88:9327015d4013 277 {
bogdanm 88:9327015d4013 278 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 88:9327015d4013 279 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 88:9327015d4013 280 } b; /*!< Structure used for bit access */
bogdanm 88:9327015d4013 281 uint32_t w; /*!< Type used for word access */
bogdanm 88:9327015d4013 282 } IPSR_Type;
bogdanm 88:9327015d4013 283
bogdanm 88:9327015d4013 284
bogdanm 88:9327015d4013 285 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 88:9327015d4013 286 */
bogdanm 88:9327015d4013 287 typedef union
bogdanm 88:9327015d4013 288 {
bogdanm 88:9327015d4013 289 struct
bogdanm 88:9327015d4013 290 {
bogdanm 88:9327015d4013 291 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 88:9327015d4013 292 #if (__CORTEX_M != 0x04)
bogdanm 88:9327015d4013 293 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 88:9327015d4013 294 #else
bogdanm 88:9327015d4013 295 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
bogdanm 88:9327015d4013 296 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
bogdanm 88:9327015d4013 297 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
bogdanm 88:9327015d4013 298 #endif
bogdanm 88:9327015d4013 299 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
bogdanm 88:9327015d4013 300 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
bogdanm 88:9327015d4013 301 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
bogdanm 88:9327015d4013 302 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 88:9327015d4013 303 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 88:9327015d4013 304 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 88:9327015d4013 305 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 88:9327015d4013 306 } b; /*!< Structure used for bit access */
bogdanm 88:9327015d4013 307 uint32_t w; /*!< Type used for word access */
bogdanm 88:9327015d4013 308 } xPSR_Type;
bogdanm 88:9327015d4013 309
bogdanm 88:9327015d4013 310
bogdanm 88:9327015d4013 311 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 88:9327015d4013 312 */
bogdanm 88:9327015d4013 313 typedef union
bogdanm 88:9327015d4013 314 {
bogdanm 88:9327015d4013 315 struct
bogdanm 88:9327015d4013 316 {
bogdanm 88:9327015d4013 317 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
bogdanm 88:9327015d4013 318 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
bogdanm 88:9327015d4013 319 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
bogdanm 88:9327015d4013 320 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
bogdanm 88:9327015d4013 321 } b; /*!< Structure used for bit access */
bogdanm 88:9327015d4013 322 uint32_t w; /*!< Type used for word access */
bogdanm 88:9327015d4013 323 } CONTROL_Type;
bogdanm 88:9327015d4013 324
bogdanm 88:9327015d4013 325 /*@} end of group CMSIS_CORE */
bogdanm 88:9327015d4013 326
bogdanm 88:9327015d4013 327
bogdanm 88:9327015d4013 328 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 329 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 88:9327015d4013 330 \brief Type definitions for the NVIC Registers
bogdanm 88:9327015d4013 331 @{
bogdanm 88:9327015d4013 332 */
bogdanm 88:9327015d4013 333
bogdanm 88:9327015d4013 334 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 88:9327015d4013 335 */
bogdanm 88:9327015d4013 336 typedef struct
bogdanm 88:9327015d4013 337 {
bogdanm 88:9327015d4013 338 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 88:9327015d4013 339 uint32_t RESERVED0[24];
bogdanm 88:9327015d4013 340 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 88:9327015d4013 341 uint32_t RSERVED1[24];
bogdanm 88:9327015d4013 342 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 88:9327015d4013 343 uint32_t RESERVED2[24];
bogdanm 88:9327015d4013 344 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 88:9327015d4013 345 uint32_t RESERVED3[24];
bogdanm 88:9327015d4013 346 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
bogdanm 88:9327015d4013 347 uint32_t RESERVED4[56];
bogdanm 88:9327015d4013 348 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
bogdanm 88:9327015d4013 349 uint32_t RESERVED5[644];
bogdanm 88:9327015d4013 350 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
bogdanm 88:9327015d4013 351 } NVIC_Type;
bogdanm 88:9327015d4013 352
bogdanm 88:9327015d4013 353 /* Software Triggered Interrupt Register Definitions */
bogdanm 88:9327015d4013 354 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
bogdanm 88:9327015d4013 355 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
bogdanm 88:9327015d4013 356
bogdanm 88:9327015d4013 357 /*@} end of group CMSIS_NVIC */
bogdanm 88:9327015d4013 358
bogdanm 88:9327015d4013 359
bogdanm 88:9327015d4013 360 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 361 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 88:9327015d4013 362 \brief Type definitions for the System Control Block Registers
bogdanm 88:9327015d4013 363 @{
bogdanm 88:9327015d4013 364 */
bogdanm 88:9327015d4013 365
bogdanm 88:9327015d4013 366 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 88:9327015d4013 367 */
bogdanm 88:9327015d4013 368 typedef struct
bogdanm 88:9327015d4013 369 {
bogdanm 88:9327015d4013 370 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 88:9327015d4013 371 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 88:9327015d4013 372 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
bogdanm 88:9327015d4013 373 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 88:9327015d4013 374 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 88:9327015d4013 375 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 88:9327015d4013 376 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
bogdanm 88:9327015d4013 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 88:9327015d4013 378 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
bogdanm 88:9327015d4013 379 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
bogdanm 88:9327015d4013 380 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
bogdanm 88:9327015d4013 381 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
bogdanm 88:9327015d4013 382 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
bogdanm 88:9327015d4013 383 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
bogdanm 88:9327015d4013 384 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
bogdanm 88:9327015d4013 385 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
bogdanm 88:9327015d4013 386 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
bogdanm 88:9327015d4013 387 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
bogdanm 88:9327015d4013 388 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
bogdanm 88:9327015d4013 389 uint32_t RESERVED0[5];
bogdanm 88:9327015d4013 390 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
bogdanm 88:9327015d4013 391 } SCB_Type;
bogdanm 88:9327015d4013 392
bogdanm 88:9327015d4013 393 /* SCB CPUID Register Definitions */
bogdanm 88:9327015d4013 394 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 88:9327015d4013 395 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 88:9327015d4013 396
bogdanm 88:9327015d4013 397 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 88:9327015d4013 398 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 88:9327015d4013 399
bogdanm 88:9327015d4013 400 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 88:9327015d4013 401 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 88:9327015d4013 402
bogdanm 88:9327015d4013 403 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 88:9327015d4013 404 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 88:9327015d4013 405
bogdanm 88:9327015d4013 406 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
bogdanm 88:9327015d4013 407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
bogdanm 88:9327015d4013 408
bogdanm 88:9327015d4013 409 /* SCB Interrupt Control State Register Definitions */
bogdanm 88:9327015d4013 410 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 88:9327015d4013 411 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 88:9327015d4013 412
bogdanm 88:9327015d4013 413 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 88:9327015d4013 414 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 88:9327015d4013 415
bogdanm 88:9327015d4013 416 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 88:9327015d4013 417 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 88:9327015d4013 418
bogdanm 88:9327015d4013 419 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 88:9327015d4013 420 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 88:9327015d4013 421
bogdanm 88:9327015d4013 422 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 88:9327015d4013 423 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 88:9327015d4013 424
bogdanm 88:9327015d4013 425 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 88:9327015d4013 426 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 88:9327015d4013 427
bogdanm 88:9327015d4013 428 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 88:9327015d4013 429 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 88:9327015d4013 430
bogdanm 88:9327015d4013 431 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 88:9327015d4013 432 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 88:9327015d4013 433
bogdanm 88:9327015d4013 434 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
bogdanm 88:9327015d4013 435 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
bogdanm 88:9327015d4013 436
bogdanm 88:9327015d4013 437 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
bogdanm 88:9327015d4013 438 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 88:9327015d4013 439
bogdanm 88:9327015d4013 440 /* SCB Vector Table Offset Register Definitions */
bogdanm 88:9327015d4013 441 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
bogdanm 88:9327015d4013 442 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
bogdanm 88:9327015d4013 443
bogdanm 88:9327015d4013 444 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 88:9327015d4013 445 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 88:9327015d4013 446 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 88:9327015d4013 447
bogdanm 88:9327015d4013 448 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 88:9327015d4013 449 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 88:9327015d4013 450
bogdanm 88:9327015d4013 451 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 88:9327015d4013 452 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 88:9327015d4013 453
bogdanm 88:9327015d4013 454 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
bogdanm 88:9327015d4013 455 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
bogdanm 88:9327015d4013 456
bogdanm 88:9327015d4013 457 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 88:9327015d4013 458 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 88:9327015d4013 459
bogdanm 88:9327015d4013 460 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 88:9327015d4013 461 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 88:9327015d4013 462
bogdanm 88:9327015d4013 463 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
bogdanm 88:9327015d4013 464 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
bogdanm 88:9327015d4013 465
bogdanm 88:9327015d4013 466 /* SCB System Control Register Definitions */
bogdanm 88:9327015d4013 467 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 88:9327015d4013 468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 88:9327015d4013 469
bogdanm 88:9327015d4013 470 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 88:9327015d4013 471 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 88:9327015d4013 472
bogdanm 88:9327015d4013 473 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 88:9327015d4013 474 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 88:9327015d4013 475
bogdanm 88:9327015d4013 476 /* SCB Configuration Control Register Definitions */
bogdanm 88:9327015d4013 477 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 88:9327015d4013 478 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 88:9327015d4013 479
bogdanm 88:9327015d4013 480 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
bogdanm 88:9327015d4013 481 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
bogdanm 88:9327015d4013 482
bogdanm 88:9327015d4013 483 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
bogdanm 88:9327015d4013 484 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
bogdanm 88:9327015d4013 485
bogdanm 88:9327015d4013 486 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 88:9327015d4013 487 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 88:9327015d4013 488
bogdanm 88:9327015d4013 489 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
bogdanm 88:9327015d4013 490 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
bogdanm 88:9327015d4013 491
bogdanm 88:9327015d4013 492 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
bogdanm 88:9327015d4013 493 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
bogdanm 88:9327015d4013 494
bogdanm 88:9327015d4013 495 /* SCB System Handler Control and State Register Definitions */
bogdanm 88:9327015d4013 496 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
bogdanm 88:9327015d4013 497 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
bogdanm 88:9327015d4013 498
bogdanm 88:9327015d4013 499 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
bogdanm 88:9327015d4013 500 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
bogdanm 88:9327015d4013 501
bogdanm 88:9327015d4013 502 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
bogdanm 88:9327015d4013 503 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
bogdanm 88:9327015d4013 504
bogdanm 88:9327015d4013 505 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 88:9327015d4013 506 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 88:9327015d4013 507
bogdanm 88:9327015d4013 508 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
bogdanm 88:9327015d4013 509 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
bogdanm 88:9327015d4013 510
bogdanm 88:9327015d4013 511 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
bogdanm 88:9327015d4013 512 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
bogdanm 88:9327015d4013 513
bogdanm 88:9327015d4013 514 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
bogdanm 88:9327015d4013 515 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
bogdanm 88:9327015d4013 516
bogdanm 88:9327015d4013 517 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
bogdanm 88:9327015d4013 518 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
bogdanm 88:9327015d4013 519
bogdanm 88:9327015d4013 520 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
bogdanm 88:9327015d4013 521 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
bogdanm 88:9327015d4013 522
bogdanm 88:9327015d4013 523 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
bogdanm 88:9327015d4013 524 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
bogdanm 88:9327015d4013 525
bogdanm 88:9327015d4013 526 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
bogdanm 88:9327015d4013 527 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
bogdanm 88:9327015d4013 528
bogdanm 88:9327015d4013 529 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
bogdanm 88:9327015d4013 530 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
bogdanm 88:9327015d4013 531
bogdanm 88:9327015d4013 532 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
bogdanm 88:9327015d4013 533 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
bogdanm 88:9327015d4013 534
bogdanm 88:9327015d4013 535 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
bogdanm 88:9327015d4013 536 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
bogdanm 88:9327015d4013 537
bogdanm 88:9327015d4013 538 /* SCB Configurable Fault Status Registers Definitions */
bogdanm 88:9327015d4013 539 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
bogdanm 88:9327015d4013 540 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
bogdanm 88:9327015d4013 541
bogdanm 88:9327015d4013 542 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
bogdanm 88:9327015d4013 543 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
bogdanm 88:9327015d4013 544
bogdanm 88:9327015d4013 545 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
bogdanm 88:9327015d4013 546 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
bogdanm 88:9327015d4013 547
bogdanm 88:9327015d4013 548 /* SCB Hard Fault Status Registers Definitions */
bogdanm 88:9327015d4013 549 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
bogdanm 88:9327015d4013 550 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
bogdanm 88:9327015d4013 551
bogdanm 88:9327015d4013 552 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
bogdanm 88:9327015d4013 553 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
bogdanm 88:9327015d4013 554
bogdanm 88:9327015d4013 555 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
bogdanm 88:9327015d4013 556 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
bogdanm 88:9327015d4013 557
bogdanm 88:9327015d4013 558 /* SCB Debug Fault Status Register Definitions */
bogdanm 88:9327015d4013 559 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
bogdanm 88:9327015d4013 560 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
bogdanm 88:9327015d4013 561
bogdanm 88:9327015d4013 562 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
bogdanm 88:9327015d4013 563 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
bogdanm 88:9327015d4013 564
bogdanm 88:9327015d4013 565 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
bogdanm 88:9327015d4013 566 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
bogdanm 88:9327015d4013 567
bogdanm 88:9327015d4013 568 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
bogdanm 88:9327015d4013 569 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
bogdanm 88:9327015d4013 570
bogdanm 88:9327015d4013 571 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
bogdanm 88:9327015d4013 572 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
bogdanm 88:9327015d4013 573
bogdanm 88:9327015d4013 574 /*@} end of group CMSIS_SCB */
bogdanm 88:9327015d4013 575
bogdanm 88:9327015d4013 576
bogdanm 88:9327015d4013 577 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 578 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
bogdanm 88:9327015d4013 579 \brief Type definitions for the System Control and ID Register not in the SCB
bogdanm 88:9327015d4013 580 @{
bogdanm 88:9327015d4013 581 */
bogdanm 88:9327015d4013 582
bogdanm 88:9327015d4013 583 /** \brief Structure type to access the System Control and ID Register not in the SCB.
bogdanm 88:9327015d4013 584 */
bogdanm 88:9327015d4013 585 typedef struct
bogdanm 88:9327015d4013 586 {
bogdanm 88:9327015d4013 587 uint32_t RESERVED0[1];
bogdanm 88:9327015d4013 588 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
bogdanm 88:9327015d4013 589 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
bogdanm 88:9327015d4013 590 } SCnSCB_Type;
bogdanm 88:9327015d4013 591
bogdanm 88:9327015d4013 592 /* Interrupt Controller Type Register Definitions */
bogdanm 88:9327015d4013 593 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
bogdanm 88:9327015d4013 594 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
bogdanm 88:9327015d4013 595
bogdanm 88:9327015d4013 596 /* Auxiliary Control Register Definitions */
bogdanm 88:9327015d4013 597 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
bogdanm 88:9327015d4013 598 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
bogdanm 88:9327015d4013 599
bogdanm 88:9327015d4013 600 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
bogdanm 88:9327015d4013 601 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
bogdanm 88:9327015d4013 602
bogdanm 88:9327015d4013 603 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
bogdanm 88:9327015d4013 604 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
bogdanm 88:9327015d4013 605
bogdanm 88:9327015d4013 606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
bogdanm 88:9327015d4013 607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
bogdanm 88:9327015d4013 608
bogdanm 88:9327015d4013 609 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
bogdanm 88:9327015d4013 610 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
bogdanm 88:9327015d4013 611
bogdanm 88:9327015d4013 612 /*@} end of group CMSIS_SCnotSCB */
bogdanm 88:9327015d4013 613
bogdanm 88:9327015d4013 614
bogdanm 88:9327015d4013 615 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 616 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 88:9327015d4013 617 \brief Type definitions for the System Timer Registers.
bogdanm 88:9327015d4013 618 @{
bogdanm 88:9327015d4013 619 */
bogdanm 88:9327015d4013 620
bogdanm 88:9327015d4013 621 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 88:9327015d4013 622 */
bogdanm 88:9327015d4013 623 typedef struct
bogdanm 88:9327015d4013 624 {
bogdanm 88:9327015d4013 625 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 88:9327015d4013 626 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 88:9327015d4013 627 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 88:9327015d4013 628 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 88:9327015d4013 629 } SysTick_Type;
bogdanm 88:9327015d4013 630
bogdanm 88:9327015d4013 631 /* SysTick Control / Status Register Definitions */
bogdanm 88:9327015d4013 632 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 88:9327015d4013 633 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 88:9327015d4013 634
bogdanm 88:9327015d4013 635 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 88:9327015d4013 636 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 88:9327015d4013 637
bogdanm 88:9327015d4013 638 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 88:9327015d4013 639 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 88:9327015d4013 640
bogdanm 88:9327015d4013 641 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
bogdanm 88:9327015d4013 642 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 88:9327015d4013 643
bogdanm 88:9327015d4013 644 /* SysTick Reload Register Definitions */
bogdanm 88:9327015d4013 645 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
bogdanm 88:9327015d4013 646 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 88:9327015d4013 647
bogdanm 88:9327015d4013 648 /* SysTick Current Register Definitions */
bogdanm 88:9327015d4013 649 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
bogdanm 88:9327015d4013 650 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
bogdanm 88:9327015d4013 651
bogdanm 88:9327015d4013 652 /* SysTick Calibration Register Definitions */
bogdanm 88:9327015d4013 653 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 88:9327015d4013 654 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 88:9327015d4013 655
bogdanm 88:9327015d4013 656 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 88:9327015d4013 657 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 88:9327015d4013 658
bogdanm 88:9327015d4013 659 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
bogdanm 88:9327015d4013 660 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
bogdanm 88:9327015d4013 661
bogdanm 88:9327015d4013 662 /*@} end of group CMSIS_SysTick */
bogdanm 88:9327015d4013 663
bogdanm 88:9327015d4013 664
bogdanm 88:9327015d4013 665 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 666 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
bogdanm 88:9327015d4013 667 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
bogdanm 88:9327015d4013 668 @{
bogdanm 88:9327015d4013 669 */
bogdanm 88:9327015d4013 670
bogdanm 88:9327015d4013 671 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
bogdanm 88:9327015d4013 672 */
bogdanm 88:9327015d4013 673 typedef struct
bogdanm 88:9327015d4013 674 {
bogdanm 88:9327015d4013 675 __O union
bogdanm 88:9327015d4013 676 {
bogdanm 88:9327015d4013 677 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
bogdanm 88:9327015d4013 678 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
bogdanm 88:9327015d4013 679 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
bogdanm 88:9327015d4013 680 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
bogdanm 88:9327015d4013 681 uint32_t RESERVED0[864];
bogdanm 88:9327015d4013 682 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
bogdanm 88:9327015d4013 683 uint32_t RESERVED1[15];
bogdanm 88:9327015d4013 684 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
bogdanm 88:9327015d4013 685 uint32_t RESERVED2[15];
bogdanm 88:9327015d4013 686 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
bogdanm 88:9327015d4013 687 uint32_t RESERVED3[29];
bogdanm 88:9327015d4013 688 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
bogdanm 88:9327015d4013 689 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
bogdanm 88:9327015d4013 690 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
bogdanm 88:9327015d4013 691 uint32_t RESERVED4[43];
bogdanm 88:9327015d4013 692 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
bogdanm 88:9327015d4013 693 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
bogdanm 88:9327015d4013 694 uint32_t RESERVED5[6];
bogdanm 88:9327015d4013 695 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
bogdanm 88:9327015d4013 696 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
bogdanm 88:9327015d4013 697 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
bogdanm 88:9327015d4013 698 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
bogdanm 88:9327015d4013 699 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
bogdanm 88:9327015d4013 700 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
bogdanm 88:9327015d4013 701 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
bogdanm 88:9327015d4013 702 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
bogdanm 88:9327015d4013 703 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
bogdanm 88:9327015d4013 704 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
bogdanm 88:9327015d4013 705 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
bogdanm 88:9327015d4013 706 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
bogdanm 88:9327015d4013 707 } ITM_Type;
bogdanm 88:9327015d4013 708
bogdanm 88:9327015d4013 709 /* ITM Trace Privilege Register Definitions */
bogdanm 88:9327015d4013 710 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
bogdanm 88:9327015d4013 711 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
bogdanm 88:9327015d4013 712
bogdanm 88:9327015d4013 713 /* ITM Trace Control Register Definitions */
bogdanm 88:9327015d4013 714 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
bogdanm 88:9327015d4013 715 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
bogdanm 88:9327015d4013 716
bogdanm 88:9327015d4013 717 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
bogdanm 88:9327015d4013 718 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
bogdanm 88:9327015d4013 719
bogdanm 88:9327015d4013 720 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
bogdanm 88:9327015d4013 721 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
bogdanm 88:9327015d4013 722
bogdanm 88:9327015d4013 723 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
bogdanm 88:9327015d4013 724 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
bogdanm 88:9327015d4013 725
bogdanm 88:9327015d4013 726 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
bogdanm 88:9327015d4013 727 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
bogdanm 88:9327015d4013 728
bogdanm 88:9327015d4013 729 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
bogdanm 88:9327015d4013 730 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
bogdanm 88:9327015d4013 731
bogdanm 88:9327015d4013 732 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
bogdanm 88:9327015d4013 733 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
bogdanm 88:9327015d4013 734
bogdanm 88:9327015d4013 735 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
bogdanm 88:9327015d4013 736 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
bogdanm 88:9327015d4013 737
bogdanm 88:9327015d4013 738 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
bogdanm 88:9327015d4013 739 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
bogdanm 88:9327015d4013 740
bogdanm 88:9327015d4013 741 /* ITM Integration Write Register Definitions */
bogdanm 88:9327015d4013 742 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
bogdanm 88:9327015d4013 743 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
bogdanm 88:9327015d4013 744
bogdanm 88:9327015d4013 745 /* ITM Integration Read Register Definitions */
bogdanm 88:9327015d4013 746 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
bogdanm 88:9327015d4013 747 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
bogdanm 88:9327015d4013 748
bogdanm 88:9327015d4013 749 /* ITM Integration Mode Control Register Definitions */
bogdanm 88:9327015d4013 750 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
bogdanm 88:9327015d4013 751 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
bogdanm 88:9327015d4013 752
bogdanm 88:9327015d4013 753 /* ITM Lock Status Register Definitions */
bogdanm 88:9327015d4013 754 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
bogdanm 88:9327015d4013 755 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
bogdanm 88:9327015d4013 756
bogdanm 88:9327015d4013 757 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
bogdanm 88:9327015d4013 758 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
bogdanm 88:9327015d4013 759
bogdanm 88:9327015d4013 760 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
bogdanm 88:9327015d4013 761 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
bogdanm 88:9327015d4013 762
bogdanm 88:9327015d4013 763 /*@}*/ /* end of group CMSIS_ITM */
bogdanm 88:9327015d4013 764
bogdanm 88:9327015d4013 765
bogdanm 88:9327015d4013 766 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 767 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
bogdanm 88:9327015d4013 768 \brief Type definitions for the Data Watchpoint and Trace (DWT)
bogdanm 88:9327015d4013 769 @{
bogdanm 88:9327015d4013 770 */
bogdanm 88:9327015d4013 771
bogdanm 88:9327015d4013 772 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
bogdanm 88:9327015d4013 773 */
bogdanm 88:9327015d4013 774 typedef struct
bogdanm 88:9327015d4013 775 {
bogdanm 88:9327015d4013 776 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
bogdanm 88:9327015d4013 777 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
bogdanm 88:9327015d4013 778 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
bogdanm 88:9327015d4013 779 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
bogdanm 88:9327015d4013 780 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
bogdanm 88:9327015d4013 781 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
bogdanm 88:9327015d4013 782 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
bogdanm 88:9327015d4013 783 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
bogdanm 88:9327015d4013 784 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
bogdanm 88:9327015d4013 785 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
bogdanm 88:9327015d4013 786 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
bogdanm 88:9327015d4013 787 uint32_t RESERVED0[1];
bogdanm 88:9327015d4013 788 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
bogdanm 88:9327015d4013 789 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
bogdanm 88:9327015d4013 790 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
bogdanm 88:9327015d4013 791 uint32_t RESERVED1[1];
bogdanm 88:9327015d4013 792 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
bogdanm 88:9327015d4013 793 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
bogdanm 88:9327015d4013 794 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
bogdanm 88:9327015d4013 795 uint32_t RESERVED2[1];
bogdanm 88:9327015d4013 796 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
bogdanm 88:9327015d4013 797 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
bogdanm 88:9327015d4013 798 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
bogdanm 88:9327015d4013 799 } DWT_Type;
bogdanm 88:9327015d4013 800
bogdanm 88:9327015d4013 801 /* DWT Control Register Definitions */
bogdanm 88:9327015d4013 802 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
bogdanm 88:9327015d4013 803 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
bogdanm 88:9327015d4013 804
bogdanm 88:9327015d4013 805 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
bogdanm 88:9327015d4013 806 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
bogdanm 88:9327015d4013 807
bogdanm 88:9327015d4013 808 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
bogdanm 88:9327015d4013 809 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
bogdanm 88:9327015d4013 810
bogdanm 88:9327015d4013 811 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
bogdanm 88:9327015d4013 812 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
bogdanm 88:9327015d4013 813
bogdanm 88:9327015d4013 814 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
bogdanm 88:9327015d4013 815 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
bogdanm 88:9327015d4013 816
bogdanm 88:9327015d4013 817 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
bogdanm 88:9327015d4013 818 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
bogdanm 88:9327015d4013 819
bogdanm 88:9327015d4013 820 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
bogdanm 88:9327015d4013 821 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
bogdanm 88:9327015d4013 822
bogdanm 88:9327015d4013 823 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
bogdanm 88:9327015d4013 824 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
bogdanm 88:9327015d4013 825
bogdanm 88:9327015d4013 826 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
bogdanm 88:9327015d4013 827 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
bogdanm 88:9327015d4013 828
bogdanm 88:9327015d4013 829 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
bogdanm 88:9327015d4013 830 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
bogdanm 88:9327015d4013 831
bogdanm 88:9327015d4013 832 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
bogdanm 88:9327015d4013 833 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
bogdanm 88:9327015d4013 834
bogdanm 88:9327015d4013 835 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
bogdanm 88:9327015d4013 836 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
bogdanm 88:9327015d4013 837
bogdanm 88:9327015d4013 838 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
bogdanm 88:9327015d4013 839 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
bogdanm 88:9327015d4013 840
bogdanm 88:9327015d4013 841 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
bogdanm 88:9327015d4013 842 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
bogdanm 88:9327015d4013 843
bogdanm 88:9327015d4013 844 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
bogdanm 88:9327015d4013 845 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
bogdanm 88:9327015d4013 846
bogdanm 88:9327015d4013 847 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
bogdanm 88:9327015d4013 848 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
bogdanm 88:9327015d4013 849
bogdanm 88:9327015d4013 850 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
bogdanm 88:9327015d4013 851 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
bogdanm 88:9327015d4013 852
bogdanm 88:9327015d4013 853 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
bogdanm 88:9327015d4013 854 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
bogdanm 88:9327015d4013 855
bogdanm 88:9327015d4013 856 /* DWT CPI Count Register Definitions */
bogdanm 88:9327015d4013 857 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
bogdanm 88:9327015d4013 858 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
bogdanm 88:9327015d4013 859
bogdanm 88:9327015d4013 860 /* DWT Exception Overhead Count Register Definitions */
bogdanm 88:9327015d4013 861 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
bogdanm 88:9327015d4013 862 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
bogdanm 88:9327015d4013 863
bogdanm 88:9327015d4013 864 /* DWT Sleep Count Register Definitions */
bogdanm 88:9327015d4013 865 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
bogdanm 88:9327015d4013 866 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
bogdanm 88:9327015d4013 867
bogdanm 88:9327015d4013 868 /* DWT LSU Count Register Definitions */
bogdanm 88:9327015d4013 869 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
bogdanm 88:9327015d4013 870 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
bogdanm 88:9327015d4013 871
bogdanm 88:9327015d4013 872 /* DWT Folded-instruction Count Register Definitions */
bogdanm 88:9327015d4013 873 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
bogdanm 88:9327015d4013 874 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
bogdanm 88:9327015d4013 875
bogdanm 88:9327015d4013 876 /* DWT Comparator Mask Register Definitions */
bogdanm 88:9327015d4013 877 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
bogdanm 88:9327015d4013 878 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
bogdanm 88:9327015d4013 879
bogdanm 88:9327015d4013 880 /* DWT Comparator Function Register Definitions */
bogdanm 88:9327015d4013 881 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
bogdanm 88:9327015d4013 882 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
bogdanm 88:9327015d4013 883
bogdanm 88:9327015d4013 884 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
bogdanm 88:9327015d4013 885 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
bogdanm 88:9327015d4013 886
bogdanm 88:9327015d4013 887 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
bogdanm 88:9327015d4013 888 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
bogdanm 88:9327015d4013 889
bogdanm 88:9327015d4013 890 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
bogdanm 88:9327015d4013 891 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
bogdanm 88:9327015d4013 892
bogdanm 88:9327015d4013 893 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
bogdanm 88:9327015d4013 894 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
bogdanm 88:9327015d4013 895
bogdanm 88:9327015d4013 896 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
bogdanm 88:9327015d4013 897 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
bogdanm 88:9327015d4013 898
bogdanm 88:9327015d4013 899 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
bogdanm 88:9327015d4013 900 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
bogdanm 88:9327015d4013 901
bogdanm 88:9327015d4013 902 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
bogdanm 88:9327015d4013 903 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
bogdanm 88:9327015d4013 904
bogdanm 88:9327015d4013 905 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
bogdanm 88:9327015d4013 906 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
bogdanm 88:9327015d4013 907
bogdanm 88:9327015d4013 908 /*@}*/ /* end of group CMSIS_DWT */
bogdanm 88:9327015d4013 909
bogdanm 88:9327015d4013 910
bogdanm 88:9327015d4013 911 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 912 \defgroup CMSIS_TPI Trace Port Interface (TPI)
bogdanm 88:9327015d4013 913 \brief Type definitions for the Trace Port Interface (TPI)
bogdanm 88:9327015d4013 914 @{
bogdanm 88:9327015d4013 915 */
bogdanm 88:9327015d4013 916
bogdanm 88:9327015d4013 917 /** \brief Structure type to access the Trace Port Interface Register (TPI).
bogdanm 88:9327015d4013 918 */
bogdanm 88:9327015d4013 919 typedef struct
bogdanm 88:9327015d4013 920 {
bogdanm 88:9327015d4013 921 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
bogdanm 88:9327015d4013 922 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
bogdanm 88:9327015d4013 923 uint32_t RESERVED0[2];
bogdanm 88:9327015d4013 924 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
bogdanm 88:9327015d4013 925 uint32_t RESERVED1[55];
bogdanm 88:9327015d4013 926 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
bogdanm 88:9327015d4013 927 uint32_t RESERVED2[131];
bogdanm 88:9327015d4013 928 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
bogdanm 88:9327015d4013 929 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
bogdanm 88:9327015d4013 930 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
bogdanm 88:9327015d4013 931 uint32_t RESERVED3[759];
bogdanm 88:9327015d4013 932 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
bogdanm 88:9327015d4013 933 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
bogdanm 88:9327015d4013 934 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
bogdanm 88:9327015d4013 935 uint32_t RESERVED4[1];
bogdanm 88:9327015d4013 936 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
bogdanm 88:9327015d4013 937 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
bogdanm 88:9327015d4013 938 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
bogdanm 88:9327015d4013 939 uint32_t RESERVED5[39];
bogdanm 88:9327015d4013 940 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
bogdanm 88:9327015d4013 941 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
bogdanm 88:9327015d4013 942 uint32_t RESERVED7[8];
bogdanm 88:9327015d4013 943 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
bogdanm 88:9327015d4013 944 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
bogdanm 88:9327015d4013 945 } TPI_Type;
bogdanm 88:9327015d4013 946
bogdanm 88:9327015d4013 947 /* TPI Asynchronous Clock Prescaler Register Definitions */
bogdanm 88:9327015d4013 948 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
bogdanm 88:9327015d4013 949 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
bogdanm 88:9327015d4013 950
bogdanm 88:9327015d4013 951 /* TPI Selected Pin Protocol Register Definitions */
bogdanm 88:9327015d4013 952 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
bogdanm 88:9327015d4013 953 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
bogdanm 88:9327015d4013 954
bogdanm 88:9327015d4013 955 /* TPI Formatter and Flush Status Register Definitions */
bogdanm 88:9327015d4013 956 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
bogdanm 88:9327015d4013 957 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
bogdanm 88:9327015d4013 958
bogdanm 88:9327015d4013 959 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
bogdanm 88:9327015d4013 960 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
bogdanm 88:9327015d4013 961
bogdanm 88:9327015d4013 962 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
bogdanm 88:9327015d4013 963 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
bogdanm 88:9327015d4013 964
bogdanm 88:9327015d4013 965 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
bogdanm 88:9327015d4013 966 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
bogdanm 88:9327015d4013 967
bogdanm 88:9327015d4013 968 /* TPI Formatter and Flush Control Register Definitions */
bogdanm 88:9327015d4013 969 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
bogdanm 88:9327015d4013 970 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
bogdanm 88:9327015d4013 971
bogdanm 88:9327015d4013 972 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
bogdanm 88:9327015d4013 973 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
bogdanm 88:9327015d4013 974
bogdanm 88:9327015d4013 975 /* TPI TRIGGER Register Definitions */
bogdanm 88:9327015d4013 976 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
bogdanm 88:9327015d4013 977 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
bogdanm 88:9327015d4013 978
bogdanm 88:9327015d4013 979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
bogdanm 88:9327015d4013 980 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
bogdanm 88:9327015d4013 981 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
bogdanm 88:9327015d4013 982
bogdanm 88:9327015d4013 983 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
bogdanm 88:9327015d4013 984 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
bogdanm 88:9327015d4013 985
bogdanm 88:9327015d4013 986 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
bogdanm 88:9327015d4013 987 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
bogdanm 88:9327015d4013 988
bogdanm 88:9327015d4013 989 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
bogdanm 88:9327015d4013 990 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
bogdanm 88:9327015d4013 991
bogdanm 88:9327015d4013 992 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
bogdanm 88:9327015d4013 993 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
bogdanm 88:9327015d4013 994
bogdanm 88:9327015d4013 995 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
bogdanm 88:9327015d4013 996 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
bogdanm 88:9327015d4013 997
bogdanm 88:9327015d4013 998 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
bogdanm 88:9327015d4013 999 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
bogdanm 88:9327015d4013 1000
bogdanm 88:9327015d4013 1001 /* TPI ITATBCTR2 Register Definitions */
bogdanm 88:9327015d4013 1002 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
bogdanm 88:9327015d4013 1003 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
bogdanm 88:9327015d4013 1004
bogdanm 88:9327015d4013 1005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
bogdanm 88:9327015d4013 1006 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
bogdanm 88:9327015d4013 1007 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
bogdanm 88:9327015d4013 1008
bogdanm 88:9327015d4013 1009 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
bogdanm 88:9327015d4013 1010 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
bogdanm 88:9327015d4013 1011
bogdanm 88:9327015d4013 1012 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
bogdanm 88:9327015d4013 1013 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
bogdanm 88:9327015d4013 1014
bogdanm 88:9327015d4013 1015 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
bogdanm 88:9327015d4013 1016 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
bogdanm 88:9327015d4013 1017
bogdanm 88:9327015d4013 1018 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
bogdanm 88:9327015d4013 1019 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
bogdanm 88:9327015d4013 1020
bogdanm 88:9327015d4013 1021 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
bogdanm 88:9327015d4013 1022 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
bogdanm 88:9327015d4013 1023
bogdanm 88:9327015d4013 1024 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
bogdanm 88:9327015d4013 1025 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
bogdanm 88:9327015d4013 1026
bogdanm 88:9327015d4013 1027 /* TPI ITATBCTR0 Register Definitions */
bogdanm 88:9327015d4013 1028 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
bogdanm 88:9327015d4013 1029 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
bogdanm 88:9327015d4013 1030
bogdanm 88:9327015d4013 1031 /* TPI Integration Mode Control Register Definitions */
bogdanm 88:9327015d4013 1032 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
bogdanm 88:9327015d4013 1033 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
bogdanm 88:9327015d4013 1034
bogdanm 88:9327015d4013 1035 /* TPI DEVID Register Definitions */
bogdanm 88:9327015d4013 1036 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
bogdanm 88:9327015d4013 1037 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
bogdanm 88:9327015d4013 1038
bogdanm 88:9327015d4013 1039 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
bogdanm 88:9327015d4013 1040 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
bogdanm 88:9327015d4013 1041
bogdanm 88:9327015d4013 1042 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
bogdanm 88:9327015d4013 1043 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
bogdanm 88:9327015d4013 1044
bogdanm 88:9327015d4013 1045 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
bogdanm 88:9327015d4013 1046 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
bogdanm 88:9327015d4013 1047
bogdanm 88:9327015d4013 1048 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
bogdanm 88:9327015d4013 1049 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
bogdanm 88:9327015d4013 1050
bogdanm 88:9327015d4013 1051 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
bogdanm 88:9327015d4013 1052 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
bogdanm 88:9327015d4013 1053
bogdanm 88:9327015d4013 1054 /* TPI DEVTYPE Register Definitions */
bogdanm 88:9327015d4013 1055 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
bogdanm 88:9327015d4013 1056 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
bogdanm 88:9327015d4013 1057
bogdanm 88:9327015d4013 1058 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
bogdanm 88:9327015d4013 1059 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
bogdanm 88:9327015d4013 1060
bogdanm 88:9327015d4013 1061 /*@}*/ /* end of group CMSIS_TPI */
bogdanm 88:9327015d4013 1062
bogdanm 88:9327015d4013 1063
bogdanm 88:9327015d4013 1064 #if (__MPU_PRESENT == 1)
bogdanm 88:9327015d4013 1065 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 1066 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
bogdanm 88:9327015d4013 1067 \brief Type definitions for the Memory Protection Unit (MPU)
bogdanm 88:9327015d4013 1068 @{
bogdanm 88:9327015d4013 1069 */
bogdanm 88:9327015d4013 1070
bogdanm 88:9327015d4013 1071 /** \brief Structure type to access the Memory Protection Unit (MPU).
bogdanm 88:9327015d4013 1072 */
bogdanm 88:9327015d4013 1073 typedef struct
bogdanm 88:9327015d4013 1074 {
bogdanm 88:9327015d4013 1075 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
bogdanm 88:9327015d4013 1076 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
bogdanm 88:9327015d4013 1077 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
bogdanm 88:9327015d4013 1078 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
bogdanm 88:9327015d4013 1079 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
bogdanm 88:9327015d4013 1080 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
bogdanm 88:9327015d4013 1081 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
bogdanm 88:9327015d4013 1082 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
bogdanm 88:9327015d4013 1083 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
bogdanm 88:9327015d4013 1084 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
bogdanm 88:9327015d4013 1085 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
bogdanm 88:9327015d4013 1086 } MPU_Type;
bogdanm 88:9327015d4013 1087
bogdanm 88:9327015d4013 1088 /* MPU Type Register */
bogdanm 88:9327015d4013 1089 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
bogdanm 88:9327015d4013 1090 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
bogdanm 88:9327015d4013 1091
bogdanm 88:9327015d4013 1092 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
bogdanm 88:9327015d4013 1093 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
bogdanm 88:9327015d4013 1094
bogdanm 88:9327015d4013 1095 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
bogdanm 88:9327015d4013 1096 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
bogdanm 88:9327015d4013 1097
bogdanm 88:9327015d4013 1098 /* MPU Control Register */
bogdanm 88:9327015d4013 1099 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
bogdanm 88:9327015d4013 1100 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
bogdanm 88:9327015d4013 1101
bogdanm 88:9327015d4013 1102 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
bogdanm 88:9327015d4013 1103 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
bogdanm 88:9327015d4013 1104
bogdanm 88:9327015d4013 1105 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
bogdanm 88:9327015d4013 1106 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
bogdanm 88:9327015d4013 1107
bogdanm 88:9327015d4013 1108 /* MPU Region Number Register */
bogdanm 88:9327015d4013 1109 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
bogdanm 88:9327015d4013 1110 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
bogdanm 88:9327015d4013 1111
bogdanm 88:9327015d4013 1112 /* MPU Region Base Address Register */
bogdanm 88:9327015d4013 1113 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
bogdanm 88:9327015d4013 1114 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
bogdanm 88:9327015d4013 1115
bogdanm 88:9327015d4013 1116 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
bogdanm 88:9327015d4013 1117 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
bogdanm 88:9327015d4013 1118
bogdanm 88:9327015d4013 1119 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
bogdanm 88:9327015d4013 1120 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
bogdanm 88:9327015d4013 1121
bogdanm 88:9327015d4013 1122 /* MPU Region Attribute and Size Register */
bogdanm 88:9327015d4013 1123 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
bogdanm 88:9327015d4013 1124 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
bogdanm 88:9327015d4013 1125
bogdanm 88:9327015d4013 1126 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
bogdanm 88:9327015d4013 1127 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
bogdanm 88:9327015d4013 1128
bogdanm 88:9327015d4013 1129 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
bogdanm 88:9327015d4013 1130 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
bogdanm 88:9327015d4013 1131
bogdanm 88:9327015d4013 1132 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
bogdanm 88:9327015d4013 1133 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
bogdanm 88:9327015d4013 1134
bogdanm 88:9327015d4013 1135 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
bogdanm 88:9327015d4013 1136 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
bogdanm 88:9327015d4013 1137
bogdanm 88:9327015d4013 1138 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
bogdanm 88:9327015d4013 1139 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
bogdanm 88:9327015d4013 1140
bogdanm 88:9327015d4013 1141 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
bogdanm 88:9327015d4013 1142 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
bogdanm 88:9327015d4013 1143
bogdanm 88:9327015d4013 1144 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
bogdanm 88:9327015d4013 1145 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
bogdanm 88:9327015d4013 1146
bogdanm 88:9327015d4013 1147 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
bogdanm 88:9327015d4013 1148 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
bogdanm 88:9327015d4013 1149
bogdanm 88:9327015d4013 1150 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
bogdanm 88:9327015d4013 1151 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
bogdanm 88:9327015d4013 1152
bogdanm 88:9327015d4013 1153 /*@} end of group CMSIS_MPU */
bogdanm 88:9327015d4013 1154 #endif
bogdanm 88:9327015d4013 1155
bogdanm 88:9327015d4013 1156
bogdanm 88:9327015d4013 1157 #if (__FPU_PRESENT == 1)
bogdanm 88:9327015d4013 1158 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 1159 \defgroup CMSIS_FPU Floating Point Unit (FPU)
bogdanm 88:9327015d4013 1160 \brief Type definitions for the Floating Point Unit (FPU)
bogdanm 88:9327015d4013 1161 @{
bogdanm 88:9327015d4013 1162 */
bogdanm 88:9327015d4013 1163
bogdanm 88:9327015d4013 1164 /** \brief Structure type to access the Floating Point Unit (FPU).
bogdanm 88:9327015d4013 1165 */
bogdanm 88:9327015d4013 1166 typedef struct
bogdanm 88:9327015d4013 1167 {
bogdanm 88:9327015d4013 1168 uint32_t RESERVED0[1];
bogdanm 88:9327015d4013 1169 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
bogdanm 88:9327015d4013 1170 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
bogdanm 88:9327015d4013 1171 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
bogdanm 88:9327015d4013 1172 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
bogdanm 88:9327015d4013 1173 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
bogdanm 88:9327015d4013 1174 } FPU_Type;
bogdanm 88:9327015d4013 1175
bogdanm 88:9327015d4013 1176 /* Floating-Point Context Control Register */
bogdanm 88:9327015d4013 1177 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
bogdanm 88:9327015d4013 1178 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
bogdanm 88:9327015d4013 1179
bogdanm 88:9327015d4013 1180 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
bogdanm 88:9327015d4013 1181 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
bogdanm 88:9327015d4013 1182
bogdanm 88:9327015d4013 1183 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
bogdanm 88:9327015d4013 1184 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
bogdanm 88:9327015d4013 1185
bogdanm 88:9327015d4013 1186 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
bogdanm 88:9327015d4013 1187 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
bogdanm 88:9327015d4013 1188
bogdanm 88:9327015d4013 1189 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
bogdanm 88:9327015d4013 1190 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
bogdanm 88:9327015d4013 1191
bogdanm 88:9327015d4013 1192 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
bogdanm 88:9327015d4013 1193 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
bogdanm 88:9327015d4013 1194
bogdanm 88:9327015d4013 1195 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
bogdanm 88:9327015d4013 1196 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
bogdanm 88:9327015d4013 1197
bogdanm 88:9327015d4013 1198 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
bogdanm 88:9327015d4013 1199 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
bogdanm 88:9327015d4013 1200
bogdanm 88:9327015d4013 1201 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
bogdanm 88:9327015d4013 1202 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
bogdanm 88:9327015d4013 1203
bogdanm 88:9327015d4013 1204 /* Floating-Point Context Address Register */
bogdanm 88:9327015d4013 1205 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
bogdanm 88:9327015d4013 1206 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
bogdanm 88:9327015d4013 1207
bogdanm 88:9327015d4013 1208 /* Floating-Point Default Status Control Register */
bogdanm 88:9327015d4013 1209 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
bogdanm 88:9327015d4013 1210 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
bogdanm 88:9327015d4013 1211
bogdanm 88:9327015d4013 1212 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
bogdanm 88:9327015d4013 1213 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
bogdanm 88:9327015d4013 1214
bogdanm 88:9327015d4013 1215 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
bogdanm 88:9327015d4013 1216 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
bogdanm 88:9327015d4013 1217
bogdanm 88:9327015d4013 1218 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
bogdanm 88:9327015d4013 1219 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
bogdanm 88:9327015d4013 1220
bogdanm 88:9327015d4013 1221 /* Media and FP Feature Register 0 */
bogdanm 88:9327015d4013 1222 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
bogdanm 88:9327015d4013 1223 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
bogdanm 88:9327015d4013 1224
bogdanm 88:9327015d4013 1225 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
bogdanm 88:9327015d4013 1226 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
bogdanm 88:9327015d4013 1227
bogdanm 88:9327015d4013 1228 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
bogdanm 88:9327015d4013 1229 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
bogdanm 88:9327015d4013 1230
bogdanm 88:9327015d4013 1231 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
bogdanm 88:9327015d4013 1232 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
bogdanm 88:9327015d4013 1233
bogdanm 88:9327015d4013 1234 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
bogdanm 88:9327015d4013 1235 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
bogdanm 88:9327015d4013 1236
bogdanm 88:9327015d4013 1237 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
bogdanm 88:9327015d4013 1238 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
bogdanm 88:9327015d4013 1239
bogdanm 88:9327015d4013 1240 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
bogdanm 88:9327015d4013 1241 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
bogdanm 88:9327015d4013 1242
bogdanm 88:9327015d4013 1243 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
bogdanm 88:9327015d4013 1244 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
bogdanm 88:9327015d4013 1245
bogdanm 88:9327015d4013 1246 /* Media and FP Feature Register 1 */
bogdanm 88:9327015d4013 1247 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
bogdanm 88:9327015d4013 1248 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
bogdanm 88:9327015d4013 1249
bogdanm 88:9327015d4013 1250 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
bogdanm 88:9327015d4013 1251 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
bogdanm 88:9327015d4013 1252
bogdanm 88:9327015d4013 1253 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
bogdanm 88:9327015d4013 1254 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
bogdanm 88:9327015d4013 1255
bogdanm 88:9327015d4013 1256 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
bogdanm 88:9327015d4013 1257 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
bogdanm 88:9327015d4013 1258
bogdanm 88:9327015d4013 1259 /*@} end of group CMSIS_FPU */
bogdanm 88:9327015d4013 1260 #endif
bogdanm 88:9327015d4013 1261
bogdanm 88:9327015d4013 1262
bogdanm 88:9327015d4013 1263 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 1264 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 88:9327015d4013 1265 \brief Type definitions for the Core Debug Registers
bogdanm 88:9327015d4013 1266 @{
bogdanm 88:9327015d4013 1267 */
bogdanm 88:9327015d4013 1268
bogdanm 88:9327015d4013 1269 /** \brief Structure type to access the Core Debug Register (CoreDebug).
bogdanm 88:9327015d4013 1270 */
bogdanm 88:9327015d4013 1271 typedef struct
bogdanm 88:9327015d4013 1272 {
bogdanm 88:9327015d4013 1273 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
bogdanm 88:9327015d4013 1274 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
bogdanm 88:9327015d4013 1275 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
bogdanm 88:9327015d4013 1276 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
bogdanm 88:9327015d4013 1277 } CoreDebug_Type;
bogdanm 88:9327015d4013 1278
bogdanm 88:9327015d4013 1279 /* Debug Halting Control and Status Register */
bogdanm 88:9327015d4013 1280 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
bogdanm 88:9327015d4013 1281 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
bogdanm 88:9327015d4013 1282
bogdanm 88:9327015d4013 1283 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
bogdanm 88:9327015d4013 1284 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
bogdanm 88:9327015d4013 1285
bogdanm 88:9327015d4013 1286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
bogdanm 88:9327015d4013 1287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
bogdanm 88:9327015d4013 1288
bogdanm 88:9327015d4013 1289 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
bogdanm 88:9327015d4013 1290 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
bogdanm 88:9327015d4013 1291
bogdanm 88:9327015d4013 1292 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
bogdanm 88:9327015d4013 1293 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
bogdanm 88:9327015d4013 1294
bogdanm 88:9327015d4013 1295 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
bogdanm 88:9327015d4013 1296 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
bogdanm 88:9327015d4013 1297
bogdanm 88:9327015d4013 1298 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
bogdanm 88:9327015d4013 1299 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
bogdanm 88:9327015d4013 1300
bogdanm 88:9327015d4013 1301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
bogdanm 88:9327015d4013 1302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
bogdanm 88:9327015d4013 1303
bogdanm 88:9327015d4013 1304 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
bogdanm 88:9327015d4013 1305 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
bogdanm 88:9327015d4013 1306
bogdanm 88:9327015d4013 1307 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
bogdanm 88:9327015d4013 1308 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
bogdanm 88:9327015d4013 1309
bogdanm 88:9327015d4013 1310 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
bogdanm 88:9327015d4013 1311 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
bogdanm 88:9327015d4013 1312
bogdanm 88:9327015d4013 1313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
bogdanm 88:9327015d4013 1314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
bogdanm 88:9327015d4013 1315
bogdanm 88:9327015d4013 1316 /* Debug Core Register Selector Register */
bogdanm 88:9327015d4013 1317 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
bogdanm 88:9327015d4013 1318 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
bogdanm 88:9327015d4013 1319
bogdanm 88:9327015d4013 1320 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
bogdanm 88:9327015d4013 1321 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
bogdanm 88:9327015d4013 1322
bogdanm 88:9327015d4013 1323 /* Debug Exception and Monitor Control Register */
bogdanm 88:9327015d4013 1324 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
bogdanm 88:9327015d4013 1325 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
bogdanm 88:9327015d4013 1326
bogdanm 88:9327015d4013 1327 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
bogdanm 88:9327015d4013 1328 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
bogdanm 88:9327015d4013 1329
bogdanm 88:9327015d4013 1330 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
bogdanm 88:9327015d4013 1331 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
bogdanm 88:9327015d4013 1332
bogdanm 88:9327015d4013 1333 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
bogdanm 88:9327015d4013 1334 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
bogdanm 88:9327015d4013 1335
bogdanm 88:9327015d4013 1336 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
bogdanm 88:9327015d4013 1337 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
bogdanm 88:9327015d4013 1338
bogdanm 88:9327015d4013 1339 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
bogdanm 88:9327015d4013 1340 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
bogdanm 88:9327015d4013 1341
bogdanm 88:9327015d4013 1342 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
bogdanm 88:9327015d4013 1343 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
bogdanm 88:9327015d4013 1344
bogdanm 88:9327015d4013 1345 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
bogdanm 88:9327015d4013 1346 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
bogdanm 88:9327015d4013 1347
bogdanm 88:9327015d4013 1348 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
bogdanm 88:9327015d4013 1349 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
bogdanm 88:9327015d4013 1350
bogdanm 88:9327015d4013 1351 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
bogdanm 88:9327015d4013 1352 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
bogdanm 88:9327015d4013 1353
bogdanm 88:9327015d4013 1354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
bogdanm 88:9327015d4013 1355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
bogdanm 88:9327015d4013 1356
bogdanm 88:9327015d4013 1357 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
bogdanm 88:9327015d4013 1358 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
bogdanm 88:9327015d4013 1359
bogdanm 88:9327015d4013 1360 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
bogdanm 88:9327015d4013 1361 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
bogdanm 88:9327015d4013 1362
bogdanm 88:9327015d4013 1363 /*@} end of group CMSIS_CoreDebug */
bogdanm 88:9327015d4013 1364
bogdanm 88:9327015d4013 1365
bogdanm 88:9327015d4013 1366 /** \ingroup CMSIS_core_register
bogdanm 88:9327015d4013 1367 \defgroup CMSIS_core_base Core Definitions
bogdanm 88:9327015d4013 1368 \brief Definitions for base addresses, unions, and structures.
bogdanm 88:9327015d4013 1369 @{
bogdanm 88:9327015d4013 1370 */
bogdanm 88:9327015d4013 1371
bogdanm 88:9327015d4013 1372 /* Memory mapping of Cortex-M4 Hardware */
bogdanm 88:9327015d4013 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 88:9327015d4013 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
bogdanm 88:9327015d4013 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
bogdanm 88:9327015d4013 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
bogdanm 88:9327015d4013 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
bogdanm 88:9327015d4013 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 88:9327015d4013 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 88:9327015d4013 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 88:9327015d4013 1381
bogdanm 88:9327015d4013 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
bogdanm 88:9327015d4013 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 88:9327015d4013 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 88:9327015d4013 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 88:9327015d4013 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
bogdanm 88:9327015d4013 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
bogdanm 88:9327015d4013 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
bogdanm 88:9327015d4013 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
bogdanm 88:9327015d4013 1390
bogdanm 88:9327015d4013 1391 #if (__MPU_PRESENT == 1)
bogdanm 88:9327015d4013 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
bogdanm 88:9327015d4013 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
bogdanm 88:9327015d4013 1394 #endif
bogdanm 88:9327015d4013 1395
bogdanm 88:9327015d4013 1396 #if (__FPU_PRESENT == 1)
bogdanm 88:9327015d4013 1397 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
bogdanm 88:9327015d4013 1398 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
bogdanm 88:9327015d4013 1399 #endif
bogdanm 88:9327015d4013 1400
bogdanm 88:9327015d4013 1401 /*@} */
bogdanm 88:9327015d4013 1402
bogdanm 88:9327015d4013 1403
bogdanm 88:9327015d4013 1404
bogdanm 88:9327015d4013 1405 /*******************************************************************************
bogdanm 88:9327015d4013 1406 * Hardware Abstraction Layer
bogdanm 88:9327015d4013 1407 Core Function Interface contains:
bogdanm 88:9327015d4013 1408 - Core NVIC Functions
bogdanm 88:9327015d4013 1409 - Core SysTick Functions
bogdanm 88:9327015d4013 1410 - Core Debug Functions
bogdanm 88:9327015d4013 1411 - Core Register Access Functions
bogdanm 88:9327015d4013 1412 ******************************************************************************/
bogdanm 88:9327015d4013 1413 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 88:9327015d4013 1414 */
bogdanm 88:9327015d4013 1415
bogdanm 88:9327015d4013 1416
bogdanm 88:9327015d4013 1417
bogdanm 88:9327015d4013 1418 /* ########################## NVIC functions #################################### */
bogdanm 88:9327015d4013 1419 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 88:9327015d4013 1420 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 88:9327015d4013 1421 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 88:9327015d4013 1422 @{
bogdanm 88:9327015d4013 1423 */
bogdanm 88:9327015d4013 1424
bogdanm 88:9327015d4013 1425 /** \brief Set Priority Grouping
bogdanm 88:9327015d4013 1426
bogdanm 88:9327015d4013 1427 The function sets the priority grouping field using the required unlock sequence.
bogdanm 88:9327015d4013 1428 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
bogdanm 88:9327015d4013 1429 Only values from 0..7 are used.
bogdanm 88:9327015d4013 1430 In case of a conflict between priority grouping and available
bogdanm 88:9327015d4013 1431 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
bogdanm 88:9327015d4013 1432
bogdanm 88:9327015d4013 1433 \param [in] PriorityGroup Priority grouping field.
bogdanm 88:9327015d4013 1434 */
bogdanm 88:9327015d4013 1435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
bogdanm 88:9327015d4013 1436 {
bogdanm 88:9327015d4013 1437 uint32_t reg_value;
bogdanm 88:9327015d4013 1438 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
bogdanm 88:9327015d4013 1439
bogdanm 88:9327015d4013 1440 reg_value = SCB->AIRCR; /* read old register configuration */
bogdanm 88:9327015d4013 1441 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
bogdanm 88:9327015d4013 1442 reg_value = (reg_value |
bogdanm 88:9327015d4013 1443 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 88:9327015d4013 1444 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
bogdanm 88:9327015d4013 1445 SCB->AIRCR = reg_value;
bogdanm 88:9327015d4013 1446 }
bogdanm 88:9327015d4013 1447
bogdanm 88:9327015d4013 1448
bogdanm 88:9327015d4013 1449 /** \brief Get Priority Grouping
bogdanm 88:9327015d4013 1450
bogdanm 88:9327015d4013 1451 The function reads the priority grouping field from the NVIC Interrupt Controller.
bogdanm 88:9327015d4013 1452
bogdanm 88:9327015d4013 1453 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
bogdanm 88:9327015d4013 1454 */
bogdanm 88:9327015d4013 1455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
bogdanm 88:9327015d4013 1456 {
bogdanm 88:9327015d4013 1457 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
bogdanm 88:9327015d4013 1458 }
bogdanm 88:9327015d4013 1459
bogdanm 88:9327015d4013 1460
bogdanm 88:9327015d4013 1461 /** \brief Enable External Interrupt
bogdanm 88:9327015d4013 1462
bogdanm 88:9327015d4013 1463 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 88:9327015d4013 1464
bogdanm 88:9327015d4013 1465 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 88:9327015d4013 1466 */
bogdanm 88:9327015d4013 1467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 88:9327015d4013 1468 {
bogdanm 88:9327015d4013 1469 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
bogdanm 88:9327015d4013 1470 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
bogdanm 88:9327015d4013 1471 }
bogdanm 88:9327015d4013 1472
bogdanm 88:9327015d4013 1473
bogdanm 88:9327015d4013 1474 /** \brief Disable External Interrupt
bogdanm 88:9327015d4013 1475
bogdanm 88:9327015d4013 1476 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 88:9327015d4013 1477
bogdanm 88:9327015d4013 1478 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 88:9327015d4013 1479 */
bogdanm 88:9327015d4013 1480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 88:9327015d4013 1481 {
bogdanm 88:9327015d4013 1482 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
bogdanm 88:9327015d4013 1483 }
bogdanm 88:9327015d4013 1484
bogdanm 88:9327015d4013 1485
bogdanm 88:9327015d4013 1486 /** \brief Get Pending Interrupt
bogdanm 88:9327015d4013 1487
bogdanm 88:9327015d4013 1488 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 88:9327015d4013 1489 for the specified interrupt.
bogdanm 88:9327015d4013 1490
bogdanm 88:9327015d4013 1491 \param [in] IRQn Interrupt number.
bogdanm 88:9327015d4013 1492
bogdanm 88:9327015d4013 1493 \return 0 Interrupt status is not pending.
bogdanm 88:9327015d4013 1494 \return 1 Interrupt status is pending.
bogdanm 88:9327015d4013 1495 */
bogdanm 88:9327015d4013 1496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 88:9327015d4013 1497 {
bogdanm 88:9327015d4013 1498 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
bogdanm 88:9327015d4013 1499 }
bogdanm 88:9327015d4013 1500
bogdanm 88:9327015d4013 1501
bogdanm 88:9327015d4013 1502 /** \brief Set Pending Interrupt
bogdanm 88:9327015d4013 1503
bogdanm 88:9327015d4013 1504 The function sets the pending bit of an external interrupt.
bogdanm 88:9327015d4013 1505
bogdanm 88:9327015d4013 1506 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 88:9327015d4013 1507 */
bogdanm 88:9327015d4013 1508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 88:9327015d4013 1509 {
bogdanm 88:9327015d4013 1510 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
bogdanm 88:9327015d4013 1511 }
bogdanm 88:9327015d4013 1512
bogdanm 88:9327015d4013 1513
bogdanm 88:9327015d4013 1514 /** \brief Clear Pending Interrupt
bogdanm 88:9327015d4013 1515
bogdanm 88:9327015d4013 1516 The function clears the pending bit of an external interrupt.
bogdanm 88:9327015d4013 1517
bogdanm 88:9327015d4013 1518 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 88:9327015d4013 1519 */
bogdanm 88:9327015d4013 1520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 88:9327015d4013 1521 {
bogdanm 88:9327015d4013 1522 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
bogdanm 88:9327015d4013 1523 }
bogdanm 88:9327015d4013 1524
bogdanm 88:9327015d4013 1525
bogdanm 88:9327015d4013 1526 /** \brief Get Active Interrupt
bogdanm 88:9327015d4013 1527
bogdanm 88:9327015d4013 1528 The function reads the active register in NVIC and returns the active bit.
bogdanm 88:9327015d4013 1529
bogdanm 88:9327015d4013 1530 \param [in] IRQn Interrupt number.
bogdanm 88:9327015d4013 1531
bogdanm 88:9327015d4013 1532 \return 0 Interrupt status is not active.
bogdanm 88:9327015d4013 1533 \return 1 Interrupt status is active.
bogdanm 88:9327015d4013 1534 */
bogdanm 88:9327015d4013 1535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
bogdanm 88:9327015d4013 1536 {
bogdanm 88:9327015d4013 1537 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
bogdanm 88:9327015d4013 1538 }
bogdanm 88:9327015d4013 1539
bogdanm 88:9327015d4013 1540
bogdanm 88:9327015d4013 1541 /** \brief Set Interrupt Priority
bogdanm 88:9327015d4013 1542
bogdanm 88:9327015d4013 1543 The function sets the priority of an interrupt.
bogdanm 88:9327015d4013 1544
bogdanm 88:9327015d4013 1545 \note The priority cannot be set for every core interrupt.
bogdanm 88:9327015d4013 1546
bogdanm 88:9327015d4013 1547 \param [in] IRQn Interrupt number.
bogdanm 88:9327015d4013 1548 \param [in] priority Priority to set.
bogdanm 88:9327015d4013 1549 */
bogdanm 88:9327015d4013 1550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 88:9327015d4013 1551 {
bogdanm 88:9327015d4013 1552 if(IRQn < 0) {
bogdanm 88:9327015d4013 1553 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
bogdanm 88:9327015d4013 1554 else {
bogdanm 88:9327015d4013 1555 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
bogdanm 88:9327015d4013 1556 }
bogdanm 88:9327015d4013 1557
bogdanm 88:9327015d4013 1558
bogdanm 88:9327015d4013 1559 /** \brief Get Interrupt Priority
bogdanm 88:9327015d4013 1560
bogdanm 88:9327015d4013 1561 The function reads the priority of an interrupt. The interrupt
bogdanm 88:9327015d4013 1562 number can be positive to specify an external (device specific)
bogdanm 88:9327015d4013 1563 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 88:9327015d4013 1564
bogdanm 88:9327015d4013 1565
bogdanm 88:9327015d4013 1566 \param [in] IRQn Interrupt number.
bogdanm 88:9327015d4013 1567 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 88:9327015d4013 1568 priority bits of the microcontroller.
bogdanm 88:9327015d4013 1569 */
bogdanm 88:9327015d4013 1570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 88:9327015d4013 1571 {
bogdanm 88:9327015d4013 1572
bogdanm 88:9327015d4013 1573 if(IRQn < 0) {
bogdanm 88:9327015d4013 1574 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
bogdanm 88:9327015d4013 1575 else {
bogdanm 88:9327015d4013 1576 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
bogdanm 88:9327015d4013 1577 }
bogdanm 88:9327015d4013 1578
bogdanm 88:9327015d4013 1579
bogdanm 88:9327015d4013 1580 /** \brief Encode Priority
bogdanm 88:9327015d4013 1581
bogdanm 88:9327015d4013 1582 The function encodes the priority for an interrupt with the given priority group,
bogdanm 88:9327015d4013 1583 preemptive priority value, and subpriority value.
bogdanm 88:9327015d4013 1584 In case of a conflict between priority grouping and available
bogdanm 88:9327015d4013 1585 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
bogdanm 88:9327015d4013 1586
bogdanm 88:9327015d4013 1587 \param [in] PriorityGroup Used priority group.
bogdanm 88:9327015d4013 1588 \param [in] PreemptPriority Preemptive priority value (starting from 0).
bogdanm 88:9327015d4013 1589 \param [in] SubPriority Subpriority value (starting from 0).
bogdanm 88:9327015d4013 1590 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
bogdanm 88:9327015d4013 1591 */
bogdanm 88:9327015d4013 1592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
bogdanm 88:9327015d4013 1593 {
bogdanm 88:9327015d4013 1594 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
bogdanm 88:9327015d4013 1595 uint32_t PreemptPriorityBits;
bogdanm 88:9327015d4013 1596 uint32_t SubPriorityBits;
bogdanm 88:9327015d4013 1597
bogdanm 88:9327015d4013 1598 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
bogdanm 88:9327015d4013 1599 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
bogdanm 88:9327015d4013 1600
bogdanm 88:9327015d4013 1601 return (
bogdanm 88:9327015d4013 1602 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
bogdanm 88:9327015d4013 1603 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
bogdanm 88:9327015d4013 1604 );
bogdanm 88:9327015d4013 1605 }
bogdanm 88:9327015d4013 1606
bogdanm 88:9327015d4013 1607
bogdanm 88:9327015d4013 1608 /** \brief Decode Priority
bogdanm 88:9327015d4013 1609
bogdanm 88:9327015d4013 1610 The function decodes an interrupt priority value with a given priority group to
bogdanm 88:9327015d4013 1611 preemptive priority value and subpriority value.
bogdanm 88:9327015d4013 1612 In case of a conflict between priority grouping and available
bogdanm 88:9327015d4013 1613 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
bogdanm 88:9327015d4013 1614
bogdanm 88:9327015d4013 1615 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
bogdanm 88:9327015d4013 1616 \param [in] PriorityGroup Used priority group.
bogdanm 88:9327015d4013 1617 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
bogdanm 88:9327015d4013 1618 \param [out] pSubPriority Subpriority value (starting from 0).
bogdanm 88:9327015d4013 1619 */
bogdanm 88:9327015d4013 1620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
bogdanm 88:9327015d4013 1621 {
bogdanm 88:9327015d4013 1622 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
bogdanm 88:9327015d4013 1623 uint32_t PreemptPriorityBits;
bogdanm 88:9327015d4013 1624 uint32_t SubPriorityBits;
bogdanm 88:9327015d4013 1625
bogdanm 88:9327015d4013 1626 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
bogdanm 88:9327015d4013 1627 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
bogdanm 88:9327015d4013 1628
bogdanm 88:9327015d4013 1629 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
bogdanm 88:9327015d4013 1630 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
bogdanm 88:9327015d4013 1631 }
bogdanm 88:9327015d4013 1632
bogdanm 88:9327015d4013 1633
bogdanm 88:9327015d4013 1634 /** \brief System Reset
bogdanm 88:9327015d4013 1635
bogdanm 88:9327015d4013 1636 The function initiates a system reset request to reset the MCU.
bogdanm 88:9327015d4013 1637 */
bogdanm 88:9327015d4013 1638 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 88:9327015d4013 1639 {
bogdanm 88:9327015d4013 1640 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 88:9327015d4013 1641 buffered write are completed before reset */
bogdanm 88:9327015d4013 1642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 88:9327015d4013 1643 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
bogdanm 88:9327015d4013 1644 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
bogdanm 88:9327015d4013 1645 __DSB(); /* Ensure completion of memory access */
bogdanm 88:9327015d4013 1646 while(1); /* wait until reset */
bogdanm 88:9327015d4013 1647 }
bogdanm 88:9327015d4013 1648
bogdanm 88:9327015d4013 1649 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 88:9327015d4013 1650
bogdanm 88:9327015d4013 1651
bogdanm 88:9327015d4013 1652
bogdanm 88:9327015d4013 1653 /* ################################## SysTick function ############################################ */
bogdanm 88:9327015d4013 1654 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 88:9327015d4013 1655 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 88:9327015d4013 1656 \brief Functions that configure the System.
bogdanm 88:9327015d4013 1657 @{
bogdanm 88:9327015d4013 1658 */
bogdanm 88:9327015d4013 1659
bogdanm 88:9327015d4013 1660 #if (__Vendor_SysTickConfig == 0)
bogdanm 88:9327015d4013 1661
bogdanm 88:9327015d4013 1662 /** \brief System Tick Configuration
bogdanm 88:9327015d4013 1663
bogdanm 88:9327015d4013 1664 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 88:9327015d4013 1665 Counter is in free running mode to generate periodic interrupts.
bogdanm 88:9327015d4013 1666
bogdanm 88:9327015d4013 1667 \param [in] ticks Number of ticks between two interrupts.
bogdanm 88:9327015d4013 1668
bogdanm 88:9327015d4013 1669 \return 0 Function succeeded.
bogdanm 88:9327015d4013 1670 \return 1 Function failed.
bogdanm 88:9327015d4013 1671
bogdanm 88:9327015d4013 1672 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 88:9327015d4013 1673 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 88:9327015d4013 1674 must contain a vendor-specific implementation of this function.
bogdanm 88:9327015d4013 1675
bogdanm 88:9327015d4013 1676 */
bogdanm 88:9327015d4013 1677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 88:9327015d4013 1678 {
bogdanm 88:9327015d4013 1679 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
bogdanm 88:9327015d4013 1680
bogdanm 88:9327015d4013 1681 SysTick->LOAD = ticks - 1; /* set reload register */
bogdanm 88:9327015d4013 1682 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
bogdanm 88:9327015d4013 1683 SysTick->VAL = 0; /* Load the SysTick Counter Value */
bogdanm 88:9327015d4013 1684 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 88:9327015d4013 1685 SysTick_CTRL_TICKINT_Msk |
bogdanm 88:9327015d4013 1686 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
bogdanm 88:9327015d4013 1687 return (0); /* Function successful */
bogdanm 88:9327015d4013 1688 }
bogdanm 88:9327015d4013 1689
bogdanm 88:9327015d4013 1690 #endif
bogdanm 88:9327015d4013 1691
bogdanm 88:9327015d4013 1692 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 88:9327015d4013 1693
bogdanm 88:9327015d4013 1694
bogdanm 88:9327015d4013 1695
bogdanm 88:9327015d4013 1696 /* ##################################### Debug In/Output function ########################################### */
bogdanm 88:9327015d4013 1697 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 88:9327015d4013 1698 \defgroup CMSIS_core_DebugFunctions ITM Functions
bogdanm 88:9327015d4013 1699 \brief Functions that access the ITM debug interface.
bogdanm 88:9327015d4013 1700 @{
bogdanm 88:9327015d4013 1701 */
bogdanm 88:9327015d4013 1702
bogdanm 88:9327015d4013 1703 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
bogdanm 88:9327015d4013 1704 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
bogdanm 88:9327015d4013 1705
bogdanm 88:9327015d4013 1706
bogdanm 88:9327015d4013 1707 /** \brief ITM Send Character
bogdanm 88:9327015d4013 1708
bogdanm 88:9327015d4013 1709 The function transmits a character via the ITM channel 0, and
bogdanm 88:9327015d4013 1710 \li Just returns when no debugger is connected that has booked the output.
bogdanm 88:9327015d4013 1711 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
bogdanm 88:9327015d4013 1712
bogdanm 88:9327015d4013 1713 \param [in] ch Character to transmit.
bogdanm 88:9327015d4013 1714
bogdanm 88:9327015d4013 1715 \returns Character to transmit.
bogdanm 88:9327015d4013 1716 */
bogdanm 88:9327015d4013 1717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
bogdanm 88:9327015d4013 1718 {
bogdanm 88:9327015d4013 1719 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
bogdanm 88:9327015d4013 1720 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
bogdanm 88:9327015d4013 1721 {
bogdanm 88:9327015d4013 1722 while (ITM->PORT[0].u32 == 0);
bogdanm 88:9327015d4013 1723 ITM->PORT[0].u8 = (uint8_t) ch;
bogdanm 88:9327015d4013 1724 }
bogdanm 88:9327015d4013 1725 return (ch);
bogdanm 88:9327015d4013 1726 }
bogdanm 88:9327015d4013 1727
bogdanm 88:9327015d4013 1728
bogdanm 88:9327015d4013 1729 /** \brief ITM Receive Character
bogdanm 88:9327015d4013 1730
bogdanm 88:9327015d4013 1731 The function inputs a character via the external variable \ref ITM_RxBuffer.
bogdanm 88:9327015d4013 1732
bogdanm 88:9327015d4013 1733 \return Received character.
bogdanm 88:9327015d4013 1734 \return -1 No character pending.
bogdanm 88:9327015d4013 1735 */
bogdanm 88:9327015d4013 1736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
bogdanm 88:9327015d4013 1737 int32_t ch = -1; /* no character available */
bogdanm 88:9327015d4013 1738
bogdanm 88:9327015d4013 1739 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
bogdanm 88:9327015d4013 1740 ch = ITM_RxBuffer;
bogdanm 88:9327015d4013 1741 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
bogdanm 88:9327015d4013 1742 }
bogdanm 88:9327015d4013 1743
bogdanm 88:9327015d4013 1744 return (ch);
bogdanm 88:9327015d4013 1745 }
bogdanm 88:9327015d4013 1746
bogdanm 88:9327015d4013 1747
bogdanm 88:9327015d4013 1748 /** \brief ITM Check Character
bogdanm 88:9327015d4013 1749
bogdanm 88:9327015d4013 1750 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
bogdanm 88:9327015d4013 1751
bogdanm 88:9327015d4013 1752 \return 0 No character available.
bogdanm 88:9327015d4013 1753 \return 1 Character available.
bogdanm 88:9327015d4013 1754 */
bogdanm 88:9327015d4013 1755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
bogdanm 88:9327015d4013 1756
bogdanm 88:9327015d4013 1757 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
bogdanm 88:9327015d4013 1758 return (0); /* no character available */
bogdanm 88:9327015d4013 1759 } else {
bogdanm 88:9327015d4013 1760 return (1); /* character available */
bogdanm 88:9327015d4013 1761 }
bogdanm 88:9327015d4013 1762 }
bogdanm 88:9327015d4013 1763
bogdanm 88:9327015d4013 1764 /*@} end of CMSIS_core_DebugFunctions */
bogdanm 88:9327015d4013 1765
bogdanm 88:9327015d4013 1766 #endif /* __CORE_CM4_H_DEPENDANT */
bogdanm 88:9327015d4013 1767
bogdanm 88:9327015d4013 1768 #endif /* __CMSIS_GENERIC */
bogdanm 88:9327015d4013 1769
bogdanm 88:9327015d4013 1770 #ifdef __cplusplus
bogdanm 88:9327015d4013 1771 }
bogdanm 88:9327015d4013 1772 #endif