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TARGET_NUCLEO_F446RE/stm32f4xx_hal_eth.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
106:ba1f97679dad 
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 106:ba1f97679dad 1 /**
Kojto 106:ba1f97679dad 2 ******************************************************************************
Kojto 106:ba1f97679dad 3 * @file stm32f4xx_hal_eth.h
Kojto 106:ba1f97679dad 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
Kojto 106:ba1f97679dad 7 * @brief Header file of ETH HAL module.
Kojto 106:ba1f97679dad 8 ******************************************************************************
Kojto 106:ba1f97679dad 9 * @attention
Kojto 106:ba1f97679dad 10 *
Kojto 106:ba1f97679dad 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
Kojto 106:ba1f97679dad 12 *
Kojto 106:ba1f97679dad 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 106:ba1f97679dad 14 * are permitted provided that the following conditions are met:
Kojto 106:ba1f97679dad 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 106:ba1f97679dad 16 * this list of conditions and the following disclaimer.
Kojto 106:ba1f97679dad 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 106:ba1f97679dad 18 * this list of conditions and the following disclaimer in the documentation
Kojto 106:ba1f97679dad 19 * and/or other materials provided with the distribution.
Kojto 106:ba1f97679dad 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 106:ba1f97679dad 21 * may be used to endorse or promote products derived from this software
Kojto 106:ba1f97679dad 22 * without specific prior written permission.
Kojto 106:ba1f97679dad 23 *
Kojto 106:ba1f97679dad 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 106:ba1f97679dad 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 106:ba1f97679dad 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 106:ba1f97679dad 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 106:ba1f97679dad 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 106:ba1f97679dad 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 106:ba1f97679dad 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 106:ba1f97679dad 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 106:ba1f97679dad 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 106:ba1f97679dad 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 106:ba1f97679dad 34 *
Kojto 106:ba1f97679dad 35 ******************************************************************************
Kojto 106:ba1f97679dad 36 */
Kojto 106:ba1f97679dad 37
Kojto 106:ba1f97679dad 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 106:ba1f97679dad 39 #ifndef __STM32F4xx_HAL_ETH_H
Kojto 106:ba1f97679dad 40 #define __STM32F4xx_HAL_ETH_H
Kojto 106:ba1f97679dad 41
Kojto 106:ba1f97679dad 42 #ifdef __cplusplus
Kojto 106:ba1f97679dad 43 extern "C" {
Kojto 106:ba1f97679dad 44 #endif
Kojto 106:ba1f97679dad 45
Kojto 110:165afa46840b 46 #if defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) ||\
Kojto 110:165afa46840b 47 defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
Kojto 106:ba1f97679dad 48 /* Includes ------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 49 #include "stm32f4xx_hal_def.h"
Kojto 106:ba1f97679dad 50
Kojto 106:ba1f97679dad 51 /** @addtogroup STM32F4xx_HAL_Driver
Kojto 106:ba1f97679dad 52 * @{
Kojto 106:ba1f97679dad 53 */
Kojto 106:ba1f97679dad 54
Kojto 106:ba1f97679dad 55 /** @addtogroup ETH
Kojto 106:ba1f97679dad 56 * @{
Kojto 106:ba1f97679dad 57 */
Kojto 106:ba1f97679dad 58
Kojto 106:ba1f97679dad 59 /** @addtogroup ETH_Private_Macros
Kojto 106:ba1f97679dad 60 * @{
Kojto 106:ba1f97679dad 61 */
Kojto 106:ba1f97679dad 62 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
Kojto 106:ba1f97679dad 63 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
Kojto 106:ba1f97679dad 64 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
Kojto 106:ba1f97679dad 65 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
Kojto 106:ba1f97679dad 66 ((SPEED) == ETH_SPEED_100M))
Kojto 106:ba1f97679dad 67 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
Kojto 106:ba1f97679dad 68 ((MODE) == ETH_MODE_HALFDUPLEX))
Kojto 106:ba1f97679dad 69 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
Kojto 106:ba1f97679dad 70 ((MODE) == ETH_RXINTERRUPT_MODE))
Kojto 106:ba1f97679dad 71 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
Kojto 106:ba1f97679dad 72 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
Kojto 106:ba1f97679dad 73 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
Kojto 106:ba1f97679dad 74 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
Kojto 106:ba1f97679dad 75 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
Kojto 106:ba1f97679dad 76 ((CMD) == ETH_WATCHDOG_DISABLE))
Kojto 106:ba1f97679dad 77 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
Kojto 106:ba1f97679dad 78 ((CMD) == ETH_JABBER_DISABLE))
Kojto 106:ba1f97679dad 79 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
Kojto 106:ba1f97679dad 80 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
Kojto 106:ba1f97679dad 81 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
Kojto 106:ba1f97679dad 82 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
Kojto 106:ba1f97679dad 83 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
Kojto 106:ba1f97679dad 84 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
Kojto 106:ba1f97679dad 85 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
Kojto 106:ba1f97679dad 86 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
Kojto 106:ba1f97679dad 87 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
Kojto 106:ba1f97679dad 88 ((CMD) == ETH_CARRIERSENCE_DISABLE))
Kojto 106:ba1f97679dad 89 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
Kojto 106:ba1f97679dad 90 ((CMD) == ETH_RECEIVEOWN_DISABLE))
Kojto 106:ba1f97679dad 91 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
Kojto 106:ba1f97679dad 92 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
Kojto 106:ba1f97679dad 93 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
Kojto 106:ba1f97679dad 94 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
Kojto 106:ba1f97679dad 95 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
Kojto 106:ba1f97679dad 96 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
Kojto 106:ba1f97679dad 97 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
Kojto 106:ba1f97679dad 98 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
Kojto 106:ba1f97679dad 99 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
Kojto 106:ba1f97679dad 100 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
Kojto 106:ba1f97679dad 101 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
Kojto 106:ba1f97679dad 102 ((LIMIT) == ETH_BACKOFFLIMIT_1))
Kojto 106:ba1f97679dad 103 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
Kojto 106:ba1f97679dad 104 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
Kojto 106:ba1f97679dad 105 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
Kojto 106:ba1f97679dad 106 ((CMD) == ETH_RECEIVEAll_DISABLE))
Kojto 106:ba1f97679dad 107 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
Kojto 106:ba1f97679dad 108 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
Kojto 106:ba1f97679dad 109 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
Kojto 106:ba1f97679dad 110 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
Kojto 106:ba1f97679dad 111 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
Kojto 106:ba1f97679dad 112 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
Kojto 106:ba1f97679dad 113 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
Kojto 106:ba1f97679dad 114 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
Kojto 106:ba1f97679dad 115 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
Kojto 106:ba1f97679dad 116 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
Kojto 106:ba1f97679dad 117 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
Kojto 106:ba1f97679dad 118 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
Kojto 106:ba1f97679dad 119 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
Kojto 106:ba1f97679dad 120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
Kojto 106:ba1f97679dad 121 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
Kojto 106:ba1f97679dad 122 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
Kojto 106:ba1f97679dad 123 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
Kojto 106:ba1f97679dad 124 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
Kojto 106:ba1f97679dad 125 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
Kojto 106:ba1f97679dad 126 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
Kojto 106:ba1f97679dad 127 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
Kojto 106:ba1f97679dad 128 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
Kojto 106:ba1f97679dad 129 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
Kojto 106:ba1f97679dad 130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
Kojto 106:ba1f97679dad 131 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
Kojto 106:ba1f97679dad 132 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
Kojto 106:ba1f97679dad 133 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
Kojto 106:ba1f97679dad 134 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
Kojto 106:ba1f97679dad 135 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
Kojto 106:ba1f97679dad 136 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
Kojto 106:ba1f97679dad 137 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
Kojto 106:ba1f97679dad 138 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
Kojto 106:ba1f97679dad 139 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
Kojto 106:ba1f97679dad 140 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
Kojto 106:ba1f97679dad 141 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
Kojto 106:ba1f97679dad 142 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
Kojto 106:ba1f97679dad 143 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
Kojto 106:ba1f97679dad 144 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
Kojto 106:ba1f97679dad 145 ((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto 106:ba1f97679dad 146 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
Kojto 106:ba1f97679dad 147 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
Kojto 106:ba1f97679dad 148 ((ADDRESS) == ETH_MAC_ADDRESS3))
Kojto 106:ba1f97679dad 149 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
Kojto 106:ba1f97679dad 150 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
Kojto 106:ba1f97679dad 151 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
Kojto 106:ba1f97679dad 152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
Kojto 106:ba1f97679dad 153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
Kojto 106:ba1f97679dad 154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
Kojto 106:ba1f97679dad 155 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
Kojto 106:ba1f97679dad 156 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
Kojto 106:ba1f97679dad 157 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
Kojto 106:ba1f97679dad 158 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
Kojto 106:ba1f97679dad 159 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
Kojto 106:ba1f97679dad 160 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
Kojto 106:ba1f97679dad 161 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
Kojto 106:ba1f97679dad 162 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
Kojto 106:ba1f97679dad 163 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
Kojto 106:ba1f97679dad 164 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
Kojto 106:ba1f97679dad 165 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
Kojto 106:ba1f97679dad 166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
Kojto 106:ba1f97679dad 167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
Kojto 106:ba1f97679dad 168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
Kojto 106:ba1f97679dad 169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
Kojto 106:ba1f97679dad 170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
Kojto 106:ba1f97679dad 171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
Kojto 106:ba1f97679dad 172 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
Kojto 106:ba1f97679dad 173 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
Kojto 106:ba1f97679dad 174 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
Kojto 106:ba1f97679dad 175 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
Kojto 106:ba1f97679dad 176 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
Kojto 106:ba1f97679dad 177 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
Kojto 106:ba1f97679dad 178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
Kojto 106:ba1f97679dad 179 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
Kojto 106:ba1f97679dad 180 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
Kojto 106:ba1f97679dad 181 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
Kojto 106:ba1f97679dad 182 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
Kojto 106:ba1f97679dad 183 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
Kojto 106:ba1f97679dad 184 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
Kojto 106:ba1f97679dad 185 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
Kojto 106:ba1f97679dad 186 ((CMD) == ETH_FIXEDBURST_DISABLE))
Kojto 106:ba1f97679dad 187 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
Kojto 106:ba1f97679dad 188 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
Kojto 106:ba1f97679dad 189 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
Kojto 106:ba1f97679dad 190 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
Kojto 106:ba1f97679dad 191 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
Kojto 106:ba1f97679dad 192 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
Kojto 106:ba1f97679dad 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
Kojto 106:ba1f97679dad 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
Kojto 106:ba1f97679dad 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
Kojto 106:ba1f97679dad 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
Kojto 106:ba1f97679dad 197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
Kojto 106:ba1f97679dad 198 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto 106:ba1f97679dad 199 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
Kojto 106:ba1f97679dad 200 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
Kojto 106:ba1f97679dad 201 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
Kojto 106:ba1f97679dad 202 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
Kojto 106:ba1f97679dad 203 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
Kojto 106:ba1f97679dad 204 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
Kojto 106:ba1f97679dad 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
Kojto 106:ba1f97679dad 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
Kojto 106:ba1f97679dad 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
Kojto 106:ba1f97679dad 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
Kojto 106:ba1f97679dad 209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
Kojto 106:ba1f97679dad 210 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
Kojto 106:ba1f97679dad 211 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
Kojto 106:ba1f97679dad 212 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
Kojto 106:ba1f97679dad 213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
Kojto 106:ba1f97679dad 214 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
Kojto 106:ba1f97679dad 215 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
Kojto 106:ba1f97679dad 216 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
Kojto 106:ba1f97679dad 217 #define IS_ETH_DMATXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMATXDESC_OWN) || \
Kojto 106:ba1f97679dad 218 ((FLAG) == ETH_DMATXDESC_IC) || \
Kojto 106:ba1f97679dad 219 ((FLAG) == ETH_DMATXDESC_LS) || \
Kojto 106:ba1f97679dad 220 ((FLAG) == ETH_DMATXDESC_FS) || \
Kojto 106:ba1f97679dad 221 ((FLAG) == ETH_DMATXDESC_DC) || \
Kojto 106:ba1f97679dad 222 ((FLAG) == ETH_DMATXDESC_DP) || \
Kojto 106:ba1f97679dad 223 ((FLAG) == ETH_DMATXDESC_TTSE) || \
Kojto 106:ba1f97679dad 224 ((FLAG) == ETH_DMATXDESC_TER) || \
Kojto 106:ba1f97679dad 225 ((FLAG) == ETH_DMATXDESC_TCH) || \
Kojto 106:ba1f97679dad 226 ((FLAG) == ETH_DMATXDESC_TTSS) || \
Kojto 106:ba1f97679dad 227 ((FLAG) == ETH_DMATXDESC_IHE) || \
Kojto 106:ba1f97679dad 228 ((FLAG) == ETH_DMATXDESC_ES) || \
Kojto 106:ba1f97679dad 229 ((FLAG) == ETH_DMATXDESC_JT) || \
Kojto 106:ba1f97679dad 230 ((FLAG) == ETH_DMATXDESC_FF) || \
Kojto 106:ba1f97679dad 231 ((FLAG) == ETH_DMATXDESC_PCE) || \
Kojto 106:ba1f97679dad 232 ((FLAG) == ETH_DMATXDESC_LCA) || \
Kojto 106:ba1f97679dad 233 ((FLAG) == ETH_DMATXDESC_NC) || \
Kojto 106:ba1f97679dad 234 ((FLAG) == ETH_DMATXDESC_LCO) || \
Kojto 106:ba1f97679dad 235 ((FLAG) == ETH_DMATXDESC_EC) || \
Kojto 106:ba1f97679dad 236 ((FLAG) == ETH_DMATXDESC_VF) || \
Kojto 106:ba1f97679dad 237 ((FLAG) == ETH_DMATXDESC_CC) || \
Kojto 106:ba1f97679dad 238 ((FLAG) == ETH_DMATXDESC_ED) || \
Kojto 106:ba1f97679dad 239 ((FLAG) == ETH_DMATXDESC_UF) || \
Kojto 106:ba1f97679dad 240 ((FLAG) == ETH_DMATXDESC_DB))
Kojto 106:ba1f97679dad 241 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
Kojto 106:ba1f97679dad 242 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
Kojto 106:ba1f97679dad 243 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
Kojto 106:ba1f97679dad 244 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
Kojto 106:ba1f97679dad 245 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
Kojto 106:ba1f97679dad 246 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
Kojto 106:ba1f97679dad 247 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
Kojto 106:ba1f97679dad 248 #define IS_ETH_DMARXDESC_GET_FLAG(FLAG) (((FLAG) == ETH_DMARXDESC_OWN) || \
Kojto 106:ba1f97679dad 249 ((FLAG) == ETH_DMARXDESC_AFM) || \
Kojto 106:ba1f97679dad 250 ((FLAG) == ETH_DMARXDESC_ES) || \
Kojto 106:ba1f97679dad 251 ((FLAG) == ETH_DMARXDESC_DE) || \
Kojto 106:ba1f97679dad 252 ((FLAG) == ETH_DMARXDESC_SAF) || \
Kojto 106:ba1f97679dad 253 ((FLAG) == ETH_DMARXDESC_LE) || \
Kojto 106:ba1f97679dad 254 ((FLAG) == ETH_DMARXDESC_OE) || \
Kojto 106:ba1f97679dad 255 ((FLAG) == ETH_DMARXDESC_VLAN) || \
Kojto 106:ba1f97679dad 256 ((FLAG) == ETH_DMARXDESC_FS) || \
Kojto 106:ba1f97679dad 257 ((FLAG) == ETH_DMARXDESC_LS) || \
Kojto 106:ba1f97679dad 258 ((FLAG) == ETH_DMARXDESC_IPV4HCE) || \
Kojto 106:ba1f97679dad 259 ((FLAG) == ETH_DMARXDESC_LC) || \
Kojto 106:ba1f97679dad 260 ((FLAG) == ETH_DMARXDESC_FT) || \
Kojto 106:ba1f97679dad 261 ((FLAG) == ETH_DMARXDESC_RWT) || \
Kojto 106:ba1f97679dad 262 ((FLAG) == ETH_DMARXDESC_RE) || \
Kojto 106:ba1f97679dad 263 ((FLAG) == ETH_DMARXDESC_DBE) || \
Kojto 106:ba1f97679dad 264 ((FLAG) == ETH_DMARXDESC_CE) || \
Kojto 106:ba1f97679dad 265 ((FLAG) == ETH_DMARXDESC_MAMPCE))
Kojto 106:ba1f97679dad 266 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
Kojto 106:ba1f97679dad 267 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
Kojto 106:ba1f97679dad 268 #define IS_ETH_PMT_GET_FLAG(FLAG) (((FLAG) == ETH_PMT_FLAG_WUFR) || \
Kojto 106:ba1f97679dad 269 ((FLAG) == ETH_PMT_FLAG_MPR))
Kojto 106:ba1f97679dad 270 #define IS_ETH_DMA_FLAG(FLAG) ((((FLAG) & (uint32_t)0xC7FE1800) == 0x00) && ((FLAG) != 0x00))
Kojto 106:ba1f97679dad 271 #define IS_ETH_DMA_GET_FLAG(FLAG) (((FLAG) == ETH_DMA_FLAG_TST) || ((FLAG) == ETH_DMA_FLAG_PMT) || \
Kojto 106:ba1f97679dad 272 ((FLAG) == ETH_DMA_FLAG_MMC) || ((FLAG) == ETH_DMA_FLAG_DATATRANSFERERROR) || \
Kojto 106:ba1f97679dad 273 ((FLAG) == ETH_DMA_FLAG_READWRITEERROR) || ((FLAG) == ETH_DMA_FLAG_ACCESSERROR) || \
Kojto 106:ba1f97679dad 274 ((FLAG) == ETH_DMA_FLAG_NIS) || ((FLAG) == ETH_DMA_FLAG_AIS) || \
Kojto 106:ba1f97679dad 275 ((FLAG) == ETH_DMA_FLAG_ER) || ((FLAG) == ETH_DMA_FLAG_FBE) || \
Kojto 106:ba1f97679dad 276 ((FLAG) == ETH_DMA_FLAG_ET) || ((FLAG) == ETH_DMA_FLAG_RWT) || \
Kojto 106:ba1f97679dad 277 ((FLAG) == ETH_DMA_FLAG_RPS) || ((FLAG) == ETH_DMA_FLAG_RBU) || \
Kojto 106:ba1f97679dad 278 ((FLAG) == ETH_DMA_FLAG_R) || ((FLAG) == ETH_DMA_FLAG_TU) || \
Kojto 106:ba1f97679dad 279 ((FLAG) == ETH_DMA_FLAG_RO) || ((FLAG) == ETH_DMA_FLAG_TJT) || \
Kojto 106:ba1f97679dad 280 ((FLAG) == ETH_DMA_FLAG_TBU) || ((FLAG) == ETH_DMA_FLAG_TPS) || \
Kojto 106:ba1f97679dad 281 ((FLAG) == ETH_DMA_FLAG_T))
Kojto 106:ba1f97679dad 282 #define IS_ETH_MAC_IT(IT) ((((IT) & (uint32_t)0xFFFFFDF1) == 0x00) && ((IT) != 0x00))
Kojto 106:ba1f97679dad 283 #define IS_ETH_MAC_GET_IT(IT) (((IT) == ETH_MAC_IT_TST) || ((IT) == ETH_MAC_IT_MMCT) || \
Kojto 106:ba1f97679dad 284 ((IT) == ETH_MAC_IT_MMCR) || ((IT) == ETH_MAC_IT_MMC) || \
Kojto 106:ba1f97679dad 285 ((IT) == ETH_MAC_IT_PMT))
Kojto 106:ba1f97679dad 286 #define IS_ETH_MAC_GET_FLAG(FLAG) (((FLAG) == ETH_MAC_FLAG_TST) || ((FLAG) == ETH_MAC_FLAG_MMCT) || \
Kojto 106:ba1f97679dad 287 ((FLAG) == ETH_MAC_FLAG_MMCR) || ((FLAG) == ETH_MAC_FLAG_MMC) || \
Kojto 106:ba1f97679dad 288 ((FLAG) == ETH_MAC_FLAG_PMT))
Kojto 106:ba1f97679dad 289 #define IS_ETH_DMA_IT(IT) ((((IT) & (uint32_t)0xC7FE1800) == 0x00) && ((IT) != 0x00))
Kojto 106:ba1f97679dad 290 #define IS_ETH_DMA_GET_IT(IT) (((IT) == ETH_DMA_IT_TST) || ((IT) == ETH_DMA_IT_PMT) || \
Kojto 106:ba1f97679dad 291 ((IT) == ETH_DMA_IT_MMC) || ((IT) == ETH_DMA_IT_NIS) || \
Kojto 106:ba1f97679dad 292 ((IT) == ETH_DMA_IT_AIS) || ((IT) == ETH_DMA_IT_ER) || \
Kojto 106:ba1f97679dad 293 ((IT) == ETH_DMA_IT_FBE) || ((IT) == ETH_DMA_IT_ET) || \
Kojto 106:ba1f97679dad 294 ((IT) == ETH_DMA_IT_RWT) || ((IT) == ETH_DMA_IT_RPS) || \
Kojto 106:ba1f97679dad 295 ((IT) == ETH_DMA_IT_RBU) || ((IT) == ETH_DMA_IT_R) || \
Kojto 106:ba1f97679dad 296 ((IT) == ETH_DMA_IT_TU) || ((IT) == ETH_DMA_IT_RO) || \
Kojto 106:ba1f97679dad 297 ((IT) == ETH_DMA_IT_TJT) || ((IT) == ETH_DMA_IT_TBU) || \
Kojto 106:ba1f97679dad 298 ((IT) == ETH_DMA_IT_TPS) || ((IT) == ETH_DMA_IT_T))
Kojto 106:ba1f97679dad 299 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
Kojto 106:ba1f97679dad 300 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
Kojto 106:ba1f97679dad 301 #define IS_ETH_MMC_IT(IT) (((((IT) & (uint32_t)0xFFDF3FFF) == 0x00) || (((IT) & (uint32_t)0xEFFDFF9F) == 0x00)) && \
Kojto 106:ba1f97679dad 302 ((IT) != 0x00))
Kojto 106:ba1f97679dad 303 #define IS_ETH_MMC_GET_IT(IT) (((IT) == ETH_MMC_IT_TGF) || ((IT) == ETH_MMC_IT_TGFMSC) || \
Kojto 106:ba1f97679dad 304 ((IT) == ETH_MMC_IT_TGFSC) || ((IT) == ETH_MMC_IT_RGUF) || \
Kojto 106:ba1f97679dad 305 ((IT) == ETH_MMC_IT_RFAE) || ((IT) == ETH_MMC_IT_RFCE))
Kojto 106:ba1f97679dad 306 #define IS_ETH_ENHANCED_DESCRIPTOR_FORMAT(CMD) (((CMD) == ETH_DMAENHANCEDDESCRIPTOR_ENABLE) || \
Kojto 106:ba1f97679dad 307 ((CMD) == ETH_DMAENHANCEDDESCRIPTOR_DISABLE))
Kojto 106:ba1f97679dad 308
Kojto 106:ba1f97679dad 309
Kojto 106:ba1f97679dad 310 /**
Kojto 106:ba1f97679dad 311 * @}
Kojto 106:ba1f97679dad 312 */
Kojto 106:ba1f97679dad 313
Kojto 106:ba1f97679dad 314 /** @addtogroup ETH_Private_Defines
Kojto 106:ba1f97679dad 315 * @{
Kojto 106:ba1f97679dad 316 */
Kojto 106:ba1f97679dad 317 /* Delay to wait when writing to some Ethernet registers */
Kojto 106:ba1f97679dad 318 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
Kojto 106:ba1f97679dad 319
Kojto 106:ba1f97679dad 320 /* ETHERNET Errors */
Kojto 106:ba1f97679dad 321 #define ETH_SUCCESS ((uint32_t)0)
Kojto 106:ba1f97679dad 322 #define ETH_ERROR ((uint32_t)1)
Kojto 106:ba1f97679dad 323
Kojto 106:ba1f97679dad 324 /* ETHERNET DMA Tx descriptors Collision Count Shift */
Kojto 106:ba1f97679dad 325 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
Kojto 106:ba1f97679dad 326
Kojto 106:ba1f97679dad 327 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
Kojto 106:ba1f97679dad 328 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto 106:ba1f97679dad 329
Kojto 106:ba1f97679dad 330 /* ETHERNET DMA Rx descriptors Frame Length Shift */
Kojto 106:ba1f97679dad 331 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
Kojto 106:ba1f97679dad 332
Kojto 106:ba1f97679dad 333 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
Kojto 106:ba1f97679dad 334 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
Kojto 106:ba1f97679dad 335
Kojto 106:ba1f97679dad 336 /* ETHERNET DMA Rx descriptors Frame length Shift */
Kojto 106:ba1f97679dad 337 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
Kojto 106:ba1f97679dad 338
Kojto 106:ba1f97679dad 339 /* ETHERNET MAC address offsets */
Kojto 106:ba1f97679dad 340 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
Kojto 106:ba1f97679dad 341 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
Kojto 106:ba1f97679dad 342
Kojto 106:ba1f97679dad 343 /* ETHERNET MACMIIAR register Mask */
Kojto 106:ba1f97679dad 344 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
Kojto 106:ba1f97679dad 345
Kojto 106:ba1f97679dad 346 /* ETHERNET MACCR register Mask */
Kojto 106:ba1f97679dad 347 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
Kojto 106:ba1f97679dad 348
Kojto 106:ba1f97679dad 349 /* ETHERNET MACFCR register Mask */
Kojto 106:ba1f97679dad 350 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
Kojto 106:ba1f97679dad 351
Kojto 106:ba1f97679dad 352 /* ETHERNET DMAOMR register Mask */
Kojto 106:ba1f97679dad 353 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
Kojto 106:ba1f97679dad 354
Kojto 106:ba1f97679dad 355 /* ETHERNET Remote Wake-up frame register length */
Kojto 106:ba1f97679dad 356 #define ETH_WAKEUP_REGISTER_LENGTH 8
Kojto 106:ba1f97679dad 357
Kojto 106:ba1f97679dad 358 /* ETHERNET Missed frames counter Shift */
Kojto 106:ba1f97679dad 359 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
Kojto 106:ba1f97679dad 360 /**
Kojto 106:ba1f97679dad 361 * @}
Kojto 106:ba1f97679dad 362 */
Kojto 106:ba1f97679dad 363
Kojto 106:ba1f97679dad 364 /* Exported types ------------------------------------------------------------*/
Kojto 106:ba1f97679dad 365 /** @defgroup ETH_Exported_Types ETH Exported Types
Kojto 106:ba1f97679dad 366 * @{
Kojto 106:ba1f97679dad 367 */
Kojto 106:ba1f97679dad 368
Kojto 106:ba1f97679dad 369 /**
Kojto 106:ba1f97679dad 370 * @brief HAL State structures definition
Kojto 106:ba1f97679dad 371 */
Kojto 106:ba1f97679dad 372 typedef enum
Kojto 106:ba1f97679dad 373 {
Kojto 106:ba1f97679dad 374 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
Kojto 106:ba1f97679dad 375 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
Kojto 106:ba1f97679dad 376 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
Kojto 106:ba1f97679dad 377 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
Kojto 106:ba1f97679dad 378 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
Kojto 106:ba1f97679dad 379 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
Kojto 106:ba1f97679dad 380 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
Kojto 106:ba1f97679dad 381 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
Kojto 106:ba1f97679dad 382 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
Kojto 106:ba1f97679dad 383 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
Kojto 106:ba1f97679dad 384 }HAL_ETH_StateTypeDef;
Kojto 106:ba1f97679dad 385
Kojto 106:ba1f97679dad 386 /**
Kojto 106:ba1f97679dad 387 * @brief ETH Init Structure definition
Kojto 106:ba1f97679dad 388 */
Kojto 106:ba1f97679dad 389
Kojto 106:ba1f97679dad 390 typedef struct
Kojto 106:ba1f97679dad 391 {
Kojto 106:ba1f97679dad 392 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
Kojto 106:ba1f97679dad 393 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
Kojto 106:ba1f97679dad 394 and the mode (half/full-duplex).
Kojto 106:ba1f97679dad 395 This parameter can be a value of @ref ETH_AutoNegotiation */
Kojto 106:ba1f97679dad 396
Kojto 106:ba1f97679dad 397 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
Kojto 106:ba1f97679dad 398 This parameter can be a value of @ref ETH_Speed */
Kojto 106:ba1f97679dad 399
Kojto 106:ba1f97679dad 400 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
Kojto 106:ba1f97679dad 401 This parameter can be a value of @ref ETH_Duplex_Mode */
Kojto 106:ba1f97679dad 402
Kojto 106:ba1f97679dad 403 uint16_t PhyAddress; /*!< Ethernet PHY address.
Kojto 106:ba1f97679dad 404 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto 106:ba1f97679dad 405
Kojto 106:ba1f97679dad 406 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
Kojto 106:ba1f97679dad 407
Kojto 106:ba1f97679dad 408 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
Kojto 106:ba1f97679dad 409 This parameter can be a value of @ref ETH_Rx_Mode */
Kojto 106:ba1f97679dad 410
Kojto 106:ba1f97679dad 411 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
Kojto 106:ba1f97679dad 412 This parameter can be a value of @ref ETH_Checksum_Mode */
Kojto 106:ba1f97679dad 413
Kojto 106:ba1f97679dad 414 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
Kojto 106:ba1f97679dad 415 This parameter can be a value of @ref ETH_Media_Interface */
Kojto 106:ba1f97679dad 416
Kojto 106:ba1f97679dad 417 } ETH_InitTypeDef;
Kojto 106:ba1f97679dad 418
Kojto 106:ba1f97679dad 419
Kojto 106:ba1f97679dad 420 /**
Kojto 106:ba1f97679dad 421 * @brief ETH MAC Configuration Structure definition
Kojto 106:ba1f97679dad 422 */
Kojto 106:ba1f97679dad 423
Kojto 106:ba1f97679dad 424 typedef struct
Kojto 106:ba1f97679dad 425 {
Kojto 106:ba1f97679dad 426 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
Kojto 106:ba1f97679dad 427 When enabled, the MAC allows no more then 2048 bytes to be received.
Kojto 106:ba1f97679dad 428 When disabled, the MAC can receive up to 16384 bytes.
Kojto 106:ba1f97679dad 429 This parameter can be a value of @ref ETH_Watchdog */
Kojto 106:ba1f97679dad 430
Kojto 106:ba1f97679dad 431 uint32_t Jabber; /*!< Selects or not Jabber timer
Kojto 106:ba1f97679dad 432 When enabled, the MAC allows no more then 2048 bytes to be sent.
Kojto 106:ba1f97679dad 433 When disabled, the MAC can send up to 16384 bytes.
Kojto 106:ba1f97679dad 434 This parameter can be a value of @ref ETH_Jabber */
Kojto 106:ba1f97679dad 435
Kojto 106:ba1f97679dad 436 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
Kojto 106:ba1f97679dad 437 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
Kojto 106:ba1f97679dad 438
Kojto 106:ba1f97679dad 439 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
Kojto 106:ba1f97679dad 440 This parameter can be a value of @ref ETH_Carrier_Sense */
Kojto 106:ba1f97679dad 441
Kojto 106:ba1f97679dad 442 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
Kojto 106:ba1f97679dad 443 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
Kojto 106:ba1f97679dad 444 in Half-Duplex mode.
Kojto 106:ba1f97679dad 445 This parameter can be a value of @ref ETH_Receive_Own */
Kojto 106:ba1f97679dad 446
Kojto 106:ba1f97679dad 447 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
Kojto 106:ba1f97679dad 448 This parameter can be a value of @ref ETH_Loop_Back_Mode */
Kojto 106:ba1f97679dad 449
Kojto 106:ba1f97679dad 450 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
Kojto 106:ba1f97679dad 451 This parameter can be a value of @ref ETH_Checksum_Offload */
Kojto 106:ba1f97679dad 452
Kojto 106:ba1f97679dad 453 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
Kojto 106:ba1f97679dad 454 when a collision occurs (Half-Duplex mode).
Kojto 106:ba1f97679dad 455 This parameter can be a value of @ref ETH_Retry_Transmission */
Kojto 106:ba1f97679dad 456
Kojto 106:ba1f97679dad 457 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
Kojto 106:ba1f97679dad 458 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
Kojto 106:ba1f97679dad 459
Kojto 106:ba1f97679dad 460 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
Kojto 106:ba1f97679dad 461 This parameter can be a value of @ref ETH_Back_Off_Limit */
Kojto 106:ba1f97679dad 462
Kojto 106:ba1f97679dad 463 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
Kojto 106:ba1f97679dad 464 This parameter can be a value of @ref ETH_Deferral_Check */
Kojto 106:ba1f97679dad 465
Kojto 106:ba1f97679dad 466 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
Kojto 106:ba1f97679dad 467 This parameter can be a value of @ref ETH_Receive_All */
Kojto 106:ba1f97679dad 468
Kojto 106:ba1f97679dad 469 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
Kojto 106:ba1f97679dad 470 This parameter can be a value of @ref ETH_Source_Addr_Filter */
Kojto 106:ba1f97679dad 471
Kojto 106:ba1f97679dad 472 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
Kojto 106:ba1f97679dad 473 This parameter can be a value of @ref ETH_Pass_Control_Frames */
Kojto 106:ba1f97679dad 474
Kojto 106:ba1f97679dad 475 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
Kojto 106:ba1f97679dad 476 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
Kojto 106:ba1f97679dad 477
Kojto 106:ba1f97679dad 478 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
Kojto 106:ba1f97679dad 479 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
Kojto 106:ba1f97679dad 480
Kojto 106:ba1f97679dad 481 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
Kojto 106:ba1f97679dad 482 This parameter can be a value of @ref ETH_Promiscuous_Mode */
Kojto 106:ba1f97679dad 483
Kojto 106:ba1f97679dad 484 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto 106:ba1f97679dad 485 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
Kojto 106:ba1f97679dad 486
Kojto 106:ba1f97679dad 487 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
Kojto 106:ba1f97679dad 488 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
Kojto 106:ba1f97679dad 489
Kojto 106:ba1f97679dad 490 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
Kojto 106:ba1f97679dad 491 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto 106:ba1f97679dad 492
Kojto 106:ba1f97679dad 493 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
Kojto 106:ba1f97679dad 494 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
Kojto 106:ba1f97679dad 495
Kojto 106:ba1f97679dad 496 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
Kojto 106:ba1f97679dad 497 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
Kojto 106:ba1f97679dad 498
Kojto 106:ba1f97679dad 499 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
Kojto 106:ba1f97679dad 500 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
Kojto 106:ba1f97679dad 501
Kojto 106:ba1f97679dad 502 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
Kojto 106:ba1f97679dad 503 automatic retransmission of PAUSE Frame.
Kojto 106:ba1f97679dad 504 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
Kojto 106:ba1f97679dad 505
Kojto 106:ba1f97679dad 506 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
Kojto 106:ba1f97679dad 507 unicast address and unique multicast address).
Kojto 106:ba1f97679dad 508 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
Kojto 106:ba1f97679dad 509
Kojto 106:ba1f97679dad 510 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
Kojto 106:ba1f97679dad 511 disable its transmitter for a specified time (Pause Time)
Kojto 106:ba1f97679dad 512 This parameter can be a value of @ref ETH_Receive_Flow_Control */
Kojto 106:ba1f97679dad 513
Kojto 106:ba1f97679dad 514 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
Kojto 106:ba1f97679dad 515 or the MAC back-pressure operation (Half-Duplex mode)
Kojto 106:ba1f97679dad 516 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
Kojto 106:ba1f97679dad 517
Kojto 106:ba1f97679dad 518 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
Kojto 106:ba1f97679dad 519 comparison and filtering.
Kojto 106:ba1f97679dad 520 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
Kojto 106:ba1f97679dad 521
Kojto 106:ba1f97679dad 522 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
Kojto 106:ba1f97679dad 523
Kojto 106:ba1f97679dad 524 } ETH_MACInitTypeDef;
Kojto 106:ba1f97679dad 525
Kojto 106:ba1f97679dad 526
Kojto 106:ba1f97679dad 527 /**
Kojto 106:ba1f97679dad 528 * @brief ETH DMA Configuration Structure definition
Kojto 106:ba1f97679dad 529 */
Kojto 106:ba1f97679dad 530
Kojto 106:ba1f97679dad 531 typedef struct
Kojto 106:ba1f97679dad 532 {
Kojto 106:ba1f97679dad 533 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
Kojto 106:ba1f97679dad 534 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
Kojto 106:ba1f97679dad 535
Kojto 106:ba1f97679dad 536 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
Kojto 106:ba1f97679dad 537 This parameter can be a value of @ref ETH_Receive_Store_Forward */
Kojto 106:ba1f97679dad 538
Kojto 106:ba1f97679dad 539 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
Kojto 106:ba1f97679dad 540 This parameter can be a value of @ref ETH_Flush_Received_Frame */
Kojto 106:ba1f97679dad 541
Kojto 106:ba1f97679dad 542 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
Kojto 106:ba1f97679dad 543 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
Kojto 106:ba1f97679dad 544
Kojto 106:ba1f97679dad 545 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
Kojto 106:ba1f97679dad 546 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
Kojto 106:ba1f97679dad 547
Kojto 106:ba1f97679dad 548 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
Kojto 106:ba1f97679dad 549 This parameter can be a value of @ref ETH_Forward_Error_Frames */
Kojto 106:ba1f97679dad 550
Kojto 106:ba1f97679dad 551 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
Kojto 106:ba1f97679dad 552 and length less than 64 bytes) including pad-bytes and CRC)
Kojto 106:ba1f97679dad 553 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
Kojto 106:ba1f97679dad 554
Kojto 106:ba1f97679dad 555 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
Kojto 106:ba1f97679dad 556 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
Kojto 106:ba1f97679dad 557
Kojto 106:ba1f97679dad 558 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
Kojto 106:ba1f97679dad 559 frame of Transmit data even before obtaining the status for the first frame.
Kojto 106:ba1f97679dad 560 This parameter can be a value of @ref ETH_Second_Frame_Operate */
Kojto 106:ba1f97679dad 561
Kojto 106:ba1f97679dad 562 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
Kojto 106:ba1f97679dad 563 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
Kojto 106:ba1f97679dad 564
Kojto 106:ba1f97679dad 565 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
Kojto 106:ba1f97679dad 566 This parameter can be a value of @ref ETH_Fixed_Burst */
Kojto 106:ba1f97679dad 567
Kojto 106:ba1f97679dad 568 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
Kojto 106:ba1f97679dad 569 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
Kojto 106:ba1f97679dad 570
Kojto 106:ba1f97679dad 571 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
Kojto 106:ba1f97679dad 572 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
Kojto 106:ba1f97679dad 573
Kojto 106:ba1f97679dad 574 uint32_t EnhancedDescriptorFormat; /*!< Enables the enhanced descriptor format.
Kojto 106:ba1f97679dad 575 This parameter can be a value of @ref ETH_DMA_Enhanced_descriptor_format */
Kojto 106:ba1f97679dad 576
Kojto 106:ba1f97679dad 577 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
Kojto 106:ba1f97679dad 578 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
Kojto 106:ba1f97679dad 579
Kojto 106:ba1f97679dad 580 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
Kojto 106:ba1f97679dad 581 This parameter can be a value of @ref ETH_DMA_Arbitration */
Kojto 106:ba1f97679dad 582 } ETH_DMAInitTypeDef;
Kojto 106:ba1f97679dad 583
Kojto 106:ba1f97679dad 584
Kojto 106:ba1f97679dad 585 /**
Kojto 106:ba1f97679dad 586 * @brief ETH DMA Descriptors data structure definition
Kojto 106:ba1f97679dad 587 */
Kojto 106:ba1f97679dad 588
Kojto 106:ba1f97679dad 589 typedef struct
Kojto 106:ba1f97679dad 590 {
Kojto 106:ba1f97679dad 591 __IO uint32_t Status; /*!< Status */
Kojto 106:ba1f97679dad 592
Kojto 106:ba1f97679dad 593 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
Kojto 106:ba1f97679dad 594
Kojto 106:ba1f97679dad 595 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
Kojto 106:ba1f97679dad 596
Kojto 106:ba1f97679dad 597 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
Kojto 106:ba1f97679dad 598
Kojto 106:ba1f97679dad 599 /*!< Enhanced ETHERNET DMA PTP Descriptors */
Kojto 106:ba1f97679dad 600 uint32_t ExtendedStatus; /*!< Extended status for PTP receive descriptor */
Kojto 106:ba1f97679dad 601
Kojto 106:ba1f97679dad 602 uint32_t Reserved1; /*!< Reserved */
Kojto 106:ba1f97679dad 603
Kojto 106:ba1f97679dad 604 uint32_t TimeStampLow; /*!< Time Stamp Low value for transmit and receive */
Kojto 106:ba1f97679dad 605
Kojto 106:ba1f97679dad 606 uint32_t TimeStampHigh; /*!< Time Stamp High value for transmit and receive */
Kojto 106:ba1f97679dad 607
Kojto 106:ba1f97679dad 608 } ETH_DMADescTypeDef;
Kojto 106:ba1f97679dad 609
Kojto 106:ba1f97679dad 610
Kojto 106:ba1f97679dad 611 /**
Kojto 106:ba1f97679dad 612 * @brief Received Frame Informations structure definition
Kojto 106:ba1f97679dad 613 */
Kojto 106:ba1f97679dad 614 typedef struct
Kojto 106:ba1f97679dad 615 {
Kojto 106:ba1f97679dad 616 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
Kojto 106:ba1f97679dad 617
Kojto 106:ba1f97679dad 618 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
Kojto 106:ba1f97679dad 619
Kojto 106:ba1f97679dad 620 uint32_t SegCount; /*!< Segment count */
Kojto 106:ba1f97679dad 621
Kojto 106:ba1f97679dad 622 uint32_t length; /*!< Frame length */
Kojto 106:ba1f97679dad 623
Kojto 106:ba1f97679dad 624 uint32_t buffer; /*!< Frame buffer */
Kojto 106:ba1f97679dad 625
Kojto 106:ba1f97679dad 626 } ETH_DMARxFrameInfos;
Kojto 106:ba1f97679dad 627
Kojto 106:ba1f97679dad 628
Kojto 106:ba1f97679dad 629 /**
Kojto 106:ba1f97679dad 630 * @brief ETH Handle Structure definition
Kojto 106:ba1f97679dad 631 */
Kojto 106:ba1f97679dad 632
Kojto 106:ba1f97679dad 633 typedef struct
Kojto 106:ba1f97679dad 634 {
Kojto 106:ba1f97679dad 635 ETH_TypeDef *Instance; /*!< Register base address */
Kojto 106:ba1f97679dad 636
Kojto 106:ba1f97679dad 637 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
Kojto 106:ba1f97679dad 638
Kojto 106:ba1f97679dad 639 uint32_t LinkStatus; /*!< Ethernet link status */
Kojto 106:ba1f97679dad 640
Kojto 106:ba1f97679dad 641 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
Kojto 106:ba1f97679dad 642
Kojto 106:ba1f97679dad 643 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
Kojto 106:ba1f97679dad 644
Kojto 106:ba1f97679dad 645 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
Kojto 106:ba1f97679dad 646
Kojto 106:ba1f97679dad 647 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
Kojto 106:ba1f97679dad 648
Kojto 106:ba1f97679dad 649 HAL_LockTypeDef Lock; /*!< ETH Lock */
Kojto 106:ba1f97679dad 650
Kojto 106:ba1f97679dad 651 } ETH_HandleTypeDef;
Kojto 106:ba1f97679dad 652
Kojto 106:ba1f97679dad 653 /**
Kojto 106:ba1f97679dad 654 * @}
Kojto 106:ba1f97679dad 655 */
Kojto 106:ba1f97679dad 656
Kojto 106:ba1f97679dad 657 /* Exported constants --------------------------------------------------------*/
Kojto 106:ba1f97679dad 658 /** @defgroup ETH_Exported_Constants ETH Exported Constants
Kojto 106:ba1f97679dad 659 * @{
Kojto 106:ba1f97679dad 660 */
Kojto 106:ba1f97679dad 661
Kojto 106:ba1f97679dad 662 /** @defgroup ETH_Buffers_setting ETH Buffers setting
Kojto 106:ba1f97679dad 663 * @{
Kojto 106:ba1f97679dad 664 */
Kojto 106:ba1f97679dad 665 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
Kojto 106:ba1f97679dad 666 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
Kojto 106:ba1f97679dad 667 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
Kojto 106:ba1f97679dad 668 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
Kojto 106:ba1f97679dad 669 #define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
Kojto 106:ba1f97679dad 670 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
Kojto 106:ba1f97679dad 671 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
Kojto 106:ba1f97679dad 672 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
Kojto 106:ba1f97679dad 673
Kojto 106:ba1f97679dad 674 /* Ethernet driver receive buffers are organized in a chained linked-list, when
Kojto 106:ba1f97679dad 675 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
Kojto 106:ba1f97679dad 676 to the driver receive buffers memory.
Kojto 106:ba1f97679dad 677
Kojto 106:ba1f97679dad 678 Depending on the size of the received ethernet packet and the size of
Kojto 106:ba1f97679dad 679 each ethernet driver receive buffer, the received packet can take one or more
Kojto 106:ba1f97679dad 680 ethernet driver receive buffer.
Kojto 106:ba1f97679dad 681
Kojto 106:ba1f97679dad 682 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
Kojto 106:ba1f97679dad 683 and the total count of the driver receive buffers ETH_RXBUFNB.
Kojto 106:ba1f97679dad 684
Kojto 106:ba1f97679dad 685 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
Kojto 106:ba1f97679dad 686 example, they can be reconfigured in the application layer to fit the application
Kojto 106:ba1f97679dad 687 needs */
Kojto 106:ba1f97679dad 688
Kojto 106:ba1f97679dad 689 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
Kojto 106:ba1f97679dad 690 packet */
Kojto 106:ba1f97679dad 691 #ifndef ETH_RX_BUF_SIZE
Kojto 106:ba1f97679dad 692 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto 106:ba1f97679dad 693 #endif
Kojto 106:ba1f97679dad 694
Kojto 106:ba1f97679dad 695 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
Kojto 106:ba1f97679dad 696 #ifndef ETH_RXBUFNB
Kojto 106:ba1f97679dad 697 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
Kojto 106:ba1f97679dad 698 #endif
Kojto 106:ba1f97679dad 699
Kojto 106:ba1f97679dad 700
Kojto 106:ba1f97679dad 701 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
Kojto 106:ba1f97679dad 702 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
Kojto 106:ba1f97679dad 703 driver transmit buffers memory to the TxFIFO.
Kojto 106:ba1f97679dad 704
Kojto 106:ba1f97679dad 705 Depending on the size of the Ethernet packet to be transmitted and the size of
Kojto 106:ba1f97679dad 706 each ethernet driver transmit buffer, the packet to be transmitted can take
Kojto 106:ba1f97679dad 707 one or more ethernet driver transmit buffer.
Kojto 106:ba1f97679dad 708
Kojto 106:ba1f97679dad 709 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
Kojto 106:ba1f97679dad 710 and the total count of the driver transmit buffers ETH_TXBUFNB.
Kojto 106:ba1f97679dad 711
Kojto 106:ba1f97679dad 712 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
Kojto 106:ba1f97679dad 713 example, they can be reconfigured in the application layer to fit the application
Kojto 106:ba1f97679dad 714 needs */
Kojto 106:ba1f97679dad 715
Kojto 106:ba1f97679dad 716 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
Kojto 106:ba1f97679dad 717 packet */
Kojto 106:ba1f97679dad 718 #ifndef ETH_TX_BUF_SIZE
Kojto 106:ba1f97679dad 719 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
Kojto 106:ba1f97679dad 720 #endif
Kojto 106:ba1f97679dad 721
Kojto 106:ba1f97679dad 722 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
Kojto 106:ba1f97679dad 723 #ifndef ETH_TXBUFNB
Kojto 106:ba1f97679dad 724 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
Kojto 106:ba1f97679dad 725 #endif
Kojto 106:ba1f97679dad 726
Kojto 106:ba1f97679dad 727 /**
Kojto 106:ba1f97679dad 728 * @}
Kojto 106:ba1f97679dad 729 */
Kojto 106:ba1f97679dad 730
Kojto 106:ba1f97679dad 731 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
Kojto 106:ba1f97679dad 732 * @{
Kojto 106:ba1f97679dad 733 */
Kojto 106:ba1f97679dad 734
Kojto 106:ba1f97679dad 735 /*
Kojto 106:ba1f97679dad 736 DMA Tx Descriptor
Kojto 106:ba1f97679dad 737 -----------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 738 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
Kojto 106:ba1f97679dad 739 -----------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 740 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
Kojto 106:ba1f97679dad 741 -----------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 742 TDES2 | Buffer1 Address [31:0] |
Kojto 106:ba1f97679dad 743 -----------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 744 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
Kojto 106:ba1f97679dad 745 -----------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 746 */
Kojto 106:ba1f97679dad 747
Kojto 106:ba1f97679dad 748 /**
Kojto 106:ba1f97679dad 749 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
Kojto 106:ba1f97679dad 750 */
Kojto 106:ba1f97679dad 751 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
Kojto 106:ba1f97679dad 752 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
Kojto 106:ba1f97679dad 753 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
Kojto 106:ba1f97679dad 754 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
Kojto 106:ba1f97679dad 755 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
Kojto 106:ba1f97679dad 756 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
Kojto 106:ba1f97679dad 757 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
Kojto 106:ba1f97679dad 758 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
Kojto 106:ba1f97679dad 759 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
Kojto 106:ba1f97679dad 760 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
Kojto 106:ba1f97679dad 761 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
Kojto 106:ba1f97679dad 762 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
Kojto 106:ba1f97679dad 763 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
Kojto 106:ba1f97679dad 764 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
Kojto 106:ba1f97679dad 765 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
Kojto 106:ba1f97679dad 766 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
Kojto 106:ba1f97679dad 767 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
Kojto 106:ba1f97679dad 768 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
Kojto 106:ba1f97679dad 769 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
Kojto 106:ba1f97679dad 770 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
Kojto 106:ba1f97679dad 771 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
Kojto 106:ba1f97679dad 772 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
Kojto 106:ba1f97679dad 773 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
Kojto 106:ba1f97679dad 774 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
Kojto 106:ba1f97679dad 775 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
Kojto 106:ba1f97679dad 776 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
Kojto 106:ba1f97679dad 777 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
Kojto 106:ba1f97679dad 778 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
Kojto 106:ba1f97679dad 779 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
Kojto 106:ba1f97679dad 780
Kojto 106:ba1f97679dad 781 /**
Kojto 106:ba1f97679dad 782 * @brief Bit definition of TDES1 register
Kojto 106:ba1f97679dad 783 */
Kojto 106:ba1f97679dad 784 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
Kojto 106:ba1f97679dad 785 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
Kojto 106:ba1f97679dad 786
Kojto 106:ba1f97679dad 787 /**
Kojto 106:ba1f97679dad 788 * @brief Bit definition of TDES2 register
Kojto 106:ba1f97679dad 789 */
Kojto 106:ba1f97679dad 790 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
Kojto 106:ba1f97679dad 791
Kojto 106:ba1f97679dad 792 /**
Kojto 106:ba1f97679dad 793 * @brief Bit definition of TDES3 register
Kojto 106:ba1f97679dad 794 */
Kojto 106:ba1f97679dad 795 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
Kojto 106:ba1f97679dad 796
Kojto 106:ba1f97679dad 797 /*---------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 798 TDES6 | Transmit Time Stamp Low [31:0] |
Kojto 106:ba1f97679dad 799 -----------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 800 TDES7 | Transmit Time Stamp High [31:0] |
Kojto 106:ba1f97679dad 801 ----------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 802
Kojto 106:ba1f97679dad 803 /* Bit definition of TDES6 register */
Kojto 106:ba1f97679dad 804 #define ETH_DMAPTPTXDESC_TTSL ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp Low */
Kojto 106:ba1f97679dad 805
Kojto 106:ba1f97679dad 806 /* Bit definition of TDES7 register */
Kojto 106:ba1f97679dad 807 #define ETH_DMAPTPTXDESC_TTSH ((uint32_t)0xFFFFFFFF) /* Transmit Time Stamp High */
Kojto 106:ba1f97679dad 808
Kojto 106:ba1f97679dad 809 /**
Kojto 106:ba1f97679dad 810 * @}
Kojto 106:ba1f97679dad 811 */
Kojto 106:ba1f97679dad 812 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
Kojto 106:ba1f97679dad 813 * @{
Kojto 106:ba1f97679dad 814 */
Kojto 106:ba1f97679dad 815
Kojto 106:ba1f97679dad 816 /*
Kojto 106:ba1f97679dad 817 DMA Rx Descriptor
Kojto 106:ba1f97679dad 818 --------------------------------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 819 RDES0 | OWN(31) | Status [30:0] |
Kojto 106:ba1f97679dad 820 ---------------------------------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 821 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
Kojto 106:ba1f97679dad 822 ---------------------------------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 823 RDES2 | Buffer1 Address [31:0] |
Kojto 106:ba1f97679dad 824 ---------------------------------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 825 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
Kojto 106:ba1f97679dad 826 ---------------------------------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 827 */
Kojto 106:ba1f97679dad 828
Kojto 106:ba1f97679dad 829 /**
Kojto 106:ba1f97679dad 830 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
Kojto 106:ba1f97679dad 831 */
Kojto 106:ba1f97679dad 832 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
Kojto 106:ba1f97679dad 833 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
Kojto 106:ba1f97679dad 834 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
Kojto 106:ba1f97679dad 835 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
Kojto 106:ba1f97679dad 836 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
Kojto 106:ba1f97679dad 837 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
Kojto 106:ba1f97679dad 838 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
Kojto 106:ba1f97679dad 839 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
Kojto 106:ba1f97679dad 840 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
Kojto 106:ba1f97679dad 841 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
Kojto 106:ba1f97679dad 842 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
Kojto 106:ba1f97679dad 843 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
Kojto 106:ba1f97679dad 844 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
Kojto 106:ba1f97679dad 845 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
Kojto 106:ba1f97679dad 846 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
Kojto 106:ba1f97679dad 847 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
Kojto 106:ba1f97679dad 848 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
Kojto 106:ba1f97679dad 849 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
Kojto 106:ba1f97679dad 850 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
Kojto 106:ba1f97679dad 851
Kojto 106:ba1f97679dad 852 /**
Kojto 106:ba1f97679dad 853 * @brief Bit definition of RDES1 register
Kojto 106:ba1f97679dad 854 */
Kojto 106:ba1f97679dad 855 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
Kojto 106:ba1f97679dad 856 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
Kojto 106:ba1f97679dad 857 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
Kojto 106:ba1f97679dad 858 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
Kojto 106:ba1f97679dad 859 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
Kojto 106:ba1f97679dad 860
Kojto 106:ba1f97679dad 861 /**
Kojto 106:ba1f97679dad 862 * @brief Bit definition of RDES2 register
Kojto 106:ba1f97679dad 863 */
Kojto 106:ba1f97679dad 864 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
Kojto 106:ba1f97679dad 865
Kojto 106:ba1f97679dad 866 /**
Kojto 106:ba1f97679dad 867 * @brief Bit definition of RDES3 register
Kojto 106:ba1f97679dad 868 */
Kojto 106:ba1f97679dad 869 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
Kojto 106:ba1f97679dad 870
Kojto 106:ba1f97679dad 871 /*---------------------------------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 872 RDES4 | Reserved[31:15] | Extended Status [14:0] |
Kojto 106:ba1f97679dad 873 ---------------------------------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 874 RDES5 | Reserved[31:0] |
Kojto 106:ba1f97679dad 875 ---------------------------------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 876 RDES6 | Receive Time Stamp Low [31:0] |
Kojto 106:ba1f97679dad 877 ---------------------------------------------------------------------------------------------------------------------
Kojto 106:ba1f97679dad 878 RDES7 | Receive Time Stamp High [31:0] |
Kojto 106:ba1f97679dad 879 --------------------------------------------------------------------------------------------------------------------*/
Kojto 106:ba1f97679dad 880
Kojto 106:ba1f97679dad 881 /* Bit definition of RDES4 register */
Kojto 106:ba1f97679dad 882 #define ETH_DMAPTPRXDESC_PTPV ((uint32_t)0x00002000) /* PTP Version */
Kojto 106:ba1f97679dad 883 #define ETH_DMAPTPRXDESC_PTPFT ((uint32_t)0x00001000) /* PTP Frame Type */
Kojto 106:ba1f97679dad 884 #define ETH_DMAPTPRXDESC_PTPMT ((uint32_t)0x00000F00) /* PTP Message Type */
Kojto 106:ba1f97679dad 885 #define ETH_DMAPTPRXDESC_PTPMT_SYNC ((uint32_t)0x00000100) /* SYNC message (all clock types) */
Kojto 106:ba1f97679dad 886 #define ETH_DMAPTPRXDESC_PTPMT_FOLLOWUP ((uint32_t)0x00000200) /* FollowUp message (all clock types) */
Kojto 106:ba1f97679dad 887 #define ETH_DMAPTPRXDESC_PTPMT_DELAYREQ ((uint32_t)0x00000300) /* DelayReq message (all clock types) */
Kojto 106:ba1f97679dad 888 #define ETH_DMAPTPRXDESC_PTPMT_DELAYRESP ((uint32_t)0x00000400) /* DelayResp message (all clock types) */
Kojto 106:ba1f97679dad 889 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYREQ_ANNOUNCE ((uint32_t)0x00000500) /* PdelayReq message (peer-to-peer transparent clock) or Announce message (Ordinary or Boundary clock) */
Kojto 106:ba1f97679dad 890 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESP_MANAG ((uint32_t)0x00000600) /* PdelayResp message (peer-to-peer transparent clock) or Management message (Ordinary or Boundary clock) */
Kojto 106:ba1f97679dad 891 #define ETH_DMAPTPRXDESC_PTPMT_PDELAYRESPFOLLOWUP_SIGNAL ((uint32_t)0x00000700) /* PdelayRespFollowUp message (peer-to-peer transparent clock) or Signaling message (Ordinary or Boundary clock) */
Kojto 106:ba1f97679dad 892 #define ETH_DMAPTPRXDESC_IPV6PR ((uint32_t)0x00000080) /* IPv6 Packet Received */
Kojto 106:ba1f97679dad 893 #define ETH_DMAPTPRXDESC_IPV4PR ((uint32_t)0x00000040) /* IPv4 Packet Received */
Kojto 106:ba1f97679dad 894 #define ETH_DMAPTPRXDESC_IPCB ((uint32_t)0x00000020) /* IP Checksum Bypassed */
Kojto 106:ba1f97679dad 895 #define ETH_DMAPTPRXDESC_IPPE ((uint32_t)0x00000010) /* IP Payload Error */
Kojto 106:ba1f97679dad 896 #define ETH_DMAPTPRXDESC_IPHE ((uint32_t)0x00000008) /* IP Header Error */
Kojto 106:ba1f97679dad 897 #define ETH_DMAPTPRXDESC_IPPT ((uint32_t)0x00000007) /* IP Payload Type */
Kojto 106:ba1f97679dad 898 #define ETH_DMAPTPRXDESC_IPPT_UDP ((uint32_t)0x00000001) /* UDP payload encapsulated in the IP datagram */
Kojto 106:ba1f97679dad 899 #define ETH_DMAPTPRXDESC_IPPT_TCP ((uint32_t)0x00000002) /* TCP payload encapsulated in the IP datagram */
Kojto 106:ba1f97679dad 900 #define ETH_DMAPTPRXDESC_IPPT_ICMP ((uint32_t)0x00000003) /* ICMP payload encapsulated in the IP datagram */
Kojto 106:ba1f97679dad 901
Kojto 106:ba1f97679dad 902 /* Bit definition of RDES6 register */
Kojto 106:ba1f97679dad 903 #define ETH_DMAPTPRXDESC_RTSL ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp Low */
Kojto 106:ba1f97679dad 904
Kojto 106:ba1f97679dad 905 /* Bit definition of RDES7 register */
Kojto 106:ba1f97679dad 906 #define ETH_DMAPTPRXDESC_RTSH ((uint32_t)0xFFFFFFFF) /* Receive Time Stamp High */
Kojto 106:ba1f97679dad 907 /**
Kojto 106:ba1f97679dad 908 * @}
Kojto 106:ba1f97679dad 909 */
Kojto 106:ba1f97679dad 910 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
Kojto 106:ba1f97679dad 911 * @{
Kojto 106:ba1f97679dad 912 */
Kojto 106:ba1f97679dad 913 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
Kojto 106:ba1f97679dad 914 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 915
Kojto 106:ba1f97679dad 916 /**
Kojto 106:ba1f97679dad 917 * @}
Kojto 106:ba1f97679dad 918 */
Kojto 106:ba1f97679dad 919 /** @defgroup ETH_Speed ETH Speed
Kojto 106:ba1f97679dad 920 * @{
Kojto 106:ba1f97679dad 921 */
Kojto 106:ba1f97679dad 922 #define ETH_SPEED_10M ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 923 #define ETH_SPEED_100M ((uint32_t)0x00004000)
Kojto 106:ba1f97679dad 924
Kojto 106:ba1f97679dad 925 /**
Kojto 106:ba1f97679dad 926 * @}
Kojto 106:ba1f97679dad 927 */
Kojto 106:ba1f97679dad 928 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
Kojto 106:ba1f97679dad 929 * @{
Kojto 106:ba1f97679dad 930 */
Kojto 106:ba1f97679dad 931 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
Kojto 106:ba1f97679dad 932 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 933 /**
Kojto 106:ba1f97679dad 934 * @}
Kojto 106:ba1f97679dad 935 */
Kojto 106:ba1f97679dad 936 /** @defgroup ETH_Rx_Mode ETH Rx Mode
Kojto 106:ba1f97679dad 937 * @{
Kojto 106:ba1f97679dad 938 */
Kojto 106:ba1f97679dad 939 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 940 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
Kojto 106:ba1f97679dad 941 /**
Kojto 106:ba1f97679dad 942 * @}
Kojto 106:ba1f97679dad 943 */
Kojto 106:ba1f97679dad 944
Kojto 106:ba1f97679dad 945 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
Kojto 106:ba1f97679dad 946 * @{
Kojto 106:ba1f97679dad 947 */
Kojto 106:ba1f97679dad 948 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 949 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
Kojto 106:ba1f97679dad 950 /**
Kojto 106:ba1f97679dad 951 * @}
Kojto 106:ba1f97679dad 952 */
Kojto 106:ba1f97679dad 953
Kojto 106:ba1f97679dad 954 /** @defgroup ETH_Media_Interface ETH Media Interface
Kojto 106:ba1f97679dad 955 * @{
Kojto 106:ba1f97679dad 956 */
Kojto 106:ba1f97679dad 957 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 958 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)SYSCFG_PMC_MII_RMII_SEL)
Kojto 106:ba1f97679dad 959 /**
Kojto 106:ba1f97679dad 960 * @}
Kojto 106:ba1f97679dad 961 */
Kojto 106:ba1f97679dad 962
Kojto 106:ba1f97679dad 963 /** @defgroup ETH_Watchdog ETH Watchdog
Kojto 106:ba1f97679dad 964 * @{
Kojto 106:ba1f97679dad 965 */
Kojto 106:ba1f97679dad 966 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 967 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
Kojto 106:ba1f97679dad 968 /**
Kojto 106:ba1f97679dad 969 * @}
Kojto 106:ba1f97679dad 970 */
Kojto 106:ba1f97679dad 971
Kojto 106:ba1f97679dad 972 /** @defgroup ETH_Jabber ETH Jabber
Kojto 106:ba1f97679dad 973 * @{
Kojto 106:ba1f97679dad 974 */
Kojto 106:ba1f97679dad 975 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 976 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
Kojto 106:ba1f97679dad 977 /**
Kojto 106:ba1f97679dad 978 * @}
Kojto 106:ba1f97679dad 979 */
Kojto 106:ba1f97679dad 980
Kojto 106:ba1f97679dad 981 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
Kojto 106:ba1f97679dad 982 * @{
Kojto 106:ba1f97679dad 983 */
Kojto 106:ba1f97679dad 984 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
Kojto 106:ba1f97679dad 985 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
Kojto 106:ba1f97679dad 986 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
Kojto 106:ba1f97679dad 987 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
Kojto 106:ba1f97679dad 988 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
Kojto 106:ba1f97679dad 989 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
Kojto 106:ba1f97679dad 990 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
Kojto 106:ba1f97679dad 991 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
Kojto 106:ba1f97679dad 992 /**
Kojto 106:ba1f97679dad 993 * @}
Kojto 106:ba1f97679dad 994 */
Kojto 106:ba1f97679dad 995
Kojto 106:ba1f97679dad 996 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
Kojto 106:ba1f97679dad 997 * @{
Kojto 106:ba1f97679dad 998 */
Kojto 106:ba1f97679dad 999 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1000 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
Kojto 106:ba1f97679dad 1001 /**
Kojto 106:ba1f97679dad 1002 * @}
Kojto 106:ba1f97679dad 1003 */
Kojto 106:ba1f97679dad 1004
Kojto 106:ba1f97679dad 1005 /** @defgroup ETH_Receive_Own ETH Receive Own
Kojto 106:ba1f97679dad 1006 * @{
Kojto 106:ba1f97679dad 1007 */
Kojto 106:ba1f97679dad 1008 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1009 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
Kojto 106:ba1f97679dad 1010 /**
Kojto 106:ba1f97679dad 1011 * @}
Kojto 106:ba1f97679dad 1012 */
Kojto 106:ba1f97679dad 1013
Kojto 106:ba1f97679dad 1014 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
Kojto 106:ba1f97679dad 1015 * @{
Kojto 106:ba1f97679dad 1016 */
Kojto 106:ba1f97679dad 1017 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
Kojto 106:ba1f97679dad 1018 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1019 /**
Kojto 106:ba1f97679dad 1020 * @}
Kojto 106:ba1f97679dad 1021 */
Kojto 106:ba1f97679dad 1022
Kojto 106:ba1f97679dad 1023 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
Kojto 106:ba1f97679dad 1024 * @{
Kojto 106:ba1f97679dad 1025 */
Kojto 106:ba1f97679dad 1026 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
Kojto 106:ba1f97679dad 1027 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1028 /**
Kojto 106:ba1f97679dad 1029 * @}
Kojto 106:ba1f97679dad 1030 */
Kojto 106:ba1f97679dad 1031
Kojto 106:ba1f97679dad 1032 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
Kojto 106:ba1f97679dad 1033 * @{
Kojto 106:ba1f97679dad 1034 */
Kojto 106:ba1f97679dad 1035 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1036 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
Kojto 106:ba1f97679dad 1037 /**
Kojto 106:ba1f97679dad 1038 * @}
Kojto 106:ba1f97679dad 1039 */
Kojto 106:ba1f97679dad 1040
Kojto 106:ba1f97679dad 1041 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
Kojto 106:ba1f97679dad 1042 * @{
Kojto 106:ba1f97679dad 1043 */
Kojto 106:ba1f97679dad 1044 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
Kojto 106:ba1f97679dad 1045 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1046 /**
Kojto 106:ba1f97679dad 1047 * @}
Kojto 106:ba1f97679dad 1048 */
Kojto 106:ba1f97679dad 1049
Kojto 106:ba1f97679dad 1050 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
Kojto 106:ba1f97679dad 1051 * @{
Kojto 106:ba1f97679dad 1052 */
Kojto 106:ba1f97679dad 1053 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1054 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
Kojto 106:ba1f97679dad 1055 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
Kojto 106:ba1f97679dad 1056 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
Kojto 106:ba1f97679dad 1057 /**
Kojto 106:ba1f97679dad 1058 * @}
Kojto 106:ba1f97679dad 1059 */
Kojto 106:ba1f97679dad 1060
Kojto 106:ba1f97679dad 1061 /** @defgroup ETH_Deferral_Check ETH Deferral Check
Kojto 106:ba1f97679dad 1062 * @{
Kojto 106:ba1f97679dad 1063 */
Kojto 106:ba1f97679dad 1064 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
Kojto 106:ba1f97679dad 1065 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1066 /**
Kojto 106:ba1f97679dad 1067 * @}
Kojto 106:ba1f97679dad 1068 */
Kojto 106:ba1f97679dad 1069
Kojto 106:ba1f97679dad 1070 /** @defgroup ETH_Receive_All ETH Receive All
Kojto 106:ba1f97679dad 1071 * @{
Kojto 106:ba1f97679dad 1072 */
Kojto 106:ba1f97679dad 1073 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
Kojto 106:ba1f97679dad 1074 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1075 /**
Kojto 106:ba1f97679dad 1076 * @}
Kojto 106:ba1f97679dad 1077 */
Kojto 106:ba1f97679dad 1078
Kojto 106:ba1f97679dad 1079 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
Kojto 106:ba1f97679dad 1080 * @{
Kojto 106:ba1f97679dad 1081 */
Kojto 106:ba1f97679dad 1082 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
Kojto 106:ba1f97679dad 1083 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
Kojto 106:ba1f97679dad 1084 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1085 /**
Kojto 106:ba1f97679dad 1086 * @}
Kojto 106:ba1f97679dad 1087 */
Kojto 106:ba1f97679dad 1088
Kojto 106:ba1f97679dad 1089 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
Kojto 106:ba1f97679dad 1090 * @{
Kojto 106:ba1f97679dad 1091 */
Kojto 106:ba1f97679dad 1092 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
Kojto 106:ba1f97679dad 1093 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
Kojto 106:ba1f97679dad 1094 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
Kojto 106:ba1f97679dad 1095 /**
Kojto 106:ba1f97679dad 1096 * @}
Kojto 106:ba1f97679dad 1097 */
Kojto 106:ba1f97679dad 1098
Kojto 106:ba1f97679dad 1099 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
Kojto 106:ba1f97679dad 1100 * @{
Kojto 106:ba1f97679dad 1101 */
Kojto 106:ba1f97679dad 1102 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1103 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
Kojto 106:ba1f97679dad 1104 /**
Kojto 106:ba1f97679dad 1105 * @}
Kojto 106:ba1f97679dad 1106 */
Kojto 106:ba1f97679dad 1107
Kojto 106:ba1f97679dad 1108 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
Kojto 106:ba1f97679dad 1109 * @{
Kojto 106:ba1f97679dad 1110 */
Kojto 106:ba1f97679dad 1111 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1112 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
Kojto 106:ba1f97679dad 1113 /**
Kojto 106:ba1f97679dad 1114 * @}
Kojto 106:ba1f97679dad 1115 */
Kojto 106:ba1f97679dad 1116
Kojto 106:ba1f97679dad 1117 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
Kojto 106:ba1f97679dad 1118 * @{
Kojto 106:ba1f97679dad 1119 */
Kojto 106:ba1f97679dad 1120 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
Kojto 106:ba1f97679dad 1121 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1122 /**
Kojto 106:ba1f97679dad 1123 * @}
Kojto 106:ba1f97679dad 1124 */
Kojto 106:ba1f97679dad 1125
Kojto 106:ba1f97679dad 1126 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
Kojto 106:ba1f97679dad 1127 * @{
Kojto 106:ba1f97679dad 1128 */
Kojto 106:ba1f97679dad 1129 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
Kojto 106:ba1f97679dad 1130 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
Kojto 106:ba1f97679dad 1131 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1132 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
Kojto 106:ba1f97679dad 1133 /**
Kojto 106:ba1f97679dad 1134 * @}
Kojto 106:ba1f97679dad 1135 */
Kojto 106:ba1f97679dad 1136
Kojto 106:ba1f97679dad 1137 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
Kojto 106:ba1f97679dad 1138 * @{
Kojto 106:ba1f97679dad 1139 */
Kojto 106:ba1f97679dad 1140 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
Kojto 106:ba1f97679dad 1141 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
Kojto 106:ba1f97679dad 1142 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1143 /**
Kojto 106:ba1f97679dad 1144 * @}
Kojto 106:ba1f97679dad 1145 */
Kojto 106:ba1f97679dad 1146
Kojto 106:ba1f97679dad 1147 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
Kojto 106:ba1f97679dad 1148 * @{
Kojto 106:ba1f97679dad 1149 */
Kojto 106:ba1f97679dad 1150 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1151 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
Kojto 106:ba1f97679dad 1152 /**
Kojto 106:ba1f97679dad 1153 * @}
Kojto 106:ba1f97679dad 1154 */
Kojto 106:ba1f97679dad 1155
Kojto 106:ba1f97679dad 1156 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
Kojto 106:ba1f97679dad 1157 * @{
Kojto 106:ba1f97679dad 1158 */
Kojto 106:ba1f97679dad 1159 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
Kojto 106:ba1f97679dad 1160 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
Kojto 106:ba1f97679dad 1161 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
Kojto 106:ba1f97679dad 1162 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
Kojto 106:ba1f97679dad 1163 /**
Kojto 106:ba1f97679dad 1164 * @}
Kojto 106:ba1f97679dad 1165 */
Kojto 106:ba1f97679dad 1166
Kojto 106:ba1f97679dad 1167 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
Kojto 106:ba1f97679dad 1168 * @{
Kojto 106:ba1f97679dad 1169 */
Kojto 106:ba1f97679dad 1170 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
Kojto 106:ba1f97679dad 1171 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1172 /**
Kojto 106:ba1f97679dad 1173 * @}
Kojto 106:ba1f97679dad 1174 */
Kojto 106:ba1f97679dad 1175
Kojto 106:ba1f97679dad 1176 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
Kojto 106:ba1f97679dad 1177 * @{
Kojto 106:ba1f97679dad 1178 */
Kojto 106:ba1f97679dad 1179 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
Kojto 106:ba1f97679dad 1180 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1181 /**
Kojto 106:ba1f97679dad 1182 * @}
Kojto 106:ba1f97679dad 1183 */
Kojto 106:ba1f97679dad 1184
Kojto 106:ba1f97679dad 1185 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
Kojto 106:ba1f97679dad 1186 * @{
Kojto 106:ba1f97679dad 1187 */
Kojto 106:ba1f97679dad 1188 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
Kojto 106:ba1f97679dad 1189 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1190 /**
Kojto 106:ba1f97679dad 1191 * @}
Kojto 106:ba1f97679dad 1192 */
Kojto 106:ba1f97679dad 1193
Kojto 106:ba1f97679dad 1194 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
Kojto 106:ba1f97679dad 1195 * @{
Kojto 106:ba1f97679dad 1196 */
Kojto 106:ba1f97679dad 1197 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
Kojto 106:ba1f97679dad 1198 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1199 /**
Kojto 106:ba1f97679dad 1200 * @}
Kojto 106:ba1f97679dad 1201 */
Kojto 106:ba1f97679dad 1202
Kojto 106:ba1f97679dad 1203 /** @defgroup ETH_MAC_addresses ETH MAC addresses
Kojto 106:ba1f97679dad 1204 * @{
Kojto 106:ba1f97679dad 1205 */
Kojto 106:ba1f97679dad 1206 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1207 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
Kojto 106:ba1f97679dad 1208 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
Kojto 106:ba1f97679dad 1209 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
Kojto 106:ba1f97679dad 1210 /**
Kojto 106:ba1f97679dad 1211 * @}
Kojto 106:ba1f97679dad 1212 */
Kojto 106:ba1f97679dad 1213
Kojto 106:ba1f97679dad 1214 /** @defgroup ETH_MAC_addresses_filter_SA_DA ETH MAC addresses filter SA DA
Kojto 106:ba1f97679dad 1215 * @{
Kojto 106:ba1f97679dad 1216 */
Kojto 106:ba1f97679dad 1217 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1218 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
Kojto 106:ba1f97679dad 1219 /**
Kojto 106:ba1f97679dad 1220 * @}
Kojto 106:ba1f97679dad 1221 */
Kojto 106:ba1f97679dad 1222
Kojto 106:ba1f97679dad 1223 /** @defgroup ETH_MAC_addresses_filter_Mask_bytes ETH MAC addresses filter Mask bytes
Kojto 106:ba1f97679dad 1224 * @{
Kojto 106:ba1f97679dad 1225 */
Kojto 106:ba1f97679dad 1226 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
Kojto 106:ba1f97679dad 1227 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
Kojto 106:ba1f97679dad 1228 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
Kojto 106:ba1f97679dad 1229 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
Kojto 106:ba1f97679dad 1230 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
Kojto 106:ba1f97679dad 1231 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
Kojto 106:ba1f97679dad 1232 /**
Kojto 106:ba1f97679dad 1233 * @}
Kojto 106:ba1f97679dad 1234 */
Kojto 106:ba1f97679dad 1235
Kojto 106:ba1f97679dad 1236 /** @defgroup ETH_MAC_Debug_flags ETH MAC Debug flags
Kojto 106:ba1f97679dad 1237 * @{
Kojto 106:ba1f97679dad 1238 */
Kojto 106:ba1f97679dad 1239 #define ETH_MAC_TXFIFO_FULL ((uint32_t)0x02000000) /* Tx FIFO full */
Kojto 106:ba1f97679dad 1240 #define ETH_MAC_TXFIFONOT_EMPTY ((uint32_t)0x01000000) /* Tx FIFO not empty */
Kojto 106:ba1f97679dad 1241 #define ETH_MAC_TXFIFO_WRITE_ACTIVE ((uint32_t)0x00400000) /* Tx FIFO write active */
Kojto 106:ba1f97679dad 1242 #define ETH_MAC_TXFIFO_IDLE ((uint32_t)0x00000000) /* Tx FIFO read status: Idle */
Kojto 106:ba1f97679dad 1243 #define ETH_MAC_TXFIFO_READ ((uint32_t)0x00100000) /* Tx FIFO read status: Read (transferring data to the MAC transmitter) */
Kojto 106:ba1f97679dad 1244 #define ETH_MAC_TXFIFO_WAITING ((uint32_t)0x00200000) /* Tx FIFO read status: Waiting for TxStatus from MAC transmitter */
Kojto 106:ba1f97679dad 1245 #define ETH_MAC_TXFIFO_WRITING ((uint32_t)0x00300000) /* Tx FIFO read status: Writing the received TxStatus or flushing the TxFIFO */
Kojto 106:ba1f97679dad 1246 #define ETH_MAC_TRANSMISSION_PAUSE ((uint32_t)0x00080000) /* MAC transmitter in pause */
Kojto 106:ba1f97679dad 1247 #define ETH_MAC_TRANSMITFRAMECONTROLLER_IDLE ((uint32_t)0x00000000) /* MAC transmit frame controller: Idle */
Kojto 106:ba1f97679dad 1248 #define ETH_MAC_TRANSMITFRAMECONTROLLER_WAITING ((uint32_t)0x00020000) /* MAC transmit frame controller: Waiting for Status of previous frame or IFG/backoff period to be over */
Kojto 106:ba1f97679dad 1249 #define ETH_MAC_TRANSMITFRAMECONTROLLER_GENRATING_PCF ((uint32_t)0x00040000) /* MAC transmit frame controller: Generating and transmitting a Pause control frame (in full duplex mode) */
Kojto 106:ba1f97679dad 1250 #define ETH_MAC_TRANSMITFRAMECONTROLLER_TRANSFERRING ((uint32_t)0x00060000) /* MAC transmit frame controller: Transferring input frame for transmission */
Kojto 106:ba1f97679dad 1251 #define ETH_MAC_MII_TRANSMIT_ACTIVE ((uint32_t)0x00010000) /* MAC MII transmit engine active */
Kojto 106:ba1f97679dad 1252 #define ETH_MAC_RXFIFO_EMPTY ((uint32_t)0x00000000) /* Rx FIFO fill level: empty */
Kojto 106:ba1f97679dad 1253 #define ETH_MAC_RXFIFO_BELOW_THRESHOLD ((uint32_t)0x00000100) /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
Kojto 106:ba1f97679dad 1254 #define ETH_MAC_RXFIFO_ABOVE_THRESHOLD ((uint32_t)0x00000200) /* Rx FIFO fill level: fill-level above flow-control activate threshold */
Kojto 106:ba1f97679dad 1255 #define ETH_MAC_RXFIFO_FULL ((uint32_t)0x00000300) /* Rx FIFO fill level: full */
Kojto 106:ba1f97679dad 1256 #define ETH_MAC_READCONTROLLER_IDLE ((uint32_t)0x00000000) /* Rx FIFO read controller IDLE state */
Kojto 106:ba1f97679dad 1257 #define ETH_MAC_READCONTROLLER_READING_DATA ((uint32_t)0x00000020) /* Rx FIFO read controller Reading frame data */
Kojto 106:ba1f97679dad 1258 #define ETH_MAC_READCONTROLLER_READING_STATUS ((uint32_t)0x00000040) /* Rx FIFO read controller Reading frame status (or time-stamp) */
Kojto 106:ba1f97679dad 1259 #define ETH_MAC_READCONTROLLER_FLUSHING ((uint32_t)0x00000060) /* Rx FIFO read controller Flushing the frame data and status */
Kojto 106:ba1f97679dad 1260 #define ETH_MAC_RXFIFO_WRITE_ACTIVE ((uint32_t)0x00000010) /* Rx FIFO write controller active */
Kojto 106:ba1f97679dad 1261 #define ETH_MAC_SMALL_FIFO_NOTACTIVE ((uint32_t)0x00000000) /* MAC small FIFO read / write controllers not active */
Kojto 106:ba1f97679dad 1262 #define ETH_MAC_SMALL_FIFO_READ_ACTIVE ((uint32_t)0x00000002) /* MAC small FIFO read controller active */
Kojto 106:ba1f97679dad 1263 #define ETH_MAC_SMALL_FIFO_WRITE_ACTIVE ((uint32_t)0x00000004) /* MAC small FIFO write controller active */
Kojto 106:ba1f97679dad 1264 #define ETH_MAC_SMALL_FIFO_RW_ACTIVE ((uint32_t)0x00000006) /* MAC small FIFO read / write controllers active */
Kojto 106:ba1f97679dad 1265 #define ETH_MAC_MII_RECEIVE_PROTOCOL_ACTIVE ((uint32_t)0x00000001) /* MAC MII receive protocol engine active */
Kojto 106:ba1f97679dad 1266 /**
Kojto 106:ba1f97679dad 1267 * @}
Kojto 106:ba1f97679dad 1268 */
Kojto 106:ba1f97679dad 1269
Kojto 106:ba1f97679dad 1270 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
Kojto 106:ba1f97679dad 1271 * @{
Kojto 106:ba1f97679dad 1272 */
Kojto 106:ba1f97679dad 1273 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1274 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
Kojto 106:ba1f97679dad 1275 /**
Kojto 106:ba1f97679dad 1276 * @}
Kojto 106:ba1f97679dad 1277 */
Kojto 106:ba1f97679dad 1278
Kojto 106:ba1f97679dad 1279 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
Kojto 106:ba1f97679dad 1280 * @{
Kojto 106:ba1f97679dad 1281 */
Kojto 106:ba1f97679dad 1282 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
Kojto 106:ba1f97679dad 1283 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1284 /**
Kojto 106:ba1f97679dad 1285 * @}
Kojto 106:ba1f97679dad 1286 */
Kojto 106:ba1f97679dad 1287
Kojto 106:ba1f97679dad 1288 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
Kojto 106:ba1f97679dad 1289 * @{
Kojto 106:ba1f97679dad 1290 */
Kojto 106:ba1f97679dad 1291 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1292 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
Kojto 106:ba1f97679dad 1293 /**
Kojto 106:ba1f97679dad 1294 * @}
Kojto 106:ba1f97679dad 1295 */
Kojto 106:ba1f97679dad 1296
Kojto 106:ba1f97679dad 1297 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
Kojto 106:ba1f97679dad 1298 * @{
Kojto 106:ba1f97679dad 1299 */
Kojto 106:ba1f97679dad 1300 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
Kojto 106:ba1f97679dad 1301 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1302 /**
Kojto 106:ba1f97679dad 1303 * @}
Kojto 106:ba1f97679dad 1304 */
Kojto 106:ba1f97679dad 1305
Kojto 106:ba1f97679dad 1306 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
Kojto 106:ba1f97679dad 1307 * @{
Kojto 106:ba1f97679dad 1308 */
Kojto 106:ba1f97679dad 1309 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
Kojto 106:ba1f97679dad 1310 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
Kojto 106:ba1f97679dad 1311 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
Kojto 106:ba1f97679dad 1312 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
Kojto 106:ba1f97679dad 1313 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
Kojto 106:ba1f97679dad 1314 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
Kojto 106:ba1f97679dad 1315 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
Kojto 106:ba1f97679dad 1316 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
Kojto 106:ba1f97679dad 1317 /**
Kojto 106:ba1f97679dad 1318 * @}
Kojto 106:ba1f97679dad 1319 */
Kojto 106:ba1f97679dad 1320
Kojto 106:ba1f97679dad 1321 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
Kojto 106:ba1f97679dad 1322 * @{
Kojto 106:ba1f97679dad 1323 */
Kojto 106:ba1f97679dad 1324 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
Kojto 106:ba1f97679dad 1325 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1326 /**
Kojto 106:ba1f97679dad 1327 * @}
Kojto 106:ba1f97679dad 1328 */
Kojto 106:ba1f97679dad 1329
Kojto 106:ba1f97679dad 1330 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
Kojto 106:ba1f97679dad 1331 * @{
Kojto 106:ba1f97679dad 1332 */
Kojto 106:ba1f97679dad 1333 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
Kojto 106:ba1f97679dad 1334 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1335 /**
Kojto 106:ba1f97679dad 1336 * @}
Kojto 106:ba1f97679dad 1337 */
Kojto 106:ba1f97679dad 1338
Kojto 106:ba1f97679dad 1339 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
Kojto 106:ba1f97679dad 1340 * @{
Kojto 106:ba1f97679dad 1341 */
Kojto 106:ba1f97679dad 1342 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
Kojto 106:ba1f97679dad 1343 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
Kojto 106:ba1f97679dad 1344 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
Kojto 106:ba1f97679dad 1345 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
Kojto 106:ba1f97679dad 1346 /**
Kojto 106:ba1f97679dad 1347 * @}
Kojto 106:ba1f97679dad 1348 */
Kojto 106:ba1f97679dad 1349
Kojto 106:ba1f97679dad 1350 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
Kojto 106:ba1f97679dad 1351 * @{
Kojto 106:ba1f97679dad 1352 */
Kojto 106:ba1f97679dad 1353 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
Kojto 106:ba1f97679dad 1354 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1355 /**
Kojto 106:ba1f97679dad 1356 * @}
Kojto 106:ba1f97679dad 1357 */
Kojto 106:ba1f97679dad 1358
Kojto 106:ba1f97679dad 1359 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
Kojto 106:ba1f97679dad 1360 * @{
Kojto 106:ba1f97679dad 1361 */
Kojto 106:ba1f97679dad 1362 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
Kojto 106:ba1f97679dad 1363 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1364 /**
Kojto 106:ba1f97679dad 1365 * @}
Kojto 106:ba1f97679dad 1366 */
Kojto 106:ba1f97679dad 1367
Kojto 106:ba1f97679dad 1368 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
Kojto 106:ba1f97679dad 1369 * @{
Kojto 106:ba1f97679dad 1370 */
Kojto 106:ba1f97679dad 1371 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
Kojto 106:ba1f97679dad 1372 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1373 /**
Kojto 106:ba1f97679dad 1374 * @}
Kojto 106:ba1f97679dad 1375 */
Kojto 106:ba1f97679dad 1376
Kojto 106:ba1f97679dad 1377 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
Kojto 106:ba1f97679dad 1378 * @{
Kojto 106:ba1f97679dad 1379 */
Kojto 106:ba1f97679dad 1380 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
Kojto 106:ba1f97679dad 1381 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
Kojto 106:ba1f97679dad 1382 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 106:ba1f97679dad 1383 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 106:ba1f97679dad 1384 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 106:ba1f97679dad 1385 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 106:ba1f97679dad 1386 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto 106:ba1f97679dad 1387 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto 106:ba1f97679dad 1388 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto 106:ba1f97679dad 1389 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto 106:ba1f97679dad 1390 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
Kojto 106:ba1f97679dad 1391 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
Kojto 106:ba1f97679dad 1392 /**
Kojto 106:ba1f97679dad 1393 * @}
Kojto 106:ba1f97679dad 1394 */
Kojto 106:ba1f97679dad 1395
Kojto 106:ba1f97679dad 1396 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
Kojto 106:ba1f97679dad 1397 * @{
Kojto 106:ba1f97679dad 1398 */
Kojto 106:ba1f97679dad 1399 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
Kojto 106:ba1f97679dad 1400 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
Kojto 106:ba1f97679dad 1401 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 106:ba1f97679dad 1402 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 106:ba1f97679dad 1403 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 106:ba1f97679dad 1404 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 106:ba1f97679dad 1405 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto 106:ba1f97679dad 1406 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto 106:ba1f97679dad 1407 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto 106:ba1f97679dad 1408 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto 106:ba1f97679dad 1409 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
Kojto 106:ba1f97679dad 1410 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Kojto 106:ba1f97679dad 1411 /**
Kojto 106:ba1f97679dad 1412 * @}
Kojto 106:ba1f97679dad 1413 */
Kojto 106:ba1f97679dad 1414
Kojto 106:ba1f97679dad 1415 /** @defgroup ETH_DMA_Enhanced_descriptor_format ETH DMA Enhanced descriptor format
Kojto 106:ba1f97679dad 1416 * @{
Kojto 106:ba1f97679dad 1417 */
Kojto 106:ba1f97679dad 1418 #define ETH_DMAENHANCEDDESCRIPTOR_ENABLE ((uint32_t)0x00000080)
Kojto 106:ba1f97679dad 1419 #define ETH_DMAENHANCEDDESCRIPTOR_DISABLE ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1420 /**
Kojto 106:ba1f97679dad 1421 * @}
Kojto 106:ba1f97679dad 1422 */
Kojto 106:ba1f97679dad 1423
Kojto 106:ba1f97679dad 1424 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
Kojto 106:ba1f97679dad 1425 * @{
Kojto 106:ba1f97679dad 1426 */
Kojto 106:ba1f97679dad 1427 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
Kojto 106:ba1f97679dad 1428 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
Kojto 106:ba1f97679dad 1429 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
Kojto 106:ba1f97679dad 1430 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
Kojto 106:ba1f97679dad 1431 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
Kojto 106:ba1f97679dad 1432 /**
Kojto 106:ba1f97679dad 1433 * @}
Kojto 106:ba1f97679dad 1434 */
Kojto 106:ba1f97679dad 1435
Kojto 106:ba1f97679dad 1436 /** @defgroup ETH_DMA_Tx_descriptor_segment ETH DMA Tx descriptor segment
Kojto 106:ba1f97679dad 1437 * @{
Kojto 106:ba1f97679dad 1438 */
Kojto 106:ba1f97679dad 1439 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
Kojto 106:ba1f97679dad 1440 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
Kojto 106:ba1f97679dad 1441 /**
Kojto 106:ba1f97679dad 1442 * @}
Kojto 106:ba1f97679dad 1443 */
Kojto 106:ba1f97679dad 1444
Kojto 106:ba1f97679dad 1445 /** @defgroup ETH_DMA_Tx_descriptor_Checksum_Insertion_Control ETH DMA Tx descriptor Checksum Insertion Control
Kojto 106:ba1f97679dad 1446 * @{
Kojto 106:ba1f97679dad 1447 */
Kojto 106:ba1f97679dad 1448 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
Kojto 106:ba1f97679dad 1449 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
Kojto 106:ba1f97679dad 1450 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
Kojto 106:ba1f97679dad 1451 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
Kojto 106:ba1f97679dad 1452 /**
Kojto 106:ba1f97679dad 1453 * @}
Kojto 106:ba1f97679dad 1454 */
Kojto 106:ba1f97679dad 1455
Kojto 106:ba1f97679dad 1456 /** @defgroup ETH_DMA_Rx_descriptor_buffers ETH DMA Rx descriptor buffers
Kojto 106:ba1f97679dad 1457 * @{
Kojto 106:ba1f97679dad 1458 */
Kojto 106:ba1f97679dad 1459 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
Kojto 106:ba1f97679dad 1460 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
Kojto 106:ba1f97679dad 1461 /**
Kojto 106:ba1f97679dad 1462 * @}
Kojto 106:ba1f97679dad 1463 */
Kojto 106:ba1f97679dad 1464
Kojto 106:ba1f97679dad 1465 /** @defgroup ETH_PMT_Flags ETH PMT Flags
Kojto 106:ba1f97679dad 1466 * @{
Kojto 106:ba1f97679dad 1467 */
Kojto 106:ba1f97679dad 1468 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
Kojto 106:ba1f97679dad 1469 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
Kojto 106:ba1f97679dad 1470 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
Kojto 106:ba1f97679dad 1471 /**
Kojto 106:ba1f97679dad 1472 * @}
Kojto 106:ba1f97679dad 1473 */
Kojto 106:ba1f97679dad 1474
Kojto 106:ba1f97679dad 1475 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
Kojto 106:ba1f97679dad 1476 * @{
Kojto 106:ba1f97679dad 1477 */
Kojto 106:ba1f97679dad 1478 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
Kojto 106:ba1f97679dad 1479 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
Kojto 106:ba1f97679dad 1480 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
Kojto 106:ba1f97679dad 1481 /**
Kojto 106:ba1f97679dad 1482 * @}
Kojto 106:ba1f97679dad 1483 */
Kojto 106:ba1f97679dad 1484
Kojto 106:ba1f97679dad 1485 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
Kojto 106:ba1f97679dad 1486 * @{
Kojto 106:ba1f97679dad 1487 */
Kojto 106:ba1f97679dad 1488 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
Kojto 106:ba1f97679dad 1489 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
Kojto 106:ba1f97679dad 1490 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
Kojto 106:ba1f97679dad 1491 /**
Kojto 106:ba1f97679dad 1492 * @}
Kojto 106:ba1f97679dad 1493 */
Kojto 106:ba1f97679dad 1494
Kojto 106:ba1f97679dad 1495 /** @defgroup ETH_MAC_Flags ETH MAC Flags
Kojto 106:ba1f97679dad 1496 * @{
Kojto 106:ba1f97679dad 1497 */
Kojto 106:ba1f97679dad 1498 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
Kojto 106:ba1f97679dad 1499 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
Kojto 106:ba1f97679dad 1500 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
Kojto 106:ba1f97679dad 1501 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
Kojto 106:ba1f97679dad 1502 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
Kojto 106:ba1f97679dad 1503 /**
Kojto 106:ba1f97679dad 1504 * @}
Kojto 106:ba1f97679dad 1505 */
Kojto 106:ba1f97679dad 1506
Kojto 106:ba1f97679dad 1507 /** @defgroup ETH_DMA_Flags ETH DMA Flags
Kojto 106:ba1f97679dad 1508 * @{
Kojto 106:ba1f97679dad 1509 */
Kojto 106:ba1f97679dad 1510 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
Kojto 106:ba1f97679dad 1511 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
Kojto 106:ba1f97679dad 1512 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
Kojto 106:ba1f97679dad 1513 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
Kojto 106:ba1f97679dad 1514 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write transfer, 1-read transfer */
Kojto 106:ba1f97679dad 1515 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
Kojto 106:ba1f97679dad 1516 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
Kojto 106:ba1f97679dad 1517 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
Kojto 106:ba1f97679dad 1518 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
Kojto 106:ba1f97679dad 1519 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
Kojto 106:ba1f97679dad 1520 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
Kojto 106:ba1f97679dad 1521 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
Kojto 106:ba1f97679dad 1522 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
Kojto 106:ba1f97679dad 1523 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
Kojto 106:ba1f97679dad 1524 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
Kojto 106:ba1f97679dad 1525 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
Kojto 106:ba1f97679dad 1526 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
Kojto 106:ba1f97679dad 1527 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
Kojto 106:ba1f97679dad 1528 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
Kojto 106:ba1f97679dad 1529 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
Kojto 106:ba1f97679dad 1530 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
Kojto 106:ba1f97679dad 1531 /**
Kojto 106:ba1f97679dad 1532 * @}
Kojto 106:ba1f97679dad 1533 */
Kojto 106:ba1f97679dad 1534
Kojto 106:ba1f97679dad 1535 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
Kojto 106:ba1f97679dad 1536 * @{
Kojto 106:ba1f97679dad 1537 */
Kojto 106:ba1f97679dad 1538 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
Kojto 106:ba1f97679dad 1539 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
Kojto 106:ba1f97679dad 1540 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
Kojto 106:ba1f97679dad 1541 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
Kojto 106:ba1f97679dad 1542 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
Kojto 106:ba1f97679dad 1543 /**
Kojto 106:ba1f97679dad 1544 * @}
Kojto 106:ba1f97679dad 1545 */
Kojto 106:ba1f97679dad 1546
Kojto 106:ba1f97679dad 1547 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
Kojto 106:ba1f97679dad 1548 * @{
Kojto 106:ba1f97679dad 1549 */
Kojto 106:ba1f97679dad 1550 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
Kojto 106:ba1f97679dad 1551 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
Kojto 106:ba1f97679dad 1552 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
Kojto 106:ba1f97679dad 1553 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
Kojto 106:ba1f97679dad 1554 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
Kojto 106:ba1f97679dad 1555 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
Kojto 106:ba1f97679dad 1556 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
Kojto 106:ba1f97679dad 1557 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
Kojto 106:ba1f97679dad 1558 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
Kojto 106:ba1f97679dad 1559 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
Kojto 106:ba1f97679dad 1560 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
Kojto 106:ba1f97679dad 1561 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
Kojto 106:ba1f97679dad 1562 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
Kojto 106:ba1f97679dad 1563 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
Kojto 106:ba1f97679dad 1564 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
Kojto 106:ba1f97679dad 1565 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
Kojto 106:ba1f97679dad 1566 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
Kojto 106:ba1f97679dad 1567 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
Kojto 106:ba1f97679dad 1568 /**
Kojto 106:ba1f97679dad 1569 * @}
Kojto 106:ba1f97679dad 1570 */
Kojto 106:ba1f97679dad 1571
Kojto 106:ba1f97679dad 1572 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
Kojto 106:ba1f97679dad 1573 * @{
Kojto 106:ba1f97679dad 1574 */
Kojto 106:ba1f97679dad 1575 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
Kojto 106:ba1f97679dad 1576 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
Kojto 106:ba1f97679dad 1577 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
Kojto 106:ba1f97679dad 1578 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
Kojto 106:ba1f97679dad 1579 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
Kojto 106:ba1f97679dad 1580 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
Kojto 106:ba1f97679dad 1581
Kojto 106:ba1f97679dad 1582 /**
Kojto 106:ba1f97679dad 1583 * @}
Kojto 106:ba1f97679dad 1584 */
Kojto 106:ba1f97679dad 1585
Kojto 106:ba1f97679dad 1586
Kojto 106:ba1f97679dad 1587 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
Kojto 106:ba1f97679dad 1588 * @{
Kojto 106:ba1f97679dad 1589 */
Kojto 106:ba1f97679dad 1590 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
Kojto 106:ba1f97679dad 1591 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
Kojto 106:ba1f97679dad 1592 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
Kojto 106:ba1f97679dad 1593 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
Kojto 106:ba1f97679dad 1594 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
Kojto 106:ba1f97679dad 1595 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
Kojto 106:ba1f97679dad 1596
Kojto 106:ba1f97679dad 1597 /**
Kojto 106:ba1f97679dad 1598 * @}
Kojto 106:ba1f97679dad 1599 */
Kojto 106:ba1f97679dad 1600
Kojto 106:ba1f97679dad 1601 /** @defgroup ETH_DMA_overflow ETH DMA overflow
Kojto 106:ba1f97679dad 1602 * @{
Kojto 106:ba1f97679dad 1603 */
Kojto 106:ba1f97679dad 1604 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
Kojto 106:ba1f97679dad 1605 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
Kojto 106:ba1f97679dad 1606 /**
Kojto 106:ba1f97679dad 1607 * @}
Kojto 106:ba1f97679dad 1608 */
Kojto 106:ba1f97679dad 1609
Kojto 106:ba1f97679dad 1610 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
Kojto 106:ba1f97679dad 1611 * @{
Kojto 106:ba1f97679dad 1612 */
Kojto 106:ba1f97679dad 1613 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
Kojto 106:ba1f97679dad 1614
Kojto 106:ba1f97679dad 1615 /**
Kojto 106:ba1f97679dad 1616 * @}
Kojto 106:ba1f97679dad 1617 */
Kojto 106:ba1f97679dad 1618
Kojto 106:ba1f97679dad 1619 /**
Kojto 106:ba1f97679dad 1620 * @}
Kojto 106:ba1f97679dad 1621 */
Kojto 106:ba1f97679dad 1622
Kojto 106:ba1f97679dad 1623 /* Exported macro ------------------------------------------------------------*/
Kojto 106:ba1f97679dad 1624 /** @defgroup ETH_Exported_Macros ETH Exported Macros
Kojto 106:ba1f97679dad 1625 * @brief macros to handle interrupts and specific clock configurations
Kojto 106:ba1f97679dad 1626 * @{
Kojto 106:ba1f97679dad 1627 */
Kojto 106:ba1f97679dad 1628
Kojto 106:ba1f97679dad 1629 /** @brief Reset ETH handle state
Kojto 106:ba1f97679dad 1630 * @param __HANDLE__: specifies the ETH handle.
Kojto 106:ba1f97679dad 1631 * @retval None
Kojto 106:ba1f97679dad 1632 */
Kojto 106:ba1f97679dad 1633 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
Kojto 106:ba1f97679dad 1634
Kojto 106:ba1f97679dad 1635 /**
Kojto 106:ba1f97679dad 1636 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
Kojto 106:ba1f97679dad 1637 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1638 * @param __FLAG__: specifies the flag of TDES0 to check.
Kojto 106:ba1f97679dad 1639 * @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto 106:ba1f97679dad 1640 */
Kojto 106:ba1f97679dad 1641 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto 106:ba1f97679dad 1642
Kojto 106:ba1f97679dad 1643 /**
Kojto 106:ba1f97679dad 1644 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
Kojto 106:ba1f97679dad 1645 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1646 * @param __FLAG__: specifies the flag of RDES0 to check.
Kojto 106:ba1f97679dad 1647 * @retval the ETH_DMATxDescFlag (SET or RESET).
Kojto 106:ba1f97679dad 1648 */
Kojto 106:ba1f97679dad 1649 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
Kojto 106:ba1f97679dad 1650
Kojto 106:ba1f97679dad 1651 /**
Kojto 106:ba1f97679dad 1652 * @brief Enables the specified DMA Rx Desc receive interrupt.
Kojto 106:ba1f97679dad 1653 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1654 * @retval None
Kojto 106:ba1f97679dad 1655 */
Kojto 106:ba1f97679dad 1656 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
Kojto 106:ba1f97679dad 1657
Kojto 106:ba1f97679dad 1658 /**
Kojto 106:ba1f97679dad 1659 * @brief Disables the specified DMA Rx Desc receive interrupt.
Kojto 106:ba1f97679dad 1660 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1661 * @retval None
Kojto 106:ba1f97679dad 1662 */
Kojto 106:ba1f97679dad 1663 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
Kojto 106:ba1f97679dad 1664
Kojto 106:ba1f97679dad 1665 /**
Kojto 106:ba1f97679dad 1666 * @brief Set the specified DMA Rx Desc Own bit.
Kojto 106:ba1f97679dad 1667 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1668 * @retval None
Kojto 106:ba1f97679dad 1669 */
Kojto 106:ba1f97679dad 1670 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
Kojto 106:ba1f97679dad 1671
Kojto 106:ba1f97679dad 1672 /**
Kojto 106:ba1f97679dad 1673 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
Kojto 106:ba1f97679dad 1674 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1675 * @retval The Transmit descriptor collision counter value.
Kojto 106:ba1f97679dad 1676 */
Kojto 106:ba1f97679dad 1677 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
Kojto 106:ba1f97679dad 1678
Kojto 106:ba1f97679dad 1679 /**
Kojto 106:ba1f97679dad 1680 * @brief Set the specified DMA Tx Desc Own bit.
Kojto 106:ba1f97679dad 1681 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1682 * @retval None
Kojto 106:ba1f97679dad 1683 */
Kojto 106:ba1f97679dad 1684 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
Kojto 106:ba1f97679dad 1685
Kojto 106:ba1f97679dad 1686 /**
Kojto 106:ba1f97679dad 1687 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
Kojto 106:ba1f97679dad 1688 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1689 * @retval None
Kojto 106:ba1f97679dad 1690 */
Kojto 106:ba1f97679dad 1691 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
Kojto 106:ba1f97679dad 1692
Kojto 106:ba1f97679dad 1693 /**
Kojto 106:ba1f97679dad 1694 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
Kojto 106:ba1f97679dad 1695 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1696 * @retval None
Kojto 106:ba1f97679dad 1697 */
Kojto 106:ba1f97679dad 1698 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
Kojto 106:ba1f97679dad 1699
Kojto 106:ba1f97679dad 1700 /**
Kojto 106:ba1f97679dad 1701 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
Kojto 106:ba1f97679dad 1702 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1703 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
Kojto 106:ba1f97679dad 1704 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 1705 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
Kojto 106:ba1f97679dad 1706 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
Kojto 106:ba1f97679dad 1707 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
Kojto 106:ba1f97679dad 1708 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
Kojto 106:ba1f97679dad 1709 * @retval None
Kojto 106:ba1f97679dad 1710 */
Kojto 106:ba1f97679dad 1711 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
Kojto 106:ba1f97679dad 1712
Kojto 106:ba1f97679dad 1713 /**
Kojto 106:ba1f97679dad 1714 * @brief Enables the DMA Tx Desc CRC.
Kojto 106:ba1f97679dad 1715 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1716 * @retval None
Kojto 106:ba1f97679dad 1717 */
Kojto 106:ba1f97679dad 1718 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
Kojto 106:ba1f97679dad 1719
Kojto 106:ba1f97679dad 1720 /**
Kojto 106:ba1f97679dad 1721 * @brief Disables the DMA Tx Desc CRC.
Kojto 106:ba1f97679dad 1722 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1723 * @retval None
Kojto 106:ba1f97679dad 1724 */
Kojto 106:ba1f97679dad 1725 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
Kojto 106:ba1f97679dad 1726
Kojto 106:ba1f97679dad 1727 /**
Kojto 106:ba1f97679dad 1728 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto 106:ba1f97679dad 1729 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1730 * @retval None
Kojto 106:ba1f97679dad 1731 */
Kojto 106:ba1f97679dad 1732 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
Kojto 106:ba1f97679dad 1733
Kojto 106:ba1f97679dad 1734 /**
Kojto 106:ba1f97679dad 1735 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
Kojto 106:ba1f97679dad 1736 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1737 * @retval None
Kojto 106:ba1f97679dad 1738 */
Kojto 106:ba1f97679dad 1739 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
Kojto 106:ba1f97679dad 1740
Kojto 106:ba1f97679dad 1741 /**
Kojto 106:ba1f97679dad 1742 * @brief Enables the specified ETHERNET MAC interrupts.
Kojto 106:ba1f97679dad 1743 * @param __HANDLE__ : ETH Handle
Kojto 106:ba1f97679dad 1744 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto 106:ba1f97679dad 1745 * enabled or disabled.
Kojto 106:ba1f97679dad 1746 * This parameter can be any combination of the following values:
Kojto 106:ba1f97679dad 1747 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto 106:ba1f97679dad 1748 * @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto 106:ba1f97679dad 1749 * @retval None
Kojto 106:ba1f97679dad 1750 */
Kojto 106:ba1f97679dad 1751 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
Kojto 106:ba1f97679dad 1752
Kojto 106:ba1f97679dad 1753 /**
Kojto 106:ba1f97679dad 1754 * @brief Disables the specified ETHERNET MAC interrupts.
Kojto 106:ba1f97679dad 1755 * @param __HANDLE__ : ETH Handle
Kojto 106:ba1f97679dad 1756 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
Kojto 106:ba1f97679dad 1757 * enabled or disabled.
Kojto 106:ba1f97679dad 1758 * This parameter can be any combination of the following values:
Kojto 106:ba1f97679dad 1759 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
Kojto 106:ba1f97679dad 1760 * @arg ETH_MAC_IT_PMT : PMT interrupt
Kojto 106:ba1f97679dad 1761 * @retval None
Kojto 106:ba1f97679dad 1762 */
Kojto 106:ba1f97679dad 1763 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
Kojto 106:ba1f97679dad 1764
Kojto 106:ba1f97679dad 1765 /**
Kojto 106:ba1f97679dad 1766 * @brief Initiate a Pause Control Frame (Full-duplex only).
Kojto 106:ba1f97679dad 1767 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1768 * @retval None
Kojto 106:ba1f97679dad 1769 */
Kojto 106:ba1f97679dad 1770 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
Kojto 106:ba1f97679dad 1771
Kojto 106:ba1f97679dad 1772 /**
Kojto 106:ba1f97679dad 1773 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
Kojto 106:ba1f97679dad 1774 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1775 * @retval The new state of flow control busy status bit (SET or RESET).
Kojto 106:ba1f97679dad 1776 */
Kojto 106:ba1f97679dad 1777 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
Kojto 106:ba1f97679dad 1778
Kojto 106:ba1f97679dad 1779 /**
Kojto 106:ba1f97679dad 1780 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
Kojto 106:ba1f97679dad 1781 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1782 * @retval None
Kojto 106:ba1f97679dad 1783 */
Kojto 106:ba1f97679dad 1784 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
Kojto 106:ba1f97679dad 1785
Kojto 106:ba1f97679dad 1786 /**
Kojto 106:ba1f97679dad 1787 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
Kojto 106:ba1f97679dad 1788 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1789 * @retval None
Kojto 106:ba1f97679dad 1790 */
Kojto 106:ba1f97679dad 1791 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
Kojto 106:ba1f97679dad 1792
Kojto 106:ba1f97679dad 1793 /**
Kojto 106:ba1f97679dad 1794 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
Kojto 106:ba1f97679dad 1795 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1796 * @param __FLAG__: specifies the flag to check.
Kojto 106:ba1f97679dad 1797 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 1798 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
Kojto 106:ba1f97679dad 1799 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
Kojto 106:ba1f97679dad 1800 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
Kojto 106:ba1f97679dad 1801 * @arg ETH_MAC_FLAG_MMC : MMC flag
Kojto 106:ba1f97679dad 1802 * @arg ETH_MAC_FLAG_PMT : PMT flag
Kojto 106:ba1f97679dad 1803 * @retval The state of ETHERNET MAC flag.
Kojto 106:ba1f97679dad 1804 */
Kojto 106:ba1f97679dad 1805 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
Kojto 106:ba1f97679dad 1806
Kojto 106:ba1f97679dad 1807 /**
Kojto 106:ba1f97679dad 1808 * @brief Enables the specified ETHERNET DMA interrupts.
Kojto 106:ba1f97679dad 1809 * @param __HANDLE__ : ETH Handle
Kojto 106:ba1f97679dad 1810 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto 106:ba1f97679dad 1811 * enabled @ref ETH_DMA_Interrupts
Kojto 106:ba1f97679dad 1812 * @retval None
Kojto 106:ba1f97679dad 1813 */
Kojto 106:ba1f97679dad 1814 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
Kojto 106:ba1f97679dad 1815
Kojto 106:ba1f97679dad 1816 /**
Kojto 106:ba1f97679dad 1817 * @brief Disables the specified ETHERNET DMA interrupts.
Kojto 106:ba1f97679dad 1818 * @param __HANDLE__ : ETH Handle
Kojto 106:ba1f97679dad 1819 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
Kojto 106:ba1f97679dad 1820 * disabled. @ref ETH_DMA_Interrupts
Kojto 106:ba1f97679dad 1821 * @retval None
Kojto 106:ba1f97679dad 1822 */
Kojto 106:ba1f97679dad 1823 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
Kojto 106:ba1f97679dad 1824
Kojto 106:ba1f97679dad 1825 /**
Kojto 106:ba1f97679dad 1826 * @brief Clears the ETHERNET DMA IT pending bit.
Kojto 106:ba1f97679dad 1827 * @param __HANDLE__ : ETH Handle
Kojto 106:ba1f97679dad 1828 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
Kojto 106:ba1f97679dad 1829 * @retval None
Kojto 106:ba1f97679dad 1830 */
Kojto 106:ba1f97679dad 1831 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
Kojto 106:ba1f97679dad 1832
Kojto 106:ba1f97679dad 1833 /**
Kojto 106:ba1f97679dad 1834 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto 106:ba1f97679dad 1835 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1836 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
Kojto 106:ba1f97679dad 1837 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto 106:ba1f97679dad 1838 */
Kojto 106:ba1f97679dad 1839 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
Kojto 106:ba1f97679dad 1840
Kojto 106:ba1f97679dad 1841 /**
Kojto 106:ba1f97679dad 1842 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
Kojto 106:ba1f97679dad 1843 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1844 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
Kojto 106:ba1f97679dad 1845 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
Kojto 106:ba1f97679dad 1846 */
Kojto 106:ba1f97679dad 1847 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
Kojto 106:ba1f97679dad 1848
Kojto 106:ba1f97679dad 1849 /**
Kojto 106:ba1f97679dad 1850 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
Kojto 106:ba1f97679dad 1851 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1852 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
Kojto 106:ba1f97679dad 1853 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 1854 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
Kojto 106:ba1f97679dad 1855 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
Kojto 106:ba1f97679dad 1856 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
Kojto 106:ba1f97679dad 1857 */
Kojto 106:ba1f97679dad 1858 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
Kojto 106:ba1f97679dad 1859
Kojto 106:ba1f97679dad 1860 /**
Kojto 106:ba1f97679dad 1861 * @brief Set the DMA Receive status watchdog timer register value
Kojto 106:ba1f97679dad 1862 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1863 * @param __VALUE__: DMA Receive status watchdog timer register value
Kojto 106:ba1f97679dad 1864 * @retval None
Kojto 106:ba1f97679dad 1865 */
Kojto 106:ba1f97679dad 1866 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
Kojto 106:ba1f97679dad 1867
Kojto 106:ba1f97679dad 1868 /**
Kojto 106:ba1f97679dad 1869 * @brief Enables any unicast packet filtered by the MAC address
Kojto 106:ba1f97679dad 1870 * recognition to be a wake-up frame.
Kojto 106:ba1f97679dad 1871 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1872 * @retval None
Kojto 106:ba1f97679dad 1873 */
Kojto 106:ba1f97679dad 1874 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
Kojto 106:ba1f97679dad 1875
Kojto 106:ba1f97679dad 1876 /**
Kojto 106:ba1f97679dad 1877 * @brief Disables any unicast packet filtered by the MAC address
Kojto 106:ba1f97679dad 1878 * recognition to be a wake-up frame.
Kojto 106:ba1f97679dad 1879 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1880 * @retval None
Kojto 106:ba1f97679dad 1881 */
Kojto 106:ba1f97679dad 1882 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
Kojto 106:ba1f97679dad 1883
Kojto 106:ba1f97679dad 1884 /**
Kojto 106:ba1f97679dad 1885 * @brief Enables the MAC Wake-Up Frame Detection.
Kojto 106:ba1f97679dad 1886 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1887 * @retval None
Kojto 106:ba1f97679dad 1888 */
Kojto 106:ba1f97679dad 1889 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
Kojto 106:ba1f97679dad 1890
Kojto 106:ba1f97679dad 1891 /**
Kojto 106:ba1f97679dad 1892 * @brief Disables the MAC Wake-Up Frame Detection.
Kojto 106:ba1f97679dad 1893 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1894 * @retval None
Kojto 106:ba1f97679dad 1895 */
Kojto 106:ba1f97679dad 1896 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto 106:ba1f97679dad 1897
Kojto 106:ba1f97679dad 1898 /**
Kojto 106:ba1f97679dad 1899 * @brief Enables the MAC Magic Packet Detection.
Kojto 106:ba1f97679dad 1900 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1901 * @retval None
Kojto 106:ba1f97679dad 1902 */
Kojto 106:ba1f97679dad 1903 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
Kojto 106:ba1f97679dad 1904
Kojto 106:ba1f97679dad 1905 /**
Kojto 106:ba1f97679dad 1906 * @brief Disables the MAC Magic Packet Detection.
Kojto 106:ba1f97679dad 1907 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1908 * @retval None
Kojto 106:ba1f97679dad 1909 */
Kojto 106:ba1f97679dad 1910 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
Kojto 106:ba1f97679dad 1911
Kojto 106:ba1f97679dad 1912 /**
Kojto 106:ba1f97679dad 1913 * @brief Enables the MAC Power Down.
Kojto 106:ba1f97679dad 1914 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1915 * @retval None
Kojto 106:ba1f97679dad 1916 */
Kojto 106:ba1f97679dad 1917 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
Kojto 106:ba1f97679dad 1918
Kojto 106:ba1f97679dad 1919 /**
Kojto 106:ba1f97679dad 1920 * @brief Disables the MAC Power Down.
Kojto 106:ba1f97679dad 1921 * @param __HANDLE__: ETH Handle
Kojto 106:ba1f97679dad 1922 * @retval None
Kojto 106:ba1f97679dad 1923 */
Kojto 106:ba1f97679dad 1924 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
Kojto 106:ba1f97679dad 1925
Kojto 106:ba1f97679dad 1926 /**
Kojto 106:ba1f97679dad 1927 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
Kojto 106:ba1f97679dad 1928 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1929 * @param __FLAG__: specifies the flag to check.
Kojto 106:ba1f97679dad 1930 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 1931 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
Kojto 106:ba1f97679dad 1932 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
Kojto 106:ba1f97679dad 1933 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
Kojto 106:ba1f97679dad 1934 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
Kojto 106:ba1f97679dad 1935 */
Kojto 106:ba1f97679dad 1936 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
Kojto 106:ba1f97679dad 1937
Kojto 106:ba1f97679dad 1938 /**
Kojto 106:ba1f97679dad 1939 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
Kojto 106:ba1f97679dad 1940 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1941 * @retval None
Kojto 106:ba1f97679dad 1942 */
Kojto 106:ba1f97679dad 1943 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
Kojto 106:ba1f97679dad 1944
Kojto 106:ba1f97679dad 1945 /**
Kojto 106:ba1f97679dad 1946 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
Kojto 106:ba1f97679dad 1947 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1948 * @retval None
Kojto 106:ba1f97679dad 1949 */
Kojto 106:ba1f97679dad 1950 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
Kojto 106:ba1f97679dad 1951 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
Kojto 106:ba1f97679dad 1952
Kojto 106:ba1f97679dad 1953 /**
Kojto 106:ba1f97679dad 1954 * @brief Enables the MMC Counter Freeze.
Kojto 106:ba1f97679dad 1955 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1956 * @retval None
Kojto 106:ba1f97679dad 1957 */
Kojto 106:ba1f97679dad 1958 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
Kojto 106:ba1f97679dad 1959
Kojto 106:ba1f97679dad 1960 /**
Kojto 106:ba1f97679dad 1961 * @brief Disables the MMC Counter Freeze.
Kojto 106:ba1f97679dad 1962 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1963 * @retval None
Kojto 106:ba1f97679dad 1964 */
Kojto 106:ba1f97679dad 1965 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
Kojto 106:ba1f97679dad 1966
Kojto 106:ba1f97679dad 1967 /**
Kojto 106:ba1f97679dad 1968 * @brief Enables the MMC Reset On Read.
Kojto 106:ba1f97679dad 1969 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1970 * @retval None
Kojto 106:ba1f97679dad 1971 */
Kojto 106:ba1f97679dad 1972 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
Kojto 106:ba1f97679dad 1973
Kojto 106:ba1f97679dad 1974 /**
Kojto 106:ba1f97679dad 1975 * @brief Disables the MMC Reset On Read.
Kojto 106:ba1f97679dad 1976 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1977 * @retval None
Kojto 106:ba1f97679dad 1978 */
Kojto 106:ba1f97679dad 1979 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
Kojto 106:ba1f97679dad 1980
Kojto 106:ba1f97679dad 1981 /**
Kojto 106:ba1f97679dad 1982 * @brief Enables the MMC Counter Stop Rollover.
Kojto 106:ba1f97679dad 1983 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1984 * @retval None
Kojto 106:ba1f97679dad 1985 */
Kojto 106:ba1f97679dad 1986 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
Kojto 106:ba1f97679dad 1987
Kojto 106:ba1f97679dad 1988 /**
Kojto 106:ba1f97679dad 1989 * @brief Disables the MMC Counter Stop Rollover.
Kojto 106:ba1f97679dad 1990 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1991 * @retval None
Kojto 106:ba1f97679dad 1992 */
Kojto 106:ba1f97679dad 1993 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
Kojto 106:ba1f97679dad 1994
Kojto 106:ba1f97679dad 1995 /**
Kojto 106:ba1f97679dad 1996 * @brief Resets the MMC Counters.
Kojto 106:ba1f97679dad 1997 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 1998 * @retval None
Kojto 106:ba1f97679dad 1999 */
Kojto 106:ba1f97679dad 2000 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
Kojto 106:ba1f97679dad 2001
Kojto 106:ba1f97679dad 2002 /**
Kojto 106:ba1f97679dad 2003 * @brief Enables the specified ETHERNET MMC Rx interrupts.
Kojto 106:ba1f97679dad 2004 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 2005 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto 106:ba1f97679dad 2006 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2007 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto 106:ba1f97679dad 2008 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto 106:ba1f97679dad 2009 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto 106:ba1f97679dad 2010 * @retval None
Kojto 106:ba1f97679dad 2011 */
Kojto 106:ba1f97679dad 2012 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
Kojto 106:ba1f97679dad 2013 /**
Kojto 106:ba1f97679dad 2014 * @brief Disables the specified ETHERNET MMC Rx interrupts.
Kojto 106:ba1f97679dad 2015 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 2016 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto 106:ba1f97679dad 2017 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2018 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
Kojto 106:ba1f97679dad 2019 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
Kojto 106:ba1f97679dad 2020 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
Kojto 106:ba1f97679dad 2021 * @retval None
Kojto 106:ba1f97679dad 2022 */
Kojto 106:ba1f97679dad 2023 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
Kojto 106:ba1f97679dad 2024 /**
Kojto 106:ba1f97679dad 2025 * @brief Enables the specified ETHERNET MMC Tx interrupts.
Kojto 106:ba1f97679dad 2026 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 2027 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto 106:ba1f97679dad 2028 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2029 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto 106:ba1f97679dad 2030 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto 106:ba1f97679dad 2031 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto 106:ba1f97679dad 2032 * @retval None
Kojto 106:ba1f97679dad 2033 */
Kojto 106:ba1f97679dad 2034 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
Kojto 106:ba1f97679dad 2035
Kojto 106:ba1f97679dad 2036 /**
Kojto 106:ba1f97679dad 2037 * @brief Disables the specified ETHERNET MMC Tx interrupts.
Kojto 106:ba1f97679dad 2038 * @param __HANDLE__: ETH Handle.
Kojto 106:ba1f97679dad 2039 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
Kojto 106:ba1f97679dad 2040 * This parameter can be one of the following values:
Kojto 106:ba1f97679dad 2041 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
Kojto 106:ba1f97679dad 2042 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
Kojto 106:ba1f97679dad 2043 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
Kojto 106:ba1f97679dad 2044 * @retval None
Kojto 106:ba1f97679dad 2045 */
Kojto 106:ba1f97679dad 2046 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
Kojto 106:ba1f97679dad 2047
Kojto 106:ba1f97679dad 2048 /**
Kojto 106:ba1f97679dad 2049 * @brief Enables the ETH External interrupt line.
Kojto 106:ba1f97679dad 2050 * @retval None
Kojto 106:ba1f97679dad 2051 */
Kojto 106:ba1f97679dad 2052 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2053
Kojto 106:ba1f97679dad 2054 /**
Kojto 106:ba1f97679dad 2055 * @brief Disables the ETH External interrupt line.
Kojto 106:ba1f97679dad 2056 * @retval None
Kojto 106:ba1f97679dad 2057 */
Kojto 106:ba1f97679dad 2058 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2059
Kojto 106:ba1f97679dad 2060 /**
Kojto 106:ba1f97679dad 2061 * @brief Enable event on ETH External event line.
Kojto 106:ba1f97679dad 2062 * @retval None.
Kojto 106:ba1f97679dad 2063 */
Kojto 106:ba1f97679dad 2064 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2065
Kojto 106:ba1f97679dad 2066 /**
Kojto 106:ba1f97679dad 2067 * @brief Disable event on ETH External event line
Kojto 106:ba1f97679dad 2068 * @retval None.
Kojto 106:ba1f97679dad 2069 */
Kojto 106:ba1f97679dad 2070 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2071
Kojto 106:ba1f97679dad 2072 /**
Kojto 106:ba1f97679dad 2073 * @brief Get flag of the ETH External interrupt line.
Kojto 106:ba1f97679dad 2074 * @retval None
Kojto 106:ba1f97679dad 2075 */
Kojto 106:ba1f97679dad 2076 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2077
Kojto 106:ba1f97679dad 2078 /**
Kojto 106:ba1f97679dad 2079 * @brief Clear flag of the ETH External interrupt line.
Kojto 106:ba1f97679dad 2080 * @retval None
Kojto 106:ba1f97679dad 2081 */
Kojto 106:ba1f97679dad 2082 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2083
Kojto 106:ba1f97679dad 2084 /**
Kojto 106:ba1f97679dad 2085 * @brief Enables rising edge trigger to the ETH External interrupt line.
Kojto 106:ba1f97679dad 2086 * @retval None
Kojto 106:ba1f97679dad 2087 */
Kojto 106:ba1f97679dad 2088 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
Kojto 106:ba1f97679dad 2089
Kojto 106:ba1f97679dad 2090 /**
Kojto 106:ba1f97679dad 2091 * @brief Disables the rising edge trigger to the ETH External interrupt line.
Kojto 106:ba1f97679dad 2092 * @retval None
Kojto 106:ba1f97679dad 2093 */
Kojto 110:165afa46840b 2094 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2095
Kojto 106:ba1f97679dad 2096 /**
Kojto 106:ba1f97679dad 2097 * @brief Enables falling edge trigger to the ETH External interrupt line.
Kojto 106:ba1f97679dad 2098 * @retval None
Kojto 106:ba1f97679dad 2099 */
Kojto 106:ba1f97679dad 2100 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2101
Kojto 106:ba1f97679dad 2102 /**
Kojto 106:ba1f97679dad 2103 * @brief Disables falling edge trigger to the ETH External interrupt line.
Kojto 106:ba1f97679dad 2104 * @retval None
Kojto 106:ba1f97679dad 2105 */
Kojto 106:ba1f97679dad 2106 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2107
Kojto 106:ba1f97679dad 2108 /**
Kojto 106:ba1f97679dad 2109 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
Kojto 106:ba1f97679dad 2110 * @retval None
Kojto 106:ba1f97679dad 2111 */
Kojto 106:ba1f97679dad 2112 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
Kojto 106:ba1f97679dad 2113 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
Kojto 106:ba1f97679dad 2114
Kojto 106:ba1f97679dad 2115 /**
Kojto 106:ba1f97679dad 2116 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
Kojto 106:ba1f97679dad 2117 * @retval None
Kojto 106:ba1f97679dad 2118 */
Kojto 106:ba1f97679dad 2119 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
Kojto 106:ba1f97679dad 2120 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
Kojto 106:ba1f97679dad 2121
Kojto 106:ba1f97679dad 2122 /**
Kojto 106:ba1f97679dad 2123 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 106:ba1f97679dad 2124 * @retval None.
Kojto 106:ba1f97679dad 2125 */
Kojto 106:ba1f97679dad 2126 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
Kojto 106:ba1f97679dad 2127
Kojto 106:ba1f97679dad 2128 /**
Kojto 106:ba1f97679dad 2129 * @}
Kojto 106:ba1f97679dad 2130 */
Kojto 106:ba1f97679dad 2131 /* Exported functions --------------------------------------------------------*/
Kojto 106:ba1f97679dad 2132
Kojto 106:ba1f97679dad 2133 /** @addtogroup ETH_Exported_Functions
Kojto 106:ba1f97679dad 2134 * @{
Kojto 106:ba1f97679dad 2135 */
Kojto 106:ba1f97679dad 2136
Kojto 106:ba1f97679dad 2137 /* Initialization and de-initialization functions ****************************/
Kojto 106:ba1f97679dad 2138
Kojto 106:ba1f97679dad 2139 /** @addtogroup ETH_Exported_Functions_Group1
Kojto 106:ba1f97679dad 2140 * @{
Kojto 106:ba1f97679dad 2141 */
Kojto 106:ba1f97679dad 2142 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2143 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2144 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2145 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2146 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
Kojto 106:ba1f97679dad 2147 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
Kojto 106:ba1f97679dad 2148
Kojto 106:ba1f97679dad 2149 /**
Kojto 106:ba1f97679dad 2150 * @}
Kojto 106:ba1f97679dad 2151 */
Kojto 106:ba1f97679dad 2152 /* IO operation functions ****************************************************/
Kojto 106:ba1f97679dad 2153
Kojto 106:ba1f97679dad 2154 /** @addtogroup ETH_Exported_Functions_Group2
Kojto 106:ba1f97679dad 2155 * @{
Kojto 106:ba1f97679dad 2156 */
Kojto 106:ba1f97679dad 2157 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
Kojto 106:ba1f97679dad 2158 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2159 /* Communication with PHY functions*/
Kojto 106:ba1f97679dad 2160 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
Kojto 106:ba1f97679dad 2161 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
Kojto 106:ba1f97679dad 2162 /* Non-Blocking mode: Interrupt */
Kojto 106:ba1f97679dad 2163 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2164 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2165 /* Callback in non blocking modes (Interrupt) */
Kojto 106:ba1f97679dad 2166 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2167 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2168 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2169 /**
Kojto 106:ba1f97679dad 2170 * @}
Kojto 106:ba1f97679dad 2171 */
Kojto 106:ba1f97679dad 2172
Kojto 106:ba1f97679dad 2173 /* Peripheral Control functions **********************************************/
Kojto 106:ba1f97679dad 2174
Kojto 106:ba1f97679dad 2175 /** @addtogroup ETH_Exported_Functions_Group3
Kojto 106:ba1f97679dad 2176 * @{
Kojto 106:ba1f97679dad 2177 */
Kojto 106:ba1f97679dad 2178
Kojto 106:ba1f97679dad 2179 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2180 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2181 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
Kojto 106:ba1f97679dad 2182 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
Kojto 106:ba1f97679dad 2183 /**
Kojto 106:ba1f97679dad 2184 * @}
Kojto 106:ba1f97679dad 2185 */
Kojto 106:ba1f97679dad 2186
Kojto 106:ba1f97679dad 2187 /* Peripheral State functions ************************************************/
Kojto 106:ba1f97679dad 2188
Kojto 106:ba1f97679dad 2189 /** @addtogroup ETH_Exported_Functions_Group4
Kojto 106:ba1f97679dad 2190 * @{
Kojto 106:ba1f97679dad 2191 */
Kojto 106:ba1f97679dad 2192 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
Kojto 106:ba1f97679dad 2193 /**
Kojto 106:ba1f97679dad 2194 * @}
Kojto 106:ba1f97679dad 2195 */
Kojto 106:ba1f97679dad 2196
Kojto 106:ba1f97679dad 2197 /**
Kojto 106:ba1f97679dad 2198 * @}
Kojto 106:ba1f97679dad 2199 */
Kojto 106:ba1f97679dad 2200
Kojto 106:ba1f97679dad 2201 /**
Kojto 106:ba1f97679dad 2202 * @}
Kojto 106:ba1f97679dad 2203 */
Kojto 106:ba1f97679dad 2204
Kojto 106:ba1f97679dad 2205 /**
Kojto 106:ba1f97679dad 2206 * @}
Kojto 106:ba1f97679dad 2207 */
Kojto 106:ba1f97679dad 2208
Kojto 110:165afa46840b 2209 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
Kojto 110:165afa46840b 2210 STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
Kojto 106:ba1f97679dad 2211
Kojto 106:ba1f97679dad 2212 #ifdef __cplusplus
Kojto 106:ba1f97679dad 2213 }
Kojto 106:ba1f97679dad 2214 #endif
Kojto 106:ba1f97679dad 2215
Kojto 106:ba1f97679dad 2216 #endif /* __STM32F4xx_HAL_ETH_H */
Kojto 106:ba1f97679dad 2217
Kojto 106:ba1f97679dad 2218
Kojto 106:ba1f97679dad 2219 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/