Ricardo Benitez / mbed

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TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
106:ba1f97679dad 
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_pwr.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
emilmont 77:869cf507173a 7 * @brief Header file of PWR HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_PWR_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_PWR_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup PWR
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 58
Kojto 99:dbbf35b96557 59 /** @defgroup PWR_Exported_Types PWR Exported Types
Kojto 99:dbbf35b96557 60 * @{
Kojto 99:dbbf35b96557 61 */
Kojto 99:dbbf35b96557 62
emilmont 77:869cf507173a 63 /**
emilmont 77:869cf507173a 64 * @brief PWR PVD configuration structure definition
emilmont 77:869cf507173a 65 */
emilmont 77:869cf507173a 66 typedef struct
emilmont 77:869cf507173a 67 {
bogdanm 85:024bf7f99721 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
emilmont 77:869cf507173a 69 This parameter can be a value of @ref PWR_PVD_detection_level */
emilmont 77:869cf507173a 70
emilmont 77:869cf507173a 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
emilmont 77:869cf507173a 72 This parameter can be a value of @ref PWR_PVD_Mode */
emilmont 77:869cf507173a 73 }PWR_PVDTypeDef;
emilmont 77:869cf507173a 74
emilmont 77:869cf507173a 75 /**
emilmont 77:869cf507173a 76 * @}
emilmont 77:869cf507173a 77 */
emilmont 77:869cf507173a 78
Kojto 99:dbbf35b96557 79 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 80 /** @defgroup PWR_Exported_Constants PWR Exported Constants
Kojto 99:dbbf35b96557 81 * @{
Kojto 99:dbbf35b96557 82 */
Kojto 99:dbbf35b96557 83
Kojto 99:dbbf35b96557 84 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
Kojto 99:dbbf35b96557 85 * @{
Kojto 99:dbbf35b96557 86 */
Kojto 99:dbbf35b96557 87 #define PWR_WAKEUP_PIN1 ((uint32_t)0x00000100)
Kojto 99:dbbf35b96557 88 /**
Kojto 99:dbbf35b96557 89 * @}
Kojto 99:dbbf35b96557 90 */
Kojto 99:dbbf35b96557 91
Kojto 99:dbbf35b96557 92 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
emilmont 77:869cf507173a 93 * @{
emilmont 77:869cf507173a 94 */
emilmont 77:869cf507173a 95 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
emilmont 77:869cf507173a 96 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
emilmont 77:869cf507173a 97 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
emilmont 77:869cf507173a 98 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
emilmont 77:869cf507173a 99 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
emilmont 77:869cf507173a 100 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
emilmont 77:869cf507173a 101 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
Kojto 99:dbbf35b96557 102 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7/* External input analog voltage
Kojto 99:dbbf35b96557 103 (Compare internally to VREFINT) */
emilmont 77:869cf507173a 104 /**
emilmont 77:869cf507173a 105 * @}
emilmont 77:869cf507173a 106 */
emilmont 77:869cf507173a 107
Kojto 99:dbbf35b96557 108 /** @defgroup PWR_PVD_Mode PWR PVD Mode
emilmont 77:869cf507173a 109 * @{
emilmont 77:869cf507173a 110 */
Kojto 99:dbbf35b96557 111 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
Kojto 99:dbbf35b96557 112 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
Kojto 99:dbbf35b96557 113 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
Kojto 99:dbbf35b96557 114 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
Kojto 99:dbbf35b96557 115 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
Kojto 99:dbbf35b96557 116 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
Kojto 99:dbbf35b96557 117 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
emilmont 77:869cf507173a 118 /**
emilmont 77:869cf507173a 119 * @}
Kojto 99:dbbf35b96557 120 */
emilmont 77:869cf507173a 121
Kojto 99:dbbf35b96557 122
Kojto 99:dbbf35b96557 123 /** @defgroup PWR_Regulator_state_in_STOP_mode PWR Regulator state in SLEEP/STOP mode
emilmont 77:869cf507173a 124 * @{
emilmont 77:869cf507173a 125 */
emilmont 77:869cf507173a 126 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
emilmont 77:869cf507173a 127 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
emilmont 77:869cf507173a 128 /**
emilmont 77:869cf507173a 129 * @}
emilmont 77:869cf507173a 130 */
emilmont 77:869cf507173a 131
Kojto 99:dbbf35b96557 132 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
emilmont 77:869cf507173a 133 * @{
emilmont 77:869cf507173a 134 */
emilmont 77:869cf507173a 135 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
emilmont 77:869cf507173a 136 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
emilmont 77:869cf507173a 137 /**
emilmont 77:869cf507173a 138 * @}
emilmont 77:869cf507173a 139 */
emilmont 77:869cf507173a 140
Kojto 99:dbbf35b96557 141 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
emilmont 77:869cf507173a 142 * @{
emilmont 77:869cf507173a 143 */
emilmont 77:869cf507173a 144 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
emilmont 77:869cf507173a 145 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
emilmont 77:869cf507173a 146 /**
emilmont 77:869cf507173a 147 * @}
emilmont 77:869cf507173a 148 */
emilmont 77:869cf507173a 149
Kojto 99:dbbf35b96557 150 /** @defgroup PWR_Flag PWR Flag
emilmont 77:869cf507173a 151 * @{
emilmont 77:869cf507173a 152 */
emilmont 77:869cf507173a 153 #define PWR_FLAG_WU PWR_CSR_WUF
emilmont 77:869cf507173a 154 #define PWR_FLAG_SB PWR_CSR_SBF
emilmont 77:869cf507173a 155 #define PWR_FLAG_PVDO PWR_CSR_PVDO
emilmont 77:869cf507173a 156 #define PWR_FLAG_BRR PWR_CSR_BRR
emilmont 77:869cf507173a 157 #define PWR_FLAG_VOSRDY PWR_CSR_VOSRDY
emilmont 77:869cf507173a 158 /**
emilmont 77:869cf507173a 159 * @}
emilmont 77:869cf507173a 160 */
emilmont 77:869cf507173a 161
emilmont 77:869cf507173a 162 /**
emilmont 77:869cf507173a 163 * @}
emilmont 77:869cf507173a 164 */
emilmont 77:869cf507173a 165
emilmont 77:869cf507173a 166 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 167 /** @defgroup PWR_Exported_Macro PWR Exported Macro
Kojto 99:dbbf35b96557 168 * @{
Kojto 99:dbbf35b96557 169 */
emilmont 77:869cf507173a 170
emilmont 77:869cf507173a 171 /** @brief Check PWR flag is set or not.
emilmont 77:869cf507173a 172 * @param __FLAG__: specifies the flag to check.
emilmont 77:869cf507173a 173 * This parameter can be one of the following values:
emilmont 77:869cf507173a 174 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
emilmont 77:869cf507173a 175 * was received from the WKUP pin or from the RTC alarm (Alarm A
emilmont 77:869cf507173a 176 * or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
emilmont 77:869cf507173a 177 * An additional wakeup event is detected if the WKUP pin is enabled
emilmont 77:869cf507173a 178 * (by setting the EWUP bit) when the WKUP pin level is already high.
emilmont 77:869cf507173a 179 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
emilmont 77:869cf507173a 180 * resumed from StandBy mode.
emilmont 77:869cf507173a 181 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
emilmont 77:869cf507173a 182 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
emilmont 77:869cf507173a 183 * For this reason, this bit is equal to 0 after Standby or reset
emilmont 77:869cf507173a 184 * until the PVDE bit is set.
emilmont 77:869cf507173a 185 * @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset
emilmont 77:869cf507173a 186 * when the device wakes up from Standby mode or by a system reset
emilmont 77:869cf507173a 187 * or power reset.
emilmont 77:869cf507173a 188 * @arg PWR_FLAG_VOSRDY: This flag indicates that the Regulator voltage
emilmont 77:869cf507173a 189 * scaling output selection is ready.
emilmont 77:869cf507173a 190 * @retval The new state of __FLAG__ (TRUE or FALSE).
emilmont 77:869cf507173a 191 */
emilmont 77:869cf507173a 192 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
emilmont 77:869cf507173a 193
emilmont 77:869cf507173a 194 /** @brief Clear the PWR's pending flags.
emilmont 77:869cf507173a 195 * @param __FLAG__: specifies the flag to clear.
emilmont 77:869cf507173a 196 * This parameter can be one of the following values:
emilmont 77:869cf507173a 197 * @arg PWR_FLAG_WU: Wake Up flag
emilmont 77:869cf507173a 198 * @arg PWR_FLAG_SB: StandBy flag
emilmont 77:869cf507173a 199 */
emilmont 77:869cf507173a 200 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
emilmont 77:869cf507173a 201
Kojto 99:dbbf35b96557 202 /**
Kojto 99:dbbf35b96557 203 * @brief Enable the PVD Exti Line 16.
Kojto 99:dbbf35b96557 204 * @retval None.
Kojto 99:dbbf35b96557 205 */
Kojto 99:dbbf35b96557 206 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 207
Kojto 99:dbbf35b96557 208 /**
Kojto 99:dbbf35b96557 209 * @brief Disable the PVD EXTI Line 16.
Kojto 99:dbbf35b96557 210 * @retval None.
Kojto 99:dbbf35b96557 211 */
Kojto 99:dbbf35b96557 212 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 213
emilmont 77:869cf507173a 214 /**
Kojto 99:dbbf35b96557 215 * @brief Enable event on PVD Exti Line 16.
Kojto 99:dbbf35b96557 216 * @retval None.
Kojto 99:dbbf35b96557 217 */
Kojto 99:dbbf35b96557 218 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 219
Kojto 99:dbbf35b96557 220 /**
Kojto 99:dbbf35b96557 221 * @brief Disable event on PVD Exti Line 16.
Kojto 99:dbbf35b96557 222 * @retval None.
Kojto 99:dbbf35b96557 223 */
Kojto 99:dbbf35b96557 224 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 225
Kojto 99:dbbf35b96557 226 /**
Kojto 99:dbbf35b96557 227 * @brief Enable the PVD Extended Interrupt Rising Trigger.
emilmont 77:869cf507173a 228 * @retval None.
emilmont 77:869cf507173a 229 */
Kojto 99:dbbf35b96557 230 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 231
Kojto 99:dbbf35b96557 232 /**
Kojto 99:dbbf35b96557 233 * @brief Disable the PVD Extended Interrupt Rising Trigger.
Kojto 99:dbbf35b96557 234 * @retval None.
Kojto 99:dbbf35b96557 235 */
Kojto 99:dbbf35b96557 236 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 237
Kojto 99:dbbf35b96557 238 /**
Kojto 99:dbbf35b96557 239 * @brief Enable the PVD Extended Interrupt Falling Trigger.
Kojto 99:dbbf35b96557 240 * @retval None.
Kojto 99:dbbf35b96557 241 */
Kojto 99:dbbf35b96557 242 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 243
emilmont 77:869cf507173a 244
emilmont 77:869cf507173a 245 /**
Kojto 99:dbbf35b96557 246 * @brief Disable the PVD Extended Interrupt Falling Trigger.
emilmont 77:869cf507173a 247 * @retval None.
emilmont 77:869cf507173a 248 */
Kojto 99:dbbf35b96557 249 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
Kojto 99:dbbf35b96557 250
Kojto 99:dbbf35b96557 251
Kojto 99:dbbf35b96557 252 /**
Kojto 99:dbbf35b96557 253 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
Kojto 99:dbbf35b96557 254 * @retval None.
Kojto 99:dbbf35b96557 255 */
Kojto 99:dbbf35b96557 256 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
Kojto 99:dbbf35b96557 257
Kojto 99:dbbf35b96557 258 /**
Kojto 99:dbbf35b96557 259 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
Kojto 99:dbbf35b96557 260 * This parameter can be:
Kojto 99:dbbf35b96557 261 * @retval None.
Kojto 99:dbbf35b96557 262 */
Kojto 99:dbbf35b96557 263 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
emilmont 77:869cf507173a 264
emilmont 77:869cf507173a 265 /**
emilmont 77:869cf507173a 266 * @brief checks whether the specified PVD Exti interrupt flag is set or not.
emilmont 77:869cf507173a 267 * @retval EXTI PVD Line Status.
emilmont 77:869cf507173a 268 */
Kojto 99:dbbf35b96557 269 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
emilmont 77:869cf507173a 270
emilmont 77:869cf507173a 271 /**
emilmont 77:869cf507173a 272 * @brief Clear the PVD Exti flag.
emilmont 77:869cf507173a 273 * @retval None.
emilmont 77:869cf507173a 274 */
Kojto 99:dbbf35b96557 275 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
emilmont 77:869cf507173a 276
Kojto 90:cb3d968589d8 277 /**
Kojto 99:dbbf35b96557 278 * @brief Generates a Software interrupt on PVD EXTI line.
Kojto 90:cb3d968589d8 279 * @retval None
Kojto 90:cb3d968589d8 280 */
Kojto 99:dbbf35b96557 281 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Kojto 99:dbbf35b96557 282
Kojto 99:dbbf35b96557 283 /**
Kojto 99:dbbf35b96557 284 * @}
Kojto 99:dbbf35b96557 285 */
emilmont 77:869cf507173a 286
emilmont 77:869cf507173a 287 /* Include PWR HAL Extension module */
emilmont 77:869cf507173a 288 #include "stm32f4xx_hal_pwr_ex.h"
emilmont 77:869cf507173a 289
emilmont 77:869cf507173a 290 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 291 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
Kojto 99:dbbf35b96557 292 * @{
Kojto 99:dbbf35b96557 293 */
Kojto 99:dbbf35b96557 294
Kojto 99:dbbf35b96557 295 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 99:dbbf35b96557 296 * @{
Kojto 99:dbbf35b96557 297 */
Kojto 90:cb3d968589d8 298 /* Initialization and de-initialization functions *****************************/
Kojto 90:cb3d968589d8 299 void HAL_PWR_DeInit(void);
Kojto 90:cb3d968589d8 300 void HAL_PWR_EnableBkUpAccess(void);
Kojto 90:cb3d968589d8 301 void HAL_PWR_DisableBkUpAccess(void);
Kojto 99:dbbf35b96557 302 /**
Kojto 99:dbbf35b96557 303 * @}
Kojto 99:dbbf35b96557 304 */
Kojto 90:cb3d968589d8 305
Kojto 99:dbbf35b96557 306 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
Kojto 99:dbbf35b96557 307 * @{
Kojto 99:dbbf35b96557 308 */
Kojto 90:cb3d968589d8 309 /* Peripheral Control functions **********************************************/
Kojto 90:cb3d968589d8 310 /* PVD configuration */
Kojto 99:dbbf35b96557 311 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
Kojto 90:cb3d968589d8 312 void HAL_PWR_EnablePVD(void);
Kojto 90:cb3d968589d8 313 void HAL_PWR_DisablePVD(void);
emilmont 77:869cf507173a 314
Kojto 90:cb3d968589d8 315 /* WakeUp pins configuration */
Kojto 90:cb3d968589d8 316 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
Kojto 90:cb3d968589d8 317 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
emilmont 77:869cf507173a 318
Kojto 90:cb3d968589d8 319 /* Low Power modes entry */
Kojto 90:cb3d968589d8 320 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
Kojto 90:cb3d968589d8 321 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
Kojto 90:cb3d968589d8 322 void HAL_PWR_EnterSTANDBYMode(void);
emilmont 77:869cf507173a 323
Kojto 99:dbbf35b96557 324 /* Power PVD IRQ Handler */
Kojto 90:cb3d968589d8 325 void HAL_PWR_PVD_IRQHandler(void);
bogdanm 81:7d30d6019079 326 void HAL_PWR_PVDCallback(void);
emilmont 77:869cf507173a 327
Kojto 99:dbbf35b96557 328 /* Cortex System Control functions *******************************************/
Kojto 99:dbbf35b96557 329 void HAL_PWR_EnableSleepOnExit(void);
Kojto 99:dbbf35b96557 330 void HAL_PWR_DisableSleepOnExit(void);
Kojto 99:dbbf35b96557 331 void HAL_PWR_EnableSEVOnPend(void);
Kojto 99:dbbf35b96557 332 void HAL_PWR_DisableSEVOnPend(void);
Kojto 99:dbbf35b96557 333 /**
Kojto 99:dbbf35b96557 334 * @}
Kojto 99:dbbf35b96557 335 */
Kojto 99:dbbf35b96557 336
Kojto 99:dbbf35b96557 337 /**
Kojto 99:dbbf35b96557 338 * @}
Kojto 99:dbbf35b96557 339 */
Kojto 99:dbbf35b96557 340
Kojto 99:dbbf35b96557 341 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 342 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 343 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 344 /** @defgroup PWR_Private_Constants PWR Private Constants
Kojto 99:dbbf35b96557 345 * @{
Kojto 99:dbbf35b96557 346 */
Kojto 99:dbbf35b96557 347
Kojto 99:dbbf35b96557 348 /** @defgroup PWR_PVD_EXTI_Line PWR PVD EXTI Line
Kojto 99:dbbf35b96557 349 * @{
Kojto 99:dbbf35b96557 350 */
Kojto 99:dbbf35b96557 351 #define PWR_EXTI_LINE_PVD ((uint32_t)EXTI_IMR_MR16) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
Kojto 99:dbbf35b96557 352 /**
Kojto 99:dbbf35b96557 353 * @}
Kojto 99:dbbf35b96557 354 */
Kojto 99:dbbf35b96557 355
Kojto 99:dbbf35b96557 356 /** @defgroup PWR_register_alias_address PWR Register alias address
Kojto 99:dbbf35b96557 357 * @{
Kojto 99:dbbf35b96557 358 */
Kojto 99:dbbf35b96557 359 /* ------------- PWR registers bit address in the alias region ---------------*/
Kojto 99:dbbf35b96557 360 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
Kojto 99:dbbf35b96557 361 #define PWR_CR_OFFSET 0x00
Kojto 99:dbbf35b96557 362 #define PWR_CSR_OFFSET 0x04
Kojto 99:dbbf35b96557 363 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
Kojto 99:dbbf35b96557 364 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
Kojto 99:dbbf35b96557 365 /**
Kojto 99:dbbf35b96557 366 * @}
Kojto 99:dbbf35b96557 367 */
Kojto 99:dbbf35b96557 368
Kojto 99:dbbf35b96557 369 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
Kojto 99:dbbf35b96557 370 * @{
Kojto 99:dbbf35b96557 371 */
Kojto 99:dbbf35b96557 372 /* --- CR Register ---*/
Kojto 99:dbbf35b96557 373 /* Alias word address of DBP bit */
Kojto 99:dbbf35b96557 374 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
Kojto 99:dbbf35b96557 375 #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 376
Kojto 99:dbbf35b96557 377 /* Alias word address of PVDE bit */
Kojto 99:dbbf35b96557 378 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
Kojto 99:dbbf35b96557 379 #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 380
Kojto 99:dbbf35b96557 381 /* Alias word address of PMODE bit */
Kojto 99:dbbf35b96557 382 #define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE)
Kojto 99:dbbf35b96557 383 #define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PMODE_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 384 /**
Kojto 99:dbbf35b96557 385 * @}
Kojto 99:dbbf35b96557 386 */
Kojto 99:dbbf35b96557 387
Kojto 99:dbbf35b96557 388 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
Kojto 99:dbbf35b96557 389 * @{
Kojto 99:dbbf35b96557 390 */
Kojto 99:dbbf35b96557 391 /* --- CSR Register ---*/
Kojto 99:dbbf35b96557 392 /* Alias word address of EWUP bit */
Kojto 99:dbbf35b96557 393 #define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP)
Kojto 99:dbbf35b96557 394 #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (EWUP_BIT_NUMBER * 4))
Kojto 99:dbbf35b96557 395 /**
Kojto 99:dbbf35b96557 396 * @}
Kojto 99:dbbf35b96557 397 */
Kojto 99:dbbf35b96557 398
Kojto 99:dbbf35b96557 399 /**
Kojto 99:dbbf35b96557 400 * @}
Kojto 99:dbbf35b96557 401 */
Kojto 99:dbbf35b96557 402 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 403 /** @defgroup PWR_Private_Macros PWR Private Macros
Kojto 99:dbbf35b96557 404 * @{
Kojto 99:dbbf35b96557 405 */
Kojto 99:dbbf35b96557 406
Kojto 99:dbbf35b96557 407 /** @defgroup PWR_IS_PWR_Definitions PWR Private macros to check input parameters
Kojto 99:dbbf35b96557 408 * @{
Kojto 99:dbbf35b96557 409 */
Kojto 99:dbbf35b96557 410 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
Kojto 99:dbbf35b96557 411 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
Kojto 99:dbbf35b96557 412 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
Kojto 99:dbbf35b96557 413 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
Kojto 99:dbbf35b96557 414 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
Kojto 99:dbbf35b96557 415 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
Kojto 99:dbbf35b96557 416 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
Kojto 99:dbbf35b96557 417 ((MODE) == PWR_PVD_MODE_NORMAL))
Kojto 99:dbbf35b96557 418 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
Kojto 99:dbbf35b96557 419 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
Kojto 99:dbbf35b96557 420 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
Kojto 99:dbbf35b96557 421 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
Kojto 99:dbbf35b96557 422 /**
Kojto 99:dbbf35b96557 423 * @}
Kojto 99:dbbf35b96557 424 */
Kojto 99:dbbf35b96557 425
Kojto 99:dbbf35b96557 426 /**
Kojto 99:dbbf35b96557 427 * @}
Kojto 99:dbbf35b96557 428 */
emilmont 77:869cf507173a 429
emilmont 77:869cf507173a 430 /**
emilmont 77:869cf507173a 431 * @}
emilmont 77:869cf507173a 432 */
emilmont 77:869cf507173a 433
emilmont 77:869cf507173a 434 /**
emilmont 77:869cf507173a 435 * @}
emilmont 77:869cf507173a 436 */
emilmont 77:869cf507173a 437
emilmont 77:869cf507173a 438 #ifdef __cplusplus
emilmont 77:869cf507173a 439 }
emilmont 77:869cf507173a 440 #endif
emilmont 77:869cf507173a 441
emilmont 77:869cf507173a 442
emilmont 77:869cf507173a 443 #endif /* __STM32F4xx_HAL_PWR_H */
emilmont 77:869cf507173a 444
emilmont 77:869cf507173a 445 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/