meh

Fork of mbed by mbed official

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
106:ba1f97679dad
Release 110  of the mbed library

Changes:
- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI
- Nucleo L476 - gcc and uvision template
- k22,k64f targets - ADC channels A addition
- EFM32 - bugfixes in sleep, serial and spi
- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_dma2d.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 110:165afa46840b 5 * @version V1.4.1
Kojto 110:165afa46840b 6 * @date 09-October-2015
emilmont 77:869cf507173a 7 * @brief Header file of DMA2D HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
Kojto 99:dbbf35b96557 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_DMA2D_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_DMA2D_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
Kojto 110:165afa46840b 46 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
Kojto 110:165afa46840b 47 defined(STM32F469xx) || defined(STM32F479xx)
emilmont 77:869cf507173a 48 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 49 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 52 * @{
emilmont 77:869cf507173a 53 */
emilmont 77:869cf507173a 54
Kojto 99:dbbf35b96557 55 /** @defgroup DMA2D DMA2D
Kojto 99:dbbf35b96557 56 * @brief DMA2D HAL module driver
emilmont 77:869cf507173a 57 * @{
Kojto 99:dbbf35b96557 58 */
Kojto 99:dbbf35b96557 59
emilmont 77:869cf507173a 60 /* Exported types ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 61 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
Kojto 99:dbbf35b96557 62 * @{
Kojto 99:dbbf35b96557 63 */
emilmont 77:869cf507173a 64 #define MAX_DMA2D_LAYER 2
bogdanm 85:024bf7f99721 65
emilmont 77:869cf507173a 66 /**
bogdanm 85:024bf7f99721 67 * @brief DMA2D color Structure definition
emilmont 77:869cf507173a 68 */
emilmont 77:869cf507173a 69 typedef struct
emilmont 77:869cf507173a 70 {
emilmont 77:869cf507173a 71 uint32_t Blue; /*!< Configures the blue value.
emilmont 77:869cf507173a 72 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
emilmont 77:869cf507173a 73
bogdanm 85:024bf7f99721 74 uint32_t Green; /*!< Configures the green value.
emilmont 77:869cf507173a 75 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
bogdanm 85:024bf7f99721 76
bogdanm 85:024bf7f99721 77 uint32_t Red; /*!< Configures the red value.
emilmont 77:869cf507173a 78 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
emilmont 77:869cf507173a 79 } DMA2D_ColorTypeDef;
emilmont 77:869cf507173a 80
emilmont 77:869cf507173a 81 /**
bogdanm 85:024bf7f99721 82 * @brief DMA2D CLUT Structure definition
emilmont 77:869cf507173a 83 */
emilmont 77:869cf507173a 84 typedef struct
emilmont 77:869cf507173a 85 {
bogdanm 85:024bf7f99721 86 uint32_t *pCLUT; /*!< Configures the DMA2D CLUT memory address.*/
emilmont 77:869cf507173a 87
bogdanm 85:024bf7f99721 88 uint32_t CLUTColorMode; /*!< configures the DMA2D CLUT color mode.
emilmont 77:869cf507173a 89 This parameter can be one value of @ref DMA2D_CLUT_CM */
bogdanm 85:024bf7f99721 90
emilmont 77:869cf507173a 91 uint32_t Size; /*!< configures the DMA2D CLUT size.
bogdanm 85:024bf7f99721 92 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
emilmont 77:869cf507173a 93 } DMA2D_CLUTCfgTypeDef;
emilmont 77:869cf507173a 94
emilmont 77:869cf507173a 95 /**
bogdanm 85:024bf7f99721 96 * @brief DMA2D Init structure definition
emilmont 77:869cf507173a 97 */
emilmont 77:869cf507173a 98 typedef struct
emilmont 77:869cf507173a 99 {
emilmont 77:869cf507173a 100 uint32_t Mode; /*!< configures the DMA2D transfer mode.
emilmont 77:869cf507173a 101 This parameter can be one value of @ref DMA2D_Mode */
bogdanm 85:024bf7f99721 102
emilmont 77:869cf507173a 103 uint32_t ColorMode; /*!< configures the color format of the output image.
emilmont 77:869cf507173a 104 This parameter can be one value of @ref DMA2D_Color_Mode */
emilmont 77:869cf507173a 105
emilmont 77:869cf507173a 106 uint32_t OutputOffset; /*!< Specifies the Offset value.
emilmont 77:869cf507173a 107 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
emilmont 77:869cf507173a 108 } DMA2D_InitTypeDef;
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 /**
bogdanm 85:024bf7f99721 111 * @brief DMA2D Layer structure definition
emilmont 77:869cf507173a 112 */
emilmont 77:869cf507173a 113 typedef struct
emilmont 77:869cf507173a 114 {
emilmont 77:869cf507173a 115 uint32_t InputOffset; /*!< configures the DMA2D foreground offset.
emilmont 77:869cf507173a 116 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
emilmont 77:869cf507173a 117
emilmont 77:869cf507173a 118 uint32_t InputColorMode; /*!< configures the DMA2D foreground color mode .
emilmont 77:869cf507173a 119 This parameter can be one value of @ref DMA2D_Input_Color_Mode */
bogdanm 85:024bf7f99721 120
emilmont 77:869cf507173a 121 uint32_t AlphaMode; /*!< configures the DMA2D foreground alpha mode.
emilmont 77:869cf507173a 122 This parameter can be one value of @ref DMA2D_ALPHA_MODE */
emilmont 77:869cf507173a 123
Kojto 90:cb3d968589d8 124 uint32_t InputAlpha; /*!< Specifies the DMA2D foreground alpha value and color value in case of A8 or A4 color mode.
Kojto 90:cb3d968589d8 125 This parameter must be a number between Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF
Kojto 90:cb3d968589d8 126 in case of A8 or A4 color mode (ARGB).
Kojto 90:cb3d968589d8 127 Otherwise, This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
bogdanm 85:024bf7f99721 128
emilmont 77:869cf507173a 129 } DMA2D_LayerCfgTypeDef;
emilmont 77:869cf507173a 130
emilmont 77:869cf507173a 131 /**
bogdanm 85:024bf7f99721 132 * @brief HAL DMA2D State structures definition
bogdanm 85:024bf7f99721 133 */
emilmont 77:869cf507173a 134 typedef enum
emilmont 77:869cf507173a 135 {
emilmont 77:869cf507173a 136 HAL_DMA2D_STATE_RESET = 0x00, /*!< DMA2D not yet initialized or disabled */
emilmont 77:869cf507173a 137 HAL_DMA2D_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
bogdanm 85:024bf7f99721 138 HAL_DMA2D_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
bogdanm 85:024bf7f99721 139 HAL_DMA2D_STATE_TIMEOUT = 0x03, /*!< Timeout state */
emilmont 77:869cf507173a 140 HAL_DMA2D_STATE_ERROR = 0x04, /*!< DMA2D state error */
emilmont 77:869cf507173a 141 HAL_DMA2D_STATE_SUSPEND = 0x05 /*!< DMA2D process is suspended */
emilmont 77:869cf507173a 142 }HAL_DMA2D_StateTypeDef;
emilmont 77:869cf507173a 143
emilmont 77:869cf507173a 144 /**
bogdanm 85:024bf7f99721 145 * @brief DMA2D handle Structure definition
bogdanm 85:024bf7f99721 146 */
emilmont 77:869cf507173a 147 typedef struct __DMA2D_HandleTypeDef
bogdanm 85:024bf7f99721 148 {
emilmont 77:869cf507173a 149 DMA2D_TypeDef *Instance; /*!< DMA2D Register base address */
bogdanm 85:024bf7f99721 150
emilmont 77:869cf507173a 151 DMA2D_InitTypeDef Init; /*!< DMA2D communication parameters */
bogdanm 85:024bf7f99721 152
emilmont 77:869cf507173a 153 void (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer complete callback */
bogdanm 85:024bf7f99721 154
emilmont 77:869cf507173a 155 void (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback */
bogdanm 85:024bf7f99721 156
emilmont 77:869cf507173a 157 DMA2D_LayerCfgTypeDef LayerCfg[MAX_DMA2D_LAYER]; /*!< DMA2D Layers parameters */
bogdanm 85:024bf7f99721 158
emilmont 77:869cf507173a 159 HAL_LockTypeDef Lock; /*!< DMA2D Lock */
bogdanm 85:024bf7f99721 160
emilmont 77:869cf507173a 161 __IO HAL_DMA2D_StateTypeDef State; /*!< DMA2D transfer state */
bogdanm 85:024bf7f99721 162
emilmont 77:869cf507173a 163 __IO uint32_t ErrorCode; /*!< DMA2D Error code */
bogdanm 85:024bf7f99721 164 } DMA2D_HandleTypeDef;
emilmont 77:869cf507173a 165 /**
emilmont 77:869cf507173a 166 * @}
emilmont 77:869cf507173a 167 */
emilmont 77:869cf507173a 168
Kojto 99:dbbf35b96557 169 /* Exported constants --------------------------------------------------------*/
Kojto 99:dbbf35b96557 170 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
Kojto 99:dbbf35b96557 171 * @{
Kojto 99:dbbf35b96557 172 */
Kojto 99:dbbf35b96557 173
Kojto 99:dbbf35b96557 174 /** @defgroup DMA2D_Error_Code DMA2D Error Code
emilmont 77:869cf507173a 175 * @{
emilmont 77:869cf507173a 176 */
emilmont 77:869cf507173a 177 #define HAL_DMA2D_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
emilmont 77:869cf507173a 178 #define HAL_DMA2D_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 85:024bf7f99721 179 #define HAL_DMA2D_ERROR_CE ((uint32_t)0x00000002) /*!< Configuration error */
emilmont 77:869cf507173a 180 #define HAL_DMA2D_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
emilmont 77:869cf507173a 181 /**
emilmont 77:869cf507173a 182 * @}
emilmont 77:869cf507173a 183 */
bogdanm 85:024bf7f99721 184
Kojto 99:dbbf35b96557 185 /** @defgroup DMA2D_Mode DMA2D Mode
emilmont 77:869cf507173a 186 * @{
emilmont 77:869cf507173a 187 */
emilmont 77:869cf507173a 188 #define DMA2D_M2M ((uint32_t)0x00000000) /*!< DMA2D memory to memory transfer mode */
emilmont 77:869cf507173a 189 #define DMA2D_M2M_PFC ((uint32_t)0x00010000) /*!< DMA2D memory to memory with pixel format conversion transfer mode */
emilmont 77:869cf507173a 190 #define DMA2D_M2M_BLEND ((uint32_t)0x00020000) /*!< DMA2D memory to memory with blending transfer mode */
emilmont 77:869cf507173a 191 #define DMA2D_R2M ((uint32_t)0x00030000) /*!< DMA2D register to memory transfer mode */
emilmont 77:869cf507173a 192 /**
emilmont 77:869cf507173a 193 * @}
bogdanm 85:024bf7f99721 194 */
emilmont 77:869cf507173a 195
Kojto 99:dbbf35b96557 196 /** @defgroup DMA2D_Color_Mode DMA2D Color Mode
emilmont 77:869cf507173a 197 * @{
emilmont 77:869cf507173a 198 */
emilmont 77:869cf507173a 199 #define DMA2D_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D color mode */
emilmont 77:869cf507173a 200 #define DMA2D_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D color mode */
emilmont 77:869cf507173a 201 #define DMA2D_RGB565 ((uint32_t)0x00000002) /*!< RGB565 DMA2D color mode */
emilmont 77:869cf507173a 202 #define DMA2D_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 DMA2D color mode */
emilmont 77:869cf507173a 203 #define DMA2D_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 DMA2D color mode */
emilmont 77:869cf507173a 204 /**
emilmont 77:869cf507173a 205 * @}
emilmont 77:869cf507173a 206 */
emilmont 77:869cf507173a 207
Kojto 99:dbbf35b96557 208 /** @defgroup DMA2D_COLOR_VALUE DMA2D COLOR VALUE
emilmont 77:869cf507173a 209 * @{
emilmont 77:869cf507173a 210 */
emilmont 77:869cf507173a 211 #define COLOR_VALUE ((uint32_t)0x000000FF) /*!< color value mask */
emilmont 77:869cf507173a 212 /**
emilmont 77:869cf507173a 213 * @}
emilmont 77:869cf507173a 214 */
emilmont 77:869cf507173a 215
Kojto 99:dbbf35b96557 216 /** @defgroup DMA2D_SIZE DMA2D SIZE
emilmont 77:869cf507173a 217 * @{
emilmont 77:869cf507173a 218 */
emilmont 77:869cf507173a 219 #define DMA2D_PIXEL (DMA2D_NLR_PL >> 16) /*!< DMA2D pixel per line */
emilmont 77:869cf507173a 220 #define DMA2D_LINE DMA2D_NLR_NL /*!< DMA2D number of line */
emilmont 77:869cf507173a 221 /**
emilmont 77:869cf507173a 222 * @}
emilmont 77:869cf507173a 223 */
emilmont 77:869cf507173a 224
Kojto 99:dbbf35b96557 225 /** @defgroup DMA2D_Offset DMA2D Offset
emilmont 77:869cf507173a 226 * @{
emilmont 77:869cf507173a 227 */
emilmont 77:869cf507173a 228 #define DMA2D_OFFSET DMA2D_FGOR_LO /*!< Line Offset */
emilmont 77:869cf507173a 229 /**
emilmont 77:869cf507173a 230 * @}
emilmont 77:869cf507173a 231 */
emilmont 77:869cf507173a 232
Kojto 99:dbbf35b96557 233 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
emilmont 77:869cf507173a 234 * @{
emilmont 77:869cf507173a 235 */
emilmont 77:869cf507173a 236 #define CM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 color mode */
emilmont 77:869cf507173a 237 #define CM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 color mode */
emilmont 77:869cf507173a 238 #define CM_RGB565 ((uint32_t)0x00000002) /*!< RGB565 color mode */
emilmont 77:869cf507173a 239 #define CM_ARGB1555 ((uint32_t)0x00000003) /*!< ARGB1555 color mode */
emilmont 77:869cf507173a 240 #define CM_ARGB4444 ((uint32_t)0x00000004) /*!< ARGB4444 color mode */
emilmont 77:869cf507173a 241 #define CM_L8 ((uint32_t)0x00000005) /*!< L8 color mode */
emilmont 77:869cf507173a 242 #define CM_AL44 ((uint32_t)0x00000006) /*!< AL44 color mode */
emilmont 77:869cf507173a 243 #define CM_AL88 ((uint32_t)0x00000007) /*!< AL88 color mode */
emilmont 77:869cf507173a 244 #define CM_L4 ((uint32_t)0x00000008) /*!< L4 color mode */
emilmont 77:869cf507173a 245 #define CM_A8 ((uint32_t)0x00000009) /*!< A8 color mode */
emilmont 77:869cf507173a 246 #define CM_A4 ((uint32_t)0x0000000A) /*!< A4 color mode */
emilmont 77:869cf507173a 247 /**
emilmont 77:869cf507173a 248 * @}
emilmont 77:869cf507173a 249 */
emilmont 77:869cf507173a 250
Kojto 99:dbbf35b96557 251 /** @defgroup DMA2D_ALPHA_MODE DMA2D ALPHA MODE
emilmont 77:869cf507173a 252 * @{
emilmont 77:869cf507173a 253 */
emilmont 77:869cf507173a 254 #define DMA2D_NO_MODIF_ALPHA ((uint32_t)0x00000000) /*!< No modification of the alpha channel value */
emilmont 77:869cf507173a 255 #define DMA2D_REPLACE_ALPHA ((uint32_t)0x00000001) /*!< Replace original alpha channel value by programmed alpha value */
emilmont 77:869cf507173a 256 #define DMA2D_COMBINE_ALPHA ((uint32_t)0x00000002) /*!< Replace original alpha channel value by programmed alpha value
emilmont 77:869cf507173a 257 with original alpha channel value */
emilmont 77:869cf507173a 258 /**
emilmont 77:869cf507173a 259 * @}
emilmont 77:869cf507173a 260 */
emilmont 77:869cf507173a 261
Kojto 99:dbbf35b96557 262 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT CM
emilmont 77:869cf507173a 263 * @{
emilmont 77:869cf507173a 264 */
emilmont 77:869cf507173a 265 #define DMA2D_CCM_ARGB8888 ((uint32_t)0x00000000) /*!< ARGB8888 DMA2D C-LUT color mode */
emilmont 77:869cf507173a 266 #define DMA2D_CCM_RGB888 ((uint32_t)0x00000001) /*!< RGB888 DMA2D C-LUT color mode */
emilmont 77:869cf507173a 267 /**
emilmont 77:869cf507173a 268 * @}
emilmont 77:869cf507173a 269 */
emilmont 77:869cf507173a 270
Kojto 99:dbbf35b96557 271 /** @defgroup DMA2D_Size_Clut DMA2D Size Clut
emilmont 77:869cf507173a 272 * @{
emilmont 77:869cf507173a 273 */
emilmont 77:869cf507173a 274 #define DMA2D_CLUT_SIZE (DMA2D_FGPFCCR_CS >> 8) /*!< DMA2D C-LUT size */
emilmont 77:869cf507173a 275 /**
emilmont 77:869cf507173a 276 * @}
emilmont 77:869cf507173a 277 */
emilmont 77:869cf507173a 278
Kojto 99:dbbf35b96557 279 /** @defgroup DMA2D_DeadTime DMA2D DeadTime
emilmont 77:869cf507173a 280 * @{
emilmont 77:869cf507173a 281 */
emilmont 77:869cf507173a 282 #define LINE_WATERMARK DMA2D_LWR_LW
emilmont 77:869cf507173a 283 /**
emilmont 77:869cf507173a 284 * @}
bogdanm 85:024bf7f99721 285 */
bogdanm 85:024bf7f99721 286
Kojto 99:dbbf35b96557 287 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
emilmont 77:869cf507173a 288 * @{
emilmont 77:869cf507173a 289 */
emilmont 77:869cf507173a 290 #define DMA2D_IT_CE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
emilmont 77:869cf507173a 291 #define DMA2D_IT_CTC DMA2D_CR_CTCIE /*!< C-LUT Transfer Complete Interrupt */
emilmont 77:869cf507173a 292 #define DMA2D_IT_CAE DMA2D_CR_CAEIE /*!< C-LUT Access Error Interrupt */
emilmont 77:869cf507173a 293 #define DMA2D_IT_TW DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
emilmont 77:869cf507173a 294 #define DMA2D_IT_TC DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
emilmont 77:869cf507173a 295 #define DMA2D_IT_TE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
emilmont 77:869cf507173a 296 /**
emilmont 77:869cf507173a 297 * @}
emilmont 77:869cf507173a 298 */
bogdanm 85:024bf7f99721 299
Kojto 99:dbbf35b96557 300 /** @defgroup DMA2D_Flag DMA2D Flag
emilmont 77:869cf507173a 301 * @{
emilmont 77:869cf507173a 302 */
emilmont 77:869cf507173a 303 #define DMA2D_FLAG_CE DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
emilmont 77:869cf507173a 304 #define DMA2D_FLAG_CTC DMA2D_ISR_CTCIF /*!< C-LUT Transfer Complete Interrupt Flag */
emilmont 77:869cf507173a 305 #define DMA2D_FLAG_CAE DMA2D_ISR_CAEIF /*!< C-LUT Access Error Interrupt Flag */
emilmont 77:869cf507173a 306 #define DMA2D_FLAG_TW DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
emilmont 77:869cf507173a 307 #define DMA2D_FLAG_TC DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
emilmont 77:869cf507173a 308 #define DMA2D_FLAG_TE DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
emilmont 77:869cf507173a 309 /**
emilmont 77:869cf507173a 310 * @}
emilmont 77:869cf507173a 311 */
emilmont 77:869cf507173a 312
emilmont 77:869cf507173a 313 /**
emilmont 77:869cf507173a 314 * @}
emilmont 77:869cf507173a 315 */
emilmont 77:869cf507173a 316 /* Exported macro ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 317 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
Kojto 99:dbbf35b96557 318 * @{
Kojto 99:dbbf35b96557 319 */
bogdanm 85:024bf7f99721 320
bogdanm 85:024bf7f99721 321 /** @brief Reset DMA2D handle state
bogdanm 85:024bf7f99721 322 * @param __HANDLE__: specifies the DMA2D handle.
bogdanm 85:024bf7f99721 323 * @retval None
bogdanm 85:024bf7f99721 324 */
bogdanm 85:024bf7f99721 325 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
bogdanm 85:024bf7f99721 326
emilmont 77:869cf507173a 327 /**
emilmont 77:869cf507173a 328 * @brief Enable the DMA2D.
emilmont 77:869cf507173a 329 * @param __HANDLE__: DMA2D handle
emilmont 77:869cf507173a 330 * @retval None.
emilmont 77:869cf507173a 331 */
emilmont 77:869cf507173a 332 #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
emilmont 77:869cf507173a 333
emilmont 77:869cf507173a 334 /**
emilmont 77:869cf507173a 335 * @brief Disable the DMA2D.
emilmont 77:869cf507173a 336 * @param __HANDLE__: DMA2D handle
emilmont 77:869cf507173a 337 * @retval None.
emilmont 77:869cf507173a 338 */
emilmont 77:869cf507173a 339 #define __HAL_DMA2D_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA2D_CR_START)
emilmont 77:869cf507173a 340
emilmont 77:869cf507173a 341 /* Interrupt & Flag management */
emilmont 77:869cf507173a 342 /**
emilmont 77:869cf507173a 343 * @brief Get the DMA2D pending flags.
emilmont 77:869cf507173a 344 * @param __HANDLE__: DMA2D handle
emilmont 77:869cf507173a 345 * @param __FLAG__: Get the specified flag.
emilmont 77:869cf507173a 346 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 347 * @arg DMA2D_FLAG_CE: Configuration error flag
emilmont 77:869cf507173a 348 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
emilmont 77:869cf507173a 349 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
emilmont 77:869cf507173a 350 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
emilmont 77:869cf507173a 351 * @arg DMA2D_FLAG_TC: Transfer complete flag
emilmont 77:869cf507173a 352 * @arg DMA2D_FLAG_TE: Transfer error flag
emilmont 77:869cf507173a 353 * @retval The state of FLAG.
emilmont 77:869cf507173a 354 */
emilmont 77:869cf507173a 355 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
emilmont 77:869cf507173a 356
emilmont 77:869cf507173a 357 /**
emilmont 77:869cf507173a 358 * @brief Clears the DMA2D pending flags.
emilmont 77:869cf507173a 359 * @param __HANDLE__: DMA2D handle
emilmont 77:869cf507173a 360 * @param __FLAG__: specifies the flag to clear.
emilmont 77:869cf507173a 361 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 362 * @arg DMA2D_FLAG_CE: Configuration error flag
emilmont 77:869cf507173a 363 * @arg DMA2D_FLAG_CTC: C-LUT transfer complete flag
emilmont 77:869cf507173a 364 * @arg DMA2D_FLAG_CAE: C-LUT access error flag
emilmont 77:869cf507173a 365 * @arg DMA2D_FLAG_TW: Transfer Watermark flag
emilmont 77:869cf507173a 366 * @arg DMA2D_FLAG_TC: Transfer complete flag
emilmont 77:869cf507173a 367 * @arg DMA2D_FLAG_TE: Transfer error flag
emilmont 77:869cf507173a 368 * @retval None
emilmont 77:869cf507173a 369 */
Kojto 90:cb3d968589d8 370 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
emilmont 77:869cf507173a 371
emilmont 77:869cf507173a 372 /**
emilmont 77:869cf507173a 373 * @brief Enables the specified DMA2D interrupts.
emilmont 77:869cf507173a 374 * @param __HANDLE__: DMA2D handle
emilmont 77:869cf507173a 375 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
emilmont 77:869cf507173a 376 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 377 * @arg DMA2D_IT_CE: Configuration error interrupt mask
emilmont 77:869cf507173a 378 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
emilmont 77:869cf507173a 379 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
emilmont 77:869cf507173a 380 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
emilmont 77:869cf507173a 381 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
emilmont 77:869cf507173a 382 * @arg DMA2D_IT_TE: Transfer error interrupt mask
emilmont 77:869cf507173a 383 * @retval None
emilmont 77:869cf507173a 384 */
emilmont 77:869cf507173a 385 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
emilmont 77:869cf507173a 386
emilmont 77:869cf507173a 387 /**
emilmont 77:869cf507173a 388 * @brief Disables the specified DMA2D interrupts.
emilmont 77:869cf507173a 389 * @param __HANDLE__: DMA2D handle
emilmont 77:869cf507173a 390 * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
emilmont 77:869cf507173a 391 * This parameter can be any combination of the following values:
emilmont 77:869cf507173a 392 * @arg DMA2D_IT_CE: Configuration error interrupt mask
emilmont 77:869cf507173a 393 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
emilmont 77:869cf507173a 394 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
emilmont 77:869cf507173a 395 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
emilmont 77:869cf507173a 396 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
emilmont 77:869cf507173a 397 * @arg DMA2D_IT_TE: Transfer error interrupt mask
emilmont 77:869cf507173a 398 * @retval None
emilmont 77:869cf507173a 399 */
emilmont 77:869cf507173a 400 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
emilmont 77:869cf507173a 401
emilmont 77:869cf507173a 402 /**
emilmont 77:869cf507173a 403 * @brief Checks whether the specified DMA2D interrupt has occurred or not.
emilmont 77:869cf507173a 404 * @param __HANDLE__: DMA2D handle
emilmont 77:869cf507173a 405 * @param __INTERRUPT__: specifies the DMA2D interrupt source to check.
emilmont 77:869cf507173a 406 * This parameter can be one of the following values:
emilmont 77:869cf507173a 407 * @arg DMA2D_IT_CE: Configuration error interrupt mask
emilmont 77:869cf507173a 408 * @arg DMA2D_IT_CTC: C-LUT transfer complete interrupt mask
emilmont 77:869cf507173a 409 * @arg DMA2D_IT_CAE: C-LUT access error interrupt mask
emilmont 77:869cf507173a 410 * @arg DMA2D_IT_TW: Transfer Watermark interrupt mask
emilmont 77:869cf507173a 411 * @arg DMA2D_IT_TC: Transfer complete interrupt mask
emilmont 77:869cf507173a 412 * @arg DMA2D_IT_TE: Transfer error interrupt mask
emilmont 77:869cf507173a 413 * @retval The state of INTERRUPT.
emilmont 77:869cf507173a 414 */
bogdanm 81:7d30d6019079 415 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
Kojto 99:dbbf35b96557 416 /**
Kojto 99:dbbf35b96557 417 * @}
Kojto 99:dbbf35b96557 418 */
emilmont 77:869cf507173a 419
emilmont 77:869cf507173a 420 /* Exported functions --------------------------------------------------------*/
Kojto 99:dbbf35b96557 421 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
Kojto 99:dbbf35b96557 422 * @{
Kojto 99:dbbf35b96557 423 */
emilmont 77:869cf507173a 424 /* Initialization and de-initialization functions *******************************/
emilmont 77:869cf507173a 425 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
emilmont 77:869cf507173a 426 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
bogdanm 81:7d30d6019079 427 void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
bogdanm 81:7d30d6019079 428 void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
emilmont 77:869cf507173a 429
emilmont 77:869cf507173a 430 /* IO operation functions *******************************************************/
Kojto 99:dbbf35b96557 431 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
Kojto 99:dbbf35b96557 432 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
Kojto 99:dbbf35b96557 433 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
Kojto 99:dbbf35b96557 434 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
emilmont 77:869cf507173a 435 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
emilmont 77:869cf507173a 436 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
emilmont 77:869cf507173a 437 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
emilmont 77:869cf507173a 438 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
emilmont 77:869cf507173a 439 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
emilmont 77:869cf507173a 440
emilmont 77:869cf507173a 441 /* Peripheral Control functions *************************************************/
emilmont 77:869cf507173a 442 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
emilmont 77:869cf507173a 443 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
emilmont 77:869cf507173a 444 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
emilmont 77:869cf507173a 445 HAL_StatusTypeDef HAL_DMA2D_DisableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
emilmont 77:869cf507173a 446 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
emilmont 77:869cf507173a 447
emilmont 77:869cf507173a 448 /* Peripheral State functions ***************************************************/
emilmont 77:869cf507173a 449 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
emilmont 77:869cf507173a 450 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
Kojto 99:dbbf35b96557 451 /**
Kojto 99:dbbf35b96557 452 * @}
Kojto 99:dbbf35b96557 453 */
emilmont 77:869cf507173a 454
Kojto 99:dbbf35b96557 455 /* Private types -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 456 /** @defgroup DMA2D_Private_Types DMA2D Private Types
Kojto 99:dbbf35b96557 457 * @{
Kojto 99:dbbf35b96557 458 */
Kojto 99:dbbf35b96557 459
Kojto 99:dbbf35b96557 460 /**
Kojto 99:dbbf35b96557 461 * @}
Kojto 99:dbbf35b96557 462 */
Kojto 99:dbbf35b96557 463
Kojto 99:dbbf35b96557 464 /* Private defines -------------------------------------------------------------*/
Kojto 99:dbbf35b96557 465 /** @defgroup DMA2D_Private_Defines DMA2D Private Defines
Kojto 99:dbbf35b96557 466 * @{
Kojto 99:dbbf35b96557 467 */
Kojto 99:dbbf35b96557 468
Kojto 99:dbbf35b96557 469 /**
Kojto 99:dbbf35b96557 470 * @}
Kojto 99:dbbf35b96557 471 */
Kojto 99:dbbf35b96557 472
Kojto 99:dbbf35b96557 473 /* Private variables ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 474 /** @defgroup DMA2D_Private_Variables DMA2D Private Variables
Kojto 99:dbbf35b96557 475 * @{
Kojto 99:dbbf35b96557 476 */
Kojto 99:dbbf35b96557 477
Kojto 99:dbbf35b96557 478 /**
Kojto 99:dbbf35b96557 479 * @}
Kojto 99:dbbf35b96557 480 */
Kojto 99:dbbf35b96557 481
Kojto 99:dbbf35b96557 482 /* Private constants ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 483 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
Kojto 99:dbbf35b96557 484 * @{
Kojto 99:dbbf35b96557 485 */
Kojto 99:dbbf35b96557 486
Kojto 99:dbbf35b96557 487 /**
Kojto 99:dbbf35b96557 488 * @}
Kojto 99:dbbf35b96557 489 */
Kojto 99:dbbf35b96557 490
Kojto 99:dbbf35b96557 491 /* Private macros ------------------------------------------------------------*/
Kojto 99:dbbf35b96557 492 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
Kojto 99:dbbf35b96557 493 * @{
Kojto 99:dbbf35b96557 494 */
Kojto 99:dbbf35b96557 495 #define IS_DMA2D_LAYER(LAYER) ((LAYER) <= MAX_DMA2D_LAYER)
Kojto 99:dbbf35b96557 496 #define IS_DMA2D_MODE(MODE) (((MODE) == DMA2D_M2M) || ((MODE) == DMA2D_M2M_PFC) || \
Kojto 99:dbbf35b96557 497 ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
Kojto 99:dbbf35b96557 498 #define IS_DMA2D_CMODE(MODE_ARGB) (((MODE_ARGB) == DMA2D_ARGB8888) || ((MODE_ARGB) == DMA2D_RGB888) || \
Kojto 99:dbbf35b96557 499 ((MODE_ARGB) == DMA2D_RGB565) || ((MODE_ARGB) == DMA2D_ARGB1555) || \
Kojto 99:dbbf35b96557 500 ((MODE_ARGB) == DMA2D_ARGB4444))
Kojto 99:dbbf35b96557 501 #define IS_DMA2D_COLOR(COLOR) ((COLOR) <= COLOR_VALUE)
Kojto 99:dbbf35b96557 502 #define IS_DMA2D_LINE(LINE) ((LINE) <= DMA2D_LINE)
Kojto 99:dbbf35b96557 503 #define IS_DMA2D_PIXEL(PIXEL) ((PIXEL) <= DMA2D_PIXEL)
Kojto 99:dbbf35b96557 504 #define IS_DMA2D_OFFSET(OOFFSET) ((OOFFSET) <= DMA2D_OFFSET)
Kojto 99:dbbf35b96557 505 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM) (((INPUT_CM) == CM_ARGB8888) || ((INPUT_CM) == CM_RGB888) || \
Kojto 99:dbbf35b96557 506 ((INPUT_CM) == CM_RGB565) || ((INPUT_CM) == CM_ARGB1555) || \
Kojto 99:dbbf35b96557 507 ((INPUT_CM) == CM_ARGB4444) || ((INPUT_CM) == CM_L8) || \
Kojto 99:dbbf35b96557 508 ((INPUT_CM) == CM_AL44) || ((INPUT_CM) == CM_AL88) || \
Kojto 99:dbbf35b96557 509 ((INPUT_CM) == CM_L4) || ((INPUT_CM) == CM_A8) || \
Kojto 99:dbbf35b96557 510 ((INPUT_CM) == CM_A4))
Kojto 99:dbbf35b96557 511 #define IS_DMA2D_ALPHA_MODE(AlphaMode) (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
Kojto 99:dbbf35b96557 512 ((AlphaMode) == DMA2D_REPLACE_ALPHA) || \
Kojto 99:dbbf35b96557 513 ((AlphaMode) == DMA2D_COMBINE_ALPHA))
Kojto 99:dbbf35b96557 514 #define IS_DMA2D_CLUT_CM(CLUT_CM) (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
Kojto 99:dbbf35b96557 515 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE) ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
Kojto 99:dbbf35b96557 516 #define IS_DMA2D_LineWatermark(LineWatermark) ((LineWatermark) <= LINE_WATERMARK)
Kojto 99:dbbf35b96557 517 /**
Kojto 99:dbbf35b96557 518 * @}
Kojto 99:dbbf35b96557 519 */
Kojto 99:dbbf35b96557 520
Kojto 99:dbbf35b96557 521 /* Private functions prototypes ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 522 /** @defgroup DMA2D_Private_Functions_Prototypes DMA2D Private Functions Prototypes
Kojto 99:dbbf35b96557 523 * @{
Kojto 99:dbbf35b96557 524 */
Kojto 99:dbbf35b96557 525
Kojto 99:dbbf35b96557 526 /**
Kojto 99:dbbf35b96557 527 * @}
Kojto 99:dbbf35b96557 528 */
Kojto 99:dbbf35b96557 529
Kojto 99:dbbf35b96557 530 /* Private functions ---------------------------------------------------------*/
Kojto 99:dbbf35b96557 531 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
Kojto 99:dbbf35b96557 532 * @{
Kojto 99:dbbf35b96557 533 */
Kojto 99:dbbf35b96557 534
Kojto 99:dbbf35b96557 535 /**
Kojto 99:dbbf35b96557 536 * @}
Kojto 99:dbbf35b96557 537 */
emilmont 77:869cf507173a 538
emilmont 77:869cf507173a 539 /**
emilmont 77:869cf507173a 540 * @}
emilmont 77:869cf507173a 541 */
emilmont 77:869cf507173a 542
emilmont 77:869cf507173a 543 /**
emilmont 77:869cf507173a 544 * @}
emilmont 77:869cf507173a 545 */
Kojto 99:dbbf35b96557 546
Kojto 110:165afa46840b 547 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
Kojto 99:dbbf35b96557 548
emilmont 77:869cf507173a 549 #ifdef __cplusplus
emilmont 77:869cf507173a 550 }
emilmont 77:869cf507173a 551 #endif
emilmont 77:869cf507173a 552
emilmont 77:869cf507173a 553 #endif /* __STM32F4xx_HAL_DMA2D_H */
emilmont 77:869cf507173a 554
emilmont 77:869cf507173a 555 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/