Ricardo Benitez / mbed

meh

Fork of mbed by mbed official

TARGET_NRF51822/core_cm0.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
80:8e73be2a2ac1 
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 80:8e73be2a2ac1 1 /**************************************************************************//**
emilmont 80:8e73be2a2ac1 2 * @file core_cm0.h
emilmont 80:8e73be2a2ac1 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
emilmont 80:8e73be2a2ac1 6 *
emilmont 80:8e73be2a2ac1 7 * @note
emilmont 80:8e73be2a2ac1 8 *
emilmont 80:8e73be2a2ac1 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
emilmont 80:8e73be2a2ac1 11
emilmont 80:8e73be2a2ac1 12 All rights reserved.
emilmont 80:8e73be2a2ac1 13 Redistribution and use in source and binary forms, with or without
emilmont 80:8e73be2a2ac1 14 modification, are permitted provided that the following conditions are met:
emilmont 80:8e73be2a2ac1 15 - Redistributions of source code must retain the above copyright
emilmont 80:8e73be2a2ac1 16 notice, this list of conditions and the following disclaimer.
emilmont 80:8e73be2a2ac1 17 - Redistributions in binary form must reproduce the above copyright
emilmont 80:8e73be2a2ac1 18 notice, this list of conditions and the following disclaimer in the
emilmont 80:8e73be2a2ac1 19 documentation and/or other materials provided with the distribution.
emilmont 80:8e73be2a2ac1 20 - Neither the name of ARM nor the names of its contributors may be used
emilmont 80:8e73be2a2ac1 21 to endorse or promote products derived from this software without
emilmont 80:8e73be2a2ac1 22 specific prior written permission.
emilmont 80:8e73be2a2ac1 23 *
emilmont 80:8e73be2a2ac1 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 80:8e73be2a2ac1 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 80:8e73be2a2ac1 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
emilmont 80:8e73be2a2ac1 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
emilmont 80:8e73be2a2ac1 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
emilmont 80:8e73be2a2ac1 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
emilmont 80:8e73be2a2ac1 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
emilmont 80:8e73be2a2ac1 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
emilmont 80:8e73be2a2ac1 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
emilmont 80:8e73be2a2ac1 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
emilmont 80:8e73be2a2ac1 34 POSSIBILITY OF SUCH DAMAGE.
emilmont 80:8e73be2a2ac1 35 ---------------------------------------------------------------------------*/
emilmont 80:8e73be2a2ac1 36
emilmont 80:8e73be2a2ac1 37
emilmont 80:8e73be2a2ac1 38 #if defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 39 #pragma system_include /* treat file as system include file for MISRA check */
emilmont 80:8e73be2a2ac1 40 #endif
emilmont 80:8e73be2a2ac1 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
emilmont 80:8e73be2a2ac1 45 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 46 extern "C" {
emilmont 80:8e73be2a2ac1 47 #endif
emilmont 80:8e73be2a2ac1 48
emilmont 80:8e73be2a2ac1 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
emilmont 80:8e73be2a2ac1 50 CMSIS violates the following MISRA-C:2004 rules:
emilmont 80:8e73be2a2ac1 51
emilmont 80:8e73be2a2ac1 52 \li Required Rule 8.5, object/function definition in header file.<br>
emilmont 80:8e73be2a2ac1 53 Function definitions in header files are used to allow 'inlining'.
emilmont 80:8e73be2a2ac1 54
emilmont 80:8e73be2a2ac1 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
emilmont 80:8e73be2a2ac1 56 Unions are used for effective representation of core registers.
emilmont 80:8e73be2a2ac1 57
emilmont 80:8e73be2a2ac1 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
emilmont 80:8e73be2a2ac1 59 Function-like macros are used to allow more efficient code.
emilmont 80:8e73be2a2ac1 60 */
emilmont 80:8e73be2a2ac1 61
emilmont 80:8e73be2a2ac1 62
emilmont 80:8e73be2a2ac1 63 /*******************************************************************************
emilmont 80:8e73be2a2ac1 64 * CMSIS definitions
emilmont 80:8e73be2a2ac1 65 ******************************************************************************/
emilmont 80:8e73be2a2ac1 66 /** \ingroup Cortex_M0
emilmont 80:8e73be2a2ac1 67 @{
emilmont 80:8e73be2a2ac1 68 */
emilmont 80:8e73be2a2ac1 69
emilmont 80:8e73be2a2ac1 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
emilmont 80:8e73be2a2ac1 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
emilmont 80:8e73be2a2ac1 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
emilmont 80:8e73be2a2ac1 75
emilmont 80:8e73be2a2ac1 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
emilmont 80:8e73be2a2ac1 77
emilmont 80:8e73be2a2ac1 78
emilmont 80:8e73be2a2ac1 79 #if defined ( __CC_ARM )
emilmont 80:8e73be2a2ac1 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
emilmont 80:8e73be2a2ac1 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
emilmont 80:8e73be2a2ac1 82 #define __STATIC_INLINE static __inline
emilmont 80:8e73be2a2ac1 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
emilmont 80:8e73be2a2ac1 89 #elif defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
emilmont 80:8e73be2a2ac1 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
emilmont 80:8e73be2a2ac1 92 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
emilmont 80:8e73be2a2ac1 96 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 97
emilmont 80:8e73be2a2ac1 98 #elif defined ( __TASKING__ )
emilmont 80:8e73be2a2ac1 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
emilmont 80:8e73be2a2ac1 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
emilmont 80:8e73be2a2ac1 101 #define __STATIC_INLINE static inline
emilmont 80:8e73be2a2ac1 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
emilmont 80:8e73be2a2ac1 109 #endif
emilmont 80:8e73be2a2ac1 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
emilmont 80:8e73be2a2ac1 113 */
emilmont 80:8e73be2a2ac1 114 #define __FPU_USED 0
emilmont 80:8e73be2a2ac1 115
emilmont 80:8e73be2a2ac1 116 #if defined ( __CC_ARM )
emilmont 80:8e73be2a2ac1 117 #if defined __TARGET_FPU_VFP
emilmont 80:8e73be2a2ac1 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 119 #endif
emilmont 80:8e73be2a2ac1 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
emilmont 80:8e73be2a2ac1 126 #elif defined ( __ICCARM__ )
emilmont 80:8e73be2a2ac1 127 #if defined __ARMVFP__
emilmont 80:8e73be2a2ac1 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 129 #endif
emilmont 80:8e73be2a2ac1 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
emilmont 80:8e73be2a2ac1 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 134 #endif
emilmont 80:8e73be2a2ac1 135
emilmont 80:8e73be2a2ac1 136 #elif defined ( __TASKING__ )
emilmont 80:8e73be2a2ac1 137 #if defined __FPU_VFP__
emilmont 80:8e73be2a2ac1 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
emilmont 80:8e73be2a2ac1 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
emilmont 80:8e73be2a2ac1 145 #endif
emilmont 80:8e73be2a2ac1 146
emilmont 80:8e73be2a2ac1 147 #include <stdint.h> /* standard types definitions */
emilmont 80:8e73be2a2ac1 148 #include <core_cmInstr.h> /* Core Instruction Access */
emilmont 80:8e73be2a2ac1 149 #include <core_cmFunc.h> /* Core Function Access */
emilmont 80:8e73be2a2ac1 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
emilmont 80:8e73be2a2ac1 155 #endif /* __CORE_CM0_H_GENERIC */
emilmont 80:8e73be2a2ac1 156
emilmont 80:8e73be2a2ac1 157 #ifndef __CMSIS_GENERIC
emilmont 80:8e73be2a2ac1 158
emilmont 80:8e73be2a2ac1 159 #ifndef __CORE_CM0_H_DEPENDANT
emilmont 80:8e73be2a2ac1 160 #define __CORE_CM0_H_DEPENDANT
emilmont 80:8e73be2a2ac1 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
emilmont 80:8e73be2a2ac1 166 /* check device defines and use defaults */
emilmont 80:8e73be2a2ac1 167 #if defined __CHECK_DEVICE_DEFINES
emilmont 80:8e73be2a2ac1 168 #ifndef __CM0_REV
emilmont 80:8e73be2a2ac1 169 #define __CM0_REV 0x0000
emilmont 80:8e73be2a2ac1 170 #warning "__CM0_REV not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 171 #endif
emilmont 80:8e73be2a2ac1 172
emilmont 80:8e73be2a2ac1 173 #ifndef __NVIC_PRIO_BITS
emilmont 80:8e73be2a2ac1 174 #define __NVIC_PRIO_BITS 2
emilmont 80:8e73be2a2ac1 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 176 #endif
emilmont 80:8e73be2a2ac1 177
emilmont 80:8e73be2a2ac1 178 #ifndef __Vendor_SysTickConfig
emilmont 80:8e73be2a2ac1 179 #define __Vendor_SysTickConfig 0
emilmont 80:8e73be2a2ac1 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
emilmont 80:8e73be2a2ac1 181 #endif
emilmont 80:8e73be2a2ac1 182 #endif
emilmont 80:8e73be2a2ac1 183
emilmont 80:8e73be2a2ac1 184 /* IO definitions (access restrictions to peripheral registers) */
emilmont 80:8e73be2a2ac1 185 /**
emilmont 80:8e73be2a2ac1 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
emilmont 80:8e73be2a2ac1 187
emilmont 80:8e73be2a2ac1 188 <strong>IO Type Qualifiers</strong> are used
emilmont 80:8e73be2a2ac1 189 \li to specify the access to peripheral variables.
emilmont 80:8e73be2a2ac1 190 \li for automatic generation of peripheral register debug information.
emilmont 80:8e73be2a2ac1 191 */
emilmont 80:8e73be2a2ac1 192 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 193 #define __I volatile /*!< Defines 'read only' permissions */
emilmont 80:8e73be2a2ac1 194 #else
emilmont 80:8e73be2a2ac1 195 #define __I volatile const /*!< Defines 'read only' permissions */
emilmont 80:8e73be2a2ac1 196 #endif
emilmont 80:8e73be2a2ac1 197 #define __O volatile /*!< Defines 'write only' permissions */
emilmont 80:8e73be2a2ac1 198 #define __IO volatile /*!< Defines 'read / write' permissions */
emilmont 80:8e73be2a2ac1 199
emilmont 80:8e73be2a2ac1 200 /*@} end of group Cortex_M0 */
emilmont 80:8e73be2a2ac1 201
emilmont 80:8e73be2a2ac1 202
emilmont 80:8e73be2a2ac1 203
emilmont 80:8e73be2a2ac1 204 /*******************************************************************************
emilmont 80:8e73be2a2ac1 205 * Register Abstraction
emilmont 80:8e73be2a2ac1 206 Core Register contain:
emilmont 80:8e73be2a2ac1 207 - Core Register
emilmont 80:8e73be2a2ac1 208 - Core NVIC Register
emilmont 80:8e73be2a2ac1 209 - Core SCB Register
emilmont 80:8e73be2a2ac1 210 - Core SysTick Register
emilmont 80:8e73be2a2ac1 211 ******************************************************************************/
emilmont 80:8e73be2a2ac1 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
emilmont 80:8e73be2a2ac1 213 \brief Type definitions and defines for Cortex-M processor based devices.
emilmont 80:8e73be2a2ac1 214 */
emilmont 80:8e73be2a2ac1 215
emilmont 80:8e73be2a2ac1 216 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 217 \defgroup CMSIS_CORE Status and Control Registers
emilmont 80:8e73be2a2ac1 218 \brief Core Register type definitions.
emilmont 80:8e73be2a2ac1 219 @{
emilmont 80:8e73be2a2ac1 220 */
emilmont 80:8e73be2a2ac1 221
emilmont 80:8e73be2a2ac1 222 /** \brief Union type to access the Application Program Status Register (APSR).
emilmont 80:8e73be2a2ac1 223 */
emilmont 80:8e73be2a2ac1 224 typedef union
emilmont 80:8e73be2a2ac1 225 {
emilmont 80:8e73be2a2ac1 226 struct
emilmont 80:8e73be2a2ac1 227 {
Kojto 110:165afa46840b 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
emilmont 80:8e73be2a2ac1 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 80:8e73be2a2ac1 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 80:8e73be2a2ac1 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 80:8e73be2a2ac1 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 80:8e73be2a2ac1 233 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 234 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 235 } APSR_Type;
emilmont 80:8e73be2a2ac1 236
Kojto 110:165afa46840b 237 /* APSR Register Definitions */
Kojto 110:165afa46840b 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 240
Kojto 110:165afa46840b 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 243
Kojto 110:165afa46840b 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 246
Kojto 110:165afa46840b 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 249
emilmont 80:8e73be2a2ac1 250
emilmont 80:8e73be2a2ac1 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
emilmont 80:8e73be2a2ac1 252 */
emilmont 80:8e73be2a2ac1 253 typedef union
emilmont 80:8e73be2a2ac1 254 {
emilmont 80:8e73be2a2ac1 255 struct
emilmont 80:8e73be2a2ac1 256 {
emilmont 80:8e73be2a2ac1 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 80:8e73be2a2ac1 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
emilmont 80:8e73be2a2ac1 259 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 260 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 261 } IPSR_Type;
emilmont 80:8e73be2a2ac1 262
Kojto 110:165afa46840b 263 /* IPSR Register Definitions */
Kojto 110:165afa46840b 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 266
emilmont 80:8e73be2a2ac1 267
emilmont 80:8e73be2a2ac1 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
emilmont 80:8e73be2a2ac1 269 */
emilmont 80:8e73be2a2ac1 270 typedef union
emilmont 80:8e73be2a2ac1 271 {
emilmont 80:8e73be2a2ac1 272 struct
emilmont 80:8e73be2a2ac1 273 {
emilmont 80:8e73be2a2ac1 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
emilmont 80:8e73be2a2ac1 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
emilmont 80:8e73be2a2ac1 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
emilmont 80:8e73be2a2ac1 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
emilmont 80:8e73be2a2ac1 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
emilmont 80:8e73be2a2ac1 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
emilmont 80:8e73be2a2ac1 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
emilmont 80:8e73be2a2ac1 282 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 283 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 284 } xPSR_Type;
emilmont 80:8e73be2a2ac1 285
Kojto 110:165afa46840b 286 /* xPSR Register Definitions */
Kojto 110:165afa46840b 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 289
Kojto 110:165afa46840b 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 292
Kojto 110:165afa46840b 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 295
Kojto 110:165afa46840b 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 298
Kojto 110:165afa46840b 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 301
Kojto 110:165afa46840b 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 304
emilmont 80:8e73be2a2ac1 305
emilmont 80:8e73be2a2ac1 306 /** \brief Union type to access the Control Registers (CONTROL).
emilmont 80:8e73be2a2ac1 307 */
emilmont 80:8e73be2a2ac1 308 typedef union
emilmont 80:8e73be2a2ac1 309 {
emilmont 80:8e73be2a2ac1 310 struct
emilmont 80:8e73be2a2ac1 311 {
Kojto 110:165afa46840b 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
emilmont 80:8e73be2a2ac1 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
emilmont 80:8e73be2a2ac1 315 } b; /*!< Structure used for bit access */
emilmont 80:8e73be2a2ac1 316 uint32_t w; /*!< Type used for word access */
emilmont 80:8e73be2a2ac1 317 } CONTROL_Type;
emilmont 80:8e73be2a2ac1 318
Kojto 110:165afa46840b 319 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 322
emilmont 80:8e73be2a2ac1 323 /*@} end of group CMSIS_CORE */
emilmont 80:8e73be2a2ac1 324
emilmont 80:8e73be2a2ac1 325
emilmont 80:8e73be2a2ac1 326 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
emilmont 80:8e73be2a2ac1 328 \brief Type definitions for the NVIC Registers
emilmont 80:8e73be2a2ac1 329 @{
emilmont 80:8e73be2a2ac1 330 */
emilmont 80:8e73be2a2ac1 331
emilmont 80:8e73be2a2ac1 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
emilmont 80:8e73be2a2ac1 333 */
emilmont 80:8e73be2a2ac1 334 typedef struct
emilmont 80:8e73be2a2ac1 335 {
emilmont 80:8e73be2a2ac1 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
emilmont 80:8e73be2a2ac1 337 uint32_t RESERVED0[31];
emilmont 80:8e73be2a2ac1 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
emilmont 80:8e73be2a2ac1 339 uint32_t RSERVED1[31];
emilmont 80:8e73be2a2ac1 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
emilmont 80:8e73be2a2ac1 341 uint32_t RESERVED2[31];
emilmont 80:8e73be2a2ac1 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
emilmont 80:8e73be2a2ac1 343 uint32_t RESERVED3[31];
emilmont 80:8e73be2a2ac1 344 uint32_t RESERVED4[64];
emilmont 80:8e73be2a2ac1 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
emilmont 80:8e73be2a2ac1 346 } NVIC_Type;
emilmont 80:8e73be2a2ac1 347
emilmont 80:8e73be2a2ac1 348 /*@} end of group CMSIS_NVIC */
emilmont 80:8e73be2a2ac1 349
emilmont 80:8e73be2a2ac1 350
emilmont 80:8e73be2a2ac1 351 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 352 \defgroup CMSIS_SCB System Control Block (SCB)
emilmont 80:8e73be2a2ac1 353 \brief Type definitions for the System Control Block Registers
emilmont 80:8e73be2a2ac1 354 @{
emilmont 80:8e73be2a2ac1 355 */
emilmont 80:8e73be2a2ac1 356
emilmont 80:8e73be2a2ac1 357 /** \brief Structure type to access the System Control Block (SCB).
emilmont 80:8e73be2a2ac1 358 */
emilmont 80:8e73be2a2ac1 359 typedef struct
emilmont 80:8e73be2a2ac1 360 {
emilmont 80:8e73be2a2ac1 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
emilmont 80:8e73be2a2ac1 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
emilmont 80:8e73be2a2ac1 363 uint32_t RESERVED0;
emilmont 80:8e73be2a2ac1 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
emilmont 80:8e73be2a2ac1 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
emilmont 80:8e73be2a2ac1 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
emilmont 80:8e73be2a2ac1 367 uint32_t RESERVED1;
emilmont 80:8e73be2a2ac1 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
emilmont 80:8e73be2a2ac1 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
emilmont 80:8e73be2a2ac1 370 } SCB_Type;
emilmont 80:8e73be2a2ac1 371
emilmont 80:8e73be2a2ac1 372 /* SCB CPUID Register Definitions */
emilmont 80:8e73be2a2ac1 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
emilmont 80:8e73be2a2ac1 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
emilmont 80:8e73be2a2ac1 375
emilmont 80:8e73be2a2ac1 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
emilmont 80:8e73be2a2ac1 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
emilmont 80:8e73be2a2ac1 378
emilmont 80:8e73be2a2ac1 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
emilmont 80:8e73be2a2ac1 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
emilmont 80:8e73be2a2ac1 381
emilmont 80:8e73be2a2ac1 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
emilmont 80:8e73be2a2ac1 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
emilmont 80:8e73be2a2ac1 384
emilmont 80:8e73be2a2ac1 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
emilmont 80:8e73be2a2ac1 387
emilmont 80:8e73be2a2ac1 388 /* SCB Interrupt Control State Register Definitions */
emilmont 80:8e73be2a2ac1 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
emilmont 80:8e73be2a2ac1 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
emilmont 80:8e73be2a2ac1 391
emilmont 80:8e73be2a2ac1 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
emilmont 80:8e73be2a2ac1 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
emilmont 80:8e73be2a2ac1 394
emilmont 80:8e73be2a2ac1 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
emilmont 80:8e73be2a2ac1 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
emilmont 80:8e73be2a2ac1 397
emilmont 80:8e73be2a2ac1 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
emilmont 80:8e73be2a2ac1 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
emilmont 80:8e73be2a2ac1 400
emilmont 80:8e73be2a2ac1 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
emilmont 80:8e73be2a2ac1 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
emilmont 80:8e73be2a2ac1 403
emilmont 80:8e73be2a2ac1 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
emilmont 80:8e73be2a2ac1 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
emilmont 80:8e73be2a2ac1 406
emilmont 80:8e73be2a2ac1 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
emilmont 80:8e73be2a2ac1 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
emilmont 80:8e73be2a2ac1 409
emilmont 80:8e73be2a2ac1 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
emilmont 80:8e73be2a2ac1 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
emilmont 80:8e73be2a2ac1 412
emilmont 80:8e73be2a2ac1 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
emilmont 80:8e73be2a2ac1 415
emilmont 80:8e73be2a2ac1 416 /* SCB Application Interrupt and Reset Control Register Definitions */
emilmont 80:8e73be2a2ac1 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
emilmont 80:8e73be2a2ac1 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
emilmont 80:8e73be2a2ac1 419
emilmont 80:8e73be2a2ac1 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
emilmont 80:8e73be2a2ac1 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
emilmont 80:8e73be2a2ac1 422
emilmont 80:8e73be2a2ac1 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
emilmont 80:8e73be2a2ac1 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
emilmont 80:8e73be2a2ac1 425
emilmont 80:8e73be2a2ac1 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
emilmont 80:8e73be2a2ac1 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
emilmont 80:8e73be2a2ac1 428
emilmont 80:8e73be2a2ac1 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
emilmont 80:8e73be2a2ac1 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
emilmont 80:8e73be2a2ac1 431
emilmont 80:8e73be2a2ac1 432 /* SCB System Control Register Definitions */
emilmont 80:8e73be2a2ac1 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
emilmont 80:8e73be2a2ac1 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
emilmont 80:8e73be2a2ac1 435
emilmont 80:8e73be2a2ac1 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
emilmont 80:8e73be2a2ac1 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
emilmont 80:8e73be2a2ac1 438
emilmont 80:8e73be2a2ac1 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
emilmont 80:8e73be2a2ac1 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
emilmont 80:8e73be2a2ac1 441
emilmont 80:8e73be2a2ac1 442 /* SCB Configuration Control Register Definitions */
emilmont 80:8e73be2a2ac1 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
emilmont 80:8e73be2a2ac1 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
emilmont 80:8e73be2a2ac1 445
emilmont 80:8e73be2a2ac1 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
emilmont 80:8e73be2a2ac1 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
emilmont 80:8e73be2a2ac1 448
emilmont 80:8e73be2a2ac1 449 /* SCB System Handler Control and State Register Definitions */
emilmont 80:8e73be2a2ac1 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
emilmont 80:8e73be2a2ac1 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
emilmont 80:8e73be2a2ac1 452
emilmont 80:8e73be2a2ac1 453 /*@} end of group CMSIS_SCB */
emilmont 80:8e73be2a2ac1 454
emilmont 80:8e73be2a2ac1 455
emilmont 80:8e73be2a2ac1 456 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
emilmont 80:8e73be2a2ac1 458 \brief Type definitions for the System Timer Registers.
emilmont 80:8e73be2a2ac1 459 @{
emilmont 80:8e73be2a2ac1 460 */
emilmont 80:8e73be2a2ac1 461
emilmont 80:8e73be2a2ac1 462 /** \brief Structure type to access the System Timer (SysTick).
emilmont 80:8e73be2a2ac1 463 */
emilmont 80:8e73be2a2ac1 464 typedef struct
emilmont 80:8e73be2a2ac1 465 {
emilmont 80:8e73be2a2ac1 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
emilmont 80:8e73be2a2ac1 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
emilmont 80:8e73be2a2ac1 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
emilmont 80:8e73be2a2ac1 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
emilmont 80:8e73be2a2ac1 470 } SysTick_Type;
emilmont 80:8e73be2a2ac1 471
emilmont 80:8e73be2a2ac1 472 /* SysTick Control / Status Register Definitions */
emilmont 80:8e73be2a2ac1 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
emilmont 80:8e73be2a2ac1 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
emilmont 80:8e73be2a2ac1 475
emilmont 80:8e73be2a2ac1 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
emilmont 80:8e73be2a2ac1 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
emilmont 80:8e73be2a2ac1 478
emilmont 80:8e73be2a2ac1 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
emilmont 80:8e73be2a2ac1 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
emilmont 80:8e73be2a2ac1 481
emilmont 80:8e73be2a2ac1 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
emilmont 80:8e73be2a2ac1 484
emilmont 80:8e73be2a2ac1 485 /* SysTick Reload Register Definitions */
emilmont 80:8e73be2a2ac1 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
emilmont 80:8e73be2a2ac1 488
emilmont 80:8e73be2a2ac1 489 /* SysTick Current Register Definitions */
emilmont 80:8e73be2a2ac1 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
emilmont 80:8e73be2a2ac1 492
emilmont 80:8e73be2a2ac1 493 /* SysTick Calibration Register Definitions */
emilmont 80:8e73be2a2ac1 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
emilmont 80:8e73be2a2ac1 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
emilmont 80:8e73be2a2ac1 496
emilmont 80:8e73be2a2ac1 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
emilmont 80:8e73be2a2ac1 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
emilmont 80:8e73be2a2ac1 499
emilmont 80:8e73be2a2ac1 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
emilmont 80:8e73be2a2ac1 502
emilmont 80:8e73be2a2ac1 503 /*@} end of group CMSIS_SysTick */
emilmont 80:8e73be2a2ac1 504
emilmont 80:8e73be2a2ac1 505
emilmont 80:8e73be2a2ac1 506 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
emilmont 80:8e73be2a2ac1 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
emilmont 80:8e73be2a2ac1 509 are only accessible over DAP and not via processor. Therefore
emilmont 80:8e73be2a2ac1 510 they are not covered by the Cortex-M0 header file.
emilmont 80:8e73be2a2ac1 511 @{
emilmont 80:8e73be2a2ac1 512 */
emilmont 80:8e73be2a2ac1 513 /*@} end of group CMSIS_CoreDebug */
emilmont 80:8e73be2a2ac1 514
emilmont 80:8e73be2a2ac1 515
emilmont 80:8e73be2a2ac1 516 /** \ingroup CMSIS_core_register
emilmont 80:8e73be2a2ac1 517 \defgroup CMSIS_core_base Core Definitions
emilmont 80:8e73be2a2ac1 518 \brief Definitions for base addresses, unions, and structures.
emilmont 80:8e73be2a2ac1 519 @{
emilmont 80:8e73be2a2ac1 520 */
emilmont 80:8e73be2a2ac1 521
emilmont 80:8e73be2a2ac1 522 /* Memory mapping of Cortex-M0 Hardware */
emilmont 80:8e73be2a2ac1 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
emilmont 80:8e73be2a2ac1 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
emilmont 80:8e73be2a2ac1 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
emilmont 80:8e73be2a2ac1 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
emilmont 80:8e73be2a2ac1 527
emilmont 80:8e73be2a2ac1 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
emilmont 80:8e73be2a2ac1 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
emilmont 80:8e73be2a2ac1 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
emilmont 80:8e73be2a2ac1 531
emilmont 80:8e73be2a2ac1 532
emilmont 80:8e73be2a2ac1 533 /*@} */
emilmont 80:8e73be2a2ac1 534
emilmont 80:8e73be2a2ac1 535
emilmont 80:8e73be2a2ac1 536
emilmont 80:8e73be2a2ac1 537 /*******************************************************************************
emilmont 80:8e73be2a2ac1 538 * Hardware Abstraction Layer
emilmont 80:8e73be2a2ac1 539 Core Function Interface contains:
emilmont 80:8e73be2a2ac1 540 - Core NVIC Functions
emilmont 80:8e73be2a2ac1 541 - Core SysTick Functions
emilmont 80:8e73be2a2ac1 542 - Core Register Access Functions
emilmont 80:8e73be2a2ac1 543 ******************************************************************************/
emilmont 80:8e73be2a2ac1 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
emilmont 80:8e73be2a2ac1 545 */
emilmont 80:8e73be2a2ac1 546
emilmont 80:8e73be2a2ac1 547
emilmont 80:8e73be2a2ac1 548
emilmont 80:8e73be2a2ac1 549 /* ########################## NVIC functions #################################### */
emilmont 80:8e73be2a2ac1 550 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
emilmont 80:8e73be2a2ac1 552 \brief Functions that manage interrupts and exceptions via the NVIC.
emilmont 80:8e73be2a2ac1 553 @{
emilmont 80:8e73be2a2ac1 554 */
emilmont 80:8e73be2a2ac1 555
emilmont 80:8e73be2a2ac1 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
emilmont 80:8e73be2a2ac1 557 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
emilmont 80:8e73be2a2ac1 561
emilmont 80:8e73be2a2ac1 562
emilmont 80:8e73be2a2ac1 563 /** \brief Enable External Interrupt
emilmont 80:8e73be2a2ac1 564
emilmont 80:8e73be2a2ac1 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
emilmont 80:8e73be2a2ac1 566
emilmont 80:8e73be2a2ac1 567 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 568 */
emilmont 80:8e73be2a2ac1 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 570 {
Kojto 110:165afa46840b 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 80:8e73be2a2ac1 572 }
emilmont 80:8e73be2a2ac1 573
emilmont 80:8e73be2a2ac1 574
emilmont 80:8e73be2a2ac1 575 /** \brief Disable External Interrupt
emilmont 80:8e73be2a2ac1 576
emilmont 80:8e73be2a2ac1 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
emilmont 80:8e73be2a2ac1 578
emilmont 80:8e73be2a2ac1 579 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 580 */
emilmont 80:8e73be2a2ac1 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 582 {
Kojto 110:165afa46840b 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 80:8e73be2a2ac1 584 }
emilmont 80:8e73be2a2ac1 585
emilmont 80:8e73be2a2ac1 586
emilmont 80:8e73be2a2ac1 587 /** \brief Get Pending Interrupt
emilmont 80:8e73be2a2ac1 588
emilmont 80:8e73be2a2ac1 589 The function reads the pending register in the NVIC and returns the pending bit
emilmont 80:8e73be2a2ac1 590 for the specified interrupt.
emilmont 80:8e73be2a2ac1 591
emilmont 80:8e73be2a2ac1 592 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 593
emilmont 80:8e73be2a2ac1 594 \return 0 Interrupt status is not pending.
emilmont 80:8e73be2a2ac1 595 \return 1 Interrupt status is pending.
emilmont 80:8e73be2a2ac1 596 */
emilmont 80:8e73be2a2ac1 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 598 {
Kojto 110:165afa46840b 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
emilmont 80:8e73be2a2ac1 600 }
emilmont 80:8e73be2a2ac1 601
emilmont 80:8e73be2a2ac1 602
emilmont 80:8e73be2a2ac1 603 /** \brief Set Pending Interrupt
emilmont 80:8e73be2a2ac1 604
emilmont 80:8e73be2a2ac1 605 The function sets the pending bit of an external interrupt.
emilmont 80:8e73be2a2ac1 606
emilmont 80:8e73be2a2ac1 607 \param [in] IRQn Interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 608 */
emilmont 80:8e73be2a2ac1 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 610 {
Kojto 110:165afa46840b 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 80:8e73be2a2ac1 612 }
emilmont 80:8e73be2a2ac1 613
emilmont 80:8e73be2a2ac1 614
emilmont 80:8e73be2a2ac1 615 /** \brief Clear Pending Interrupt
emilmont 80:8e73be2a2ac1 616
emilmont 80:8e73be2a2ac1 617 The function clears the pending bit of an external interrupt.
emilmont 80:8e73be2a2ac1 618
emilmont 80:8e73be2a2ac1 619 \param [in] IRQn External interrupt number. Value cannot be negative.
emilmont 80:8e73be2a2ac1 620 */
emilmont 80:8e73be2a2ac1 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 622 {
Kojto 110:165afa46840b 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
emilmont 80:8e73be2a2ac1 624 }
emilmont 80:8e73be2a2ac1 625
emilmont 80:8e73be2a2ac1 626
emilmont 80:8e73be2a2ac1 627 /** \brief Set Interrupt Priority
emilmont 80:8e73be2a2ac1 628
emilmont 80:8e73be2a2ac1 629 The function sets the priority of an interrupt.
emilmont 80:8e73be2a2ac1 630
emilmont 80:8e73be2a2ac1 631 \note The priority cannot be set for every core interrupt.
emilmont 80:8e73be2a2ac1 632
emilmont 80:8e73be2a2ac1 633 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 634 \param [in] priority Priority to set.
emilmont 80:8e73be2a2ac1 635 */
emilmont 80:8e73be2a2ac1 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
emilmont 80:8e73be2a2ac1 637 {
Kojto 110:165afa46840b 638 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 641 }
emilmont 80:8e73be2a2ac1 642 else {
Kojto 110:165afa46840b 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 645 }
emilmont 80:8e73be2a2ac1 646 }
emilmont 80:8e73be2a2ac1 647
emilmont 80:8e73be2a2ac1 648
emilmont 80:8e73be2a2ac1 649 /** \brief Get Interrupt Priority
emilmont 80:8e73be2a2ac1 650
emilmont 80:8e73be2a2ac1 651 The function reads the priority of an interrupt. The interrupt
emilmont 80:8e73be2a2ac1 652 number can be positive to specify an external (device specific)
emilmont 80:8e73be2a2ac1 653 interrupt, or negative to specify an internal (core) interrupt.
emilmont 80:8e73be2a2ac1 654
emilmont 80:8e73be2a2ac1 655
emilmont 80:8e73be2a2ac1 656 \param [in] IRQn Interrupt number.
emilmont 80:8e73be2a2ac1 657 \return Interrupt Priority. Value is aligned automatically to the implemented
emilmont 80:8e73be2a2ac1 658 priority bits of the microcontroller.
emilmont 80:8e73be2a2ac1 659 */
emilmont 80:8e73be2a2ac1 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
emilmont 80:8e73be2a2ac1 661 {
emilmont 80:8e73be2a2ac1 662
Kojto 110:165afa46840b 663 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 665 }
emilmont 80:8e73be2a2ac1 666 else {
Kojto 110:165afa46840b 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 668 }
emilmont 80:8e73be2a2ac1 669 }
emilmont 80:8e73be2a2ac1 670
emilmont 80:8e73be2a2ac1 671
emilmont 80:8e73be2a2ac1 672 /** \brief System Reset
emilmont 80:8e73be2a2ac1 673
emilmont 80:8e73be2a2ac1 674 The function initiates a system reset request to reset the MCU.
emilmont 80:8e73be2a2ac1 675 */
emilmont 80:8e73be2a2ac1 676 __STATIC_INLINE void NVIC_SystemReset(void)
emilmont 80:8e73be2a2ac1 677 {
emilmont 80:8e73be2a2ac1 678 __DSB(); /* Ensure all outstanding memory accesses included
emilmont 80:8e73be2a2ac1 679 buffered write are completed before reset */
Kojto 110:165afa46840b 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
emilmont 80:8e73be2a2ac1 681 SCB_AIRCR_SYSRESETREQ_Msk);
emilmont 80:8e73be2a2ac1 682 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 683 while(1) { __NOP(); } /* wait until reset */
emilmont 80:8e73be2a2ac1 684 }
emilmont 80:8e73be2a2ac1 685
emilmont 80:8e73be2a2ac1 686 /*@} end of CMSIS_Core_NVICFunctions */
emilmont 80:8e73be2a2ac1 687
emilmont 80:8e73be2a2ac1 688
emilmont 80:8e73be2a2ac1 689
emilmont 80:8e73be2a2ac1 690 /* ################################## SysTick function ############################################ */
emilmont 80:8e73be2a2ac1 691 /** \ingroup CMSIS_Core_FunctionInterface
emilmont 80:8e73be2a2ac1 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
emilmont 80:8e73be2a2ac1 693 \brief Functions that configure the System.
emilmont 80:8e73be2a2ac1 694 @{
emilmont 80:8e73be2a2ac1 695 */
emilmont 80:8e73be2a2ac1 696
emilmont 80:8e73be2a2ac1 697 #if (__Vendor_SysTickConfig == 0)
emilmont 80:8e73be2a2ac1 698
emilmont 80:8e73be2a2ac1 699 /** \brief System Tick Configuration
emilmont 80:8e73be2a2ac1 700
emilmont 80:8e73be2a2ac1 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
emilmont 80:8e73be2a2ac1 702 Counter is in free running mode to generate periodic interrupts.
emilmont 80:8e73be2a2ac1 703
emilmont 80:8e73be2a2ac1 704 \param [in] ticks Number of ticks between two interrupts.
emilmont 80:8e73be2a2ac1 705
emilmont 80:8e73be2a2ac1 706 \return 0 Function succeeded.
emilmont 80:8e73be2a2ac1 707 \return 1 Function failed.
emilmont 80:8e73be2a2ac1 708
emilmont 80:8e73be2a2ac1 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
emilmont 80:8e73be2a2ac1 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
emilmont 80:8e73be2a2ac1 711 must contain a vendor-specific implementation of this function.
emilmont 80:8e73be2a2ac1 712
emilmont 80:8e73be2a2ac1 713 */
emilmont 80:8e73be2a2ac1 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
emilmont 80:8e73be2a2ac1 715 {
Kojto 110:165afa46840b 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
emilmont 80:8e73be2a2ac1 717
Kojto 110:165afa46840b 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
emilmont 80:8e73be2a2ac1 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
emilmont 80:8e73be2a2ac1 722 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 724 return (0UL); /* Function successful */
emilmont 80:8e73be2a2ac1 725 }
emilmont 80:8e73be2a2ac1 726
emilmont 80:8e73be2a2ac1 727 #endif
emilmont 80:8e73be2a2ac1 728
emilmont 80:8e73be2a2ac1 729 /*@} end of CMSIS_Core_SysTickFunctions */
emilmont 80:8e73be2a2ac1 730
emilmont 80:8e73be2a2ac1 731
emilmont 80:8e73be2a2ac1 732
emilmont 80:8e73be2a2ac1 733
Kojto 110:165afa46840b 734 #ifdef __cplusplus
Kojto 110:165afa46840b 735 }
Kojto 110:165afa46840b 736 #endif
Kojto 110:165afa46840b 737
emilmont 80:8e73be2a2ac1 738 #endif /* __CORE_CM0_H_DEPENDANT */
emilmont 80:8e73be2a2ac1 739
emilmont 80:8e73be2a2ac1 740 #endif /* __CMSIS_GENERIC */