Ricardo Benitez / mbed

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TARGET_LPC812/core_cm0.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
64:e3affc9e7238 
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 64:e3affc9e7238 1 /**************************************************************************//**
bogdanm 64:e3affc9e7238 2 * @file core_cm0.h
bogdanm 64:e3affc9e7238 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
bogdanm 64:e3affc9e7238 6 *
bogdanm 64:e3affc9e7238 7 * @note
bogdanm 64:e3affc9e7238 8 *
bogdanm 64:e3affc9e7238 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 64:e3affc9e7238 11
bogdanm 64:e3affc9e7238 12 All rights reserved.
bogdanm 64:e3affc9e7238 13 Redistribution and use in source and binary forms, with or without
bogdanm 64:e3affc9e7238 14 modification, are permitted provided that the following conditions are met:
bogdanm 64:e3affc9e7238 15 - Redistributions of source code must retain the above copyright
bogdanm 64:e3affc9e7238 16 notice, this list of conditions and the following disclaimer.
bogdanm 64:e3affc9e7238 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 64:e3affc9e7238 18 notice, this list of conditions and the following disclaimer in the
bogdanm 64:e3affc9e7238 19 documentation and/or other materials provided with the distribution.
bogdanm 64:e3affc9e7238 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 64:e3affc9e7238 21 to endorse or promote products derived from this software without
bogdanm 64:e3affc9e7238 22 specific prior written permission.
bogdanm 64:e3affc9e7238 23 *
bogdanm 64:e3affc9e7238 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 64:e3affc9e7238 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 64:e3affc9e7238 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 64:e3affc9e7238 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 64:e3affc9e7238 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 64:e3affc9e7238 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 64:e3affc9e7238 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 64:e3affc9e7238 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 64:e3affc9e7238 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 64:e3affc9e7238 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 64:e3affc9e7238 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 64:e3affc9e7238 35 ---------------------------------------------------------------------------*/
bogdanm 64:e3affc9e7238 36
bogdanm 64:e3affc9e7238 37
bogdanm 64:e3affc9e7238 38 #if defined ( __ICCARM__ )
bogdanm 64:e3affc9e7238 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 64:e3affc9e7238 40 #endif
bogdanm 64:e3affc9e7238 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
bogdanm 64:e3affc9e7238 45 #ifdef __cplusplus
bogdanm 64:e3affc9e7238 46 extern "C" {
bogdanm 64:e3affc9e7238 47 #endif
bogdanm 64:e3affc9e7238 48
bogdanm 64:e3affc9e7238 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 64:e3affc9e7238 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 64:e3affc9e7238 51
bogdanm 64:e3affc9e7238 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 64:e3affc9e7238 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 64:e3affc9e7238 54
bogdanm 64:e3affc9e7238 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 64:e3affc9e7238 56 Unions are used for effective representation of core registers.
bogdanm 64:e3affc9e7238 57
bogdanm 64:e3affc9e7238 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 64:e3affc9e7238 59 Function-like macros are used to allow more efficient code.
bogdanm 64:e3affc9e7238 60 */
bogdanm 64:e3affc9e7238 61
bogdanm 64:e3affc9e7238 62
bogdanm 64:e3affc9e7238 63 /*******************************************************************************
bogdanm 64:e3affc9e7238 64 * CMSIS definitions
bogdanm 64:e3affc9e7238 65 ******************************************************************************/
bogdanm 64:e3affc9e7238 66 /** \ingroup Cortex_M0
bogdanm 64:e3affc9e7238 67 @{
bogdanm 64:e3affc9e7238 68 */
bogdanm 64:e3affc9e7238 69
bogdanm 64:e3affc9e7238 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 64:e3affc9e7238 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
bogdanm 64:e3affc9e7238 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 64:e3affc9e7238 75
bogdanm 64:e3affc9e7238 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 64:e3affc9e7238 77
bogdanm 64:e3affc9e7238 78
bogdanm 64:e3affc9e7238 79 #if defined ( __CC_ARM )
bogdanm 64:e3affc9e7238 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 64:e3affc9e7238 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 64:e3affc9e7238 82 #define __STATIC_INLINE static __inline
bogdanm 64:e3affc9e7238 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
bogdanm 64:e3affc9e7238 89 #elif defined ( __ICCARM__ )
bogdanm 64:e3affc9e7238 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 64:e3affc9e7238 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 64:e3affc9e7238 92 #define __STATIC_INLINE static inline
bogdanm 64:e3affc9e7238 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 64:e3affc9e7238 96 #define __STATIC_INLINE static inline
bogdanm 64:e3affc9e7238 97
bogdanm 64:e3affc9e7238 98 #elif defined ( __TASKING__ )
bogdanm 64:e3affc9e7238 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 64:e3affc9e7238 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 64:e3affc9e7238 101 #define __STATIC_INLINE static inline
bogdanm 64:e3affc9e7238 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
bogdanm 64:e3affc9e7238 109 #endif
bogdanm 64:e3affc9e7238 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
bogdanm 64:e3affc9e7238 113 */
bogdanm 64:e3affc9e7238 114 #define __FPU_USED 0
bogdanm 64:e3affc9e7238 115
bogdanm 64:e3affc9e7238 116 #if defined ( __CC_ARM )
bogdanm 64:e3affc9e7238 117 #if defined __TARGET_FPU_VFP
bogdanm 64:e3affc9e7238 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 64:e3affc9e7238 119 #endif
bogdanm 64:e3affc9e7238 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
bogdanm 64:e3affc9e7238 126 #elif defined ( __ICCARM__ )
bogdanm 64:e3affc9e7238 127 #if defined __ARMVFP__
bogdanm 64:e3affc9e7238 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 64:e3affc9e7238 129 #endif
bogdanm 64:e3affc9e7238 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
bogdanm 64:e3affc9e7238 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 64:e3affc9e7238 134 #endif
bogdanm 64:e3affc9e7238 135
bogdanm 64:e3affc9e7238 136 #elif defined ( __TASKING__ )
bogdanm 64:e3affc9e7238 137 #if defined __FPU_VFP__
bogdanm 64:e3affc9e7238 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 64:e3affc9e7238 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
bogdanm 64:e3affc9e7238 145 #endif
bogdanm 64:e3affc9e7238 146
bogdanm 64:e3affc9e7238 147 #include <stdint.h> /* standard types definitions */
bogdanm 64:e3affc9e7238 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 64:e3affc9e7238 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 64:e3affc9e7238 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
bogdanm 64:e3affc9e7238 155 #endif /* __CORE_CM0_H_GENERIC */
bogdanm 64:e3affc9e7238 156
bogdanm 64:e3affc9e7238 157 #ifndef __CMSIS_GENERIC
bogdanm 64:e3affc9e7238 158
bogdanm 64:e3affc9e7238 159 #ifndef __CORE_CM0_H_DEPENDANT
bogdanm 64:e3affc9e7238 160 #define __CORE_CM0_H_DEPENDANT
bogdanm 64:e3affc9e7238 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
bogdanm 64:e3affc9e7238 166 /* check device defines and use defaults */
bogdanm 64:e3affc9e7238 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 64:e3affc9e7238 168 #ifndef __CM0_REV
bogdanm 64:e3affc9e7238 169 #define __CM0_REV 0x0000
bogdanm 64:e3affc9e7238 170 #warning "__CM0_REV not defined in device header file; using default!"
bogdanm 64:e3affc9e7238 171 #endif
bogdanm 64:e3affc9e7238 172
bogdanm 64:e3affc9e7238 173 #ifndef __NVIC_PRIO_BITS
bogdanm 64:e3affc9e7238 174 #define __NVIC_PRIO_BITS 2
bogdanm 64:e3affc9e7238 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 64:e3affc9e7238 176 #endif
bogdanm 64:e3affc9e7238 177
bogdanm 64:e3affc9e7238 178 #ifndef __Vendor_SysTickConfig
bogdanm 64:e3affc9e7238 179 #define __Vendor_SysTickConfig 0
bogdanm 64:e3affc9e7238 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 64:e3affc9e7238 181 #endif
bogdanm 64:e3affc9e7238 182 #endif
bogdanm 64:e3affc9e7238 183
bogdanm 64:e3affc9e7238 184 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 64:e3affc9e7238 185 /**
bogdanm 64:e3affc9e7238 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 64:e3affc9e7238 187
bogdanm 64:e3affc9e7238 188 <strong>IO Type Qualifiers</strong> are used
bogdanm 64:e3affc9e7238 189 \li to specify the access to peripheral variables.
bogdanm 64:e3affc9e7238 190 \li for automatic generation of peripheral register debug information.
bogdanm 64:e3affc9e7238 191 */
bogdanm 64:e3affc9e7238 192 #ifdef __cplusplus
bogdanm 64:e3affc9e7238 193 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 64:e3affc9e7238 194 #else
bogdanm 64:e3affc9e7238 195 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 64:e3affc9e7238 196 #endif
bogdanm 64:e3affc9e7238 197 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 64:e3affc9e7238 198 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 64:e3affc9e7238 199
bogdanm 64:e3affc9e7238 200 /*@} end of group Cortex_M0 */
bogdanm 64:e3affc9e7238 201
bogdanm 64:e3affc9e7238 202
bogdanm 64:e3affc9e7238 203
bogdanm 64:e3affc9e7238 204 /*******************************************************************************
bogdanm 64:e3affc9e7238 205 * Register Abstraction
bogdanm 64:e3affc9e7238 206 Core Register contain:
bogdanm 64:e3affc9e7238 207 - Core Register
bogdanm 64:e3affc9e7238 208 - Core NVIC Register
bogdanm 64:e3affc9e7238 209 - Core SCB Register
bogdanm 64:e3affc9e7238 210 - Core SysTick Register
bogdanm 64:e3affc9e7238 211 ******************************************************************************/
bogdanm 64:e3affc9e7238 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 64:e3affc9e7238 213 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 64:e3affc9e7238 214 */
bogdanm 64:e3affc9e7238 215
bogdanm 64:e3affc9e7238 216 /** \ingroup CMSIS_core_register
bogdanm 64:e3affc9e7238 217 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 64:e3affc9e7238 218 \brief Core Register type definitions.
bogdanm 64:e3affc9e7238 219 @{
bogdanm 64:e3affc9e7238 220 */
bogdanm 64:e3affc9e7238 221
bogdanm 64:e3affc9e7238 222 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 64:e3affc9e7238 223 */
bogdanm 64:e3affc9e7238 224 typedef union
bogdanm 64:e3affc9e7238 225 {
bogdanm 64:e3affc9e7238 226 struct
bogdanm 64:e3affc9e7238 227 {
Kojto 110:165afa46840b 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
bogdanm 64:e3affc9e7238 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 64:e3affc9e7238 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 64:e3affc9e7238 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 64:e3affc9e7238 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 64:e3affc9e7238 233 } b; /*!< Structure used for bit access */
bogdanm 64:e3affc9e7238 234 uint32_t w; /*!< Type used for word access */
bogdanm 64:e3affc9e7238 235 } APSR_Type;
bogdanm 64:e3affc9e7238 236
Kojto 110:165afa46840b 237 /* APSR Register Definitions */
Kojto 110:165afa46840b 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 240
Kojto 110:165afa46840b 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 243
Kojto 110:165afa46840b 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 246
Kojto 110:165afa46840b 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 249
bogdanm 64:e3affc9e7238 250
bogdanm 64:e3affc9e7238 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 64:e3affc9e7238 252 */
bogdanm 64:e3affc9e7238 253 typedef union
bogdanm 64:e3affc9e7238 254 {
bogdanm 64:e3affc9e7238 255 struct
bogdanm 64:e3affc9e7238 256 {
bogdanm 64:e3affc9e7238 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 64:e3affc9e7238 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 64:e3affc9e7238 259 } b; /*!< Structure used for bit access */
bogdanm 64:e3affc9e7238 260 uint32_t w; /*!< Type used for word access */
bogdanm 64:e3affc9e7238 261 } IPSR_Type;
bogdanm 64:e3affc9e7238 262
Kojto 110:165afa46840b 263 /* IPSR Register Definitions */
Kojto 110:165afa46840b 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 266
bogdanm 64:e3affc9e7238 267
bogdanm 64:e3affc9e7238 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 64:e3affc9e7238 269 */
bogdanm 64:e3affc9e7238 270 typedef union
bogdanm 64:e3affc9e7238 271 {
bogdanm 64:e3affc9e7238 272 struct
bogdanm 64:e3affc9e7238 273 {
bogdanm 64:e3affc9e7238 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 64:e3affc9e7238 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 64:e3affc9e7238 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
bogdanm 64:e3affc9e7238 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 64:e3affc9e7238 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 64:e3affc9e7238 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 64:e3affc9e7238 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 64:e3affc9e7238 282 } b; /*!< Structure used for bit access */
bogdanm 64:e3affc9e7238 283 uint32_t w; /*!< Type used for word access */
bogdanm 64:e3affc9e7238 284 } xPSR_Type;
bogdanm 64:e3affc9e7238 285
Kojto 110:165afa46840b 286 /* xPSR Register Definitions */
Kojto 110:165afa46840b 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 289
Kojto 110:165afa46840b 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 292
Kojto 110:165afa46840b 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 295
Kojto 110:165afa46840b 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 298
Kojto 110:165afa46840b 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 301
Kojto 110:165afa46840b 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 304
bogdanm 64:e3affc9e7238 305
bogdanm 64:e3affc9e7238 306 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 64:e3affc9e7238 307 */
bogdanm 64:e3affc9e7238 308 typedef union
bogdanm 64:e3affc9e7238 309 {
bogdanm 64:e3affc9e7238 310 struct
bogdanm 64:e3affc9e7238 311 {
Kojto 110:165afa46840b 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
bogdanm 64:e3affc9e7238 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 64:e3affc9e7238 315 } b; /*!< Structure used for bit access */
bogdanm 64:e3affc9e7238 316 uint32_t w; /*!< Type used for word access */
bogdanm 64:e3affc9e7238 317 } CONTROL_Type;
bogdanm 64:e3affc9e7238 318
Kojto 110:165afa46840b 319 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 322
bogdanm 64:e3affc9e7238 323 /*@} end of group CMSIS_CORE */
bogdanm 64:e3affc9e7238 324
bogdanm 64:e3affc9e7238 325
bogdanm 64:e3affc9e7238 326 /** \ingroup CMSIS_core_register
bogdanm 64:e3affc9e7238 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 64:e3affc9e7238 328 \brief Type definitions for the NVIC Registers
bogdanm 64:e3affc9e7238 329 @{
bogdanm 64:e3affc9e7238 330 */
bogdanm 64:e3affc9e7238 331
bogdanm 64:e3affc9e7238 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 64:e3affc9e7238 333 */
bogdanm 64:e3affc9e7238 334 typedef struct
bogdanm 64:e3affc9e7238 335 {
bogdanm 64:e3affc9e7238 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 64:e3affc9e7238 337 uint32_t RESERVED0[31];
bogdanm 64:e3affc9e7238 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 64:e3affc9e7238 339 uint32_t RSERVED1[31];
bogdanm 64:e3affc9e7238 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 64:e3affc9e7238 341 uint32_t RESERVED2[31];
bogdanm 64:e3affc9e7238 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 64:e3affc9e7238 343 uint32_t RESERVED3[31];
bogdanm 64:e3affc9e7238 344 uint32_t RESERVED4[64];
bogdanm 64:e3affc9e7238 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 64:e3affc9e7238 346 } NVIC_Type;
bogdanm 64:e3affc9e7238 347
bogdanm 64:e3affc9e7238 348 /*@} end of group CMSIS_NVIC */
bogdanm 64:e3affc9e7238 349
bogdanm 64:e3affc9e7238 350
bogdanm 64:e3affc9e7238 351 /** \ingroup CMSIS_core_register
bogdanm 64:e3affc9e7238 352 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 64:e3affc9e7238 353 \brief Type definitions for the System Control Block Registers
bogdanm 64:e3affc9e7238 354 @{
bogdanm 64:e3affc9e7238 355 */
bogdanm 64:e3affc9e7238 356
bogdanm 64:e3affc9e7238 357 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 64:e3affc9e7238 358 */
bogdanm 64:e3affc9e7238 359 typedef struct
bogdanm 64:e3affc9e7238 360 {
bogdanm 64:e3affc9e7238 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 64:e3affc9e7238 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 64:e3affc9e7238 363 uint32_t RESERVED0;
bogdanm 64:e3affc9e7238 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 64:e3affc9e7238 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 64:e3affc9e7238 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 64:e3affc9e7238 367 uint32_t RESERVED1;
bogdanm 64:e3affc9e7238 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 64:e3affc9e7238 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 64:e3affc9e7238 370 } SCB_Type;
bogdanm 64:e3affc9e7238 371
bogdanm 64:e3affc9e7238 372 /* SCB CPUID Register Definitions */
bogdanm 64:e3affc9e7238 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 64:e3affc9e7238 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 64:e3affc9e7238 375
bogdanm 64:e3affc9e7238 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 64:e3affc9e7238 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 64:e3affc9e7238 378
bogdanm 64:e3affc9e7238 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 64:e3affc9e7238 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 64:e3affc9e7238 381
bogdanm 64:e3affc9e7238 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 64:e3affc9e7238 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 64:e3affc9e7238 384
bogdanm 64:e3affc9e7238 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 64:e3affc9e7238 387
bogdanm 64:e3affc9e7238 388 /* SCB Interrupt Control State Register Definitions */
bogdanm 64:e3affc9e7238 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 64:e3affc9e7238 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 64:e3affc9e7238 391
bogdanm 64:e3affc9e7238 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 64:e3affc9e7238 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 64:e3affc9e7238 394
bogdanm 64:e3affc9e7238 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 64:e3affc9e7238 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 64:e3affc9e7238 397
bogdanm 64:e3affc9e7238 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 64:e3affc9e7238 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 64:e3affc9e7238 400
bogdanm 64:e3affc9e7238 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 64:e3affc9e7238 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 64:e3affc9e7238 403
bogdanm 64:e3affc9e7238 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 64:e3affc9e7238 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 64:e3affc9e7238 406
bogdanm 64:e3affc9e7238 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 64:e3affc9e7238 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 64:e3affc9e7238 409
bogdanm 64:e3affc9e7238 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 64:e3affc9e7238 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 64:e3affc9e7238 412
bogdanm 64:e3affc9e7238 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 64:e3affc9e7238 415
bogdanm 64:e3affc9e7238 416 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 64:e3affc9e7238 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 64:e3affc9e7238 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 64:e3affc9e7238 419
bogdanm 64:e3affc9e7238 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 64:e3affc9e7238 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 64:e3affc9e7238 422
bogdanm 64:e3affc9e7238 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 64:e3affc9e7238 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 64:e3affc9e7238 425
bogdanm 64:e3affc9e7238 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 64:e3affc9e7238 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 64:e3affc9e7238 428
bogdanm 64:e3affc9e7238 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 64:e3affc9e7238 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 64:e3affc9e7238 431
bogdanm 64:e3affc9e7238 432 /* SCB System Control Register Definitions */
bogdanm 64:e3affc9e7238 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 64:e3affc9e7238 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 64:e3affc9e7238 435
bogdanm 64:e3affc9e7238 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 64:e3affc9e7238 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 64:e3affc9e7238 438
bogdanm 64:e3affc9e7238 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 64:e3affc9e7238 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 64:e3affc9e7238 441
bogdanm 64:e3affc9e7238 442 /* SCB Configuration Control Register Definitions */
bogdanm 64:e3affc9e7238 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 64:e3affc9e7238 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 64:e3affc9e7238 445
bogdanm 64:e3affc9e7238 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 64:e3affc9e7238 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 64:e3affc9e7238 448
bogdanm 64:e3affc9e7238 449 /* SCB System Handler Control and State Register Definitions */
bogdanm 64:e3affc9e7238 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 64:e3affc9e7238 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 64:e3affc9e7238 452
bogdanm 64:e3affc9e7238 453 /*@} end of group CMSIS_SCB */
bogdanm 64:e3affc9e7238 454
bogdanm 64:e3affc9e7238 455
bogdanm 64:e3affc9e7238 456 /** \ingroup CMSIS_core_register
bogdanm 64:e3affc9e7238 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 64:e3affc9e7238 458 \brief Type definitions for the System Timer Registers.
bogdanm 64:e3affc9e7238 459 @{
bogdanm 64:e3affc9e7238 460 */
bogdanm 64:e3affc9e7238 461
bogdanm 64:e3affc9e7238 462 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 64:e3affc9e7238 463 */
bogdanm 64:e3affc9e7238 464 typedef struct
bogdanm 64:e3affc9e7238 465 {
bogdanm 64:e3affc9e7238 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 64:e3affc9e7238 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 64:e3affc9e7238 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 64:e3affc9e7238 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 64:e3affc9e7238 470 } SysTick_Type;
bogdanm 64:e3affc9e7238 471
bogdanm 64:e3affc9e7238 472 /* SysTick Control / Status Register Definitions */
bogdanm 64:e3affc9e7238 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 64:e3affc9e7238 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 64:e3affc9e7238 475
bogdanm 64:e3affc9e7238 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 64:e3affc9e7238 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 64:e3affc9e7238 478
bogdanm 64:e3affc9e7238 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 64:e3affc9e7238 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 64:e3affc9e7238 481
bogdanm 64:e3affc9e7238 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 64:e3affc9e7238 484
bogdanm 64:e3affc9e7238 485 /* SysTick Reload Register Definitions */
bogdanm 64:e3affc9e7238 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 64:e3affc9e7238 488
bogdanm 64:e3affc9e7238 489 /* SysTick Current Register Definitions */
bogdanm 64:e3affc9e7238 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 64:e3affc9e7238 492
bogdanm 64:e3affc9e7238 493 /* SysTick Calibration Register Definitions */
bogdanm 64:e3affc9e7238 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 64:e3affc9e7238 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 64:e3affc9e7238 496
bogdanm 64:e3affc9e7238 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 64:e3affc9e7238 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 64:e3affc9e7238 499
bogdanm 64:e3affc9e7238 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 64:e3affc9e7238 502
bogdanm 64:e3affc9e7238 503 /*@} end of group CMSIS_SysTick */
bogdanm 64:e3affc9e7238 504
bogdanm 64:e3affc9e7238 505
bogdanm 64:e3affc9e7238 506 /** \ingroup CMSIS_core_register
bogdanm 64:e3affc9e7238 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 64:e3affc9e7238 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 64:e3affc9e7238 509 are only accessible over DAP and not via processor. Therefore
bogdanm 64:e3affc9e7238 510 they are not covered by the Cortex-M0 header file.
bogdanm 64:e3affc9e7238 511 @{
bogdanm 64:e3affc9e7238 512 */
bogdanm 64:e3affc9e7238 513 /*@} end of group CMSIS_CoreDebug */
bogdanm 64:e3affc9e7238 514
bogdanm 64:e3affc9e7238 515
bogdanm 64:e3affc9e7238 516 /** \ingroup CMSIS_core_register
bogdanm 64:e3affc9e7238 517 \defgroup CMSIS_core_base Core Definitions
bogdanm 64:e3affc9e7238 518 \brief Definitions for base addresses, unions, and structures.
bogdanm 64:e3affc9e7238 519 @{
bogdanm 64:e3affc9e7238 520 */
bogdanm 64:e3affc9e7238 521
bogdanm 64:e3affc9e7238 522 /* Memory mapping of Cortex-M0 Hardware */
bogdanm 64:e3affc9e7238 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 64:e3affc9e7238 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 64:e3affc9e7238 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 64:e3affc9e7238 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 64:e3affc9e7238 527
bogdanm 64:e3affc9e7238 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 64:e3affc9e7238 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 64:e3affc9e7238 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 64:e3affc9e7238 531
bogdanm 64:e3affc9e7238 532
bogdanm 64:e3affc9e7238 533 /*@} */
bogdanm 64:e3affc9e7238 534
bogdanm 64:e3affc9e7238 535
bogdanm 64:e3affc9e7238 536
bogdanm 64:e3affc9e7238 537 /*******************************************************************************
bogdanm 64:e3affc9e7238 538 * Hardware Abstraction Layer
bogdanm 64:e3affc9e7238 539 Core Function Interface contains:
bogdanm 64:e3affc9e7238 540 - Core NVIC Functions
bogdanm 64:e3affc9e7238 541 - Core SysTick Functions
bogdanm 64:e3affc9e7238 542 - Core Register Access Functions
bogdanm 64:e3affc9e7238 543 ******************************************************************************/
bogdanm 64:e3affc9e7238 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 64:e3affc9e7238 545 */
bogdanm 64:e3affc9e7238 546
bogdanm 64:e3affc9e7238 547
bogdanm 64:e3affc9e7238 548
bogdanm 64:e3affc9e7238 549 /* ########################## NVIC functions #################################### */
bogdanm 64:e3affc9e7238 550 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 64:e3affc9e7238 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 64:e3affc9e7238 552 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 64:e3affc9e7238 553 @{
bogdanm 64:e3affc9e7238 554 */
bogdanm 64:e3affc9e7238 555
bogdanm 64:e3affc9e7238 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 64:e3affc9e7238 557 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
bogdanm 64:e3affc9e7238 561
bogdanm 64:e3affc9e7238 562
bogdanm 64:e3affc9e7238 563 /** \brief Enable External Interrupt
bogdanm 64:e3affc9e7238 564
bogdanm 64:e3affc9e7238 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 64:e3affc9e7238 566
bogdanm 64:e3affc9e7238 567 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 64:e3affc9e7238 568 */
bogdanm 64:e3affc9e7238 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 64:e3affc9e7238 570 {
Kojto 110:165afa46840b 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 64:e3affc9e7238 572 }
bogdanm 64:e3affc9e7238 573
bogdanm 64:e3affc9e7238 574
bogdanm 64:e3affc9e7238 575 /** \brief Disable External Interrupt
bogdanm 64:e3affc9e7238 576
bogdanm 64:e3affc9e7238 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 64:e3affc9e7238 578
bogdanm 64:e3affc9e7238 579 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 64:e3affc9e7238 580 */
bogdanm 64:e3affc9e7238 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 64:e3affc9e7238 582 {
Kojto 110:165afa46840b 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 64:e3affc9e7238 584 }
bogdanm 64:e3affc9e7238 585
bogdanm 64:e3affc9e7238 586
bogdanm 64:e3affc9e7238 587 /** \brief Get Pending Interrupt
bogdanm 64:e3affc9e7238 588
bogdanm 64:e3affc9e7238 589 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 64:e3affc9e7238 590 for the specified interrupt.
bogdanm 64:e3affc9e7238 591
bogdanm 64:e3affc9e7238 592 \param [in] IRQn Interrupt number.
bogdanm 64:e3affc9e7238 593
bogdanm 64:e3affc9e7238 594 \return 0 Interrupt status is not pending.
bogdanm 64:e3affc9e7238 595 \return 1 Interrupt status is pending.
bogdanm 64:e3affc9e7238 596 */
bogdanm 64:e3affc9e7238 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 64:e3affc9e7238 598 {
Kojto 110:165afa46840b 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 64:e3affc9e7238 600 }
bogdanm 64:e3affc9e7238 601
bogdanm 64:e3affc9e7238 602
bogdanm 64:e3affc9e7238 603 /** \brief Set Pending Interrupt
bogdanm 64:e3affc9e7238 604
bogdanm 64:e3affc9e7238 605 The function sets the pending bit of an external interrupt.
bogdanm 64:e3affc9e7238 606
bogdanm 64:e3affc9e7238 607 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 64:e3affc9e7238 608 */
bogdanm 64:e3affc9e7238 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 64:e3affc9e7238 610 {
Kojto 110:165afa46840b 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 64:e3affc9e7238 612 }
bogdanm 64:e3affc9e7238 613
bogdanm 64:e3affc9e7238 614
bogdanm 64:e3affc9e7238 615 /** \brief Clear Pending Interrupt
bogdanm 64:e3affc9e7238 616
bogdanm 64:e3affc9e7238 617 The function clears the pending bit of an external interrupt.
bogdanm 64:e3affc9e7238 618
bogdanm 64:e3affc9e7238 619 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 64:e3affc9e7238 620 */
bogdanm 64:e3affc9e7238 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 64:e3affc9e7238 622 {
Kojto 110:165afa46840b 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 64:e3affc9e7238 624 }
bogdanm 64:e3affc9e7238 625
bogdanm 64:e3affc9e7238 626
bogdanm 64:e3affc9e7238 627 /** \brief Set Interrupt Priority
bogdanm 64:e3affc9e7238 628
bogdanm 64:e3affc9e7238 629 The function sets the priority of an interrupt.
bogdanm 64:e3affc9e7238 630
bogdanm 64:e3affc9e7238 631 \note The priority cannot be set for every core interrupt.
bogdanm 64:e3affc9e7238 632
bogdanm 64:e3affc9e7238 633 \param [in] IRQn Interrupt number.
bogdanm 64:e3affc9e7238 634 \param [in] priority Priority to set.
bogdanm 64:e3affc9e7238 635 */
bogdanm 64:e3affc9e7238 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 64:e3affc9e7238 637 {
Kojto 110:165afa46840b 638 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 641 }
bogdanm 64:e3affc9e7238 642 else {
Kojto 110:165afa46840b 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 645 }
bogdanm 64:e3affc9e7238 646 }
bogdanm 64:e3affc9e7238 647
bogdanm 64:e3affc9e7238 648
bogdanm 64:e3affc9e7238 649 /** \brief Get Interrupt Priority
bogdanm 64:e3affc9e7238 650
bogdanm 64:e3affc9e7238 651 The function reads the priority of an interrupt. The interrupt
bogdanm 64:e3affc9e7238 652 number can be positive to specify an external (device specific)
bogdanm 64:e3affc9e7238 653 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 64:e3affc9e7238 654
bogdanm 64:e3affc9e7238 655
bogdanm 64:e3affc9e7238 656 \param [in] IRQn Interrupt number.
bogdanm 64:e3affc9e7238 657 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 64:e3affc9e7238 658 priority bits of the microcontroller.
bogdanm 64:e3affc9e7238 659 */
bogdanm 64:e3affc9e7238 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 64:e3affc9e7238 661 {
bogdanm 64:e3affc9e7238 662
Kojto 110:165afa46840b 663 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 665 }
bogdanm 64:e3affc9e7238 666 else {
Kojto 110:165afa46840b 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 668 }
bogdanm 64:e3affc9e7238 669 }
bogdanm 64:e3affc9e7238 670
bogdanm 64:e3affc9e7238 671
bogdanm 64:e3affc9e7238 672 /** \brief System Reset
bogdanm 64:e3affc9e7238 673
bogdanm 64:e3affc9e7238 674 The function initiates a system reset request to reset the MCU.
bogdanm 64:e3affc9e7238 675 */
bogdanm 64:e3affc9e7238 676 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 64:e3affc9e7238 677 {
bogdanm 64:e3affc9e7238 678 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 64:e3affc9e7238 679 buffered write are completed before reset */
Kojto 110:165afa46840b 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 64:e3affc9e7238 681 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 64:e3affc9e7238 682 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 683 while(1) { __NOP(); } /* wait until reset */
bogdanm 64:e3affc9e7238 684 }
bogdanm 64:e3affc9e7238 685
bogdanm 64:e3affc9e7238 686 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 64:e3affc9e7238 687
bogdanm 64:e3affc9e7238 688
bogdanm 64:e3affc9e7238 689
bogdanm 64:e3affc9e7238 690 /* ################################## SysTick function ############################################ */
bogdanm 64:e3affc9e7238 691 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 64:e3affc9e7238 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 64:e3affc9e7238 693 \brief Functions that configure the System.
bogdanm 64:e3affc9e7238 694 @{
bogdanm 64:e3affc9e7238 695 */
bogdanm 64:e3affc9e7238 696
bogdanm 64:e3affc9e7238 697 #if (__Vendor_SysTickConfig == 0)
bogdanm 64:e3affc9e7238 698
bogdanm 64:e3affc9e7238 699 /** \brief System Tick Configuration
bogdanm 64:e3affc9e7238 700
bogdanm 64:e3affc9e7238 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 64:e3affc9e7238 702 Counter is in free running mode to generate periodic interrupts.
bogdanm 64:e3affc9e7238 703
bogdanm 64:e3affc9e7238 704 \param [in] ticks Number of ticks between two interrupts.
bogdanm 64:e3affc9e7238 705
bogdanm 64:e3affc9e7238 706 \return 0 Function succeeded.
bogdanm 64:e3affc9e7238 707 \return 1 Function failed.
bogdanm 64:e3affc9e7238 708
bogdanm 64:e3affc9e7238 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 64:e3affc9e7238 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 64:e3affc9e7238 711 must contain a vendor-specific implementation of this function.
bogdanm 64:e3affc9e7238 712
bogdanm 64:e3affc9e7238 713 */
bogdanm 64:e3affc9e7238 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 64:e3affc9e7238 715 {
Kojto 110:165afa46840b 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
bogdanm 64:e3affc9e7238 717
Kojto 110:165afa46840b 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 64:e3affc9e7238 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 64:e3affc9e7238 722 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 724 return (0UL); /* Function successful */
bogdanm 64:e3affc9e7238 725 }
bogdanm 64:e3affc9e7238 726
bogdanm 64:e3affc9e7238 727 #endif
bogdanm 64:e3affc9e7238 728
bogdanm 64:e3affc9e7238 729 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 64:e3affc9e7238 730
bogdanm 64:e3affc9e7238 731
bogdanm 64:e3affc9e7238 732
bogdanm 64:e3affc9e7238 733
Kojto 110:165afa46840b 734 #ifdef __cplusplus
Kojto 110:165afa46840b 735 }
Kojto 110:165afa46840b 736 #endif
Kojto 110:165afa46840b 737
bogdanm 64:e3affc9e7238 738 #endif /* __CORE_CM0_H_DEPENDANT */
bogdanm 64:e3affc9e7238 739
bogdanm 64:e3affc9e7238 740 #endif /* __CMSIS_GENERIC */