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Fork of mbed by
TARGET_LPC1549/core_cm0plus.h@110:165afa46840b, 2015-11-25 (annotated)
- Committer:
- Kojto
- Date:
- Wed Nov 25 13:21:40 2015 +0000
- Revision:
- 110:165afa46840b
- Parent:
- 79:0c05e21ae27e
Release 110 of the mbed library
Changes:
- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI
- Nucleo L476 - gcc and uvision template
- k22,k64f targets - ADC channels A addition
- EFM32 - bugfixes in sleep, serial and spi
- Delta DFCM NNN40 - pinnames update
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 79:0c05e21ae27e | 1 | /**************************************************************************//** |
emilmont | 79:0c05e21ae27e | 2 | * @file core_cm0plus.h |
emilmont | 79:0c05e21ae27e | 3 | * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File |
Kojto | 110:165afa46840b | 4 | * @version V4.10 |
Kojto | 110:165afa46840b | 5 | * @date 18. March 2015 |
emilmont | 79:0c05e21ae27e | 6 | * |
emilmont | 79:0c05e21ae27e | 7 | * @note |
emilmont | 79:0c05e21ae27e | 8 | * |
emilmont | 79:0c05e21ae27e | 9 | ******************************************************************************/ |
Kojto | 110:165afa46840b | 10 | /* Copyright (c) 2009 - 2015 ARM LIMITED |
emilmont | 79:0c05e21ae27e | 11 | |
emilmont | 79:0c05e21ae27e | 12 | All rights reserved. |
emilmont | 79:0c05e21ae27e | 13 | Redistribution and use in source and binary forms, with or without |
emilmont | 79:0c05e21ae27e | 14 | modification, are permitted provided that the following conditions are met: |
emilmont | 79:0c05e21ae27e | 15 | - Redistributions of source code must retain the above copyright |
emilmont | 79:0c05e21ae27e | 16 | notice, this list of conditions and the following disclaimer. |
emilmont | 79:0c05e21ae27e | 17 | - Redistributions in binary form must reproduce the above copyright |
emilmont | 79:0c05e21ae27e | 18 | notice, this list of conditions and the following disclaimer in the |
emilmont | 79:0c05e21ae27e | 19 | documentation and/or other materials provided with the distribution. |
emilmont | 79:0c05e21ae27e | 20 | - Neither the name of ARM nor the names of its contributors may be used |
emilmont | 79:0c05e21ae27e | 21 | to endorse or promote products derived from this software without |
emilmont | 79:0c05e21ae27e | 22 | specific prior written permission. |
emilmont | 79:0c05e21ae27e | 23 | * |
emilmont | 79:0c05e21ae27e | 24 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
emilmont | 79:0c05e21ae27e | 25 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
emilmont | 79:0c05e21ae27e | 26 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
emilmont | 79:0c05e21ae27e | 27 | ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE |
emilmont | 79:0c05e21ae27e | 28 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
emilmont | 79:0c05e21ae27e | 29 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
emilmont | 79:0c05e21ae27e | 30 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
emilmont | 79:0c05e21ae27e | 31 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
emilmont | 79:0c05e21ae27e | 32 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
emilmont | 79:0c05e21ae27e | 33 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
emilmont | 79:0c05e21ae27e | 34 | POSSIBILITY OF SUCH DAMAGE. |
emilmont | 79:0c05e21ae27e | 35 | ---------------------------------------------------------------------------*/ |
emilmont | 79:0c05e21ae27e | 36 | |
emilmont | 79:0c05e21ae27e | 37 | |
emilmont | 79:0c05e21ae27e | 38 | #if defined ( __ICCARM__ ) |
emilmont | 79:0c05e21ae27e | 39 | #pragma system_include /* treat file as system include file for MISRA check */ |
emilmont | 79:0c05e21ae27e | 40 | #endif |
emilmont | 79:0c05e21ae27e | 41 | |
Kojto | 110:165afa46840b | 42 | #ifndef __CORE_CM0PLUS_H_GENERIC |
Kojto | 110:165afa46840b | 43 | #define __CORE_CM0PLUS_H_GENERIC |
Kojto | 110:165afa46840b | 44 | |
emilmont | 79:0c05e21ae27e | 45 | #ifdef __cplusplus |
emilmont | 79:0c05e21ae27e | 46 | extern "C" { |
emilmont | 79:0c05e21ae27e | 47 | #endif |
emilmont | 79:0c05e21ae27e | 48 | |
emilmont | 79:0c05e21ae27e | 49 | /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions |
emilmont | 79:0c05e21ae27e | 50 | CMSIS violates the following MISRA-C:2004 rules: |
emilmont | 79:0c05e21ae27e | 51 | |
emilmont | 79:0c05e21ae27e | 52 | \li Required Rule 8.5, object/function definition in header file.<br> |
emilmont | 79:0c05e21ae27e | 53 | Function definitions in header files are used to allow 'inlining'. |
emilmont | 79:0c05e21ae27e | 54 | |
emilmont | 79:0c05e21ae27e | 55 | \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br> |
emilmont | 79:0c05e21ae27e | 56 | Unions are used for effective representation of core registers. |
emilmont | 79:0c05e21ae27e | 57 | |
emilmont | 79:0c05e21ae27e | 58 | \li Advisory Rule 19.7, Function-like macro defined.<br> |
emilmont | 79:0c05e21ae27e | 59 | Function-like macros are used to allow more efficient code. |
emilmont | 79:0c05e21ae27e | 60 | */ |
emilmont | 79:0c05e21ae27e | 61 | |
emilmont | 79:0c05e21ae27e | 62 | |
emilmont | 79:0c05e21ae27e | 63 | /******************************************************************************* |
emilmont | 79:0c05e21ae27e | 64 | * CMSIS definitions |
emilmont | 79:0c05e21ae27e | 65 | ******************************************************************************/ |
emilmont | 79:0c05e21ae27e | 66 | /** \ingroup Cortex-M0+ |
emilmont | 79:0c05e21ae27e | 67 | @{ |
emilmont | 79:0c05e21ae27e | 68 | */ |
emilmont | 79:0c05e21ae27e | 69 | |
emilmont | 79:0c05e21ae27e | 70 | /* CMSIS CM0P definitions */ |
Kojto | 110:165afa46840b | 71 | #define __CM0PLUS_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */ |
Kojto | 110:165afa46840b | 72 | #define __CM0PLUS_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */ |
emilmont | 79:0c05e21ae27e | 73 | #define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \ |
emilmont | 79:0c05e21ae27e | 74 | __CM0PLUS_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */ |
emilmont | 79:0c05e21ae27e | 75 | |
emilmont | 79:0c05e21ae27e | 76 | #define __CORTEX_M (0x00) /*!< Cortex-M Core */ |
emilmont | 79:0c05e21ae27e | 77 | |
emilmont | 79:0c05e21ae27e | 78 | |
emilmont | 79:0c05e21ae27e | 79 | #if defined ( __CC_ARM ) |
emilmont | 79:0c05e21ae27e | 80 | #define __ASM __asm /*!< asm keyword for ARM Compiler */ |
emilmont | 79:0c05e21ae27e | 81 | #define __INLINE __inline /*!< inline keyword for ARM Compiler */ |
emilmont | 79:0c05e21ae27e | 82 | #define __STATIC_INLINE static __inline |
emilmont | 79:0c05e21ae27e | 83 | |
Kojto | 110:165afa46840b | 84 | #elif defined ( __GNUC__ ) |
Kojto | 110:165afa46840b | 85 | #define __ASM __asm /*!< asm keyword for GNU Compiler */ |
Kojto | 110:165afa46840b | 86 | #define __INLINE inline /*!< inline keyword for GNU Compiler */ |
Kojto | 110:165afa46840b | 87 | #define __STATIC_INLINE static inline |
Kojto | 110:165afa46840b | 88 | |
emilmont | 79:0c05e21ae27e | 89 | #elif defined ( __ICCARM__ ) |
emilmont | 79:0c05e21ae27e | 90 | #define __ASM __asm /*!< asm keyword for IAR Compiler */ |
emilmont | 79:0c05e21ae27e | 91 | #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */ |
emilmont | 79:0c05e21ae27e | 92 | #define __STATIC_INLINE static inline |
emilmont | 79:0c05e21ae27e | 93 | |
Kojto | 110:165afa46840b | 94 | #elif defined ( __TMS470__ ) |
Kojto | 110:165afa46840b | 95 | #define __ASM __asm /*!< asm keyword for TI CCS Compiler */ |
emilmont | 79:0c05e21ae27e | 96 | #define __STATIC_INLINE static inline |
emilmont | 79:0c05e21ae27e | 97 | |
emilmont | 79:0c05e21ae27e | 98 | #elif defined ( __TASKING__ ) |
emilmont | 79:0c05e21ae27e | 99 | #define __ASM __asm /*!< asm keyword for TASKING Compiler */ |
emilmont | 79:0c05e21ae27e | 100 | #define __INLINE inline /*!< inline keyword for TASKING Compiler */ |
emilmont | 79:0c05e21ae27e | 101 | #define __STATIC_INLINE static inline |
emilmont | 79:0c05e21ae27e | 102 | |
Kojto | 110:165afa46840b | 103 | #elif defined ( __CSMC__ ) |
Kojto | 110:165afa46840b | 104 | #define __packed |
Kojto | 110:165afa46840b | 105 | #define __ASM _asm /*!< asm keyword for COSMIC Compiler */ |
Kojto | 110:165afa46840b | 106 | #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */ |
Kojto | 110:165afa46840b | 107 | #define __STATIC_INLINE static inline |
Kojto | 110:165afa46840b | 108 | |
emilmont | 79:0c05e21ae27e | 109 | #endif |
emilmont | 79:0c05e21ae27e | 110 | |
Kojto | 110:165afa46840b | 111 | /** __FPU_USED indicates whether an FPU is used or not. |
Kojto | 110:165afa46840b | 112 | This core does not support an FPU at all |
emilmont | 79:0c05e21ae27e | 113 | */ |
emilmont | 79:0c05e21ae27e | 114 | #define __FPU_USED 0 |
emilmont | 79:0c05e21ae27e | 115 | |
emilmont | 79:0c05e21ae27e | 116 | #if defined ( __CC_ARM ) |
emilmont | 79:0c05e21ae27e | 117 | #if defined __TARGET_FPU_VFP |
emilmont | 79:0c05e21ae27e | 118 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emilmont | 79:0c05e21ae27e | 119 | #endif |
emilmont | 79:0c05e21ae27e | 120 | |
Kojto | 110:165afa46840b | 121 | #elif defined ( __GNUC__ ) |
Kojto | 110:165afa46840b | 122 | #if defined (__VFP_FP__) && !defined(__SOFTFP__) |
Kojto | 110:165afa46840b | 123 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 110:165afa46840b | 124 | #endif |
Kojto | 110:165afa46840b | 125 | |
emilmont | 79:0c05e21ae27e | 126 | #elif defined ( __ICCARM__ ) |
emilmont | 79:0c05e21ae27e | 127 | #if defined __ARMVFP__ |
emilmont | 79:0c05e21ae27e | 128 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emilmont | 79:0c05e21ae27e | 129 | #endif |
emilmont | 79:0c05e21ae27e | 130 | |
Kojto | 110:165afa46840b | 131 | #elif defined ( __TMS470__ ) |
Kojto | 110:165afa46840b | 132 | #if defined __TI__VFP_SUPPORT____ |
emilmont | 79:0c05e21ae27e | 133 | #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emilmont | 79:0c05e21ae27e | 134 | #endif |
emilmont | 79:0c05e21ae27e | 135 | |
emilmont | 79:0c05e21ae27e | 136 | #elif defined ( __TASKING__ ) |
emilmont | 79:0c05e21ae27e | 137 | #if defined __FPU_VFP__ |
emilmont | 79:0c05e21ae27e | 138 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
emilmont | 79:0c05e21ae27e | 139 | #endif |
Kojto | 110:165afa46840b | 140 | |
Kojto | 110:165afa46840b | 141 | #elif defined ( __CSMC__ ) /* Cosmic */ |
Kojto | 110:165afa46840b | 142 | #if ( __CSMC__ & 0x400) // FPU present for parser |
Kojto | 110:165afa46840b | 143 | #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" |
Kojto | 110:165afa46840b | 144 | #endif |
emilmont | 79:0c05e21ae27e | 145 | #endif |
emilmont | 79:0c05e21ae27e | 146 | |
emilmont | 79:0c05e21ae27e | 147 | #include <stdint.h> /* standard types definitions */ |
emilmont | 79:0c05e21ae27e | 148 | #include <core_cmInstr.h> /* Core Instruction Access */ |
emilmont | 79:0c05e21ae27e | 149 | #include <core_cmFunc.h> /* Core Function Access */ |
emilmont | 79:0c05e21ae27e | 150 | |
Kojto | 110:165afa46840b | 151 | #ifdef __cplusplus |
Kojto | 110:165afa46840b | 152 | } |
Kojto | 110:165afa46840b | 153 | #endif |
Kojto | 110:165afa46840b | 154 | |
emilmont | 79:0c05e21ae27e | 155 | #endif /* __CORE_CM0PLUS_H_GENERIC */ |
emilmont | 79:0c05e21ae27e | 156 | |
emilmont | 79:0c05e21ae27e | 157 | #ifndef __CMSIS_GENERIC |
emilmont | 79:0c05e21ae27e | 158 | |
emilmont | 79:0c05e21ae27e | 159 | #ifndef __CORE_CM0PLUS_H_DEPENDANT |
emilmont | 79:0c05e21ae27e | 160 | #define __CORE_CM0PLUS_H_DEPENDANT |
emilmont | 79:0c05e21ae27e | 161 | |
Kojto | 110:165afa46840b | 162 | #ifdef __cplusplus |
Kojto | 110:165afa46840b | 163 | extern "C" { |
Kojto | 110:165afa46840b | 164 | #endif |
Kojto | 110:165afa46840b | 165 | |
emilmont | 79:0c05e21ae27e | 166 | /* check device defines and use defaults */ |
emilmont | 79:0c05e21ae27e | 167 | #if defined __CHECK_DEVICE_DEFINES |
emilmont | 79:0c05e21ae27e | 168 | #ifndef __CM0PLUS_REV |
emilmont | 79:0c05e21ae27e | 169 | #define __CM0PLUS_REV 0x0000 |
emilmont | 79:0c05e21ae27e | 170 | #warning "__CM0PLUS_REV not defined in device header file; using default!" |
emilmont | 79:0c05e21ae27e | 171 | #endif |
emilmont | 79:0c05e21ae27e | 172 | |
emilmont | 79:0c05e21ae27e | 173 | #ifndef __MPU_PRESENT |
emilmont | 79:0c05e21ae27e | 174 | #define __MPU_PRESENT 0 |
emilmont | 79:0c05e21ae27e | 175 | #warning "__MPU_PRESENT not defined in device header file; using default!" |
emilmont | 79:0c05e21ae27e | 176 | #endif |
emilmont | 79:0c05e21ae27e | 177 | |
emilmont | 79:0c05e21ae27e | 178 | #ifndef __VTOR_PRESENT |
emilmont | 79:0c05e21ae27e | 179 | #define __VTOR_PRESENT 0 |
emilmont | 79:0c05e21ae27e | 180 | #warning "__VTOR_PRESENT not defined in device header file; using default!" |
emilmont | 79:0c05e21ae27e | 181 | #endif |
emilmont | 79:0c05e21ae27e | 182 | |
emilmont | 79:0c05e21ae27e | 183 | #ifndef __NVIC_PRIO_BITS |
emilmont | 79:0c05e21ae27e | 184 | #define __NVIC_PRIO_BITS 2 |
emilmont | 79:0c05e21ae27e | 185 | #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" |
emilmont | 79:0c05e21ae27e | 186 | #endif |
emilmont | 79:0c05e21ae27e | 187 | |
emilmont | 79:0c05e21ae27e | 188 | #ifndef __Vendor_SysTickConfig |
emilmont | 79:0c05e21ae27e | 189 | #define __Vendor_SysTickConfig 0 |
emilmont | 79:0c05e21ae27e | 190 | #warning "__Vendor_SysTickConfig not defined in device header file; using default!" |
emilmont | 79:0c05e21ae27e | 191 | #endif |
emilmont | 79:0c05e21ae27e | 192 | #endif |
emilmont | 79:0c05e21ae27e | 193 | |
emilmont | 79:0c05e21ae27e | 194 | /* IO definitions (access restrictions to peripheral registers) */ |
emilmont | 79:0c05e21ae27e | 195 | /** |
emilmont | 79:0c05e21ae27e | 196 | \defgroup CMSIS_glob_defs CMSIS Global Defines |
emilmont | 79:0c05e21ae27e | 197 | |
emilmont | 79:0c05e21ae27e | 198 | <strong>IO Type Qualifiers</strong> are used |
emilmont | 79:0c05e21ae27e | 199 | \li to specify the access to peripheral variables. |
emilmont | 79:0c05e21ae27e | 200 | \li for automatic generation of peripheral register debug information. |
emilmont | 79:0c05e21ae27e | 201 | */ |
emilmont | 79:0c05e21ae27e | 202 | #ifdef __cplusplus |
emilmont | 79:0c05e21ae27e | 203 | #define __I volatile /*!< Defines 'read only' permissions */ |
emilmont | 79:0c05e21ae27e | 204 | #else |
emilmont | 79:0c05e21ae27e | 205 | #define __I volatile const /*!< Defines 'read only' permissions */ |
emilmont | 79:0c05e21ae27e | 206 | #endif |
emilmont | 79:0c05e21ae27e | 207 | #define __O volatile /*!< Defines 'write only' permissions */ |
emilmont | 79:0c05e21ae27e | 208 | #define __IO volatile /*!< Defines 'read / write' permissions */ |
emilmont | 79:0c05e21ae27e | 209 | |
emilmont | 79:0c05e21ae27e | 210 | /*@} end of group Cortex-M0+ */ |
emilmont | 79:0c05e21ae27e | 211 | |
emilmont | 79:0c05e21ae27e | 212 | |
emilmont | 79:0c05e21ae27e | 213 | |
emilmont | 79:0c05e21ae27e | 214 | /******************************************************************************* |
emilmont | 79:0c05e21ae27e | 215 | * Register Abstraction |
emilmont | 79:0c05e21ae27e | 216 | Core Register contain: |
emilmont | 79:0c05e21ae27e | 217 | - Core Register |
emilmont | 79:0c05e21ae27e | 218 | - Core NVIC Register |
emilmont | 79:0c05e21ae27e | 219 | - Core SCB Register |
emilmont | 79:0c05e21ae27e | 220 | - Core SysTick Register |
emilmont | 79:0c05e21ae27e | 221 | - Core MPU Register |
emilmont | 79:0c05e21ae27e | 222 | ******************************************************************************/ |
emilmont | 79:0c05e21ae27e | 223 | /** \defgroup CMSIS_core_register Defines and Type Definitions |
emilmont | 79:0c05e21ae27e | 224 | \brief Type definitions and defines for Cortex-M processor based devices. |
emilmont | 79:0c05e21ae27e | 225 | */ |
emilmont | 79:0c05e21ae27e | 226 | |
emilmont | 79:0c05e21ae27e | 227 | /** \ingroup CMSIS_core_register |
emilmont | 79:0c05e21ae27e | 228 | \defgroup CMSIS_CORE Status and Control Registers |
emilmont | 79:0c05e21ae27e | 229 | \brief Core Register type definitions. |
emilmont | 79:0c05e21ae27e | 230 | @{ |
emilmont | 79:0c05e21ae27e | 231 | */ |
emilmont | 79:0c05e21ae27e | 232 | |
emilmont | 79:0c05e21ae27e | 233 | /** \brief Union type to access the Application Program Status Register (APSR). |
emilmont | 79:0c05e21ae27e | 234 | */ |
emilmont | 79:0c05e21ae27e | 235 | typedef union |
emilmont | 79:0c05e21ae27e | 236 | { |
emilmont | 79:0c05e21ae27e | 237 | struct |
emilmont | 79:0c05e21ae27e | 238 | { |
Kojto | 110:165afa46840b | 239 | uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ |
emilmont | 79:0c05e21ae27e | 240 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
emilmont | 79:0c05e21ae27e | 241 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
emilmont | 79:0c05e21ae27e | 242 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
emilmont | 79:0c05e21ae27e | 243 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
emilmont | 79:0c05e21ae27e | 244 | } b; /*!< Structure used for bit access */ |
emilmont | 79:0c05e21ae27e | 245 | uint32_t w; /*!< Type used for word access */ |
emilmont | 79:0c05e21ae27e | 246 | } APSR_Type; |
emilmont | 79:0c05e21ae27e | 247 | |
Kojto | 110:165afa46840b | 248 | /* APSR Register Definitions */ |
Kojto | 110:165afa46840b | 249 | #define APSR_N_Pos 31 /*!< APSR: N Position */ |
Kojto | 110:165afa46840b | 250 | #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ |
Kojto | 110:165afa46840b | 251 | |
Kojto | 110:165afa46840b | 252 | #define APSR_Z_Pos 30 /*!< APSR: Z Position */ |
Kojto | 110:165afa46840b | 253 | #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ |
Kojto | 110:165afa46840b | 254 | |
Kojto | 110:165afa46840b | 255 | #define APSR_C_Pos 29 /*!< APSR: C Position */ |
Kojto | 110:165afa46840b | 256 | #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ |
Kojto | 110:165afa46840b | 257 | |
Kojto | 110:165afa46840b | 258 | #define APSR_V_Pos 28 /*!< APSR: V Position */ |
Kojto | 110:165afa46840b | 259 | #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ |
Kojto | 110:165afa46840b | 260 | |
emilmont | 79:0c05e21ae27e | 261 | |
emilmont | 79:0c05e21ae27e | 262 | /** \brief Union type to access the Interrupt Program Status Register (IPSR). |
emilmont | 79:0c05e21ae27e | 263 | */ |
emilmont | 79:0c05e21ae27e | 264 | typedef union |
emilmont | 79:0c05e21ae27e | 265 | { |
emilmont | 79:0c05e21ae27e | 266 | struct |
emilmont | 79:0c05e21ae27e | 267 | { |
emilmont | 79:0c05e21ae27e | 268 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
emilmont | 79:0c05e21ae27e | 269 | uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ |
emilmont | 79:0c05e21ae27e | 270 | } b; /*!< Structure used for bit access */ |
emilmont | 79:0c05e21ae27e | 271 | uint32_t w; /*!< Type used for word access */ |
emilmont | 79:0c05e21ae27e | 272 | } IPSR_Type; |
emilmont | 79:0c05e21ae27e | 273 | |
Kojto | 110:165afa46840b | 274 | /* IPSR Register Definitions */ |
Kojto | 110:165afa46840b | 275 | #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */ |
Kojto | 110:165afa46840b | 276 | #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ |
Kojto | 110:165afa46840b | 277 | |
emilmont | 79:0c05e21ae27e | 278 | |
emilmont | 79:0c05e21ae27e | 279 | /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR). |
emilmont | 79:0c05e21ae27e | 280 | */ |
emilmont | 79:0c05e21ae27e | 281 | typedef union |
emilmont | 79:0c05e21ae27e | 282 | { |
emilmont | 79:0c05e21ae27e | 283 | struct |
emilmont | 79:0c05e21ae27e | 284 | { |
emilmont | 79:0c05e21ae27e | 285 | uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ |
emilmont | 79:0c05e21ae27e | 286 | uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ |
emilmont | 79:0c05e21ae27e | 287 | uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ |
Kojto | 110:165afa46840b | 288 | uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ |
emilmont | 79:0c05e21ae27e | 289 | uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ |
emilmont | 79:0c05e21ae27e | 290 | uint32_t C:1; /*!< bit: 29 Carry condition code flag */ |
emilmont | 79:0c05e21ae27e | 291 | uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ |
emilmont | 79:0c05e21ae27e | 292 | uint32_t N:1; /*!< bit: 31 Negative condition code flag */ |
emilmont | 79:0c05e21ae27e | 293 | } b; /*!< Structure used for bit access */ |
emilmont | 79:0c05e21ae27e | 294 | uint32_t w; /*!< Type used for word access */ |
emilmont | 79:0c05e21ae27e | 295 | } xPSR_Type; |
emilmont | 79:0c05e21ae27e | 296 | |
Kojto | 110:165afa46840b | 297 | /* xPSR Register Definitions */ |
Kojto | 110:165afa46840b | 298 | #define xPSR_N_Pos 31 /*!< xPSR: N Position */ |
Kojto | 110:165afa46840b | 299 | #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ |
Kojto | 110:165afa46840b | 300 | |
Kojto | 110:165afa46840b | 301 | #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */ |
Kojto | 110:165afa46840b | 302 | #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ |
Kojto | 110:165afa46840b | 303 | |
Kojto | 110:165afa46840b | 304 | #define xPSR_C_Pos 29 /*!< xPSR: C Position */ |
Kojto | 110:165afa46840b | 305 | #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ |
Kojto | 110:165afa46840b | 306 | |
Kojto | 110:165afa46840b | 307 | #define xPSR_V_Pos 28 /*!< xPSR: V Position */ |
Kojto | 110:165afa46840b | 308 | #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ |
Kojto | 110:165afa46840b | 309 | |
Kojto | 110:165afa46840b | 310 | #define xPSR_T_Pos 24 /*!< xPSR: T Position */ |
Kojto | 110:165afa46840b | 311 | #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ |
Kojto | 110:165afa46840b | 312 | |
Kojto | 110:165afa46840b | 313 | #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */ |
Kojto | 110:165afa46840b | 314 | #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ |
Kojto | 110:165afa46840b | 315 | |
emilmont | 79:0c05e21ae27e | 316 | |
emilmont | 79:0c05e21ae27e | 317 | /** \brief Union type to access the Control Registers (CONTROL). |
emilmont | 79:0c05e21ae27e | 318 | */ |
emilmont | 79:0c05e21ae27e | 319 | typedef union |
emilmont | 79:0c05e21ae27e | 320 | { |
emilmont | 79:0c05e21ae27e | 321 | struct |
emilmont | 79:0c05e21ae27e | 322 | { |
emilmont | 79:0c05e21ae27e | 323 | uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ |
emilmont | 79:0c05e21ae27e | 324 | uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ |
Kojto | 110:165afa46840b | 325 | uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ |
emilmont | 79:0c05e21ae27e | 326 | } b; /*!< Structure used for bit access */ |
emilmont | 79:0c05e21ae27e | 327 | uint32_t w; /*!< Type used for word access */ |
emilmont | 79:0c05e21ae27e | 328 | } CONTROL_Type; |
emilmont | 79:0c05e21ae27e | 329 | |
Kojto | 110:165afa46840b | 330 | /* CONTROL Register Definitions */ |
Kojto | 110:165afa46840b | 331 | #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */ |
Kojto | 110:165afa46840b | 332 | #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ |
Kojto | 110:165afa46840b | 333 | |
Kojto | 110:165afa46840b | 334 | #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */ |
Kojto | 110:165afa46840b | 335 | #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ |
Kojto | 110:165afa46840b | 336 | |
emilmont | 79:0c05e21ae27e | 337 | /*@} end of group CMSIS_CORE */ |
emilmont | 79:0c05e21ae27e | 338 | |
emilmont | 79:0c05e21ae27e | 339 | |
emilmont | 79:0c05e21ae27e | 340 | /** \ingroup CMSIS_core_register |
emilmont | 79:0c05e21ae27e | 341 | \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) |
emilmont | 79:0c05e21ae27e | 342 | \brief Type definitions for the NVIC Registers |
emilmont | 79:0c05e21ae27e | 343 | @{ |
emilmont | 79:0c05e21ae27e | 344 | */ |
emilmont | 79:0c05e21ae27e | 345 | |
emilmont | 79:0c05e21ae27e | 346 | /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). |
emilmont | 79:0c05e21ae27e | 347 | */ |
emilmont | 79:0c05e21ae27e | 348 | typedef struct |
emilmont | 79:0c05e21ae27e | 349 | { |
emilmont | 79:0c05e21ae27e | 350 | __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ |
emilmont | 79:0c05e21ae27e | 351 | uint32_t RESERVED0[31]; |
emilmont | 79:0c05e21ae27e | 352 | __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ |
emilmont | 79:0c05e21ae27e | 353 | uint32_t RSERVED1[31]; |
emilmont | 79:0c05e21ae27e | 354 | __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ |
emilmont | 79:0c05e21ae27e | 355 | uint32_t RESERVED2[31]; |
emilmont | 79:0c05e21ae27e | 356 | __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ |
emilmont | 79:0c05e21ae27e | 357 | uint32_t RESERVED3[31]; |
emilmont | 79:0c05e21ae27e | 358 | uint32_t RESERVED4[64]; |
emilmont | 79:0c05e21ae27e | 359 | __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ |
emilmont | 79:0c05e21ae27e | 360 | } NVIC_Type; |
emilmont | 79:0c05e21ae27e | 361 | |
emilmont | 79:0c05e21ae27e | 362 | /*@} end of group CMSIS_NVIC */ |
emilmont | 79:0c05e21ae27e | 363 | |
emilmont | 79:0c05e21ae27e | 364 | |
emilmont | 79:0c05e21ae27e | 365 | /** \ingroup CMSIS_core_register |
emilmont | 79:0c05e21ae27e | 366 | \defgroup CMSIS_SCB System Control Block (SCB) |
emilmont | 79:0c05e21ae27e | 367 | \brief Type definitions for the System Control Block Registers |
emilmont | 79:0c05e21ae27e | 368 | @{ |
emilmont | 79:0c05e21ae27e | 369 | */ |
emilmont | 79:0c05e21ae27e | 370 | |
emilmont | 79:0c05e21ae27e | 371 | /** \brief Structure type to access the System Control Block (SCB). |
emilmont | 79:0c05e21ae27e | 372 | */ |
emilmont | 79:0c05e21ae27e | 373 | typedef struct |
emilmont | 79:0c05e21ae27e | 374 | { |
emilmont | 79:0c05e21ae27e | 375 | __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ |
emilmont | 79:0c05e21ae27e | 376 | __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ |
emilmont | 79:0c05e21ae27e | 377 | #if (__VTOR_PRESENT == 1) |
emilmont | 79:0c05e21ae27e | 378 | __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ |
emilmont | 79:0c05e21ae27e | 379 | #else |
emilmont | 79:0c05e21ae27e | 380 | uint32_t RESERVED0; |
emilmont | 79:0c05e21ae27e | 381 | #endif |
emilmont | 79:0c05e21ae27e | 382 | __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ |
emilmont | 79:0c05e21ae27e | 383 | __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ |
emilmont | 79:0c05e21ae27e | 384 | __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ |
emilmont | 79:0c05e21ae27e | 385 | uint32_t RESERVED1; |
emilmont | 79:0c05e21ae27e | 386 | __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ |
emilmont | 79:0c05e21ae27e | 387 | __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ |
emilmont | 79:0c05e21ae27e | 388 | } SCB_Type; |
emilmont | 79:0c05e21ae27e | 389 | |
emilmont | 79:0c05e21ae27e | 390 | /* SCB CPUID Register Definitions */ |
emilmont | 79:0c05e21ae27e | 391 | #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */ |
emilmont | 79:0c05e21ae27e | 392 | #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ |
emilmont | 79:0c05e21ae27e | 393 | |
emilmont | 79:0c05e21ae27e | 394 | #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */ |
emilmont | 79:0c05e21ae27e | 395 | #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ |
emilmont | 79:0c05e21ae27e | 396 | |
emilmont | 79:0c05e21ae27e | 397 | #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */ |
emilmont | 79:0c05e21ae27e | 398 | #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ |
emilmont | 79:0c05e21ae27e | 399 | |
emilmont | 79:0c05e21ae27e | 400 | #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */ |
emilmont | 79:0c05e21ae27e | 401 | #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ |
emilmont | 79:0c05e21ae27e | 402 | |
emilmont | 79:0c05e21ae27e | 403 | #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */ |
Kojto | 110:165afa46840b | 404 | #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ |
emilmont | 79:0c05e21ae27e | 405 | |
emilmont | 79:0c05e21ae27e | 406 | /* SCB Interrupt Control State Register Definitions */ |
emilmont | 79:0c05e21ae27e | 407 | #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */ |
emilmont | 79:0c05e21ae27e | 408 | #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ |
emilmont | 79:0c05e21ae27e | 409 | |
emilmont | 79:0c05e21ae27e | 410 | #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */ |
emilmont | 79:0c05e21ae27e | 411 | #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ |
emilmont | 79:0c05e21ae27e | 412 | |
emilmont | 79:0c05e21ae27e | 413 | #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */ |
emilmont | 79:0c05e21ae27e | 414 | #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ |
emilmont | 79:0c05e21ae27e | 415 | |
emilmont | 79:0c05e21ae27e | 416 | #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */ |
emilmont | 79:0c05e21ae27e | 417 | #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ |
emilmont | 79:0c05e21ae27e | 418 | |
emilmont | 79:0c05e21ae27e | 419 | #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */ |
emilmont | 79:0c05e21ae27e | 420 | #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ |
emilmont | 79:0c05e21ae27e | 421 | |
emilmont | 79:0c05e21ae27e | 422 | #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */ |
emilmont | 79:0c05e21ae27e | 423 | #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ |
emilmont | 79:0c05e21ae27e | 424 | |
emilmont | 79:0c05e21ae27e | 425 | #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */ |
emilmont | 79:0c05e21ae27e | 426 | #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ |
emilmont | 79:0c05e21ae27e | 427 | |
emilmont | 79:0c05e21ae27e | 428 | #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */ |
emilmont | 79:0c05e21ae27e | 429 | #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ |
emilmont | 79:0c05e21ae27e | 430 | |
emilmont | 79:0c05e21ae27e | 431 | #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */ |
Kojto | 110:165afa46840b | 432 | #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ |
emilmont | 79:0c05e21ae27e | 433 | |
emilmont | 79:0c05e21ae27e | 434 | #if (__VTOR_PRESENT == 1) |
emilmont | 79:0c05e21ae27e | 435 | /* SCB Interrupt Control State Register Definitions */ |
emilmont | 79:0c05e21ae27e | 436 | #define SCB_VTOR_TBLOFF_Pos 8 /*!< SCB VTOR: TBLOFF Position */ |
emilmont | 79:0c05e21ae27e | 437 | #define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ |
emilmont | 79:0c05e21ae27e | 438 | #endif |
emilmont | 79:0c05e21ae27e | 439 | |
emilmont | 79:0c05e21ae27e | 440 | /* SCB Application Interrupt and Reset Control Register Definitions */ |
emilmont | 79:0c05e21ae27e | 441 | #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */ |
emilmont | 79:0c05e21ae27e | 442 | #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ |
emilmont | 79:0c05e21ae27e | 443 | |
emilmont | 79:0c05e21ae27e | 444 | #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */ |
emilmont | 79:0c05e21ae27e | 445 | #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ |
emilmont | 79:0c05e21ae27e | 446 | |
emilmont | 79:0c05e21ae27e | 447 | #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */ |
emilmont | 79:0c05e21ae27e | 448 | #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ |
emilmont | 79:0c05e21ae27e | 449 | |
emilmont | 79:0c05e21ae27e | 450 | #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */ |
emilmont | 79:0c05e21ae27e | 451 | #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ |
emilmont | 79:0c05e21ae27e | 452 | |
emilmont | 79:0c05e21ae27e | 453 | #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */ |
emilmont | 79:0c05e21ae27e | 454 | #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ |
emilmont | 79:0c05e21ae27e | 455 | |
emilmont | 79:0c05e21ae27e | 456 | /* SCB System Control Register Definitions */ |
emilmont | 79:0c05e21ae27e | 457 | #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */ |
emilmont | 79:0c05e21ae27e | 458 | #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ |
emilmont | 79:0c05e21ae27e | 459 | |
emilmont | 79:0c05e21ae27e | 460 | #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */ |
emilmont | 79:0c05e21ae27e | 461 | #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ |
emilmont | 79:0c05e21ae27e | 462 | |
emilmont | 79:0c05e21ae27e | 463 | #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */ |
emilmont | 79:0c05e21ae27e | 464 | #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ |
emilmont | 79:0c05e21ae27e | 465 | |
emilmont | 79:0c05e21ae27e | 466 | /* SCB Configuration Control Register Definitions */ |
emilmont | 79:0c05e21ae27e | 467 | #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */ |
emilmont | 79:0c05e21ae27e | 468 | #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ |
emilmont | 79:0c05e21ae27e | 469 | |
emilmont | 79:0c05e21ae27e | 470 | #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */ |
emilmont | 79:0c05e21ae27e | 471 | #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ |
emilmont | 79:0c05e21ae27e | 472 | |
emilmont | 79:0c05e21ae27e | 473 | /* SCB System Handler Control and State Register Definitions */ |
emilmont | 79:0c05e21ae27e | 474 | #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */ |
emilmont | 79:0c05e21ae27e | 475 | #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ |
emilmont | 79:0c05e21ae27e | 476 | |
emilmont | 79:0c05e21ae27e | 477 | /*@} end of group CMSIS_SCB */ |
emilmont | 79:0c05e21ae27e | 478 | |
emilmont | 79:0c05e21ae27e | 479 | |
emilmont | 79:0c05e21ae27e | 480 | /** \ingroup CMSIS_core_register |
emilmont | 79:0c05e21ae27e | 481 | \defgroup CMSIS_SysTick System Tick Timer (SysTick) |
emilmont | 79:0c05e21ae27e | 482 | \brief Type definitions for the System Timer Registers. |
emilmont | 79:0c05e21ae27e | 483 | @{ |
emilmont | 79:0c05e21ae27e | 484 | */ |
emilmont | 79:0c05e21ae27e | 485 | |
emilmont | 79:0c05e21ae27e | 486 | /** \brief Structure type to access the System Timer (SysTick). |
emilmont | 79:0c05e21ae27e | 487 | */ |
emilmont | 79:0c05e21ae27e | 488 | typedef struct |
emilmont | 79:0c05e21ae27e | 489 | { |
emilmont | 79:0c05e21ae27e | 490 | __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ |
emilmont | 79:0c05e21ae27e | 491 | __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ |
emilmont | 79:0c05e21ae27e | 492 | __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ |
emilmont | 79:0c05e21ae27e | 493 | __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ |
emilmont | 79:0c05e21ae27e | 494 | } SysTick_Type; |
emilmont | 79:0c05e21ae27e | 495 | |
emilmont | 79:0c05e21ae27e | 496 | /* SysTick Control / Status Register Definitions */ |
emilmont | 79:0c05e21ae27e | 497 | #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */ |
emilmont | 79:0c05e21ae27e | 498 | #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ |
emilmont | 79:0c05e21ae27e | 499 | |
emilmont | 79:0c05e21ae27e | 500 | #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */ |
emilmont | 79:0c05e21ae27e | 501 | #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ |
emilmont | 79:0c05e21ae27e | 502 | |
emilmont | 79:0c05e21ae27e | 503 | #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */ |
emilmont | 79:0c05e21ae27e | 504 | #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ |
emilmont | 79:0c05e21ae27e | 505 | |
emilmont | 79:0c05e21ae27e | 506 | #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */ |
Kojto | 110:165afa46840b | 507 | #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ |
emilmont | 79:0c05e21ae27e | 508 | |
emilmont | 79:0c05e21ae27e | 509 | /* SysTick Reload Register Definitions */ |
emilmont | 79:0c05e21ae27e | 510 | #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */ |
Kojto | 110:165afa46840b | 511 | #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ |
emilmont | 79:0c05e21ae27e | 512 | |
emilmont | 79:0c05e21ae27e | 513 | /* SysTick Current Register Definitions */ |
emilmont | 79:0c05e21ae27e | 514 | #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */ |
Kojto | 110:165afa46840b | 515 | #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ |
emilmont | 79:0c05e21ae27e | 516 | |
emilmont | 79:0c05e21ae27e | 517 | /* SysTick Calibration Register Definitions */ |
emilmont | 79:0c05e21ae27e | 518 | #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */ |
emilmont | 79:0c05e21ae27e | 519 | #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ |
emilmont | 79:0c05e21ae27e | 520 | |
emilmont | 79:0c05e21ae27e | 521 | #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */ |
emilmont | 79:0c05e21ae27e | 522 | #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ |
emilmont | 79:0c05e21ae27e | 523 | |
emilmont | 79:0c05e21ae27e | 524 | #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */ |
Kojto | 110:165afa46840b | 525 | #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ |
emilmont | 79:0c05e21ae27e | 526 | |
emilmont | 79:0c05e21ae27e | 527 | /*@} end of group CMSIS_SysTick */ |
emilmont | 79:0c05e21ae27e | 528 | |
emilmont | 79:0c05e21ae27e | 529 | #if (__MPU_PRESENT == 1) |
emilmont | 79:0c05e21ae27e | 530 | /** \ingroup CMSIS_core_register |
emilmont | 79:0c05e21ae27e | 531 | \defgroup CMSIS_MPU Memory Protection Unit (MPU) |
emilmont | 79:0c05e21ae27e | 532 | \brief Type definitions for the Memory Protection Unit (MPU) |
emilmont | 79:0c05e21ae27e | 533 | @{ |
emilmont | 79:0c05e21ae27e | 534 | */ |
emilmont | 79:0c05e21ae27e | 535 | |
emilmont | 79:0c05e21ae27e | 536 | /** \brief Structure type to access the Memory Protection Unit (MPU). |
emilmont | 79:0c05e21ae27e | 537 | */ |
emilmont | 79:0c05e21ae27e | 538 | typedef struct |
emilmont | 79:0c05e21ae27e | 539 | { |
emilmont | 79:0c05e21ae27e | 540 | __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ |
emilmont | 79:0c05e21ae27e | 541 | __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ |
emilmont | 79:0c05e21ae27e | 542 | __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ |
emilmont | 79:0c05e21ae27e | 543 | __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ |
emilmont | 79:0c05e21ae27e | 544 | __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ |
emilmont | 79:0c05e21ae27e | 545 | } MPU_Type; |
emilmont | 79:0c05e21ae27e | 546 | |
emilmont | 79:0c05e21ae27e | 547 | /* MPU Type Register */ |
emilmont | 79:0c05e21ae27e | 548 | #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */ |
emilmont | 79:0c05e21ae27e | 549 | #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ |
emilmont | 79:0c05e21ae27e | 550 | |
emilmont | 79:0c05e21ae27e | 551 | #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */ |
emilmont | 79:0c05e21ae27e | 552 | #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ |
emilmont | 79:0c05e21ae27e | 553 | |
emilmont | 79:0c05e21ae27e | 554 | #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */ |
Kojto | 110:165afa46840b | 555 | #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ |
emilmont | 79:0c05e21ae27e | 556 | |
emilmont | 79:0c05e21ae27e | 557 | /* MPU Control Register */ |
emilmont | 79:0c05e21ae27e | 558 | #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */ |
emilmont | 79:0c05e21ae27e | 559 | #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ |
emilmont | 79:0c05e21ae27e | 560 | |
emilmont | 79:0c05e21ae27e | 561 | #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */ |
emilmont | 79:0c05e21ae27e | 562 | #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ |
emilmont | 79:0c05e21ae27e | 563 | |
emilmont | 79:0c05e21ae27e | 564 | #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */ |
Kojto | 110:165afa46840b | 565 | #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ |
emilmont | 79:0c05e21ae27e | 566 | |
emilmont | 79:0c05e21ae27e | 567 | /* MPU Region Number Register */ |
emilmont | 79:0c05e21ae27e | 568 | #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */ |
Kojto | 110:165afa46840b | 569 | #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ |
emilmont | 79:0c05e21ae27e | 570 | |
emilmont | 79:0c05e21ae27e | 571 | /* MPU Region Base Address Register */ |
emilmont | 79:0c05e21ae27e | 572 | #define MPU_RBAR_ADDR_Pos 8 /*!< MPU RBAR: ADDR Position */ |
emilmont | 79:0c05e21ae27e | 573 | #define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ |
emilmont | 79:0c05e21ae27e | 574 | |
emilmont | 79:0c05e21ae27e | 575 | #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */ |
emilmont | 79:0c05e21ae27e | 576 | #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ |
emilmont | 79:0c05e21ae27e | 577 | |
emilmont | 79:0c05e21ae27e | 578 | #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */ |
Kojto | 110:165afa46840b | 579 | #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ |
emilmont | 79:0c05e21ae27e | 580 | |
emilmont | 79:0c05e21ae27e | 581 | /* MPU Region Attribute and Size Register */ |
emilmont | 79:0c05e21ae27e | 582 | #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */ |
emilmont | 79:0c05e21ae27e | 583 | #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ |
emilmont | 79:0c05e21ae27e | 584 | |
emilmont | 79:0c05e21ae27e | 585 | #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */ |
emilmont | 79:0c05e21ae27e | 586 | #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ |
emilmont | 79:0c05e21ae27e | 587 | |
emilmont | 79:0c05e21ae27e | 588 | #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */ |
emilmont | 79:0c05e21ae27e | 589 | #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ |
emilmont | 79:0c05e21ae27e | 590 | |
emilmont | 79:0c05e21ae27e | 591 | #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */ |
emilmont | 79:0c05e21ae27e | 592 | #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ |
emilmont | 79:0c05e21ae27e | 593 | |
emilmont | 79:0c05e21ae27e | 594 | #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */ |
emilmont | 79:0c05e21ae27e | 595 | #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ |
emilmont | 79:0c05e21ae27e | 596 | |
emilmont | 79:0c05e21ae27e | 597 | #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */ |
emilmont | 79:0c05e21ae27e | 598 | #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ |
emilmont | 79:0c05e21ae27e | 599 | |
emilmont | 79:0c05e21ae27e | 600 | #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */ |
emilmont | 79:0c05e21ae27e | 601 | #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ |
emilmont | 79:0c05e21ae27e | 602 | |
emilmont | 79:0c05e21ae27e | 603 | #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */ |
emilmont | 79:0c05e21ae27e | 604 | #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ |
emilmont | 79:0c05e21ae27e | 605 | |
emilmont | 79:0c05e21ae27e | 606 | #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */ |
emilmont | 79:0c05e21ae27e | 607 | #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ |
emilmont | 79:0c05e21ae27e | 608 | |
emilmont | 79:0c05e21ae27e | 609 | #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */ |
Kojto | 110:165afa46840b | 610 | #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ |
emilmont | 79:0c05e21ae27e | 611 | |
emilmont | 79:0c05e21ae27e | 612 | /*@} end of group CMSIS_MPU */ |
emilmont | 79:0c05e21ae27e | 613 | #endif |
emilmont | 79:0c05e21ae27e | 614 | |
emilmont | 79:0c05e21ae27e | 615 | |
emilmont | 79:0c05e21ae27e | 616 | /** \ingroup CMSIS_core_register |
emilmont | 79:0c05e21ae27e | 617 | \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) |
emilmont | 79:0c05e21ae27e | 618 | \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) |
emilmont | 79:0c05e21ae27e | 619 | are only accessible over DAP and not via processor. Therefore |
emilmont | 79:0c05e21ae27e | 620 | they are not covered by the Cortex-M0 header file. |
emilmont | 79:0c05e21ae27e | 621 | @{ |
emilmont | 79:0c05e21ae27e | 622 | */ |
emilmont | 79:0c05e21ae27e | 623 | /*@} end of group CMSIS_CoreDebug */ |
emilmont | 79:0c05e21ae27e | 624 | |
emilmont | 79:0c05e21ae27e | 625 | |
emilmont | 79:0c05e21ae27e | 626 | /** \ingroup CMSIS_core_register |
emilmont | 79:0c05e21ae27e | 627 | \defgroup CMSIS_core_base Core Definitions |
emilmont | 79:0c05e21ae27e | 628 | \brief Definitions for base addresses, unions, and structures. |
emilmont | 79:0c05e21ae27e | 629 | @{ |
emilmont | 79:0c05e21ae27e | 630 | */ |
emilmont | 79:0c05e21ae27e | 631 | |
emilmont | 79:0c05e21ae27e | 632 | /* Memory mapping of Cortex-M0+ Hardware */ |
emilmont | 79:0c05e21ae27e | 633 | #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ |
emilmont | 79:0c05e21ae27e | 634 | #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ |
emilmont | 79:0c05e21ae27e | 635 | #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ |
emilmont | 79:0c05e21ae27e | 636 | #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ |
emilmont | 79:0c05e21ae27e | 637 | |
emilmont | 79:0c05e21ae27e | 638 | #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ |
emilmont | 79:0c05e21ae27e | 639 | #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ |
emilmont | 79:0c05e21ae27e | 640 | #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ |
emilmont | 79:0c05e21ae27e | 641 | |
emilmont | 79:0c05e21ae27e | 642 | #if (__MPU_PRESENT == 1) |
emilmont | 79:0c05e21ae27e | 643 | #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ |
emilmont | 79:0c05e21ae27e | 644 | #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ |
emilmont | 79:0c05e21ae27e | 645 | #endif |
emilmont | 79:0c05e21ae27e | 646 | |
emilmont | 79:0c05e21ae27e | 647 | /*@} */ |
emilmont | 79:0c05e21ae27e | 648 | |
emilmont | 79:0c05e21ae27e | 649 | |
emilmont | 79:0c05e21ae27e | 650 | |
emilmont | 79:0c05e21ae27e | 651 | /******************************************************************************* |
emilmont | 79:0c05e21ae27e | 652 | * Hardware Abstraction Layer |
emilmont | 79:0c05e21ae27e | 653 | Core Function Interface contains: |
emilmont | 79:0c05e21ae27e | 654 | - Core NVIC Functions |
emilmont | 79:0c05e21ae27e | 655 | - Core SysTick Functions |
emilmont | 79:0c05e21ae27e | 656 | - Core Register Access Functions |
emilmont | 79:0c05e21ae27e | 657 | ******************************************************************************/ |
emilmont | 79:0c05e21ae27e | 658 | /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference |
emilmont | 79:0c05e21ae27e | 659 | */ |
emilmont | 79:0c05e21ae27e | 660 | |
emilmont | 79:0c05e21ae27e | 661 | |
emilmont | 79:0c05e21ae27e | 662 | |
emilmont | 79:0c05e21ae27e | 663 | /* ########################## NVIC functions #################################### */ |
emilmont | 79:0c05e21ae27e | 664 | /** \ingroup CMSIS_Core_FunctionInterface |
emilmont | 79:0c05e21ae27e | 665 | \defgroup CMSIS_Core_NVICFunctions NVIC Functions |
emilmont | 79:0c05e21ae27e | 666 | \brief Functions that manage interrupts and exceptions via the NVIC. |
emilmont | 79:0c05e21ae27e | 667 | @{ |
emilmont | 79:0c05e21ae27e | 668 | */ |
emilmont | 79:0c05e21ae27e | 669 | |
emilmont | 79:0c05e21ae27e | 670 | /* Interrupt Priorities are WORD accessible only under ARMv6M */ |
emilmont | 79:0c05e21ae27e | 671 | /* The following MACROS handle generation of the register offset and byte masks */ |
Kojto | 110:165afa46840b | 672 | #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) |
Kojto | 110:165afa46840b | 673 | #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) |
Kojto | 110:165afa46840b | 674 | #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) |
emilmont | 79:0c05e21ae27e | 675 | |
emilmont | 79:0c05e21ae27e | 676 | |
emilmont | 79:0c05e21ae27e | 677 | /** \brief Enable External Interrupt |
emilmont | 79:0c05e21ae27e | 678 | |
emilmont | 79:0c05e21ae27e | 679 | The function enables a device-specific interrupt in the NVIC interrupt controller. |
emilmont | 79:0c05e21ae27e | 680 | |
emilmont | 79:0c05e21ae27e | 681 | \param [in] IRQn External interrupt number. Value cannot be negative. |
emilmont | 79:0c05e21ae27e | 682 | */ |
emilmont | 79:0c05e21ae27e | 683 | __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn) |
emilmont | 79:0c05e21ae27e | 684 | { |
Kojto | 110:165afa46840b | 685 | NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
emilmont | 79:0c05e21ae27e | 686 | } |
emilmont | 79:0c05e21ae27e | 687 | |
emilmont | 79:0c05e21ae27e | 688 | |
emilmont | 79:0c05e21ae27e | 689 | /** \brief Disable External Interrupt |
emilmont | 79:0c05e21ae27e | 690 | |
emilmont | 79:0c05e21ae27e | 691 | The function disables a device-specific interrupt in the NVIC interrupt controller. |
emilmont | 79:0c05e21ae27e | 692 | |
emilmont | 79:0c05e21ae27e | 693 | \param [in] IRQn External interrupt number. Value cannot be negative. |
emilmont | 79:0c05e21ae27e | 694 | */ |
emilmont | 79:0c05e21ae27e | 695 | __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn) |
emilmont | 79:0c05e21ae27e | 696 | { |
Kojto | 110:165afa46840b | 697 | NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
emilmont | 79:0c05e21ae27e | 698 | } |
emilmont | 79:0c05e21ae27e | 699 | |
emilmont | 79:0c05e21ae27e | 700 | |
emilmont | 79:0c05e21ae27e | 701 | /** \brief Get Pending Interrupt |
emilmont | 79:0c05e21ae27e | 702 | |
emilmont | 79:0c05e21ae27e | 703 | The function reads the pending register in the NVIC and returns the pending bit |
emilmont | 79:0c05e21ae27e | 704 | for the specified interrupt. |
emilmont | 79:0c05e21ae27e | 705 | |
emilmont | 79:0c05e21ae27e | 706 | \param [in] IRQn Interrupt number. |
emilmont | 79:0c05e21ae27e | 707 | |
emilmont | 79:0c05e21ae27e | 708 | \return 0 Interrupt status is not pending. |
emilmont | 79:0c05e21ae27e | 709 | \return 1 Interrupt status is pending. |
emilmont | 79:0c05e21ae27e | 710 | */ |
emilmont | 79:0c05e21ae27e | 711 | __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn) |
emilmont | 79:0c05e21ae27e | 712 | { |
Kojto | 110:165afa46840b | 713 | return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); |
emilmont | 79:0c05e21ae27e | 714 | } |
emilmont | 79:0c05e21ae27e | 715 | |
emilmont | 79:0c05e21ae27e | 716 | |
emilmont | 79:0c05e21ae27e | 717 | /** \brief Set Pending Interrupt |
emilmont | 79:0c05e21ae27e | 718 | |
emilmont | 79:0c05e21ae27e | 719 | The function sets the pending bit of an external interrupt. |
emilmont | 79:0c05e21ae27e | 720 | |
emilmont | 79:0c05e21ae27e | 721 | \param [in] IRQn Interrupt number. Value cannot be negative. |
emilmont | 79:0c05e21ae27e | 722 | */ |
emilmont | 79:0c05e21ae27e | 723 | __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn) |
emilmont | 79:0c05e21ae27e | 724 | { |
Kojto | 110:165afa46840b | 725 | NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
emilmont | 79:0c05e21ae27e | 726 | } |
emilmont | 79:0c05e21ae27e | 727 | |
emilmont | 79:0c05e21ae27e | 728 | |
emilmont | 79:0c05e21ae27e | 729 | /** \brief Clear Pending Interrupt |
emilmont | 79:0c05e21ae27e | 730 | |
emilmont | 79:0c05e21ae27e | 731 | The function clears the pending bit of an external interrupt. |
emilmont | 79:0c05e21ae27e | 732 | |
emilmont | 79:0c05e21ae27e | 733 | \param [in] IRQn External interrupt number. Value cannot be negative. |
emilmont | 79:0c05e21ae27e | 734 | */ |
emilmont | 79:0c05e21ae27e | 735 | __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn) |
emilmont | 79:0c05e21ae27e | 736 | { |
Kojto | 110:165afa46840b | 737 | NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL)); |
emilmont | 79:0c05e21ae27e | 738 | } |
emilmont | 79:0c05e21ae27e | 739 | |
emilmont | 79:0c05e21ae27e | 740 | |
emilmont | 79:0c05e21ae27e | 741 | /** \brief Set Interrupt Priority |
emilmont | 79:0c05e21ae27e | 742 | |
emilmont | 79:0c05e21ae27e | 743 | The function sets the priority of an interrupt. |
emilmont | 79:0c05e21ae27e | 744 | |
emilmont | 79:0c05e21ae27e | 745 | \note The priority cannot be set for every core interrupt. |
emilmont | 79:0c05e21ae27e | 746 | |
emilmont | 79:0c05e21ae27e | 747 | \param [in] IRQn Interrupt number. |
emilmont | 79:0c05e21ae27e | 748 | \param [in] priority Priority to set. |
emilmont | 79:0c05e21ae27e | 749 | */ |
emilmont | 79:0c05e21ae27e | 750 | __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) |
emilmont | 79:0c05e21ae27e | 751 | { |
Kojto | 110:165afa46840b | 752 | if((int32_t)(IRQn) < 0) { |
Kojto | 110:165afa46840b | 753 | SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
Kojto | 110:165afa46840b | 754 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
Kojto | 110:165afa46840b | 755 | } |
emilmont | 79:0c05e21ae27e | 756 | else { |
Kojto | 110:165afa46840b | 757 | NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | |
Kojto | 110:165afa46840b | 758 | (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); |
Kojto | 110:165afa46840b | 759 | } |
emilmont | 79:0c05e21ae27e | 760 | } |
emilmont | 79:0c05e21ae27e | 761 | |
emilmont | 79:0c05e21ae27e | 762 | |
emilmont | 79:0c05e21ae27e | 763 | /** \brief Get Interrupt Priority |
emilmont | 79:0c05e21ae27e | 764 | |
emilmont | 79:0c05e21ae27e | 765 | The function reads the priority of an interrupt. The interrupt |
emilmont | 79:0c05e21ae27e | 766 | number can be positive to specify an external (device specific) |
emilmont | 79:0c05e21ae27e | 767 | interrupt, or negative to specify an internal (core) interrupt. |
emilmont | 79:0c05e21ae27e | 768 | |
emilmont | 79:0c05e21ae27e | 769 | |
emilmont | 79:0c05e21ae27e | 770 | \param [in] IRQn Interrupt number. |
emilmont | 79:0c05e21ae27e | 771 | \return Interrupt Priority. Value is aligned automatically to the implemented |
emilmont | 79:0c05e21ae27e | 772 | priority bits of the microcontroller. |
emilmont | 79:0c05e21ae27e | 773 | */ |
emilmont | 79:0c05e21ae27e | 774 | __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn) |
emilmont | 79:0c05e21ae27e | 775 | { |
emilmont | 79:0c05e21ae27e | 776 | |
Kojto | 110:165afa46840b | 777 | if((int32_t)(IRQn) < 0) { |
Kojto | 110:165afa46840b | 778 | return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
Kojto | 110:165afa46840b | 779 | } |
emilmont | 79:0c05e21ae27e | 780 | else { |
Kojto | 110:165afa46840b | 781 | return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS))); |
Kojto | 110:165afa46840b | 782 | } |
emilmont | 79:0c05e21ae27e | 783 | } |
emilmont | 79:0c05e21ae27e | 784 | |
emilmont | 79:0c05e21ae27e | 785 | |
emilmont | 79:0c05e21ae27e | 786 | /** \brief System Reset |
emilmont | 79:0c05e21ae27e | 787 | |
emilmont | 79:0c05e21ae27e | 788 | The function initiates a system reset request to reset the MCU. |
emilmont | 79:0c05e21ae27e | 789 | */ |
emilmont | 79:0c05e21ae27e | 790 | __STATIC_INLINE void NVIC_SystemReset(void) |
emilmont | 79:0c05e21ae27e | 791 | { |
emilmont | 79:0c05e21ae27e | 792 | __DSB(); /* Ensure all outstanding memory accesses included |
emilmont | 79:0c05e21ae27e | 793 | buffered write are completed before reset */ |
Kojto | 110:165afa46840b | 794 | SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | |
emilmont | 79:0c05e21ae27e | 795 | SCB_AIRCR_SYSRESETREQ_Msk); |
emilmont | 79:0c05e21ae27e | 796 | __DSB(); /* Ensure completion of memory access */ |
Kojto | 110:165afa46840b | 797 | while(1) { __NOP(); } /* wait until reset */ |
emilmont | 79:0c05e21ae27e | 798 | } |
emilmont | 79:0c05e21ae27e | 799 | |
emilmont | 79:0c05e21ae27e | 800 | /*@} end of CMSIS_Core_NVICFunctions */ |
emilmont | 79:0c05e21ae27e | 801 | |
emilmont | 79:0c05e21ae27e | 802 | |
emilmont | 79:0c05e21ae27e | 803 | |
emilmont | 79:0c05e21ae27e | 804 | /* ################################## SysTick function ############################################ */ |
emilmont | 79:0c05e21ae27e | 805 | /** \ingroup CMSIS_Core_FunctionInterface |
emilmont | 79:0c05e21ae27e | 806 | \defgroup CMSIS_Core_SysTickFunctions SysTick Functions |
emilmont | 79:0c05e21ae27e | 807 | \brief Functions that configure the System. |
emilmont | 79:0c05e21ae27e | 808 | @{ |
emilmont | 79:0c05e21ae27e | 809 | */ |
emilmont | 79:0c05e21ae27e | 810 | |
emilmont | 79:0c05e21ae27e | 811 | #if (__Vendor_SysTickConfig == 0) |
emilmont | 79:0c05e21ae27e | 812 | |
emilmont | 79:0c05e21ae27e | 813 | /** \brief System Tick Configuration |
emilmont | 79:0c05e21ae27e | 814 | |
emilmont | 79:0c05e21ae27e | 815 | The function initializes the System Timer and its interrupt, and starts the System Tick Timer. |
emilmont | 79:0c05e21ae27e | 816 | Counter is in free running mode to generate periodic interrupts. |
emilmont | 79:0c05e21ae27e | 817 | |
emilmont | 79:0c05e21ae27e | 818 | \param [in] ticks Number of ticks between two interrupts. |
emilmont | 79:0c05e21ae27e | 819 | |
emilmont | 79:0c05e21ae27e | 820 | \return 0 Function succeeded. |
emilmont | 79:0c05e21ae27e | 821 | \return 1 Function failed. |
emilmont | 79:0c05e21ae27e | 822 | |
emilmont | 79:0c05e21ae27e | 823 | \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the |
emilmont | 79:0c05e21ae27e | 824 | function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b> |
emilmont | 79:0c05e21ae27e | 825 | must contain a vendor-specific implementation of this function. |
emilmont | 79:0c05e21ae27e | 826 | |
emilmont | 79:0c05e21ae27e | 827 | */ |
emilmont | 79:0c05e21ae27e | 828 | __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) |
emilmont | 79:0c05e21ae27e | 829 | { |
Kojto | 110:165afa46840b | 830 | if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) {return (1UL);} /* Reload value impossible */ |
emilmont | 79:0c05e21ae27e | 831 | |
Kojto | 110:165afa46840b | 832 | SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ |
Kojto | 110:165afa46840b | 833 | NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ |
Kojto | 110:165afa46840b | 834 | SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ |
emilmont | 79:0c05e21ae27e | 835 | SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | |
emilmont | 79:0c05e21ae27e | 836 | SysTick_CTRL_TICKINT_Msk | |
Kojto | 110:165afa46840b | 837 | SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ |
Kojto | 110:165afa46840b | 838 | return (0UL); /* Function successful */ |
emilmont | 79:0c05e21ae27e | 839 | } |
emilmont | 79:0c05e21ae27e | 840 | |
emilmont | 79:0c05e21ae27e | 841 | #endif |
emilmont | 79:0c05e21ae27e | 842 | |
emilmont | 79:0c05e21ae27e | 843 | /*@} end of CMSIS_Core_SysTickFunctions */ |
emilmont | 79:0c05e21ae27e | 844 | |
emilmont | 79:0c05e21ae27e | 845 | |
emilmont | 79:0c05e21ae27e | 846 | |
emilmont | 79:0c05e21ae27e | 847 | |
Kojto | 110:165afa46840b | 848 | #ifdef __cplusplus |
Kojto | 110:165afa46840b | 849 | } |
Kojto | 110:165afa46840b | 850 | #endif |
Kojto | 110:165afa46840b | 851 | |
emilmont | 79:0c05e21ae27e | 852 | #endif /* __CORE_CM0PLUS_H_DEPENDANT */ |
emilmont | 79:0c05e21ae27e | 853 | |
emilmont | 79:0c05e21ae27e | 854 | #endif /* __CMSIS_GENERIC */ |