Ricardo Benitez / mbed

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TARGET_LPC11U68/core_cm0.h@110:165afa46840b, 2015-11-25 (annotated)

Committer:
Kojto
Date:
Wed Nov 25 13:21:40 2015 +0000
Revision:
110:165afa46840b
Parent:
84:0b3ab51c8877 
Release 110  of the mbed library



Changes:

- new platforms - STM32F410R, DISCO_F429ZI, DISCO_F469NI

- Nucleo L476 - gcc and uvision template

- k22,k64f targets - ADC channels A addition

- EFM32 - bugfixes in sleep, serial and spi

- Delta DFCM NNN40 - pinnames update

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**************************************************************************//**
bogdanm 84:0b3ab51c8877 2 * @file core_cm0.h
bogdanm 84:0b3ab51c8877 3 * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
Kojto 110:165afa46840b 4 * @version V4.10
Kojto 110:165afa46840b 5 * @date 18. March 2015
bogdanm 84:0b3ab51c8877 6 *
bogdanm 84:0b3ab51c8877 7 * @note
bogdanm 84:0b3ab51c8877 8 *
bogdanm 84:0b3ab51c8877 9 ******************************************************************************/
Kojto 110:165afa46840b 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
bogdanm 84:0b3ab51c8877 11
bogdanm 84:0b3ab51c8877 12 All rights reserved.
bogdanm 84:0b3ab51c8877 13 Redistribution and use in source and binary forms, with or without
bogdanm 84:0b3ab51c8877 14 modification, are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 - Redistributions of source code must retain the above copyright
bogdanm 84:0b3ab51c8877 16 notice, this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 - Redistributions in binary form must reproduce the above copyright
bogdanm 84:0b3ab51c8877 18 notice, this list of conditions and the following disclaimer in the
bogdanm 84:0b3ab51c8877 19 documentation and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 - Neither the name of ARM nor the names of its contributors may be used
bogdanm 84:0b3ab51c8877 21 to endorse or promote products derived from this software without
bogdanm 84:0b3ab51c8877 22 specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
bogdanm 84:0b3ab51c8877 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
bogdanm 84:0b3ab51c8877 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
bogdanm 84:0b3ab51c8877 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
bogdanm 84:0b3ab51c8877 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
bogdanm 84:0b3ab51c8877 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
bogdanm 84:0b3ab51c8877 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
bogdanm 84:0b3ab51c8877 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
bogdanm 84:0b3ab51c8877 34 POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 35 ---------------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 36
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 #if defined ( __ICCARM__ )
bogdanm 84:0b3ab51c8877 39 #pragma system_include /* treat file as system include file for MISRA check */
bogdanm 84:0b3ab51c8877 40 #endif
bogdanm 84:0b3ab51c8877 41
Kojto 110:165afa46840b 42 #ifndef __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 43 #define __CORE_CM0_H_GENERIC
Kojto 110:165afa46840b 44
bogdanm 84:0b3ab51c8877 45 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 46 extern "C" {
bogdanm 84:0b3ab51c8877 47 #endif
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
bogdanm 84:0b3ab51c8877 50 CMSIS violates the following MISRA-C:2004 rules:
bogdanm 84:0b3ab51c8877 51
bogdanm 84:0b3ab51c8877 52 \li Required Rule 8.5, object/function definition in header file.<br>
bogdanm 84:0b3ab51c8877 53 Function definitions in header files are used to allow 'inlining'.
bogdanm 84:0b3ab51c8877 54
bogdanm 84:0b3ab51c8877 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
bogdanm 84:0b3ab51c8877 56 Unions are used for effective representation of core registers.
bogdanm 84:0b3ab51c8877 57
bogdanm 84:0b3ab51c8877 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
bogdanm 84:0b3ab51c8877 59 Function-like macros are used to allow more efficient code.
bogdanm 84:0b3ab51c8877 60 */
bogdanm 84:0b3ab51c8877 61
bogdanm 84:0b3ab51c8877 62
bogdanm 84:0b3ab51c8877 63 /*******************************************************************************
bogdanm 84:0b3ab51c8877 64 * CMSIS definitions
bogdanm 84:0b3ab51c8877 65 ******************************************************************************/
bogdanm 84:0b3ab51c8877 66 /** \ingroup Cortex_M0
bogdanm 84:0b3ab51c8877 67 @{
bogdanm 84:0b3ab51c8877 68 */
bogdanm 84:0b3ab51c8877 69
bogdanm 84:0b3ab51c8877 70 /* CMSIS CM0 definitions */
Kojto 110:165afa46840b 71 #define __CM0_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
Kojto 110:165afa46840b 72 #define __CM0_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
bogdanm 84:0b3ab51c8877 73 #define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
bogdanm 84:0b3ab51c8877 74 __CM0_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
bogdanm 84:0b3ab51c8877 75
bogdanm 84:0b3ab51c8877 76 #define __CORTEX_M (0x00) /*!< Cortex-M Core */
bogdanm 84:0b3ab51c8877 77
bogdanm 84:0b3ab51c8877 78
bogdanm 84:0b3ab51c8877 79 #if defined ( __CC_ARM )
bogdanm 84:0b3ab51c8877 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 84:0b3ab51c8877 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 84:0b3ab51c8877 82 #define __STATIC_INLINE static __inline
bogdanm 84:0b3ab51c8877 83
Kojto 110:165afa46840b 84 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
Kojto 110:165afa46840b 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
Kojto 110:165afa46840b 87 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 88
bogdanm 84:0b3ab51c8877 89 #elif defined ( __ICCARM__ )
bogdanm 84:0b3ab51c8877 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 84:0b3ab51c8877 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
bogdanm 84:0b3ab51c8877 92 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 93
Kojto 110:165afa46840b 94 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
bogdanm 84:0b3ab51c8877 96 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98 #elif defined ( __TASKING__ )
bogdanm 84:0b3ab51c8877 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 84:0b3ab51c8877 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 84:0b3ab51c8877 101 #define __STATIC_INLINE static inline
bogdanm 84:0b3ab51c8877 102
Kojto 110:165afa46840b 103 #elif defined ( __CSMC__ )
Kojto 110:165afa46840b 104 #define __packed
Kojto 110:165afa46840b 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
Kojto 110:165afa46840b 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
Kojto 110:165afa46840b 107 #define __STATIC_INLINE static inline
Kojto 110:165afa46840b 108
bogdanm 84:0b3ab51c8877 109 #endif
bogdanm 84:0b3ab51c8877 110
Kojto 110:165afa46840b 111 /** __FPU_USED indicates whether an FPU is used or not.
Kojto 110:165afa46840b 112 This core does not support an FPU at all
bogdanm 84:0b3ab51c8877 113 */
bogdanm 84:0b3ab51c8877 114 #define __FPU_USED 0
bogdanm 84:0b3ab51c8877 115
bogdanm 84:0b3ab51c8877 116 #if defined ( __CC_ARM )
bogdanm 84:0b3ab51c8877 117 #if defined __TARGET_FPU_VFP
bogdanm 84:0b3ab51c8877 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 119 #endif
bogdanm 84:0b3ab51c8877 120
Kojto 110:165afa46840b 121 #elif defined ( __GNUC__ )
Kojto 110:165afa46840b 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
Kojto 110:165afa46840b 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 124 #endif
Kojto 110:165afa46840b 125
bogdanm 84:0b3ab51c8877 126 #elif defined ( __ICCARM__ )
bogdanm 84:0b3ab51c8877 127 #if defined __ARMVFP__
bogdanm 84:0b3ab51c8877 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 129 #endif
bogdanm 84:0b3ab51c8877 130
Kojto 110:165afa46840b 131 #elif defined ( __TMS470__ )
Kojto 110:165afa46840b 132 #if defined __TI__VFP_SUPPORT____
bogdanm 84:0b3ab51c8877 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 134 #endif
bogdanm 84:0b3ab51c8877 135
bogdanm 84:0b3ab51c8877 136 #elif defined ( __TASKING__ )
bogdanm 84:0b3ab51c8877 137 #if defined __FPU_VFP__
bogdanm 84:0b3ab51c8877 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
bogdanm 84:0b3ab51c8877 139 #endif
Kojto 110:165afa46840b 140
Kojto 110:165afa46840b 141 #elif defined ( __CSMC__ ) /* Cosmic */
Kojto 110:165afa46840b 142 #if ( __CSMC__ & 0x400) // FPU present for parser
Kojto 110:165afa46840b 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
Kojto 110:165afa46840b 144 #endif
bogdanm 84:0b3ab51c8877 145 #endif
bogdanm 84:0b3ab51c8877 146
bogdanm 84:0b3ab51c8877 147 #include <stdint.h> /* standard types definitions */
bogdanm 84:0b3ab51c8877 148 #include <core_cmInstr.h> /* Core Instruction Access */
bogdanm 84:0b3ab51c8877 149 #include <core_cmFunc.h> /* Core Function Access */
bogdanm 84:0b3ab51c8877 150
Kojto 110:165afa46840b 151 #ifdef __cplusplus
Kojto 110:165afa46840b 152 }
Kojto 110:165afa46840b 153 #endif
Kojto 110:165afa46840b 154
bogdanm 84:0b3ab51c8877 155 #endif /* __CORE_CM0_H_GENERIC */
bogdanm 84:0b3ab51c8877 156
bogdanm 84:0b3ab51c8877 157 #ifndef __CMSIS_GENERIC
bogdanm 84:0b3ab51c8877 158
bogdanm 84:0b3ab51c8877 159 #ifndef __CORE_CM0_H_DEPENDANT
bogdanm 84:0b3ab51c8877 160 #define __CORE_CM0_H_DEPENDANT
bogdanm 84:0b3ab51c8877 161
Kojto 110:165afa46840b 162 #ifdef __cplusplus
Kojto 110:165afa46840b 163 extern "C" {
Kojto 110:165afa46840b 164 #endif
Kojto 110:165afa46840b 165
bogdanm 84:0b3ab51c8877 166 /* check device defines and use defaults */
bogdanm 84:0b3ab51c8877 167 #if defined __CHECK_DEVICE_DEFINES
bogdanm 84:0b3ab51c8877 168 #ifndef __CM0_REV
bogdanm 84:0b3ab51c8877 169 #define __CM0_REV 0x0000
bogdanm 84:0b3ab51c8877 170 #warning "__CM0_REV not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 171 #endif
bogdanm 84:0b3ab51c8877 172
bogdanm 84:0b3ab51c8877 173 #ifndef __NVIC_PRIO_BITS
bogdanm 84:0b3ab51c8877 174 #define __NVIC_PRIO_BITS 2
bogdanm 84:0b3ab51c8877 175 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 176 #endif
bogdanm 84:0b3ab51c8877 177
bogdanm 84:0b3ab51c8877 178 #ifndef __Vendor_SysTickConfig
bogdanm 84:0b3ab51c8877 179 #define __Vendor_SysTickConfig 0
bogdanm 84:0b3ab51c8877 180 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
bogdanm 84:0b3ab51c8877 181 #endif
bogdanm 84:0b3ab51c8877 182 #endif
bogdanm 84:0b3ab51c8877 183
bogdanm 84:0b3ab51c8877 184 /* IO definitions (access restrictions to peripheral registers) */
bogdanm 84:0b3ab51c8877 185 /**
bogdanm 84:0b3ab51c8877 186 \defgroup CMSIS_glob_defs CMSIS Global Defines
bogdanm 84:0b3ab51c8877 187
bogdanm 84:0b3ab51c8877 188 <strong>IO Type Qualifiers</strong> are used
bogdanm 84:0b3ab51c8877 189 \li to specify the access to peripheral variables.
bogdanm 84:0b3ab51c8877 190 \li for automatic generation of peripheral register debug information.
bogdanm 84:0b3ab51c8877 191 */
bogdanm 84:0b3ab51c8877 192 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 193 #define __I volatile /*!< Defines 'read only' permissions */
bogdanm 84:0b3ab51c8877 194 #else
bogdanm 84:0b3ab51c8877 195 #define __I volatile const /*!< Defines 'read only' permissions */
bogdanm 84:0b3ab51c8877 196 #endif
bogdanm 84:0b3ab51c8877 197 #define __O volatile /*!< Defines 'write only' permissions */
bogdanm 84:0b3ab51c8877 198 #define __IO volatile /*!< Defines 'read / write' permissions */
bogdanm 84:0b3ab51c8877 199
bogdanm 84:0b3ab51c8877 200 /*@} end of group Cortex_M0 */
bogdanm 84:0b3ab51c8877 201
bogdanm 84:0b3ab51c8877 202
bogdanm 84:0b3ab51c8877 203
bogdanm 84:0b3ab51c8877 204 /*******************************************************************************
bogdanm 84:0b3ab51c8877 205 * Register Abstraction
bogdanm 84:0b3ab51c8877 206 Core Register contain:
bogdanm 84:0b3ab51c8877 207 - Core Register
bogdanm 84:0b3ab51c8877 208 - Core NVIC Register
bogdanm 84:0b3ab51c8877 209 - Core SCB Register
bogdanm 84:0b3ab51c8877 210 - Core SysTick Register
bogdanm 84:0b3ab51c8877 211 ******************************************************************************/
bogdanm 84:0b3ab51c8877 212 /** \defgroup CMSIS_core_register Defines and Type Definitions
bogdanm 84:0b3ab51c8877 213 \brief Type definitions and defines for Cortex-M processor based devices.
bogdanm 84:0b3ab51c8877 214 */
bogdanm 84:0b3ab51c8877 215
bogdanm 84:0b3ab51c8877 216 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 217 \defgroup CMSIS_CORE Status and Control Registers
bogdanm 84:0b3ab51c8877 218 \brief Core Register type definitions.
bogdanm 84:0b3ab51c8877 219 @{
bogdanm 84:0b3ab51c8877 220 */
bogdanm 84:0b3ab51c8877 221
bogdanm 84:0b3ab51c8877 222 /** \brief Union type to access the Application Program Status Register (APSR).
bogdanm 84:0b3ab51c8877 223 */
bogdanm 84:0b3ab51c8877 224 typedef union
bogdanm 84:0b3ab51c8877 225 {
bogdanm 84:0b3ab51c8877 226 struct
bogdanm 84:0b3ab51c8877 227 {
Kojto 110:165afa46840b 228 uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */
bogdanm 84:0b3ab51c8877 229 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 84:0b3ab51c8877 230 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 84:0b3ab51c8877 231 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 84:0b3ab51c8877 232 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 84:0b3ab51c8877 233 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 234 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 235 } APSR_Type;
bogdanm 84:0b3ab51c8877 236
Kojto 110:165afa46840b 237 /* APSR Register Definitions */
Kojto 110:165afa46840b 238 #define APSR_N_Pos 31 /*!< APSR: N Position */
Kojto 110:165afa46840b 239 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
Kojto 110:165afa46840b 240
Kojto 110:165afa46840b 241 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
Kojto 110:165afa46840b 242 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
Kojto 110:165afa46840b 243
Kojto 110:165afa46840b 244 #define APSR_C_Pos 29 /*!< APSR: C Position */
Kojto 110:165afa46840b 245 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
Kojto 110:165afa46840b 246
Kojto 110:165afa46840b 247 #define APSR_V_Pos 28 /*!< APSR: V Position */
Kojto 110:165afa46840b 248 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
Kojto 110:165afa46840b 249
bogdanm 84:0b3ab51c8877 250
bogdanm 84:0b3ab51c8877 251 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
bogdanm 84:0b3ab51c8877 252 */
bogdanm 84:0b3ab51c8877 253 typedef union
bogdanm 84:0b3ab51c8877 254 {
bogdanm 84:0b3ab51c8877 255 struct
bogdanm 84:0b3ab51c8877 256 {
bogdanm 84:0b3ab51c8877 257 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 84:0b3ab51c8877 258 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
bogdanm 84:0b3ab51c8877 259 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 260 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 261 } IPSR_Type;
bogdanm 84:0b3ab51c8877 262
Kojto 110:165afa46840b 263 /* IPSR Register Definitions */
Kojto 110:165afa46840b 264 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
Kojto 110:165afa46840b 265 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
Kojto 110:165afa46840b 266
bogdanm 84:0b3ab51c8877 267
bogdanm 84:0b3ab51c8877 268 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
bogdanm 84:0b3ab51c8877 269 */
bogdanm 84:0b3ab51c8877 270 typedef union
bogdanm 84:0b3ab51c8877 271 {
bogdanm 84:0b3ab51c8877 272 struct
bogdanm 84:0b3ab51c8877 273 {
bogdanm 84:0b3ab51c8877 274 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
bogdanm 84:0b3ab51c8877 275 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
bogdanm 84:0b3ab51c8877 276 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
Kojto 110:165afa46840b 277 uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */
bogdanm 84:0b3ab51c8877 278 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
bogdanm 84:0b3ab51c8877 279 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
bogdanm 84:0b3ab51c8877 280 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
bogdanm 84:0b3ab51c8877 281 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
bogdanm 84:0b3ab51c8877 282 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 283 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 284 } xPSR_Type;
bogdanm 84:0b3ab51c8877 285
Kojto 110:165afa46840b 286 /* xPSR Register Definitions */
Kojto 110:165afa46840b 287 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
Kojto 110:165afa46840b 288 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
Kojto 110:165afa46840b 289
Kojto 110:165afa46840b 290 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
Kojto 110:165afa46840b 291 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
Kojto 110:165afa46840b 292
Kojto 110:165afa46840b 293 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
Kojto 110:165afa46840b 294 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
Kojto 110:165afa46840b 295
Kojto 110:165afa46840b 296 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
Kojto 110:165afa46840b 297 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
Kojto 110:165afa46840b 298
Kojto 110:165afa46840b 299 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
Kojto 110:165afa46840b 300 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
Kojto 110:165afa46840b 301
Kojto 110:165afa46840b 302 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
Kojto 110:165afa46840b 303 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
Kojto 110:165afa46840b 304
bogdanm 84:0b3ab51c8877 305
bogdanm 84:0b3ab51c8877 306 /** \brief Union type to access the Control Registers (CONTROL).
bogdanm 84:0b3ab51c8877 307 */
bogdanm 84:0b3ab51c8877 308 typedef union
bogdanm 84:0b3ab51c8877 309 {
bogdanm 84:0b3ab51c8877 310 struct
bogdanm 84:0b3ab51c8877 311 {
Kojto 110:165afa46840b 312 uint32_t _reserved0:1; /*!< bit: 0 Reserved */
bogdanm 84:0b3ab51c8877 313 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
Kojto 110:165afa46840b 314 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
bogdanm 84:0b3ab51c8877 315 } b; /*!< Structure used for bit access */
bogdanm 84:0b3ab51c8877 316 uint32_t w; /*!< Type used for word access */
bogdanm 84:0b3ab51c8877 317 } CONTROL_Type;
bogdanm 84:0b3ab51c8877 318
Kojto 110:165afa46840b 319 /* CONTROL Register Definitions */
Kojto 110:165afa46840b 320 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
Kojto 110:165afa46840b 321 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
Kojto 110:165afa46840b 322
bogdanm 84:0b3ab51c8877 323 /*@} end of group CMSIS_CORE */
bogdanm 84:0b3ab51c8877 324
bogdanm 84:0b3ab51c8877 325
bogdanm 84:0b3ab51c8877 326 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 327 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
bogdanm 84:0b3ab51c8877 328 \brief Type definitions for the NVIC Registers
bogdanm 84:0b3ab51c8877 329 @{
bogdanm 84:0b3ab51c8877 330 */
bogdanm 84:0b3ab51c8877 331
bogdanm 84:0b3ab51c8877 332 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
bogdanm 84:0b3ab51c8877 333 */
bogdanm 84:0b3ab51c8877 334 typedef struct
bogdanm 84:0b3ab51c8877 335 {
bogdanm 84:0b3ab51c8877 336 __IO uint32_t ISER[1]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
bogdanm 84:0b3ab51c8877 337 uint32_t RESERVED0[31];
bogdanm 84:0b3ab51c8877 338 __IO uint32_t ICER[1]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
bogdanm 84:0b3ab51c8877 339 uint32_t RSERVED1[31];
bogdanm 84:0b3ab51c8877 340 __IO uint32_t ISPR[1]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
bogdanm 84:0b3ab51c8877 341 uint32_t RESERVED2[31];
bogdanm 84:0b3ab51c8877 342 __IO uint32_t ICPR[1]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
bogdanm 84:0b3ab51c8877 343 uint32_t RESERVED3[31];
bogdanm 84:0b3ab51c8877 344 uint32_t RESERVED4[64];
bogdanm 84:0b3ab51c8877 345 __IO uint32_t IP[8]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */
bogdanm 84:0b3ab51c8877 346 } NVIC_Type;
bogdanm 84:0b3ab51c8877 347
bogdanm 84:0b3ab51c8877 348 /*@} end of group CMSIS_NVIC */
bogdanm 84:0b3ab51c8877 349
bogdanm 84:0b3ab51c8877 350
bogdanm 84:0b3ab51c8877 351 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 352 \defgroup CMSIS_SCB System Control Block (SCB)
bogdanm 84:0b3ab51c8877 353 \brief Type definitions for the System Control Block Registers
bogdanm 84:0b3ab51c8877 354 @{
bogdanm 84:0b3ab51c8877 355 */
bogdanm 84:0b3ab51c8877 356
bogdanm 84:0b3ab51c8877 357 /** \brief Structure type to access the System Control Block (SCB).
bogdanm 84:0b3ab51c8877 358 */
bogdanm 84:0b3ab51c8877 359 typedef struct
bogdanm 84:0b3ab51c8877 360 {
bogdanm 84:0b3ab51c8877 361 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
bogdanm 84:0b3ab51c8877 362 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
bogdanm 84:0b3ab51c8877 363 uint32_t RESERVED0;
bogdanm 84:0b3ab51c8877 364 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
bogdanm 84:0b3ab51c8877 365 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
bogdanm 84:0b3ab51c8877 366 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
bogdanm 84:0b3ab51c8877 367 uint32_t RESERVED1;
bogdanm 84:0b3ab51c8877 368 __IO uint32_t SHP[2]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */
bogdanm 84:0b3ab51c8877 369 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
bogdanm 84:0b3ab51c8877 370 } SCB_Type;
bogdanm 84:0b3ab51c8877 371
bogdanm 84:0b3ab51c8877 372 /* SCB CPUID Register Definitions */
bogdanm 84:0b3ab51c8877 373 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
bogdanm 84:0b3ab51c8877 374 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
bogdanm 84:0b3ab51c8877 375
bogdanm 84:0b3ab51c8877 376 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
bogdanm 84:0b3ab51c8877 377 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
bogdanm 84:0b3ab51c8877 378
bogdanm 84:0b3ab51c8877 379 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
bogdanm 84:0b3ab51c8877 380 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
bogdanm 84:0b3ab51c8877 381
bogdanm 84:0b3ab51c8877 382 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
bogdanm 84:0b3ab51c8877 383 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
bogdanm 84:0b3ab51c8877 384
bogdanm 84:0b3ab51c8877 385 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
Kojto 110:165afa46840b 386 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
bogdanm 84:0b3ab51c8877 387
bogdanm 84:0b3ab51c8877 388 /* SCB Interrupt Control State Register Definitions */
bogdanm 84:0b3ab51c8877 389 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
bogdanm 84:0b3ab51c8877 390 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
bogdanm 84:0b3ab51c8877 391
bogdanm 84:0b3ab51c8877 392 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
bogdanm 84:0b3ab51c8877 393 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
bogdanm 84:0b3ab51c8877 394
bogdanm 84:0b3ab51c8877 395 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
bogdanm 84:0b3ab51c8877 396 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
bogdanm 84:0b3ab51c8877 397
bogdanm 84:0b3ab51c8877 398 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
bogdanm 84:0b3ab51c8877 399 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
bogdanm 84:0b3ab51c8877 400
bogdanm 84:0b3ab51c8877 401 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
bogdanm 84:0b3ab51c8877 402 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
bogdanm 84:0b3ab51c8877 403
bogdanm 84:0b3ab51c8877 404 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
bogdanm 84:0b3ab51c8877 405 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
bogdanm 84:0b3ab51c8877 406
bogdanm 84:0b3ab51c8877 407 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
bogdanm 84:0b3ab51c8877 408 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
bogdanm 84:0b3ab51c8877 409
bogdanm 84:0b3ab51c8877 410 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
bogdanm 84:0b3ab51c8877 411 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
bogdanm 84:0b3ab51c8877 412
bogdanm 84:0b3ab51c8877 413 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
Kojto 110:165afa46840b 414 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
bogdanm 84:0b3ab51c8877 415
bogdanm 84:0b3ab51c8877 416 /* SCB Application Interrupt and Reset Control Register Definitions */
bogdanm 84:0b3ab51c8877 417 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
bogdanm 84:0b3ab51c8877 418 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
bogdanm 84:0b3ab51c8877 419
bogdanm 84:0b3ab51c8877 420 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
bogdanm 84:0b3ab51c8877 421 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
bogdanm 84:0b3ab51c8877 422
bogdanm 84:0b3ab51c8877 423 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
bogdanm 84:0b3ab51c8877 424 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
bogdanm 84:0b3ab51c8877 425
bogdanm 84:0b3ab51c8877 426 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
bogdanm 84:0b3ab51c8877 427 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
bogdanm 84:0b3ab51c8877 428
bogdanm 84:0b3ab51c8877 429 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
bogdanm 84:0b3ab51c8877 430 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
bogdanm 84:0b3ab51c8877 431
bogdanm 84:0b3ab51c8877 432 /* SCB System Control Register Definitions */
bogdanm 84:0b3ab51c8877 433 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
bogdanm 84:0b3ab51c8877 434 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
bogdanm 84:0b3ab51c8877 435
bogdanm 84:0b3ab51c8877 436 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
bogdanm 84:0b3ab51c8877 437 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
bogdanm 84:0b3ab51c8877 438
bogdanm 84:0b3ab51c8877 439 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
bogdanm 84:0b3ab51c8877 440 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
bogdanm 84:0b3ab51c8877 441
bogdanm 84:0b3ab51c8877 442 /* SCB Configuration Control Register Definitions */
bogdanm 84:0b3ab51c8877 443 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
bogdanm 84:0b3ab51c8877 444 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
bogdanm 84:0b3ab51c8877 445
bogdanm 84:0b3ab51c8877 446 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
bogdanm 84:0b3ab51c8877 447 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
bogdanm 84:0b3ab51c8877 448
bogdanm 84:0b3ab51c8877 449 /* SCB System Handler Control and State Register Definitions */
bogdanm 84:0b3ab51c8877 450 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
bogdanm 84:0b3ab51c8877 451 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
bogdanm 84:0b3ab51c8877 452
bogdanm 84:0b3ab51c8877 453 /*@} end of group CMSIS_SCB */
bogdanm 84:0b3ab51c8877 454
bogdanm 84:0b3ab51c8877 455
bogdanm 84:0b3ab51c8877 456 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 457 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
bogdanm 84:0b3ab51c8877 458 \brief Type definitions for the System Timer Registers.
bogdanm 84:0b3ab51c8877 459 @{
bogdanm 84:0b3ab51c8877 460 */
bogdanm 84:0b3ab51c8877 461
bogdanm 84:0b3ab51c8877 462 /** \brief Structure type to access the System Timer (SysTick).
bogdanm 84:0b3ab51c8877 463 */
bogdanm 84:0b3ab51c8877 464 typedef struct
bogdanm 84:0b3ab51c8877 465 {
bogdanm 84:0b3ab51c8877 466 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
bogdanm 84:0b3ab51c8877 467 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
bogdanm 84:0b3ab51c8877 468 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
bogdanm 84:0b3ab51c8877 469 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
bogdanm 84:0b3ab51c8877 470 } SysTick_Type;
bogdanm 84:0b3ab51c8877 471
bogdanm 84:0b3ab51c8877 472 /* SysTick Control / Status Register Definitions */
bogdanm 84:0b3ab51c8877 473 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
bogdanm 84:0b3ab51c8877 474 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
bogdanm 84:0b3ab51c8877 475
bogdanm 84:0b3ab51c8877 476 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
bogdanm 84:0b3ab51c8877 477 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
bogdanm 84:0b3ab51c8877 478
bogdanm 84:0b3ab51c8877 479 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
bogdanm 84:0b3ab51c8877 480 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
bogdanm 84:0b3ab51c8877 481
bogdanm 84:0b3ab51c8877 482 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
Kojto 110:165afa46840b 483 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
bogdanm 84:0b3ab51c8877 484
bogdanm 84:0b3ab51c8877 485 /* SysTick Reload Register Definitions */
bogdanm 84:0b3ab51c8877 486 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
Kojto 110:165afa46840b 487 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
bogdanm 84:0b3ab51c8877 488
bogdanm 84:0b3ab51c8877 489 /* SysTick Current Register Definitions */
bogdanm 84:0b3ab51c8877 490 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
Kojto 110:165afa46840b 491 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
bogdanm 84:0b3ab51c8877 492
bogdanm 84:0b3ab51c8877 493 /* SysTick Calibration Register Definitions */
bogdanm 84:0b3ab51c8877 494 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
bogdanm 84:0b3ab51c8877 495 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
bogdanm 84:0b3ab51c8877 496
bogdanm 84:0b3ab51c8877 497 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
bogdanm 84:0b3ab51c8877 498 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
bogdanm 84:0b3ab51c8877 499
bogdanm 84:0b3ab51c8877 500 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
Kojto 110:165afa46840b 501 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
bogdanm 84:0b3ab51c8877 502
bogdanm 84:0b3ab51c8877 503 /*@} end of group CMSIS_SysTick */
bogdanm 84:0b3ab51c8877 504
bogdanm 84:0b3ab51c8877 505
bogdanm 84:0b3ab51c8877 506 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 507 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
bogdanm 84:0b3ab51c8877 508 \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR)
bogdanm 84:0b3ab51c8877 509 are only accessible over DAP and not via processor. Therefore
bogdanm 84:0b3ab51c8877 510 they are not covered by the Cortex-M0 header file.
bogdanm 84:0b3ab51c8877 511 @{
bogdanm 84:0b3ab51c8877 512 */
bogdanm 84:0b3ab51c8877 513 /*@} end of group CMSIS_CoreDebug */
bogdanm 84:0b3ab51c8877 514
bogdanm 84:0b3ab51c8877 515
bogdanm 84:0b3ab51c8877 516 /** \ingroup CMSIS_core_register
bogdanm 84:0b3ab51c8877 517 \defgroup CMSIS_core_base Core Definitions
bogdanm 84:0b3ab51c8877 518 \brief Definitions for base addresses, unions, and structures.
bogdanm 84:0b3ab51c8877 519 @{
bogdanm 84:0b3ab51c8877 520 */
bogdanm 84:0b3ab51c8877 521
bogdanm 84:0b3ab51c8877 522 /* Memory mapping of Cortex-M0 Hardware */
bogdanm 84:0b3ab51c8877 523 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
bogdanm 84:0b3ab51c8877 524 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
bogdanm 84:0b3ab51c8877 525 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
bogdanm 84:0b3ab51c8877 526 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
bogdanm 84:0b3ab51c8877 527
bogdanm 84:0b3ab51c8877 528 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
bogdanm 84:0b3ab51c8877 529 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
bogdanm 84:0b3ab51c8877 530 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
bogdanm 84:0b3ab51c8877 531
bogdanm 84:0b3ab51c8877 532
bogdanm 84:0b3ab51c8877 533 /*@} */
bogdanm 84:0b3ab51c8877 534
bogdanm 84:0b3ab51c8877 535
bogdanm 84:0b3ab51c8877 536
bogdanm 84:0b3ab51c8877 537 /*******************************************************************************
bogdanm 84:0b3ab51c8877 538 * Hardware Abstraction Layer
bogdanm 84:0b3ab51c8877 539 Core Function Interface contains:
bogdanm 84:0b3ab51c8877 540 - Core NVIC Functions
bogdanm 84:0b3ab51c8877 541 - Core SysTick Functions
bogdanm 84:0b3ab51c8877 542 - Core Register Access Functions
bogdanm 84:0b3ab51c8877 543 ******************************************************************************/
bogdanm 84:0b3ab51c8877 544 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
bogdanm 84:0b3ab51c8877 545 */
bogdanm 84:0b3ab51c8877 546
bogdanm 84:0b3ab51c8877 547
bogdanm 84:0b3ab51c8877 548
bogdanm 84:0b3ab51c8877 549 /* ########################## NVIC functions #################################### */
bogdanm 84:0b3ab51c8877 550 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 84:0b3ab51c8877 551 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
bogdanm 84:0b3ab51c8877 552 \brief Functions that manage interrupts and exceptions via the NVIC.
bogdanm 84:0b3ab51c8877 553 @{
bogdanm 84:0b3ab51c8877 554 */
bogdanm 84:0b3ab51c8877 555
bogdanm 84:0b3ab51c8877 556 /* Interrupt Priorities are WORD accessible only under ARMv6M */
bogdanm 84:0b3ab51c8877 557 /* The following MACROS handle generation of the register offset and byte masks */
Kojto 110:165afa46840b 558 #define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
Kojto 110:165afa46840b 559 #define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
Kojto 110:165afa46840b 560 #define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
bogdanm 84:0b3ab51c8877 561
bogdanm 84:0b3ab51c8877 562
bogdanm 84:0b3ab51c8877 563 /** \brief Enable External Interrupt
bogdanm 84:0b3ab51c8877 564
bogdanm 84:0b3ab51c8877 565 The function enables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 84:0b3ab51c8877 566
bogdanm 84:0b3ab51c8877 567 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 568 */
bogdanm 84:0b3ab51c8877 569 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 570 {
Kojto 110:165afa46840b 571 NVIC->ISER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 84:0b3ab51c8877 572 }
bogdanm 84:0b3ab51c8877 573
bogdanm 84:0b3ab51c8877 574
bogdanm 84:0b3ab51c8877 575 /** \brief Disable External Interrupt
bogdanm 84:0b3ab51c8877 576
bogdanm 84:0b3ab51c8877 577 The function disables a device-specific interrupt in the NVIC interrupt controller.
bogdanm 84:0b3ab51c8877 578
bogdanm 84:0b3ab51c8877 579 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 580 */
bogdanm 84:0b3ab51c8877 581 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 582 {
Kojto 110:165afa46840b 583 NVIC->ICER[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 84:0b3ab51c8877 584 }
bogdanm 84:0b3ab51c8877 585
bogdanm 84:0b3ab51c8877 586
bogdanm 84:0b3ab51c8877 587 /** \brief Get Pending Interrupt
bogdanm 84:0b3ab51c8877 588
bogdanm 84:0b3ab51c8877 589 The function reads the pending register in the NVIC and returns the pending bit
bogdanm 84:0b3ab51c8877 590 for the specified interrupt.
bogdanm 84:0b3ab51c8877 591
bogdanm 84:0b3ab51c8877 592 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 593
bogdanm 84:0b3ab51c8877 594 \return 0 Interrupt status is not pending.
bogdanm 84:0b3ab51c8877 595 \return 1 Interrupt status is pending.
bogdanm 84:0b3ab51c8877 596 */
bogdanm 84:0b3ab51c8877 597 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 598 {
Kojto 110:165afa46840b 599 return((uint32_t)(((NVIC->ISPR[0] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
bogdanm 84:0b3ab51c8877 600 }
bogdanm 84:0b3ab51c8877 601
bogdanm 84:0b3ab51c8877 602
bogdanm 84:0b3ab51c8877 603 /** \brief Set Pending Interrupt
bogdanm 84:0b3ab51c8877 604
bogdanm 84:0b3ab51c8877 605 The function sets the pending bit of an external interrupt.
bogdanm 84:0b3ab51c8877 606
bogdanm 84:0b3ab51c8877 607 \param [in] IRQn Interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 608 */
bogdanm 84:0b3ab51c8877 609 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 610 {
Kojto 110:165afa46840b 611 NVIC->ISPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 84:0b3ab51c8877 612 }
bogdanm 84:0b3ab51c8877 613
bogdanm 84:0b3ab51c8877 614
bogdanm 84:0b3ab51c8877 615 /** \brief Clear Pending Interrupt
bogdanm 84:0b3ab51c8877 616
bogdanm 84:0b3ab51c8877 617 The function clears the pending bit of an external interrupt.
bogdanm 84:0b3ab51c8877 618
bogdanm 84:0b3ab51c8877 619 \param [in] IRQn External interrupt number. Value cannot be negative.
bogdanm 84:0b3ab51c8877 620 */
bogdanm 84:0b3ab51c8877 621 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 622 {
Kojto 110:165afa46840b 623 NVIC->ICPR[0] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
bogdanm 84:0b3ab51c8877 624 }
bogdanm 84:0b3ab51c8877 625
bogdanm 84:0b3ab51c8877 626
bogdanm 84:0b3ab51c8877 627 /** \brief Set Interrupt Priority
bogdanm 84:0b3ab51c8877 628
bogdanm 84:0b3ab51c8877 629 The function sets the priority of an interrupt.
bogdanm 84:0b3ab51c8877 630
bogdanm 84:0b3ab51c8877 631 \note The priority cannot be set for every core interrupt.
bogdanm 84:0b3ab51c8877 632
bogdanm 84:0b3ab51c8877 633 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 634 \param [in] priority Priority to set.
bogdanm 84:0b3ab51c8877 635 */
bogdanm 84:0b3ab51c8877 636 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
bogdanm 84:0b3ab51c8877 637 {
Kojto 110:165afa46840b 638 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 639 SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 640 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 641 }
bogdanm 84:0b3ab51c8877 642 else {
Kojto 110:165afa46840b 643 NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) |
Kojto 110:165afa46840b 644 (((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
Kojto 110:165afa46840b 645 }
bogdanm 84:0b3ab51c8877 646 }
bogdanm 84:0b3ab51c8877 647
bogdanm 84:0b3ab51c8877 648
bogdanm 84:0b3ab51c8877 649 /** \brief Get Interrupt Priority
bogdanm 84:0b3ab51c8877 650
bogdanm 84:0b3ab51c8877 651 The function reads the priority of an interrupt. The interrupt
bogdanm 84:0b3ab51c8877 652 number can be positive to specify an external (device specific)
bogdanm 84:0b3ab51c8877 653 interrupt, or negative to specify an internal (core) interrupt.
bogdanm 84:0b3ab51c8877 654
bogdanm 84:0b3ab51c8877 655
bogdanm 84:0b3ab51c8877 656 \param [in] IRQn Interrupt number.
bogdanm 84:0b3ab51c8877 657 \return Interrupt Priority. Value is aligned automatically to the implemented
bogdanm 84:0b3ab51c8877 658 priority bits of the microcontroller.
bogdanm 84:0b3ab51c8877 659 */
bogdanm 84:0b3ab51c8877 660 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
bogdanm 84:0b3ab51c8877 661 {
bogdanm 84:0b3ab51c8877 662
Kojto 110:165afa46840b 663 if((int32_t)(IRQn) < 0) {
Kojto 110:165afa46840b 664 return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 665 }
bogdanm 84:0b3ab51c8877 666 else {
Kojto 110:165afa46840b 667 return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8 - __NVIC_PRIO_BITS)));
Kojto 110:165afa46840b 668 }
bogdanm 84:0b3ab51c8877 669 }
bogdanm 84:0b3ab51c8877 670
bogdanm 84:0b3ab51c8877 671
bogdanm 84:0b3ab51c8877 672 /** \brief System Reset
bogdanm 84:0b3ab51c8877 673
bogdanm 84:0b3ab51c8877 674 The function initiates a system reset request to reset the MCU.
bogdanm 84:0b3ab51c8877 675 */
bogdanm 84:0b3ab51c8877 676 __STATIC_INLINE void NVIC_SystemReset(void)
bogdanm 84:0b3ab51c8877 677 {
bogdanm 84:0b3ab51c8877 678 __DSB(); /* Ensure all outstanding memory accesses included
bogdanm 84:0b3ab51c8877 679 buffered write are completed before reset */
Kojto 110:165afa46840b 680 SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
bogdanm 84:0b3ab51c8877 681 SCB_AIRCR_SYSRESETREQ_Msk);
bogdanm 84:0b3ab51c8877 682 __DSB(); /* Ensure completion of memory access */
Kojto 110:165afa46840b 683 while(1) { __NOP(); } /* wait until reset */
bogdanm 84:0b3ab51c8877 684 }
bogdanm 84:0b3ab51c8877 685
bogdanm 84:0b3ab51c8877 686 /*@} end of CMSIS_Core_NVICFunctions */
bogdanm 84:0b3ab51c8877 687
bogdanm 84:0b3ab51c8877 688
bogdanm 84:0b3ab51c8877 689
bogdanm 84:0b3ab51c8877 690 /* ################################## SysTick function ############################################ */
bogdanm 84:0b3ab51c8877 691 /** \ingroup CMSIS_Core_FunctionInterface
bogdanm 84:0b3ab51c8877 692 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
bogdanm 84:0b3ab51c8877 693 \brief Functions that configure the System.
bogdanm 84:0b3ab51c8877 694 @{
bogdanm 84:0b3ab51c8877 695 */
bogdanm 84:0b3ab51c8877 696
bogdanm 84:0b3ab51c8877 697 #if (__Vendor_SysTickConfig == 0)
bogdanm 84:0b3ab51c8877 698
bogdanm 84:0b3ab51c8877 699 /** \brief System Tick Configuration
bogdanm 84:0b3ab51c8877 700
bogdanm 84:0b3ab51c8877 701 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
bogdanm 84:0b3ab51c8877 702 Counter is in free running mode to generate periodic interrupts.
bogdanm 84:0b3ab51c8877 703
bogdanm 84:0b3ab51c8877 704 \param [in] ticks Number of ticks between two interrupts.
bogdanm 84:0b3ab51c8877 705
bogdanm 84:0b3ab51c8877 706 \return 0 Function succeeded.
bogdanm 84:0b3ab51c8877 707 \return 1 Function failed.
bogdanm 84:0b3ab51c8877 708
bogdanm 84:0b3ab51c8877 709 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
bogdanm 84:0b3ab51c8877 710 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
bogdanm 84:0b3ab51c8877 711 must contain a vendor-specific implementation of this function.
bogdanm 84:0b3ab51c8877 712
bogdanm 84:0b3ab51c8877 713 */
bogdanm 84:0b3ab51c8877 714 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
bogdanm 84:0b3ab51c8877 715 {
Kojto 110:165afa46840b 716 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
bogdanm 84:0b3ab51c8877 717
Kojto 110:165afa46840b 718 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
Kojto 110:165afa46840b 719 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
Kojto 110:165afa46840b 720 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
bogdanm 84:0b3ab51c8877 721 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
bogdanm 84:0b3ab51c8877 722 SysTick_CTRL_TICKINT_Msk |
Kojto 110:165afa46840b 723 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
Kojto 110:165afa46840b 724 return (0UL); /* Function successful */
bogdanm 84:0b3ab51c8877 725 }
bogdanm 84:0b3ab51c8877 726
bogdanm 84:0b3ab51c8877 727 #endif
bogdanm 84:0b3ab51c8877 728
bogdanm 84:0b3ab51c8877 729 /*@} end of CMSIS_Core_SysTickFunctions */
bogdanm 84:0b3ab51c8877 730
bogdanm 84:0b3ab51c8877 731
bogdanm 84:0b3ab51c8877 732
bogdanm 84:0b3ab51c8877 733
Kojto 110:165afa46840b 734 #ifdef __cplusplus
Kojto 110:165afa46840b 735 }
Kojto 110:165afa46840b 736 #endif
Kojto 110:165afa46840b 737
bogdanm 84:0b3ab51c8877 738 #endif /* __CORE_CM0_H_DEPENDANT */
bogdanm 84:0b3ab51c8877 739
bogdanm 84:0b3ab51c8877 740 #endif /* __CMSIS_GENERIC */