Marta Avramovic / Mbed 2 deprecated FLOW_Sensor_Tester

YFS201 sensor tester. It works on interrupt so you need to set the Interrupt pin as input. Check your Nucleo board pinout list.

Dependencies:   mbed

main.cpp@2:6700d7f380bd, 2020-03-22 (annotated)

Committer:
dragica
Date:
Sun Mar 22 15:37:36 2020 +0000
Revision:
2:6700d7f380bd
Parent:
1:1214d9ff2f14
Child:
3:d6b68897773f
Dragica Stoiljkovic posle Martine revizije

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dragica 0:f49f58e4b0c9 1 #include "mbed.h"
dragica 0:f49f58e4b0c9 2 #include <string>
dragica 0:f49f58e4b0c9 3 using std::string;
dragica 2:6700d7f380bd 4
dragica 2:6700d7f380bd 5 #define FRMWRT_SGL_R 0x00 // single device read with response
dragica 2:6700d7f380bd 6 #define FRMWRT_SGL_NR 0x10 // single device write without response
dragica 2:6700d7f380bd 7 #define FRMWRT_ALL_R 0x40 // general broadcast read with response
dragica 2:6700d7f380bd 8 #define FRMWRT_ALL_NR 0x50 // general broadcast write without response
dragica 0:f49f58e4b0c9 9
dragica 0:f49f58e4b0c9 10 #define CONFIG 0x001
dragica 0:f49f58e4b0c9 11 #define COMM_CTRL 0x20
dragica 0:f49f58e4b0c9 12 #define ECC_TEST 0x11D
dragica 0:f49f58e4b0c9 13 #define CONTROL1 0x105
dragica 0:f49f58e4b0c9 14 #define COMM_TO 0x23
dragica 0:f49f58e4b0c9 15 #define TX_HOLD_OFF 0x22
dragica 0:f49f58e4b0c9 16 #define CONTROL2 0x106
dragica 2:6700d7f380bd 17 #define SYSFLT1_FLT_RST 0x13B
dragica 2:6700d7f380bd 18 #define SYSFLT1_FLT_MSK 0x16
dragica 2:6700d7f380bd 19 #define VCELL1H 0x215
dragica 0:f49f58e4b0c9 20
dragica 0:f49f58e4b0c9 21 typedef unsigned char BYTE;
dragica 2:6700d7f380bd 22
dragica 0:f49f58e4b0c9 23 const uint16_t crc16_table[256] = {
dragica 0:f49f58e4b0c9 24 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
dragica 0:f49f58e4b0c9 25 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
dragica 0:f49f58e4b0c9 26 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
dragica 0:f49f58e4b0c9 27 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
dragica 0:f49f58e4b0c9 28 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
dragica 0:f49f58e4b0c9 29 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
dragica 0:f49f58e4b0c9 30 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
dragica 0:f49f58e4b0c9 31 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
dragica 0:f49f58e4b0c9 32 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
dragica 0:f49f58e4b0c9 33 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
dragica 0:f49f58e4b0c9 34 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
dragica 0:f49f58e4b0c9 35 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
dragica 0:f49f58e4b0c9 36 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
dragica 0:f49f58e4b0c9 37 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
dragica 0:f49f58e4b0c9 38 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
dragica 0:f49f58e4b0c9 39 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
dragica 0:f49f58e4b0c9 40 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
dragica 0:f49f58e4b0c9 41 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
dragica 0:f49f58e4b0c9 42 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
dragica 0:f49f58e4b0c9 43 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
dragica 0:f49f58e4b0c9 44 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
dragica 0:f49f58e4b0c9 45 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
dragica 0:f49f58e4b0c9 46 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
dragica 0:f49f58e4b0c9 47 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
dragica 0:f49f58e4b0c9 48 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
dragica 0:f49f58e4b0c9 49 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
dragica 0:f49f58e4b0c9 50 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
dragica 0:f49f58e4b0c9 51 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
dragica 0:f49f58e4b0c9 52 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
dragica 0:f49f58e4b0c9 53 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
dragica 0:f49f58e4b0c9 54 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
dragica 0:f49f58e4b0c9 55 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
dragica 0:f49f58e4b0c9 56 };
dragica 2:6700d7f380bd 57 //ISTI KAO MARTINI, DOGOVOR, PROMENITI U ODNOSU NA LV MASTER
dragica 2:6700d7f380bd 58 DigitalOut bmsLVWakeUp(PB_0);
dragica 2:6700d7f380bd 59 DigitalIn bmsFault(PA_4);
dragica 0:f49f58e4b0c9 60
dragica 2:6700d7f380bd 61 Serial pc(PA_0, PA_1, 250000);
dragica 2:6700d7f380bd 62 Serial pc1(USBTX, USBRX, 9600);
dragica 0:f49f58e4b0c9 63
dragica 0:f49f58e4b0c9 64 void wakeUp()
dragica 0:f49f58e4b0c9 65 {
dragica 0:f49f58e4b0c9 66 bmsLVWakeUp=0;
dragica 0:f49f58e4b0c9 67 wait_us(300);
dragica 0:f49f58e4b0c9 68 bmsLVWakeUp=1;
dragica 0:f49f58e4b0c9 69 wait_ms(12);
dragica 0:f49f58e4b0c9 70 }
dragica 0:f49f58e4b0c9 71
dragica 0:f49f58e4b0c9 72 uint16_t CRC16(BYTE *pBuf, int nLen)
dragica 0:f49f58e4b0c9 73 {
dragica 0:f49f58e4b0c9 74 uint16_t wCRC = 0;
dragica 0:f49f58e4b0c9 75 int i;
dragica 0:f49f58e4b0c9 76
dragica 0:f49f58e4b0c9 77 for (i = 0; i < nLen; i++)
dragica 0:f49f58e4b0c9 78 {
dragica 0:f49f58e4b0c9 79 wCRC ^= (*pBuf++) & 0x00FF;
dragica 0:f49f58e4b0c9 80 wCRC = crc16_table[wCRC & 0x00FF] ^ (wCRC >> 8);
dragica 0:f49f58e4b0c9 81 }
dragica 0:f49f58e4b0c9 82
dragica 0:f49f58e4b0c9 83 return wCRC;
dragica 0:f49f58e4b0c9 84 }
dragica 0:f49f58e4b0c9 85 void posaljiUARTu(int length, uint8_t * data)
dragica 0:f49f58e4b0c9 86 {
dragica 0:f49f58e4b0c9 87 for(int i=0;i<length;i++)
dragica 0:f49f58e4b0c9 88 pc.putc(data[i]);
dragica 0:f49f58e4b0c9 89 wait_ms(1);
dragica 0:f49f58e4b0c9 90 }
dragica 0:f49f58e4b0c9 91
dragica 0:f49f58e4b0c9 92
dragica 0:f49f58e4b0c9 93 int WriteFrame(BYTE bID, uint16_t& wAddr, BYTE * pData, BYTE bLen, BYTE bWriteType)//pitati Martu!!
dragica 0:f49f58e4b0c9 94 {
dragica 0:f49f58e4b0c9 95
dragica 0:f49f58e4b0c9 96 int bPktLen = 0;
dragica 0:f49f58e4b0c9 97 BYTE pFrame[32];
dragica 0:f49f58e4b0c9 98 BYTE * pBuf = pFrame;
dragica 0:f49f58e4b0c9 99 uint16_t wCRC;
dragica 0:f49f58e4b0c9 100
dragica 0:f49f58e4b0c9 101 if (bLen == 7 || bLen > 8)
dragica 0:f49f58e4b0c9 102 return 0;
dragica 0:f49f58e4b0c9 103
dragica 0:f49f58e4b0c9 104 memset(pFrame, 0x7F, sizeof(pFrame));
dragica 0:f49f58e4b0c9 105 if (wAddr > 255) {
dragica 0:f49f58e4b0c9 106 *pBuf++ = 0x88 | bWriteType | bLen; // use 16-bit address
dragica 0:f49f58e4b0c9 107 if (bWriteType == FRMWRT_SGL_R || bWriteType == FRMWRT_SGL_NR )//(bWriteType != FRMWRT_ALL_NR)// || (bWriteType != FRMWRT_ALL_R))
dragica 0:f49f58e4b0c9 108 {
dragica 0:f49f58e4b0c9 109 *pBuf++ = (bID & 0x00FF);
dragica 0:f49f58e4b0c9 110 }
dragica 0:f49f58e4b0c9 111 *pBuf++ = (wAddr & 0xFF00) >> 8;
dragica 0:f49f58e4b0c9 112 *pBuf++ = wAddr & 0x00FF;
dragica 0:f49f58e4b0c9 113 }
dragica 0:f49f58e4b0c9 114 else {
dragica 0:f49f58e4b0c9 115
dragica 0:f49f58e4b0c9 116 *pBuf++ = 0x80 | bWriteType | bLen; // use 8-bit address
dragica 0:f49f58e4b0c9 117 if (bWriteType == FRMWRT_SGL_R || bWriteType == FRMWRT_SGL_NR )
dragica 0:f49f58e4b0c9 118 {
dragica 0:f49f58e4b0c9 119 *pBuf++ = (bID & 0x00FF);
dragica 0:f49f58e4b0c9 120 }
dragica 0:f49f58e4b0c9 121 *pBuf++ = wAddr & 0x00FF;
dragica 0:f49f58e4b0c9 122 }
dragica 0:f49f58e4b0c9 123
dragica 0:f49f58e4b0c9 124 while(bLen--)
dragica 0:f49f58e4b0c9 125 *pBuf++ = *pData++;
dragica 0:f49f58e4b0c9 126
dragica 0:f49f58e4b0c9 127 bPktLen = pBuf - pFrame;
dragica 0:f49f58e4b0c9 128
dragica 0:f49f58e4b0c9 129 wCRC = CRC16(pFrame, bPktLen);
dragica 0:f49f58e4b0c9 130 *pBuf++ = wCRC & 0x00FF;
dragica 0:f49f58e4b0c9 131 *pBuf++ = (wCRC & 0xFF00) >> 8;
dragica 0:f49f58e4b0c9 132 bPktLen += 2;
dragica 0:f49f58e4b0c9 133
dragica 0:f49f58e4b0c9 134 posaljiUARTu(bPktLen,pFrame);
dragica 0:f49f58e4b0c9 135
dragica 0:f49f58e4b0c9 136 return bPktLen;
dragica 0:f49f58e4b0c9 137 }
dragica 0:f49f58e4b0c9 138
dragica 0:f49f58e4b0c9 139 int WriteReg(BYTE DevID, uint16_t wAddr, uint64_t dwData, BYTE numDATAb, BYTE bWriteType)// eg: WriteReg(nDev_ID,0x0106,0x01,1, FRMWRT_SGL_NR)
dragica 0:f49f58e4b0c9 140 {
dragica 0:f49f58e4b0c9 141 //Kopija Martinog koda
dragica 0:f49f58e4b0c9 142 int bRes = 0;
dragica 0:f49f58e4b0c9 143 BYTE bBuf[8] = {0, 0, 0, 0, 0, 0, 0, 0};
dragica 0:f49f58e4b0c9 144 switch(numDATAb)
dragica 0:f49f58e4b0c9 145 {
dragica 0:f49f58e4b0c9 146 case 1:
dragica 0:f49f58e4b0c9 147 bBuf[0] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 148
dragica 0:f49f58e4b0c9 149 bRes = WriteFrame(DevID, wAddr, bBuf, 1, bWriteType);
dragica 0:f49f58e4b0c9 150 break;
dragica 0:f49f58e4b0c9 151 case 2:
dragica 0:f49f58e4b0c9 152 bBuf[0] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 153 bBuf[1] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 154
dragica 0:f49f58e4b0c9 155 bRes = WriteFrame(DevID, wAddr, bBuf, 2, bWriteType);
dragica 0:f49f58e4b0c9 156 break;
dragica 0:f49f58e4b0c9 157 case 3:
dragica 0:f49f58e4b0c9 158 bBuf[0] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 159 bBuf[1] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 160 bBuf[2] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 161
dragica 0:f49f58e4b0c9 162 bRes = WriteFrame(DevID, wAddr, bBuf, 3, bWriteType);
dragica 0:f49f58e4b0c9 163 break;
dragica 0:f49f58e4b0c9 164 case 4:
dragica 0:f49f58e4b0c9 165 bBuf[0] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 166 bBuf[1] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 167 bBuf[2] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 168 bBuf[3] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 169
dragica 0:f49f58e4b0c9 170 bRes = WriteFrame(DevID, wAddr, bBuf, 4, bWriteType);
dragica 0:f49f58e4b0c9 171 break;
dragica 0:f49f58e4b0c9 172 case 5:
dragica 0:f49f58e4b0c9 173 bBuf[0] = (dwData & 0x000000FF00000000) >> 32;
dragica 0:f49f58e4b0c9 174 bBuf[1] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 175 bBuf[2] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 176 bBuf[3] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 177 bBuf[4] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 178
dragica 0:f49f58e4b0c9 179 bRes = WriteFrame(DevID, wAddr, bBuf, 5, bWriteType);
dragica 0:f49f58e4b0c9 180 break;
dragica 0:f49f58e4b0c9 181 case 6:
dragica 0:f49f58e4b0c9 182 bBuf[0] = (dwData & 0x0000FF0000000000) >> 40;
dragica 0:f49f58e4b0c9 183 bBuf[1] = (dwData & 0x000000FF00000000) >> 32;
dragica 0:f49f58e4b0c9 184 bBuf[2] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 185 bBuf[3] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 186 bBuf[4] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 187 bBuf[5] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 188
dragica 0:f49f58e4b0c9 189 bRes = WriteFrame(DevID, wAddr, bBuf, 6, bWriteType);
dragica 0:f49f58e4b0c9 190 break;
dragica 0:f49f58e4b0c9 191 case 7:
dragica 0:f49f58e4b0c9 192 bBuf[0] = (dwData & 0x00FF000000000000) >> 48;
dragica 0:f49f58e4b0c9 193 bBuf[1] = (dwData & 0x0000FF0000000000) >> 40;
dragica 0:f49f58e4b0c9 194 bBuf[2] = (dwData & 0x000000FF00000000) >> 32;
dragica 0:f49f58e4b0c9 195 bBuf[3] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 196 bBuf[4] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 197 bBuf[5] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 198 bBuf[6] = dwData & 0x00000000000000FF;;
dragica 0:f49f58e4b0c9 199
dragica 0:f49f58e4b0c9 200 bRes = WriteFrame(DevID, wAddr, bBuf, 7, bWriteType);
dragica 0:f49f58e4b0c9 201 break;
dragica 0:f49f58e4b0c9 202 case 8:
dragica 0:f49f58e4b0c9 203 bBuf[0] = (dwData & 0xFF00000000000000) >> 56;
dragica 0:f49f58e4b0c9 204 bBuf[1] = (dwData & 0x00FF000000000000) >> 48;
dragica 0:f49f58e4b0c9 205 bBuf[2] = (dwData & 0x0000FF0000000000) >> 40;
dragica 0:f49f58e4b0c9 206 bBuf[3] = (dwData & 0x000000FF00000000) >> 32;
dragica 0:f49f58e4b0c9 207 bBuf[4] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 208 bBuf[5] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 209 bBuf[6] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 210 bBuf[7] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 211
dragica 0:f49f58e4b0c9 212 bRes = WriteFrame(DevID, wAddr, bBuf, 8, bWriteType);
dragica 0:f49f58e4b0c9 213 break;
dragica 0:f49f58e4b0c9 214 default:
dragica 0:f49f58e4b0c9 215 break;
dragica 0:f49f58e4b0c9 216 }
dragica 0:f49f58e4b0c9 217 return bRes;
dragica 0:f49f58e4b0c9 218 }
dragica 0:f49f58e4b0c9 219 int ReadFrameReq(BYTE bID, uint16_t wAddr, BYTE bByteToReturn)
dragica 0:f49f58e4b0c9 220 {
dragica 0:f49f58e4b0c9 221 BYTE bReturn = bByteToReturn - 1;
dragica 0:f49f58e4b0c9 222
dragica 0:f49f58e4b0c9 223 if (bReturn > 127)
dragica 0:f49f58e4b0c9 224 return 0;
dragica 0:f49f58e4b0c9 225
dragica 0:f49f58e4b0c9 226 return WriteFrame(bID, wAddr, &bReturn, 1, FRMWRT_SGL_R);
dragica 0:f49f58e4b0c9 227 }
dragica 2:6700d7f380bd 228
dragica 0:f49f58e4b0c9 229 // eg: ReadReg(nDev_ID,0x0207,bFrame,12, 0, FRMWRT_SGL_R)
dragica 1:1214d9ff2f14 230 int ReadReg (BYTE DevID, uint16_t wAddr, void * bufferData, BYTE numDATAb, uint32_t dwTimeOut, BYTE FRM)
dragica 0:f49f58e4b0c9 231
dragica 0:f49f58e4b0c9 232 {
dragica 0:f49f58e4b0c9 233 //Kopija Martinog koda
dragica 0:f49f58e4b0c9 234 int bRes = 0;
dragica 0:f49f58e4b0c9 235
dragica 0:f49f58e4b0c9 236 switch(numDATAb)
dragica 0:f49f58e4b0c9 237 {
dragica 0:f49f58e4b0c9 238 case 1:
dragica 0:f49f58e4b0c9 239 bRes = ReadFrameReq(DevID, wAddr, 1);
dragica 0:f49f58e4b0c9 240 break;
dragica 0:f49f58e4b0c9 241 case 2:
dragica 0:f49f58e4b0c9 242 bRes = ReadFrameReq(DevID, wAddr, 2);
dragica 0:f49f58e4b0c9 243 break;
dragica 0:f49f58e4b0c9 244 case 3:
dragica 0:f49f58e4b0c9 245 bRes = ReadFrameReq(DevID, wAddr, 3);
dragica 0:f49f58e4b0c9 246 break;
dragica 0:f49f58e4b0c9 247 case 4:
dragica 0:f49f58e4b0c9 248 bRes = ReadFrameReq(DevID, wAddr, 4);
dragica 0:f49f58e4b0c9 249 break;
dragica 0:f49f58e4b0c9 250 default:
dragica 0:f49f58e4b0c9 251 break;
dragica 0:f49f58e4b0c9 252 }
dragica 0:f49f58e4b0c9 253 return bRes;
dragica 0:f49f58e4b0c9 254 }
dragica 0:f49f58e4b0c9 255
dragica 0:f49f58e4b0c9 256 void shutDown()
dragica 0:f49f58e4b0c9 257 {
dragica 0:f49f58e4b0c9 258 WriteReg(0,CONTROL1,0x08,1, FRMWRT_ALL_NR);
dragica 0:f49f58e4b0c9 259 }
dragica 0:f49f58e4b0c9 260
dragica 0:f49f58e4b0c9 261 BYTE recBuff[1024];
dragica 0:f49f58e4b0c9 262 int recLen=0;
dragica 0:f49f58e4b0c9 263 int expected=0;
dragica 0:f49f58e4b0c9 264 volatile bool full = false;
dragica 0:f49f58e4b0c9 265 int rdLen=0;
dragica 0:f49f58e4b0c9 266
dragica 0:f49f58e4b0c9 267 void callback() {
dragica 0:f49f58e4b0c9 268 // Note: you need to actually read from the serial to clear the RX interrupt
dragica 0:f49f58e4b0c9 269 //pc1.printf("* * * Uspesan PRIJEM! * * *\n");
dragica 0:f49f58e4b0c9 270 while(pc.readable()){
dragica 0:f49f58e4b0c9 271 //pc1.printf("jepse");
dragica 0:f49f58e4b0c9 272 //pc1.printf("%d\n", pc.getc());
dragica 0:f49f58e4b0c9 273 recBuff[recLen++]=pc.getc();
dragica 0:f49f58e4b0c9 274 if(expected==0) expected = recBuff[0]+4;
dragica 0:f49f58e4b0c9 275 if(expected==recLen){
dragica 0:f49f58e4b0c9 276 full=true;
dragica 0:f49f58e4b0c9 277 rdLen=expected;
dragica 0:f49f58e4b0c9 278 expected=0;
dragica 0:f49f58e4b0c9 279 recLen=0;
dragica 0:f49f58e4b0c9 280 }
dragica 0:f49f58e4b0c9 281 }
dragica 0:f49f58e4b0c9 282 }
dragica 1:1214d9ff2f14 283 void waitFrame(){
dragica 1:1214d9ff2f14 284 while(!full);
dragica 1:1214d9ff2f14 285 full=false;
dragica 1:1214d9ff2f14 286 for(int i = 0;i<rdLen;i++){
dragica 1:1214d9ff2f14 287 pc1.printf("%X ",recBuff[i]);
dragica 1:1214d9ff2f14 288 }
dragica 1:1214d9ff2f14 289
dragica 2:6700d7f380bd 290 /*pc1.printf("\n\n- - - VOLTAGE - - -\n");
dragica 1:1214d9ff2f14 291 for(int i = 1; i < recBuff[0] - 1; i += 2){
dragica 1:1214d9ff2f14 292 int voltage = recBuff[i+1];
dragica 1:1214d9ff2f14 293 voltage |= (recBuff[i]) << 8;
dragica 1:1214d9ff2f14 294 double vol = ((double)voltage)/65536.0 * 5.0;
dragica 1:1214d9ff2f14 295 pc1.printf("CELL[%d] = %.6f V\n",(recBuff[0] - 1)/2 -(i-1)/2,vol);
dragica 2:6700d7f380bd 296 }*/
dragica 1:1214d9ff2f14 297
dragica 1:1214d9ff2f14 298 pc1.printf("\n");
dragica 1:1214d9ff2f14 299 }
dragica 0:f49f58e4b0c9 300
dragica 0:f49f58e4b0c9 301 int main()
dragica 0:f49f58e4b0c9 302 {
dragica 2:6700d7f380bd 303 bmsLVWakeUp = 1; //po defaultu je HIGHT
dragica 2:6700d7f380bd 304
dragica 1:1214d9ff2f14 305 uint32_t wTemp = 0;
dragica 2:6700d7f380bd 306 pc.attach(&callback);
dragica 0:f49f58e4b0c9 307
dragica 0:f49f58e4b0c9 308 pc1.printf("INICIJALIZACIJA START \n");
dragica 0:f49f58e4b0c9 309 wakeUp();
dragica 0:f49f58e4b0c9 310
dragica 2:6700d7f380bd 311 //CommReset(); <<<-----
dragica 2:6700d7f380bd 312
dragica 2:6700d7f380bd 313 //set 250K baud to BMS first board
dragica 2:6700d7f380bd 314 WriteReg(0,COMM_CTRL,0x343C,2, FRMWRT_ALL_NR);//setting the baud rate to device
dragica 2:6700d7f380bd 315 //****PROVERITI***?
dragica 2:6700d7f380bd 316 WriteReg(0,ECC_TEST,0x00,1, FRMWRT_ALL_NR); //dummy write to the ECC_TESTregisterto syncthe DLL
dragica 0:f49f58e4b0c9 317
dragica 0:f49f58e4b0c9 318 WriteReg(0,CONFIG,0x00,1, FRMWRT_ALL_NR);//making sure auto-address mode is set on all devices(and NOT GPIO address mode)
dragica 0:f49f58e4b0c9 319
dragica 0:f49f58e4b0c9 320 WriteReg(0,CONTROL1,0x01,1, FRMWRT_ALL_NR);//enabling and entering auto-addressing mode on the devices by setting the CONTROL1 register
dragica 0:f49f58e4b0c9 321
dragica 0:f49f58e4b0c9 322 WriteReg(0,CONFIG, 0x01 ,1, FRMWRT_SGL_NR);//If there is only one device,you can instead do one command to assign the device as both the base AND top of stack(set CONFIG to 0x01)
dragica 0:f49f58e4b0c9 323 //****
dragica 1:1214d9ff2f14 324 //ReadReg(0, uint16_t wAddr, void * bufferData, 1, uint32_t dwTimeOut, FRMWRT_SGL_R)//dummy read of ECC_TEST DORADITI!
dragica 0:f49f58e4b0c9 325 //****
dragica 2:6700d7f380bd 326 //waitFrame();?????????????????
dragica 2:6700d7f380bd 327 //COMM_TO DISABLED
dragica 2:6700d7f380bd 328 WriteReg(0, COMM_TO, 0x00, 1, FRMWRT_ALL_NR);//noT(Setting Communications Timeout (10 minute short communication timeout, sleep mode on long communication timeout, long timeout length of 30 minutes))
dragica 0:f49f58e4b0c9 329 WriteReg(0, TX_HOLD_OFF, 0x00, 1, FRMWRT_ALL_NR);//Communications transmit delay set to zero
dragica 0:f49f58e4b0c9 330
dragica 0:f49f58e4b0c9 331 //masking all low level faults (zakomentovacemo ono sto nam ne treba)
dragica 0:f49f58e4b0c9 332
dragica 2:6700d7f380bd 333 WriteReg(0, SYSFLT1_FLT_RST, 0xFFFFFF, 3, FRMWRT_ALL_NR); //reset system faults
dragica 2:6700d7f380bd 334 WriteReg(0, SYSFLT1_FLT_MSK, 0xFFFFFF, 3, FRMWRT_ALL_NR); //mask system faults (so we can test boards and not worry about triggering these faults accidentally)
dragica 0:f49f58e4b0c9 335
dragica 0:f49f58e4b0c9 336 //MASKING_END
dragica 0:f49f58e4b0c9 337
dragica 0:f49f58e4b0c9 338 pc1.printf("INICIJALIZACIJA END \n");
dragica 0:f49f58e4b0c9 339
dragica 0:f49f58e4b0c9 340 pc1.printf("Response? \n");
dragica 0:f49f58e4b0c9 341 // read device ID to see if there is a response
dragica 1:1214d9ff2f14 342 ReadReg(0, 10, &wTemp, 1, 0,FRMWRT_SGL_R );
dragica 0:f49f58e4b0c9 343 wait_ms(10);
dragica 0:f49f58e4b0c9 344 wait(1);
dragica 2:6700d7f380bd 345
dragica 2:6700d7f380bd 346 //----------------------
dragica 0:f49f58e4b0c9 347 WriteReg(0, CONTROL2, 0x00, 1, FRMWRT_ALL_NR);//Set OVUV_EN=0 before changing settings
dragica 0:f49f58e4b0c9 348
dragica 0:f49f58e4b0c9 349 WriteReg(0, 0x29, 0x3F, 1, FRMWRT_ALL_NR);//enabling over voltage under voltage for all 6? cell channels
dragica 0:f49f58e4b0c9 350 WriteReg(0, 0x2A, 0x53, 1, FRMWRT_ALL_NR);//set cell UV to 2.8 V
dragica 0:f49f58e4b0c9 351 WriteReg(0, 0x2B, 0x5B, 1, FRMWRT_ALL_NR);// set cell OV to 4.3V
dragica 0:f49f58e4b0c9 352
dragica 0:f49f58e4b0c9 353 WriteReg(0, CONTROL2, 0x04, 1, FRMWRT_ALL_NR);//OVUV_EN=1
dragica 2:6700d7f380bd 354 //----------------------
dragica 0:f49f58e4b0c9 355
dragica 0:f49f58e4b0c9 356 WriteReg(0, 0x28, 0x3F, 1, FRMWRT_ALL_NR);//configure GPIO as AUX voltage(absolute voltage INSTEAD OF RATIOMETRIC) if necessary
dragica 0:f49f58e4b0c9 357
dragica 0:f49f58e4b0c9 358 WriteReg(0, 0x27, 0x00, 1, FRMWRT_SGL_NR);//modifying the ADC delay of each device individually, since there is only one...modify device 0 delay
dragica 0:f49f58e4b0c9 359
dragica 0:f49f58e4b0c9 360 WriteReg(0, 0x26, 0x08, 1, FRMWRT_ALL_NR);//AUX sample rate 1 MHz,128 decimation ratio
dragica 2:6700d7f380bd 361 //Konsultuj se s DJalom da bi smo odredili sample i low pass filter koji je on stavio na ploci
dragica 0:f49f58e4b0c9 362 WriteReg(0, 0x24, 0x23, 1, FRMWRT_ALL_NR);//1 MHz sample rate,64 decimation ratio,19.7Hz LPF
dragica 2:6700d7f380bd 363 /* ????Odnosi se na DIETEMP pitati Djaleta
dragica 0:f49f58e4b0c9 364 WriteReg(0, 0x25, 0x02, 1, FRMWRT_ALL_NR);//5 ms conversion interval if continuous conversion enabled
dragica 0:f49f58e4b0c9 365 */
dragica 2:6700d7f380bd 366
dragica 0:f49f58e4b0c9 367 WriteReg(0, 0x109, 0x3F, 1, FRMWRT_ALL_NR);// enables ADC for all 6 cell channels
dragica 1:1214d9ff2f14 368 wait_ms(5);// ensure proper settling time for best accuracy
dragica 0:f49f58e4b0c9 369
dragica 2:6700d7f380bd 370 /* ODLUCILE SMO SE ZA CONTINUOUS READ
dragica 0:f49f58e4b0c9 371 //WHICHEVER WE NEED
dragica 0:f49f58e4b0c9 372 //One-Shot ADC Conversions
dragica 0:f49f58e4b0c9 373 WriteReg(0, CONTROL2, 0x01, 1, FRMWRT_ALL_NR);//set the CELL_ADC_GO bit
dragica 1:1214d9ff2f14 374 wait_ms(5);//delay for ADC accuracy
dragica 0:f49f58e4b0c9 375
dragica 0:f49f58e4b0c9 376 //DORADI!
dragica 1:1214d9ff2f14 377 //ReadReg(0, 0x215, void * bufferData, 12, 0, FRMWRT_SGL_R);// will return 6 overhead byte sand 12 data bytes per device, highest device address responds first
dragica 1:1214d9ff2f14 378 wait_ms(1);
dragica 2:6700d7f380bd 379 */
dragica 0:f49f58e4b0c9 380 //Continuous ADC Conversions
dragica 0:f49f58e4b0c9 381 WriteReg(0, 0x25, 0x0A, 1, FRMWRT_ALL_NR);// enable continuous conversion with 5ms conversion interval
dragica 2:6700d7f380bd 382 WriteReg(0, CONTROL2, 0x01, 1, FRMWRT_ALL_R);//set the CELL_ADC_GO bit
dragica 2:6700d7f380bd 383 waitFrame();
dragica 2:6700d7f380bd 384
dragica 1:1214d9ff2f14 385 wait_ms(5);//delay for ADC accuracy
dragica 2:6700d7f380bd 386
dragica 0:f49f58e4b0c9 387 //da li je ovo ispod isto sto i Martin waitFrame? Ako jeste staviti ga u posebnu funkciju, ako nije proveriti da li je uopste potrebno
dragica 2:6700d7f380bd 388 //ReadReg(0, VCELL1H, response_frame, 6*2, 0, FRMWRT_ALL_R); NJIHOV KOD
dragica 1:1214d9ff2f14 389 //ReadReg(0, 0x215, void * bufferData, 12, 0, FRMWRT_SGL_R);// will return 6 overhead byte sand 12 data bytes per device, highest device address responds first
dragica 1:1214d9ff2f14 390 wait_ms(1);//ISTA STVAR KAO IZNAD KOD ONE-SHOT
dragica 2:6700d7f380bd 391
dragica 0:f49f58e4b0c9 392 //martin deo koda
dragica 0:f49f58e4b0c9 393 while (1) {
dragica 0:f49f58e4b0c9 394 pc1.printf("Main Code \n");
dragica 0:f49f58e4b0c9 395 wait(2);
dragica 0:f49f58e4b0c9 396 //*****
dragica 2:6700d7f380bd 397 //WriteReg(0, 2, 0x20, 1, FRMWRT_SGL_R); // send read sampled values command, OVO TREBA PROMENITI AKO VEC ZADRZAVAS OVAJ KOD!!!!!
dragica 2:6700d7f380bd 398 //ReadReg(0, VCELL1H, response_frame, 6*2, 0, FRMWRT_ALL_R); PREPORUCEN KOD
dragica 2:6700d7f380bd 399 //waitFrame();
dragica 2:6700d7f380bd 400
dragica 0:f49f58e4b0c9 401 if(bmsFault)
dragica 0:f49f58e4b0c9 402 pc1.printf("- - - GRESKA FAULT! - - -\n");
dragica 0:f49f58e4b0c9 403
dragica 0:f49f58e4b0c9 404
dragica 0:f49f58e4b0c9 405 }
dragica 0:f49f58e4b0c9 406
dragica 0:f49f58e4b0c9 407
dragica 0:f49f58e4b0c9 408 }