Marta Avramovic / Mbed 2 deprecated FLOW_Sensor_Tester

YFS201 sensor tester. It works on interrupt so you need to set the Interrupt pin as input. Check your Nucleo board pinout list.

Dependencies:   mbed

main.cpp@0:f49f58e4b0c9, 2020-03-20 (annotated)

Committer:
dragica
Date:
Fri Mar 20 23:15:36 2020 +0000
Revision:
0:f49f58e4b0c9
Child:
1:1214d9ff2f14
21.03.2020.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dragica 0:f49f58e4b0c9 1 #include "mbed.h"
dragica 0:f49f58e4b0c9 2 #include <string>
dragica 0:f49f58e4b0c9 3 using std::string;
dragica 0:f49f58e4b0c9 4 //PITATI GDE SE DEFINISU FRAMEOVI
dragica 0:f49f58e4b0c9 5 #define FRMWRT_SGL_R 0x80 // single device read with response
dragica 0:f49f58e4b0c9 6 #define FRMWRT_SGL_NR 0x90 // single device write without response
dragica 0:f49f58e4b0c9 7 #define FRMWRT_ALL_R 0xC0 // general broadcast read with response
dragica 0:f49f58e4b0c9 8 #define FRMWRT_ALL_NR 0xD0 // general broadcast write without response
dragica 0:f49f58e4b0c9 9
dragica 0:f49f58e4b0c9 10 #define CONFIG 0x001
dragica 0:f49f58e4b0c9 11 #define COMM_CTRL 0x20
dragica 0:f49f58e4b0c9 12 #define ECC_TEST 0x11D
dragica 0:f49f58e4b0c9 13 #define CONTROL1 0x105
dragica 0:f49f58e4b0c9 14 #define COMM_TO 0x23
dragica 0:f49f58e4b0c9 15 #define TX_HOLD_OFF 0x22
dragica 0:f49f58e4b0c9 16 #define CONTROL2 0x106
dragica 0:f49f58e4b0c9 17
dragica 0:f49f58e4b0c9 18 typedef unsigned char BYTE;
dragica 0:f49f58e4b0c9 19 //CRC TABELA REKLA MARTA DA JE ISTA, PROVERITI!
dragica 0:f49f58e4b0c9 20 const uint16_t crc16_table[256] = {
dragica 0:f49f58e4b0c9 21 0x0000, 0xC0C1, 0xC181, 0x0140, 0xC301, 0x03C0, 0x0280, 0xC241,
dragica 0:f49f58e4b0c9 22 0xC601, 0x06C0, 0x0780, 0xC741, 0x0500, 0xC5C1, 0xC481, 0x0440,
dragica 0:f49f58e4b0c9 23 0xCC01, 0x0CC0, 0x0D80, 0xCD41, 0x0F00, 0xCFC1, 0xCE81, 0x0E40,
dragica 0:f49f58e4b0c9 24 0x0A00, 0xCAC1, 0xCB81, 0x0B40, 0xC901, 0x09C0, 0x0880, 0xC841,
dragica 0:f49f58e4b0c9 25 0xD801, 0x18C0, 0x1980, 0xD941, 0x1B00, 0xDBC1, 0xDA81, 0x1A40,
dragica 0:f49f58e4b0c9 26 0x1E00, 0xDEC1, 0xDF81, 0x1F40, 0xDD01, 0x1DC0, 0x1C80, 0xDC41,
dragica 0:f49f58e4b0c9 27 0x1400, 0xD4C1, 0xD581, 0x1540, 0xD701, 0x17C0, 0x1680, 0xD641,
dragica 0:f49f58e4b0c9 28 0xD201, 0x12C0, 0x1380, 0xD341, 0x1100, 0xD1C1, 0xD081, 0x1040,
dragica 0:f49f58e4b0c9 29 0xF001, 0x30C0, 0x3180, 0xF141, 0x3300, 0xF3C1, 0xF281, 0x3240,
dragica 0:f49f58e4b0c9 30 0x3600, 0xF6C1, 0xF781, 0x3740, 0xF501, 0x35C0, 0x3480, 0xF441,
dragica 0:f49f58e4b0c9 31 0x3C00, 0xFCC1, 0xFD81, 0x3D40, 0xFF01, 0x3FC0, 0x3E80, 0xFE41,
dragica 0:f49f58e4b0c9 32 0xFA01, 0x3AC0, 0x3B80, 0xFB41, 0x3900, 0xF9C1, 0xF881, 0x3840,
dragica 0:f49f58e4b0c9 33 0x2800, 0xE8C1, 0xE981, 0x2940, 0xEB01, 0x2BC0, 0x2A80, 0xEA41,
dragica 0:f49f58e4b0c9 34 0xEE01, 0x2EC0, 0x2F80, 0xEF41, 0x2D00, 0xEDC1, 0xEC81, 0x2C40,
dragica 0:f49f58e4b0c9 35 0xE401, 0x24C0, 0x2580, 0xE541, 0x2700, 0xE7C1, 0xE681, 0x2640,
dragica 0:f49f58e4b0c9 36 0x2200, 0xE2C1, 0xE381, 0x2340, 0xE101, 0x21C0, 0x2080, 0xE041,
dragica 0:f49f58e4b0c9 37 0xA001, 0x60C0, 0x6180, 0xA141, 0x6300, 0xA3C1, 0xA281, 0x6240,
dragica 0:f49f58e4b0c9 38 0x6600, 0xA6C1, 0xA781, 0x6740, 0xA501, 0x65C0, 0x6480, 0xA441,
dragica 0:f49f58e4b0c9 39 0x6C00, 0xACC1, 0xAD81, 0x6D40, 0xAF01, 0x6FC0, 0x6E80, 0xAE41,
dragica 0:f49f58e4b0c9 40 0xAA01, 0x6AC0, 0x6B80, 0xAB41, 0x6900, 0xA9C1, 0xA881, 0x6840,
dragica 0:f49f58e4b0c9 41 0x7800, 0xB8C1, 0xB981, 0x7940, 0xBB01, 0x7BC0, 0x7A80, 0xBA41,
dragica 0:f49f58e4b0c9 42 0xBE01, 0x7EC0, 0x7F80, 0xBF41, 0x7D00, 0xBDC1, 0xBC81, 0x7C40,
dragica 0:f49f58e4b0c9 43 0xB401, 0x74C0, 0x7580, 0xB541, 0x7700, 0xB7C1, 0xB681, 0x7640,
dragica 0:f49f58e4b0c9 44 0x7200, 0xB2C1, 0xB381, 0x7340, 0xB101, 0x71C0, 0x7080, 0xB041,
dragica 0:f49f58e4b0c9 45 0x5000, 0x90C1, 0x9181, 0x5140, 0x9301, 0x53C0, 0x5280, 0x9241,
dragica 0:f49f58e4b0c9 46 0x9601, 0x56C0, 0x5780, 0x9741, 0x5500, 0x95C1, 0x9481, 0x5440,
dragica 0:f49f58e4b0c9 47 0x9C01, 0x5CC0, 0x5D80, 0x9D41, 0x5F00, 0x9FC1, 0x9E81, 0x5E40,
dragica 0:f49f58e4b0c9 48 0x5A00, 0x9AC1, 0x9B81, 0x5B40, 0x9901, 0x59C0, 0x5880, 0x9841,
dragica 0:f49f58e4b0c9 49 0x8801, 0x48C0, 0x4980, 0x8941, 0x4B00, 0x8BC1, 0x8A81, 0x4A40,
dragica 0:f49f58e4b0c9 50 0x4E00, 0x8EC1, 0x8F81, 0x4F40, 0x8D01, 0x4DC0, 0x4C80, 0x8C41,
dragica 0:f49f58e4b0c9 51 0x4400, 0x84C1, 0x8581, 0x4540, 0x8701, 0x47C0, 0x4680, 0x8641,
dragica 0:f49f58e4b0c9 52 0x8201, 0x42C0, 0x4380, 0x8341, 0x4100, 0x81C1, 0x8081, 0x4040
dragica 0:f49f58e4b0c9 53 };
dragica 0:f49f58e4b0c9 54 //PROVERITI PINOVE
dragica 0:f49f58e4b0c9 55 DigitalOut bmsLVWakeUp(PB_0);//PC_9);
dragica 0:f49f58e4b0c9 56 DigitalIn bmsFault(PA_4);//PC_8);
dragica 0:f49f58e4b0c9 57
dragica 0:f49f58e4b0c9 58 Serial pc(PA_0, PA_1, 250000);//PA_9, PA_10,250000);
dragica 0:f49f58e4b0c9 59 Serial pc1(USBTX, USBRX, 9600);//PC_10, PC_11,9600);
dragica 0:f49f58e4b0c9 60
dragica 0:f49f58e4b0c9 61 void wakeUp()
dragica 0:f49f58e4b0c9 62 {
dragica 0:f49f58e4b0c9 63 bmsLVWakeUp=0;
dragica 0:f49f58e4b0c9 64 wait_us(300);
dragica 0:f49f58e4b0c9 65 bmsLVWakeUp=1;
dragica 0:f49f58e4b0c9 66 wait_ms(12);
dragica 0:f49f58e4b0c9 67 }
dragica 0:f49f58e4b0c9 68
dragica 0:f49f58e4b0c9 69 uint16_t CRC16(BYTE *pBuf, int nLen)
dragica 0:f49f58e4b0c9 70 {
dragica 0:f49f58e4b0c9 71 uint16_t wCRC = 0;
dragica 0:f49f58e4b0c9 72 int i;
dragica 0:f49f58e4b0c9 73
dragica 0:f49f58e4b0c9 74 for (i = 0; i < nLen; i++)
dragica 0:f49f58e4b0c9 75 {
dragica 0:f49f58e4b0c9 76 wCRC ^= (*pBuf++) & 0x00FF;
dragica 0:f49f58e4b0c9 77 wCRC = crc16_table[wCRC & 0x00FF] ^ (wCRC >> 8);
dragica 0:f49f58e4b0c9 78 }
dragica 0:f49f58e4b0c9 79
dragica 0:f49f58e4b0c9 80 return wCRC;
dragica 0:f49f58e4b0c9 81 }
dragica 0:f49f58e4b0c9 82 void posaljiUARTu(int length, uint8_t * data)
dragica 0:f49f58e4b0c9 83 {
dragica 0:f49f58e4b0c9 84 for(int i=0;i<length;i++)
dragica 0:f49f58e4b0c9 85 pc.putc(data[i]);
dragica 0:f49f58e4b0c9 86 wait_ms(1);
dragica 0:f49f58e4b0c9 87 }
dragica 0:f49f58e4b0c9 88
dragica 0:f49f58e4b0c9 89
dragica 0:f49f58e4b0c9 90 int WriteFrame(BYTE bID, uint16_t& wAddr, BYTE * pData, BYTE bLen, BYTE bWriteType)//pitati Martu!!
dragica 0:f49f58e4b0c9 91 {
dragica 0:f49f58e4b0c9 92
dragica 0:f49f58e4b0c9 93 int bPktLen = 0;
dragica 0:f49f58e4b0c9 94 BYTE pFrame[32];
dragica 0:f49f58e4b0c9 95 BYTE * pBuf = pFrame;
dragica 0:f49f58e4b0c9 96 uint16_t wCRC;
dragica 0:f49f58e4b0c9 97
dragica 0:f49f58e4b0c9 98 if (bLen == 7 || bLen > 8)
dragica 0:f49f58e4b0c9 99 return 0;
dragica 0:f49f58e4b0c9 100
dragica 0:f49f58e4b0c9 101 memset(pFrame, 0x7F, sizeof(pFrame));
dragica 0:f49f58e4b0c9 102 if (wAddr > 255) {
dragica 0:f49f58e4b0c9 103 *pBuf++ = 0x88 | bWriteType | bLen; // use 16-bit address
dragica 0:f49f58e4b0c9 104 if (bWriteType == FRMWRT_SGL_R || bWriteType == FRMWRT_SGL_NR )//(bWriteType != FRMWRT_ALL_NR)// || (bWriteType != FRMWRT_ALL_R))
dragica 0:f49f58e4b0c9 105 {
dragica 0:f49f58e4b0c9 106 *pBuf++ = (bID & 0x00FF);
dragica 0:f49f58e4b0c9 107 }
dragica 0:f49f58e4b0c9 108 *pBuf++ = (wAddr & 0xFF00) >> 8;
dragica 0:f49f58e4b0c9 109 *pBuf++ = wAddr & 0x00FF;
dragica 0:f49f58e4b0c9 110 }
dragica 0:f49f58e4b0c9 111 else {
dragica 0:f49f58e4b0c9 112
dragica 0:f49f58e4b0c9 113 *pBuf++ = 0x80 | bWriteType | bLen; // use 8-bit address
dragica 0:f49f58e4b0c9 114 if (bWriteType == FRMWRT_SGL_R || bWriteType == FRMWRT_SGL_NR )
dragica 0:f49f58e4b0c9 115 {
dragica 0:f49f58e4b0c9 116 *pBuf++ = (bID & 0x00FF);
dragica 0:f49f58e4b0c9 117 }
dragica 0:f49f58e4b0c9 118 *pBuf++ = wAddr & 0x00FF;
dragica 0:f49f58e4b0c9 119 }
dragica 0:f49f58e4b0c9 120
dragica 0:f49f58e4b0c9 121 while(bLen--)
dragica 0:f49f58e4b0c9 122 *pBuf++ = *pData++;
dragica 0:f49f58e4b0c9 123
dragica 0:f49f58e4b0c9 124 bPktLen = pBuf - pFrame;
dragica 0:f49f58e4b0c9 125
dragica 0:f49f58e4b0c9 126 wCRC = CRC16(pFrame, bPktLen);
dragica 0:f49f58e4b0c9 127 *pBuf++ = wCRC & 0x00FF;
dragica 0:f49f58e4b0c9 128 *pBuf++ = (wCRC & 0xFF00) >> 8;
dragica 0:f49f58e4b0c9 129 bPktLen += 2;
dragica 0:f49f58e4b0c9 130
dragica 0:f49f58e4b0c9 131 //sciSend(scilinREG, bPktLen, pFrame);
dragica 0:f49f58e4b0c9 132
dragica 0:f49f58e4b0c9 133 posaljiUARTu(bPktLen,pFrame);
dragica 0:f49f58e4b0c9 134
dragica 0:f49f58e4b0c9 135 return bPktLen;
dragica 0:f49f58e4b0c9 136 }
dragica 0:f49f58e4b0c9 137
dragica 0:f49f58e4b0c9 138 int WriteReg(BYTE DevID, uint16_t wAddr, uint64_t dwData, BYTE numDATAb, BYTE bWriteType)// eg: WriteReg(nDev_ID,0x0106,0x01,1, FRMWRT_SGL_NR)
dragica 0:f49f58e4b0c9 139 {
dragica 0:f49f58e4b0c9 140 //Kopija Martinog koda
dragica 0:f49f58e4b0c9 141 int bRes = 0;
dragica 0:f49f58e4b0c9 142 BYTE bBuf[8] = {0, 0, 0, 0, 0, 0, 0, 0};
dragica 0:f49f58e4b0c9 143 switch(numDATAb)
dragica 0:f49f58e4b0c9 144 {
dragica 0:f49f58e4b0c9 145 case 1:
dragica 0:f49f58e4b0c9 146 bBuf[0] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 147
dragica 0:f49f58e4b0c9 148 bRes = WriteFrame(DevID, wAddr, bBuf, 1, bWriteType);
dragica 0:f49f58e4b0c9 149 break;
dragica 0:f49f58e4b0c9 150 case 2:
dragica 0:f49f58e4b0c9 151 bBuf[0] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 152 bBuf[1] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 153
dragica 0:f49f58e4b0c9 154 bRes = WriteFrame(DevID, wAddr, bBuf, 2, bWriteType);
dragica 0:f49f58e4b0c9 155 break;
dragica 0:f49f58e4b0c9 156 case 3:
dragica 0:f49f58e4b0c9 157 bBuf[0] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 158 bBuf[1] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 159 bBuf[2] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 160
dragica 0:f49f58e4b0c9 161 bRes = WriteFrame(DevID, wAddr, bBuf, 3, bWriteType);
dragica 0:f49f58e4b0c9 162 break;
dragica 0:f49f58e4b0c9 163 case 4:
dragica 0:f49f58e4b0c9 164 bBuf[0] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 165 bBuf[1] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 166 bBuf[2] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 167 bBuf[3] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 168
dragica 0:f49f58e4b0c9 169 bRes = WriteFrame(DevID, wAddr, bBuf, 4, bWriteType);
dragica 0:f49f58e4b0c9 170 break;
dragica 0:f49f58e4b0c9 171 case 5:
dragica 0:f49f58e4b0c9 172 bBuf[0] = (dwData & 0x000000FF00000000) >> 32;
dragica 0:f49f58e4b0c9 173 bBuf[1] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 174 bBuf[2] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 175 bBuf[3] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 176 bBuf[4] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 177
dragica 0:f49f58e4b0c9 178 bRes = WriteFrame(DevID, wAddr, bBuf, 5, bWriteType);
dragica 0:f49f58e4b0c9 179 break;
dragica 0:f49f58e4b0c9 180 case 6:
dragica 0:f49f58e4b0c9 181 bBuf[0] = (dwData & 0x0000FF0000000000) >> 40;
dragica 0:f49f58e4b0c9 182 bBuf[1] = (dwData & 0x000000FF00000000) >> 32;
dragica 0:f49f58e4b0c9 183 bBuf[2] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 184 bBuf[3] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 185 bBuf[4] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 186 bBuf[5] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 187
dragica 0:f49f58e4b0c9 188 bRes = WriteFrame(DevID, wAddr, bBuf, 6, bWriteType);
dragica 0:f49f58e4b0c9 189 break;
dragica 0:f49f58e4b0c9 190 case 7:
dragica 0:f49f58e4b0c9 191 bBuf[0] = (dwData & 0x00FF000000000000) >> 48;
dragica 0:f49f58e4b0c9 192 bBuf[1] = (dwData & 0x0000FF0000000000) >> 40;
dragica 0:f49f58e4b0c9 193 bBuf[2] = (dwData & 0x000000FF00000000) >> 32;
dragica 0:f49f58e4b0c9 194 bBuf[3] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 195 bBuf[4] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 196 bBuf[5] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 197 bBuf[6] = dwData & 0x00000000000000FF;;
dragica 0:f49f58e4b0c9 198
dragica 0:f49f58e4b0c9 199 bRes = WriteFrame(DevID, wAddr, bBuf, 7, bWriteType);
dragica 0:f49f58e4b0c9 200 break;
dragica 0:f49f58e4b0c9 201 case 8:
dragica 0:f49f58e4b0c9 202 bBuf[0] = (dwData & 0xFF00000000000000) >> 56;
dragica 0:f49f58e4b0c9 203 bBuf[1] = (dwData & 0x00FF000000000000) >> 48;
dragica 0:f49f58e4b0c9 204 bBuf[2] = (dwData & 0x0000FF0000000000) >> 40;
dragica 0:f49f58e4b0c9 205 bBuf[3] = (dwData & 0x000000FF00000000) >> 32;
dragica 0:f49f58e4b0c9 206 bBuf[4] = (dwData & 0x00000000FF000000) >> 24;
dragica 0:f49f58e4b0c9 207 bBuf[5] = (dwData & 0x0000000000FF0000) >> 16;
dragica 0:f49f58e4b0c9 208 bBuf[6] = (dwData & 0x000000000000FF00) >> 8;
dragica 0:f49f58e4b0c9 209 bBuf[7] = dwData & 0x00000000000000FF;
dragica 0:f49f58e4b0c9 210
dragica 0:f49f58e4b0c9 211 bRes = WriteFrame(DevID, wAddr, bBuf, 8, bWriteType);
dragica 0:f49f58e4b0c9 212 break;
dragica 0:f49f58e4b0c9 213 default:
dragica 0:f49f58e4b0c9 214 break;
dragica 0:f49f58e4b0c9 215 }
dragica 0:f49f58e4b0c9 216 return bRes;
dragica 0:f49f58e4b0c9 217 }
dragica 0:f49f58e4b0c9 218 int ReadFrameReq(BYTE bID, uint16_t wAddr, BYTE bByteToReturn)
dragica 0:f49f58e4b0c9 219 {
dragica 0:f49f58e4b0c9 220 BYTE bReturn = bByteToReturn - 1;
dragica 0:f49f58e4b0c9 221
dragica 0:f49f58e4b0c9 222 if (bReturn > 127)
dragica 0:f49f58e4b0c9 223 return 0;
dragica 0:f49f58e4b0c9 224
dragica 0:f49f58e4b0c9 225 return WriteFrame(bID, wAddr, &bReturn, 1, FRMWRT_SGL_R);
dragica 0:f49f58e4b0c9 226 }
dragica 0:f49f58e4b0c9 227 // eg: ReadReg(nDev_ID,0x0207,bFrame,12, 0, FRMWRT_SGL_R)
dragica 0:f49f58e4b0c9 228 int ReadReg(BYTE DevID, uint16_t wAddr, void * bufferData, BYTE numDATAb, uint32_t dwTimeOut, BYTE FRMWRT_SGL_R)
dragica 0:f49f58e4b0c9 229
dragica 0:f49f58e4b0c9 230 {
dragica 0:f49f58e4b0c9 231 //Kopija Martinog koda
dragica 0:f49f58e4b0c9 232 int bRes = 0;
dragica 0:f49f58e4b0c9 233
dragica 0:f49f58e4b0c9 234 switch(numDATAb)
dragica 0:f49f58e4b0c9 235 {
dragica 0:f49f58e4b0c9 236 case 1:
dragica 0:f49f58e4b0c9 237 bRes = ReadFrameReq(DevID, wAddr, 1);
dragica 0:f49f58e4b0c9 238 break;
dragica 0:f49f58e4b0c9 239 case 2:
dragica 0:f49f58e4b0c9 240 bRes = ReadFrameReq(DevID, wAddr, 2);
dragica 0:f49f58e4b0c9 241 break;
dragica 0:f49f58e4b0c9 242 case 3:
dragica 0:f49f58e4b0c9 243 bRes = ReadFrameReq(DevID, wAddr, 3);
dragica 0:f49f58e4b0c9 244 break;
dragica 0:f49f58e4b0c9 245 case 4:
dragica 0:f49f58e4b0c9 246 bRes = ReadFrameReq(DevID, wAddr, 4);
dragica 0:f49f58e4b0c9 247 break;
dragica 0:f49f58e4b0c9 248 default:
dragica 0:f49f58e4b0c9 249 break;
dragica 0:f49f58e4b0c9 250 }
dragica 0:f49f58e4b0c9 251 return bRes;
dragica 0:f49f58e4b0c9 252 }
dragica 0:f49f58e4b0c9 253
dragica 0:f49f58e4b0c9 254 void shutDown()
dragica 0:f49f58e4b0c9 255 {
dragica 0:f49f58e4b0c9 256 WriteReg(0,CONTROL1,0x08,1, FRMWRT_ALL_NR);
dragica 0:f49f58e4b0c9 257 }
dragica 0:f49f58e4b0c9 258
dragica 0:f49f58e4b0c9 259 BYTE recBuff[1024];
dragica 0:f49f58e4b0c9 260 int recLen=0;
dragica 0:f49f58e4b0c9 261 int expected=0;
dragica 0:f49f58e4b0c9 262 volatile bool full = false;
dragica 0:f49f58e4b0c9 263 int rdLen=0;
dragica 0:f49f58e4b0c9 264
dragica 0:f49f58e4b0c9 265 void callback() {
dragica 0:f49f58e4b0c9 266 // Note: you need to actually read from the serial to clear the RX interrupt
dragica 0:f49f58e4b0c9 267 //pc1.printf("* * * Uspesan PRIJEM! * * *\n");
dragica 0:f49f58e4b0c9 268 while(pc.readable()){
dragica 0:f49f58e4b0c9 269 //pc1.printf("jepse");
dragica 0:f49f58e4b0c9 270 //pc1.printf("%d\n", pc.getc());
dragica 0:f49f58e4b0c9 271 recBuff[recLen++]=pc.getc();
dragica 0:f49f58e4b0c9 272 if(expected==0) expected = recBuff[0]+4;
dragica 0:f49f58e4b0c9 273 if(expected==recLen){
dragica 0:f49f58e4b0c9 274 full=true;
dragica 0:f49f58e4b0c9 275 rdLen=expected;
dragica 0:f49f58e4b0c9 276 expected=0;
dragica 0:f49f58e4b0c9 277 recLen=0;
dragica 0:f49f58e4b0c9 278 }
dragica 0:f49f58e4b0c9 279 }
dragica 0:f49f58e4b0c9 280 }
dragica 0:f49f58e4b0c9 281
dragica 0:f49f58e4b0c9 282
dragica 0:f49f58e4b0c9 283 int main()
dragica 0:f49f58e4b0c9 284 {
dragica 0:f49f58e4b0c9 285 pc.attach(&callback);//sta radi callback?
dragica 0:f49f58e4b0c9 286
dragica 0:f49f58e4b0c9 287 sciSetBaudrate(scilinREG,250000);
dragica 0:f49f58e4b0c9 288 pc1.printf("INICIJALIZACIJA START \n");
dragica 0:f49f58e4b0c9 289 wakeUp();
dragica 0:f49f58e4b0c9 290
dragica 0:f49f58e4b0c9 291 sciSetBaudrate(scilinREG,250000);
dragica 0:f49f58e4b0c9 292 CommReset();
dragica 0:f49f58e4b0c9 293 WriteReg(0,COMM_CTRL,0x3C3C,2, FRMWRT_ALL_NR);//setting the baud rate to device
dragica 0:f49f58e4b0c9 294 sciSetBaudrate(scilinREG,1000000);
dragica 0:f49f58e4b0c9 295
dragica 0:f49f58e4b0c9 296 WriteReg(0,ECC_TEST,0x00,1, FRMWRT_ALL_NR); //dummy write to the ECC_TESTregisterto syncthe DLL
dragica 0:f49f58e4b0c9 297
dragica 0:f49f58e4b0c9 298 WriteReg(0,CONFIG,0x00,1, FRMWRT_ALL_NR);//making sure auto-address mode is set on all devices(and NOT GPIO address mode)
dragica 0:f49f58e4b0c9 299
dragica 0:f49f58e4b0c9 300 WriteReg(0,CONTROL1,0x01,1, FRMWRT_ALL_NR);//enabling and entering auto-addressing mode on the devices by setting the CONTROL1 register
dragica 0:f49f58e4b0c9 301
dragica 0:f49f58e4b0c9 302 WriteReg(0,CONFIG, 0x01 ,1, FRMWRT_SGL_NR);//If there is only one device,you can instead do one command to assign the device as both the base AND top of stack(set CONFIG to 0x01)
dragica 0:f49f58e4b0c9 303 //****
dragica 0:f49f58e4b0c9 304 ReadReg(0, uint16_t wAddr, void * bufferData, 1, uint32_t dwTimeOut, FRMWRT_SGL_R)//dummy read of ECC_TEST DORADITI!
dragica 0:f49f58e4b0c9 305 //****
dragica 0:f49f58e4b0c9 306
dragica 0:f49f58e4b0c9 307 WriteReg(0, COMM_TO, 0x56, 1, FRMWRT_ALL_NR);//Setting Communications Timeout (10 minute short communication timeout, sleep mode on long communication timeout, long timeout length of 30 minutes)
dragica 0:f49f58e4b0c9 308
dragica 0:f49f58e4b0c9 309 WriteReg(0, TX_HOLD_OFF, 0x00, 1, FRMWRT_ALL_NR);//Communications transmit delay set to zero
dragica 0:f49f58e4b0c9 310
dragica 0:f49f58e4b0c9 311 //masking all low level faults (zakomentovacemo ono sto nam ne treba)
dragica 0:f49f58e4b0c9 312
dragica 0:f49f58e4b0c9 313 WriteReg(0, 0x0002, 0x3F, 1, FRMWRT_ALL_NR);//GPIO
dragica 0:f49f58e4b0c9 314 WriteReg(0, 0x0003, 0x3F, 1, FRMWRT_ALL_NR);//UV
dragica 0:f49f58e4b0c9 315 WriteReg(0, 0x0004, 0x3F, 1, FRMWRT_ALL_NR);//OV
dragica 0:f49f58e4b0c9 316 WriteReg(0, 0x0005, 0x3F, 1, FRMWRT_ALL_NR);//UT
dragica 0:f49f58e4b0c9 317 WriteReg(0, 0x0006, 0x3F, 1, FRMWRT_ALL_NR);//OT
dragica 0:f49f58e4b0c9 318 WriteReg(0, 0x0007, 0x07, 1, FRMWRT_ALL_NR);//all tone faults
dragica 0:f49f58e4b0c9 319 WriteReg(0, 0x0008, 0x07, 1, FRMWRT_ALL_NR);//UART
dragica 0:f49f58e4b0c9 320 WriteReg(0, 0x0009, 0x3F, 1, FRMWRT_ALL_NR);//UART
dragica 0:f49f58e4b0c9 321 WriteReg(0, 0x000A, 0x3F, 1, FRMWRT_ALL_NR);//UART
dragica 0:f49f58e4b0c9 322 WriteReg(0, 0x000B, 0x03, 1, FRMWRT_ALL_NR);//UART
dragica 0:f49f58e4b0c9 323 WriteReg(0, 0x000C, 0x3F, 1, FRMWRT_ALL_NR);//COMH
dragica 0:f49f58e4b0c9 324 WriteReg(0, 0x000D, 0x3F, 1, FRMWRT_ALL_NR);//COMH
dragica 0:f49f58e4b0c9 325 WriteReg(0, 0x000E, 0x3F, 1, FRMWRT_ALL_NR);//COMH
dragica 0:f49f58e4b0c9 326 WriteReg(0, 0x000F, 0x03, 1, FRMWRT_ALL_NR);//COMH
dragica 0:f49f58e4b0c9 327 WriteReg(0, 0x0010, 0x3F, 1, FRMWRT_ALL_NR);//COML
dragica 0:f49f58e4b0c9 328 WriteReg(0, 0x0011, 0x3F, 1, FRMWRT_ALL_NR);//COML
dragica 0:f49f58e4b0c9 329 WriteReg(0, 0x0012, 0x3F, 1, FRMWRT_ALL_NR);//COML
dragica 0:f49f58e4b0c9 330 WriteReg(0, 0x0013, 0x03, 1, FRMWRT_ALL_NR);//COML
dragica 0:f49f58e4b0c9 331 WriteReg(0, 0x0014, 0x07, 1, FRMWRT_ALL_NR);//OTP
dragica 0:f49f58e4b0c9 332 WriteReg(0, 0x0015, 0xFF, 1, FRMWRT_ALL_NR);//POWER RAIL
dragica 0:f49f58e4b0c9 333 WriteReg(0, 0x0016, 0x7F, 1, FRMWRT_ALL_NR);//SYS_FAULT1
dragica 0:f49f58e4b0c9 334 WriteReg(0, 0x0017, 0xFF, 1, FRMWRT_ALL_NR);//SYS_FAULT2
dragica 0:f49f58e4b0c9 335 WriteReg(0, 0x0018, 0x7F, 1, FRMWRT_ALL_NR);//SYS_FAULT3
dragica 0:f49f58e4b0c9 336 WriteReg(0, 0x0019, 0x03, 1, FRMWRT_ALL_NR);//OVUV BIST
dragica 0:f49f58e4b0c9 337 WriteReg(0, 0x001A, 0xFF, 1, FRMWRT_ALL_NR);//OTUT BIST
dragica 0:f49f58e4b0c9 338
dragica 0:f49f58e4b0c9 339 //MASKING_END
dragica 0:f49f58e4b0c9 340
dragica 0:f49f58e4b0c9 341 pc1.printf("INICIJALIZACIJA END \n");
dragica 0:f49f58e4b0c9 342
dragica 0:f49f58e4b0c9 343 pc1.printf("Response? \n");
dragica 0:f49f58e4b0c9 344 // read device ID to see if there is a response
dragica 0:f49f58e4b0c9 345 ReadReg(0, 10, &wTemp, 1, 0);
dragica 0:f49f58e4b0c9 346 wait_ms(10);
dragica 0:f49f58e4b0c9 347 wait(1);
dragica 0:f49f58e4b0c9 348
dragica 0:f49f58e4b0c9 349 WriteReg(0, CONTROL2, 0x00, 1, FRMWRT_ALL_NR);//Set OVUV_EN=0 before changing settings
dragica 0:f49f58e4b0c9 350
dragica 0:f49f58e4b0c9 351 WriteReg(0, 0x29, 0x3F, 1, FRMWRT_ALL_NR);//enabling over voltage under voltage for all 6? cell channels
dragica 0:f49f58e4b0c9 352 WriteReg(0, 0x2A, 0x53, 1, FRMWRT_ALL_NR);//set cell UV to 2.8 V
dragica 0:f49f58e4b0c9 353 WriteReg(0, 0x2B, 0x5B, 1, FRMWRT_ALL_NR);// set cell OV to 4.3V
dragica 0:f49f58e4b0c9 354
dragica 0:f49f58e4b0c9 355 WriteReg(0, CONTROL2, 0x04, 1, FRMWRT_ALL_NR);//OVUV_EN=1
dragica 0:f49f58e4b0c9 356
dragica 0:f49f58e4b0c9 357 WriteReg(0, 0x28, 0x3F, 1, FRMWRT_ALL_NR);//configure GPIO as AUX voltage(absolute voltage INSTEAD OF RATIOMETRIC) if necessary
dragica 0:f49f58e4b0c9 358
dragica 0:f49f58e4b0c9 359 WriteReg(0, 0x27, 0x00, 1, FRMWRT_SGL_NR);//modifying the ADC delay of each device individually, since there is only one...modify device 0 delay
dragica 0:f49f58e4b0c9 360
dragica 0:f49f58e4b0c9 361 WriteReg(0, 0x26, 0x08, 1, FRMWRT_ALL_NR);//AUX sample rate 1 MHz,128 decimation ratio
dragica 0:f49f58e4b0c9 362 WriteReg(0, 0x24, 0x23, 1, FRMWRT_ALL_NR);//1 MHz sample rate,64 decimation ratio,19.7Hz LPF
dragica 0:f49f58e4b0c9 363 WriteReg(0, 0x25, 0x02, 1, FRMWRT_ALL_NR);//5 ms conversion interval if continuous conversion enabled
dragica 0:f49f58e4b0c9 364
dragica 0:f49f58e4b0c9 365 /*
dragica 0:f49f58e4b0c9 366 nSent= WriteReg(0,CONTROL2,0x10,1, FRMWRT_ALL_NR);// enable TSREF-external temperature sensors
dragica 0:f49f58e4b0c9 367 delayms(2);// provides settling time for TSREF
dragica 0:f49f58e4b0c9 368 */
dragica 0:f49f58e4b0c9 369
dragica 0:f49f58e4b0c9 370 WriteReg(0, 0x109, 0x3F, 1, FRMWRT_ALL_NR);// enables ADC for all 6 cell channels
dragica 0:f49f58e4b0c9 371 delayms(5);// ensure proper settling time for best accuracy
dragica 0:f49f58e4b0c9 372
dragica 0:f49f58e4b0c9 373
dragica 0:f49f58e4b0c9 374 //WHICHEVER WE NEED
dragica 0:f49f58e4b0c9 375 //One-Shot ADC Conversions
dragica 0:f49f58e4b0c9 376 WriteReg(0, CONTROL2, 0x01, 1, FRMWRT_ALL_NR);//set the CELL_ADC_GO bit
dragica 0:f49f58e4b0c9 377 delayms(5);//delay for ADC accuracy
dragica 0:f49f58e4b0c9 378
dragica 0:f49f58e4b0c9 379 //DORADI!
dragica 0:f49f58e4b0c9 380 ReadReg(0, 0x215, void * bufferData, 12, 0, FRMWRT_SGL_R);// will return 6 overhead byte sand 12 data bytes per device, highest device address responds first
dragica 0:f49f58e4b0c9 381 delayms(1);
dragica 0:f49f58e4b0c9 382
dragica 0:f49f58e4b0c9 383 //Continuous ADC Conversions
dragica 0:f49f58e4b0c9 384 WriteReg(0, 0x25, 0x0A, 1, FRMWRT_ALL_NR);// enable continuous conversion with 5ms conversion interval
dragica 0:f49f58e4b0c9 385 WriteReg(0, CONTROL2, 0x01, 1, FRMWRT_ALL_NR);//set the CELL_ADC_GO bit
dragica 0:f49f58e4b0c9 386 delayms(5);//delay for ADC accuracy
dragica 0:f49f58e4b0c9 387 //da li je ovo ispod isto sto i Martin waitFrame? Ako jeste staviti ga u posebnu funkciju, ako nije proveriti da li je uopste potrebno
dragica 0:f49f58e4b0c9 388 ReadReg(0, 0x215, void * bufferData, 12, 0, FRMWRT_SGL_R);// will return 6 overhead byte sand 12 data bytes per device, highest device address responds first
dragica 0:f49f58e4b0c9 389 delayms(1);//ISTA STVAR KAO IZNAD KOD ONE-SHOT
dragica 0:f49f58e4b0c9 390 //martin deo koda
dragica 0:f49f58e4b0c9 391 while (1) {
dragica 0:f49f58e4b0c9 392 pc1.printf("Main Code \n");
dragica 0:f49f58e4b0c9 393 wait(2);
dragica 0:f49f58e4b0c9 394 nDev_ID = 0;
dragica 0:f49f58e4b0c9 395 //*****
dragica 0:f49f58e4b0c9 396 WriteReg(nDev_ID, 2, 0x20, 1, FRMWRT_SGL_R); // send read sampled values command, OVO TREBA PROMENITI AKO VEC ZADRZAVAS OVAJ KOD!!!!!
dragica 0:f49f58e4b0c9 397 //*****
dragica 0:f49f58e4b0c9 398 waitFrame();
dragica 0:f49f58e4b0c9 399 if(bmsFault)
dragica 0:f49f58e4b0c9 400 pc1.printf("- - - GRESKA FAULT! - - -\n");
dragica 0:f49f58e4b0c9 401
dragica 0:f49f58e4b0c9 402
dragica 0:f49f58e4b0c9 403 }
dragica 0:f49f58e4b0c9 404
dragica 0:f49f58e4b0c9 405
dragica 0:f49f58e4b0c9 406 }