Marta Avramovic / Mbed 2 deprecated BMS_by_Marta

First version. No response from BMS Slave. Very sad story.

Dependencies:   mbed

main.cpp@2:234a2c91b0e0, 2019-04-12 (annotated)

Committer:
renemagrit
Date:
Fri Apr 12 17:55:17 2019 +0000
Revision:
2:234a2c91b0e0
Parent:
0:b3d31a017887 
BMS Main Example

Who changed what in which revision?

UserRevisionLine numberNew contents of line
renemagrit 2:234a2c91b0e0 1 /**
renemagrit 2:234a2c91b0e0 2 *
renemagrit 2:234a2c91b0e0 3 * @file main.c
renemagrit 2:234a2c91b0e0 4 * @brief this file contains example command sequences and functions to interface with the bq76PL455A-Q1 from a
renemagrit 2:234a2c91b0e0 5 * microcontroller. The examples provided are described in the bq76PL455A-Q1 Software Design Reference (SLVA617A)
renemagrit 2:234a2c91b0e0 6 * and the sections that correlate to each example are noted in the comments.
renemagrit 2:234a2c91b0e0 7 *
renemagrit 2:234a2c91b0e0 8 * This code was written for the TMS570LS04x Launchpad Board, modified to remove R8, allowing use of the SCI1 UART.
renemagrit 2:234a2c91b0e0 9 * A bq76PL455A-Q1 EVM single-ended communication interface is connected to the Boosterpack connectors J1 and J2 as
renemagrit 2:234a2c91b0e0 10 * shown below. Connection of these boards must be made by the user.
renemagrit 2:234a2c91b0e0 11 *
renemagrit 2:234a2c91b0e0 12 * J1 pin 1 (+3V3) -> bq76PL455A-Q1 EVM J3 pin 3 (VIO)
renemagrit 2:234a2c91b0e0 13 * J1 pin 3 (SCI1_RX) -> bq76PL455A-Q1 EVM J3 pin 5 (TX) **remove R8 from TMS570LS04x Launchpad
renemagrit 2:234a2c91b0e0 14 * J1 pin 4 (SCI1_TX) -> bq76PL455A-Q1 EVM J3 pin 4 (RX)
renemagrit 2:234a2c91b0e0 15 * J2 pin 1 (GND) -> bq76PL455A-Q1 EVM J3 pin 1 (DGND)
renemagrit 2:234a2c91b0e0 16 * J2 pin 3 (GIOA0) -> bq76PL455A-Q1 EVM J3 pin 6 (nWAKE)
renemagrit 2:234a2c91b0e0 17 * J2 pin 4 (GIOA1) -> bq76PL455A-Q1 EVM J3 pin 2 (nFAULT)
renemagrit 2:234a2c91b0e0 18 *
renemagrit 2:234a2c91b0e0 19 *
renemagrit 2:234a2c91b0e0 20 * @author Stephen Holland - Texas Instruments, Inc
renemagrit 2:234a2c91b0e0 21 * @date June 2015
renemagrit 2:234a2c91b0e0 22 * @version 1.0 Initial version
renemagrit 2:234a2c91b0e0 23 * @note Built with CCS for Hercules Version: 5.5.0
renemagrit 2:234a2c91b0e0 24 */
renemagrit 2:234a2c91b0e0 25
renemagrit 2:234a2c91b0e0 26 /*****************************************************************************
renemagrit 2:234a2c91b0e0 27 **
renemagrit 2:234a2c91b0e0 28 ** Copyright (c) 2011-2015 Texas Instruments
renemagrit 2:234a2c91b0e0 29 **
renemagrit 2:234a2c91b0e0 30 ******************************************************************************/
renemagrit 2:234a2c91b0e0 31
renemagrit 2:234a2c91b0e0 32
renemagrit 2:234a2c91b0e0 33 /* USER CODE BEGIN (0) */
renemagrit 2:234a2c91b0e0 34 /* USER CODE END */
renemagrit 2:234a2c91b0e0 35
renemagrit 2:234a2c91b0e0 36 /* Include Files */
renemagrit 2:234a2c91b0e0 37
renemagrit 2:234a2c91b0e0 38 #include "sys_common.h"
renemagrit 2:234a2c91b0e0 39 #include "system.h"
renemagrit 2:234a2c91b0e0 40
renemagrit 2:234a2c91b0e0 41 /* USER CODE BEGIN (1) */
renemagrit 2:234a2c91b0e0 42 #include "gio.h"
renemagrit 2:234a2c91b0e0 43 #include "sci.h"
renemagrit 2:234a2c91b0e0 44 #include "rti.h"
renemagrit 2:234a2c91b0e0 45 #include "sys_vim.h"
renemagrit 2:234a2c91b0e0 46 #include "swi_util.h"
renemagrit 2:234a2c91b0e0 47
renemagrit 2:234a2c91b0e0 48 #include "pl455.h"
renemagrit 2:234a2c91b0e0 49
renemagrit 2:234a2c91b0e0 50 //***************************************************************************
renemagrit 2:234a2c91b0e0 51 // Fja _enable_IRQ() nema telo ni u jednom od .h fjalova pa je zakomenatrisana
renemagrit 2:234a2c91b0e0 52 // Takodje ove dve promenljive int UART_RX_RDY = 0;int RTI_TIMEOUT = 0; su deklarisane na jos jednom mestuu i to je isto bila greska
renemagrit 2:234a2c91b0e0 53
renemagrit 2:234a2c91b0e0 54 //***************************************************************************
renemagrit 2:234a2c91b0e0 55 //int UART_RX_RDY = 0;
renemagrit 2:234a2c91b0e0 56 //int RTI_TIMEOUT = 0;
renemagrit 2:234a2c91b0e0 57
renemagrit 2:234a2c91b0e0 58 /* USER CODE END */
renemagrit 2:234a2c91b0e0 59
renemagrit 2:234a2c91b0e0 60 /** @fn void main(void)
renemagrit 2:234a2c91b0e0 61 * @brief Application main function
renemagrit 2:234a2c91b0e0 62 * @note This function is empty by default.
renemagrit 2:234a2c91b0e0 63 *
renemagrit 2:234a2c91b0e0 64 * This function is called after startup.
renemagrit 2:234a2c91b0e0 65 * The user can use this function to implement the application.
renemagrit 2:234a2c91b0e0 66 */
renemagrit 2:234a2c91b0e0 67
renemagrit 2:234a2c91b0e0 68 /* USER CODE BEGIN (2) */
renemagrit 2:234a2c91b0e0 69 /* USER CODE END */
renemagrit 2:234a2c91b0e0 70
renemagrit 2:234a2c91b0e0 71 void main(void)
renemagrit 2:234a2c91b0e0 72 {
renemagrit 2:234a2c91b0e0 73 /* USER CODE BEGIN (3) */
renemagrit 2:234a2c91b0e0 74 systemInit();
renemagrit 2:234a2c91b0e0 75 gioInit();
renemagrit 2:234a2c91b0e0 76 sciInit();
renemagrit 2:234a2c91b0e0 77 sciSetBaudrate(scilinREG, BAUDRATE);
renemagrit 2:234a2c91b0e0 78 rtiInit();
renemagrit 2:234a2c91b0e0 79 vimInit();
renemagrit 2:234a2c91b0e0 80
renemagrit 2:234a2c91b0e0 81 //_enable_IRQ();
renemagrit 0:b3d31a017887 82
renemagrit 2:234a2c91b0e0 83 WakePL455();
renemagrit 2:234a2c91b0e0 84
renemagrit 2:234a2c91b0e0 85 CommClear();
renemagrit 2:234a2c91b0e0 86
renemagrit 2:234a2c91b0e0 87 CommReset();
renemagrit 2:234a2c91b0e0 88
renemagrit 2:234a2c91b0e0 89 // initialize local variables
renemagrit 2:234a2c91b0e0 90 int nSent, nRead, nTopFound = 0;
renemagrit 2:234a2c91b0e0 91 int nDev_ID, nGrp_ID;
renemagrit 2:234a2c91b0e0 92 BYTE bFrame[132];
renemagrit 2:234a2c91b0e0 93 uint32 wTemp = 0;
renemagrit 2:234a2c91b0e0 94
renemagrit 2:234a2c91b0e0 95 /** Code examples
renemagrit 2:234a2c91b0e0 96 * The command sequences below are examples of the message examples in the bq76PL455 Communication Examples document.
renemagrit 2:234a2c91b0e0 97 * each message example references the section in the document.
renemagrit 2:234a2c91b0e0 98 */
renemagrit 2:234a2c91b0e0 99
renemagrit 2:234a2c91b0e0 100 // Wake all devices
renemagrit 2:234a2c91b0e0 101 // The wake tone will awaken any device that is already in shutdown and the pwrdown will shutdown any device
renemagrit 2:234a2c91b0e0 102 // that is already awake. The least number of times to sequence wake and pwrdown will be half the number of
renemagrit 2:234a2c91b0e0 103 // boards to cover the worst case combination of boards already awake or shutdown.
renemagrit 2:234a2c91b0e0 104 for(nDev_ID = 0; nDev_ID < TOTALBOARDS>>1; nDev_ID++) {
renemagrit 2:234a2c91b0e0 105 nSent = WriteReg(nDev_ID, 12, 0x40, 1, FRMWRT_ALL_NR); // send out broadcast pwrdown command
renemagrit 2:234a2c91b0e0 106 delayms(5); //~5ms
renemagrit 2:234a2c91b0e0 107 WakePL455();
renemagrit 2:234a2c91b0e0 108 delayms(5); //~5ms
renemagrit 2:234a2c91b0e0 109 }
renemagrit 2:234a2c91b0e0 110
renemagrit 2:234a2c91b0e0 111 // Mask Customer Checksum Fault bit
renemagrit 2:234a2c91b0e0 112 nSent = WriteReg(0, 107, 0x8000, 2, FRMWRT_ALL_NR); // clear all fault summary flags
renemagrit 2:234a2c91b0e0 113
renemagrit 2:234a2c91b0e0 114 // Clear all faults
renemagrit 2:234a2c91b0e0 115 nSent = WriteReg(0, 82, 0xFFC0, 2, FRMWRT_ALL_NR); // clear all fault summary flags
renemagrit 2:234a2c91b0e0 116 nSent = WriteReg(0, 81, 0x38, 1, FRMWRT_ALL_NR); // clear fault flags in the system status register
renemagrit 2:234a2c91b0e0 117
renemagrit 2:234a2c91b0e0 118 // Auto-address all boards (section 1.2.2)
renemagrit 2:234a2c91b0e0 119 nSent = WriteReg(0, 14, 0x19, 1, FRMWRT_ALL_NR); // set auto-address mode on all boards
renemagrit 2:234a2c91b0e0 120 nSent = WriteReg(0, 12, 0x08, 1, FRMWRT_ALL_NR); // enter auto address mode on all boards, the next write to this ID will be its address
renemagrit 2:234a2c91b0e0 121
renemagrit 2:234a2c91b0e0 122 // Set addresses for all boards in daisy-chain (section 1.2.3)
renemagrit 2:234a2c91b0e0 123 for (nDev_ID = 0; nDev_ID < TOTALBOARDS; nDev_ID++)
renemagrit 2:234a2c91b0e0 124 {
renemagrit 2:234a2c91b0e0 125 nSent = WriteReg(nDev_ID, 10, nDev_ID, 1, FRMWRT_ALL_NR); // send address to each board
renemagrit 2:234a2c91b0e0 126 }
renemagrit 2:234a2c91b0e0 127
renemagrit 2:234a2c91b0e0 128 // Enable all communication interfaces on all boards in the stack (section 1.2.1)
renemagrit 2:234a2c91b0e0 129 nSent = WriteReg(0, 16, 0x10F8, 2, FRMWRT_ALL_NR); // set communications baud rate and enable all interfaces on all boards in stack
renemagrit 2:234a2c91b0e0 130
renemagrit 2:234a2c91b0e0 131 /* Change to final baud rate used in the application (set by BAUDRATE define in pl455.h).
renemagrit 2:234a2c91b0e0 132 * Up to this point, all communication is at 250Kb, as the COMM_RESET done at the initial
renemagrit 2:234a2c91b0e0 133 * startup resets the bq76PL455A-Q1 UART to 250Kb. */
renemagrit 2:234a2c91b0e0 134 switch(BAUDRATE)
renemagrit 2:234a2c91b0e0 135 {
renemagrit 2:234a2c91b0e0 136 case 125000:
renemagrit 2:234a2c91b0e0 137 nSent = WriteReg(0, 16, 0x00F8, 2, FRMWRT_ALL_NR); // set communications baud rate and enable all interfaces
renemagrit 2:234a2c91b0e0 138 delayms(1);
renemagrit 2:234a2c91b0e0 139 sciSetBaudrate(scilinREG, BAUDRATE);
renemagrit 2:234a2c91b0e0 140 break;
renemagrit 2:234a2c91b0e0 141 case 250000:
renemagrit 2:234a2c91b0e0 142 delayms(1);
renemagrit 2:234a2c91b0e0 143 break;
renemagrit 2:234a2c91b0e0 144 case 500000:
renemagrit 2:234a2c91b0e0 145 nSent = WriteReg(0, 16, 0x20F8, 2, FRMWRT_ALL_NR); // set communications baud rate and enable all interfaces
renemagrit 2:234a2c91b0e0 146 delayms(1);
renemagrit 2:234a2c91b0e0 147 sciSetBaudrate(scilinREG, BAUDRATE);
renemagrit 2:234a2c91b0e0 148 break;
renemagrit 2:234a2c91b0e0 149 case 1000000:
renemagrit 2:234a2c91b0e0 150 nSent = WriteReg(0, 16, 0x30F8, 2, FRMWRT_ALL_NR); // set communications baud rate and enable all interfaces
renemagrit 2:234a2c91b0e0 151 delayms(1);
renemagrit 2:234a2c91b0e0 152 sciSetBaudrate(scilinREG, BAUDRATE);
renemagrit 2:234a2c91b0e0 153 break;
renemagrit 2:234a2c91b0e0 154 }
renemagrit 2:234a2c91b0e0 155
renemagrit 2:234a2c91b0e0 156 /* Set communications interfaces appropriately for their position in the stack, and
renemagrit 2:234a2c91b0e0 157 * for baud rate used in the application (set by BAUDRATE define in pl455.h).
renemagrit 2:234a2c91b0e0 158 * (section 1.2.4)
renemagrit 2:234a2c91b0e0 159 */
renemagrit 2:234a2c91b0e0 160 for (nDev_ID = TOTALBOARDS - 1; nDev_ID >= 0; --nDev_ID)
renemagrit 2:234a2c91b0e0 161 {
renemagrit 2:234a2c91b0e0 162 // read device ID to see if there is a response
renemagrit 2:234a2c91b0e0 163 nRead = ReadReg(nDev_ID, 10, &wTemp, 1, 0); // 0ms timeout
renemagrit 0:b3d31a017887 164
renemagrit 2:234a2c91b0e0 165 if(nRead == 0) // if nothing is read then this board doesn't exist
renemagrit 2:234a2c91b0e0 166 nTopFound = 0;
renemagrit 2:234a2c91b0e0 167 else // a response was received
renemagrit 2:234a2c91b0e0 168 {
renemagrit 2:234a2c91b0e0 169 if(nTopFound == 0)
renemagrit 2:234a2c91b0e0 170 { // if the last board was not present but this one is, this is the top board
renemagrit 2:234a2c91b0e0 171 if(nDev_ID == 0) // this is the only board
renemagrit 2:234a2c91b0e0 172 {
renemagrit 2:234a2c91b0e0 173 switch(BAUDRATE)
renemagrit 2:234a2c91b0e0 174 {
renemagrit 2:234a2c91b0e0 175 case 125000:
renemagrit 2:234a2c91b0e0 176 nSent = WriteReg(nDev_ID, 16, 0x0080, 2, FRMWRT_SGL_NR); // enable only single-end comm port on board
renemagrit 2:234a2c91b0e0 177 break;
renemagrit 2:234a2c91b0e0 178 case 250000:
renemagrit 2:234a2c91b0e0 179 nSent = WriteReg(nDev_ID, 16, 0x1080, 2, FRMWRT_SGL_NR); // enable only single-end comm port on board
renemagrit 2:234a2c91b0e0 180 break;
renemagrit 2:234a2c91b0e0 181 case 500000:
renemagrit 2:234a2c91b0e0 182 nSent = WriteReg(nDev_ID, 16, 0x2080, 2, FRMWRT_SGL_NR); // enable only single-end comm port on board
renemagrit 2:234a2c91b0e0 183 break;
renemagrit 2:234a2c91b0e0 184 case 1000000:
renemagrit 2:234a2c91b0e0 185 nSent = WriteReg(nDev_ID, 16, 0x3080, 2, FRMWRT_SGL_NR); // enable only single-end comm port on board
renemagrit 2:234a2c91b0e0 186 break;
renemagrit 2:234a2c91b0e0 187 }
renemagrit 2:234a2c91b0e0 188 }
renemagrit 2:234a2c91b0e0 189 else // this is the top board of a stack (section 1.2.5)
renemagrit 2:234a2c91b0e0 190 {
renemagrit 2:234a2c91b0e0 191 switch(BAUDRATE)
renemagrit 2:234a2c91b0e0 192 {
renemagrit 2:234a2c91b0e0 193 case 125000:
renemagrit 2:234a2c91b0e0 194 nSent = WriteReg(nDev_ID, 16, 0x0028, 2, FRMWRT_SGL_NR); // enable only comm-low and fault-low for the top board
renemagrit 2:234a2c91b0e0 195 break;
renemagrit 2:234a2c91b0e0 196 case 250000:
renemagrit 2:234a2c91b0e0 197 nSent = WriteReg(nDev_ID, 16, 0x1028, 2, FRMWRT_SGL_NR); // enable only comm-low and fault-low for the top board
renemagrit 2:234a2c91b0e0 198 break;
renemagrit 2:234a2c91b0e0 199 case 500000:
renemagrit 2:234a2c91b0e0 200 nSent = WriteReg(nDev_ID, 16, 0x2028, 2, FRMWRT_SGL_NR); // enable only comm-low and fault-low for the top board
renemagrit 2:234a2c91b0e0 201 break;
renemagrit 2:234a2c91b0e0 202 case 1000000:
renemagrit 2:234a2c91b0e0 203 nSent = WriteReg(nDev_ID, 16, 0x3028, 2, FRMWRT_SGL_NR); // enable only comm-low and fault-low for the top board
renemagrit 2:234a2c91b0e0 204 break;
renemagrit 2:234a2c91b0e0 205 }
renemagrit 2:234a2c91b0e0 206 nTopFound = 1;
renemagrit 2:234a2c91b0e0 207 }
renemagrit 2:234a2c91b0e0 208 }
renemagrit 2:234a2c91b0e0 209 else // this is a middle or bottom board
renemagrit 2:234a2c91b0e0 210 {
renemagrit 2:234a2c91b0e0 211 if(nDev_ID == 0) // this is a bottom board of a stack (section 1.2.6)
renemagrit 2:234a2c91b0e0 212 {
renemagrit 2:234a2c91b0e0 213 switch(BAUDRATE)
renemagrit 2:234a2c91b0e0 214 {
renemagrit 2:234a2c91b0e0 215 case 125000:
renemagrit 2:234a2c91b0e0 216 nSent = WriteReg(nDev_ID, 16, 0x00D0, 2, FRMWRT_SGL_NR); // enable comm-high, fault-high and single-end comm port on bottom board
renemagrit 2:234a2c91b0e0 217 break;
renemagrit 2:234a2c91b0e0 218 case 250000:
renemagrit 2:234a2c91b0e0 219 nSent = WriteReg(nDev_ID, 16, 0x10D0, 2, FRMWRT_SGL_NR); // enable comm-high, fault-high and single-end comm port on bottom board
renemagrit 2:234a2c91b0e0 220 break;
renemagrit 2:234a2c91b0e0 221 case 500000:
renemagrit 2:234a2c91b0e0 222 nSent = WriteReg(nDev_ID, 16, 0x20D0, 2, FRMWRT_SGL_NR); // enable comm-high, fault-high and single-end comm port on bottom board
renemagrit 2:234a2c91b0e0 223 break;
renemagrit 2:234a2c91b0e0 224 case 1000000:
renemagrit 2:234a2c91b0e0 225 nSent = WriteReg(nDev_ID, 16, 0x30D0, 2, FRMWRT_SGL_NR); // enable comm-high, fault-high and single-end comm port on bottom board
renemagrit 2:234a2c91b0e0 226 break;
renemagrit 2:234a2c91b0e0 227 }
renemagrit 2:234a2c91b0e0 228 }
renemagrit 2:234a2c91b0e0 229 else // this is a middle board
renemagrit 2:234a2c91b0e0 230 {
renemagrit 2:234a2c91b0e0 231 switch(BAUDRATE)
renemagrit 2:234a2c91b0e0 232 {
renemagrit 2:234a2c91b0e0 233 case 125000:
renemagrit 2:234a2c91b0e0 234 nSent = WriteReg(nDev_ID, 16, 0x0078, 2, FRMWRT_SGL_NR); // enable comm-high, fault-high, comm-low and fault-low on all middle boards
renemagrit 2:234a2c91b0e0 235 break;
renemagrit 2:234a2c91b0e0 236 case 250000:
renemagrit 2:234a2c91b0e0 237 nSent = WriteReg(nDev_ID, 16, 0x1078, 2, FRMWRT_SGL_NR); // enable comm-high, fault-high, comm-low and fault-low on all middle boards
renemagrit 2:234a2c91b0e0 238 break;
renemagrit 2:234a2c91b0e0 239 case 500000:
renemagrit 2:234a2c91b0e0 240 nSent = WriteReg(nDev_ID, 16, 0x2078, 2, FRMWRT_SGL_NR); // enable comm-high, fault-high, comm-low and fault-low on all middle boards
renemagrit 2:234a2c91b0e0 241 break;
renemagrit 2:234a2c91b0e0 242 case 1000000:
renemagrit 2:234a2c91b0e0 243 nSent = WriteReg(nDev_ID, 16, 0x3078, 2, FRMWRT_SGL_NR); // enable comm-high, fault-high, comm-low and fault-low on all middle boards
renemagrit 2:234a2c91b0e0 244 break;
renemagrit 2:234a2c91b0e0 245 }
renemagrit 2:234a2c91b0e0 246 }
renemagrit 2:234a2c91b0e0 247 }
renemagrit 2:234a2c91b0e0 248 }
renemagrit 0:b3d31a017887 249 }
renemagrit 2:234a2c91b0e0 250
renemagrit 2:234a2c91b0e0 251 // Clear all faults (section 1.2.7)
renemagrit 2:234a2c91b0e0 252 nSent = WriteReg(0, 82, 0xFFC0, 2, FRMWRT_ALL_NR); // clear all fault summary flags
renemagrit 2:234a2c91b0e0 253 nSent = WriteReg(0, 81, 0x38, 1, FRMWRT_ALL_NR); // clear fault flags in the system status register
renemagrit 2:234a2c91b0e0 254
renemagrit 2:234a2c91b0e0 255 delayms(10);
renemagrit 2:234a2c91b0e0 256
renemagrit 2:234a2c91b0e0 257 // Configure AFE (section 2.2.1)
renemagrit 2:234a2c91b0e0 258
renemagrit 2:234a2c91b0e0 259 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 260 nSent = WriteReg(nDev_ID, 60, 0x00, 1, FRMWRT_SGL_NR); // set 0 mux delay
renemagrit 2:234a2c91b0e0 261 nSent = WriteReg(nDev_ID, 61, 0x00, 1, FRMWRT_SGL_NR); // set 0 initial delay
renemagrit 2:234a2c91b0e0 262
renemagrit 2:234a2c91b0e0 263 // Configure voltage and internal sample period (section 2.2.2)
renemagrit 2:234a2c91b0e0 264 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 265 nSent = WriteReg(nDev_ID, 62, 0xCC, 1, FRMWRT_SGL_NR); // set 99.92us ADC sampling period
renemagrit 2:234a2c91b0e0 266
renemagrit 2:234a2c91b0e0 267 // Configure the oversampling rate (section 2.2.3)
renemagrit 2:234a2c91b0e0 268 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 269 nSent = WriteReg(nDev_ID, 7, 0x00, 1, FRMWRT_SGL_NR); // set no oversampling period
renemagrit 2:234a2c91b0e0 270
renemagrit 2:234a2c91b0e0 271 // Clear and check faults (section 2.2.4)
renemagrit 2:234a2c91b0e0 272 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 273 nSent = WriteReg(nDev_ID, 81, 0x38, 1, FRMWRT_SGL_NR); // clear fault flags in the system status register
renemagrit 2:234a2c91b0e0 274 nSent = WriteReg(nDev_ID, 82, 0xFFC0, 2, FRMWRT_SGL_NR); // clear all fault summary flags
renemagrit 2:234a2c91b0e0 275 nRead = ReadReg(nDev_ID, 81, &wTemp, 1, 0); // 0ms timeout
renemagrit 2:234a2c91b0e0 276 nRead = ReadReg(nDev_ID, 82, &wTemp, 2, 0); // 0ms timeout
renemagrit 2:234a2c91b0e0 277
renemagrit 2:234a2c91b0e0 278 // Select number of cells and channels to sample (section 2.2.5.1)
renemagrit 2:234a2c91b0e0 279 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 280 nSent = WriteReg(nDev_ID, 13, 0x10, 1, FRMWRT_SGL_NR); // set number of cells to 16
renemagrit 2:234a2c91b0e0 281 nSent = WriteReg(nDev_ID, 3, 0xFFFF03C0, 4, FRMWRT_SGL_NR); // select all cell, AUX channels 0 and 1, and internal digital die and internal analog die temperatures
renemagrit 2:234a2c91b0e0 282
renemagrit 2:234a2c91b0e0 283 // Select identical number of cells and channels on all modules simultaneously (section 2.2.5.2)
renemagrit 2:234a2c91b0e0 284 nSent = WriteReg(0, 13, 0x10, 1, FRMWRT_ALL_NR); // set number of cells to 16
renemagrit 2:234a2c91b0e0 285 nSent = WriteReg(0, 3, 0xFFFF03C0, 4, FRMWRT_ALL_NR); // select all cell, AUX channels 0 and 1, and internal digital die and internal analog die temperatures
renemagrit 2:234a2c91b0e0 286 nSent = WriteReg(0, 13, 0x08, 1, FRMWRT_ALL_NR); // set number of cells to 8
renemagrit 2:234a2c91b0e0 287 nSent = WriteReg(0, 3, 0x00FF03C0, 4, FRMWRT_ALL_NR); // select all cell channels 1-8, AUX channels 0 and 1, and internal digital die and internal analog die temperatures
renemagrit 2:234a2c91b0e0 288
renemagrit 2:234a2c91b0e0 289 // Set cell over-voltage and cell under-voltage thresholds on a single board (section 2.2.6.1)
renemagrit 2:234a2c91b0e0 290 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 291 nSent = WriteReg(nDev_ID, 144, 0xD1EC, 2, FRMWRT_SGL_NR); // set OV threshold = 4.1000V
renemagrit 2:234a2c91b0e0 292 nSent = WriteReg(nDev_ID, 142, 0x6148, 2, FRMWRT_SGL_NR); // set UV threshold = 1.9000V
renemagrit 2:234a2c91b0e0 293
renemagrit 2:234a2c91b0e0 294 // Set cell over-voltage and cell under-voltage thresholds on all boards simultaneously (section 2.2.6.2)
renemagrit 2:234a2c91b0e0 295 nSent = WriteReg(0, 144, 0xD1EC, 2, FRMWRT_ALL_NR); // set OV threshold = 4.1000V
renemagrit 2:234a2c91b0e0 296 nSent = WriteReg(0, 142, 0x6148, 2, FRMWRT_ALL_NR); // set UV threshold = 1.9000V
renemagrit 2:234a2c91b0e0 297
renemagrit 2:234a2c91b0e0 298 // Send broadcast request to all boards to sample and send results (section 3.2)
renemagrit 2:234a2c91b0e0 299 nSent = WriteReg(0, 2, 0x02, 1, FRMWRT_ALL_NR); // send sync sample command
renemagrit 2:234a2c91b0e0 300 nSent = WaitRespFrame(bFrame, 81, 0); // 24 bytes data (x3) + packet header (x3) + CRC (x3), 0ms timeout
renemagrit 2:234a2c91b0e0 301
renemagrit 2:234a2c91b0e0 302 // Send broadcast request to all boards to sample and store results (section 3.3.1)
renemagrit 2:234a2c91b0e0 303 nSent = WriteReg(0, 2, 0x00, 1, FRMWRT_ALL_NR); // send sync sample command
renemagrit 2:234a2c91b0e0 304
renemagrit 2:234a2c91b0e0 305 // Read sampled data from boards (section 3.3.2)
renemagrit 2:234a2c91b0e0 306 // 24 bytes - still configured for 8 AFE channels plus 2 AUX channels plus internal digital and analog die
renemagrit 2:234a2c91b0e0 307 // temperatures (see code for section 2.2.5.2)
renemagrit 2:234a2c91b0e0 308 nDev_ID = 2;
renemagrit 2:234a2c91b0e0 309 nSent = WriteReg(nDev_ID, 2, 0x20, 1, FRMWRT_SGL_R); // send read sampled values command
renemagrit 2:234a2c91b0e0 310 nSent = WaitRespFrame(bFrame, 27, 0); // 24 bytes data + packet header + CRC, 0ms timeout
renemagrit 2:234a2c91b0e0 311 nDev_ID = 1;
renemagrit 2:234a2c91b0e0 312 nSent = WriteReg(nDev_ID, 2, 0x20, 1, FRMWRT_SGL_R); // send read sampled values command
renemagrit 2:234a2c91b0e0 313 nSent = WaitRespFrame(bFrame, 27, 0); // 24 bytes data + packet header + CRC, 0ms timeout
renemagrit 2:234a2c91b0e0 314 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 315 nSent = WriteReg(nDev_ID, 2, 0x20, 1, FRMWRT_SGL_R); // send read sampled values command
renemagrit 2:234a2c91b0e0 316 nSent = WaitRespFrame(bFrame, 27, 0); // 24 bytes data + packet header + CRC, 0ms timeout
renemagrit 2:234a2c91b0e0 317
renemagrit 2:234a2c91b0e0 318 // Send sample request to single board to sample and send results (section 4.2)
renemagrit 2:234a2c91b0e0 319 nDev_ID = 1;
renemagrit 2:234a2c91b0e0 320 nSent = WriteReg(nDev_ID, 2, 0x01, 1, FRMWRT_SGL_NR); // send sync sample command
renemagrit 2:234a2c91b0e0 321 nSent = WaitRespFrame(bFrame, 27, 0); // 24 bytes data + packet header + CRC, 0ms timeout
renemagrit 2:234a2c91b0e0 322
renemagrit 2:234a2c91b0e0 323 // Send sample request with embedded channel and oversample information (section 4.3.1)
renemagrit 2:234a2c91b0e0 324 nDev_ID = 3;
renemagrit 2:234a2c91b0e0 325 nSent = WriteReg(nDev_ID, 2, 0x0000FF03C000, 6, FRMWRT_SGL_NR); // send sync sample command with channel
renemagrit 2:234a2c91b0e0 326 // selection and oversample selection embedded
renemagrit 2:234a2c91b0e0 327
renemagrit 2:234a2c91b0e0 328 // Read previously sampled data from single board (section 4.3.2)
renemagrit 2:234a2c91b0e0 329 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 330 nSent = WriteReg(nDev_ID, 2, 0x20, 1, FRMWRT_SGL_R); // send read sampled values command
renemagrit 2:234a2c91b0e0 331 nSent = WaitRespFrame(bFrame, 27, 0); // 24 bytes data + packet header + CRC, 0ms timeout
renemagrit 2:234a2c91b0e0 332
renemagrit 2:234a2c91b0e0 333 // Configure GPIO pin direction and set new pin values (section 5.2.1)
renemagrit 2:234a2c91b0e0 334 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 335 nSent = WriteReg(nDev_ID, 123, 0x00, 1, FRMWRT_SGL_NR); // turn off all GPIO pull downs
renemagrit 2:234a2c91b0e0 336 nSent = WriteReg(nDev_ID, 122, 0x00, 1, FRMWRT_SGL_NR); // turn off all GPIO pull ups
renemagrit 2:234a2c91b0e0 337 nSent = WriteReg(nDev_ID, 120, 0x07, 1, FRMWRT_SGL_NR); // set GPIO[2:0] to output direction
renemagrit 2:234a2c91b0e0 338 nSent = WriteReg(nDev_ID, 122, 0x07, 1, FRMWRT_SGL_NR); // turn off GPIO[5:4] pull ups and turn on GPIO[2:0] pull ups
renemagrit 2:234a2c91b0e0 339 nSent = WriteReg(nDev_ID, 121, 0x01, 1, FRMWRT_SGL_NR); // set GPIO outputs (pattern b001)
renemagrit 2:234a2c91b0e0 340 nSent = WriteReg(nDev_ID, 121, 0x02, 1, FRMWRT_SGL_NR); // set GPIO outputs (pattern b010)
renemagrit 2:234a2c91b0e0 341 nSent = WriteReg(nDev_ID, 121, 0x04, 1, FRMWRT_SGL_NR); // set GPIO outputs (pattern b100)
renemagrit 2:234a2c91b0e0 342 nSent = WriteReg(nDev_ID, 121, 0x07, 1, FRMWRT_SGL_NR); // set GPIO outputs (pattern b111)
renemagrit 2:234a2c91b0e0 343 nSent = WriteReg(nDev_ID, 121, 0x00, 1, FRMWRT_SGL_NR); // set GPIO outputs (pattern b000)
renemagrit 2:234a2c91b0e0 344
renemagrit 2:234a2c91b0e0 345 // Configure GPIO inputs with or without pull ups or pull downs (section 5.2.2)
renemagrit 2:234a2c91b0e0 346 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 347 nSent = WriteReg(nDev_ID, 123, 0x04, 1, FRMWRT_SGL_NR); // enable pull down for GPIO2, turn off all other GPIO pull downs
renemagrit 2:234a2c91b0e0 348 nSent = WriteReg(nDev_ID, 122, 0x03, 1, FRMWRT_SGL_NR); // enable pull ups for GPIO[1:0], turn off all other GPIO pull ups
renemagrit 2:234a2c91b0e0 349 nSent = WriteReg(0, 122, 0x03, 1, FRMWRT_ALL_NR); // broadcast to all boards to enable pull ups for GPIO[1:0] and turn off all other GPIO pull ups
renemagrit 2:234a2c91b0e0 350
renemagrit 2:234a2c91b0e0 351 // Setting a GPIO output value (section 5.2.3.1)
renemagrit 2:234a2c91b0e0 352 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 353 nSent = WriteReg(nDev_ID, 120, 0x17, 1, FRMWRT_SGL_NR); // set GPIO direction for GPIO4 and GPIO[2:0] as outputs, GPIO3 and GPIO5 as inputs
renemagrit 2:234a2c91b0e0 354 nSent = WriteReg(nDev_ID, 121, 0x12, 1, FRMWRT_SGL_NR); // set GPIO4 and GPIO1, clear GPIO2 and GPIO0
renemagrit 2:234a2c91b0e0 355
renemagrit 2:234a2c91b0e0 356 // Reading a GPIO input value (section 5.2.3.2)
renemagrit 2:234a2c91b0e0 357 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 358 nSent = WriteReg(nDev_ID, 120, 0x30, 1, FRMWRT_SGL_NR); // set GPIO direction for GPIO[5:4] as outputs, GPIO[3:0] as inputs
renemagrit 2:234a2c91b0e0 359 nRead = ReadReg(nDev_ID, 124, &wTemp, 1, 0); // read GPIO inputs, 0ms timeout
renemagrit 2:234a2c91b0e0 360
renemagrit 2:234a2c91b0e0 361 // Steps for saving register configuration to EEPROM (sections 6.2.1 to 6.2.4)
renemagrit 2:234a2c91b0e0 362 // ** the code is commented out below to avoid accidental use - uncomment to use
renemagrit 2:234a2c91b0e0 363 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 364 //nSent = WriteReg(nDev_ID, 130, 0x8C2DB194, 4, FRMWRT_SGL_NR); // write Magic Number 1
renemagrit 2:234a2c91b0e0 365 //nSent = WriteReg(nDev_ID, 252, 0xA375E60F, 4, FRMWRT_SGL_NR); // write Magic Number 2
renemagrit 2:234a2c91b0e0 366 //nSent = WriteReg(nDev_ID, 12, 0x10, 1, FRMWRT_SGL_NR); // send Write RAM to EEPROM command
renemagrit 2:234a2c91b0e0 367 nRead = ReadReg(nDev_ID, 12, &wTemp, 1, 0); // read WRITE_EEPROM status bit, 0ms timeout
renemagrit 2:234a2c91b0e0 368 //test WRITE_EEPROM bit to check for completion
renemagrit 2:234a2c91b0e0 369
renemagrit 2:234a2c91b0e0 370 // Steps for saving register configuration to EEPROM in all devices in stack (sections 6.2.5)
renemagrit 2:234a2c91b0e0 371 // ** the code is commented out below to avoid accidental use - uncomment to use
renemagrit 2:234a2c91b0e0 372 //nSent = WriteReg(0, 130, 0x8C2DB194, 4, FRMWRT_ALL_NR); // write Magic Number 1
renemagrit 2:234a2c91b0e0 373 //nSent = WriteReg(0, 252, 0xA375E60F, 4, FRMWRT_ALL_NR); // write Magic Number 2
renemagrit 2:234a2c91b0e0 374 //nSent = WriteReg(0, 12, 0x10, 1, FRMWRT_ALL_NR); // send Write RAM to EEPROM command
renemagrit 2:234a2c91b0e0 375 nDev_ID = 0;
renemagrit 2:234a2c91b0e0 376 nRead = ReadReg(nDev_ID, 12, &wTemp, 1, 0); // read WRITE_EEPROM status bit, 0ms timeout
renemagrit 2:234a2c91b0e0 377 //test WRITE_EEPROM bit to check for completion
renemagrit 2:234a2c91b0e0 378 nDev_ID = 1;
renemagrit 2:234a2c91b0e0 379 nRead = ReadReg(nDev_ID, 12, &wTemp, 1, 0); // read WRITE_EEPROM status bit, 0ms timeout
renemagrit 2:234a2c91b0e0 380 //test WRITE_EEPROM bit to check for completion
renemagrit 2:234a2c91b0e0 381 nDev_ID = 2;
renemagrit 2:234a2c91b0e0 382 nRead = ReadReg(nDev_ID, 12, &wTemp, 1, 0); // read WRITE_EEPROM status bit, 0ms timeout
renemagrit 2:234a2c91b0e0 383 //test WRITE_EEPROM bit to check for completion
renemagrit 2:234a2c91b0e0 384
renemagrit 2:234a2c91b0e0 385 // Assign devices to specific group IDs (section 7)
renemagrit 2:234a2c91b0e0 386 nDev_ID = 1;
renemagrit 2:234a2c91b0e0 387 nSent = WriteReg(nDev_ID, 11, 0x01, 1, FRMWRT_SGL_NR); // assign Dev ID 1 to Group ID 1
renemagrit 2:234a2c91b0e0 388 nDev_ID = 2;
renemagrit 2:234a2c91b0e0 389 nSent = WriteReg(nDev_ID, 11, 0x01, 1, FRMWRT_SGL_NR); // assign Dev ID 1 to Group ID 1
renemagrit 2:234a2c91b0e0 390
renemagrit 2:234a2c91b0e0 391 delayms(1);
renemagrit 2:234a2c91b0e0 392 nRead = ReadReg(1, 11, &wTemp, 1, 0); // read group ID register, 0ms timeout
renemagrit 2:234a2c91b0e0 393 nRead = ReadReg(2, 11, &wTemp, 1, 0); // read group ID register, 0ms timeout
renemagrit 2:234a2c91b0e0 394
renemagrit 2:234a2c91b0e0 395 // Send group sample request with embedded channel and oversample information (section 7.1)
renemagrit 2:234a2c91b0e0 396 // send sync sample command (first data byte = command (b[7:5] = 0) | highest device to respond (0x01)) with
renemagrit 2:234a2c91b0e0 397 // channel selection and oversample selection embedded
renemagrit 2:234a2c91b0e0 398 nGrp_ID = 1;
renemagrit 2:234a2c91b0e0 399 nSent = WriteReg(nGrp_ID, 2, 0x02FFFF550000, 6, FRMWRT_GRP_R);
renemagrit 2:234a2c91b0e0 400 nSent = WaitRespFrame(bFrame, 86, 0); // 40 bytes data (x2) + packet header (x2) + CRC (x2), 0ms timeout
renemagrit 2:234a2c91b0e0 401
renemagrit 2:234a2c91b0e0 402 // Send group sample request - 1 byte method (section 7.2)
renemagrit 2:234a2c91b0e0 403 // send sync sample command with channel (data byte = command (b[7:5] = 0) | highest device to respond (0x01))
renemagrit 2:234a2c91b0e0 404 // sampling parameters are taken from values already stored in Command Channel Select and Oversampling registers
renemagrit 2:234a2c91b0e0 405 nGrp_ID = 1;
renemagrit 2:234a2c91b0e0 406 nSent = WriteReg(nGrp_ID, 2, 0x02, 1, FRMWRT_GRP_R);
renemagrit 2:234a2c91b0e0 407 nSent = WaitRespFrame(bFrame, 86, 0); // 40 bytes data (x2) + packet header (x2) + CRC (x2), 0ms timeout
renemagrit 2:234a2c91b0e0 408
renemagrit 2:234a2c91b0e0 409 // Send group register read - 2 byte method (section 7.3)
renemagrit 2:234a2c91b0e0 410 // read Command Channel Select register (first data byte = highest device to respond (0x01), second data byte
renemagrit 2:234a2c91b0e0 411 // = number of data bytes - 1 (4 bytes = 0x03))
renemagrit 2:234a2c91b0e0 412 // sampling parameters are taken from values already stored in Command Channel Select and Oversampling registers
renemagrit 2:234a2c91b0e0 413 nGrp_ID = 1;
renemagrit 2:234a2c91b0e0 414 nSent = WriteReg(nGrp_ID, 3, 0x0203, 2, FRMWRT_GRP_R);
renemagrit 2:234a2c91b0e0 415 nSent = WaitRespFrame(bFrame, 14, 0); // 4 bytes data (x2) + packet header (x2) + CRC (x2), 0ms timeout
renemagrit 2:234a2c91b0e0 416
renemagrit 2:234a2c91b0e0 417 // Send group register read - 1 byte method (section 7.4)
renemagrit 2:234a2c91b0e0 418 // read Command Channel Select register (data byte = number of data bytes - 1 (4 bytes = b011) | highest device
renemagrit 2:234a2c91b0e0 419 // to respond (0x01))
renemagrit 2:234a2c91b0e0 420 // sampling parameters are taken from values already stored in Command Channel Select and Oversampling registers
renemagrit 2:234a2c91b0e0 421 nGrp_ID = 1;
renemagrit 2:234a2c91b0e0 422 nSent = WriteReg(nGrp_ID, 3, 0x62, 1, FRMWRT_GRP_R);
renemagrit 2:234a2c91b0e0 423 nSent = WaitRespFrame(bFrame, 14, 0); // 4 bytes data (x2) + packet header (x2) + CRC (x2), 0ms timeout
renemagrit 2:234a2c91b0e0 424
renemagrit 2:234a2c91b0e0 425 // Send general broadcast register read - 2 byte method (section 8.1)
renemagrit 2:234a2c91b0e0 426 // read Command Channel Select register (first data byte = highest device to respond (0x01), second data byte
renemagrit 2:234a2c91b0e0 427 // = number of data bytes - 1 (0x03))
renemagrit 2:234a2c91b0e0 428 nSent = WriteReg(0, 3, 0x0203, 2, FRMWRT_ALL_R);
renemagrit 2:234a2c91b0e0 429 nSent = WaitRespFrame(bFrame, 14, 0); // 4 bytes data (x2) + packet header (x2) + CRC (x2), 0ms timeout
renemagrit 2:234a2c91b0e0 430
renemagrit 2:234a2c91b0e0 431 // Send general broadcast register read - 1 byte method (section 8.2)
renemagrit 2:234a2c91b0e0 432 // read Command Channel Select register (data byte = number of data bytes - 1 (4 bytes = b011) | highest device
renemagrit 2:234a2c91b0e0 433 // to respond (0x01))
renemagrit 2:234a2c91b0e0 434 nSent = WriteReg(0, 3, 0x62, 1, FRMWRT_ALL_R);
renemagrit 2:234a2c91b0e0 435 nSent = WaitRespFrame(bFrame, 14, 0); // 4 bytes data (x2) + packet header (x2) + CRC (x2), 0ms timeout
renemagrit 2:234a2c91b0e0 436
renemagrit 2:234a2c91b0e0 437
renemagrit 2:234a2c91b0e0 438 while(1);
renemagrit 2:234a2c91b0e0 439 /* USER CODE END */
renemagrit 0:b3d31a017887 440 }
renemagrit 2:234a2c91b0e0 441
renemagrit 2:234a2c91b0e0 442 /* USER CODE BEGIN (4) */
renemagrit 2:234a2c91b0e0 443 /* USER CODE END */