Diff: BurstSPI_LPC_X.cpp

Revision:

15:5809125b8dac

Parent:

9:b69faea5252c

--- a/BurstSPI_LPC_X.cpp	Sat Oct 15 16:01:12 2016 +0000
+++ b/BurstSPI_LPC_X.cpp	Sun Apr 18 21:31:53 2021 +0000
@@ -1,20 +1,27 @@
 #if defined(TARGET_LPC1768) || defined(TARGET_LPC1114) || defined(TARGET_LPC11U24) || defined(TARGET_LPC13XX)
 #include "BurstSPI.h"
+#include "LPC17xx.h"
+
+#define READABLE_BIT (1<<2)
+#define WRITABLE_BIT (1<<1)
+#define BUSY_BIT (1<<4)
 
 void BurstSPI::fastWrite(int data) {
     //Wait until FIFO has space
-    while(((_spi.spi->SR) & 0x02) == 0);
+    while(((_peripheral->spi.spi->SR) & WRITABLE_BIT) == 0);
     
     //transmit data
-    _spi.spi->DR = data;
-    }
+    _peripheral->spi.spi->DR = data;
+    while(((_peripheral->spi.spi->SR) & READABLE_BIT) == 0);
+    int dummy = _peripheral->spi.spi->DR;
+}
 
 void BurstSPI::clearRX( void ) {
     //Do it while either data in RX buffer, or while it is busy
-    while(((_spi.spi->SR) & ((1<<4) + (1<<2))) != 0) {
+    while(((_peripheral->spi.spi->SR) & (BUSY_BIT + READABLE_BIT)) != 0) {
         //Wait until data in RX buffer
-        while(((_spi.spi->SR) & (1<<2)) == 0);
-        int dummy = _spi.spi->DR;
-        }
+        while(((_peripheral->spi.spi->SR) & READABLE_BIT) == 0);
+        int dummy = _peripheral->spi.spi->DR;
+    }
 }
 #endif
\ No newline at end of file