Rene G. / BurstSPI

Just a fork with fix for newer mbed versions

BurstSPI_LPC_X.cpp@15:5809125b8dac, 2021-04-18 (annotated)

Committer:
reneg973
Date:
Sun Apr 18 21:31:53 2021 +0000
Revision:
15:5809125b8dac
Parent:
9:b69faea5252c 
fixed LPC_1768 compiler issue and transfer problems; ; Performance:; loop SPI.write() => 138.1 ms for updating a display; loop BurstSPI.fastWrite() => 22.4 ms;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 9:b69faea5252c 1 #if defined(TARGET_LPC1768) || defined(TARGET_LPC1114) || defined(TARGET_LPC11U24) || defined(TARGET_LPC13XX)
Sissors 9:b69faea5252c 2 #include "BurstSPI.h"
reneg973 15:5809125b8dac 3 #include "LPC17xx.h"
reneg973 15:5809125b8dac 4
reneg973 15:5809125b8dac 5 #define READABLE_BIT (1<<2)
reneg973 15:5809125b8dac 6 #define WRITABLE_BIT (1<<1)
reneg973 15:5809125b8dac 7 #define BUSY_BIT (1<<4)
Sissors 9:b69faea5252c 8
Sissors 9:b69faea5252c 9 void BurstSPI::fastWrite(int data) {
Sissors 9:b69faea5252c 10 //Wait until FIFO has space
reneg973 15:5809125b8dac 11 while(((_peripheral->spi.spi->SR) & WRITABLE_BIT) == 0);
Sissors 9:b69faea5252c 12
Sissors 9:b69faea5252c 13 //transmit data
reneg973 15:5809125b8dac 14 _peripheral->spi.spi->DR = data;
reneg973 15:5809125b8dac 15 while(((_peripheral->spi.spi->SR) & READABLE_BIT) == 0);
reneg973 15:5809125b8dac 16 int dummy = _peripheral->spi.spi->DR;
reneg973 15:5809125b8dac 17 }
Sissors 9:b69faea5252c 18
Sissors 9:b69faea5252c 19 void BurstSPI::clearRX( void ) {
Sissors 9:b69faea5252c 20 //Do it while either data in RX buffer, or while it is busy
reneg973 15:5809125b8dac 21 while(((_peripheral->spi.spi->SR) & (BUSY_BIT + READABLE_BIT)) != 0) {
Sissors 9:b69faea5252c 22 //Wait until data in RX buffer
reneg973 15:5809125b8dac 23 while(((_peripheral->spi.spi->SR) & READABLE_BIT) == 0);
reneg973 15:5809125b8dac 24 int dummy = _peripheral->spi.spi->DR;
reneg973 15:5809125b8dac 25 }
Sissors 9:b69faea5252c 26 }
Sissors 9:b69faea5252c 27 #endif