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easy-connect/atmel-rf-driver/source/AT86RFReg.h@0:a49e37a83a7a, 2019-04-15 (annotated)

Committer:
DuaaAbusharkh
Date:
Mon Apr 15 08:30:22 2019 +0000
Revision:
0:a49e37a83a7a
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DuaaAbusharkh 0:a49e37a83a7a 1 /*
DuaaAbusharkh 0:a49e37a83a7a 2 * Copyright (c) 2014-2015 ARM Limited. All rights reserved.
DuaaAbusharkh 0:a49e37a83a7a 3 * SPDX-License-Identifier: Apache-2.0
DuaaAbusharkh 0:a49e37a83a7a 4 * Licensed under the Apache License, Version 2.0 (the License); you may
DuaaAbusharkh 0:a49e37a83a7a 5 * not use this file except in compliance with the License.
DuaaAbusharkh 0:a49e37a83a7a 6 * You may obtain a copy of the License at
DuaaAbusharkh 0:a49e37a83a7a 7 *
DuaaAbusharkh 0:a49e37a83a7a 8 * http://www.apache.org/licenses/LICENSE-2.0
DuaaAbusharkh 0:a49e37a83a7a 9 *
DuaaAbusharkh 0:a49e37a83a7a 10 * Unless required by applicable law or agreed to in writing, software
DuaaAbusharkh 0:a49e37a83a7a 11 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
DuaaAbusharkh 0:a49e37a83a7a 12 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
DuaaAbusharkh 0:a49e37a83a7a 13 * See the License for the specific language governing permissions and
DuaaAbusharkh 0:a49e37a83a7a 14 * limitations under the License.
DuaaAbusharkh 0:a49e37a83a7a 15 */
DuaaAbusharkh 0:a49e37a83a7a 16
DuaaAbusharkh 0:a49e37a83a7a 17 #ifndef AT86RFREG_H_
DuaaAbusharkh 0:a49e37a83a7a 18 #define AT86RFREG_H_
DuaaAbusharkh 0:a49e37a83a7a 19 #ifdef __cplusplus
DuaaAbusharkh 0:a49e37a83a7a 20 extern "C" {
DuaaAbusharkh 0:a49e37a83a7a 21 #endif
DuaaAbusharkh 0:a49e37a83a7a 22
DuaaAbusharkh 0:a49e37a83a7a 23 /*AT86RF212 PHY Modes*/
DuaaAbusharkh 0:a49e37a83a7a 24 #define BPSK_20 0x00
DuaaAbusharkh 0:a49e37a83a7a 25 #define BPSK_40 0x04
DuaaAbusharkh 0:a49e37a83a7a 26 #define BPSK_40_ALT 0x14
DuaaAbusharkh 0:a49e37a83a7a 27 #define OQPSK_SIN_RC_100 0x08
DuaaAbusharkh 0:a49e37a83a7a 28 #define OQPSK_SIN_RC_200 0x09
DuaaAbusharkh 0:a49e37a83a7a 29 #define OQPSK_RC_100 0x18
DuaaAbusharkh 0:a49e37a83a7a 30 #define OQPSK_RC_200 0x19
DuaaAbusharkh 0:a49e37a83a7a 31 #define OQPSK_SIN_250 0x0c
DuaaAbusharkh 0:a49e37a83a7a 32 #define OQPSK_SIN_500 0x0d
DuaaAbusharkh 0:a49e37a83a7a 33 #define OQPSK_SIN_500_ALT 0x0f
DuaaAbusharkh 0:a49e37a83a7a 34 #define OQPSK_RC_250 0x1c
DuaaAbusharkh 0:a49e37a83a7a 35 #define OQPSK_RC_500 0x1d
DuaaAbusharkh 0:a49e37a83a7a 36 #define OQPSK_RC_500_ALT 0x1f
DuaaAbusharkh 0:a49e37a83a7a 37 #define OQPSK_SIN_RC_400_SCR_ON 0x2A
DuaaAbusharkh 0:a49e37a83a7a 38 #define OQPSK_SIN_RC_400_SCR_OFF 0x0A
DuaaAbusharkh 0:a49e37a83a7a 39 #define OQPSK_RC_400_SCR_ON 0x3A
DuaaAbusharkh 0:a49e37a83a7a 40 #define OQPSK_RC_400_SCR_OFF 0x1A
DuaaAbusharkh 0:a49e37a83a7a 41 #define OQPSK_SIN_1000_SCR_ON 0x2E
DuaaAbusharkh 0:a49e37a83a7a 42 #define OQPSK_SIN_1000_SCR_OFF 0x0E
DuaaAbusharkh 0:a49e37a83a7a 43 #define OQPSK_RC_1000_SCR_ON 0x3E
DuaaAbusharkh 0:a49e37a83a7a 44 #define OQPSK_RC_1000_SCR_OFF 0x1E
DuaaAbusharkh 0:a49e37a83a7a 45
DuaaAbusharkh 0:a49e37a83a7a 46 /*Supported transceivers*/
DuaaAbusharkh 0:a49e37a83a7a 47 #define PART_AT86RF231 0x03
DuaaAbusharkh 0:a49e37a83a7a 48 #define PART_AT86RF212 0x07
DuaaAbusharkh 0:a49e37a83a7a 49 #define PART_AT86RF233 0x0B
DuaaAbusharkh 0:a49e37a83a7a 50 #define VERSION_AT86RF212 0x01
DuaaAbusharkh 0:a49e37a83a7a 51 #define VERSION_AT86RF212B 0x03
DuaaAbusharkh 0:a49e37a83a7a 52
DuaaAbusharkh 0:a49e37a83a7a 53 /*RF Configuration Registers*/
DuaaAbusharkh 0:a49e37a83a7a 54 #define TRX_STATUS 0x01
DuaaAbusharkh 0:a49e37a83a7a 55 #define TRX_STATE 0x02
DuaaAbusharkh 0:a49e37a83a7a 56 #define TRX_CTRL_0 0x03
DuaaAbusharkh 0:a49e37a83a7a 57 #define TRX_CTRL_1 0x04
DuaaAbusharkh 0:a49e37a83a7a 58 #define PHY_TX_PWR 0x05
DuaaAbusharkh 0:a49e37a83a7a 59 #define PHY_RSSI 0x06
DuaaAbusharkh 0:a49e37a83a7a 60 #define PHY_ED_LEVEL 0x07
DuaaAbusharkh 0:a49e37a83a7a 61 #define PHY_CC_CCA 0x08
DuaaAbusharkh 0:a49e37a83a7a 62 #define RX_CTRL 0x0A
DuaaAbusharkh 0:a49e37a83a7a 63 #define SFD_VALUE 0x0B
DuaaAbusharkh 0:a49e37a83a7a 64 #define TRX_CTRL_2 0x0C
DuaaAbusharkh 0:a49e37a83a7a 65 #define ANT_DIV 0x0D
DuaaAbusharkh 0:a49e37a83a7a 66 #define IRQ_MASK 0x0E
DuaaAbusharkh 0:a49e37a83a7a 67 #define IRQ_STATUS 0x0F
DuaaAbusharkh 0:a49e37a83a7a 68 #define VREG_CTRL 0x10
DuaaAbusharkh 0:a49e37a83a7a 69 #define BATMON 0x11
DuaaAbusharkh 0:a49e37a83a7a 70 #define XOSC_CTRL 0x12
DuaaAbusharkh 0:a49e37a83a7a 71 #define CC_CTRL_0 0x13
DuaaAbusharkh 0:a49e37a83a7a 72 #define CC_CTRL_1 0x14
DuaaAbusharkh 0:a49e37a83a7a 73 #define RX_SYN 0x15
DuaaAbusharkh 0:a49e37a83a7a 74 #define TRX_RPC 0x16
DuaaAbusharkh 0:a49e37a83a7a 75 #define RF_CTRL_0 0x16
DuaaAbusharkh 0:a49e37a83a7a 76 #define XAH_CTRL_1 0x17
DuaaAbusharkh 0:a49e37a83a7a 77 #define FTN_CTRL 0x18
DuaaAbusharkh 0:a49e37a83a7a 78 #define PLL_CF 0x1A
DuaaAbusharkh 0:a49e37a83a7a 79 #define PLL_DCU 0x1B
DuaaAbusharkh 0:a49e37a83a7a 80 #define PART_NUM 0x1C
DuaaAbusharkh 0:a49e37a83a7a 81 #define VERSION_NUM 0x1D
DuaaAbusharkh 0:a49e37a83a7a 82 #define MAN_ID_0 0x1E
DuaaAbusharkh 0:a49e37a83a7a 83 #define MAN_ID_1 0x1F
DuaaAbusharkh 0:a49e37a83a7a 84 #define SHORT_ADDR_0 0x20
DuaaAbusharkh 0:a49e37a83a7a 85 #define SHORT_ADDR_1 0x21
DuaaAbusharkh 0:a49e37a83a7a 86 #define PAN_ID_0 0x22
DuaaAbusharkh 0:a49e37a83a7a 87 #define PAN_ID_1 0x23
DuaaAbusharkh 0:a49e37a83a7a 88 #define IEEE_ADDR_0 0x24
DuaaAbusharkh 0:a49e37a83a7a 89 #define IEEE_ADDR_1 0x25
DuaaAbusharkh 0:a49e37a83a7a 90 #define IEEE_ADDR_2 0x26
DuaaAbusharkh 0:a49e37a83a7a 91 #define IEEE_ADDR_3 0x27
DuaaAbusharkh 0:a49e37a83a7a 92 #define IEEE_ADDR_4 0x28
DuaaAbusharkh 0:a49e37a83a7a 93 #define IEEE_ADDR_5 0x29
DuaaAbusharkh 0:a49e37a83a7a 94 #define IEEE_ADDR_6 0x2A
DuaaAbusharkh 0:a49e37a83a7a 95 #define IEEE_ADDR_7 0x2B
DuaaAbusharkh 0:a49e37a83a7a 96 #define XAH_CTRL_0 0x2C
DuaaAbusharkh 0:a49e37a83a7a 97 #define CSMA_SEED_0 0x2D
DuaaAbusharkh 0:a49e37a83a7a 98 #define CSMA_SEED_1 0x2E
DuaaAbusharkh 0:a49e37a83a7a 99 #define CSMA_BE 0x2F
DuaaAbusharkh 0:a49e37a83a7a 100
DuaaAbusharkh 0:a49e37a83a7a 101 /* CSMA_SEED_1*/
DuaaAbusharkh 0:a49e37a83a7a 102 #define AACK_FVN_MODE1 7
DuaaAbusharkh 0:a49e37a83a7a 103 #define AACK_FVN_MODE0 6
DuaaAbusharkh 0:a49e37a83a7a 104 #define AACK_SET_PD 5
DuaaAbusharkh 0:a49e37a83a7a 105 #define AACK_DIS_ACK 4
DuaaAbusharkh 0:a49e37a83a7a 106 #define AACK_I_AM_COORD 3
DuaaAbusharkh 0:a49e37a83a7a 107 #define CSMA_SEED_12 2
DuaaAbusharkh 0:a49e37a83a7a 108 #define CSMA_SEED_11 1
DuaaAbusharkh 0:a49e37a83a7a 109 #define CSMA_SEED_10 0
DuaaAbusharkh 0:a49e37a83a7a 110
DuaaAbusharkh 0:a49e37a83a7a 111 /*TRX_STATUS bits*/
DuaaAbusharkh 0:a49e37a83a7a 112 #define CCA_STATUS 0x40
DuaaAbusharkh 0:a49e37a83a7a 113 #define CCA_DONE 0x80
DuaaAbusharkh 0:a49e37a83a7a 114
DuaaAbusharkh 0:a49e37a83a7a 115 /*PHY_CC_CCA bits*/
DuaaAbusharkh 0:a49e37a83a7a 116 #define CCA_REQUEST 0x80
DuaaAbusharkh 0:a49e37a83a7a 117 #define CCA_MODE_1 0x20
DuaaAbusharkh 0:a49e37a83a7a 118 #define CCA_MODE_3 0x60
DuaaAbusharkh 0:a49e37a83a7a 119
DuaaAbusharkh 0:a49e37a83a7a 120 /*IRQ_MASK bits*/
DuaaAbusharkh 0:a49e37a83a7a 121 #define RX_START 0x04
DuaaAbusharkh 0:a49e37a83a7a 122 #define TRX_END 0x08
DuaaAbusharkh 0:a49e37a83a7a 123 #define CCA_ED_DONE 0x10
DuaaAbusharkh 0:a49e37a83a7a 124 #define AMI 0x20
DuaaAbusharkh 0:a49e37a83a7a 125 #define TRX_UR 0x40
DuaaAbusharkh 0:a49e37a83a7a 126
DuaaAbusharkh 0:a49e37a83a7a 127 /*ANT_DIV bits*/
DuaaAbusharkh 0:a49e37a83a7a 128 #define ANT_DIV_EN 0x08
DuaaAbusharkh 0:a49e37a83a7a 129 #define ANT_EXT_SW_EN 0x04
DuaaAbusharkh 0:a49e37a83a7a 130 #define ANT_CTRL_DEFAULT 0x03
DuaaAbusharkh 0:a49e37a83a7a 131
DuaaAbusharkh 0:a49e37a83a7a 132 /*TRX_CTRL_1 bits*/
DuaaAbusharkh 0:a49e37a83a7a 133 #define PA_EXT_EN 0x80
DuaaAbusharkh 0:a49e37a83a7a 134
DuaaAbusharkh 0:a49e37a83a7a 135 /*FTN_CTRL bits*/
DuaaAbusharkh 0:a49e37a83a7a 136 #define FTN_START 0x80
DuaaAbusharkh 0:a49e37a83a7a 137
DuaaAbusharkh 0:a49e37a83a7a 138 /*PHY_RSSI bits*/
DuaaAbusharkh 0:a49e37a83a7a 139 #define CRC_VALID 0x80
DuaaAbusharkh 0:a49e37a83a7a 140
DuaaAbusharkh 0:a49e37a83a7a 141 /*RX_SYN bits*/
DuaaAbusharkh 0:a49e37a83a7a 142 #define RX_PDT_DIS 0x80
DuaaAbusharkh 0:a49e37a83a7a 143
DuaaAbusharkh 0:a49e37a83a7a 144 /*TRX_RPC bits */
DuaaAbusharkh 0:a49e37a83a7a 145 #define RX_RPC_CTRL 0xC0
DuaaAbusharkh 0:a49e37a83a7a 146 #define RX_RPC_EN 0x20
DuaaAbusharkh 0:a49e37a83a7a 147 #define PDT_RPC_EN 0x10
DuaaAbusharkh 0:a49e37a83a7a 148 #define PLL_RPC_EN 0x08
DuaaAbusharkh 0:a49e37a83a7a 149 #define XAH_TX_RPC_EN 0x04
DuaaAbusharkh 0:a49e37a83a7a 150 #define IPAN_RPC_EN 0x02
DuaaAbusharkh 0:a49e37a83a7a 151 #define TRX_RPC_RSVD_1 0x01
DuaaAbusharkh 0:a49e37a83a7a 152
DuaaAbusharkh 0:a49e37a83a7a 153 /*XAH_CTRL_1 bits*/
DuaaAbusharkh 0:a49e37a83a7a 154 #define AACK_PROM_MODE 0x02
DuaaAbusharkh 0:a49e37a83a7a 155
DuaaAbusharkh 0:a49e37a83a7a 156
DuaaAbusharkh 0:a49e37a83a7a 157 #ifdef __cplusplus
DuaaAbusharkh 0:a49e37a83a7a 158 }
DuaaAbusharkh 0:a49e37a83a7a 159 #endif
DuaaAbusharkh 0:a49e37a83a7a 160
DuaaAbusharkh 0:a49e37a83a7a 161 #endif /* AT86RFREG_H_ */