Umar Naeem / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by Umar Naeem

targets/cmsis/TARGET_NXP/TARGET_LPC81X/LPC8xx.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Child:
144:ef7eb2e8f9f7
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /****************************************************************************
bogdanm 0:9b334a45a8ff 2 * $Id:: LPC8xx.h 6437 2012-10-31 11:06:06Z dep00694 $
bogdanm 0:9b334a45a8ff 3 * Project: NXP LPC8xx software example
bogdanm 0:9b334a45a8ff 4 *
bogdanm 0:9b334a45a8ff 5 * Description:
bogdanm 0:9b334a45a8ff 6 * CMSIS Cortex-M0+ Core Peripheral Access Layer Header File for
bogdanm 0:9b334a45a8ff 7 * NXP LPC800 Device Series
bogdanm 0:9b334a45a8ff 8 *
bogdanm 0:9b334a45a8ff 9 ****************************************************************************
bogdanm 0:9b334a45a8ff 10 * Software that is described herein is for illustrative purposes only
bogdanm 0:9b334a45a8ff 11 * which provides customers with programming information regarding the
bogdanm 0:9b334a45a8ff 12 * products. This software is supplied "AS IS" without any warranties.
bogdanm 0:9b334a45a8ff 13 * NXP Semiconductors assumes no responsibility or liability for the
bogdanm 0:9b334a45a8ff 14 * use of the software, conveys no license or title under any patent,
bogdanm 0:9b334a45a8ff 15 * copyright, or mask work right to the product. NXP Semiconductors
bogdanm 0:9b334a45a8ff 16 * reserves the right to make changes in the software without
bogdanm 0:9b334a45a8ff 17 * notification. NXP Semiconductors also make no representation or
bogdanm 0:9b334a45a8ff 18 * warranty that such application will be suitable for the specified
bogdanm 0:9b334a45a8ff 19 * use without further testing or modification.
bogdanm 0:9b334a45a8ff 20
bogdanm 0:9b334a45a8ff 21 * Permission to use, copy, modify, and distribute this software and its
bogdanm 0:9b334a45a8ff 22 * documentation is hereby granted, under NXP Semiconductors'
bogdanm 0:9b334a45a8ff 23 * relevant copyright in the software, without fee, provided that it
bogdanm 0:9b334a45a8ff 24 * is used in conjunction with NXP Semiconductors microcontrollers. This
bogdanm 0:9b334a45a8ff 25 * copyright, permission, and disclaimer notice must appear in all copies of
bogdanm 0:9b334a45a8ff 26 * this code.
bogdanm 0:9b334a45a8ff 27 ****************************************************************************/
bogdanm 0:9b334a45a8ff 28 #ifndef __LPC8xx_H__
bogdanm 0:9b334a45a8ff 29 #define __LPC8xx_H__
bogdanm 0:9b334a45a8ff 30
bogdanm 0:9b334a45a8ff 31 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 32 extern "C" {
bogdanm 0:9b334a45a8ff 33 #endif
bogdanm 0:9b334a45a8ff 34
bogdanm 0:9b334a45a8ff 35 /** @addtogroup LPC8xx_Definitions LPC8xx Definitions
bogdanm 0:9b334a45a8ff 36 This file defines all structures and symbols for LPC8xx:
bogdanm 0:9b334a45a8ff 37 - Registers and bitfields
bogdanm 0:9b334a45a8ff 38 - peripheral base address
bogdanm 0:9b334a45a8ff 39 - PIO definitions
bogdanm 0:9b334a45a8ff 40 @{
bogdanm 0:9b334a45a8ff 41 */
bogdanm 0:9b334a45a8ff 42
bogdanm 0:9b334a45a8ff 43
bogdanm 0:9b334a45a8ff 44 /******************************************************************************/
bogdanm 0:9b334a45a8ff 45 /* Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 46 /******************************************************************************/
bogdanm 0:9b334a45a8ff 47 /** @addtogroup LPC8xx_CMSIS LPC8xx CMSIS Definitions
bogdanm 0:9b334a45a8ff 48 Configuration of the Cortex-M0+ Processor and Core Peripherals
bogdanm 0:9b334a45a8ff 49 @{
bogdanm 0:9b334a45a8ff 50 */
bogdanm 0:9b334a45a8ff 51
bogdanm 0:9b334a45a8ff 52 /*
bogdanm 0:9b334a45a8ff 53 * ==========================================================================
bogdanm 0:9b334a45a8ff 54 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 0:9b334a45a8ff 55 * ==========================================================================
bogdanm 0:9b334a45a8ff 56 */
bogdanm 0:9b334a45a8ff 57 typedef enum IRQn
bogdanm 0:9b334a45a8ff 58 {
bogdanm 0:9b334a45a8ff 59 /****** Cortex-M0 Processor Exceptions Numbers ***************************************************/
bogdanm 0:9b334a45a8ff 60 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset*/
bogdanm 0:9b334a45a8ff 61 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 0:9b334a45a8ff 62 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
bogdanm 0:9b334a45a8ff 63 SVCall_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
bogdanm 0:9b334a45a8ff 64 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
bogdanm 0:9b334a45a8ff 65 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
bogdanm 0:9b334a45a8ff 66
bogdanm 0:9b334a45a8ff 67 /****** LPC8xx Specific Interrupt Numbers ********************************************************/
bogdanm 0:9b334a45a8ff 68 SPI0_IRQn = 0, /*!< SPI0 */
bogdanm 0:9b334a45a8ff 69 SPI1_IRQn = 1, /*!< SPI1 */
bogdanm 0:9b334a45a8ff 70 Reserved0_IRQn = 2, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 71 UART0_IRQn = 3, /*!< USART0 */
bogdanm 0:9b334a45a8ff 72 UART1_IRQn = 4, /*!< USART1 */
bogdanm 0:9b334a45a8ff 73 UART2_IRQn = 5, /*!< USART2 */
bogdanm 0:9b334a45a8ff 74 Reserved1_IRQn = 6, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 75 Reserved2_IRQn = 7, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 76 I2C_IRQn = 8, /*!< I2C */
bogdanm 0:9b334a45a8ff 77 SCT_IRQn = 9, /*!< SCT */
bogdanm 0:9b334a45a8ff 78 MRT_IRQn = 10, /*!< MRT */
bogdanm 0:9b334a45a8ff 79 CMP_IRQn = 11, /*!< CMP */
bogdanm 0:9b334a45a8ff 80 WDT_IRQn = 12, /*!< WDT */
bogdanm 0:9b334a45a8ff 81 BOD_IRQn = 13, /*!< BOD */
bogdanm 0:9b334a45a8ff 82 Reserved3_IRQn = 14, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 83 WKT_IRQn = 15, /*!< WKT Interrupt */
bogdanm 0:9b334a45a8ff 84 Reserved4_IRQn = 16, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 85 Reserved5_IRQn = 17, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 86 Reserved6_IRQn = 18, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 87 Reserved7_IRQn = 19, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 88 Reserved8_IRQn = 20, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 89 Reserved9_IRQn = 21, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 90 Reserved10_IRQn = 22, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 91 Reserved11_IRQn = 23, /*!< Reserved Interrupt */
bogdanm 0:9b334a45a8ff 92 PININT0_IRQn = 24, /*!< External Interrupt 0 */
bogdanm 0:9b334a45a8ff 93 PININT1_IRQn = 25, /*!< External Interrupt 1 */
bogdanm 0:9b334a45a8ff 94 PININT2_IRQn = 26, /*!< External Interrupt 2 */
bogdanm 0:9b334a45a8ff 95 PININT3_IRQn = 27, /*!< External Interrupt 3 */
bogdanm 0:9b334a45a8ff 96 PININT4_IRQn = 28, /*!< External Interrupt 4 */
bogdanm 0:9b334a45a8ff 97 PININT5_IRQn = 29, /*!< External Interrupt 5 */
bogdanm 0:9b334a45a8ff 98 PININT6_IRQn = 30, /*!< External Interrupt 6 */
bogdanm 0:9b334a45a8ff 99 PININT7_IRQn = 31, /*!< External Interrupt 7 */
bogdanm 0:9b334a45a8ff 100 } IRQn_Type;
bogdanm 0:9b334a45a8ff 101
bogdanm 0:9b334a45a8ff 102 /*
bogdanm 0:9b334a45a8ff 103 * ==========================================================================
bogdanm 0:9b334a45a8ff 104 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 0:9b334a45a8ff 105 * ==========================================================================
bogdanm 0:9b334a45a8ff 106 */
bogdanm 0:9b334a45a8ff 107
bogdanm 0:9b334a45a8ff 108 /* Configuration of the Cortex-M0+ Processor and Core Peripherals */
bogdanm 0:9b334a45a8ff 109 #define __MPU_PRESENT 0 /*!< MPU present or not */
bogdanm 0:9b334a45a8ff 110 #define __VTOR_PRESENT 1 /**< Defines if an VTOR is present or not */
bogdanm 0:9b334a45a8ff 111 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
bogdanm 0:9b334a45a8ff 112 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 0:9b334a45a8ff 113
bogdanm 0:9b334a45a8ff 114 /*@}*/ /* end of group LPC8xx_CMSIS */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116
bogdanm 0:9b334a45a8ff 117 #include "core_cm0plus.h" /* Cortex-M0+ processor and core peripherals */
bogdanm 0:9b334a45a8ff 118 #include "system_LPC8xx.h" /* System Header */
bogdanm 0:9b334a45a8ff 119
bogdanm 0:9b334a45a8ff 120
bogdanm 0:9b334a45a8ff 121 /******************************************************************************/
bogdanm 0:9b334a45a8ff 122 /* Device Specific Peripheral Registers structures */
bogdanm 0:9b334a45a8ff 123 /******************************************************************************/
bogdanm 0:9b334a45a8ff 124
bogdanm 0:9b334a45a8ff 125 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 126 #pragma anon_unions
bogdanm 0:9b334a45a8ff 127 #endif
bogdanm 0:9b334a45a8ff 128
bogdanm 0:9b334a45a8ff 129 /*------------- System Control (SYSCON) --------------------------------------*/
bogdanm 0:9b334a45a8ff 130 /** @addtogroup LPC8xx_SYSCON LPC8xx System Control Block
bogdanm 0:9b334a45a8ff 131 @{
bogdanm 0:9b334a45a8ff 132 */
bogdanm 0:9b334a45a8ff 133 typedef struct
bogdanm 0:9b334a45a8ff 134 {
bogdanm 0:9b334a45a8ff 135 __IO uint32_t SYSMEMREMAP; /*!< Offset: 0x000 System memory remap (R/W) */
bogdanm 0:9b334a45a8ff 136 __IO uint32_t PRESETCTRL; /*!< Offset: 0x004 Peripheral reset control (R/W) */
bogdanm 0:9b334a45a8ff 137 __IO uint32_t SYSPLLCTRL; /*!< Offset: 0x008 System PLL control (R/W) */
bogdanm 0:9b334a45a8ff 138 __IO uint32_t SYSPLLSTAT; /*!< Offset: 0x00C System PLL status (R/W ) */
bogdanm 0:9b334a45a8ff 139 uint32_t RESERVED0[4];
bogdanm 0:9b334a45a8ff 140
bogdanm 0:9b334a45a8ff 141 __IO uint32_t SYSOSCCTRL; /*!< Offset: 0x020 System oscillator control (R/W) */
bogdanm 0:9b334a45a8ff 142 __IO uint32_t WDTOSCCTRL; /*!< Offset: 0x024 Watchdog oscillator control (R/W) */
bogdanm 0:9b334a45a8ff 143 uint32_t RESERVED1[2];
bogdanm 0:9b334a45a8ff 144 __IO uint32_t SYSRSTSTAT; /*!< Offset: 0x030 System reset status Register (R/W ) */
bogdanm 0:9b334a45a8ff 145 uint32_t RESERVED2[3];
bogdanm 0:9b334a45a8ff 146 __IO uint32_t SYSPLLCLKSEL; /*!< Offset: 0x040 System PLL clock source select (R/W) */
bogdanm 0:9b334a45a8ff 147 __IO uint32_t SYSPLLCLKUEN; /*!< Offset: 0x044 System PLL clock source update enable (R/W) */
bogdanm 0:9b334a45a8ff 148 uint32_t RESERVED3[10];
bogdanm 0:9b334a45a8ff 149
bogdanm 0:9b334a45a8ff 150 __IO uint32_t MAINCLKSEL; /*!< Offset: 0x070 Main clock source select (R/W) */
bogdanm 0:9b334a45a8ff 151 __IO uint32_t MAINCLKUEN; /*!< Offset: 0x074 Main clock source update enable (R/W) */
bogdanm 0:9b334a45a8ff 152 __IO uint32_t SYSAHBCLKDIV; /*!< Offset: 0x078 System AHB clock divider (R/W) */
bogdanm 0:9b334a45a8ff 153 uint32_t RESERVED4[1];
bogdanm 0:9b334a45a8ff 154
bogdanm 0:9b334a45a8ff 155 __IO uint32_t SYSAHBCLKCTRL; /*!< Offset: 0x080 System AHB clock control (R/W) */
bogdanm 0:9b334a45a8ff 156 uint32_t RESERVED5[4];
bogdanm 0:9b334a45a8ff 157 __IO uint32_t UARTCLKDIV; /*!< Offset: 0x094 UART clock divider (R/W) */
bogdanm 0:9b334a45a8ff 158 uint32_t RESERVED6[18];
bogdanm 0:9b334a45a8ff 159
bogdanm 0:9b334a45a8ff 160 __IO uint32_t CLKOUTSEL; /*!< Offset: 0x0E0 CLKOUT clock source select (R/W) */
bogdanm 0:9b334a45a8ff 161 __IO uint32_t CLKOUTUEN; /*!< Offset: 0x0E4 CLKOUT clock source update enable (R/W) */
bogdanm 0:9b334a45a8ff 162 __IO uint32_t CLKOUTDIV; /*!< Offset: 0x0E8 CLKOUT clock divider (R/W) */
bogdanm 0:9b334a45a8ff 163 uint32_t RESERVED7;
bogdanm 0:9b334a45a8ff 164 __IO uint32_t UARTFRGDIV; /*!< Offset: 0x0F0 UART fractional divider SUB(R/W) */
bogdanm 0:9b334a45a8ff 165 __IO uint32_t UARTFRGMULT; /*!< Offset: 0x0F4 UART fractional divider ADD(R/W) */
bogdanm 0:9b334a45a8ff 166 uint32_t RESERVED8[1];
bogdanm 0:9b334a45a8ff 167 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
bogdanm 0:9b334a45a8ff 168 __IO uint32_t PIOPORCAP0; /*!< Offset: 0x100 POR captured PIO status 0 (R/ ) */
bogdanm 0:9b334a45a8ff 169 uint32_t RESERVED9[12];
bogdanm 0:9b334a45a8ff 170 __IO uint32_t IOCONCLKDIV[7]; /*!< (@0x40048134-14C) Peripheral clock x to the IOCON block for programmable glitch filter */
bogdanm 0:9b334a45a8ff 171 __IO uint32_t BODCTRL; /*!< Offset: 0x150 BOD control (R/W) */
bogdanm 0:9b334a45a8ff 172 __IO uint32_t SYSTCKCAL; /*!< Offset: 0x154 System tick counter calibration (R/W) */
bogdanm 0:9b334a45a8ff 173 uint32_t RESERVED10[6];
bogdanm 0:9b334a45a8ff 174 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IRQ delay */
bogdanm 0:9b334a45a8ff 175 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
bogdanm 0:9b334a45a8ff 176 __IO uint32_t PINTSEL[8]; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
bogdanm 0:9b334a45a8ff 177 uint32_t RESERVED11[27];
bogdanm 0:9b334a45a8ff 178 __IO uint32_t STARTERP0; /*!< Offset: 0x204 Start logic signal enable Register 0 (R/W) */
bogdanm 0:9b334a45a8ff 179 uint32_t RESERVED12[3];
bogdanm 0:9b334a45a8ff 180 __IO uint32_t STARTERP1; /*!< Offset: 0x214 Start logic signal enable Register 0 (R/W) */
bogdanm 0:9b334a45a8ff 181 uint32_t RESERVED13[6];
bogdanm 0:9b334a45a8ff 182 __IO uint32_t PDSLEEPCFG; /*!< Offset: 0x230 Power-down states in Deep-sleep mode (R/W) */
bogdanm 0:9b334a45a8ff 183 __IO uint32_t PDAWAKECFG; /*!< Offset: 0x234 Power-down states after wake-up (R/W) */
bogdanm 0:9b334a45a8ff 184 __IO uint32_t PDRUNCFG; /*!< Offset: 0x238 Power-down configuration Register (R/W) */
bogdanm 0:9b334a45a8ff 185 uint32_t RESERVED14[110];
bogdanm 0:9b334a45a8ff 186 __I uint32_t DEVICE_ID; /*!< Offset: 0x3F4 Device ID (R/ ) */
bogdanm 0:9b334a45a8ff 187 } LPC_SYSCON_TypeDef;
bogdanm 0:9b334a45a8ff 188 /*@}*/ /* end of group LPC8xx_SYSCON */
bogdanm 0:9b334a45a8ff 189
bogdanm 0:9b334a45a8ff 190
bogdanm 0:9b334a45a8ff 191 /**
bogdanm 0:9b334a45a8ff 192 * @brief Product name title=UM10462 Chapter title=LPC8xx I/O configuration Modification date=3/16/2011 Major revision=0 Minor revision=3 (IOCONFIG)
bogdanm 0:9b334a45a8ff 193 */
bogdanm 0:9b334a45a8ff 194
bogdanm 0:9b334a45a8ff 195 typedef struct { /*!< (@ 0x40044000) IOCONFIG Structure */
bogdanm 0:9b334a45a8ff 196 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
bogdanm 0:9b334a45a8ff 197 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
bogdanm 0:9b334a45a8ff 198 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
bogdanm 0:9b334a45a8ff 199 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5 */
bogdanm 0:9b334a45a8ff 200 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
bogdanm 0:9b334a45a8ff 201 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3 */
bogdanm 0:9b334a45a8ff 202 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2 */
bogdanm 0:9b334a45a8ff 203 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11 */
bogdanm 0:9b334a45a8ff 204 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10 */
bogdanm 0:9b334a45a8ff 205 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
bogdanm 0:9b334a45a8ff 206 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
bogdanm 0:9b334a45a8ff 207 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_1 */
bogdanm 0:9b334a45a8ff 208 __IO uint32_t Reserved; /*!< (@ 0x40044030) I/O configuration for pin (Reserved) */
bogdanm 0:9b334a45a8ff 209 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9 */
bogdanm 0:9b334a45a8ff 210 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8 */
bogdanm 0:9b334a45a8ff 211 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
bogdanm 0:9b334a45a8ff 212 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6 */
bogdanm 0:9b334a45a8ff 213 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0 */
bogdanm 0:9b334a45a8ff 214 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
bogdanm 0:9b334a45a8ff 215 } LPC_IOCON_TypeDef;
bogdanm 0:9b334a45a8ff 216 /*@}*/ /* end of group LPC8xx_IOCON */
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /**
bogdanm 0:9b334a45a8ff 219 * @brief Product name title=UM10462 Chapter title=LPC8xx Flash programming firmware Major revision=0 Minor revision=3 (FLASHCTRL)
bogdanm 0:9b334a45a8ff 220 */
bogdanm 0:9b334a45a8ff 221 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
bogdanm 0:9b334a45a8ff 222 __I uint32_t RESERVED0[4];
bogdanm 0:9b334a45a8ff 223 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
bogdanm 0:9b334a45a8ff 224 __I uint32_t RESERVED1[3];
bogdanm 0:9b334a45a8ff 225 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
bogdanm 0:9b334a45a8ff 226 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
bogdanm 0:9b334a45a8ff 227 __I uint32_t RESERVED2;
bogdanm 0:9b334a45a8ff 228 __I uint32_t FMSW0;
bogdanm 0:9b334a45a8ff 229 } LPC_FLASHCTRL_TypeDef;
bogdanm 0:9b334a45a8ff 230 /*@}*/ /* end of group LPC8xx_FLASHCTRL */
bogdanm 0:9b334a45a8ff 231
bogdanm 0:9b334a45a8ff 232
bogdanm 0:9b334a45a8ff 233 /*------------- Power Management Unit (PMU) --------------------------*/
bogdanm 0:9b334a45a8ff 234 /** @addtogroup LPC8xx_PMU LPC8xx Power Management Unit
bogdanm 0:9b334a45a8ff 235 @{
bogdanm 0:9b334a45a8ff 236 */
bogdanm 0:9b334a45a8ff 237 typedef struct
bogdanm 0:9b334a45a8ff 238 {
bogdanm 0:9b334a45a8ff 239 __IO uint32_t PCON; /*!< Offset: 0x000 Power control Register (R/W) */
bogdanm 0:9b334a45a8ff 240 __IO uint32_t GPREG0; /*!< Offset: 0x004 General purpose Register 0 (R/W) */
bogdanm 0:9b334a45a8ff 241 __IO uint32_t GPREG1; /*!< Offset: 0x008 General purpose Register 1 (R/W) */
bogdanm 0:9b334a45a8ff 242 __IO uint32_t GPREG2; /*!< Offset: 0x00C General purpose Register 2 (R/W) */
bogdanm 0:9b334a45a8ff 243 __IO uint32_t GPREG3; /*!< Offset: 0x010 General purpose Register 3 (R/W) */
bogdanm 0:9b334a45a8ff 244 __IO uint32_t DPDCTRL; /*!< Offset: 0x014 Deep power-down control register (R/W) */
bogdanm 0:9b334a45a8ff 245 } LPC_PMU_TypeDef;
bogdanm 0:9b334a45a8ff 246 /*@}*/ /* end of group LPC8xx_PMU */
bogdanm 0:9b334a45a8ff 247
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249 /*------------- Switch Matrix Port --------------------------*/
bogdanm 0:9b334a45a8ff 250 /** @addtogroup LPC8xx_SWM LPC8xx Switch Matrix Port
bogdanm 0:9b334a45a8ff 251 @{
bogdanm 0:9b334a45a8ff 252 */
bogdanm 0:9b334a45a8ff 253 typedef struct
bogdanm 0:9b334a45a8ff 254 {
bogdanm 0:9b334a45a8ff 255 union {
bogdanm 0:9b334a45a8ff 256 __IO uint32_t PINASSIGN[9];
bogdanm 0:9b334a45a8ff 257 struct {
bogdanm 0:9b334a45a8ff 258 __IO uint32_t PINASSIGN0;
bogdanm 0:9b334a45a8ff 259 __IO uint32_t PINASSIGN1;
bogdanm 0:9b334a45a8ff 260 __IO uint32_t PINASSIGN2;
bogdanm 0:9b334a45a8ff 261 __IO uint32_t PINASSIGN3;
bogdanm 0:9b334a45a8ff 262 __IO uint32_t PINASSIGN4;
bogdanm 0:9b334a45a8ff 263 __IO uint32_t PINASSIGN5;
bogdanm 0:9b334a45a8ff 264 __IO uint32_t PINASSIGN6;
bogdanm 0:9b334a45a8ff 265 __IO uint32_t PINASSIGN7;
bogdanm 0:9b334a45a8ff 266 __IO uint32_t PINASSIGN8;
bogdanm 0:9b334a45a8ff 267 };
bogdanm 0:9b334a45a8ff 268 };
bogdanm 0:9b334a45a8ff 269 __I uint32_t RESERVED0[103];
bogdanm 0:9b334a45a8ff 270 __IO uint32_t PINENABLE0;
bogdanm 0:9b334a45a8ff 271 } LPC_SWM_TypeDef;
bogdanm 0:9b334a45a8ff 272 /*@}*/ /* end of group LPC8xx_SWM */
bogdanm 0:9b334a45a8ff 273
bogdanm 0:9b334a45a8ff 274
bogdanm 0:9b334a45a8ff 275 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 276 // ----- GPIO_PORT -----
bogdanm 0:9b334a45a8ff 277 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 278
bogdanm 0:9b334a45a8ff 279 /**
bogdanm 0:9b334a45a8ff 280 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (GPIO_PORT)
bogdanm 0:9b334a45a8ff 281 */
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283 typedef struct {
bogdanm 0:9b334a45a8ff 284 __IO uint8_t B0[18]; /*!< (@ 0xA0000000) Byte pin registers port 0 */
bogdanm 0:9b334a45a8ff 285 __I uint16_t RESERVED0[2039];
bogdanm 0:9b334a45a8ff 286 __IO uint32_t W0[18]; /*!< (@ 0xA0001000) Word pin registers port 0 */
bogdanm 0:9b334a45a8ff 287 uint32_t RESERVED1[1006];
bogdanm 0:9b334a45a8ff 288 __IO uint32_t DIR0; /* 0x2000 */
bogdanm 0:9b334a45a8ff 289 uint32_t RESERVED2[31];
bogdanm 0:9b334a45a8ff 290 __IO uint32_t MASK0; /* 0x2080 */
bogdanm 0:9b334a45a8ff 291 uint32_t RESERVED3[31];
bogdanm 0:9b334a45a8ff 292 __IO uint32_t PIN0; /* 0x2100 */
bogdanm 0:9b334a45a8ff 293 uint32_t RESERVED4[31];
bogdanm 0:9b334a45a8ff 294 __IO uint32_t MPIN0; /* 0x2180 */
bogdanm 0:9b334a45a8ff 295 uint32_t RESERVED5[31];
bogdanm 0:9b334a45a8ff 296 __IO uint32_t SET0; /* 0x2200 */
bogdanm 0:9b334a45a8ff 297 uint32_t RESERVED6[31];
bogdanm 0:9b334a45a8ff 298 __O uint32_t CLR0; /* 0x2280 */
bogdanm 0:9b334a45a8ff 299 uint32_t RESERVED7[31];
bogdanm 0:9b334a45a8ff 300 __O uint32_t NOT0; /* 0x2300 */
bogdanm 0:9b334a45a8ff 301
bogdanm 0:9b334a45a8ff 302 } LPC_GPIO_PORT_TypeDef;
bogdanm 0:9b334a45a8ff 303
bogdanm 0:9b334a45a8ff 304
bogdanm 0:9b334a45a8ff 305 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 306 // ----- PIN_INT -----
bogdanm 0:9b334a45a8ff 307 // ------------------------------------------------------------------------------------------------
bogdanm 0:9b334a45a8ff 308
bogdanm 0:9b334a45a8ff 309 /**
bogdanm 0:9b334a45a8ff 310 * @brief Product name title=UM10462 Chapter title=LPC8xx GPIO Modification date=3/17/2011 Major revision=0 Minor revision=3 (PIN_INT)
bogdanm 0:9b334a45a8ff 311 */
bogdanm 0:9b334a45a8ff 312
bogdanm 0:9b334a45a8ff 313 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
bogdanm 0:9b334a45a8ff 314 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
bogdanm 0:9b334a45a8ff 315 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin Interrupt Enable (Rising) register */
bogdanm 0:9b334a45a8ff 316 __IO uint32_t SIENR; /*!< (@ 0xA0004008) Set Pin Interrupt Enable (Rising) register */
bogdanm 0:9b334a45a8ff 317 __IO uint32_t CIENR; /*!< (@ 0xA000400C) Clear Pin Interrupt Enable (Rising) register */
bogdanm 0:9b334a45a8ff 318 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 0:9b334a45a8ff 319 __IO uint32_t SIENF; /*!< (@ 0xA0004014) Set Pin Interrupt Enable Falling Edge / Active Level register */
bogdanm 0:9b334a45a8ff 320 __IO uint32_t CIENF; /*!< (@ 0xA0004018) Clear Pin Interrupt Enable Falling Edge / Active Level address */
bogdanm 0:9b334a45a8ff 321 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin Interrupt Rising Edge register */
bogdanm 0:9b334a45a8ff 322 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin Interrupt Falling Edge register */
bogdanm 0:9b334a45a8ff 323 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin Interrupt Status register */
bogdanm 0:9b334a45a8ff 324 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
bogdanm 0:9b334a45a8ff 325 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source register */
bogdanm 0:9b334a45a8ff 326 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration register */
bogdanm 0:9b334a45a8ff 327 } LPC_PIN_INT_TypeDef;
bogdanm 0:9b334a45a8ff 328
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /*------------- CRC Engine (CRC) -----------------------------------------*/
bogdanm 0:9b334a45a8ff 331 /** @addtogroup LPC8xx_CRC
bogdanm 0:9b334a45a8ff 332 @{
bogdanm 0:9b334a45a8ff 333 */
bogdanm 0:9b334a45a8ff 334 typedef struct
bogdanm 0:9b334a45a8ff 335 {
bogdanm 0:9b334a45a8ff 336 __IO uint32_t MODE;
bogdanm 0:9b334a45a8ff 337 __IO uint32_t SEED;
bogdanm 0:9b334a45a8ff 338 union {
bogdanm 0:9b334a45a8ff 339 __I uint32_t SUM;
bogdanm 0:9b334a45a8ff 340 __O uint32_t WR_DATA_DWORD;
bogdanm 0:9b334a45a8ff 341 __O uint16_t WR_DATA_WORD;
bogdanm 0:9b334a45a8ff 342 uint16_t RESERVED_WORD;
bogdanm 0:9b334a45a8ff 343 __O uint8_t WR_DATA_BYTE;
bogdanm 0:9b334a45a8ff 344 uint8_t RESERVED_BYTE[3];
bogdanm 0:9b334a45a8ff 345 };
bogdanm 0:9b334a45a8ff 346 } LPC_CRC_TypeDef;
bogdanm 0:9b334a45a8ff 347 /*@}*/ /* end of group LPC8xx_CRC */
bogdanm 0:9b334a45a8ff 348
bogdanm 0:9b334a45a8ff 349 /*------------- Comparator (CMP) --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 350 /** @addtogroup LPC8xx_CMP LPC8xx Comparator
bogdanm 0:9b334a45a8ff 351 @{
bogdanm 0:9b334a45a8ff 352 */
bogdanm 0:9b334a45a8ff 353 typedef struct { /*!< (@ 0x40024000) CMP Structure */
bogdanm 0:9b334a45a8ff 354 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
bogdanm 0:9b334a45a8ff 355 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
bogdanm 0:9b334a45a8ff 356 } LPC_CMP_TypeDef;
bogdanm 0:9b334a45a8ff 357 /*@}*/ /* end of group LPC8xx_CMP */
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359
bogdanm 0:9b334a45a8ff 360 /*------------- Wakeup Timer (WKT) --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 361 /** @addtogroup LPC8xx_WKT
bogdanm 0:9b334a45a8ff 362 @{
bogdanm 0:9b334a45a8ff 363 */
bogdanm 0:9b334a45a8ff 364 typedef struct { /*!< (@ 0x40028000) WKT Structure */
bogdanm 0:9b334a45a8ff 365 __IO uint32_t CTRL; /*!< (@ 0x40028000) Alarm/Wakeup Timer Control register */
bogdanm 0:9b334a45a8ff 366 uint32_t Reserved[2];
bogdanm 0:9b334a45a8ff 367 __IO uint32_t COUNT; /*!< (@ 0x4002800C) Alarm/Wakeup TImer counter register */
bogdanm 0:9b334a45a8ff 368 } LPC_WKT_TypeDef;
bogdanm 0:9b334a45a8ff 369 /*@}*/ /* end of group LPC8xx_WKT */
bogdanm 0:9b334a45a8ff 370
bogdanm 0:9b334a45a8ff 371 /*------------- Multi-Rate Timer(MRT) --------------------------------------------------*/
bogdanm 0:9b334a45a8ff 372 //New, Copied from lpc824
bogdanm 0:9b334a45a8ff 373 /**
bogdanm 0:9b334a45a8ff 374 * @brief Multi-Rate Timer (MRT) (MRT)
bogdanm 0:9b334a45a8ff 375 */
bogdanm 0:9b334a45a8ff 376 typedef struct { /*!< (@ 0x40004000) MRT Structure */
bogdanm 0:9b334a45a8ff 377 __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
bogdanm 0:9b334a45a8ff 378 is loaded into the TIMER0 register. */
bogdanm 0:9b334a45a8ff 379 __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
bogdanm 0:9b334a45a8ff 380 value of the down-counter. */
bogdanm 0:9b334a45a8ff 381 __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
bogdanm 0:9b334a45a8ff 382 the MRT0 modes. */
bogdanm 0:9b334a45a8ff 383 __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
bogdanm 0:9b334a45a8ff 384 __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
bogdanm 0:9b334a45a8ff 385 is loaded into the TIMER0 register. */
bogdanm 0:9b334a45a8ff 386 __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
bogdanm 0:9b334a45a8ff 387 value of the down-counter. */
bogdanm 0:9b334a45a8ff 388 __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
bogdanm 0:9b334a45a8ff 389 the MRT0 modes. */
bogdanm 0:9b334a45a8ff 390 __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
bogdanm 0:9b334a45a8ff 391 __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
bogdanm 0:9b334a45a8ff 392 is loaded into the TIMER0 register. */
bogdanm 0:9b334a45a8ff 393 __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
bogdanm 0:9b334a45a8ff 394 value of the down-counter. */
bogdanm 0:9b334a45a8ff 395 __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
bogdanm 0:9b334a45a8ff 396 the MRT0 modes. */
bogdanm 0:9b334a45a8ff 397 __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
bogdanm 0:9b334a45a8ff 398 __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
bogdanm 0:9b334a45a8ff 399 is loaded into the TIMER0 register. */
bogdanm 0:9b334a45a8ff 400 __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
bogdanm 0:9b334a45a8ff 401 value of the down-counter. */
bogdanm 0:9b334a45a8ff 402 __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
bogdanm 0:9b334a45a8ff 403 the MRT0 modes. */
bogdanm 0:9b334a45a8ff 404 __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
bogdanm 0:9b334a45a8ff 405 __I uint32_t RESERVED0[45];
bogdanm 0:9b334a45a8ff 406 __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
bogdanm 0:9b334a45a8ff 407 the number of the first idle channel. */
bogdanm 0:9b334a45a8ff 408 __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
bogdanm 0:9b334a45a8ff 409 } LPC_MRT_TypeDef;
bogdanm 0:9b334a45a8ff 410
bogdanm 0:9b334a45a8ff 411 /*------------- Universal Asynchronous Receiver Transmitter (USART) -----------*/
bogdanm 0:9b334a45a8ff 412 /** @addtogroup LPC8xx_UART LPC8xx Universal Asynchronous Receiver/Transmitter
bogdanm 0:9b334a45a8ff 413 @{
bogdanm 0:9b334a45a8ff 414 */
bogdanm 0:9b334a45a8ff 415 /**
bogdanm 0:9b334a45a8ff 416 * @brief Product name title=LPC8xx MCU Chapter title=USART Modification date=4/18/2012 Major revision=0 Minor revision=9 (USART)
bogdanm 0:9b334a45a8ff 417 */
bogdanm 0:9b334a45a8ff 418 typedef struct
bogdanm 0:9b334a45a8ff 419 {
bogdanm 0:9b334a45a8ff 420 __IO uint32_t CFG; /* 0x00 */
bogdanm 0:9b334a45a8ff 421 __IO uint32_t CTRL;
bogdanm 0:9b334a45a8ff 422 __IO uint32_t STAT;
bogdanm 0:9b334a45a8ff 423 __IO uint32_t INTENSET;
bogdanm 0:9b334a45a8ff 424 __O uint32_t INTENCLR; /* 0x10 */
bogdanm 0:9b334a45a8ff 425 __I uint32_t RXDATA;
bogdanm 0:9b334a45a8ff 426 __I uint32_t RXDATA_STAT;
bogdanm 0:9b334a45a8ff 427 __IO uint32_t TXDATA;
bogdanm 0:9b334a45a8ff 428 __IO uint32_t BRG; /* 0x20 */
bogdanm 0:9b334a45a8ff 429 __IO uint32_t INTSTAT;
bogdanm 0:9b334a45a8ff 430 } LPC_USART_TypeDef;
bogdanm 0:9b334a45a8ff 431
bogdanm 0:9b334a45a8ff 432 /*@}*/ /* end of group LPC8xx_USART */
bogdanm 0:9b334a45a8ff 433
bogdanm 0:9b334a45a8ff 434
bogdanm 0:9b334a45a8ff 435 /*------------- Synchronous Serial Interface Controller (SPI) -----------------------*/
bogdanm 0:9b334a45a8ff 436 /** @addtogroup LPC8xx_SPI LPC8xx Synchronous Serial Port
bogdanm 0:9b334a45a8ff 437 @{
bogdanm 0:9b334a45a8ff 438 */
bogdanm 0:9b334a45a8ff 439 typedef struct
bogdanm 0:9b334a45a8ff 440 {
bogdanm 0:9b334a45a8ff 441 __IO uint32_t CFG; /* 0x00 */
bogdanm 0:9b334a45a8ff 442 __IO uint32_t DLY;
bogdanm 0:9b334a45a8ff 443 __IO uint32_t STAT;
bogdanm 0:9b334a45a8ff 444 __IO uint32_t INTENSET;
bogdanm 0:9b334a45a8ff 445 __O uint32_t INTENCLR; /* 0x10 */
bogdanm 0:9b334a45a8ff 446 __I uint32_t RXDAT;
bogdanm 0:9b334a45a8ff 447 __IO uint32_t TXDATCTL;
bogdanm 0:9b334a45a8ff 448 __IO uint32_t TXDAT;
bogdanm 0:9b334a45a8ff 449 __IO uint32_t TXCTRL; /* 0x20 */
bogdanm 0:9b334a45a8ff 450 __IO uint32_t DIV;
bogdanm 0:9b334a45a8ff 451 __I uint32_t INTSTAT;
bogdanm 0:9b334a45a8ff 452 } LPC_SPI_TypeDef;
bogdanm 0:9b334a45a8ff 453 /*@}*/ /* end of group LPC8xx_SPI */
bogdanm 0:9b334a45a8ff 454
bogdanm 0:9b334a45a8ff 455
bogdanm 0:9b334a45a8ff 456 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 0:9b334a45a8ff 457 /** @addtogroup LPC8xx_I2C I2C-Bus Interface
bogdanm 0:9b334a45a8ff 458 @{
bogdanm 0:9b334a45a8ff 459 */
bogdanm 0:9b334a45a8ff 460 typedef struct
bogdanm 0:9b334a45a8ff 461 {
bogdanm 0:9b334a45a8ff 462 __IO uint32_t CFG; /* 0x00 */
bogdanm 0:9b334a45a8ff 463 __IO uint32_t STAT;
bogdanm 0:9b334a45a8ff 464 __IO uint32_t INTENSET;
bogdanm 0:9b334a45a8ff 465 __O uint32_t INTENCLR;
bogdanm 0:9b334a45a8ff 466 __IO uint32_t TIMEOUT; /* 0x10 */
bogdanm 0:9b334a45a8ff 467 __IO uint32_t DIV;
bogdanm 0:9b334a45a8ff 468 __IO uint32_t INTSTAT;
bogdanm 0:9b334a45a8ff 469 uint32_t Reserved0[1];
bogdanm 0:9b334a45a8ff 470 __IO uint32_t MSTCTL; /* 0x20 */
bogdanm 0:9b334a45a8ff 471 __IO uint32_t MSTTIME;
bogdanm 0:9b334a45a8ff 472 __IO uint32_t MSTDAT;
bogdanm 0:9b334a45a8ff 473 uint32_t Reserved1[5];
bogdanm 0:9b334a45a8ff 474 __IO uint32_t SLVCTL; /* 0x40 */
bogdanm 0:9b334a45a8ff 475 __IO uint32_t SLVDAT;
bogdanm 0:9b334a45a8ff 476 __IO uint32_t SLVADR0;
bogdanm 0:9b334a45a8ff 477 __IO uint32_t SLVADR1;
bogdanm 0:9b334a45a8ff 478 __IO uint32_t SLVADR2; /* 0x50 */
bogdanm 0:9b334a45a8ff 479 __IO uint32_t SLVADR3;
bogdanm 0:9b334a45a8ff 480 __IO uint32_t SLVQUAL0;
bogdanm 0:9b334a45a8ff 481 uint32_t Reserved2[9];
bogdanm 0:9b334a45a8ff 482 __I uint32_t MONRXDAT; /* 0x80 */
bogdanm 0:9b334a45a8ff 483 } LPC_I2C_TypeDef;
bogdanm 0:9b334a45a8ff 484
bogdanm 0:9b334a45a8ff 485 /*@}*/ /* end of group LPC8xx_I2C */
bogdanm 0:9b334a45a8ff 486
bogdanm 0:9b334a45a8ff 487 /**
bogdanm 0:9b334a45a8ff 488 * @brief State Configurable Timer (SCT) (SCT)
bogdanm 0:9b334a45a8ff 489 */
bogdanm 0:9b334a45a8ff 490
bogdanm 0:9b334a45a8ff 491 /**
bogdanm 0:9b334a45a8ff 492 * @brief Product name title=UM10430 Chapter title=LPC8xx State Configurable Timer (SCT) Modification date=1/18/2011 Major revision=0 Minor revision=7 (SCT)
bogdanm 0:9b334a45a8ff 493 */
bogdanm 0:9b334a45a8ff 494
bogdanm 0:9b334a45a8ff 495 #define CONFIG_SCT_nEV (6) /* Number of events */
bogdanm 0:9b334a45a8ff 496 #define CONFIG_SCT_nRG (5) /* Number of match/compare registers */
bogdanm 0:9b334a45a8ff 497 #define CONFIG_SCT_nOU (4) /* Number of outputs */
bogdanm 0:9b334a45a8ff 498
bogdanm 0:9b334a45a8ff 499 typedef struct
bogdanm 0:9b334a45a8ff 500 {
bogdanm 0:9b334a45a8ff 501 __IO uint32_t CONFIG; /* 0x000 Configuration Register */
bogdanm 0:9b334a45a8ff 502 union {
bogdanm 0:9b334a45a8ff 503 __IO uint32_t CTRL_U; /* 0x004 Control Register */
bogdanm 0:9b334a45a8ff 504 struct {
bogdanm 0:9b334a45a8ff 505 __IO uint16_t CTRL_L; /* 0x004 low control register */
bogdanm 0:9b334a45a8ff 506 __IO uint16_t CTRL_H; /* 0x006 high control register */
bogdanm 0:9b334a45a8ff 507 };
bogdanm 0:9b334a45a8ff 508 };
bogdanm 0:9b334a45a8ff 509 __IO uint16_t LIMIT_L; /* 0x008 limit register for counter L */
bogdanm 0:9b334a45a8ff 510 __IO uint16_t LIMIT_H; /* 0x00A limit register for counter H */
bogdanm 0:9b334a45a8ff 511 __IO uint16_t HALT_L; /* 0x00C halt register for counter L */
bogdanm 0:9b334a45a8ff 512 __IO uint16_t HALT_H; /* 0x00E halt register for counter H */
bogdanm 0:9b334a45a8ff 513 __IO uint16_t STOP_L; /* 0x010 stop register for counter L */
bogdanm 0:9b334a45a8ff 514 __IO uint16_t STOP_H; /* 0x012 stop register for counter H */
bogdanm 0:9b334a45a8ff 515 __IO uint16_t START_L; /* 0x014 start register for counter L */
bogdanm 0:9b334a45a8ff 516 __IO uint16_t START_H; /* 0x016 start register for counter H */
bogdanm 0:9b334a45a8ff 517 uint32_t RESERVED1[10]; /* 0x018-0x03C reserved */
bogdanm 0:9b334a45a8ff 518 union {
bogdanm 0:9b334a45a8ff 519 __IO uint32_t COUNT_U; /* 0x040 counter register */
bogdanm 0:9b334a45a8ff 520 struct {
bogdanm 0:9b334a45a8ff 521 __IO uint16_t COUNT_L; /* 0x040 counter register for counter L */
bogdanm 0:9b334a45a8ff 522 __IO uint16_t COUNT_H; /* 0x042 counter register for counter H */
bogdanm 0:9b334a45a8ff 523 };
bogdanm 0:9b334a45a8ff 524 };
bogdanm 0:9b334a45a8ff 525 __IO uint16_t STATE_L; /* 0x044 state register for counter L */
bogdanm 0:9b334a45a8ff 526 __IO uint16_t STATE_H; /* 0x046 state register for counter H */
bogdanm 0:9b334a45a8ff 527 __I uint32_t INPUT; /* 0x048 input register */
bogdanm 0:9b334a45a8ff 528 __IO uint16_t REGMODE_L; /* 0x04C match - capture registers mode register L */
bogdanm 0:9b334a45a8ff 529 __IO uint16_t REGMODE_H; /* 0x04E match - capture registers mode register H */
bogdanm 0:9b334a45a8ff 530 __IO uint32_t OUTPUT; /* 0x050 output register */
bogdanm 0:9b334a45a8ff 531 __IO uint32_t OUTPUTDIRCTRL; /* 0x054 Output counter direction Control Register */
bogdanm 0:9b334a45a8ff 532 __IO uint32_t RES; /* 0x058 conflict resolution register */
bogdanm 0:9b334a45a8ff 533 uint32_t RESERVED2[37]; /* 0x05C-0x0EC reserved */
bogdanm 0:9b334a45a8ff 534 __IO uint32_t EVEN; /* 0x0F0 event enable register */
bogdanm 0:9b334a45a8ff 535 __IO uint32_t EVFLAG; /* 0x0F4 event flag register */
bogdanm 0:9b334a45a8ff 536 __IO uint32_t CONEN; /* 0x0F8 conflict enable register */
bogdanm 0:9b334a45a8ff 537 __IO uint32_t CONFLAG; /* 0x0FC conflict flag register */
bogdanm 0:9b334a45a8ff 538
bogdanm 0:9b334a45a8ff 539 union {
bogdanm 0:9b334a45a8ff 540 __IO union { /* 0x100-... Match / Capture value */
bogdanm 0:9b334a45a8ff 541 uint32_t U; /* SCTMATCH[i].U Unified 32-bit register */
bogdanm 0:9b334a45a8ff 542 struct {
bogdanm 0:9b334a45a8ff 543 uint16_t L; /* SCTMATCH[i].L Access to L value */
bogdanm 0:9b334a45a8ff 544 uint16_t H; /* SCTMATCH[i].H Access to H value */
bogdanm 0:9b334a45a8ff 545 };
bogdanm 0:9b334a45a8ff 546 } MATCH[CONFIG_SCT_nRG];
bogdanm 0:9b334a45a8ff 547 __I union {
bogdanm 0:9b334a45a8ff 548 uint32_t U; /* SCTCAP[i].U Unified 32-bit register */
bogdanm 0:9b334a45a8ff 549 struct {
bogdanm 0:9b334a45a8ff 550 uint16_t L; /* SCTCAP[i].L Access to H value */
bogdanm 0:9b334a45a8ff 551 uint16_t H; /* SCTCAP[i].H Access to H value */
bogdanm 0:9b334a45a8ff 552 };
bogdanm 0:9b334a45a8ff 553 } CAP[CONFIG_SCT_nRG];
bogdanm 0:9b334a45a8ff 554 };
bogdanm 0:9b334a45a8ff 555
bogdanm 0:9b334a45a8ff 556
bogdanm 0:9b334a45a8ff 557 uint32_t RESERVED3[32-CONFIG_SCT_nRG]; /* ...-0x17C reserved */
bogdanm 0:9b334a45a8ff 558
bogdanm 0:9b334a45a8ff 559 union {
bogdanm 0:9b334a45a8ff 560 __IO uint16_t MATCH_L[CONFIG_SCT_nRG]; /* 0x180-... Match Value L counter */
bogdanm 0:9b334a45a8ff 561 __I uint16_t CAP_L[CONFIG_SCT_nRG]; /* 0x180-... Capture Value L counter */
bogdanm 0:9b334a45a8ff 562 };
bogdanm 0:9b334a45a8ff 563 uint16_t RESERVED4[32-CONFIG_SCT_nRG]; /* ...-0x1BE reserved */
bogdanm 0:9b334a45a8ff 564 union {
bogdanm 0:9b334a45a8ff 565 __IO uint16_t MATCH_H[CONFIG_SCT_nRG]; /* 0x1C0-... Match Value H counter */
bogdanm 0:9b334a45a8ff 566 __I uint16_t CAP_H[CONFIG_SCT_nRG]; /* 0x1C0-... Capture Value H counter */
bogdanm 0:9b334a45a8ff 567 };
bogdanm 0:9b334a45a8ff 568
bogdanm 0:9b334a45a8ff 569 uint16_t RESERVED5[32-CONFIG_SCT_nRG]; /* ...-0x1FE reserved */
bogdanm 0:9b334a45a8ff 570
bogdanm 0:9b334a45a8ff 571
bogdanm 0:9b334a45a8ff 572 union {
bogdanm 0:9b334a45a8ff 573 __IO union { /* 0x200-... Match Reload / Capture Control value */
bogdanm 0:9b334a45a8ff 574 uint32_t U; /* SCTMATCHREL[i].U Unified 32-bit register */
bogdanm 0:9b334a45a8ff 575 struct {
bogdanm 0:9b334a45a8ff 576 uint16_t L; /* SCTMATCHREL[i].L Access to L value */
bogdanm 0:9b334a45a8ff 577 uint16_t H; /* SCTMATCHREL[i].H Access to H value */
bogdanm 0:9b334a45a8ff 578 };
bogdanm 0:9b334a45a8ff 579 } MATCHREL[CONFIG_SCT_nRG];
bogdanm 0:9b334a45a8ff 580 __IO union {
bogdanm 0:9b334a45a8ff 581 uint32_t U; /* SCTCAPCTRL[i].U Unified 32-bit register */
bogdanm 0:9b334a45a8ff 582 struct {
bogdanm 0:9b334a45a8ff 583 uint16_t L; /* SCTCAPCTRL[i].L Access to H value */
bogdanm 0:9b334a45a8ff 584 uint16_t H; /* SCTCAPCTRL[i].H Access to H value */
bogdanm 0:9b334a45a8ff 585 };
bogdanm 0:9b334a45a8ff 586 } CAPCTRL[CONFIG_SCT_nRG];
bogdanm 0:9b334a45a8ff 587 };
bogdanm 0:9b334a45a8ff 588
bogdanm 0:9b334a45a8ff 589 uint32_t RESERVED6[32-CONFIG_SCT_nRG]; /* ...-0x27C reserved */
bogdanm 0:9b334a45a8ff 590
bogdanm 0:9b334a45a8ff 591 union {
bogdanm 0:9b334a45a8ff 592 __IO uint16_t MATCHREL_L[CONFIG_SCT_nRG]; /* 0x280-... Match Reload value L counter */
bogdanm 0:9b334a45a8ff 593 __IO uint16_t CAPCTRL_L[CONFIG_SCT_nRG]; /* 0x280-... Capture Control value L counter */
bogdanm 0:9b334a45a8ff 594 };
bogdanm 0:9b334a45a8ff 595 uint16_t RESERVED7[32-CONFIG_SCT_nRG]; /* ...-0x2BE reserved */
bogdanm 0:9b334a45a8ff 596 union {
bogdanm 0:9b334a45a8ff 597 __IO uint16_t MATCHREL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Match Reload value H counter */
bogdanm 0:9b334a45a8ff 598 __IO uint16_t CAPCTRL_H[CONFIG_SCT_nRG]; /* 0x2C0-... Capture Control value H counter */
bogdanm 0:9b334a45a8ff 599 };
bogdanm 0:9b334a45a8ff 600 uint16_t RESERVED8[32-CONFIG_SCT_nRG]; /* ...-0x2FE reserved */
bogdanm 0:9b334a45a8ff 601
bogdanm 0:9b334a45a8ff 602 __IO struct { /* 0x300-0x3FC SCTEVENT[i].STATE / SCTEVENT[i].CTRL*/
bogdanm 0:9b334a45a8ff 603 uint32_t STATE; /* Event State Register */
bogdanm 0:9b334a45a8ff 604 uint32_t CTRL; /* Event Control Register */
bogdanm 0:9b334a45a8ff 605 } EVENT[CONFIG_SCT_nEV];
bogdanm 0:9b334a45a8ff 606
bogdanm 0:9b334a45a8ff 607 uint32_t RESERVED9[128-2*CONFIG_SCT_nEV]; /* ...-0x4FC reserved */
bogdanm 0:9b334a45a8ff 608
bogdanm 0:9b334a45a8ff 609 __IO struct { /* 0x500-0x57C SCTOUT[i].SET / SCTOUT[i].CLR */
bogdanm 0:9b334a45a8ff 610 uint32_t SET; /* Output n Set Register */
bogdanm 0:9b334a45a8ff 611 uint32_t CLR; /* Output n Clear Register */
bogdanm 0:9b334a45a8ff 612 } OUT[CONFIG_SCT_nOU];
bogdanm 0:9b334a45a8ff 613
bogdanm 0:9b334a45a8ff 614 uint32_t RESERVED10[191-2*CONFIG_SCT_nOU]; /* ...-0x7F8 reserved */
bogdanm 0:9b334a45a8ff 615
bogdanm 0:9b334a45a8ff 616 __I uint32_t MODULECONTENT; /* 0x7FC Module Content */
bogdanm 0:9b334a45a8ff 617
bogdanm 0:9b334a45a8ff 618 } LPC_SCT_TypeDef;
bogdanm 0:9b334a45a8ff 619 /*@}*/ /* end of group LPC8xx_SCT */
bogdanm 0:9b334a45a8ff 620
bogdanm 0:9b334a45a8ff 621
bogdanm 0:9b334a45a8ff 622 /*------------- Watchdog Timer (WWDT) -----------------------------------------*/
bogdanm 0:9b334a45a8ff 623 /** @addtogroup LPC8xx_WDT LPC8xx WatchDog Timer
bogdanm 0:9b334a45a8ff 624 @{
bogdanm 0:9b334a45a8ff 625 */
bogdanm 0:9b334a45a8ff 626 typedef struct
bogdanm 0:9b334a45a8ff 627 {
bogdanm 0:9b334a45a8ff 628 __IO uint32_t MOD; /*!< Offset: 0x000 Watchdog mode register (R/W) */
bogdanm 0:9b334a45a8ff 629 __IO uint32_t TC; /*!< Offset: 0x004 Watchdog timer constant register (R/W) */
bogdanm 0:9b334a45a8ff 630 __O uint32_t FEED; /*!< Offset: 0x008 Watchdog feed sequence register (W) */
bogdanm 0:9b334a45a8ff 631 __I uint32_t TV; /*!< Offset: 0x00C Watchdog timer value register (R) */
bogdanm 0:9b334a45a8ff 632 uint32_t RESERVED; /*!< Offset: 0x010 RESERVED */
bogdanm 0:9b334a45a8ff 633 __IO uint32_t WARNINT; /*!< Offset: 0x014 Watchdog timer warning int. register (R/W) */
bogdanm 0:9b334a45a8ff 634 __IO uint32_t WINDOW; /*!< Offset: 0x018 Watchdog timer window value register (R/W) */
bogdanm 0:9b334a45a8ff 635 } LPC_WWDT_TypeDef;
bogdanm 0:9b334a45a8ff 636 /*@}*/ /* end of group LPC8xx_WDT */
bogdanm 0:9b334a45a8ff 637
bogdanm 0:9b334a45a8ff 638
bogdanm 0:9b334a45a8ff 639 #if defined ( __CC_ARM )
bogdanm 0:9b334a45a8ff 640 #pragma no_anon_unions
bogdanm 0:9b334a45a8ff 641 #endif
bogdanm 0:9b334a45a8ff 642
bogdanm 0:9b334a45a8ff 643 /******************************************************************************/
bogdanm 0:9b334a45a8ff 644 /* Peripheral memory map */
bogdanm 0:9b334a45a8ff 645 /******************************************************************************/
bogdanm 0:9b334a45a8ff 646 /* Base addresses */
bogdanm 0:9b334a45a8ff 647 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 0:9b334a45a8ff 648 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 0:9b334a45a8ff 649 #define LPC_ROM_BASE (0x1FFF0000UL)
bogdanm 0:9b334a45a8ff 650 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 0:9b334a45a8ff 651 #define LPC_AHB_BASE (0x50000000UL)
bogdanm 0:9b334a45a8ff 652
bogdanm 0:9b334a45a8ff 653 /* APB0 peripherals */
bogdanm 0:9b334a45a8ff 654 #define LPC_WWDT_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 0:9b334a45a8ff 655 #define LPC_MRT_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 0:9b334a45a8ff 656 #define LPC_WKT_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 0:9b334a45a8ff 657 #define LPC_SWM_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 0:9b334a45a8ff 658 #define LPC_PMU_BASE (LPC_APB0_BASE + 0x20000)
bogdanm 0:9b334a45a8ff 659 #define LPC_CMP_BASE (LPC_APB0_BASE + 0x24000)
bogdanm 0:9b334a45a8ff 660
bogdanm 0:9b334a45a8ff 661 #define LPC_FLASHCTRL_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 0:9b334a45a8ff 662 #define LPC_IOCON_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 0:9b334a45a8ff 663 #define LPC_SYSCON_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 0:9b334a45a8ff 664 #define LPC_I2C_BASE (LPC_APB0_BASE + 0x50000)
bogdanm 0:9b334a45a8ff 665 #define LPC_SPI0_BASE (LPC_APB0_BASE + 0x58000)
bogdanm 0:9b334a45a8ff 666 #define LPC_SPI1_BASE (LPC_APB0_BASE + 0x5C000)
bogdanm 0:9b334a45a8ff 667 #define LPC_USART0_BASE (LPC_APB0_BASE + 0x64000)
bogdanm 0:9b334a45a8ff 668 #define LPC_USART1_BASE (LPC_APB0_BASE + 0x68000)
bogdanm 0:9b334a45a8ff 669 #define LPC_USART2_BASE (LPC_APB0_BASE + 0x6C000)
bogdanm 0:9b334a45a8ff 670
bogdanm 0:9b334a45a8ff 671 /* AHB peripherals */
bogdanm 0:9b334a45a8ff 672 #define LPC_CRC_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 0:9b334a45a8ff 673 #define LPC_SCT_BASE (LPC_AHB_BASE + 0x04000)
bogdanm 0:9b334a45a8ff 674
bogdanm 0:9b334a45a8ff 675 #define LPC_GPIO_PORT_BASE (0xA0000000)
bogdanm 0:9b334a45a8ff 676 #define LPC_PIN_INT_BASE (LPC_GPIO_PORT_BASE + 0x4000)
bogdanm 0:9b334a45a8ff 677
bogdanm 0:9b334a45a8ff 678 /******************************************************************************/
bogdanm 0:9b334a45a8ff 679 /* Peripheral declaration */
bogdanm 0:9b334a45a8ff 680 /******************************************************************************/
bogdanm 0:9b334a45a8ff 681 #define LPC_WWDT ((LPC_WWDT_TypeDef *) LPC_WWDT_BASE )
bogdanm 0:9b334a45a8ff 682 #define LPC_MRT ((LPC_MRT_TypeDef *) LPC_MRT_BASE )
bogdanm 0:9b334a45a8ff 683
bogdanm 0:9b334a45a8ff 684
bogdanm 0:9b334a45a8ff 685 #define LPC_WKT ((LPC_WKT_TypeDef *) LPC_WKT_BASE )
bogdanm 0:9b334a45a8ff 686 #define LPC_SWM ((LPC_SWM_TypeDef *) LPC_SWM_BASE )
bogdanm 0:9b334a45a8ff 687 #define LPC_PMU ((LPC_PMU_TypeDef *) LPC_PMU_BASE )
bogdanm 0:9b334a45a8ff 688 #define LPC_CMP ((LPC_CMP_TypeDef *) LPC_CMP_BASE )
bogdanm 0:9b334a45a8ff 689
bogdanm 0:9b334a45a8ff 690 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_TypeDef *) LPC_FLASHCTRL_BASE )
bogdanm 0:9b334a45a8ff 691 #define LPC_IOCON ((LPC_IOCON_TypeDef *) LPC_IOCON_BASE )
bogdanm 0:9b334a45a8ff 692 #define LPC_SYSCON ((LPC_SYSCON_TypeDef *) LPC_SYSCON_BASE)
bogdanm 0:9b334a45a8ff 693 #define LPC_I2C ((LPC_I2C_TypeDef *) LPC_I2C_BASE )
bogdanm 0:9b334a45a8ff 694 #define LPC_SPI0 ((LPC_SPI_TypeDef *) LPC_SPI0_BASE )
bogdanm 0:9b334a45a8ff 695 #define LPC_SPI1 ((LPC_SPI_TypeDef *) LPC_SPI1_BASE )
bogdanm 0:9b334a45a8ff 696 #define LPC_USART0 ((LPC_USART_TypeDef *) LPC_USART0_BASE )
bogdanm 0:9b334a45a8ff 697 #define LPC_USART1 ((LPC_USART_TypeDef *) LPC_USART1_BASE )
bogdanm 0:9b334a45a8ff 698 #define LPC_USART2 ((LPC_USART_TypeDef *) LPC_USART2_BASE )
bogdanm 0:9b334a45a8ff 699
bogdanm 0:9b334a45a8ff 700 #define LPC_CRC ((LPC_CRC_TypeDef *) LPC_CRC_BASE )
bogdanm 0:9b334a45a8ff 701 #define LPC_SCT ((LPC_SCT_TypeDef *) LPC_SCT_BASE )
bogdanm 0:9b334a45a8ff 702
bogdanm 0:9b334a45a8ff 703 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_TypeDef *) LPC_GPIO_PORT_BASE )
bogdanm 0:9b334a45a8ff 704 #define LPC_PIN_INT ((LPC_PIN_INT_TypeDef *) LPC_PIN_INT_BASE )
bogdanm 0:9b334a45a8ff 705
bogdanm 0:9b334a45a8ff 706 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 707 }
bogdanm 0:9b334a45a8ff 708 #endif
bogdanm 0:9b334a45a8ff 709
bogdanm 0:9b334a45a8ff 710 #endif /* __LPC8xx_H__ */