Umar Naeem / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by Umar Naeem

targets/TARGET_Maxim/TARGET_MAX32630/mxc/pmu.h@165:2dd56e6daeec, 2017-05-23 (annotated)

Committer:
ranaumarnaeem
Date:
Tue May 23 12:54:50 2017 +0000
Revision:
165:2dd56e6daeec
Parent:
157:ff67d9f36b67 
jhjg

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 157:ff67d9f36b67 1 /**
<> 157:ff67d9f36b67 2 * @file
<> 157:ff67d9f36b67 3 * @brief Registers, Bit Masks and Bit Positions for the PMU module.
<> 157:ff67d9f36b67 4 */
<> 157:ff67d9f36b67 5 /* ****************************************************************************
<> 157:ff67d9f36b67 6 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 157:ff67d9f36b67 7 *
<> 157:ff67d9f36b67 8 * Permission is hereby granted, free of charge, to any person obtaining a
<> 157:ff67d9f36b67 9 * copy of this software and associated documentation files (the "Software"),
<> 157:ff67d9f36b67 10 * to deal in the Software without restriction, including without limitation
<> 157:ff67d9f36b67 11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 157:ff67d9f36b67 12 * and/or sell copies of the Software, and to permit persons to whom the
<> 157:ff67d9f36b67 13 * Software is furnished to do so, subject to the following conditions:
<> 157:ff67d9f36b67 14 *
<> 157:ff67d9f36b67 15 * The above copyright notice and this permission notice shall be included
<> 157:ff67d9f36b67 16 * in all copies or substantial portions of the Software.
<> 157:ff67d9f36b67 17 *
<> 157:ff67d9f36b67 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 157:ff67d9f36b67 19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 157:ff67d9f36b67 20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 157:ff67d9f36b67 21 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 157:ff67d9f36b67 22 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 157:ff67d9f36b67 23 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 157:ff67d9f36b67 24 * OTHER DEALINGS IN THE SOFTWARE.
<> 157:ff67d9f36b67 25 *
<> 157:ff67d9f36b67 26 * Except as contained in this notice, the name of Maxim Integrated
<> 157:ff67d9f36b67 27 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 157:ff67d9f36b67 28 * Products, Inc. Branding Policy.
<> 157:ff67d9f36b67 29 *
<> 157:ff67d9f36b67 30 * The mere transfer of this software does not imply any licenses
<> 157:ff67d9f36b67 31 * of trade secrets, proprietary technology, copyrights, patents,
<> 157:ff67d9f36b67 32 * trademarks, maskwork rights, or any other form of intellectual
<> 157:ff67d9f36b67 33 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 157:ff67d9f36b67 34 * ownership rights.
<> 157:ff67d9f36b67 35 *
<> 157:ff67d9f36b67 36 * $Date: 2016-10-10 19:24:21 -0500 (Mon, 10 Oct 2016) $
<> 157:ff67d9f36b67 37 * $Revision: 24667 $
<> 157:ff67d9f36b67 38 *
<> 157:ff67d9f36b67 39 **************************************************************************** */
<> 157:ff67d9f36b67 40
<> 157:ff67d9f36b67 41 /* Define to prevent redundant inclusion */
<> 157:ff67d9f36b67 42 #ifndef _PMU_H_
<> 157:ff67d9f36b67 43 #define _PMU_H_
<> 157:ff67d9f36b67 44
<> 157:ff67d9f36b67 45 /* **** Includes **** */
<> 157:ff67d9f36b67 46 #include "pmu_regs.h"
<> 157:ff67d9f36b67 47
<> 157:ff67d9f36b67 48 #ifdef __cplusplus
<> 157:ff67d9f36b67 49 extern "C" {
<> 157:ff67d9f36b67 50 #endif
<> 157:ff67d9f36b67 51
<> 157:ff67d9f36b67 52 /**
<> 157:ff67d9f36b67 53 * @ingroup periphlibs
<> 157:ff67d9f36b67 54 * @defgroup pmuGroup Peripheral Management Unit
<> 157:ff67d9f36b67 55 * @brief Peripheral Management Unit (PMU) Interface.
<> 157:ff67d9f36b67 56 * @{
<> 157:ff67d9f36b67 57 */
<> 157:ff67d9f36b67 58
<> 157:ff67d9f36b67 59 /**
<> 157:ff67d9f36b67 60 * Enum type for the clock scale used for the PMU timeout clock.
<> 157:ff67d9f36b67 61 */
<> 157:ff67d9f36b67 62 typedef enum {
<> 157:ff67d9f36b67 63 PMU_PS_SEL_DISABLE = MXC_V_PMU_CFG_PS_SEL_DISABLE, /**< Timeout disabled */
<> 157:ff67d9f36b67 64 PMU_PS_SEL_DIV_2_8 = MXC_V_PMU_CFG_PS_SEL_DIV_2_8, /**< Timeout clk = PMU clock / 2^8 = 256 */
<> 157:ff67d9f36b67 65 PMU_PS_SEL_DIV_2_16 = MXC_V_PMU_CFG_PS_SEL_DIV_2_16, /**< Timeout clk = PMU clock / 2^16 = 65536 */
<> 157:ff67d9f36b67 66 PMU_PS_SEL_DIV_2_24 = MXC_V_PMU_CFG_PS_SEL_DIV_2_24 /**< Timeout clk = PMU clock / 2^24 = 16777216 */
<> 157:ff67d9f36b67 67 }pmu_ps_sel_t;
<> 157:ff67d9f36b67 68
<> 157:ff67d9f36b67 69 /**
<> 157:ff67d9f36b67 70 * Enumeration type for the number of clk ticks for the timeout duration.
<> 157:ff67d9f36b67 71 */
<> 157:ff67d9f36b67 72 typedef enum {
<> 157:ff67d9f36b67 73 PMU_TO_SEL_TICKS_4 = MXC_V_PMU_CFG_TO_SEL_TICKS_4, /**< timeout = 4 * Timeout clk period */
<> 157:ff67d9f36b67 74 PMU_TO_SEL_TICKS_8 = MXC_V_PMU_CFG_TO_SEL_TICKS_8, /**< timeout = 8 * Timeout clk period */
<> 157:ff67d9f36b67 75 PMU_TO_SEL_TICKS_16 = MXC_V_PMU_CFG_TO_SEL_TICKS_16, /**< timeout = 16 * Timeout clk period */
<> 157:ff67d9f36b67 76 PMU_TO_SEL_TICKS_32 = MXC_V_PMU_CFG_TO_SEL_TICKS_32, /**< timeout = 32 * Timeout clk period */
<> 157:ff67d9f36b67 77 PMU_TO_SEL_TICKS_64 = MXC_V_PMU_CFG_TO_SEL_TICKS_64, /**< timeout = 64 * Timeout clk period */
<> 157:ff67d9f36b67 78 PMU_TO_SEL_TICKS_128 = MXC_V_PMU_CFG_TO_SEL_TICKS_128, /**< timeout = 128 * Timeout clk period */
<> 157:ff67d9f36b67 79 PMU_TO_SEL_TICKS_256 = MXC_V_PMU_CFG_TO_SEL_TICKS_256, /**< timeout = 256 * Timeout clk period */
<> 157:ff67d9f36b67 80 PMU_TO_SEL_TICKS_512 = MXC_V_PMU_CFG_TO_SEL_TICKS_512 /**< timeout = 512 * Timeout clk period */
<> 157:ff67d9f36b67 81 }pmu_to_sel_t;
<> 157:ff67d9f36b67 82
<> 157:ff67d9f36b67 83 /*
<> 157:ff67d9f36b67 84 * The macros like the one below are designed to help build static PMU programs
<> 157:ff67d9f36b67 85 * as arrays of 32bit words.
<> 157:ff67d9f36b67 86 */
<> 157:ff67d9f36b67 87 #define PMU_IS(interrupt, stop) ((!!interrupt) << PMU_INT_POS) | ((!!stop) << PMU_STOP_POS)
<> 157:ff67d9f36b67 88 /*
<> 157:ff67d9f36b67 89 * Structure type to build a PMU Move Op Code.
<> 157:ff67d9f36b67 90 */
<> 157:ff67d9f36b67 91 typedef struct pmu_move_des_t {
<> 157:ff67d9f36b67 92 uint32_t op_code : 3; /* 0x0 */
<> 157:ff67d9f36b67 93 uint32_t interrupt : 1;
<> 157:ff67d9f36b67 94 uint32_t stop : 1;
<> 157:ff67d9f36b67 95 uint32_t read_size : 2;
<> 157:ff67d9f36b67 96 uint32_t read_inc : 1;
<> 157:ff67d9f36b67 97 uint32_t write_size : 2;
<> 157:ff67d9f36b67 98 uint32_t write_inc : 1;
<> 157:ff67d9f36b67 99 uint32_t cont : 1;
<> 157:ff67d9f36b67 100 uint32_t length : 20;
<> 157:ff67d9f36b67 101
<> 157:ff67d9f36b67 102 uint32_t write_address;
<> 157:ff67d9f36b67 103 uint32_t read_address;
<> 157:ff67d9f36b67 104 } pmu_move_des_t;
<> 157:ff67d9f36b67 105 #define PMU_MOVE(i, s, rs, ri, ws, wi, c, length, wa, ra) \
<> 157:ff67d9f36b67 106 (PMU_MOVE_OP | PMU_IS(i,s) | ((rs & 3) << PMU_MOVE_READS_POS) | ((!!ri) << PMU_MOVE_READI_POS) | \
<> 157:ff67d9f36b67 107 ((ws & 3) << PMU_MOVE_WRITES_POS) | ((!!wi) << PMU_MOVE_WRITEI_POS) | ((!!c) << PMU_MOVE_CONT_POS) | ((length & 0xFFFFF) << PMU_MOVE_LEN_POS)), wa, ra
<> 157:ff67d9f36b67 108
<> 157:ff67d9f36b67 109 /* new_value = value | (old_value & ~ mask) */
<> 157:ff67d9f36b67 110 typedef struct pmu_write_des_t {
<> 157:ff67d9f36b67 111 uint32_t op_code : 3; /* 0x1 */
<> 157:ff67d9f36b67 112 uint32_t interrupt : 1;
<> 157:ff67d9f36b67 113 uint32_t stop : 1;
<> 157:ff67d9f36b67 114 uint32_t : 3;
<> 157:ff67d9f36b67 115 uint32_t write_method : 4;
<> 157:ff67d9f36b67 116 uint32_t : 20;
<> 157:ff67d9f36b67 117
<> 157:ff67d9f36b67 118 uint32_t write_address;
<> 157:ff67d9f36b67 119 uint32_t value;
<> 157:ff67d9f36b67 120 uint32_t mask;
<> 157:ff67d9f36b67 121 } pmu_write_des_t;
<> 157:ff67d9f36b67 122 #define PMU_WRITE(i, s, wm, a, v, m) (PMU_WRITE_OP | PMU_IS(i,s) | ((wm & 0xF) << PMU_WRITE_METHOD_POS)), a, v, m
<> 157:ff67d9f36b67 123
<> 157:ff67d9f36b67 124 typedef struct pmu_wait_des_t {
<> 157:ff67d9f36b67 125 uint32_t op_code : 3; /* 0x2 */
<> 157:ff67d9f36b67 126 uint32_t interrupt : 1;
<> 157:ff67d9f36b67 127 uint32_t stop : 1;
<> 157:ff67d9f36b67 128 uint32_t wait : 1;
<> 157:ff67d9f36b67 129 uint32_t sel : 1;
<> 157:ff67d9f36b67 130 uint32_t : 25;
<> 157:ff67d9f36b67 131
<> 157:ff67d9f36b67 132 uint32_t mask1;
<> 157:ff67d9f36b67 133 uint32_t mask2;
<> 157:ff67d9f36b67 134 uint32_t wait_count;
<> 157:ff67d9f36b67 135 } pmu_wait_des_t;
<> 157:ff67d9f36b67 136 #define PMU_WAIT(i, s, sel, m1, m2, cnt) (PMU_WAIT_OP | PMU_IS(i,s) | ((cnt>0)?(1<<PMU_WAIT_WAIT_POS):0) | ((!!sel) << PMU_WAIT_SEL_POS)), \
<> 157:ff67d9f36b67 137 m1, m2, cnt
<> 157:ff67d9f36b67 138
<> 157:ff67d9f36b67 139 typedef struct pmu_jump_des_t {
<> 157:ff67d9f36b67 140 uint32_t op_code : 3; /* 0x3 */
<> 157:ff67d9f36b67 141 uint32_t interrupt : 1;
<> 157:ff67d9f36b67 142 uint32_t stop : 1;
<> 157:ff67d9f36b67 143 uint32_t : 27;
<> 157:ff67d9f36b67 144
<> 157:ff67d9f36b67 145 uint32_t address;
<> 157:ff67d9f36b67 146 } pmu_jump_des_t;
<> 157:ff67d9f36b67 147 #define PMU_JUMP(i, s, a) (PMU_JUMP_OP | PMU_IS(i,s)), a
<> 157:ff67d9f36b67 148
<> 157:ff67d9f36b67 149 typedef struct pmu_loop_des_t {
<> 157:ff67d9f36b67 150 uint32_t op_code : 3; /* 0x4 */
<> 157:ff67d9f36b67 151 uint32_t interrupt : 1;
<> 157:ff67d9f36b67 152 uint32_t stop : 1;
<> 157:ff67d9f36b67 153 uint32_t sel_counter : 1;
<> 157:ff67d9f36b67 154 uint32_t : 26;
<> 157:ff67d9f36b67 155
<> 157:ff67d9f36b67 156 uint32_t address;
<> 157:ff67d9f36b67 157 } pmu_loop_des_t;
<> 157:ff67d9f36b67 158 #define PMU_LOOP(i, s, c, a) (PMU_LOOP_OP | PMU_IS(i,s) | ((!!c) << PMU_LOOP_SEL_COUNTER_POS)), a
<> 157:ff67d9f36b67 159
<> 157:ff67d9f36b67 160 typedef struct pmu_poll_des_t {
<> 157:ff67d9f36b67 161 uint32_t op_code : 3; /* 0x5 */
<> 157:ff67d9f36b67 162 uint32_t interrupt : 1;
<> 157:ff67d9f36b67 163 uint32_t stop : 1;
<> 157:ff67d9f36b67 164 uint32_t : 2;
<> 157:ff67d9f36b67 165 uint32_t and : 1;
<> 157:ff67d9f36b67 166 uint32_t : 24;
<> 157:ff67d9f36b67 167
<> 157:ff67d9f36b67 168 uint32_t poll_addr;
<> 157:ff67d9f36b67 169 uint32_t data;
<> 157:ff67d9f36b67 170 uint32_t mask;
<> 157:ff67d9f36b67 171 uint32_t poll_interval;
<> 157:ff67d9f36b67 172 } pmu_poll_des_t;
<> 157:ff67d9f36b67 173 #define PMU_POLL(i, s, a, adr, d, m, per) (PMU_POLL_OP | PMU_IS(i,s) | ((!!a) << PMU_POLL_AND_POS)), adr, d, m, per
<> 157:ff67d9f36b67 174
<> 157:ff67d9f36b67 175 typedef struct pmu_branch_des_t {
<> 157:ff67d9f36b67 176 uint32_t op_code : 3; /* 0x6 */
<> 157:ff67d9f36b67 177 uint32_t interrupt : 1;
<> 157:ff67d9f36b67 178 uint32_t stop : 1;
<> 157:ff67d9f36b67 179 uint32_t : 2;
<> 157:ff67d9f36b67 180 uint32_t and : 1;
<> 157:ff67d9f36b67 181 uint32_t type : 3;
<> 157:ff67d9f36b67 182 uint32_t : 21;
<> 157:ff67d9f36b67 183
<> 157:ff67d9f36b67 184 uint32_t poll_addr;
<> 157:ff67d9f36b67 185 uint32_t data;
<> 157:ff67d9f36b67 186 uint32_t mask;
<> 157:ff67d9f36b67 187 uint32_t address;
<> 157:ff67d9f36b67 188 } pmu_branch_des_t;
<> 157:ff67d9f36b67 189 #define PMU_BRANCH(i, s, a, t, adr, d, m, badr) \
<> 157:ff67d9f36b67 190 (PMU_BRANCH_OP | PMU_IS(i,s) | ((!!a) << PMU_BRANCH_AND_POS)| ((t & 7) << PMU_BRANCH_TYPE_POS)), adr, d, m, badr
<> 157:ff67d9f36b67 191
<> 157:ff67d9f36b67 192 typedef struct pmu_transfer_des_t {
<> 157:ff67d9f36b67 193 uint32_t op_code : 3; /* 0x7 */
<> 157:ff67d9f36b67 194 uint32_t interrupt : 1;
<> 157:ff67d9f36b67 195 uint32_t stop : 1;
<> 157:ff67d9f36b67 196 uint32_t read_size : 2;
<> 157:ff67d9f36b67 197 uint32_t read_inc : 1;
<> 157:ff67d9f36b67 198 uint32_t write_size : 2;
<> 157:ff67d9f36b67 199 uint32_t write_inc : 1;
<> 157:ff67d9f36b67 200 uint32_t : 1;
<> 157:ff67d9f36b67 201 uint32_t tx_length : 20;
<> 157:ff67d9f36b67 202
<> 157:ff67d9f36b67 203 uint32_t write_address;
<> 157:ff67d9f36b67 204 uint32_t read_address;
<> 157:ff67d9f36b67 205
<> 157:ff67d9f36b67 206 uint32_t int_mask : 25; /* valid int_mask is from 0 - 24 */
<> 157:ff67d9f36b67 207 uint32_t : 1;
<> 157:ff67d9f36b67 208 uint32_t burst_size : 6;
<> 157:ff67d9f36b67 209 } pmu_transfer_des_t;
<> 157:ff67d9f36b67 210 #define PMU_TRANSFER(i, s, rs, ri, ws, wi, l, wa, ra, imsk, b) \
<> 157:ff67d9f36b67 211 (PMU_TRANSFER_OP | PMU_IS(i,s) | ((rs & 3) << PMU_TX_READS_POS) | ((!!ri) << PMU_TX_READI_POS) | \
<> 157:ff67d9f36b67 212 ((ws & 3) << PMU_TX_WRITES_POS) | ((!!wi) << PMU_TX_WRITEI_POS) | ((l & 0xFFFFF) << PMU_TX_LEN_POS)), wa, ra, \
<> 157:ff67d9f36b67 213 ((imsk) | ((b & 0x3F) << PMU_TX_BS_POS))
<> 157:ff67d9f36b67 214 /**
<> 157:ff67d9f36b67 215 * Callback function type for the PMU.
<> 157:ff67d9f36b67 216 * @details The callback function signature is:
<> 157:ff67d9f36b67 217 * @code
<> 157:ff67d9f36b67 218 * void callback(int status);
<> 157:ff67d9f36b67 219 * @endcode
<> 157:ff67d9f36b67 220 * @p pmu_status - The callback function argument is a status bit
<> 157:ff67d9f36b67 221 * indicating the status of the PMU program. The callback function
<> 157:ff67d9f36b67 222 * will be called for every opcode that has the interrupt bit set.
<> 157:ff67d9f36b67 223 * If NULL, the channel interrupt will not be enabled.
<> 157:ff67d9f36b67 224 */
<> 157:ff67d9f36b67 225 typedef void (*pmu_callback)(int pmu_status);
<> 157:ff67d9f36b67 226
<> 157:ff67d9f36b67 227 /**
<> 157:ff67d9f36b67 228 * @brief Start a PMU program on a channel
<> 157:ff67d9f36b67 229 *
<> 157:ff67d9f36b67 230 * @param[in] channel The channel number to start the PMU program.
<> 157:ff67d9f36b67 231 * @param[in] program_address A pointer to the first opcode of the PMU program.
<> 157:ff67d9f36b67 232 * @param[in] callback A pointer to the callback function or NULL. See pmu_callback() for details.
<> 157:ff67d9f36b67 233 *
<> 157:ff67d9f36b67 234 * @return #E_NO_ERROR if everything is successful, error if unsuccessful.
<> 157:ff67d9f36b67 235 */
<> 157:ff67d9f36b67 236 int PMU_Start(unsigned int channel, const void *program_address, pmu_callback callback);
<> 157:ff67d9f36b67 237
<> 157:ff67d9f36b67 238 /**
<> 157:ff67d9f36b67 239 * @brief Set a loop counter value on a channel
<> 157:ff67d9f36b67 240 * @param channel Channel number to set the value on
<> 157:ff67d9f36b67 241 * @param counter_num Counter number for the channel (0 or 1)
<> 157:ff67d9f36b67 242 * @param value Loop count value
<> 157:ff67d9f36b67 243 * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
<> 157:ff67d9f36b67 244 */
<> 157:ff67d9f36b67 245 int PMU_SetCounter(unsigned int channel, unsigned int counter_num, uint16_t value);
<> 157:ff67d9f36b67 246
<> 157:ff67d9f36b67 247 /**
<> 157:ff67d9f36b67 248 * @brief Stop a running channel. This will clear the enable bit on the channel
<> 157:ff67d9f36b67 249 * and stop the running PMU program at the current opcode. The callback
<> 157:ff67d9f36b67 250 * function is not called.
<> 157:ff67d9f36b67 251 * @param channel Channel to stop
<> 157:ff67d9f36b67 252 */
<> 157:ff67d9f36b67 253 void PMU_Stop(unsigned int channel);
<> 157:ff67d9f36b67 254
<> 157:ff67d9f36b67 255 /**
<> 157:ff67d9f36b67 256 * @brief Function to handle PMU interrupts. This function can be called from
<> 157:ff67d9f36b67 257 * the PMU interrupt service routine, or periodically from the
<> 157:ff67d9f36b67 258 * application if interrupts are not enabled.
<> 157:ff67d9f36b67 259 */
<> 157:ff67d9f36b67 260 void PMU_Handler(void);
<> 157:ff67d9f36b67 261
<> 157:ff67d9f36b67 262 /**
<> 157:ff67d9f36b67 263 * @brief Set the AHB bus operation timeout on a channel
<> 157:ff67d9f36b67 264 * @param channel Selected PMU channel
<> 157:ff67d9f36b67 265 * @param timeoutClkScale Clk scale use for timeout clk
<> 157:ff67d9f36b67 266 * @param timeoutTicks Number of ticks for timeout duration
<> 157:ff67d9f36b67 267 * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
<> 157:ff67d9f36b67 268 */
<> 157:ff67d9f36b67 269 int PMU_SetTimeout(unsigned int channel, pmu_ps_sel_t timeoutClkScale, pmu_to_sel_t timeoutTicks);
<> 157:ff67d9f36b67 270
<> 157:ff67d9f36b67 271 /**
<> 157:ff67d9f36b67 272 * @brief Gets the PMU channel's flags
<> 157:ff67d9f36b67 273 * @param channel Selected PMU channel
<> 157:ff67d9f36b67 274 * @return 0 = flags not set, non-zero = flags
<> 157:ff67d9f36b67 275 */
<> 157:ff67d9f36b67 276 uint32_t PMU_GetFlags(unsigned int channel);
<> 157:ff67d9f36b67 277
<> 157:ff67d9f36b67 278 /**
<> 157:ff67d9f36b67 279 * @brief Clear the PMU channel's flags based on the mask
<> 157:ff67d9f36b67 280 * @param channel Selected PMU channel
<> 157:ff67d9f36b67 281 * @param mask bits of the flags to clear
<> 157:ff67d9f36b67 282 */
<> 157:ff67d9f36b67 283 void PMU_ClearFlags(unsigned int channel, unsigned int mask);
<> 157:ff67d9f36b67 284
<> 157:ff67d9f36b67 285 /**
<> 157:ff67d9f36b67 286 * @brief Determines if the PMU channel is running
<> 157:ff67d9f36b67 287 * @param channel Selected PMU channel
<> 157:ff67d9f36b67 288 * @return 0 - channel is off
<> 157:ff67d9f36b67 289 * @return non-zero = channel is running
<> 157:ff67d9f36b67 290 */
<> 157:ff67d9f36b67 291 uint32_t PMU_IsActive(unsigned int channel);
<> 157:ff67d9f36b67 292
<> 157:ff67d9f36b67 293 /**@} end of group pmuGroup*/
<> 157:ff67d9f36b67 294
<> 157:ff67d9f36b67 295 #ifdef __cplusplus
<> 157:ff67d9f36b67 296 }
<> 157:ff67d9f36b67 297 #endif
<> 157:ff67d9f36b67 298
<> 157:ff67d9f36b67 299 #endif /* _PMU_H_ */