Umar Naeem / mbed-dev

mbed library sources. Supersedes mbed-src.

Fork of mbed-dev by Umar Naeem

cmsis/core_sc300.h@165:2dd56e6daeec, 2017-05-23 (annotated)

Committer:
ranaumarnaeem
Date:
Tue May 23 12:54:50 2017 +0000
Revision:
165:2dd56e6daeec
Parent:
152:9a67f0b066fc 
jhjg

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 25:ac5b0a371348 1 /**************************************************************************//**
mbed_official 25:ac5b0a371348 2 * @file core_sc300.h
mbed_official 25:ac5b0a371348 3 * @brief CMSIS SC300 Core Peripheral Access Layer Header File
mbed_official 25:ac5b0a371348 4 * @version V4.10
mbed_official 25:ac5b0a371348 5 * @date 18. March 2015
mbed_official 25:ac5b0a371348 6 *
mbed_official 25:ac5b0a371348 7 * @note
mbed_official 25:ac5b0a371348 8 *
mbed_official 25:ac5b0a371348 9 ******************************************************************************/
mbed_official 25:ac5b0a371348 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
mbed_official 25:ac5b0a371348 11
mbed_official 25:ac5b0a371348 12 All rights reserved.
mbed_official 25:ac5b0a371348 13 Redistribution and use in source and binary forms, with or without
mbed_official 25:ac5b0a371348 14 modification, are permitted provided that the following conditions are met:
mbed_official 25:ac5b0a371348 15 - Redistributions of source code must retain the above copyright
mbed_official 25:ac5b0a371348 16 notice, this list of conditions and the following disclaimer.
mbed_official 25:ac5b0a371348 17 - Redistributions in binary form must reproduce the above copyright
mbed_official 25:ac5b0a371348 18 notice, this list of conditions and the following disclaimer in the
mbed_official 25:ac5b0a371348 19 documentation and/or other materials provided with the distribution.
mbed_official 25:ac5b0a371348 20 - Neither the name of ARM nor the names of its contributors may be used
mbed_official 25:ac5b0a371348 21 to endorse or promote products derived from this software without
mbed_official 25:ac5b0a371348 22 specific prior written permission.
mbed_official 25:ac5b0a371348 23 *
mbed_official 25:ac5b0a371348 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 25:ac5b0a371348 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 25:ac5b0a371348 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mbed_official 25:ac5b0a371348 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mbed_official 25:ac5b0a371348 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mbed_official 25:ac5b0a371348 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mbed_official 25:ac5b0a371348 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mbed_official 25:ac5b0a371348 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mbed_official 25:ac5b0a371348 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mbed_official 25:ac5b0a371348 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 25:ac5b0a371348 34 POSSIBILITY OF SUCH DAMAGE.
mbed_official 25:ac5b0a371348 35 ---------------------------------------------------------------------------*/
mbed_official 25:ac5b0a371348 36
mbed_official 25:ac5b0a371348 37
mbed_official 25:ac5b0a371348 38 #if defined ( __ICCARM__ )
mbed_official 25:ac5b0a371348 39 #pragma system_include /* treat file as system include file for MISRA check */
mbed_official 25:ac5b0a371348 40 #endif
mbed_official 25:ac5b0a371348 41
mbed_official 25:ac5b0a371348 42 #ifndef __CORE_SC300_H_GENERIC
mbed_official 25:ac5b0a371348 43 #define __CORE_SC300_H_GENERIC
mbed_official 25:ac5b0a371348 44
mbed_official 25:ac5b0a371348 45 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 46 extern "C" {
mbed_official 25:ac5b0a371348 47 #endif
mbed_official 25:ac5b0a371348 48
mbed_official 25:ac5b0a371348 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
mbed_official 25:ac5b0a371348 50 CMSIS violates the following MISRA-C:2004 rules:
mbed_official 25:ac5b0a371348 51
mbed_official 25:ac5b0a371348 52 \li Required Rule 8.5, object/function definition in header file.<br>
mbed_official 25:ac5b0a371348 53 Function definitions in header files are used to allow 'inlining'.
mbed_official 25:ac5b0a371348 54
mbed_official 25:ac5b0a371348 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
mbed_official 25:ac5b0a371348 56 Unions are used for effective representation of core registers.
mbed_official 25:ac5b0a371348 57
mbed_official 25:ac5b0a371348 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
mbed_official 25:ac5b0a371348 59 Function-like macros are used to allow more efficient code.
mbed_official 25:ac5b0a371348 60 */
mbed_official 25:ac5b0a371348 61
mbed_official 25:ac5b0a371348 62
mbed_official 25:ac5b0a371348 63 /*******************************************************************************
mbed_official 25:ac5b0a371348 64 * CMSIS definitions
mbed_official 25:ac5b0a371348 65 ******************************************************************************/
mbed_official 25:ac5b0a371348 66 /** \ingroup SC3000
mbed_official 25:ac5b0a371348 67 @{
mbed_official 25:ac5b0a371348 68 */
mbed_official 25:ac5b0a371348 69
mbed_official 25:ac5b0a371348 70 /* CMSIS SC300 definitions */
mbed_official 25:ac5b0a371348 71 #define __SC300_CMSIS_VERSION_MAIN (0x04) /*!< [31:16] CMSIS HAL main version */
mbed_official 25:ac5b0a371348 72 #define __SC300_CMSIS_VERSION_SUB (0x00) /*!< [15:0] CMSIS HAL sub version */
mbed_official 25:ac5b0a371348 73 #define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
mbed_official 25:ac5b0a371348 74 __SC300_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
mbed_official 25:ac5b0a371348 75
mbed_official 25:ac5b0a371348 76 #define __CORTEX_SC (300) /*!< Cortex secure core */
mbed_official 25:ac5b0a371348 77
mbed_official 25:ac5b0a371348 78
mbed_official 25:ac5b0a371348 79 #if defined ( __CC_ARM )
mbed_official 25:ac5b0a371348 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
mbed_official 25:ac5b0a371348 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
mbed_official 25:ac5b0a371348 82 #define __STATIC_INLINE static __inline
mbed_official 25:ac5b0a371348 83
mbed_official 25:ac5b0a371348 84 #elif defined ( __GNUC__ )
mbed_official 25:ac5b0a371348 85 #define __ASM __asm /*!< asm keyword for GNU Compiler */
mbed_official 25:ac5b0a371348 86 #define __INLINE inline /*!< inline keyword for GNU Compiler */
mbed_official 25:ac5b0a371348 87 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 88
mbed_official 25:ac5b0a371348 89 #elif defined ( __ICCARM__ )
mbed_official 25:ac5b0a371348 90 #define __ASM __asm /*!< asm keyword for IAR Compiler */
mbed_official 25:ac5b0a371348 91 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
mbed_official 25:ac5b0a371348 92 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 93
mbed_official 25:ac5b0a371348 94 #elif defined ( __TMS470__ )
mbed_official 25:ac5b0a371348 95 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
mbed_official 25:ac5b0a371348 96 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 97
mbed_official 25:ac5b0a371348 98 #elif defined ( __TASKING__ )
mbed_official 25:ac5b0a371348 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
mbed_official 25:ac5b0a371348 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
mbed_official 25:ac5b0a371348 101 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 102
mbed_official 25:ac5b0a371348 103 #elif defined ( __CSMC__ )
mbed_official 25:ac5b0a371348 104 #define __packed
mbed_official 25:ac5b0a371348 105 #define __ASM _asm /*!< asm keyword for COSMIC Compiler */
mbed_official 25:ac5b0a371348 106 #define __INLINE inline /*use -pc99 on compile line !< inline keyword for COSMIC Compiler */
mbed_official 25:ac5b0a371348 107 #define __STATIC_INLINE static inline
mbed_official 25:ac5b0a371348 108
mbed_official 25:ac5b0a371348 109 #endif
mbed_official 25:ac5b0a371348 110
mbed_official 25:ac5b0a371348 111 /** __FPU_USED indicates whether an FPU is used or not.
mbed_official 25:ac5b0a371348 112 This core does not support an FPU at all
mbed_official 25:ac5b0a371348 113 */
mbed_official 25:ac5b0a371348 114 #define __FPU_USED 0
mbed_official 25:ac5b0a371348 115
mbed_official 25:ac5b0a371348 116 #if defined ( __CC_ARM )
mbed_official 25:ac5b0a371348 117 #if defined __TARGET_FPU_VFP
mbed_official 25:ac5b0a371348 118 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 119 #endif
mbed_official 25:ac5b0a371348 120
mbed_official 25:ac5b0a371348 121 #elif defined ( __GNUC__ )
mbed_official 25:ac5b0a371348 122 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
mbed_official 25:ac5b0a371348 123 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 124 #endif
mbed_official 25:ac5b0a371348 125
mbed_official 25:ac5b0a371348 126 #elif defined ( __ICCARM__ )
mbed_official 25:ac5b0a371348 127 #if defined __ARMVFP__
mbed_official 25:ac5b0a371348 128 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 129 #endif
mbed_official 25:ac5b0a371348 130
mbed_official 25:ac5b0a371348 131 #elif defined ( __TMS470__ )
mbed_official 25:ac5b0a371348 132 #if defined __TI__VFP_SUPPORT____
mbed_official 25:ac5b0a371348 133 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 134 #endif
mbed_official 25:ac5b0a371348 135
mbed_official 25:ac5b0a371348 136 #elif defined ( __TASKING__ )
mbed_official 25:ac5b0a371348 137 #if defined __FPU_VFP__
mbed_official 25:ac5b0a371348 138 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 139 #endif
mbed_official 25:ac5b0a371348 140
mbed_official 25:ac5b0a371348 141 #elif defined ( __CSMC__ ) /* Cosmic */
mbed_official 25:ac5b0a371348 142 #if ( __CSMC__ & 0x400) // FPU present for parser
mbed_official 25:ac5b0a371348 143 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
mbed_official 25:ac5b0a371348 144 #endif
mbed_official 25:ac5b0a371348 145 #endif
mbed_official 25:ac5b0a371348 146
mbed_official 25:ac5b0a371348 147 #include <stdint.h> /* standard types definitions */
mbed_official 25:ac5b0a371348 148 #include <core_cmInstr.h> /* Core Instruction Access */
mbed_official 25:ac5b0a371348 149 #include <core_cmFunc.h> /* Core Function Access */
mbed_official 25:ac5b0a371348 150
mbed_official 25:ac5b0a371348 151 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 152 }
mbed_official 25:ac5b0a371348 153 #endif
mbed_official 25:ac5b0a371348 154
mbed_official 25:ac5b0a371348 155 #endif /* __CORE_SC300_H_GENERIC */
mbed_official 25:ac5b0a371348 156
mbed_official 25:ac5b0a371348 157 #ifndef __CMSIS_GENERIC
mbed_official 25:ac5b0a371348 158
mbed_official 25:ac5b0a371348 159 #ifndef __CORE_SC300_H_DEPENDANT
mbed_official 25:ac5b0a371348 160 #define __CORE_SC300_H_DEPENDANT
mbed_official 25:ac5b0a371348 161
mbed_official 25:ac5b0a371348 162 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 163 extern "C" {
mbed_official 25:ac5b0a371348 164 #endif
mbed_official 25:ac5b0a371348 165
mbed_official 25:ac5b0a371348 166 /* check device defines and use defaults */
mbed_official 25:ac5b0a371348 167 #if defined __CHECK_DEVICE_DEFINES
mbed_official 25:ac5b0a371348 168 #ifndef __SC300_REV
mbed_official 25:ac5b0a371348 169 #define __SC300_REV 0x0000
mbed_official 25:ac5b0a371348 170 #warning "__SC300_REV not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 171 #endif
mbed_official 25:ac5b0a371348 172
mbed_official 25:ac5b0a371348 173 #ifndef __MPU_PRESENT
mbed_official 25:ac5b0a371348 174 #define __MPU_PRESENT 0
mbed_official 25:ac5b0a371348 175 #warning "__MPU_PRESENT not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 176 #endif
mbed_official 25:ac5b0a371348 177
mbed_official 25:ac5b0a371348 178 #ifndef __NVIC_PRIO_BITS
mbed_official 25:ac5b0a371348 179 #define __NVIC_PRIO_BITS 4
mbed_official 25:ac5b0a371348 180 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 181 #endif
mbed_official 25:ac5b0a371348 182
mbed_official 25:ac5b0a371348 183 #ifndef __Vendor_SysTickConfig
mbed_official 25:ac5b0a371348 184 #define __Vendor_SysTickConfig 0
mbed_official 25:ac5b0a371348 185 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
mbed_official 25:ac5b0a371348 186 #endif
mbed_official 25:ac5b0a371348 187 #endif
mbed_official 25:ac5b0a371348 188
mbed_official 25:ac5b0a371348 189 /* IO definitions (access restrictions to peripheral registers) */
mbed_official 25:ac5b0a371348 190 /**
mbed_official 25:ac5b0a371348 191 \defgroup CMSIS_glob_defs CMSIS Global Defines
mbed_official 25:ac5b0a371348 192
mbed_official 25:ac5b0a371348 193 <strong>IO Type Qualifiers</strong> are used
mbed_official 25:ac5b0a371348 194 \li to specify the access to peripheral variables.
mbed_official 25:ac5b0a371348 195 \li for automatic generation of peripheral register debug information.
mbed_official 25:ac5b0a371348 196 */
mbed_official 25:ac5b0a371348 197 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 198 #define __I volatile /*!< Defines 'read only' permissions */
mbed_official 25:ac5b0a371348 199 #else
mbed_official 25:ac5b0a371348 200 #define __I volatile const /*!< Defines 'read only' permissions */
mbed_official 25:ac5b0a371348 201 #endif
mbed_official 25:ac5b0a371348 202 #define __O volatile /*!< Defines 'write only' permissions */
mbed_official 25:ac5b0a371348 203 #define __IO volatile /*!< Defines 'read / write' permissions */
mbed_official 25:ac5b0a371348 204
mbed_official 25:ac5b0a371348 205 /*@} end of group SC300 */
mbed_official 25:ac5b0a371348 206
mbed_official 25:ac5b0a371348 207
mbed_official 25:ac5b0a371348 208
mbed_official 25:ac5b0a371348 209 /*******************************************************************************
mbed_official 25:ac5b0a371348 210 * Register Abstraction
mbed_official 25:ac5b0a371348 211 Core Register contain:
mbed_official 25:ac5b0a371348 212 - Core Register
mbed_official 25:ac5b0a371348 213 - Core NVIC Register
mbed_official 25:ac5b0a371348 214 - Core SCB Register
mbed_official 25:ac5b0a371348 215 - Core SysTick Register
mbed_official 25:ac5b0a371348 216 - Core Debug Register
mbed_official 25:ac5b0a371348 217 - Core MPU Register
mbed_official 25:ac5b0a371348 218 ******************************************************************************/
mbed_official 25:ac5b0a371348 219 /** \defgroup CMSIS_core_register Defines and Type Definitions
mbed_official 25:ac5b0a371348 220 \brief Type definitions and defines for Cortex-M processor based devices.
mbed_official 25:ac5b0a371348 221 */
mbed_official 25:ac5b0a371348 222
mbed_official 25:ac5b0a371348 223 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 224 \defgroup CMSIS_CORE Status and Control Registers
mbed_official 25:ac5b0a371348 225 \brief Core Register type definitions.
mbed_official 25:ac5b0a371348 226 @{
mbed_official 25:ac5b0a371348 227 */
mbed_official 25:ac5b0a371348 228
mbed_official 25:ac5b0a371348 229 /** \brief Union type to access the Application Program Status Register (APSR).
mbed_official 25:ac5b0a371348 230 */
mbed_official 25:ac5b0a371348 231 typedef union
mbed_official 25:ac5b0a371348 232 {
mbed_official 25:ac5b0a371348 233 struct
mbed_official 25:ac5b0a371348 234 {
mbed_official 25:ac5b0a371348 235 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
mbed_official 25:ac5b0a371348 236 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbed_official 25:ac5b0a371348 237 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 25:ac5b0a371348 238 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 25:ac5b0a371348 239 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 25:ac5b0a371348 240 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 25:ac5b0a371348 241 } b; /*!< Structure used for bit access */
mbed_official 25:ac5b0a371348 242 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 243 } APSR_Type;
mbed_official 25:ac5b0a371348 244
mbed_official 25:ac5b0a371348 245 /* APSR Register Definitions */
mbed_official 25:ac5b0a371348 246 #define APSR_N_Pos 31 /*!< APSR: N Position */
mbed_official 25:ac5b0a371348 247 #define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */
mbed_official 25:ac5b0a371348 248
mbed_official 25:ac5b0a371348 249 #define APSR_Z_Pos 30 /*!< APSR: Z Position */
mbed_official 25:ac5b0a371348 250 #define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */
mbed_official 25:ac5b0a371348 251
mbed_official 25:ac5b0a371348 252 #define APSR_C_Pos 29 /*!< APSR: C Position */
mbed_official 25:ac5b0a371348 253 #define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */
mbed_official 25:ac5b0a371348 254
mbed_official 25:ac5b0a371348 255 #define APSR_V_Pos 28 /*!< APSR: V Position */
mbed_official 25:ac5b0a371348 256 #define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */
mbed_official 25:ac5b0a371348 257
mbed_official 25:ac5b0a371348 258 #define APSR_Q_Pos 27 /*!< APSR: Q Position */
mbed_official 25:ac5b0a371348 259 #define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */
mbed_official 25:ac5b0a371348 260
mbed_official 25:ac5b0a371348 261
mbed_official 25:ac5b0a371348 262 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
mbed_official 25:ac5b0a371348 263 */
mbed_official 25:ac5b0a371348 264 typedef union
mbed_official 25:ac5b0a371348 265 {
mbed_official 25:ac5b0a371348 266 struct
mbed_official 25:ac5b0a371348 267 {
mbed_official 25:ac5b0a371348 268 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 25:ac5b0a371348 269 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
mbed_official 25:ac5b0a371348 270 } b; /*!< Structure used for bit access */
mbed_official 25:ac5b0a371348 271 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 272 } IPSR_Type;
mbed_official 25:ac5b0a371348 273
mbed_official 25:ac5b0a371348 274 /* IPSR Register Definitions */
mbed_official 25:ac5b0a371348 275 #define IPSR_ISR_Pos 0 /*!< IPSR: ISR Position */
mbed_official 25:ac5b0a371348 276 #define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */
mbed_official 25:ac5b0a371348 277
mbed_official 25:ac5b0a371348 278
mbed_official 25:ac5b0a371348 279 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
mbed_official 25:ac5b0a371348 280 */
mbed_official 25:ac5b0a371348 281 typedef union
mbed_official 25:ac5b0a371348 282 {
mbed_official 25:ac5b0a371348 283 struct
mbed_official 25:ac5b0a371348 284 {
mbed_official 25:ac5b0a371348 285 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
mbed_official 25:ac5b0a371348 286 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
mbed_official 25:ac5b0a371348 287 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
mbed_official 25:ac5b0a371348 288 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
mbed_official 25:ac5b0a371348 289 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
mbed_official 25:ac5b0a371348 290 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
mbed_official 25:ac5b0a371348 291 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
mbed_official 25:ac5b0a371348 292 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
mbed_official 25:ac5b0a371348 293 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
mbed_official 25:ac5b0a371348 294 } b; /*!< Structure used for bit access */
mbed_official 25:ac5b0a371348 295 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 296 } xPSR_Type;
mbed_official 25:ac5b0a371348 297
mbed_official 25:ac5b0a371348 298 /* xPSR Register Definitions */
mbed_official 25:ac5b0a371348 299 #define xPSR_N_Pos 31 /*!< xPSR: N Position */
mbed_official 25:ac5b0a371348 300 #define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */
mbed_official 25:ac5b0a371348 301
mbed_official 25:ac5b0a371348 302 #define xPSR_Z_Pos 30 /*!< xPSR: Z Position */
mbed_official 25:ac5b0a371348 303 #define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */
mbed_official 25:ac5b0a371348 304
mbed_official 25:ac5b0a371348 305 #define xPSR_C_Pos 29 /*!< xPSR: C Position */
mbed_official 25:ac5b0a371348 306 #define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */
mbed_official 25:ac5b0a371348 307
mbed_official 25:ac5b0a371348 308 #define xPSR_V_Pos 28 /*!< xPSR: V Position */
mbed_official 25:ac5b0a371348 309 #define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */
mbed_official 25:ac5b0a371348 310
mbed_official 25:ac5b0a371348 311 #define xPSR_Q_Pos 27 /*!< xPSR: Q Position */
mbed_official 25:ac5b0a371348 312 #define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */
mbed_official 25:ac5b0a371348 313
mbed_official 25:ac5b0a371348 314 #define xPSR_IT_Pos 25 /*!< xPSR: IT Position */
mbed_official 25:ac5b0a371348 315 #define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */
mbed_official 25:ac5b0a371348 316
mbed_official 25:ac5b0a371348 317 #define xPSR_T_Pos 24 /*!< xPSR: T Position */
mbed_official 25:ac5b0a371348 318 #define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */
mbed_official 25:ac5b0a371348 319
mbed_official 25:ac5b0a371348 320 #define xPSR_ISR_Pos 0 /*!< xPSR: ISR Position */
mbed_official 25:ac5b0a371348 321 #define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */
mbed_official 25:ac5b0a371348 322
mbed_official 25:ac5b0a371348 323
mbed_official 25:ac5b0a371348 324 /** \brief Union type to access the Control Registers (CONTROL).
mbed_official 25:ac5b0a371348 325 */
mbed_official 25:ac5b0a371348 326 typedef union
mbed_official 25:ac5b0a371348 327 {
mbed_official 25:ac5b0a371348 328 struct
mbed_official 25:ac5b0a371348 329 {
mbed_official 25:ac5b0a371348 330 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
mbed_official 25:ac5b0a371348 331 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
mbed_official 25:ac5b0a371348 332 uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */
mbed_official 25:ac5b0a371348 333 } b; /*!< Structure used for bit access */
mbed_official 25:ac5b0a371348 334 uint32_t w; /*!< Type used for word access */
mbed_official 25:ac5b0a371348 335 } CONTROL_Type;
mbed_official 25:ac5b0a371348 336
mbed_official 25:ac5b0a371348 337 /* CONTROL Register Definitions */
mbed_official 25:ac5b0a371348 338 #define CONTROL_SPSEL_Pos 1 /*!< CONTROL: SPSEL Position */
mbed_official 25:ac5b0a371348 339 #define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */
mbed_official 25:ac5b0a371348 340
mbed_official 25:ac5b0a371348 341 #define CONTROL_nPRIV_Pos 0 /*!< CONTROL: nPRIV Position */
mbed_official 25:ac5b0a371348 342 #define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */
mbed_official 25:ac5b0a371348 343
mbed_official 25:ac5b0a371348 344 /*@} end of group CMSIS_CORE */
mbed_official 25:ac5b0a371348 345
mbed_official 25:ac5b0a371348 346
mbed_official 25:ac5b0a371348 347 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 348 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
mbed_official 25:ac5b0a371348 349 \brief Type definitions for the NVIC Registers
mbed_official 25:ac5b0a371348 350 @{
mbed_official 25:ac5b0a371348 351 */
mbed_official 25:ac5b0a371348 352
mbed_official 25:ac5b0a371348 353 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
mbed_official 25:ac5b0a371348 354 */
mbed_official 25:ac5b0a371348 355 typedef struct
mbed_official 25:ac5b0a371348 356 {
mbed_official 25:ac5b0a371348 357 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
mbed_official 25:ac5b0a371348 358 uint32_t RESERVED0[24];
mbed_official 25:ac5b0a371348 359 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
mbed_official 25:ac5b0a371348 360 uint32_t RSERVED1[24];
mbed_official 25:ac5b0a371348 361 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
mbed_official 25:ac5b0a371348 362 uint32_t RESERVED2[24];
mbed_official 25:ac5b0a371348 363 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
mbed_official 25:ac5b0a371348 364 uint32_t RESERVED3[24];
mbed_official 25:ac5b0a371348 365 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
mbed_official 25:ac5b0a371348 366 uint32_t RESERVED4[56];
mbed_official 25:ac5b0a371348 367 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
mbed_official 25:ac5b0a371348 368 uint32_t RESERVED5[644];
mbed_official 25:ac5b0a371348 369 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
mbed_official 25:ac5b0a371348 370 } NVIC_Type;
mbed_official 25:ac5b0a371348 371
mbed_official 25:ac5b0a371348 372 /* Software Triggered Interrupt Register Definitions */
mbed_official 25:ac5b0a371348 373 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
mbed_official 25:ac5b0a371348 374 #define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */
mbed_official 25:ac5b0a371348 375
mbed_official 25:ac5b0a371348 376 /*@} end of group CMSIS_NVIC */
mbed_official 25:ac5b0a371348 377
mbed_official 25:ac5b0a371348 378
mbed_official 25:ac5b0a371348 379 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 380 \defgroup CMSIS_SCB System Control Block (SCB)
mbed_official 25:ac5b0a371348 381 \brief Type definitions for the System Control Block Registers
mbed_official 25:ac5b0a371348 382 @{
mbed_official 25:ac5b0a371348 383 */
mbed_official 25:ac5b0a371348 384
mbed_official 25:ac5b0a371348 385 /** \brief Structure type to access the System Control Block (SCB).
mbed_official 25:ac5b0a371348 386 */
mbed_official 25:ac5b0a371348 387 typedef struct
mbed_official 25:ac5b0a371348 388 {
mbed_official 25:ac5b0a371348 389 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
mbed_official 25:ac5b0a371348 390 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
mbed_official 25:ac5b0a371348 391 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
mbed_official 25:ac5b0a371348 392 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
mbed_official 25:ac5b0a371348 393 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
mbed_official 25:ac5b0a371348 394 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
mbed_official 25:ac5b0a371348 395 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
mbed_official 25:ac5b0a371348 396 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
mbed_official 25:ac5b0a371348 397 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
mbed_official 25:ac5b0a371348 398 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
mbed_official 25:ac5b0a371348 399 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
mbed_official 25:ac5b0a371348 400 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
mbed_official 25:ac5b0a371348 401 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
mbed_official 25:ac5b0a371348 402 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
mbed_official 25:ac5b0a371348 403 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
mbed_official 25:ac5b0a371348 404 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
mbed_official 25:ac5b0a371348 405 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
mbed_official 25:ac5b0a371348 406 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
mbed_official 25:ac5b0a371348 407 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
mbed_official 25:ac5b0a371348 408 uint32_t RESERVED0[5];
mbed_official 25:ac5b0a371348 409 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
mbed_official 25:ac5b0a371348 410 uint32_t RESERVED1[129];
mbed_official 25:ac5b0a371348 411 __IO uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */
mbed_official 25:ac5b0a371348 412 } SCB_Type;
mbed_official 25:ac5b0a371348 413
mbed_official 25:ac5b0a371348 414 /* SCB CPUID Register Definitions */
mbed_official 25:ac5b0a371348 415 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
mbed_official 25:ac5b0a371348 416 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
mbed_official 25:ac5b0a371348 417
mbed_official 25:ac5b0a371348 418 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
mbed_official 25:ac5b0a371348 419 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
mbed_official 25:ac5b0a371348 420
mbed_official 25:ac5b0a371348 421 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
mbed_official 25:ac5b0a371348 422 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
mbed_official 25:ac5b0a371348 423
mbed_official 25:ac5b0a371348 424 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
mbed_official 25:ac5b0a371348 425 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
mbed_official 25:ac5b0a371348 426
mbed_official 25:ac5b0a371348 427 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
mbed_official 25:ac5b0a371348 428 #define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */
mbed_official 25:ac5b0a371348 429
mbed_official 25:ac5b0a371348 430 /* SCB Interrupt Control State Register Definitions */
mbed_official 25:ac5b0a371348 431 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
mbed_official 25:ac5b0a371348 432 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
mbed_official 25:ac5b0a371348 433
mbed_official 25:ac5b0a371348 434 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
mbed_official 25:ac5b0a371348 435 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
mbed_official 25:ac5b0a371348 436
mbed_official 25:ac5b0a371348 437 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
mbed_official 25:ac5b0a371348 438 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
mbed_official 25:ac5b0a371348 439
mbed_official 25:ac5b0a371348 440 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
mbed_official 25:ac5b0a371348 441 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
mbed_official 25:ac5b0a371348 442
mbed_official 25:ac5b0a371348 443 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
mbed_official 25:ac5b0a371348 444 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
mbed_official 25:ac5b0a371348 445
mbed_official 25:ac5b0a371348 446 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
mbed_official 25:ac5b0a371348 447 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
mbed_official 25:ac5b0a371348 448
mbed_official 25:ac5b0a371348 449 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
mbed_official 25:ac5b0a371348 450 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
mbed_official 25:ac5b0a371348 451
mbed_official 25:ac5b0a371348 452 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
mbed_official 25:ac5b0a371348 453 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
mbed_official 25:ac5b0a371348 454
mbed_official 25:ac5b0a371348 455 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
mbed_official 25:ac5b0a371348 456 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
mbed_official 25:ac5b0a371348 457
mbed_official 25:ac5b0a371348 458 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
mbed_official 25:ac5b0a371348 459 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */
mbed_official 25:ac5b0a371348 460
mbed_official 25:ac5b0a371348 461 /* SCB Vector Table Offset Register Definitions */
mbed_official 25:ac5b0a371348 462 #define SCB_VTOR_TBLBASE_Pos 29 /*!< SCB VTOR: TBLBASE Position */
mbed_official 25:ac5b0a371348 463 #define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */
mbed_official 25:ac5b0a371348 464
mbed_official 25:ac5b0a371348 465 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
mbed_official 25:ac5b0a371348 466 #define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
mbed_official 25:ac5b0a371348 467
mbed_official 25:ac5b0a371348 468 /* SCB Application Interrupt and Reset Control Register Definitions */
mbed_official 25:ac5b0a371348 469 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
mbed_official 25:ac5b0a371348 470 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
mbed_official 25:ac5b0a371348 471
mbed_official 25:ac5b0a371348 472 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
mbed_official 25:ac5b0a371348 473 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
mbed_official 25:ac5b0a371348 474
mbed_official 25:ac5b0a371348 475 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
mbed_official 25:ac5b0a371348 476 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
mbed_official 25:ac5b0a371348 477
mbed_official 25:ac5b0a371348 478 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
mbed_official 25:ac5b0a371348 479 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
mbed_official 25:ac5b0a371348 480
mbed_official 25:ac5b0a371348 481 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
mbed_official 25:ac5b0a371348 482 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
mbed_official 25:ac5b0a371348 483
mbed_official 25:ac5b0a371348 484 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
mbed_official 25:ac5b0a371348 485 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
mbed_official 25:ac5b0a371348 486
mbed_official 25:ac5b0a371348 487 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
mbed_official 25:ac5b0a371348 488 #define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */
mbed_official 25:ac5b0a371348 489
mbed_official 25:ac5b0a371348 490 /* SCB System Control Register Definitions */
mbed_official 25:ac5b0a371348 491 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
mbed_official 25:ac5b0a371348 492 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
mbed_official 25:ac5b0a371348 493
mbed_official 25:ac5b0a371348 494 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
mbed_official 25:ac5b0a371348 495 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
mbed_official 25:ac5b0a371348 496
mbed_official 25:ac5b0a371348 497 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
mbed_official 25:ac5b0a371348 498 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
mbed_official 25:ac5b0a371348 499
mbed_official 25:ac5b0a371348 500 /* SCB Configuration Control Register Definitions */
mbed_official 25:ac5b0a371348 501 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
mbed_official 25:ac5b0a371348 502 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
mbed_official 25:ac5b0a371348 503
mbed_official 25:ac5b0a371348 504 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
mbed_official 25:ac5b0a371348 505 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
mbed_official 25:ac5b0a371348 506
mbed_official 25:ac5b0a371348 507 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
mbed_official 25:ac5b0a371348 508 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
mbed_official 25:ac5b0a371348 509
mbed_official 25:ac5b0a371348 510 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
mbed_official 25:ac5b0a371348 511 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
mbed_official 25:ac5b0a371348 512
mbed_official 25:ac5b0a371348 513 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
mbed_official 25:ac5b0a371348 514 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
mbed_official 25:ac5b0a371348 515
mbed_official 25:ac5b0a371348 516 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
mbed_official 25:ac5b0a371348 517 #define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */
mbed_official 25:ac5b0a371348 518
mbed_official 25:ac5b0a371348 519 /* SCB System Handler Control and State Register Definitions */
mbed_official 25:ac5b0a371348 520 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
mbed_official 25:ac5b0a371348 521 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
mbed_official 25:ac5b0a371348 522
mbed_official 25:ac5b0a371348 523 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
mbed_official 25:ac5b0a371348 524 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
mbed_official 25:ac5b0a371348 525
mbed_official 25:ac5b0a371348 526 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
mbed_official 25:ac5b0a371348 527 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
mbed_official 25:ac5b0a371348 528
mbed_official 25:ac5b0a371348 529 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
mbed_official 25:ac5b0a371348 530 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
mbed_official 25:ac5b0a371348 531
mbed_official 25:ac5b0a371348 532 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
mbed_official 25:ac5b0a371348 533 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
mbed_official 25:ac5b0a371348 534
mbed_official 25:ac5b0a371348 535 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
mbed_official 25:ac5b0a371348 536 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
mbed_official 25:ac5b0a371348 537
mbed_official 25:ac5b0a371348 538 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
mbed_official 25:ac5b0a371348 539 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
mbed_official 25:ac5b0a371348 540
mbed_official 25:ac5b0a371348 541 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
mbed_official 25:ac5b0a371348 542 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
mbed_official 25:ac5b0a371348 543
mbed_official 25:ac5b0a371348 544 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
mbed_official 25:ac5b0a371348 545 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
mbed_official 25:ac5b0a371348 546
mbed_official 25:ac5b0a371348 547 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
mbed_official 25:ac5b0a371348 548 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
mbed_official 25:ac5b0a371348 549
mbed_official 25:ac5b0a371348 550 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
mbed_official 25:ac5b0a371348 551 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
mbed_official 25:ac5b0a371348 552
mbed_official 25:ac5b0a371348 553 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
mbed_official 25:ac5b0a371348 554 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
mbed_official 25:ac5b0a371348 555
mbed_official 25:ac5b0a371348 556 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
mbed_official 25:ac5b0a371348 557 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
mbed_official 25:ac5b0a371348 558
mbed_official 25:ac5b0a371348 559 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
mbed_official 25:ac5b0a371348 560 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */
mbed_official 25:ac5b0a371348 561
mbed_official 25:ac5b0a371348 562 /* SCB Configurable Fault Status Registers Definitions */
mbed_official 25:ac5b0a371348 563 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
mbed_official 25:ac5b0a371348 564 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
mbed_official 25:ac5b0a371348 565
mbed_official 25:ac5b0a371348 566 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
mbed_official 25:ac5b0a371348 567 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
mbed_official 25:ac5b0a371348 568
mbed_official 25:ac5b0a371348 569 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
mbed_official 25:ac5b0a371348 570 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
mbed_official 25:ac5b0a371348 571
mbed_official 25:ac5b0a371348 572 /* SCB Hard Fault Status Registers Definitions */
mbed_official 25:ac5b0a371348 573 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
mbed_official 25:ac5b0a371348 574 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
mbed_official 25:ac5b0a371348 575
mbed_official 25:ac5b0a371348 576 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
mbed_official 25:ac5b0a371348 577 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
mbed_official 25:ac5b0a371348 578
mbed_official 25:ac5b0a371348 579 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
mbed_official 25:ac5b0a371348 580 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
mbed_official 25:ac5b0a371348 581
mbed_official 25:ac5b0a371348 582 /* SCB Debug Fault Status Register Definitions */
mbed_official 25:ac5b0a371348 583 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
mbed_official 25:ac5b0a371348 584 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
mbed_official 25:ac5b0a371348 585
mbed_official 25:ac5b0a371348 586 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
mbed_official 25:ac5b0a371348 587 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
mbed_official 25:ac5b0a371348 588
mbed_official 25:ac5b0a371348 589 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
mbed_official 25:ac5b0a371348 590 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
mbed_official 25:ac5b0a371348 591
mbed_official 25:ac5b0a371348 592 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
mbed_official 25:ac5b0a371348 593 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
mbed_official 25:ac5b0a371348 594
mbed_official 25:ac5b0a371348 595 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
mbed_official 25:ac5b0a371348 596 #define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */
mbed_official 25:ac5b0a371348 597
mbed_official 25:ac5b0a371348 598 /*@} end of group CMSIS_SCB */
mbed_official 25:ac5b0a371348 599
mbed_official 25:ac5b0a371348 600
mbed_official 25:ac5b0a371348 601 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 602 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
mbed_official 25:ac5b0a371348 603 \brief Type definitions for the System Control and ID Register not in the SCB
mbed_official 25:ac5b0a371348 604 @{
mbed_official 25:ac5b0a371348 605 */
mbed_official 25:ac5b0a371348 606
mbed_official 25:ac5b0a371348 607 /** \brief Structure type to access the System Control and ID Register not in the SCB.
mbed_official 25:ac5b0a371348 608 */
mbed_official 25:ac5b0a371348 609 typedef struct
mbed_official 25:ac5b0a371348 610 {
mbed_official 25:ac5b0a371348 611 uint32_t RESERVED0[1];
mbed_official 25:ac5b0a371348 612 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
mbed_official 25:ac5b0a371348 613 uint32_t RESERVED1[1];
mbed_official 25:ac5b0a371348 614 } SCnSCB_Type;
mbed_official 25:ac5b0a371348 615
mbed_official 25:ac5b0a371348 616 /* Interrupt Controller Type Register Definitions */
mbed_official 25:ac5b0a371348 617 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
mbed_official 25:ac5b0a371348 618 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */
mbed_official 25:ac5b0a371348 619
mbed_official 25:ac5b0a371348 620 /*@} end of group CMSIS_SCnotSCB */
mbed_official 25:ac5b0a371348 621
mbed_official 25:ac5b0a371348 622
mbed_official 25:ac5b0a371348 623 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 624 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
mbed_official 25:ac5b0a371348 625 \brief Type definitions for the System Timer Registers.
mbed_official 25:ac5b0a371348 626 @{
mbed_official 25:ac5b0a371348 627 */
mbed_official 25:ac5b0a371348 628
mbed_official 25:ac5b0a371348 629 /** \brief Structure type to access the System Timer (SysTick).
mbed_official 25:ac5b0a371348 630 */
mbed_official 25:ac5b0a371348 631 typedef struct
mbed_official 25:ac5b0a371348 632 {
mbed_official 25:ac5b0a371348 633 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
mbed_official 25:ac5b0a371348 634 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
mbed_official 25:ac5b0a371348 635 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
mbed_official 25:ac5b0a371348 636 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
mbed_official 25:ac5b0a371348 637 } SysTick_Type;
mbed_official 25:ac5b0a371348 638
mbed_official 25:ac5b0a371348 639 /* SysTick Control / Status Register Definitions */
mbed_official 25:ac5b0a371348 640 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
mbed_official 25:ac5b0a371348 641 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
mbed_official 25:ac5b0a371348 642
mbed_official 25:ac5b0a371348 643 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
mbed_official 25:ac5b0a371348 644 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
mbed_official 25:ac5b0a371348 645
mbed_official 25:ac5b0a371348 646 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
mbed_official 25:ac5b0a371348 647 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
mbed_official 25:ac5b0a371348 648
mbed_official 25:ac5b0a371348 649 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
mbed_official 25:ac5b0a371348 650 #define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */
mbed_official 25:ac5b0a371348 651
mbed_official 25:ac5b0a371348 652 /* SysTick Reload Register Definitions */
mbed_official 25:ac5b0a371348 653 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
mbed_official 25:ac5b0a371348 654 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */
mbed_official 25:ac5b0a371348 655
mbed_official 25:ac5b0a371348 656 /* SysTick Current Register Definitions */
mbed_official 25:ac5b0a371348 657 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
mbed_official 25:ac5b0a371348 658 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */
mbed_official 25:ac5b0a371348 659
mbed_official 25:ac5b0a371348 660 /* SysTick Calibration Register Definitions */
mbed_official 25:ac5b0a371348 661 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
mbed_official 25:ac5b0a371348 662 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
mbed_official 25:ac5b0a371348 663
mbed_official 25:ac5b0a371348 664 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
mbed_official 25:ac5b0a371348 665 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
mbed_official 25:ac5b0a371348 666
mbed_official 25:ac5b0a371348 667 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
mbed_official 25:ac5b0a371348 668 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */
mbed_official 25:ac5b0a371348 669
mbed_official 25:ac5b0a371348 670 /*@} end of group CMSIS_SysTick */
mbed_official 25:ac5b0a371348 671
mbed_official 25:ac5b0a371348 672
mbed_official 25:ac5b0a371348 673 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 674 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
mbed_official 25:ac5b0a371348 675 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
mbed_official 25:ac5b0a371348 676 @{
mbed_official 25:ac5b0a371348 677 */
mbed_official 25:ac5b0a371348 678
mbed_official 25:ac5b0a371348 679 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
mbed_official 25:ac5b0a371348 680 */
mbed_official 25:ac5b0a371348 681 typedef struct
mbed_official 25:ac5b0a371348 682 {
mbed_official 25:ac5b0a371348 683 __O union
mbed_official 25:ac5b0a371348 684 {
mbed_official 25:ac5b0a371348 685 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
mbed_official 25:ac5b0a371348 686 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
mbed_official 25:ac5b0a371348 687 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
mbed_official 25:ac5b0a371348 688 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
mbed_official 25:ac5b0a371348 689 uint32_t RESERVED0[864];
mbed_official 25:ac5b0a371348 690 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
mbed_official 25:ac5b0a371348 691 uint32_t RESERVED1[15];
mbed_official 25:ac5b0a371348 692 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
mbed_official 25:ac5b0a371348 693 uint32_t RESERVED2[15];
mbed_official 25:ac5b0a371348 694 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
mbed_official 25:ac5b0a371348 695 uint32_t RESERVED3[29];
mbed_official 25:ac5b0a371348 696 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
mbed_official 25:ac5b0a371348 697 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
mbed_official 25:ac5b0a371348 698 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
mbed_official 25:ac5b0a371348 699 uint32_t RESERVED4[43];
mbed_official 25:ac5b0a371348 700 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
mbed_official 25:ac5b0a371348 701 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
mbed_official 25:ac5b0a371348 702 uint32_t RESERVED5[6];
mbed_official 25:ac5b0a371348 703 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
mbed_official 25:ac5b0a371348 704 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
mbed_official 25:ac5b0a371348 705 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
mbed_official 25:ac5b0a371348 706 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
mbed_official 25:ac5b0a371348 707 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
mbed_official 25:ac5b0a371348 708 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
mbed_official 25:ac5b0a371348 709 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
mbed_official 25:ac5b0a371348 710 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
mbed_official 25:ac5b0a371348 711 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
mbed_official 25:ac5b0a371348 712 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
mbed_official 25:ac5b0a371348 713 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
mbed_official 25:ac5b0a371348 714 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
mbed_official 25:ac5b0a371348 715 } ITM_Type;
mbed_official 25:ac5b0a371348 716
mbed_official 25:ac5b0a371348 717 /* ITM Trace Privilege Register Definitions */
mbed_official 25:ac5b0a371348 718 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
mbed_official 25:ac5b0a371348 719 #define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */
mbed_official 25:ac5b0a371348 720
mbed_official 25:ac5b0a371348 721 /* ITM Trace Control Register Definitions */
mbed_official 25:ac5b0a371348 722 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
mbed_official 25:ac5b0a371348 723 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
mbed_official 25:ac5b0a371348 724
mbed_official 25:ac5b0a371348 725 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
mbed_official 25:ac5b0a371348 726 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
mbed_official 25:ac5b0a371348 727
mbed_official 25:ac5b0a371348 728 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
mbed_official 25:ac5b0a371348 729 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
mbed_official 25:ac5b0a371348 730
mbed_official 25:ac5b0a371348 731 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
mbed_official 25:ac5b0a371348 732 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
mbed_official 25:ac5b0a371348 733
mbed_official 25:ac5b0a371348 734 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
mbed_official 25:ac5b0a371348 735 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
mbed_official 25:ac5b0a371348 736
mbed_official 25:ac5b0a371348 737 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
mbed_official 25:ac5b0a371348 738 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
mbed_official 25:ac5b0a371348 739
mbed_official 25:ac5b0a371348 740 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
mbed_official 25:ac5b0a371348 741 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
mbed_official 25:ac5b0a371348 742
mbed_official 25:ac5b0a371348 743 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
mbed_official 25:ac5b0a371348 744 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
mbed_official 25:ac5b0a371348 745
mbed_official 25:ac5b0a371348 746 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
mbed_official 25:ac5b0a371348 747 #define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */
mbed_official 25:ac5b0a371348 748
mbed_official 25:ac5b0a371348 749 /* ITM Integration Write Register Definitions */
mbed_official 25:ac5b0a371348 750 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
mbed_official 25:ac5b0a371348 751 #define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */
mbed_official 25:ac5b0a371348 752
mbed_official 25:ac5b0a371348 753 /* ITM Integration Read Register Definitions */
mbed_official 25:ac5b0a371348 754 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
mbed_official 25:ac5b0a371348 755 #define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */
mbed_official 25:ac5b0a371348 756
mbed_official 25:ac5b0a371348 757 /* ITM Integration Mode Control Register Definitions */
mbed_official 25:ac5b0a371348 758 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
mbed_official 25:ac5b0a371348 759 #define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */
mbed_official 25:ac5b0a371348 760
mbed_official 25:ac5b0a371348 761 /* ITM Lock Status Register Definitions */
mbed_official 25:ac5b0a371348 762 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
mbed_official 25:ac5b0a371348 763 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
mbed_official 25:ac5b0a371348 764
mbed_official 25:ac5b0a371348 765 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
mbed_official 25:ac5b0a371348 766 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
mbed_official 25:ac5b0a371348 767
mbed_official 25:ac5b0a371348 768 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
mbed_official 25:ac5b0a371348 769 #define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */
mbed_official 25:ac5b0a371348 770
mbed_official 25:ac5b0a371348 771 /*@}*/ /* end of group CMSIS_ITM */
mbed_official 25:ac5b0a371348 772
mbed_official 25:ac5b0a371348 773
mbed_official 25:ac5b0a371348 774 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 775 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
mbed_official 25:ac5b0a371348 776 \brief Type definitions for the Data Watchpoint and Trace (DWT)
mbed_official 25:ac5b0a371348 777 @{
mbed_official 25:ac5b0a371348 778 */
mbed_official 25:ac5b0a371348 779
mbed_official 25:ac5b0a371348 780 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
mbed_official 25:ac5b0a371348 781 */
mbed_official 25:ac5b0a371348 782 typedef struct
mbed_official 25:ac5b0a371348 783 {
mbed_official 25:ac5b0a371348 784 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
mbed_official 25:ac5b0a371348 785 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
mbed_official 25:ac5b0a371348 786 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
mbed_official 25:ac5b0a371348 787 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
mbed_official 25:ac5b0a371348 788 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
mbed_official 25:ac5b0a371348 789 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
mbed_official 25:ac5b0a371348 790 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
mbed_official 25:ac5b0a371348 791 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
mbed_official 25:ac5b0a371348 792 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
mbed_official 25:ac5b0a371348 793 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
mbed_official 25:ac5b0a371348 794 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
mbed_official 25:ac5b0a371348 795 uint32_t RESERVED0[1];
mbed_official 25:ac5b0a371348 796 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
mbed_official 25:ac5b0a371348 797 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
mbed_official 25:ac5b0a371348 798 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
mbed_official 25:ac5b0a371348 799 uint32_t RESERVED1[1];
mbed_official 25:ac5b0a371348 800 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
mbed_official 25:ac5b0a371348 801 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
mbed_official 25:ac5b0a371348 802 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
mbed_official 25:ac5b0a371348 803 uint32_t RESERVED2[1];
mbed_official 25:ac5b0a371348 804 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
mbed_official 25:ac5b0a371348 805 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
mbed_official 25:ac5b0a371348 806 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
mbed_official 25:ac5b0a371348 807 } DWT_Type;
mbed_official 25:ac5b0a371348 808
mbed_official 25:ac5b0a371348 809 /* DWT Control Register Definitions */
mbed_official 25:ac5b0a371348 810 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
mbed_official 25:ac5b0a371348 811 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
mbed_official 25:ac5b0a371348 812
mbed_official 25:ac5b0a371348 813 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
mbed_official 25:ac5b0a371348 814 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
mbed_official 25:ac5b0a371348 815
mbed_official 25:ac5b0a371348 816 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
mbed_official 25:ac5b0a371348 817 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
mbed_official 25:ac5b0a371348 818
mbed_official 25:ac5b0a371348 819 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
mbed_official 25:ac5b0a371348 820 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
mbed_official 25:ac5b0a371348 821
mbed_official 25:ac5b0a371348 822 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
mbed_official 25:ac5b0a371348 823 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
mbed_official 25:ac5b0a371348 824
mbed_official 25:ac5b0a371348 825 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
mbed_official 25:ac5b0a371348 826 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
mbed_official 25:ac5b0a371348 827
mbed_official 25:ac5b0a371348 828 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
mbed_official 25:ac5b0a371348 829 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
mbed_official 25:ac5b0a371348 830
mbed_official 25:ac5b0a371348 831 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
mbed_official 25:ac5b0a371348 832 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
mbed_official 25:ac5b0a371348 833
mbed_official 25:ac5b0a371348 834 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
mbed_official 25:ac5b0a371348 835 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
mbed_official 25:ac5b0a371348 836
mbed_official 25:ac5b0a371348 837 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
mbed_official 25:ac5b0a371348 838 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
mbed_official 25:ac5b0a371348 839
mbed_official 25:ac5b0a371348 840 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
mbed_official 25:ac5b0a371348 841 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
mbed_official 25:ac5b0a371348 842
mbed_official 25:ac5b0a371348 843 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
mbed_official 25:ac5b0a371348 844 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
mbed_official 25:ac5b0a371348 845
mbed_official 25:ac5b0a371348 846 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
mbed_official 25:ac5b0a371348 847 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
mbed_official 25:ac5b0a371348 848
mbed_official 25:ac5b0a371348 849 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
mbed_official 25:ac5b0a371348 850 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
mbed_official 25:ac5b0a371348 851
mbed_official 25:ac5b0a371348 852 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
mbed_official 25:ac5b0a371348 853 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
mbed_official 25:ac5b0a371348 854
mbed_official 25:ac5b0a371348 855 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
mbed_official 25:ac5b0a371348 856 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
mbed_official 25:ac5b0a371348 857
mbed_official 25:ac5b0a371348 858 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
mbed_official 25:ac5b0a371348 859 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
mbed_official 25:ac5b0a371348 860
mbed_official 25:ac5b0a371348 861 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
mbed_official 25:ac5b0a371348 862 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */
mbed_official 25:ac5b0a371348 863
mbed_official 25:ac5b0a371348 864 /* DWT CPI Count Register Definitions */
mbed_official 25:ac5b0a371348 865 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
mbed_official 25:ac5b0a371348 866 #define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */
mbed_official 25:ac5b0a371348 867
mbed_official 25:ac5b0a371348 868 /* DWT Exception Overhead Count Register Definitions */
mbed_official 25:ac5b0a371348 869 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
mbed_official 25:ac5b0a371348 870 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */
mbed_official 25:ac5b0a371348 871
mbed_official 25:ac5b0a371348 872 /* DWT Sleep Count Register Definitions */
mbed_official 25:ac5b0a371348 873 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
mbed_official 25:ac5b0a371348 874 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
mbed_official 25:ac5b0a371348 875
mbed_official 25:ac5b0a371348 876 /* DWT LSU Count Register Definitions */
mbed_official 25:ac5b0a371348 877 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
mbed_official 25:ac5b0a371348 878 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */
mbed_official 25:ac5b0a371348 879
mbed_official 25:ac5b0a371348 880 /* DWT Folded-instruction Count Register Definitions */
mbed_official 25:ac5b0a371348 881 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
mbed_official 25:ac5b0a371348 882 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */
mbed_official 25:ac5b0a371348 883
mbed_official 25:ac5b0a371348 884 /* DWT Comparator Mask Register Definitions */
mbed_official 25:ac5b0a371348 885 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
mbed_official 25:ac5b0a371348 886 #define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */
mbed_official 25:ac5b0a371348 887
mbed_official 25:ac5b0a371348 888 /* DWT Comparator Function Register Definitions */
mbed_official 25:ac5b0a371348 889 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
mbed_official 25:ac5b0a371348 890 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
mbed_official 25:ac5b0a371348 891
mbed_official 25:ac5b0a371348 892 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
mbed_official 25:ac5b0a371348 893 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
mbed_official 25:ac5b0a371348 894
mbed_official 25:ac5b0a371348 895 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
mbed_official 25:ac5b0a371348 896 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
mbed_official 25:ac5b0a371348 897
mbed_official 25:ac5b0a371348 898 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
mbed_official 25:ac5b0a371348 899 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
mbed_official 25:ac5b0a371348 900
mbed_official 25:ac5b0a371348 901 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
mbed_official 25:ac5b0a371348 902 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
mbed_official 25:ac5b0a371348 903
mbed_official 25:ac5b0a371348 904 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
mbed_official 25:ac5b0a371348 905 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
mbed_official 25:ac5b0a371348 906
mbed_official 25:ac5b0a371348 907 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
mbed_official 25:ac5b0a371348 908 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
mbed_official 25:ac5b0a371348 909
mbed_official 25:ac5b0a371348 910 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
mbed_official 25:ac5b0a371348 911 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
mbed_official 25:ac5b0a371348 912
mbed_official 25:ac5b0a371348 913 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
mbed_official 25:ac5b0a371348 914 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */
mbed_official 25:ac5b0a371348 915
mbed_official 25:ac5b0a371348 916 /*@}*/ /* end of group CMSIS_DWT */
mbed_official 25:ac5b0a371348 917
mbed_official 25:ac5b0a371348 918
mbed_official 25:ac5b0a371348 919 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 920 \defgroup CMSIS_TPI Trace Port Interface (TPI)
mbed_official 25:ac5b0a371348 921 \brief Type definitions for the Trace Port Interface (TPI)
mbed_official 25:ac5b0a371348 922 @{
mbed_official 25:ac5b0a371348 923 */
mbed_official 25:ac5b0a371348 924
mbed_official 25:ac5b0a371348 925 /** \brief Structure type to access the Trace Port Interface Register (TPI).
mbed_official 25:ac5b0a371348 926 */
mbed_official 25:ac5b0a371348 927 typedef struct
mbed_official 25:ac5b0a371348 928 {
mbed_official 25:ac5b0a371348 929 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
mbed_official 25:ac5b0a371348 930 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
mbed_official 25:ac5b0a371348 931 uint32_t RESERVED0[2];
mbed_official 25:ac5b0a371348 932 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
mbed_official 25:ac5b0a371348 933 uint32_t RESERVED1[55];
mbed_official 25:ac5b0a371348 934 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
mbed_official 25:ac5b0a371348 935 uint32_t RESERVED2[131];
mbed_official 25:ac5b0a371348 936 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
mbed_official 25:ac5b0a371348 937 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
mbed_official 25:ac5b0a371348 938 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
mbed_official 25:ac5b0a371348 939 uint32_t RESERVED3[759];
mbed_official 25:ac5b0a371348 940 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
mbed_official 25:ac5b0a371348 941 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
mbed_official 25:ac5b0a371348 942 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
mbed_official 25:ac5b0a371348 943 uint32_t RESERVED4[1];
mbed_official 25:ac5b0a371348 944 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
mbed_official 25:ac5b0a371348 945 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
mbed_official 25:ac5b0a371348 946 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
mbed_official 25:ac5b0a371348 947 uint32_t RESERVED5[39];
mbed_official 25:ac5b0a371348 948 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
mbed_official 25:ac5b0a371348 949 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
mbed_official 25:ac5b0a371348 950 uint32_t RESERVED7[8];
mbed_official 25:ac5b0a371348 951 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
mbed_official 25:ac5b0a371348 952 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
mbed_official 25:ac5b0a371348 953 } TPI_Type;
mbed_official 25:ac5b0a371348 954
mbed_official 25:ac5b0a371348 955 /* TPI Asynchronous Clock Prescaler Register Definitions */
mbed_official 25:ac5b0a371348 956 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
mbed_official 25:ac5b0a371348 957 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */
mbed_official 25:ac5b0a371348 958
mbed_official 25:ac5b0a371348 959 /* TPI Selected Pin Protocol Register Definitions */
mbed_official 25:ac5b0a371348 960 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
mbed_official 25:ac5b0a371348 961 #define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */
mbed_official 25:ac5b0a371348 962
mbed_official 25:ac5b0a371348 963 /* TPI Formatter and Flush Status Register Definitions */
mbed_official 25:ac5b0a371348 964 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
mbed_official 25:ac5b0a371348 965 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
mbed_official 25:ac5b0a371348 966
mbed_official 25:ac5b0a371348 967 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
mbed_official 25:ac5b0a371348 968 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
mbed_official 25:ac5b0a371348 969
mbed_official 25:ac5b0a371348 970 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
mbed_official 25:ac5b0a371348 971 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
mbed_official 25:ac5b0a371348 972
mbed_official 25:ac5b0a371348 973 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
mbed_official 25:ac5b0a371348 974 #define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */
mbed_official 25:ac5b0a371348 975
mbed_official 25:ac5b0a371348 976 /* TPI Formatter and Flush Control Register Definitions */
mbed_official 25:ac5b0a371348 977 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
mbed_official 25:ac5b0a371348 978 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
mbed_official 25:ac5b0a371348 979
mbed_official 25:ac5b0a371348 980 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
mbed_official 25:ac5b0a371348 981 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
mbed_official 25:ac5b0a371348 982
mbed_official 25:ac5b0a371348 983 /* TPI TRIGGER Register Definitions */
mbed_official 25:ac5b0a371348 984 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
mbed_official 25:ac5b0a371348 985 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */
mbed_official 25:ac5b0a371348 986
mbed_official 25:ac5b0a371348 987 /* TPI Integration ETM Data Register Definitions (FIFO0) */
mbed_official 25:ac5b0a371348 988 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
mbed_official 25:ac5b0a371348 989 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
mbed_official 25:ac5b0a371348 990
mbed_official 25:ac5b0a371348 991 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
mbed_official 25:ac5b0a371348 992 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
mbed_official 25:ac5b0a371348 993
mbed_official 25:ac5b0a371348 994 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
mbed_official 25:ac5b0a371348 995 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
mbed_official 25:ac5b0a371348 996
mbed_official 25:ac5b0a371348 997 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
mbed_official 25:ac5b0a371348 998 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
mbed_official 25:ac5b0a371348 999
mbed_official 25:ac5b0a371348 1000 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
mbed_official 25:ac5b0a371348 1001 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
mbed_official 25:ac5b0a371348 1002
mbed_official 25:ac5b0a371348 1003 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
mbed_official 25:ac5b0a371348 1004 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
mbed_official 25:ac5b0a371348 1005
mbed_official 25:ac5b0a371348 1006 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
mbed_official 25:ac5b0a371348 1007 #define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */
mbed_official 25:ac5b0a371348 1008
mbed_official 25:ac5b0a371348 1009 /* TPI ITATBCTR2 Register Definitions */
mbed_official 25:ac5b0a371348 1010 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
mbed_official 25:ac5b0a371348 1011 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */
mbed_official 25:ac5b0a371348 1012
mbed_official 25:ac5b0a371348 1013 /* TPI Integration ITM Data Register Definitions (FIFO1) */
mbed_official 25:ac5b0a371348 1014 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
mbed_official 25:ac5b0a371348 1015 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
mbed_official 25:ac5b0a371348 1016
mbed_official 25:ac5b0a371348 1017 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
mbed_official 25:ac5b0a371348 1018 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
mbed_official 25:ac5b0a371348 1019
mbed_official 25:ac5b0a371348 1020 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
mbed_official 25:ac5b0a371348 1021 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
mbed_official 25:ac5b0a371348 1022
mbed_official 25:ac5b0a371348 1023 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
mbed_official 25:ac5b0a371348 1024 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
mbed_official 25:ac5b0a371348 1025
mbed_official 25:ac5b0a371348 1026 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
mbed_official 25:ac5b0a371348 1027 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
mbed_official 25:ac5b0a371348 1028
mbed_official 25:ac5b0a371348 1029 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
mbed_official 25:ac5b0a371348 1030 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
mbed_official 25:ac5b0a371348 1031
mbed_official 25:ac5b0a371348 1032 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
mbed_official 25:ac5b0a371348 1033 #define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */
mbed_official 25:ac5b0a371348 1034
mbed_official 25:ac5b0a371348 1035 /* TPI ITATBCTR0 Register Definitions */
mbed_official 25:ac5b0a371348 1036 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
mbed_official 25:ac5b0a371348 1037 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */
mbed_official 25:ac5b0a371348 1038
mbed_official 25:ac5b0a371348 1039 /* TPI Integration Mode Control Register Definitions */
mbed_official 25:ac5b0a371348 1040 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
mbed_official 25:ac5b0a371348 1041 #define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */
mbed_official 25:ac5b0a371348 1042
mbed_official 25:ac5b0a371348 1043 /* TPI DEVID Register Definitions */
mbed_official 25:ac5b0a371348 1044 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
mbed_official 25:ac5b0a371348 1045 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
mbed_official 25:ac5b0a371348 1046
mbed_official 25:ac5b0a371348 1047 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
mbed_official 25:ac5b0a371348 1048 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
mbed_official 25:ac5b0a371348 1049
mbed_official 25:ac5b0a371348 1050 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
mbed_official 25:ac5b0a371348 1051 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
mbed_official 25:ac5b0a371348 1052
mbed_official 25:ac5b0a371348 1053 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
mbed_official 25:ac5b0a371348 1054 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
mbed_official 25:ac5b0a371348 1055
mbed_official 25:ac5b0a371348 1056 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
mbed_official 25:ac5b0a371348 1057 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
mbed_official 25:ac5b0a371348 1058
mbed_official 25:ac5b0a371348 1059 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
mbed_official 25:ac5b0a371348 1060 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */
mbed_official 25:ac5b0a371348 1061
mbed_official 25:ac5b0a371348 1062 /* TPI DEVTYPE Register Definitions */
mbed_official 25:ac5b0a371348 1063 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
mbed_official 25:ac5b0a371348 1064 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
mbed_official 25:ac5b0a371348 1065
mbed_official 25:ac5b0a371348 1066 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
mbed_official 25:ac5b0a371348 1067 #define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */
mbed_official 25:ac5b0a371348 1068
mbed_official 25:ac5b0a371348 1069 /*@}*/ /* end of group CMSIS_TPI */
mbed_official 25:ac5b0a371348 1070
mbed_official 25:ac5b0a371348 1071
mbed_official 25:ac5b0a371348 1072 #if (__MPU_PRESENT == 1)
mbed_official 25:ac5b0a371348 1073 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 1074 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
mbed_official 25:ac5b0a371348 1075 \brief Type definitions for the Memory Protection Unit (MPU)
mbed_official 25:ac5b0a371348 1076 @{
mbed_official 25:ac5b0a371348 1077 */
mbed_official 25:ac5b0a371348 1078
mbed_official 25:ac5b0a371348 1079 /** \brief Structure type to access the Memory Protection Unit (MPU).
mbed_official 25:ac5b0a371348 1080 */
mbed_official 25:ac5b0a371348 1081 typedef struct
mbed_official 25:ac5b0a371348 1082 {
mbed_official 25:ac5b0a371348 1083 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
mbed_official 25:ac5b0a371348 1084 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
mbed_official 25:ac5b0a371348 1085 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
mbed_official 25:ac5b0a371348 1086 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
mbed_official 25:ac5b0a371348 1087 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
mbed_official 25:ac5b0a371348 1088 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
mbed_official 25:ac5b0a371348 1089 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
mbed_official 25:ac5b0a371348 1090 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
mbed_official 25:ac5b0a371348 1091 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
mbed_official 25:ac5b0a371348 1092 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
mbed_official 25:ac5b0a371348 1093 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
mbed_official 25:ac5b0a371348 1094 } MPU_Type;
mbed_official 25:ac5b0a371348 1095
mbed_official 25:ac5b0a371348 1096 /* MPU Type Register */
mbed_official 25:ac5b0a371348 1097 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
mbed_official 25:ac5b0a371348 1098 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
mbed_official 25:ac5b0a371348 1099
mbed_official 25:ac5b0a371348 1100 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
mbed_official 25:ac5b0a371348 1101 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
mbed_official 25:ac5b0a371348 1102
mbed_official 25:ac5b0a371348 1103 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
mbed_official 25:ac5b0a371348 1104 #define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */
mbed_official 25:ac5b0a371348 1105
mbed_official 25:ac5b0a371348 1106 /* MPU Control Register */
mbed_official 25:ac5b0a371348 1107 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
mbed_official 25:ac5b0a371348 1108 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
mbed_official 25:ac5b0a371348 1109
mbed_official 25:ac5b0a371348 1110 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
mbed_official 25:ac5b0a371348 1111 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
mbed_official 25:ac5b0a371348 1112
mbed_official 25:ac5b0a371348 1113 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
mbed_official 25:ac5b0a371348 1114 #define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */
mbed_official 25:ac5b0a371348 1115
mbed_official 25:ac5b0a371348 1116 /* MPU Region Number Register */
mbed_official 25:ac5b0a371348 1117 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
mbed_official 25:ac5b0a371348 1118 #define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */
mbed_official 25:ac5b0a371348 1119
mbed_official 25:ac5b0a371348 1120 /* MPU Region Base Address Register */
mbed_official 25:ac5b0a371348 1121 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
mbed_official 25:ac5b0a371348 1122 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
mbed_official 25:ac5b0a371348 1123
mbed_official 25:ac5b0a371348 1124 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
mbed_official 25:ac5b0a371348 1125 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
mbed_official 25:ac5b0a371348 1126
mbed_official 25:ac5b0a371348 1127 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
mbed_official 25:ac5b0a371348 1128 #define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */
mbed_official 25:ac5b0a371348 1129
mbed_official 25:ac5b0a371348 1130 /* MPU Region Attribute and Size Register */
mbed_official 25:ac5b0a371348 1131 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
mbed_official 25:ac5b0a371348 1132 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
mbed_official 25:ac5b0a371348 1133
mbed_official 25:ac5b0a371348 1134 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
mbed_official 25:ac5b0a371348 1135 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
mbed_official 25:ac5b0a371348 1136
mbed_official 25:ac5b0a371348 1137 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
mbed_official 25:ac5b0a371348 1138 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
mbed_official 25:ac5b0a371348 1139
mbed_official 25:ac5b0a371348 1140 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
mbed_official 25:ac5b0a371348 1141 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
mbed_official 25:ac5b0a371348 1142
mbed_official 25:ac5b0a371348 1143 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
mbed_official 25:ac5b0a371348 1144 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
mbed_official 25:ac5b0a371348 1145
mbed_official 25:ac5b0a371348 1146 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
mbed_official 25:ac5b0a371348 1147 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
mbed_official 25:ac5b0a371348 1148
mbed_official 25:ac5b0a371348 1149 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
mbed_official 25:ac5b0a371348 1150 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
mbed_official 25:ac5b0a371348 1151
mbed_official 25:ac5b0a371348 1152 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
mbed_official 25:ac5b0a371348 1153 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
mbed_official 25:ac5b0a371348 1154
mbed_official 25:ac5b0a371348 1155 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
mbed_official 25:ac5b0a371348 1156 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
mbed_official 25:ac5b0a371348 1157
mbed_official 25:ac5b0a371348 1158 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
mbed_official 25:ac5b0a371348 1159 #define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */
mbed_official 25:ac5b0a371348 1160
mbed_official 25:ac5b0a371348 1161 /*@} end of group CMSIS_MPU */
mbed_official 25:ac5b0a371348 1162 #endif
mbed_official 25:ac5b0a371348 1163
mbed_official 25:ac5b0a371348 1164
mbed_official 25:ac5b0a371348 1165 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 1166 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
mbed_official 25:ac5b0a371348 1167 \brief Type definitions for the Core Debug Registers
mbed_official 25:ac5b0a371348 1168 @{
mbed_official 25:ac5b0a371348 1169 */
mbed_official 25:ac5b0a371348 1170
mbed_official 25:ac5b0a371348 1171 /** \brief Structure type to access the Core Debug Register (CoreDebug).
mbed_official 25:ac5b0a371348 1172 */
mbed_official 25:ac5b0a371348 1173 typedef struct
mbed_official 25:ac5b0a371348 1174 {
mbed_official 25:ac5b0a371348 1175 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
mbed_official 25:ac5b0a371348 1176 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
mbed_official 25:ac5b0a371348 1177 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
mbed_official 25:ac5b0a371348 1178 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
mbed_official 25:ac5b0a371348 1179 } CoreDebug_Type;
mbed_official 25:ac5b0a371348 1180
mbed_official 25:ac5b0a371348 1181 /* Debug Halting Control and Status Register */
mbed_official 25:ac5b0a371348 1182 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
mbed_official 25:ac5b0a371348 1183 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
mbed_official 25:ac5b0a371348 1184
mbed_official 25:ac5b0a371348 1185 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
mbed_official 25:ac5b0a371348 1186 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
mbed_official 25:ac5b0a371348 1187
mbed_official 25:ac5b0a371348 1188 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
mbed_official 25:ac5b0a371348 1189 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
mbed_official 25:ac5b0a371348 1190
mbed_official 25:ac5b0a371348 1191 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
mbed_official 25:ac5b0a371348 1192 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
mbed_official 25:ac5b0a371348 1193
mbed_official 25:ac5b0a371348 1194 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
mbed_official 25:ac5b0a371348 1195 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
mbed_official 25:ac5b0a371348 1196
mbed_official 25:ac5b0a371348 1197 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
mbed_official 25:ac5b0a371348 1198 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
mbed_official 25:ac5b0a371348 1199
mbed_official 25:ac5b0a371348 1200 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
mbed_official 25:ac5b0a371348 1201 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
mbed_official 25:ac5b0a371348 1202
mbed_official 25:ac5b0a371348 1203 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
mbed_official 25:ac5b0a371348 1204 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
mbed_official 25:ac5b0a371348 1205
mbed_official 25:ac5b0a371348 1206 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
mbed_official 25:ac5b0a371348 1207 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
mbed_official 25:ac5b0a371348 1208
mbed_official 25:ac5b0a371348 1209 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
mbed_official 25:ac5b0a371348 1210 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
mbed_official 25:ac5b0a371348 1211
mbed_official 25:ac5b0a371348 1212 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
mbed_official 25:ac5b0a371348 1213 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
mbed_official 25:ac5b0a371348 1214
mbed_official 25:ac5b0a371348 1215 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
mbed_official 25:ac5b0a371348 1216 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
mbed_official 25:ac5b0a371348 1217
mbed_official 25:ac5b0a371348 1218 /* Debug Core Register Selector Register */
mbed_official 25:ac5b0a371348 1219 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
mbed_official 25:ac5b0a371348 1220 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
mbed_official 25:ac5b0a371348 1221
mbed_official 25:ac5b0a371348 1222 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
mbed_official 25:ac5b0a371348 1223 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */
mbed_official 25:ac5b0a371348 1224
mbed_official 25:ac5b0a371348 1225 /* Debug Exception and Monitor Control Register */
mbed_official 25:ac5b0a371348 1226 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
mbed_official 25:ac5b0a371348 1227 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
mbed_official 25:ac5b0a371348 1228
mbed_official 25:ac5b0a371348 1229 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
mbed_official 25:ac5b0a371348 1230 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
mbed_official 25:ac5b0a371348 1231
mbed_official 25:ac5b0a371348 1232 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
mbed_official 25:ac5b0a371348 1233 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
mbed_official 25:ac5b0a371348 1234
mbed_official 25:ac5b0a371348 1235 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
mbed_official 25:ac5b0a371348 1236 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
mbed_official 25:ac5b0a371348 1237
mbed_official 25:ac5b0a371348 1238 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
mbed_official 25:ac5b0a371348 1239 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
mbed_official 25:ac5b0a371348 1240
mbed_official 25:ac5b0a371348 1241 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
mbed_official 25:ac5b0a371348 1242 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
mbed_official 25:ac5b0a371348 1243
mbed_official 25:ac5b0a371348 1244 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
mbed_official 25:ac5b0a371348 1245 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
mbed_official 25:ac5b0a371348 1246
mbed_official 25:ac5b0a371348 1247 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
mbed_official 25:ac5b0a371348 1248 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
mbed_official 25:ac5b0a371348 1249
mbed_official 25:ac5b0a371348 1250 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
mbed_official 25:ac5b0a371348 1251 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
mbed_official 25:ac5b0a371348 1252
mbed_official 25:ac5b0a371348 1253 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
mbed_official 25:ac5b0a371348 1254 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
mbed_official 25:ac5b0a371348 1255
mbed_official 25:ac5b0a371348 1256 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
mbed_official 25:ac5b0a371348 1257 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
mbed_official 25:ac5b0a371348 1258
mbed_official 25:ac5b0a371348 1259 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
mbed_official 25:ac5b0a371348 1260 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
mbed_official 25:ac5b0a371348 1261
mbed_official 25:ac5b0a371348 1262 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
mbed_official 25:ac5b0a371348 1263 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
mbed_official 25:ac5b0a371348 1264
mbed_official 25:ac5b0a371348 1265 /*@} end of group CMSIS_CoreDebug */
mbed_official 25:ac5b0a371348 1266
mbed_official 25:ac5b0a371348 1267
mbed_official 25:ac5b0a371348 1268 /** \ingroup CMSIS_core_register
mbed_official 25:ac5b0a371348 1269 \defgroup CMSIS_core_base Core Definitions
mbed_official 25:ac5b0a371348 1270 \brief Definitions for base addresses, unions, and structures.
mbed_official 25:ac5b0a371348 1271 @{
mbed_official 25:ac5b0a371348 1272 */
mbed_official 25:ac5b0a371348 1273
mbed_official 25:ac5b0a371348 1274 /* Memory mapping of Cortex-M3 Hardware */
mbed_official 25:ac5b0a371348 1275 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
mbed_official 25:ac5b0a371348 1276 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
mbed_official 25:ac5b0a371348 1277 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
mbed_official 25:ac5b0a371348 1278 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
mbed_official 25:ac5b0a371348 1279 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
mbed_official 25:ac5b0a371348 1280 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
mbed_official 25:ac5b0a371348 1281 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
mbed_official 25:ac5b0a371348 1282 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
mbed_official 25:ac5b0a371348 1283
mbed_official 25:ac5b0a371348 1284 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
mbed_official 25:ac5b0a371348 1285 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
mbed_official 25:ac5b0a371348 1286 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
mbed_official 25:ac5b0a371348 1287 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
mbed_official 25:ac5b0a371348 1288 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
mbed_official 25:ac5b0a371348 1289 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
mbed_official 25:ac5b0a371348 1290 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
mbed_official 25:ac5b0a371348 1291 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
mbed_official 25:ac5b0a371348 1292
mbed_official 25:ac5b0a371348 1293 #if (__MPU_PRESENT == 1)
mbed_official 25:ac5b0a371348 1294 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
mbed_official 25:ac5b0a371348 1295 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
mbed_official 25:ac5b0a371348 1296 #endif
mbed_official 25:ac5b0a371348 1297
mbed_official 25:ac5b0a371348 1298 /*@} */
mbed_official 25:ac5b0a371348 1299
mbed_official 25:ac5b0a371348 1300
mbed_official 25:ac5b0a371348 1301
mbed_official 25:ac5b0a371348 1302 /*******************************************************************************
mbed_official 25:ac5b0a371348 1303 * Hardware Abstraction Layer
mbed_official 25:ac5b0a371348 1304 Core Function Interface contains:
mbed_official 25:ac5b0a371348 1305 - Core NVIC Functions
mbed_official 25:ac5b0a371348 1306 - Core SysTick Functions
mbed_official 25:ac5b0a371348 1307 - Core Debug Functions
mbed_official 25:ac5b0a371348 1308 - Core Register Access Functions
mbed_official 25:ac5b0a371348 1309 ******************************************************************************/
mbed_official 25:ac5b0a371348 1310 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
mbed_official 25:ac5b0a371348 1311 */
mbed_official 25:ac5b0a371348 1312
mbed_official 25:ac5b0a371348 1313
mbed_official 25:ac5b0a371348 1314
mbed_official 25:ac5b0a371348 1315 /* ########################## NVIC functions #################################### */
mbed_official 25:ac5b0a371348 1316 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 25:ac5b0a371348 1317 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
mbed_official 25:ac5b0a371348 1318 \brief Functions that manage interrupts and exceptions via the NVIC.
mbed_official 25:ac5b0a371348 1319 @{
mbed_official 25:ac5b0a371348 1320 */
mbed_official 25:ac5b0a371348 1321
mbed_official 25:ac5b0a371348 1322 /** \brief Set Priority Grouping
mbed_official 25:ac5b0a371348 1323
mbed_official 25:ac5b0a371348 1324 The function sets the priority grouping field using the required unlock sequence.
mbed_official 25:ac5b0a371348 1325 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
mbed_official 25:ac5b0a371348 1326 Only values from 0..7 are used.
mbed_official 25:ac5b0a371348 1327 In case of a conflict between priority grouping and available
mbed_official 25:ac5b0a371348 1328 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mbed_official 25:ac5b0a371348 1329
mbed_official 25:ac5b0a371348 1330 \param [in] PriorityGroup Priority grouping field.
mbed_official 25:ac5b0a371348 1331 */
mbed_official 25:ac5b0a371348 1332 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
mbed_official 25:ac5b0a371348 1333 {
mbed_official 25:ac5b0a371348 1334 uint32_t reg_value;
mbed_official 25:ac5b0a371348 1335 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 25:ac5b0a371348 1336
mbed_official 25:ac5b0a371348 1337 reg_value = SCB->AIRCR; /* read old register configuration */
mbed_official 25:ac5b0a371348 1338 reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */
mbed_official 25:ac5b0a371348 1339 reg_value = (reg_value |
mbed_official 25:ac5b0a371348 1340 ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 25:ac5b0a371348 1341 (PriorityGroupTmp << 8) ); /* Insert write key and priorty group */
mbed_official 25:ac5b0a371348 1342 SCB->AIRCR = reg_value;
mbed_official 25:ac5b0a371348 1343 }
mbed_official 25:ac5b0a371348 1344
mbed_official 25:ac5b0a371348 1345
mbed_official 25:ac5b0a371348 1346 /** \brief Get Priority Grouping
mbed_official 25:ac5b0a371348 1347
mbed_official 25:ac5b0a371348 1348 The function reads the priority grouping field from the NVIC Interrupt Controller.
mbed_official 25:ac5b0a371348 1349
mbed_official 25:ac5b0a371348 1350 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
mbed_official 25:ac5b0a371348 1351 */
mbed_official 25:ac5b0a371348 1352 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
mbed_official 25:ac5b0a371348 1353 {
mbed_official 25:ac5b0a371348 1354 return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos));
mbed_official 25:ac5b0a371348 1355 }
mbed_official 25:ac5b0a371348 1356
mbed_official 25:ac5b0a371348 1357
mbed_official 25:ac5b0a371348 1358 /** \brief Enable External Interrupt
mbed_official 25:ac5b0a371348 1359
mbed_official 25:ac5b0a371348 1360 The function enables a device-specific interrupt in the NVIC interrupt controller.
mbed_official 25:ac5b0a371348 1361
mbed_official 25:ac5b0a371348 1362 \param [in] IRQn External interrupt number. Value cannot be negative.
mbed_official 25:ac5b0a371348 1363 */
mbed_official 25:ac5b0a371348 1364 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 1365 {
mbed_official 25:ac5b0a371348 1366 NVIC->ISER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 25:ac5b0a371348 1367 }
mbed_official 25:ac5b0a371348 1368
mbed_official 25:ac5b0a371348 1369
mbed_official 25:ac5b0a371348 1370 /** \brief Disable External Interrupt
mbed_official 25:ac5b0a371348 1371
mbed_official 25:ac5b0a371348 1372 The function disables a device-specific interrupt in the NVIC interrupt controller.
mbed_official 25:ac5b0a371348 1373
mbed_official 25:ac5b0a371348 1374 \param [in] IRQn External interrupt number. Value cannot be negative.
mbed_official 25:ac5b0a371348 1375 */
mbed_official 25:ac5b0a371348 1376 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 1377 {
mbed_official 25:ac5b0a371348 1378 NVIC->ICER[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
<> 152:9a67f0b066fc 1379 __DSB();
<> 152:9a67f0b066fc 1380 __ISB();
mbed_official 25:ac5b0a371348 1381 }
mbed_official 25:ac5b0a371348 1382
mbed_official 25:ac5b0a371348 1383
mbed_official 25:ac5b0a371348 1384 /** \brief Get Pending Interrupt
mbed_official 25:ac5b0a371348 1385
mbed_official 25:ac5b0a371348 1386 The function reads the pending register in the NVIC and returns the pending bit
mbed_official 25:ac5b0a371348 1387 for the specified interrupt.
mbed_official 25:ac5b0a371348 1388
mbed_official 25:ac5b0a371348 1389 \param [in] IRQn Interrupt number.
mbed_official 25:ac5b0a371348 1390
mbed_official 25:ac5b0a371348 1391 \return 0 Interrupt status is not pending.
mbed_official 25:ac5b0a371348 1392 \return 1 Interrupt status is pending.
mbed_official 25:ac5b0a371348 1393 */
mbed_official 25:ac5b0a371348 1394 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 1395 {
mbed_official 25:ac5b0a371348 1396 return((uint32_t)(((NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 25:ac5b0a371348 1397 }
mbed_official 25:ac5b0a371348 1398
mbed_official 25:ac5b0a371348 1399
mbed_official 25:ac5b0a371348 1400 /** \brief Set Pending Interrupt
mbed_official 25:ac5b0a371348 1401
mbed_official 25:ac5b0a371348 1402 The function sets the pending bit of an external interrupt.
mbed_official 25:ac5b0a371348 1403
mbed_official 25:ac5b0a371348 1404 \param [in] IRQn Interrupt number. Value cannot be negative.
mbed_official 25:ac5b0a371348 1405 */
mbed_official 25:ac5b0a371348 1406 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 1407 {
mbed_official 25:ac5b0a371348 1408 NVIC->ISPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 25:ac5b0a371348 1409 }
mbed_official 25:ac5b0a371348 1410
mbed_official 25:ac5b0a371348 1411
mbed_official 25:ac5b0a371348 1412 /** \brief Clear Pending Interrupt
mbed_official 25:ac5b0a371348 1413
mbed_official 25:ac5b0a371348 1414 The function clears the pending bit of an external interrupt.
mbed_official 25:ac5b0a371348 1415
mbed_official 25:ac5b0a371348 1416 \param [in] IRQn External interrupt number. Value cannot be negative.
mbed_official 25:ac5b0a371348 1417 */
mbed_official 25:ac5b0a371348 1418 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 1419 {
mbed_official 25:ac5b0a371348 1420 NVIC->ICPR[(((uint32_t)(int32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL));
mbed_official 25:ac5b0a371348 1421 }
mbed_official 25:ac5b0a371348 1422
mbed_official 25:ac5b0a371348 1423
mbed_official 25:ac5b0a371348 1424 /** \brief Get Active Interrupt
mbed_official 25:ac5b0a371348 1425
mbed_official 25:ac5b0a371348 1426 The function reads the active register in NVIC and returns the active bit.
mbed_official 25:ac5b0a371348 1427
mbed_official 25:ac5b0a371348 1428 \param [in] IRQn Interrupt number.
mbed_official 25:ac5b0a371348 1429
mbed_official 25:ac5b0a371348 1430 \return 0 Interrupt status is not active.
mbed_official 25:ac5b0a371348 1431 \return 1 Interrupt status is active.
mbed_official 25:ac5b0a371348 1432 */
mbed_official 25:ac5b0a371348 1433 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 1434 {
mbed_official 25:ac5b0a371348 1435 return((uint32_t)(((NVIC->IABR[(((uint32_t)(int32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)(int32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
mbed_official 25:ac5b0a371348 1436 }
mbed_official 25:ac5b0a371348 1437
mbed_official 25:ac5b0a371348 1438
mbed_official 25:ac5b0a371348 1439 /** \brief Set Interrupt Priority
mbed_official 25:ac5b0a371348 1440
mbed_official 25:ac5b0a371348 1441 The function sets the priority of an interrupt.
mbed_official 25:ac5b0a371348 1442
mbed_official 25:ac5b0a371348 1443 \note The priority cannot be set for every core interrupt.
mbed_official 25:ac5b0a371348 1444
mbed_official 25:ac5b0a371348 1445 \param [in] IRQn Interrupt number.
mbed_official 25:ac5b0a371348 1446 \param [in] priority Priority to set.
mbed_official 25:ac5b0a371348 1447 */
mbed_official 25:ac5b0a371348 1448 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
mbed_official 25:ac5b0a371348 1449 {
mbed_official 25:ac5b0a371348 1450 if((int32_t)IRQn < 0) {
mbed_official 25:ac5b0a371348 1451 SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 25:ac5b0a371348 1452 }
mbed_official 25:ac5b0a371348 1453 else {
mbed_official 25:ac5b0a371348 1454 NVIC->IP[((uint32_t)(int32_t)IRQn)] = (uint8_t)((priority << (8 - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL);
mbed_official 25:ac5b0a371348 1455 }
mbed_official 25:ac5b0a371348 1456 }
mbed_official 25:ac5b0a371348 1457
mbed_official 25:ac5b0a371348 1458
mbed_official 25:ac5b0a371348 1459 /** \brief Get Interrupt Priority
mbed_official 25:ac5b0a371348 1460
mbed_official 25:ac5b0a371348 1461 The function reads the priority of an interrupt. The interrupt
mbed_official 25:ac5b0a371348 1462 number can be positive to specify an external (device specific)
mbed_official 25:ac5b0a371348 1463 interrupt, or negative to specify an internal (core) interrupt.
mbed_official 25:ac5b0a371348 1464
mbed_official 25:ac5b0a371348 1465
mbed_official 25:ac5b0a371348 1466 \param [in] IRQn Interrupt number.
mbed_official 25:ac5b0a371348 1467 \return Interrupt Priority. Value is aligned automatically to the implemented
mbed_official 25:ac5b0a371348 1468 priority bits of the microcontroller.
mbed_official 25:ac5b0a371348 1469 */
mbed_official 25:ac5b0a371348 1470 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
mbed_official 25:ac5b0a371348 1471 {
mbed_official 25:ac5b0a371348 1472
mbed_official 25:ac5b0a371348 1473 if((int32_t)IRQn < 0) {
mbed_official 25:ac5b0a371348 1474 return(((uint32_t)SCB->SHP[(((uint32_t)(int32_t)IRQn) & 0xFUL)-4UL] >> (8 - __NVIC_PRIO_BITS)));
mbed_official 25:ac5b0a371348 1475 }
mbed_official 25:ac5b0a371348 1476 else {
mbed_official 25:ac5b0a371348 1477 return(((uint32_t)NVIC->IP[((uint32_t)(int32_t)IRQn)] >> (8 - __NVIC_PRIO_BITS)));
mbed_official 25:ac5b0a371348 1478 }
mbed_official 25:ac5b0a371348 1479 }
mbed_official 25:ac5b0a371348 1480
mbed_official 25:ac5b0a371348 1481
mbed_official 25:ac5b0a371348 1482 /** \brief Encode Priority
mbed_official 25:ac5b0a371348 1483
mbed_official 25:ac5b0a371348 1484 The function encodes the priority for an interrupt with the given priority group,
mbed_official 25:ac5b0a371348 1485 preemptive priority value, and subpriority value.
mbed_official 25:ac5b0a371348 1486 In case of a conflict between priority grouping and available
mbed_official 25:ac5b0a371348 1487 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
mbed_official 25:ac5b0a371348 1488
mbed_official 25:ac5b0a371348 1489 \param [in] PriorityGroup Used priority group.
mbed_official 25:ac5b0a371348 1490 \param [in] PreemptPriority Preemptive priority value (starting from 0).
mbed_official 25:ac5b0a371348 1491 \param [in] SubPriority Subpriority value (starting from 0).
mbed_official 25:ac5b0a371348 1492 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
mbed_official 25:ac5b0a371348 1493 */
mbed_official 25:ac5b0a371348 1494 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
mbed_official 25:ac5b0a371348 1495 {
mbed_official 25:ac5b0a371348 1496 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 25:ac5b0a371348 1497 uint32_t PreemptPriorityBits;
mbed_official 25:ac5b0a371348 1498 uint32_t SubPriorityBits;
mbed_official 25:ac5b0a371348 1499
mbed_official 25:ac5b0a371348 1500 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official 25:ac5b0a371348 1501 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official 25:ac5b0a371348 1502
mbed_official 25:ac5b0a371348 1503 return (
mbed_official 25:ac5b0a371348 1504 ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) |
mbed_official 25:ac5b0a371348 1505 ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL)))
mbed_official 25:ac5b0a371348 1506 );
mbed_official 25:ac5b0a371348 1507 }
mbed_official 25:ac5b0a371348 1508
mbed_official 25:ac5b0a371348 1509
mbed_official 25:ac5b0a371348 1510 /** \brief Decode Priority
mbed_official 25:ac5b0a371348 1511
mbed_official 25:ac5b0a371348 1512 The function decodes an interrupt priority value with a given priority group to
mbed_official 25:ac5b0a371348 1513 preemptive priority value and subpriority value.
mbed_official 25:ac5b0a371348 1514 In case of a conflict between priority grouping and available
mbed_official 25:ac5b0a371348 1515 priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
mbed_official 25:ac5b0a371348 1516
mbed_official 25:ac5b0a371348 1517 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
mbed_official 25:ac5b0a371348 1518 \param [in] PriorityGroup Used priority group.
mbed_official 25:ac5b0a371348 1519 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
mbed_official 25:ac5b0a371348 1520 \param [out] pSubPriority Subpriority value (starting from 0).
mbed_official 25:ac5b0a371348 1521 */
mbed_official 25:ac5b0a371348 1522 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
mbed_official 25:ac5b0a371348 1523 {
mbed_official 25:ac5b0a371348 1524 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */
mbed_official 25:ac5b0a371348 1525 uint32_t PreemptPriorityBits;
mbed_official 25:ac5b0a371348 1526 uint32_t SubPriorityBits;
mbed_official 25:ac5b0a371348 1527
mbed_official 25:ac5b0a371348 1528 PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp);
mbed_official 25:ac5b0a371348 1529 SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS));
mbed_official 25:ac5b0a371348 1530
mbed_official 25:ac5b0a371348 1531 *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL);
mbed_official 25:ac5b0a371348 1532 *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL);
mbed_official 25:ac5b0a371348 1533 }
mbed_official 25:ac5b0a371348 1534
mbed_official 25:ac5b0a371348 1535
mbed_official 25:ac5b0a371348 1536 /** \brief System Reset
mbed_official 25:ac5b0a371348 1537
mbed_official 25:ac5b0a371348 1538 The function initiates a system reset request to reset the MCU.
mbed_official 25:ac5b0a371348 1539 */
mbed_official 25:ac5b0a371348 1540 __STATIC_INLINE void NVIC_SystemReset(void)
mbed_official 25:ac5b0a371348 1541 {
mbed_official 25:ac5b0a371348 1542 __DSB(); /* Ensure all outstanding memory accesses included
mbed_official 25:ac5b0a371348 1543 buffered write are completed before reset */
mbed_official 25:ac5b0a371348 1544 SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) |
mbed_official 25:ac5b0a371348 1545 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
mbed_official 25:ac5b0a371348 1546 SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */
mbed_official 25:ac5b0a371348 1547 __DSB(); /* Ensure completion of memory access */
mbed_official 25:ac5b0a371348 1548 while(1) { __NOP(); } /* wait until reset */
mbed_official 25:ac5b0a371348 1549 }
mbed_official 25:ac5b0a371348 1550
mbed_official 25:ac5b0a371348 1551 /*@} end of CMSIS_Core_NVICFunctions */
mbed_official 25:ac5b0a371348 1552
mbed_official 25:ac5b0a371348 1553
mbed_official 25:ac5b0a371348 1554
mbed_official 25:ac5b0a371348 1555 /* ################################## SysTick function ############################################ */
mbed_official 25:ac5b0a371348 1556 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 25:ac5b0a371348 1557 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
mbed_official 25:ac5b0a371348 1558 \brief Functions that configure the System.
mbed_official 25:ac5b0a371348 1559 @{
mbed_official 25:ac5b0a371348 1560 */
mbed_official 25:ac5b0a371348 1561
mbed_official 25:ac5b0a371348 1562 #if (__Vendor_SysTickConfig == 0)
mbed_official 25:ac5b0a371348 1563
mbed_official 25:ac5b0a371348 1564 /** \brief System Tick Configuration
mbed_official 25:ac5b0a371348 1565
mbed_official 25:ac5b0a371348 1566 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
mbed_official 25:ac5b0a371348 1567 Counter is in free running mode to generate periodic interrupts.
mbed_official 25:ac5b0a371348 1568
mbed_official 25:ac5b0a371348 1569 \param [in] ticks Number of ticks between two interrupts.
mbed_official 25:ac5b0a371348 1570
mbed_official 25:ac5b0a371348 1571 \return 0 Function succeeded.
mbed_official 25:ac5b0a371348 1572 \return 1 Function failed.
mbed_official 25:ac5b0a371348 1573
mbed_official 25:ac5b0a371348 1574 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
mbed_official 25:ac5b0a371348 1575 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
mbed_official 25:ac5b0a371348 1576 must contain a vendor-specific implementation of this function.
mbed_official 25:ac5b0a371348 1577
mbed_official 25:ac5b0a371348 1578 */
mbed_official 25:ac5b0a371348 1579 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
mbed_official 25:ac5b0a371348 1580 {
mbed_official 25:ac5b0a371348 1581 if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) { return (1UL); } /* Reload value impossible */
mbed_official 25:ac5b0a371348 1582
mbed_official 25:ac5b0a371348 1583 SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
mbed_official 25:ac5b0a371348 1584 NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
mbed_official 25:ac5b0a371348 1585 SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
mbed_official 25:ac5b0a371348 1586 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
mbed_official 25:ac5b0a371348 1587 SysTick_CTRL_TICKINT_Msk |
mbed_official 25:ac5b0a371348 1588 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
mbed_official 25:ac5b0a371348 1589 return (0UL); /* Function successful */
mbed_official 25:ac5b0a371348 1590 }
mbed_official 25:ac5b0a371348 1591
mbed_official 25:ac5b0a371348 1592 #endif
mbed_official 25:ac5b0a371348 1593
mbed_official 25:ac5b0a371348 1594 /*@} end of CMSIS_Core_SysTickFunctions */
mbed_official 25:ac5b0a371348 1595
mbed_official 25:ac5b0a371348 1596
mbed_official 25:ac5b0a371348 1597
mbed_official 25:ac5b0a371348 1598 /* ##################################### Debug In/Output function ########################################### */
mbed_official 25:ac5b0a371348 1599 /** \ingroup CMSIS_Core_FunctionInterface
mbed_official 25:ac5b0a371348 1600 \defgroup CMSIS_core_DebugFunctions ITM Functions
mbed_official 25:ac5b0a371348 1601 \brief Functions that access the ITM debug interface.
mbed_official 25:ac5b0a371348 1602 @{
mbed_official 25:ac5b0a371348 1603 */
mbed_official 25:ac5b0a371348 1604
mbed_official 25:ac5b0a371348 1605 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
mbed_official 25:ac5b0a371348 1606 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
mbed_official 25:ac5b0a371348 1607
mbed_official 25:ac5b0a371348 1608
mbed_official 25:ac5b0a371348 1609 /** \brief ITM Send Character
mbed_official 25:ac5b0a371348 1610
mbed_official 25:ac5b0a371348 1611 The function transmits a character via the ITM channel 0, and
mbed_official 25:ac5b0a371348 1612 \li Just returns when no debugger is connected that has booked the output.
mbed_official 25:ac5b0a371348 1613 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
mbed_official 25:ac5b0a371348 1614
mbed_official 25:ac5b0a371348 1615 \param [in] ch Character to transmit.
mbed_official 25:ac5b0a371348 1616
mbed_official 25:ac5b0a371348 1617 \returns Character to transmit.
mbed_official 25:ac5b0a371348 1618 */
mbed_official 25:ac5b0a371348 1619 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
mbed_official 25:ac5b0a371348 1620 {
mbed_official 25:ac5b0a371348 1621 if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */
mbed_official 25:ac5b0a371348 1622 ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */
mbed_official 25:ac5b0a371348 1623 {
mbed_official 25:ac5b0a371348 1624 while (ITM->PORT[0].u32 == 0UL) { __NOP(); }
mbed_official 25:ac5b0a371348 1625 ITM->PORT[0].u8 = (uint8_t)ch;
mbed_official 25:ac5b0a371348 1626 }
mbed_official 25:ac5b0a371348 1627 return (ch);
mbed_official 25:ac5b0a371348 1628 }
mbed_official 25:ac5b0a371348 1629
mbed_official 25:ac5b0a371348 1630
mbed_official 25:ac5b0a371348 1631 /** \brief ITM Receive Character
mbed_official 25:ac5b0a371348 1632
mbed_official 25:ac5b0a371348 1633 The function inputs a character via the external variable \ref ITM_RxBuffer.
mbed_official 25:ac5b0a371348 1634
mbed_official 25:ac5b0a371348 1635 \return Received character.
mbed_official 25:ac5b0a371348 1636 \return -1 No character pending.
mbed_official 25:ac5b0a371348 1637 */
mbed_official 25:ac5b0a371348 1638 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
mbed_official 25:ac5b0a371348 1639 int32_t ch = -1; /* no character available */
mbed_official 25:ac5b0a371348 1640
mbed_official 25:ac5b0a371348 1641 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
mbed_official 25:ac5b0a371348 1642 ch = ITM_RxBuffer;
mbed_official 25:ac5b0a371348 1643 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
mbed_official 25:ac5b0a371348 1644 }
mbed_official 25:ac5b0a371348 1645
mbed_official 25:ac5b0a371348 1646 return (ch);
mbed_official 25:ac5b0a371348 1647 }
mbed_official 25:ac5b0a371348 1648
mbed_official 25:ac5b0a371348 1649
mbed_official 25:ac5b0a371348 1650 /** \brief ITM Check Character
mbed_official 25:ac5b0a371348 1651
mbed_official 25:ac5b0a371348 1652 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
mbed_official 25:ac5b0a371348 1653
mbed_official 25:ac5b0a371348 1654 \return 0 No character available.
mbed_official 25:ac5b0a371348 1655 \return 1 Character available.
mbed_official 25:ac5b0a371348 1656 */
mbed_official 25:ac5b0a371348 1657 __STATIC_INLINE int32_t ITM_CheckChar (void) {
mbed_official 25:ac5b0a371348 1658
mbed_official 25:ac5b0a371348 1659 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
mbed_official 25:ac5b0a371348 1660 return (0); /* no character available */
mbed_official 25:ac5b0a371348 1661 } else {
mbed_official 25:ac5b0a371348 1662 return (1); /* character available */
mbed_official 25:ac5b0a371348 1663 }
mbed_official 25:ac5b0a371348 1664 }
mbed_official 25:ac5b0a371348 1665
mbed_official 25:ac5b0a371348 1666 /*@} end of CMSIS_core_DebugFunctions */
mbed_official 25:ac5b0a371348 1667
mbed_official 25:ac5b0a371348 1668
mbed_official 25:ac5b0a371348 1669
mbed_official 25:ac5b0a371348 1670
mbed_official 25:ac5b0a371348 1671 #ifdef __cplusplus
mbed_official 25:ac5b0a371348 1672 }
mbed_official 25:ac5b0a371348 1673 #endif
mbed_official 25:ac5b0a371348 1674
mbed_official 25:ac5b0a371348 1675 #endif /* __CORE_SC300_H_DEPENDANT */
mbed_official 25:ac5b0a371348 1676
mbed_official 25:ac5b0a371348 1677 #endif /* __CMSIS_GENERIC */