Diff: targets/TARGET_WIZNET/TARGET_W7500x/spi_api.c

Revision:

149:156823d33999

Parent:

144:ef7eb2e8f9f7

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_WIZNET/TARGET_W7500x/spi_api.c	Fri Oct 28 11:17:30 2016 +0100
@@ -0,0 +1,202 @@
+/* mbed Microcontroller Library 
+ *******************************************************************************
+ * Copyright (c) 2015 WIZnet Co.,Ltd. All rights reserved.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of ARM Limited nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+ 
+#include "mbed_assert.h"
+#include <math.h>
+
+#include "spi_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+static inline int ssp_disable(spi_t *obj);
+static inline int ssp_enable(spi_t *obj);
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel) {
+    // determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+    obj->spi = (SSP_TypeDef*)pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT((int)obj->spi != NC);
+    
+    // enable power and clocking
+    switch ((int)obj->spi) {
+        case SPI_0: CRG->SSPCLK_SSR   = CRG_SSPCLK_SSR_MCLK; break; //PLL output clock
+        case SPI_1: CRG->SSPCLK_SSR   = CRG_SSPCLK_SSR_MCLK; break;
+    }
+    
+    // set default format and frequency
+    if (ssel == NC) {
+        spi_format(obj, 8, 0, 0);  // 8 bits, mode 0, master
+    } else {
+        spi_format(obj, 8, 0, 1);  // 8 bits, mode 0, slave
+    }
+    spi_frequency(obj, 1000000);
+    
+    // enable the ssp channel
+    ssp_enable(obj);
+
+    // pin out the spi pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    }
+}
+
+void spi_free(spi_t *obj) {}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave) {
+    ssp_disable(obj);
+    MBED_ASSERT(((bits >= 4) && (bits <= 16)) && (mode >= 0 && mode <= 3));
+    
+    int polarity = (mode & 0x2) ? 1 : 0;
+    int phase = (mode & 0x1) ? 1 : 0;
+    
+    // set it up
+    int DSS = bits - 1;            // DSS (data select size)
+    int SPO = (polarity) ? 1 : 0;  // SPO - clock out polarity
+    int SPH = (phase) ? 1 : 0;     // SPH - clock out phase
+    
+    int FRF = 0;                   // FRF (frame format) = SPI
+    uint32_t tmp = obj->spi->CR0;
+    tmp &= ~(0xFFFF);
+    tmp |= DSS << 0
+        | FRF << 4
+        | SPO << 6
+        | SPH << 7;
+    obj->spi->CR0 = tmp;
+    
+    tmp = obj->spi->CR1;
+    tmp &= ~(0xD);
+    tmp |= 0 << 0                   // LBM - loop back mode - off
+        | ((slave) ? 1 : 0) << 2   // MS - master slave mode, 1 = slave
+        | 0 << 3;                  // SOD - slave output disable - na
+    obj->spi->CR1 = tmp;
+    
+    ssp_enable(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz) {
+    ssp_disable(obj);
+    
+    // setup the spi clock diveder to /1
+    switch ((int)obj->spi) {
+        case SPI_0:
+            CRG->SSPCLK_PVSR  = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass) 
+            break;
+        case SPI_1:
+            CRG->SSPCLK_PVSR  = CRG_SSPCLK_PVSR_DIV1; //1/1 (bypass)
+            break;
+    }
+    
+    uint32_t HCLK = SystemCoreClock; 
+    
+    int prescaler;
+    
+    for (prescaler = 2; prescaler <= 254; prescaler += 2) {
+        int prescale_hz = HCLK / prescaler;
+        
+        // calculate the divider
+        int divider = floor(((float)prescale_hz / (float)hz) + 0.5f);
+        
+        // check we can support the divider
+        if (divider < 256) {
+            // prescaler
+            obj->spi->CPSR = prescaler;
+            
+            // divider
+            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 |= (divider - 1) << 8;
+            ssp_enable(obj);
+            return;
+        }
+    }
+    error("Couldn't setup requested SPI frequency");
+}
+
+static inline int ssp_disable(spi_t *obj) {
+    return obj->spi->CR1 &= ~(1 << 1);
+}
+
+static inline int ssp_enable(spi_t *obj) {
+    return obj->spi->CR1 |= (1 << 1);
+}
+
+static inline int ssp_readable(spi_t *obj) {
+    return obj->spi->SR & (1 << 2);
+}
+
+static inline int ssp_writeable(spi_t *obj) {
+    return obj->spi->SR & (1 << 1);
+}
+
+static inline void ssp_write(spi_t *obj, int value) {
+    while (!ssp_writeable(obj));
+    obj->spi->DR = value;
+}
+
+static inline int ssp_read(spi_t *obj) {
+    while (!ssp_readable(obj));
+    return obj->spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj) {
+    return (obj->spi->SR & (1 << 4)) ? (1) : (0);
+}
+
+int spi_master_write(spi_t *obj, int value) {
+    ssp_write(obj, value);
+    return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj) {
+    return (ssp_readable(obj) && !ssp_busy(obj)) ? (1) : (0);
+}
+
+int spi_slave_read(spi_t *obj) {
+    return obj->spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value) {
+    while (ssp_writeable(obj) == 0) ;
+    obj->spi->DR = value;
+}
+
+int spi_busy(spi_t *obj) {
+    return ssp_busy(obj);
+}
+